1 /******************************************************************************
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
51 status &= TX_STATUS_MSK;
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
121 priv->_agn.reply_tx_stats.unknown++;
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
128 status &= AGG_TX_STATUS_MSK;
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
168 priv->_agn.reply_agg_tx_stats.unknown++;
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwl_rxon_context *ctx,
176 struct iwlagn_tx_resp *tx_resp,
177 int txq_id, bool is_agg)
179 u16 status = le16_to_cpu(tx_resp->status.status);
181 info->status.rates[0].count = tx_resp->failure_frame + 1;
183 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
184 info->flags |= iwl_tx_status_to_mac80211(status);
185 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
187 if (!iwl_is_tx_success(status))
188 iwlagn_count_tx_err_status(priv, status);
190 if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
191 iwl_is_associated_ctx(ctx) && ctx->vif &&
192 ctx->vif->type == NL80211_IFTYPE_STATION) {
193 ctx->last_tx_rejected = true;
194 iwl_stop_queue(priv, &priv->txq[txq_id]);
197 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
200 iwl_get_tx_fail_reason(status), status,
201 le32_to_cpu(tx_resp->rate_n_flags),
202 tx_resp->failure_frame);
205 #ifdef CONFIG_IWLWIFI_DEBUG
206 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
208 const char *iwl_get_agg_tx_fail_reason(u16 status)
210 status &= AGG_TX_STATUS_MSK;
212 case AGG_TX_STATE_TRANSMITTED:
214 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
215 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
216 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
217 AGG_TX_STATE_FAIL(ABORT_MSK);
218 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
219 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
220 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
221 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
222 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
223 AGG_TX_STATE_FAIL(RESPONSE_MSK);
224 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
225 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
230 #endif /* CONFIG_IWLWIFI_DEBUG */
232 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
233 struct iwl_ht_agg *agg,
234 struct iwlagn_tx_resp *tx_resp,
235 int txq_id, u16 start_idx)
238 struct agg_tx_status *frame_status = &tx_resp->status;
239 struct ieee80211_hdr *hdr = NULL;
243 if (agg->wait_for_ba)
244 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
246 agg->frame_count = tx_resp->frame_count;
247 agg->start_idx = start_idx;
248 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
251 /* # frames attempted by Tx command */
252 if (agg->frame_count == 1) {
253 struct iwl_tx_info *txb;
255 /* Only one frame was attempted; no block-ack will arrive */
258 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
259 agg->frame_count, agg->start_idx, idx);
260 txb = &priv->txq[txq_id].txb[idx];
261 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
262 txb->ctx, tx_resp, txq_id, true);
263 agg->wait_for_ba = 0;
265 /* Two or more frames were attempted; expect block-ack */
269 * Start is the lowest frame sent. It may not be the first
270 * frame in the batch; we figure this out dynamically during
271 * the following loop.
273 int start = agg->start_idx;
275 /* Construct bit-map of pending frames within Tx window */
276 for (i = 0; i < agg->frame_count; i++) {
278 status = le16_to_cpu(frame_status[i].status);
279 seq = le16_to_cpu(frame_status[i].sequence);
280 idx = SEQ_TO_INDEX(seq);
281 txq_id = SEQ_TO_QUEUE(seq);
283 if (status & AGG_TX_STATUS_MSK)
284 iwlagn_count_agg_tx_err_status(priv, status);
286 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
287 AGG_TX_STATE_ABORT_MSK))
290 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
291 agg->frame_count, txq_id, idx);
292 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
293 "try-count (0x%08x)\n",
294 iwl_get_agg_tx_fail_reason(status),
295 status & AGG_TX_STATUS_MSK,
296 status & AGG_TX_TRY_MSK);
298 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
301 "BUG_ON idx doesn't point to valid skb"
302 " idx=%d, txq_id=%d\n", idx, txq_id);
306 sc = le16_to_cpu(hdr->seq_ctrl);
307 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
309 "BUG_ON idx doesn't match seq control"
310 " idx=%d, seq_idx=%d, seq=%d\n",
316 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
317 i, idx, SEQ_TO_SN(sc));
320 * sh -> how many frames ahead of the starting frame is
323 * Note that all frames sent in the batch must be in a
324 * 64-frame window, so this number should be in [0,63].
325 * If outside of this window, then we've found a new
326 * "first" frame in the batch and need to change start.
331 * If >= 64, out of window. start must be at the front
332 * of the circular buffer, idx must be near the end of
333 * the buffer, and idx is the new "first" frame. Shift
334 * the indices around.
337 /* Shift bitmap by start - idx, wrapped */
338 sh = 0x100 - idx + start;
339 bitmap = bitmap << sh;
340 /* Now idx is the new start so sh = 0 */
344 * If <= -64 then wraps the 256-pkt circular buffer
345 * (e.g., start = 255 and idx = 0, sh should be 1)
347 } else if (sh <= -64) {
348 sh = 0x100 - start + idx;
350 * If < 0 but > -64, out of window. idx is before start
351 * but not wrapped. Shift the indices around.
354 /* Shift by how far start is ahead of idx */
356 bitmap = bitmap << sh;
357 /* Now idx is the new start so sh = 0 */
361 /* Sequence number start + sh was sent in this batch */
362 bitmap |= 1ULL << sh;
363 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
364 start, (unsigned long long)bitmap);
368 * Store the bitmap and possibly the new start, if we wrapped
371 agg->bitmap = bitmap;
372 agg->start_idx = start;
373 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
374 agg->frame_count, agg->start_idx,
375 (unsigned long long)agg->bitmap);
378 agg->wait_for_ba = 1;
383 void iwl_check_abort_status(struct iwl_priv *priv,
384 u8 frame_count, u32 status)
386 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
387 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
388 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
389 queue_work(priv->workqueue, &priv->tx_flush);
393 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
394 struct iwl_rx_mem_buffer *rxb)
396 struct iwl_rx_packet *pkt = rxb_addr(rxb);
397 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
398 int txq_id = SEQ_TO_QUEUE(sequence);
399 int index = SEQ_TO_INDEX(sequence);
400 struct iwl_tx_queue *txq = &priv->txq[txq_id];
401 struct ieee80211_tx_info *info;
402 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
403 struct iwl_tx_info *txb;
404 u32 status = le16_to_cpu(tx_resp->status.status);
410 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
411 IWL_ERR(priv, "%s: Read index for DMA queue txq_id (%d) "
412 "index %d is out of range [0-%d] %d %d\n", __func__,
413 txq_id, index, txq->q.n_bd, txq->q.write_ptr,
418 txq->time_stamp = jiffies;
419 txb = &txq->txb[txq->q.read_ptr];
420 info = IEEE80211_SKB_CB(txb->skb);
421 memset(&info->status, 0, sizeof(info->status));
423 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
424 IWLAGN_TX_RES_TID_POS;
425 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
426 IWLAGN_TX_RES_RA_POS;
428 spin_lock_irqsave(&priv->sta_lock, flags);
429 if (txq->sched_retry) {
430 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
431 struct iwl_ht_agg *agg;
433 agg = &priv->stations[sta_id].tid[tid].agg;
435 * If the BT kill count is non-zero, we'll get this
436 * notification again.
438 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
439 priv->cfg->bt_params &&
440 priv->cfg->bt_params->advanced_bt_coexist) {
441 IWL_WARN(priv, "receive reply tx with bt_kill\n");
443 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
445 /* check if BAR is needed */
446 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
447 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
449 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
450 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
451 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
452 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
453 scd_ssn , index, txq_id, txq->swq_id);
455 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
456 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
458 if (priv->mac80211_registered &&
459 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
460 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
461 iwl_wake_queue(priv, txq);
464 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
466 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
467 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
469 if (priv->mac80211_registered &&
470 iwl_queue_space(&txq->q) > txq->q.low_mark &&
471 status != TX_STATUS_FAIL_PASSIVE_NO_RX)
472 iwl_wake_queue(priv, txq);
475 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
477 iwl_check_abort_status(priv, tx_resp->frame_count, status);
478 spin_unlock_irqrestore(&priv->sta_lock, flags);
481 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
483 /* init calibration handlers */
484 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
485 iwlagn_rx_calib_result;
486 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
488 /* set up notification wait support */
489 spin_lock_init(&priv->_agn.notif_wait_lock);
490 INIT_LIST_HEAD(&priv->_agn.notif_waits);
491 init_waitqueue_head(&priv->_agn.notif_waitq);
494 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
497 * nothing need to be done here anymore
498 * still keep for future use if needed
502 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
504 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
505 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
508 int iwlagn_send_tx_power(struct iwl_priv *priv)
510 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
513 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
514 "TX Power requested while scanning!\n"))
517 /* half dBm need to multiply */
518 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
520 if (priv->tx_power_lmt_in_half_dbm &&
521 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
523 * For the newer devices which using enhanced/extend tx power
524 * table in EEPROM, the format is in half dBm. driver need to
525 * convert to dBm format before report to mac80211.
526 * By doing so, there is a possibility of 1/2 dBm resolution
527 * lost. driver will perform "round-up" operation before
528 * reporting, but it will cause 1/2 dBm tx power over the
529 * regulatory limit. Perform the checking here, if the
530 * "tx_power_user_lmt" is higher than EEPROM value (in
531 * half-dBm format), lower the tx power based on EEPROM
533 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
535 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
536 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
538 if (IWL_UCODE_API(priv->ucode_ver) == 1)
539 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
541 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
543 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
547 void iwlagn_temperature(struct iwl_priv *priv)
549 /* store temperature from correct statistics (in Celsius) */
550 priv->temperature = le32_to_cpu(priv->statistics.common.temperature);
551 iwl_tt_handler(priv);
554 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
556 struct iwl_eeprom_calib_hdr {
562 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
571 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
575 if ((address & INDIRECT_ADDRESS) == 0)
578 switch (address & INDIRECT_TYPE_MSK) {
580 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
582 case INDIRECT_GENERAL:
583 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
585 case INDIRECT_REGULATORY:
586 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
588 case INDIRECT_TXP_LIMIT:
589 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
591 case INDIRECT_TXP_LIMIT_SIZE:
592 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
594 case INDIRECT_CALIBRATION:
595 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
597 case INDIRECT_PROCESS_ADJST:
598 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
600 case INDIRECT_OTHERS:
601 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
604 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
605 address & INDIRECT_TYPE_MSK);
609 /* translate the offset from words to byte */
610 return (address & ADDRESS_MSK) + (offset << 1);
613 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
616 u32 address = eeprom_indirect_address(priv, offset);
617 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
618 return &priv->eeprom[address];
621 struct iwl_mod_params iwlagn_mod_params = {
625 .bt_coex_active = true,
626 /* the rest are 0 by default */
629 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
633 spin_lock_irqsave(&rxq->lock, flags);
634 INIT_LIST_HEAD(&rxq->rx_free);
635 INIT_LIST_HEAD(&rxq->rx_used);
636 /* Fill the rx_used queue with _all_ of the Rx buffers */
637 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
638 /* In the reset function, these buffers may have been allocated
639 * to an SKB, so we need to unmap and free potential storage */
640 if (rxq->pool[i].page != NULL) {
641 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
642 PAGE_SIZE << priv->hw_params.rx_page_order,
644 __iwl_free_pages(priv, rxq->pool[i].page);
645 rxq->pool[i].page = NULL;
647 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
650 for (i = 0; i < RX_QUEUE_SIZE; i++)
651 rxq->queue[i] = NULL;
653 /* Set us so that we have processed and used all buffers, but have
654 * not restocked the Rx queue with fresh buffers */
655 rxq->read = rxq->write = 0;
656 rxq->write_actual = 0;
658 spin_unlock_irqrestore(&rxq->lock, flags);
661 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
664 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
665 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
667 rb_timeout = RX_RB_TIMEOUT;
669 if (iwlagn_mod_params.amsdu_size_8K)
670 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
672 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
675 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
677 /* Reset driver's Rx queue write index */
678 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
680 /* Tell device where to find RBD circular buffer in DRAM */
681 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
682 (u32)(rxq->bd_dma >> 8));
684 /* Tell device where in DRAM to update its Rx status */
685 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
686 rxq->rb_stts_dma >> 4);
689 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
690 * the credit mechanism in 5000 HW RX FIFO
691 * Direct rx interrupts to hosts
692 * Rx buffer size 4 or 8k
696 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
697 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
698 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
699 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
700 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
702 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
703 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
705 /* Set interrupt coalescing timer to default (2048 usecs) */
706 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
711 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
714 * (for documentation purposes)
715 * to set power to V_AUX, do:
717 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
718 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
719 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
720 ~APMG_PS_CTRL_MSK_PWR_SRC);
723 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
724 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
725 ~APMG_PS_CTRL_MSK_PWR_SRC);
728 int iwlagn_hw_nic_init(struct iwl_priv *priv)
731 struct iwl_rx_queue *rxq = &priv->rxq;
735 spin_lock_irqsave(&priv->lock, flags);
736 priv->cfg->ops->lib->apm_ops.init(priv);
738 /* Set interrupt coalescing calibration timer to default (512 usecs) */
739 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
741 spin_unlock_irqrestore(&priv->lock, flags);
743 iwlagn_set_pwr_vmain(priv);
745 priv->cfg->ops->lib->apm_ops.config(priv);
747 /* Allocate the RX queue, or reset if it is already allocated */
749 ret = iwl_rx_queue_alloc(priv);
751 IWL_ERR(priv, "Unable to initialize Rx queue\n");
755 iwlagn_rx_queue_reset(priv, rxq);
757 iwlagn_rx_replenish(priv);
759 iwlagn_rx_init(priv, rxq);
761 spin_lock_irqsave(&priv->lock, flags);
763 rxq->need_update = 1;
764 iwl_rx_queue_update_write_ptr(priv, rxq);
766 spin_unlock_irqrestore(&priv->lock, flags);
768 /* Allocate or reset and init all Tx and Command queues */
770 ret = iwlagn_txq_ctx_alloc(priv);
774 iwlagn_txq_ctx_reset(priv);
776 if (priv->cfg->base_params->shadow_reg_enable) {
777 /* enable shadow regs in HW */
778 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
782 set_bit(STATUS_INIT, &priv->status);
788 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
790 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
793 return cpu_to_le32((u32)(dma_addr >> 8));
797 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
799 * If there are slots in the RX queue that need to be restocked,
800 * and we have free pre-allocated buffers, fill the ranks as much
801 * as we can, pulling from rx_free.
803 * This moves the 'write' index forward to catch up with 'processed', and
804 * also updates the memory address in the firmware to reference the new
807 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
809 struct iwl_rx_queue *rxq = &priv->rxq;
810 struct list_head *element;
811 struct iwl_rx_mem_buffer *rxb;
814 spin_lock_irqsave(&rxq->lock, flags);
815 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
816 /* The overwritten rxb must be a used one */
817 rxb = rxq->queue[rxq->write];
818 BUG_ON(rxb && rxb->page);
820 /* Get next free Rx buffer, remove from free list */
821 element = rxq->rx_free.next;
822 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
825 /* Point to Rx buffer via next RBD in circular buffer */
826 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
828 rxq->queue[rxq->write] = rxb;
829 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
832 spin_unlock_irqrestore(&rxq->lock, flags);
833 /* If the pre-allocated buffer pool is dropping low, schedule to
835 if (rxq->free_count <= RX_LOW_WATERMARK)
836 queue_work(priv->workqueue, &priv->rx_replenish);
839 /* If we've added more space for the firmware to place data, tell it.
840 * Increment device's write pointer in multiples of 8. */
841 if (rxq->write_actual != (rxq->write & ~0x7)) {
842 spin_lock_irqsave(&rxq->lock, flags);
843 rxq->need_update = 1;
844 spin_unlock_irqrestore(&rxq->lock, flags);
845 iwl_rx_queue_update_write_ptr(priv, rxq);
850 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
852 * When moving to rx_free an SKB is allocated for the slot.
854 * Also restock the Rx queue via iwl_rx_queue_restock.
855 * This is called as a scheduled work item (except for during initialization)
857 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
859 struct iwl_rx_queue *rxq = &priv->rxq;
860 struct list_head *element;
861 struct iwl_rx_mem_buffer *rxb;
864 gfp_t gfp_mask = priority;
867 spin_lock_irqsave(&rxq->lock, flags);
868 if (list_empty(&rxq->rx_used)) {
869 spin_unlock_irqrestore(&rxq->lock, flags);
872 spin_unlock_irqrestore(&rxq->lock, flags);
874 if (rxq->free_count > RX_LOW_WATERMARK)
875 gfp_mask |= __GFP_NOWARN;
877 if (priv->hw_params.rx_page_order > 0)
878 gfp_mask |= __GFP_COMP;
880 /* Alloc a new receive buffer */
881 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
884 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
886 priv->hw_params.rx_page_order);
888 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
890 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
891 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
893 /* We don't reschedule replenish work here -- we will
894 * call the restock method and if it still needs
895 * more buffers it will schedule replenish */
899 spin_lock_irqsave(&rxq->lock, flags);
901 if (list_empty(&rxq->rx_used)) {
902 spin_unlock_irqrestore(&rxq->lock, flags);
903 __free_pages(page, priv->hw_params.rx_page_order);
906 element = rxq->rx_used.next;
907 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
910 spin_unlock_irqrestore(&rxq->lock, flags);
914 /* Get physical address of the RB */
915 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
916 PAGE_SIZE << priv->hw_params.rx_page_order,
918 /* dma address must be no more than 36 bits */
919 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
920 /* and also 256 byte aligned! */
921 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
923 spin_lock_irqsave(&rxq->lock, flags);
925 list_add_tail(&rxb->list, &rxq->rx_free);
928 spin_unlock_irqrestore(&rxq->lock, flags);
932 void iwlagn_rx_replenish(struct iwl_priv *priv)
936 iwlagn_rx_allocate(priv, GFP_KERNEL);
938 spin_lock_irqsave(&priv->lock, flags);
939 iwlagn_rx_queue_restock(priv);
940 spin_unlock_irqrestore(&priv->lock, flags);
943 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
945 iwlagn_rx_allocate(priv, GFP_ATOMIC);
947 iwlagn_rx_queue_restock(priv);
950 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
951 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
952 * This free routine walks the list of POOL entries and if SKB is set to
953 * non NULL it is unmapped and freed
955 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
958 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
959 if (rxq->pool[i].page != NULL) {
960 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
961 PAGE_SIZE << priv->hw_params.rx_page_order,
963 __iwl_free_pages(priv, rxq->pool[i].page);
964 rxq->pool[i].page = NULL;
968 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
970 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
971 rxq->rb_stts, rxq->rb_stts_dma);
976 int iwlagn_rxq_stop(struct iwl_priv *priv)
980 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
981 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
982 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
987 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
992 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
993 if (rate_n_flags & RATE_MCS_HT_MSK) {
994 idx = (rate_n_flags & 0xff);
996 /* Legacy rate format, search for match in table */
998 if (band == IEEE80211_BAND_5GHZ)
999 band_offset = IWL_FIRST_OFDM_RATE;
1000 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
1001 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
1002 return idx - band_offset;
1008 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1009 struct ieee80211_vif *vif,
1010 enum ieee80211_band band,
1011 struct iwl_scan_channel *scan_ch)
1013 const struct ieee80211_supported_band *sband;
1014 u16 passive_dwell = 0;
1015 u16 active_dwell = 0;
1019 sband = iwl_get_hw_mode(priv, band);
1021 IWL_ERR(priv, "invalid band\n");
1025 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1026 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1028 if (passive_dwell <= active_dwell)
1029 passive_dwell = active_dwell + 1;
1031 channel = iwl_get_single_channel_number(priv, band);
1033 scan_ch->channel = cpu_to_le16(channel);
1034 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1035 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1036 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1037 /* Set txpower levels to defaults */
1038 scan_ch->dsp_atten = 110;
1039 if (band == IEEE80211_BAND_5GHZ)
1040 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1042 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1045 IWL_ERR(priv, "no valid channel found\n");
1049 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1050 struct ieee80211_vif *vif,
1051 enum ieee80211_band band,
1052 u8 is_active, u8 n_probes,
1053 struct iwl_scan_channel *scan_ch)
1055 struct ieee80211_channel *chan;
1056 const struct ieee80211_supported_band *sband;
1057 const struct iwl_channel_info *ch_info;
1058 u16 passive_dwell = 0;
1059 u16 active_dwell = 0;
1063 sband = iwl_get_hw_mode(priv, band);
1067 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1068 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1070 if (passive_dwell <= active_dwell)
1071 passive_dwell = active_dwell + 1;
1073 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1074 chan = priv->scan_request->channels[i];
1076 if (chan->band != band)
1079 channel = chan->hw_value;
1080 scan_ch->channel = cpu_to_le16(channel);
1082 ch_info = iwl_get_channel_info(priv, band, channel);
1083 if (!is_channel_valid(ch_info)) {
1084 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1089 if (!is_active || is_channel_passive(ch_info) ||
1090 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1091 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1093 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1096 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1098 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1099 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1101 /* Set txpower levels to defaults */
1102 scan_ch->dsp_atten = 110;
1104 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1106 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1108 if (band == IEEE80211_BAND_5GHZ)
1109 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1111 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1113 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1114 channel, le32_to_cpu(scan_ch->type),
1115 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1116 "ACTIVE" : "PASSIVE",
1117 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1118 active_dwell : passive_dwell);
1124 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1128 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1130 struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1132 if (skb->len < maxlen)
1135 memcpy(data, skb->data, maxlen);
1140 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1142 struct iwl_host_cmd cmd = {
1143 .id = REPLY_SCAN_CMD,
1144 .len = { sizeof(struct iwl_scan_cmd), },
1146 struct iwl_scan_cmd *scan;
1147 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1151 enum ieee80211_band band;
1153 u8 rx_ant = priv->hw_params.valid_rx_ant;
1155 bool is_active = false;
1158 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1161 lockdep_assert_held(&priv->mutex);
1164 ctx = iwl_rxon_ctx_from_vif(vif);
1166 if (!priv->scan_cmd) {
1167 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1168 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1169 if (!priv->scan_cmd) {
1170 IWL_DEBUG_SCAN(priv,
1171 "fail to allocate memory for scan\n");
1175 scan = priv->scan_cmd;
1176 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1178 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1179 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1181 if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1182 iwl_is_any_associated(priv)) {
1185 u32 suspend_time = 100;
1186 u32 scan_suspend_time = 100;
1188 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1189 switch (priv->scan_type) {
1190 case IWL_SCAN_OFFCH_TX:
1193 case IWL_SCAN_RADIO_RESET:
1196 case IWL_SCAN_NORMAL:
1197 interval = vif->bss_conf.beacon_int;
1201 scan->suspend_time = 0;
1202 scan->max_out_time = cpu_to_le32(200 * 1024);
1204 interval = suspend_time;
1206 extra = (suspend_time / interval) << 22;
1207 scan_suspend_time = (extra |
1208 ((suspend_time % interval) * 1024));
1209 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1210 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1211 scan_suspend_time, interval);
1212 } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1213 scan->suspend_time = 0;
1214 scan->max_out_time =
1215 cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1218 switch (priv->scan_type) {
1219 case IWL_SCAN_RADIO_RESET:
1220 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1222 case IWL_SCAN_NORMAL:
1223 if (priv->scan_request->n_ssids) {
1225 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1226 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1227 /* always does wildcard anyway */
1228 if (!priv->scan_request->ssids[i].ssid_len)
1230 scan->direct_scan[p].id = WLAN_EID_SSID;
1231 scan->direct_scan[p].len =
1232 priv->scan_request->ssids[i].ssid_len;
1233 memcpy(scan->direct_scan[p].ssid,
1234 priv->scan_request->ssids[i].ssid,
1235 priv->scan_request->ssids[i].ssid_len);
1241 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1243 case IWL_SCAN_OFFCH_TX:
1244 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1248 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1249 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1250 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1252 switch (priv->scan_band) {
1253 case IEEE80211_BAND_2GHZ:
1254 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1255 chan_mod = le32_to_cpu(
1256 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1257 RXON_FLG_CHANNEL_MODE_MSK)
1258 >> RXON_FLG_CHANNEL_MODE_POS;
1259 if (chan_mod == CHANNEL_MODE_PURE_40) {
1260 rate = IWL_RATE_6M_PLCP;
1262 rate = IWL_RATE_1M_PLCP;
1263 rate_flags = RATE_MCS_CCK_MSK;
1266 * Internal scans are passive, so we can indiscriminately set
1267 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1269 if (priv->cfg->bt_params &&
1270 priv->cfg->bt_params->advanced_bt_coexist)
1271 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1273 case IEEE80211_BAND_5GHZ:
1274 rate = IWL_RATE_6M_PLCP;
1277 IWL_WARN(priv, "Invalid scan band\n");
1282 * If active scanning is requested but a certain channel is
1283 * marked passive, we can do active scanning if we detect
1286 * There is an issue with some firmware versions that triggers
1287 * a sysassert on a "good CRC threshold" of zero (== disabled),
1288 * on a radar channel even though this means that we should NOT
1291 * The "good CRC threshold" is the number of frames that we
1292 * need to receive during our dwell time on a channel before
1293 * sending out probes -- setting this to a huge value will
1294 * mean we never reach it, but at the same time work around
1295 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1296 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1298 * This was fixed in later versions along with some other
1299 * scan changes, and the threshold behaves as a flag in those
1302 if (priv->new_scan_threshold_behaviour)
1303 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1304 IWL_GOOD_CRC_TH_DISABLED;
1306 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1307 IWL_GOOD_CRC_TH_NEVER;
1309 band = priv->scan_band;
1311 if (priv->cfg->scan_rx_antennas[band])
1312 rx_ant = priv->cfg->scan_rx_antennas[band];
1314 if (band == IEEE80211_BAND_2GHZ &&
1315 priv->cfg->bt_params &&
1316 priv->cfg->bt_params->advanced_bt_coexist) {
1317 /* transmit 2.4 GHz probes only on first antenna */
1318 scan_tx_antennas = first_antenna(scan_tx_antennas);
1321 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1323 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1324 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1326 /* In power save mode use one chain, otherwise use all chains */
1327 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1328 /* rx_ant has been set to all valid chains previously */
1329 active_chains = rx_ant &
1330 ((u8)(priv->chain_noise_data.active_chains));
1332 active_chains = rx_ant;
1334 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1335 priv->chain_noise_data.active_chains);
1337 rx_ant = first_antenna(active_chains);
1339 if (priv->cfg->bt_params &&
1340 priv->cfg->bt_params->advanced_bt_coexist &&
1341 priv->bt_full_concurrent) {
1342 /* operated as 1x1 in full concurrency mode */
1343 rx_ant = first_antenna(rx_ant);
1346 /* MIMO is not used here, but value is required */
1347 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1348 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1349 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1350 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1351 scan->rx_chain = cpu_to_le16(rx_chain);
1352 switch (priv->scan_type) {
1353 case IWL_SCAN_NORMAL:
1354 cmd_len = iwl_fill_probe_req(priv,
1355 (struct ieee80211_mgmt *)scan->data,
1357 priv->scan_request->ie,
1358 priv->scan_request->ie_len,
1359 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1361 case IWL_SCAN_RADIO_RESET:
1362 /* use bcast addr, will not be transmitted but must be valid */
1363 cmd_len = iwl_fill_probe_req(priv,
1364 (struct ieee80211_mgmt *)scan->data,
1365 iwl_bcast_addr, NULL, 0,
1366 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1368 case IWL_SCAN_OFFCH_TX:
1369 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1372 - sizeof(struct iwl_scan_channel));
1373 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1378 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1380 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1381 RXON_FILTER_BCON_AWARE_MSK);
1383 switch (priv->scan_type) {
1384 case IWL_SCAN_RADIO_RESET:
1385 scan->channel_count =
1386 iwl_get_single_channel_for_scan(priv, vif, band,
1387 (void *)&scan->data[cmd_len]);
1389 case IWL_SCAN_NORMAL:
1390 scan->channel_count =
1391 iwl_get_channels_for_scan(priv, vif, band,
1392 is_active, n_probes,
1393 (void *)&scan->data[cmd_len]);
1395 case IWL_SCAN_OFFCH_TX: {
1396 struct iwl_scan_channel *scan_ch;
1398 scan->channel_count = 1;
1400 scan_ch = (void *)&scan->data[cmd_len];
1401 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1403 cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1404 scan_ch->active_dwell =
1405 cpu_to_le16(priv->_agn.offchan_tx_timeout);
1406 scan_ch->passive_dwell = 0;
1408 /* Set txpower levels to defaults */
1409 scan_ch->dsp_atten = 110;
1411 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1413 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1415 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1416 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1418 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1423 if (scan->channel_count == 0) {
1424 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1428 cmd.len[0] += le16_to_cpu(scan->tx_cmd.len) +
1429 scan->channel_count * sizeof(struct iwl_scan_channel);
1431 cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
1432 scan->len = cpu_to_le16(cmd.len[0]);
1434 /* set scan bit here for PAN params */
1435 set_bit(STATUS_SCAN_HW, &priv->status);
1437 if (priv->cfg->ops->hcmd->set_pan_params) {
1438 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1443 ret = iwl_send_cmd_sync(priv, &cmd);
1445 clear_bit(STATUS_SCAN_HW, &priv->status);
1446 if (priv->cfg->ops->hcmd->set_pan_params)
1447 priv->cfg->ops->hcmd->set_pan_params(priv);
1453 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1454 struct ieee80211_vif *vif, bool add)
1456 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1459 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1460 vif->bss_conf.bssid,
1461 &vif_priv->ibss_bssid_sta_id);
1462 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1463 vif->bss_conf.bssid);
1466 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1467 int sta_id, int tid, int freed)
1469 lockdep_assert_held(&priv->sta_lock);
1471 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1472 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1474 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1475 priv->stations[sta_id].tid[tid].tfds_in_queue,
1477 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1481 #define IWL_FLUSH_WAIT_MS 2000
1483 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1485 struct iwl_tx_queue *txq;
1486 struct iwl_queue *q;
1488 unsigned long now = jiffies;
1491 /* waiting for all the tx frames complete might take a while */
1492 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1493 if (cnt == priv->cmd_queue)
1495 txq = &priv->txq[cnt];
1497 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1498 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1501 if (q->read_ptr != q->write_ptr) {
1502 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1510 #define IWL_TX_QUEUE_MSK 0xfffff
1513 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1516 * 1. acquire mutex before calling
1517 * 2. make sure rf is on and not in exit state
1519 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1521 struct iwl_txfifo_flush_cmd flush_cmd;
1522 struct iwl_host_cmd cmd = {
1523 .id = REPLY_TXFIFO_FLUSH,
1524 .len = { sizeof(struct iwl_txfifo_flush_cmd), },
1526 .data = { &flush_cmd, },
1531 memset(&flush_cmd, 0, sizeof(flush_cmd));
1532 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1533 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1534 if (priv->cfg->sku & IWL_SKU_N)
1535 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1537 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1538 flush_cmd.fifo_control);
1539 flush_cmd.flush_control = cpu_to_le16(flush_control);
1541 return iwl_send_cmd(priv, &cmd);
1544 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1546 mutex_lock(&priv->mutex);
1547 ieee80211_stop_queues(priv->hw);
1548 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1549 IWL_ERR(priv, "flush request fail\n");
1552 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1553 iwlagn_wait_tx_queue_empty(priv);
1555 ieee80211_wake_queues(priv->hw);
1556 mutex_unlock(&priv->mutex);
1563 * Macros to access the lookup table.
1565 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1566 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1568 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1570 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1571 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1572 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1574 * These macros encode that format.
1576 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1577 wifi_txrx, wifi_sh_ant_req) \
1578 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1579 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1581 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1582 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1583 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1584 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1585 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1586 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1588 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1589 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1590 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1591 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1593 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1594 wifi_req, wifi_prio, wifi_txrx, \
1596 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1597 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1600 #define LUT_WLAN_KILL_OP(lut, op, val) \
1601 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1602 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1603 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1604 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1605 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1606 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1607 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1608 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1609 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1610 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1611 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1612 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1613 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1615 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1616 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1617 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1618 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1619 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1620 wifi_req, wifi_prio, wifi_txrx, \
1622 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1623 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1624 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1625 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1626 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1627 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1628 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1629 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1631 static const __le32 iwlagn_def_3w_lookup[12] = {
1632 cpu_to_le32(0xaaaaaaaa),
1633 cpu_to_le32(0xaaaaaaaa),
1634 cpu_to_le32(0xaeaaaaaa),
1635 cpu_to_le32(0xaaaaaaaa),
1636 cpu_to_le32(0xcc00ff28),
1637 cpu_to_le32(0x0000aaaa),
1638 cpu_to_le32(0xcc00aaaa),
1639 cpu_to_le32(0x0000aaaa),
1640 cpu_to_le32(0xc0004000),
1641 cpu_to_le32(0x00004000),
1642 cpu_to_le32(0xf0005000),
1643 cpu_to_le32(0xf0005000),
1646 static const __le32 iwlagn_concurrent_lookup[12] = {
1647 cpu_to_le32(0xaaaaaaaa),
1648 cpu_to_le32(0xaaaaaaaa),
1649 cpu_to_le32(0xaaaaaaaa),
1650 cpu_to_le32(0xaaaaaaaa),
1651 cpu_to_le32(0xaaaaaaaa),
1652 cpu_to_le32(0xaaaaaaaa),
1653 cpu_to_le32(0xaaaaaaaa),
1654 cpu_to_le32(0xaaaaaaaa),
1655 cpu_to_le32(0x00000000),
1656 cpu_to_le32(0x00000000),
1657 cpu_to_le32(0x00000000),
1658 cpu_to_le32(0x00000000),
1661 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1663 struct iwl_basic_bt_cmd basic = {
1664 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1665 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1666 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1667 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1669 struct iwl6000_bt_cmd bt_cmd_6000;
1670 struct iwl2000_bt_cmd bt_cmd_2000;
1673 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1674 sizeof(basic.bt3_lookup_table));
1676 if (priv->cfg->bt_params) {
1677 if (priv->cfg->bt_params->bt_session_2) {
1678 bt_cmd_2000.prio_boost = cpu_to_le32(
1679 priv->cfg->bt_params->bt_prio_boost);
1680 bt_cmd_2000.tx_prio_boost = 0;
1681 bt_cmd_2000.rx_prio_boost = 0;
1683 bt_cmd_6000.prio_boost =
1684 priv->cfg->bt_params->bt_prio_boost;
1685 bt_cmd_6000.tx_prio_boost = 0;
1686 bt_cmd_6000.rx_prio_boost = 0;
1689 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1693 basic.kill_ack_mask = priv->kill_ack_mask;
1694 basic.kill_cts_mask = priv->kill_cts_mask;
1695 basic.valid = priv->bt_valid;
1698 * Configure BT coex mode to "no coexistence" when the
1699 * user disabled BT coexistence, we have no interface
1700 * (might be in monitor mode), or the interface is in
1701 * IBSS mode (no proper uCode support for coex then).
1703 if (!iwlagn_mod_params.bt_coex_active ||
1704 priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1705 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1707 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1708 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1709 if (priv->cfg->bt_params &&
1710 priv->cfg->bt_params->bt_sco_disable)
1711 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1713 if (priv->bt_ch_announce)
1714 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1715 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1717 priv->bt_enable_flag = basic.flags;
1718 if (priv->bt_full_concurrent)
1719 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1720 sizeof(iwlagn_concurrent_lookup));
1722 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1723 sizeof(iwlagn_def_3w_lookup));
1725 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1726 basic.flags ? "active" : "disabled",
1727 priv->bt_full_concurrent ?
1728 "full concurrency" : "3-wire");
1730 if (priv->cfg->bt_params->bt_session_2) {
1731 memcpy(&bt_cmd_2000.basic, &basic,
1733 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1734 sizeof(bt_cmd_2000), &bt_cmd_2000);
1736 memcpy(&bt_cmd_6000.basic, &basic,
1738 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1739 sizeof(bt_cmd_6000), &bt_cmd_6000);
1742 IWL_ERR(priv, "failed to send BT Coex Config\n");
1746 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1748 struct iwl_priv *priv =
1749 container_of(work, struct iwl_priv, bt_traffic_change_work);
1750 struct iwl_rxon_context *ctx;
1751 int smps_request = -1;
1753 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1754 /* bt coex disabled */
1759 * Note: bt_traffic_load can be overridden by scan complete and
1760 * coex profile notifications. Ignore that since only bad consequence
1761 * can be not matching debug print with actual state.
1763 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1764 priv->bt_traffic_load);
1766 switch (priv->bt_traffic_load) {
1767 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1768 if (priv->bt_status)
1769 smps_request = IEEE80211_SMPS_DYNAMIC;
1771 smps_request = IEEE80211_SMPS_AUTOMATIC;
1773 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1774 smps_request = IEEE80211_SMPS_DYNAMIC;
1776 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1777 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1778 smps_request = IEEE80211_SMPS_STATIC;
1781 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1782 priv->bt_traffic_load);
1786 mutex_lock(&priv->mutex);
1789 * We can not send command to firmware while scanning. When the scan
1790 * complete we will schedule this work again. We do check with mutex
1791 * locked to prevent new scan request to arrive. We do not check
1792 * STATUS_SCANNING to avoid race when queue_work two times from
1793 * different notifications, but quit and not perform any work at all.
1795 if (test_bit(STATUS_SCAN_HW, &priv->status))
1798 if (priv->cfg->ops->lib->update_chain_flags)
1799 priv->cfg->ops->lib->update_chain_flags(priv);
1801 if (smps_request != -1) {
1802 priv->current_ht_config.smps = smps_request;
1803 for_each_context(priv, ctx) {
1804 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1805 ieee80211_request_smps(ctx->vif, smps_request);
1809 mutex_unlock(&priv->mutex);
1812 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1813 struct iwl_bt_uart_msg *uart_msg)
1815 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1816 "Update Req = 0x%X",
1817 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1818 BT_UART_MSG_FRAME1MSGTYPE_POS,
1819 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1820 BT_UART_MSG_FRAME1SSN_POS,
1821 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1822 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1824 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1825 "Chl_SeqN = 0x%X, In band = 0x%X",
1826 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1827 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1828 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1829 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1830 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1831 BT_UART_MSG_FRAME2CHLSEQN_POS,
1832 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1833 BT_UART_MSG_FRAME2INBAND_POS);
1835 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1836 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1837 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1838 BT_UART_MSG_FRAME3SCOESCO_POS,
1839 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1840 BT_UART_MSG_FRAME3SNIFF_POS,
1841 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1842 BT_UART_MSG_FRAME3A2DP_POS,
1843 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1844 BT_UART_MSG_FRAME3ACL_POS,
1845 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1846 BT_UART_MSG_FRAME3MASTER_POS,
1847 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1848 BT_UART_MSG_FRAME3OBEX_POS);
1850 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1851 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1852 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1854 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1855 "eSCO Retransmissions = 0x%X",
1856 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1857 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1858 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1859 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1860 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1861 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1863 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1864 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1865 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1866 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1867 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1869 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
1870 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1871 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1872 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1873 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1874 BT_UART_MSG_FRAME7PAGE_POS,
1875 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1876 BT_UART_MSG_FRAME7INQUIRY_POS,
1877 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1878 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1881 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1882 struct iwl_bt_uart_msg *uart_msg)
1885 static const __le32 bt_kill_ack_msg[2] = {
1886 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1887 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1888 static const __le32 bt_kill_cts_msg[2] = {
1889 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1890 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1892 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1894 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1895 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1896 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1897 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1898 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1899 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1901 /* schedule to send runtime bt_config */
1902 queue_work(priv->workqueue, &priv->bt_runtime_config);
1906 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1907 struct iwl_rx_mem_buffer *rxb)
1909 unsigned long flags;
1910 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1911 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1912 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1914 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1915 /* bt coex disabled */
1919 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1920 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
1921 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
1922 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
1923 coex->bt_ci_compliance);
1924 iwlagn_print_uartmsg(priv, uart_msg);
1926 priv->last_bt_traffic_load = priv->bt_traffic_load;
1927 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1928 if (priv->bt_status != coex->bt_status ||
1929 priv->last_bt_traffic_load != coex->bt_traffic_load) {
1930 if (coex->bt_status) {
1932 if (!priv->bt_ch_announce)
1933 priv->bt_traffic_load =
1934 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1936 priv->bt_traffic_load =
1937 coex->bt_traffic_load;
1940 priv->bt_traffic_load =
1941 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1943 priv->bt_status = coex->bt_status;
1944 queue_work(priv->workqueue,
1945 &priv->bt_traffic_change_work);
1949 iwlagn_set_kill_msk(priv, uart_msg);
1951 /* FIXME: based on notification, adjust the prio_boost */
1953 spin_lock_irqsave(&priv->lock, flags);
1954 priv->bt_ci_compliance = coex->bt_ci_compliance;
1955 spin_unlock_irqrestore(&priv->lock, flags);
1958 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1960 iwlagn_rx_handler_setup(priv);
1961 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1962 iwlagn_bt_coex_profile_notif;
1965 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1967 iwlagn_setup_deferred_work(priv);
1969 INIT_WORK(&priv->bt_traffic_change_work,
1970 iwlagn_bt_traffic_change_work);
1973 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1975 cancel_work_sync(&priv->bt_traffic_change_work);
1978 static bool is_single_rx_stream(struct iwl_priv *priv)
1980 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1981 priv->current_ht_config.single_chain_sufficient;
1984 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
1985 #define IWL_NUM_RX_CHAINS_SINGLE 2
1986 #define IWL_NUM_IDLE_CHAINS_DUAL 2
1987 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
1990 * Determine how many receiver/antenna chains to use.
1992 * More provides better reception via diversity. Fewer saves power
1993 * at the expense of throughput, but only when not in powersave to
1996 * MIMO (dual stream) requires at least 2, but works better with 3.
1997 * This does not determine *which* chains to use, just how many.
1999 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2001 if (priv->cfg->bt_params &&
2002 priv->cfg->bt_params->advanced_bt_coexist &&
2003 (priv->bt_full_concurrent ||
2004 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2006 * only use chain 'A' in bt high traffic load or
2007 * full concurrency mode
2009 return IWL_NUM_RX_CHAINS_SINGLE;
2011 /* # of Rx chains to use when expecting MIMO. */
2012 if (is_single_rx_stream(priv))
2013 return IWL_NUM_RX_CHAINS_SINGLE;
2015 return IWL_NUM_RX_CHAINS_MULTIPLE;
2019 * When we are in power saving mode, unless device support spatial
2020 * multiplexing power save, use the active count for rx chain count.
2022 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2024 /* # Rx chains when idling, depending on SMPS mode */
2025 switch (priv->current_ht_config.smps) {
2026 case IEEE80211_SMPS_STATIC:
2027 case IEEE80211_SMPS_DYNAMIC:
2028 return IWL_NUM_IDLE_CHAINS_SINGLE;
2029 case IEEE80211_SMPS_OFF:
2032 WARN(1, "invalid SMPS mode %d",
2033 priv->current_ht_config.smps);
2038 /* up to 4 chains */
2039 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2042 res = (chain_bitmap & BIT(0)) >> 0;
2043 res += (chain_bitmap & BIT(1)) >> 1;
2044 res += (chain_bitmap & BIT(2)) >> 2;
2045 res += (chain_bitmap & BIT(3)) >> 3;
2050 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2052 * Selects how many and which Rx receivers/antennas/chains to use.
2053 * This should not be used for scan command ... it puts data in wrong place.
2055 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2057 bool is_single = is_single_rx_stream(priv);
2058 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2059 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2063 /* Tell uCode which antennas are actually connected.
2064 * Before first association, we assume all antennas are connected.
2065 * Just after first association, iwl_chain_noise_calibration()
2066 * checks which antennas actually *are* connected. */
2067 if (priv->chain_noise_data.active_chains)
2068 active_chains = priv->chain_noise_data.active_chains;
2070 active_chains = priv->hw_params.valid_rx_ant;
2072 if (priv->cfg->bt_params &&
2073 priv->cfg->bt_params->advanced_bt_coexist &&
2074 (priv->bt_full_concurrent ||
2075 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2077 * only use chain 'A' in bt high traffic load or
2078 * full concurrency mode
2080 active_chains = first_antenna(active_chains);
2083 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2085 /* How many receivers should we use? */
2086 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2087 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2090 /* correct rx chain count according hw settings
2091 * and chain noise calibration
2093 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2094 if (valid_rx_cnt < active_rx_cnt)
2095 active_rx_cnt = valid_rx_cnt;
2097 if (valid_rx_cnt < idle_rx_cnt)
2098 idle_rx_cnt = valid_rx_cnt;
2100 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2101 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2103 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2105 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2106 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2108 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2110 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2111 ctx->staging.rx_chain,
2112 active_rx_cnt, idle_rx_cnt);
2114 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2115 active_rx_cnt < idle_rx_cnt);
2118 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2123 if (priv->band == IEEE80211_BAND_2GHZ &&
2124 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2127 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2128 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2129 if (valid & BIT(ind))
2135 static const char *get_csr_string(int cmd)
2138 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2139 IWL_CMD(CSR_INT_COALESCING);
2141 IWL_CMD(CSR_INT_MASK);
2142 IWL_CMD(CSR_FH_INT_STATUS);
2143 IWL_CMD(CSR_GPIO_IN);
2145 IWL_CMD(CSR_GP_CNTRL);
2146 IWL_CMD(CSR_HW_REV);
2147 IWL_CMD(CSR_EEPROM_REG);
2148 IWL_CMD(CSR_EEPROM_GP);
2149 IWL_CMD(CSR_OTP_GP_REG);
2150 IWL_CMD(CSR_GIO_REG);
2151 IWL_CMD(CSR_GP_UCODE_REG);
2152 IWL_CMD(CSR_GP_DRIVER_REG);
2153 IWL_CMD(CSR_UCODE_DRV_GP1);
2154 IWL_CMD(CSR_UCODE_DRV_GP2);
2155 IWL_CMD(CSR_LED_REG);
2156 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2157 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2158 IWL_CMD(CSR_ANA_PLL_CFG);
2159 IWL_CMD(CSR_HW_REV_WA_REG);
2160 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2166 void iwl_dump_csr(struct iwl_priv *priv)
2169 static const u32 csr_tbl[] = {
2170 CSR_HW_IF_CONFIG_REG,
2188 CSR_DRAM_INT_TBL_REG,
2189 CSR_GIO_CHICKEN_BITS,
2192 CSR_DBG_HPET_MEM_REG
2194 IWL_ERR(priv, "CSR values:\n");
2195 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2196 "CSR_INT_PERIODIC_REG)\n");
2197 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2198 IWL_ERR(priv, " %25s: 0X%08x\n",
2199 get_csr_string(csr_tbl[i]),
2200 iwl_read32(priv, csr_tbl[i]));
2204 static const char *get_fh_string(int cmd)
2207 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2208 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2209 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2210 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2211 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2212 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2213 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2214 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2215 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2221 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2224 #ifdef CONFIG_IWLWIFI_DEBUG
2228 static const u32 fh_tbl[] = {
2229 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2230 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2231 FH_RSCSR_CHNL0_WPTR,
2232 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2233 FH_MEM_RSSR_SHARED_CTRL_REG,
2234 FH_MEM_RSSR_RX_STATUS_REG,
2235 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2236 FH_TSSR_TX_STATUS_REG,
2237 FH_TSSR_TX_ERROR_REG
2239 #ifdef CONFIG_IWLWIFI_DEBUG
2241 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2242 *buf = kmalloc(bufsz, GFP_KERNEL);
2245 pos += scnprintf(*buf + pos, bufsz - pos,
2246 "FH register values:\n");
2247 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2248 pos += scnprintf(*buf + pos, bufsz - pos,
2250 get_fh_string(fh_tbl[i]),
2251 iwl_read_direct32(priv, fh_tbl[i]));
2256 IWL_ERR(priv, "FH register values:\n");
2257 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2258 IWL_ERR(priv, " %34s: 0X%08x\n",
2259 get_fh_string(fh_tbl[i]),
2260 iwl_read_direct32(priv, fh_tbl[i]));
2265 /* notification wait support */
2266 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2267 struct iwl_notification_wait *wait_entry,
2269 void (*fn)(struct iwl_priv *priv,
2270 struct iwl_rx_packet *pkt,
2274 wait_entry->fn = fn;
2275 wait_entry->fn_data = fn_data;
2276 wait_entry->cmd = cmd;
2277 wait_entry->triggered = false;
2278 wait_entry->aborted = false;
2280 spin_lock_bh(&priv->_agn.notif_wait_lock);
2281 list_add(&wait_entry->list, &priv->_agn.notif_waits);
2282 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2285 int iwlagn_wait_notification(struct iwl_priv *priv,
2286 struct iwl_notification_wait *wait_entry,
2287 unsigned long timeout)
2291 ret = wait_event_timeout(priv->_agn.notif_waitq,
2292 wait_entry->triggered || wait_entry->aborted,
2295 spin_lock_bh(&priv->_agn.notif_wait_lock);
2296 list_del(&wait_entry->list);
2297 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2299 if (wait_entry->aborted)
2302 /* return value is always >= 0 */
2308 void iwlagn_remove_notification(struct iwl_priv *priv,
2309 struct iwl_notification_wait *wait_entry)
2311 spin_lock_bh(&priv->_agn.notif_wait_lock);
2312 list_del(&wait_entry->list);
2313 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2316 int iwlagn_start_device(struct iwl_priv *priv)
2320 if (iwl_prepare_card_hw(priv)) {
2321 IWL_WARN(priv, "Exit HW not ready\n");
2325 /* If platform's RF_KILL switch is NOT set to KILL */
2326 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2327 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2329 set_bit(STATUS_RF_KILL_HW, &priv->status);
2331 if (iwl_is_rfkill(priv)) {
2332 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2333 iwl_enable_interrupts(priv);
2337 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2339 ret = iwlagn_hw_nic_init(priv);
2341 IWL_ERR(priv, "Unable to init nic\n");
2345 /* make sure rfkill handshake bits are cleared */
2346 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2347 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2348 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2350 /* clear (again), then enable host interrupts */
2351 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2352 iwl_enable_interrupts(priv);
2354 /* really make sure rfkill handshake bits are cleared */
2355 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2356 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2361 void iwlagn_stop_device(struct iwl_priv *priv)
2363 unsigned long flags;
2365 /* stop and reset the on-board processor */
2366 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2368 /* tell the device to stop sending interrupts */
2369 spin_lock_irqsave(&priv->lock, flags);
2370 iwl_disable_interrupts(priv);
2371 spin_unlock_irqrestore(&priv->lock, flags);
2372 iwl_synchronize_irq(priv);
2374 /* device going down, Stop using ICT table */
2375 iwl_disable_ict(priv);
2378 * If a HW restart happens during firmware loading,
2379 * then the firmware loading might call this function
2380 * and later it might be called again due to the
2381 * restart. So don't process again if the device is
2384 if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
2385 iwlagn_txq_ctx_stop(priv);
2386 iwlagn_rxq_stop(priv);
2388 /* Power-down device's busmaster DMA clocks */
2389 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2393 /* Make sure (redundant) we've released our request to stay awake */
2394 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2396 /* Stop the device, and put it in low power state */