drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 /* Highest firmware API version supported */
  48 #define IWL5000_UCODE_API_MAX 1
  49 #define IWL5150_UCODE_API_MAX 1
  50
  51 /* Lowest firmware API version supported */
  52 #define IWL5000_UCODE_API_MIN 1
  53 #define IWL5150_UCODE_API_MIN 1
  54
  55 #define IWL5000_FW_PRE "iwlwifi-5000-"
  56 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  57 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  58
  59 #define IWL5150_FW_PRE "iwlwifi-5150-"
  60 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  61 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  62
  63 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  64         IWL_TX_FIFO_AC3,
  65         IWL_TX_FIFO_AC2,
  66         IWL_TX_FIFO_AC1,
  67         IWL_TX_FIFO_AC0,
  68         IWL50_CMD_FIFO_NUM,
  69         IWL_TX_FIFO_HCCA_1,
  70         IWL_TX_FIFO_HCCA_2
  71 };
  72
  73 /* FIXME: same implementation as 4965 */
  74 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  75 {
  76         unsigned long flags;
  77
  78         spin_lock_irqsave(&priv->lock, flags);
  79
  80         /* set stop master bit */
  81         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  82
  83         iwl_poll_direct_bit(priv, CSR_RESET,
  84                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  85
  86         spin_unlock_irqrestore(&priv->lock, flags);
  87         IWL_DEBUG_INFO("stop master\n");
  88
  89         return 0;
  90 }
  91
  92
  93 static int iwl5000_apm_init(struct iwl_priv *priv)
  94 {
  95         int ret = 0;
  96
  97         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  98                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  99
 100         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 101         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 102                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 103
 104         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 105         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 106
 107         /* enable HAP INTA to move device L1a -> L0s */
 108         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 109                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 110
 111         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 112
 113         /* set "initialization complete" bit to move adapter
 114          * D0U* --> D0A* state */
 115         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 116
 117         /* wait for clock stabilization */
 118         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 119                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 120         if (ret < 0) {
 121                 IWL_DEBUG_INFO("Failed to init the card\n");
 122                 return ret;
 123         }
 124
 125         ret = iwl_grab_nic_access(priv);
 126         if (ret)
 127                 return ret;
 128
 129         /* enable DMA */
 130         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 131
 132         udelay(20);
 133
 134         /* disable L1-Active */
 135         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 136                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 137
 138         iwl_release_nic_access(priv);
 139
 140         return ret;
 141 }
 142
 143 /* FIXME: this is identical to 4965 */
 144 static void iwl5000_apm_stop(struct iwl_priv *priv)
 145 {
 146         unsigned long flags;
 147
 148         iwl5000_apm_stop_master(priv);
 149
 150         spin_lock_irqsave(&priv->lock, flags);
 151
 152         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 153
 154         udelay(10);
 155
 156         /* clear "init complete"  move adapter D0A* --> D0U state */
 157         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 158
 159         spin_unlock_irqrestore(&priv->lock, flags);
 160 }
 161
 162
 163 static int iwl5000_apm_reset(struct iwl_priv *priv)
 164 {
 165         int ret = 0;
 166         unsigned long flags;
 167
 168         iwl5000_apm_stop_master(priv);
 169
 170         spin_lock_irqsave(&priv->lock, flags);
 171
 172         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 173
 174         udelay(10);
 175
 176
 177         /* FIXME: put here L1A -L0S w/a */
 178
 179         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 180
 181         /* set "initialization complete" bit to move adapter
 182          * D0U* --> D0A* state */
 183         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 184
 185         /* wait for clock stabilization */
 186         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 187                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 188         if (ret < 0) {
 189                 IWL_DEBUG_INFO("Failed to init the card\n");
 190                 goto out;
 191         }
 192
 193         ret = iwl_grab_nic_access(priv);
 194         if (ret)
 195                 goto out;
 196
 197         /* enable DMA */
 198         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 199
 200         udelay(20);
 201
 202         /* disable L1-Active */
 203         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 204                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 205
 206         iwl_release_nic_access(priv);
 207
 208 out:
 209         spin_unlock_irqrestore(&priv->lock, flags);
 210
 211         return ret;
 212 }
 213
 214
 215 static void iwl5000_nic_config(struct iwl_priv *priv)
 216 {
 217         unsigned long flags;
 218         u16 radio_cfg;
 219         u16 link;
 220
 221         spin_lock_irqsave(&priv->lock, flags);
 222
 223         pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
 224
 225         /* L1 is enabled by BIOS */
 226         if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 227                 /* disable L0S disabled L1A enabled */
 228                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 229         else
 230                 /* L0S enabled L1A disabled */
 231                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 232
 233         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 234
 235         /* write radio config values to register */
 236         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 237                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 238                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 239                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 240                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 241
 242         /* set CSR_HW_CONFIG_REG for uCode use */
 243         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 244                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 245                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 246
 247         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 248          * (PCIe power is lost before PERST# is asserted),
 249          * causing ME FW to lose ownership and not being able to obtain it back.
 250          */
 251         iwl_grab_nic_access(priv);
 252         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 253                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 254                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 255         iwl_release_nic_access(priv);
 256
 257         spin_unlock_irqrestore(&priv->lock, flags);
 258 }
 259
 260
 261
 262 /*
 263  * EEPROM
 264  */
 265 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 266 {
 267         u16 offset = 0;
 268
 269         if ((address & INDIRECT_ADDRESS) == 0)
 270                 return address;
 271
 272         switch (address & INDIRECT_TYPE_MSK) {
 273         case INDIRECT_HOST:
 274                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 275                 break;
 276         case INDIRECT_GENERAL:
 277                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 278                 break;
 279         case INDIRECT_REGULATORY:
 280                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 281                 break;
 282         case INDIRECT_CALIBRATION:
 283                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 284                 break;
 285         case INDIRECT_PROCESS_ADJST:
 286                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 287                 break;
 288         case INDIRECT_OTHERS:
 289                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 290                 break;
 291         default:
 292                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 293                 address & INDIRECT_TYPE_MSK);
 294                 break;
 295         }
 296
 297         /* translate the offset from words to byte */
 298         return (address & ADDRESS_MSK) + (offset << 1);
 299 }
 300
 301 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 302 {
 303         struct iwl_eeprom_calib_hdr {
 304                 u8 version;
 305                 u8 pa_type;
 306                 u16 voltage;
 307         } *hdr;
 308
 309         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 310                                                         EEPROM_5000_CALIB_ALL);
 311         return hdr->version;
 312
 313 }
 314
 315 static void iwl5000_gain_computation(struct iwl_priv *priv,
 316                 u32 average_noise[NUM_RX_CHAINS],
 317                 u16 min_average_noise_antenna_i,
 318                 u32 min_average_noise)
 319 {
 320         int i;
 321         s32 delta_g;
 322         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 323
 324         /* Find Gain Code for the antennas B and C */
 325         for (i = 1; i < NUM_RX_CHAINS; i++) {
 326                 if ((data->disconn_array[i])) {
 327                         data->delta_gain_code[i] = 0;
 328                         continue;
 329                 }
 330                 delta_g = (1000 * ((s32)average_noise[0] -
 331                         (s32)average_noise[i])) / 1500;
 332                 /* bound gain by 2 bits value max, 3rd bit is sign */
 333                 data->delta_gain_code[i] =
 334                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 335
 336                 if (delta_g < 0)
 337                         /* set negative sign */
 338                         data->delta_gain_code[i] |= (1 << 2);
 339         }
 340
 341         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 342                         data->delta_gain_code[1], data->delta_gain_code[2]);
 343
 344         if (!data->radio_write) {
 345                 struct iwl_calib_chain_noise_gain_cmd cmd;
 346
 347                 memset(&cmd, 0, sizeof(cmd));
 348
 349                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 350                 cmd.hdr.first_group = 0;
 351                 cmd.hdr.groups_num = 1;
 352                 cmd.hdr.data_valid = 1;
 353                 cmd.delta_gain_1 = data->delta_gain_code[1];
 354                 cmd.delta_gain_2 = data->delta_gain_code[2];
 355                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 356                         sizeof(cmd), &cmd, NULL);
 357
 358                 data->radio_write = 1;
 359                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 360         }
 361
 362         data->chain_noise_a = 0;
 363         data->chain_noise_b = 0;
 364         data->chain_noise_c = 0;
 365         data->chain_signal_a = 0;
 366         data->chain_signal_b = 0;
 367         data->chain_signal_c = 0;
 368         data->beacon_count = 0;
 369 }
 370
 371 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 372 {
 373         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 374         int ret;
 375
 376         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 377                 struct iwl_calib_chain_noise_reset_cmd cmd;
 378                 memset(&cmd, 0, sizeof(cmd));
 379
 380                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 381                 cmd.hdr.first_group = 0;
 382                 cmd.hdr.groups_num = 1;
 383                 cmd.hdr.data_valid = 1;
 384                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 385                                         sizeof(cmd), &cmd);
 386                 if (ret)
 387                         IWL_ERR(priv,
 388                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 389                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 390                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 391         }
 392 }
 393
 394 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 395                         __le32 *tx_flags)
 396 {
 397         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 398             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 399                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 400         else
 401                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 402 }
 403
 404 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 405         .min_nrg_cck = 95,
 406         .max_nrg_cck = 0,
 407         .auto_corr_min_ofdm = 90,
 408         .auto_corr_min_ofdm_mrc = 170,
 409         .auto_corr_min_ofdm_x1 = 120,
 410         .auto_corr_min_ofdm_mrc_x1 = 240,
 411
 412         .auto_corr_max_ofdm = 120,
 413         .auto_corr_max_ofdm_mrc = 210,
 414         .auto_corr_max_ofdm_x1 = 155,
 415         .auto_corr_max_ofdm_mrc_x1 = 290,
 416
 417         .auto_corr_min_cck = 125,
 418         .auto_corr_max_cck = 200,
 419         .auto_corr_min_cck_mrc = 170,
 420         .auto_corr_max_cck_mrc = 400,
 421         .nrg_th_cck = 95,
 422         .nrg_th_ofdm = 95,
 423 };
 424
 425 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 426                                            size_t offset)
 427 {
 428         u32 address = eeprom_indirect_address(priv, offset);
 429         BUG_ON(address >= priv->cfg->eeprom_size);
 430         return &priv->eeprom[address];
 431 }
 432
 433 static s32 iwl5150_get_ct_threshold(struct iwl_priv *priv)
 434 {
 435         const s32 volt2temp_coef = -5;
 436         u16 *temp_calib = (u16 *)iwl_eeprom_query_addr(priv,
 437                                                 EEPROM_5000_TEMPERATURE);
 438         /* offset =  temperate -  voltage / coef */
 439         s32 offset = temp_calib[0] - temp_calib[1] / volt2temp_coef;
 440         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - offset;
 441         return threshold * volt2temp_coef;
 442 }
 443
 444 /*
 445  *  Calibration
 446  */
 447 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 448 {
 449         struct iwl_calib_xtal_freq_cmd cmd;
 450         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 451
 452         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 453         cmd.hdr.first_group = 0;
 454         cmd.hdr.groups_num = 1;
 455         cmd.hdr.data_valid = 1;
 456         cmd.cap_pin1 = (u8)xtal_calib[0];
 457         cmd.cap_pin2 = (u8)xtal_calib[1];
 458         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 459                              (u8 *)&cmd, sizeof(cmd));
 460 }
 461
 462 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 463 {
 464         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 465         struct iwl_host_cmd cmd = {
 466                 .id = CALIBRATION_CFG_CMD,
 467                 .len = sizeof(struct iwl_calib_cfg_cmd),
 468                 .data = &calib_cfg_cmd,
 469         };
 470
 471         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 472         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 473         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 474         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 475         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 476
 477         return iwl_send_cmd(priv, &cmd);
 478 }
 479
 480 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 481                              struct iwl_rx_mem_buffer *rxb)
 482 {
 483         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 484         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 485         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 486         int index;
 487
 488         /* reduce the size of the length field itself */
 489         len -= 4;
 490
 491         /* Define the order in which the results will be sent to the runtime
 492          * uCode. iwl_send_calib_results sends them in a row according to their
 493          * index. We sort them here */
 494         switch (hdr->op_code) {
 495         case IWL_PHY_CALIBRATE_DC_CMD:
 496                 index = IWL_CALIB_DC;
 497                 break;
 498         case IWL_PHY_CALIBRATE_LO_CMD:
 499                 index = IWL_CALIB_LO;
 500                 break;
 501         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 502                 index = IWL_CALIB_TX_IQ;
 503                 break;
 504         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 505                 index = IWL_CALIB_TX_IQ_PERD;
 506                 break;
 507         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 508                 index = IWL_CALIB_BASE_BAND;
 509                 break;
 510         default:
 511                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 512                           hdr->op_code);
 513                 return;
 514         }
 515         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 516 }
 517
 518 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 519                                struct iwl_rx_mem_buffer *rxb)
 520 {
 521         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 522         queue_work(priv->workqueue, &priv->restart);
 523 }
 524
 525 /*
 526  * ucode
 527  */
 528 static int iwl5000_load_section(struct iwl_priv *priv,
 529                                 struct fw_desc *image,
 530                                 u32 dst_addr)
 531 {
 532         int ret = 0;
 533         unsigned long flags;
 534
 535         dma_addr_t phy_addr = image->p_addr;
 536         u32 byte_cnt = image->len;
 537
 538         spin_lock_irqsave(&priv->lock, flags);
 539         ret = iwl_grab_nic_access(priv);
 540         if (ret) {
 541                 spin_unlock_irqrestore(&priv->lock, flags);
 542                 return ret;
 543         }
 544
 545         iwl_write_direct32(priv,
 546                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 547                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 548
 549         iwl_write_direct32(priv,
 550                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 551
 552         iwl_write_direct32(priv,
 553                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 554                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 555
 556         iwl_write_direct32(priv,
 557                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 558                 (iwl_get_dma_hi_addr(phy_addr)
 559                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 560
 561         iwl_write_direct32(priv,
 562                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 563                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 564                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 565                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 566
 567         iwl_write_direct32(priv,
 568                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 569                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 570                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 571                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 572
 573         iwl_release_nic_access(priv);
 574         spin_unlock_irqrestore(&priv->lock, flags);
 575         return 0;
 576 }
 577
 578 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 579                 struct fw_desc *inst_image,
 580                 struct fw_desc *data_image)
 581 {
 582         int ret = 0;
 583
 584         ret = iwl5000_load_section(priv, inst_image,
 585                                    IWL50_RTC_INST_LOWER_BOUND);
 586         if (ret)
 587                 return ret;
 588
 589         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 590         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 591                                         priv->ucode_write_complete, 5 * HZ);
 592         if (ret == -ERESTARTSYS) {
 593                 IWL_ERR(priv, "Could not load the INST uCode section due "
 594                         "to interrupt\n");
 595                 return ret;
 596         }
 597         if (!ret) {
 598                 IWL_ERR(priv, "Could not load the INST uCode section\n");
 599                 return -ETIMEDOUT;
 600         }
 601
 602         priv->ucode_write_complete = 0;
 603
 604         ret = iwl5000_load_section(
 605                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
 606         if (ret)
 607                 return ret;
 608
 609         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 610
 611         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 612                                 priv->ucode_write_complete, 5 * HZ);
 613         if (ret == -ERESTARTSYS) {
 614                 IWL_ERR(priv, "Could not load the INST uCode section due "
 615                         "to interrupt\n");
 616                 return ret;
 617         } else if (!ret) {
 618                 IWL_ERR(priv, "Could not load the DATA uCode section\n");
 619                 return -ETIMEDOUT;
 620         } else
 621                 ret = 0;
 622
 623         priv->ucode_write_complete = 0;
 624
 625         return ret;
 626 }
 627
 628 static int iwl5000_load_ucode(struct iwl_priv *priv)
 629 {
 630         int ret = 0;
 631
 632         /* check whether init ucode should be loaded, or rather runtime ucode */
 633         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 634                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 635                 ret = iwl5000_load_given_ucode(priv,
 636                         &priv->ucode_init, &priv->ucode_init_data);
 637                 if (!ret) {
 638                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 639                         priv->ucode_type = UCODE_INIT;
 640                 }
 641         } else {
 642                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 643                         "Loading runtime ucode...\n");
 644                 ret = iwl5000_load_given_ucode(priv,
 645                         &priv->ucode_code, &priv->ucode_data);
 646                 if (!ret) {
 647                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 648                         priv->ucode_type = UCODE_RT;
 649                 }
 650         }
 651
 652         return ret;
 653 }
 654
 655 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 656 {
 657         int ret = 0;
 658
 659         /* Check alive response for "valid" sign from uCode */
 660         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 661                 /* We had an error bringing up the hardware, so take it
 662                  * all the way back down so we can try again */
 663                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 664                 goto restart;
 665         }
 666
 667         /* initialize uCode was loaded... verify inst image.
 668          * This is a paranoid check, because we would not have gotten the
 669          * "initialize" alive if code weren't properly loaded.  */
 670         if (iwl_verify_ucode(priv)) {
 671                 /* Runtime instruction load was bad;
 672                  * take it all the way back down so we can try again */
 673                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 674                 goto restart;
 675         }
 676
 677         iwl_clear_stations_table(priv);
 678         ret = priv->cfg->ops->lib->alive_notify(priv);
 679         if (ret) {
 680                 IWL_WARN(priv,
 681                         "Could not complete ALIVE transition: %d\n", ret);
 682                 goto restart;
 683         }
 684
 685         iwl5000_send_calib_cfg(priv);
 686         return;
 687
 688 restart:
 689         /* real restart (first load init_ucode) */
 690         queue_work(priv->workqueue, &priv->restart);
 691 }
 692
 693 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 694                                 int txq_id, u32 index)
 695 {
 696         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 697                         (index & 0xff) | (txq_id << 8));
 698         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 699 }
 700
 701 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 702                                         struct iwl_tx_queue *txq,
 703                                         int tx_fifo_id, int scd_retry)
 704 {
 705         int txq_id = txq->q.id;
 706         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 707
 708         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 709                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 710                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 711                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 712                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 713
 714         txq->sched_retry = scd_retry;
 715
 716         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 717                        active ? "Activate" : "Deactivate",
 718                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 719 }
 720
 721 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 722 {
 723         struct iwl_wimax_coex_cmd coex_cmd;
 724
 725         memset(&coex_cmd, 0, sizeof(coex_cmd));
 726
 727         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 728                                 sizeof(coex_cmd), &coex_cmd);
 729 }
 730
 731 static int iwl5000_alive_notify(struct iwl_priv *priv)
 732 {
 733         u32 a;
 734         unsigned long flags;
 735         int ret;
 736         int i, chan;
 737         u32 reg_val;
 738
 739         spin_lock_irqsave(&priv->lock, flags);
 740
 741         ret = iwl_grab_nic_access(priv);
 742         if (ret) {
 743                 spin_unlock_irqrestore(&priv->lock, flags);
 744                 return ret;
 745         }
 746
 747         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 748         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 749         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 750                 a += 4)
 751                 iwl_write_targ_mem(priv, a, 0);
 752         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 753                 a += 4)
 754                 iwl_write_targ_mem(priv, a, 0);
 755         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 756                 iwl_write_targ_mem(priv, a, 0);
 757
 758         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 759                        priv->scd_bc_tbls.dma >> 10);
 760
 761         /* Enable DMA channel */
 762         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 763                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 764                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 765                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 766
 767         /* Update FH chicken bits */
 768         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 769         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 770                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 771
 772         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 773                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 774         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 775
 776         /* initiate the queues */
 777         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 778                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 779                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 780                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 781                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 782                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 783                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 784                                 sizeof(u32),
 785                                 ((SCD_WIN_SIZE <<
 786                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 787                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 788                                 ((SCD_FRAME_LIMIT <<
 789                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 790                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 791         }
 792
 793         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 794                         IWL_MASK(0, priv->hw_params.max_txq_num));
 795
 796         /* Activate all Tx DMA/FIFO channels */
 797         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 798
 799         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 800
 801         /* map qos queues to fifos one-to-one */
 802         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 803                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 804                 iwl_txq_ctx_activate(priv, i);
 805                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 806         }
 807         /* TODO - need to initialize those FIFOs inside the loop above,
 808          * not only mark them as active */
 809         iwl_txq_ctx_activate(priv, 4);
 810         iwl_txq_ctx_activate(priv, 7);
 811         iwl_txq_ctx_activate(priv, 8);
 812         iwl_txq_ctx_activate(priv, 9);
 813
 814         iwl_release_nic_access(priv);
 815         spin_unlock_irqrestore(&priv->lock, flags);
 816
 817
 818         iwl5000_send_wimax_coex(priv);
 819
 820         iwl5000_set_Xtal_calib(priv);
 821         iwl_send_calib_results(priv);
 822
 823         return 0;
 824 }
 825
 826 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 827 {
 828         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 829             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 830                 IWL_ERR(priv,
 831                         "invalid queues_num, should be between %d and %d\n",
 832                         IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 833                 return -EINVAL;
 834         }
 835
 836         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 837         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 838         priv->hw_params.scd_bc_tbls_size =
 839                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 840         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 841         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 842         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 843         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 844         priv->hw_params.max_bsm_size = 0;
 845         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 846                                         BIT(IEEE80211_BAND_5GHZ);
 847         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 848
 849         priv->hw_params.sens = &iwl5000_sensitivity;
 850
 851         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 852         case CSR_HW_REV_TYPE_5100:
 853                 priv->hw_params.tx_chains_num = 1;
 854                 priv->hw_params.rx_chains_num = 2;
 855                 priv->hw_params.valid_tx_ant = ANT_B;
 856                 priv->hw_params.valid_rx_ant = ANT_AB;
 857                 break;
 858         case CSR_HW_REV_TYPE_5150:
 859                 priv->hw_params.tx_chains_num = 1;
 860                 priv->hw_params.rx_chains_num = 2;
 861                 priv->hw_params.valid_tx_ant = ANT_A;
 862                 priv->hw_params.valid_rx_ant = ANT_AB;
 863                 break;
 864         case CSR_HW_REV_TYPE_5300:
 865         case CSR_HW_REV_TYPE_5350:
 866                 priv->hw_params.tx_chains_num = 3;
 867                 priv->hw_params.rx_chains_num = 3;
 868                 priv->hw_params.valid_tx_ant = ANT_ABC;
 869                 priv->hw_params.valid_rx_ant = ANT_ABC;
 870                 break;
 871         }
 872
 873         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 874         case CSR_HW_REV_TYPE_5100:
 875         case CSR_HW_REV_TYPE_5300:
 876         case CSR_HW_REV_TYPE_5350:
 877                 /* 5X00 and 5350 wants in Celsius */
 878                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 879                 break;
 880         case CSR_HW_REV_TYPE_5150:
 881                 /* 5150 wants in Kelvin */
 882                 priv->hw_params.ct_kill_threshold =
 883                                 iwl5150_get_ct_threshold(priv);
 884                 break;
 885         }
 886
 887         /* Set initial calibration set */
 888         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 889         case CSR_HW_REV_TYPE_5100:
 890         case CSR_HW_REV_TYPE_5300:
 891         case CSR_HW_REV_TYPE_5350:
 892                 priv->hw_params.calib_init_cfg =
 893                         BIT(IWL_CALIB_XTAL)             |
 894                         BIT(IWL_CALIB_LO)               |
 895                         BIT(IWL_CALIB_TX_IQ)            |
 896                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 897                         BIT(IWL_CALIB_BASE_BAND);
 898                 break;
 899         case CSR_HW_REV_TYPE_5150:
 900                 priv->hw_params.calib_init_cfg =
 901                         BIT(IWL_CALIB_DC)               |
 902                         BIT(IWL_CALIB_LO)               |
 903                         BIT(IWL_CALIB_TX_IQ)            |
 904                         BIT(IWL_CALIB_BASE_BAND);
 905
 906                 break;
 907         }
 908
 909
 910         return 0;
 911 }
 912
 913 /**
 914  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 915  */
 916 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 917                                             struct iwl_tx_queue *txq,
 918                                             u16 byte_cnt)
 919 {
 920         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 921         int write_ptr = txq->q.write_ptr;
 922         int txq_id = txq->q.id;
 923         u8 sec_ctl = 0;
 924         u8 sta_id = 0;
 925         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 926         __le16 bc_ent;
 927
 928         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 929
 930         if (txq_id != IWL_CMD_QUEUE_NUM) {
 931                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 932                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 933
 934                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 935                 case TX_CMD_SEC_CCM:
 936                         len += CCMP_MIC_LEN;
 937                         break;
 938                 case TX_CMD_SEC_TKIP:
 939                         len += TKIP_ICV_LEN;
 940                         break;
 941                 case TX_CMD_SEC_WEP:
 942                         len += WEP_IV_LEN + WEP_ICV_LEN;
 943                         break;
 944                 }
 945         }
 946
 947         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 948
 949         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 950
 951         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 952                 scd_bc_tbl[txq_id].
 953                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 954 }
 955
 956 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 957                                            struct iwl_tx_queue *txq)
 958 {
 959         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 960         int txq_id = txq->q.id;
 961         int read_ptr = txq->q.read_ptr;
 962         u8 sta_id = 0;
 963         __le16 bc_ent;
 964
 965         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 966
 967         if (txq_id != IWL_CMD_QUEUE_NUM)
 968                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 969
 970         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 971         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 972
 973         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 974                 scd_bc_tbl[txq_id].
 975                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 976 }
 977
 978 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 979                                         u16 txq_id)
 980 {
 981         u32 tbl_dw_addr;
 982         u32 tbl_dw;
 983         u16 scd_q2ratid;
 984
 985         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 986
 987         tbl_dw_addr = priv->scd_base_addr +
 988                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 989
 990         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 991
 992         if (txq_id & 0x1)
 993                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 994         else
 995                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 996
 997         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 998
 999         return 0;
1000 }
1001 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1002 {
1003         /* Simply stop the queue, but don't change any configuration;
1004          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1005         iwl_write_prph(priv,
1006                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1007                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1008                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1009 }
1010
1011 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1012                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1013 {
1014         unsigned long flags;
1015         int ret;
1016         u16 ra_tid;
1017
1018         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1019             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1020                 IWL_WARN(priv,
1021                         "queue number out of range: %d, must be %d to %d\n",
1022                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1023                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1024                 return -EINVAL;
1025         }
1026
1027         ra_tid = BUILD_RAxTID(sta_id, tid);
1028
1029         /* Modify device's station table to Tx this TID */
1030         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1031
1032         spin_lock_irqsave(&priv->lock, flags);
1033         ret = iwl_grab_nic_access(priv);
1034         if (ret) {
1035                 spin_unlock_irqrestore(&priv->lock, flags);
1036                 return ret;
1037         }
1038
1039         /* Stop this Tx queue before configuring it */
1040         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1041
1042         /* Map receiver-address / traffic-ID to this queue */
1043         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1044
1045         /* Set this queue as a chain-building queue */
1046         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1047
1048         /* enable aggregations for the queue */
1049         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1050
1051         /* Place first TFD at index corresponding to start sequence number.
1052          * Assumes that ssn_idx is valid (!= 0xFFF) */
1053         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1054         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1055         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1056
1057         /* Set up Tx window size and frame limit for this queue */
1058         iwl_write_targ_mem(priv, priv->scd_base_addr +
1059                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1060                         sizeof(u32),
1061                         ((SCD_WIN_SIZE <<
1062                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1063                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1064                         ((SCD_FRAME_LIMIT <<
1065                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1066                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1067
1068         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1069
1070         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1071         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1072
1073         iwl_release_nic_access(priv);
1074         spin_unlock_irqrestore(&priv->lock, flags);
1075
1076         return 0;
1077 }
1078
1079 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1080                                    u16 ssn_idx, u8 tx_fifo)
1081 {
1082         int ret;
1083
1084         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1085             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1086                 IWL_WARN(priv,
1087                         "queue number out of range: %d, must be %d to %d\n",
1088                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1089                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1090                 return -EINVAL;
1091         }
1092
1093         ret = iwl_grab_nic_access(priv);
1094         if (ret)
1095                 return ret;
1096
1097         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1098
1099         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1100
1101         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1102         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1103         /* supposes that ssn_idx is valid (!= 0xFFF) */
1104         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1105
1106         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1107         iwl_txq_ctx_deactivate(priv, txq_id);
1108         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1109
1110         iwl_release_nic_access(priv);
1111
1112         return 0;
1113 }
1114
1115 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1116 {
1117         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1118         memcpy(data, cmd, size);
1119         return size;
1120 }
1121
1122
1123 /*
1124  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1125  * must be called under priv->lock and mac access
1126  */
1127 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1128 {
1129         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1130 }
1131
1132
1133 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1134 {
1135         return le32_to_cpup((__le32 *)&tx_resp->status +
1136                             tx_resp->frame_count) & MAX_SN;
1137 }
1138
1139 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1140                                       struct iwl_ht_agg *agg,
1141                                       struct iwl5000_tx_resp *tx_resp,
1142                                       int txq_id, u16 start_idx)
1143 {
1144         u16 status;
1145         struct agg_tx_status *frame_status = &tx_resp->status;
1146         struct ieee80211_tx_info *info = NULL;
1147         struct ieee80211_hdr *hdr = NULL;
1148         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1149         int i, sh, idx;
1150         u16 seq;
1151
1152         if (agg->wait_for_ba)
1153                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1154
1155         agg->frame_count = tx_resp->frame_count;
1156         agg->start_idx = start_idx;
1157         agg->rate_n_flags = rate_n_flags;
1158         agg->bitmap = 0;
1159
1160         /* # frames attempted by Tx command */
1161         if (agg->frame_count == 1) {
1162                 /* Only one frame was attempted; no block-ack will arrive */
1163                 status = le16_to_cpu(frame_status[0].status);
1164                 idx = start_idx;
1165
1166                 /* FIXME: code repetition */
1167                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1168                                    agg->frame_count, agg->start_idx, idx);
1169
1170                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1171                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1172                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1173                 info->flags |= iwl_is_tx_success(status) ?
1174                                         IEEE80211_TX_STAT_ACK : 0;
1175                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1176
1177                 /* FIXME: code repetition end */
1178
1179                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1180                                     status & 0xff, tx_resp->failure_frame);
1181                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1182
1183                 agg->wait_for_ba = 0;
1184         } else {
1185                 /* Two or more frames were attempted; expect block-ack */
1186                 u64 bitmap = 0;
1187                 int start = agg->start_idx;
1188
1189                 /* Construct bit-map of pending frames within Tx window */
1190                 for (i = 0; i < agg->frame_count; i++) {
1191                         u16 sc;
1192                         status = le16_to_cpu(frame_status[i].status);
1193                         seq  = le16_to_cpu(frame_status[i].sequence);
1194                         idx = SEQ_TO_INDEX(seq);
1195                         txq_id = SEQ_TO_QUEUE(seq);
1196
1197                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1198                                       AGG_TX_STATE_ABORT_MSK))
1199                                 continue;
1200
1201                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1202                                            agg->frame_count, txq_id, idx);
1203
1204                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1205
1206                         sc = le16_to_cpu(hdr->seq_ctrl);
1207                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1208                                 IWL_ERR(priv,
1209                                         "BUG_ON idx doesn't match seq control"
1210                                         " idx=%d, seq_idx=%d, seq=%d\n",
1211                                           idx, SEQ_TO_SN(sc),
1212                                           hdr->seq_ctrl);
1213                                 return -1;
1214                         }
1215
1216                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1217                                            i, idx, SEQ_TO_SN(sc));
1218
1219                         sh = idx - start;
1220                         if (sh > 64) {
1221                                 sh = (start - idx) + 0xff;
1222                                 bitmap = bitmap << sh;
1223                                 sh = 0;
1224                                 start = idx;
1225                         } else if (sh < -64)
1226                                 sh  = 0xff - (start - idx);
1227                         else if (sh < 0) {
1228                                 sh = start - idx;
1229                                 start = idx;
1230                                 bitmap = bitmap << sh;
1231                                 sh = 0;
1232                         }
1233                         bitmap |= 1ULL << sh;
1234                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1235                                            start, (unsigned long long)bitmap);
1236                 }
1237
1238                 agg->bitmap = bitmap;
1239                 agg->start_idx = start;
1240                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1241                                    agg->frame_count, agg->start_idx,
1242                                    (unsigned long long)agg->bitmap);
1243
1244                 if (bitmap)
1245                         agg->wait_for_ba = 1;
1246         }
1247         return 0;
1248 }
1249
1250 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1251                                 struct iwl_rx_mem_buffer *rxb)
1252 {
1253         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1254         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1255         int txq_id = SEQ_TO_QUEUE(sequence);
1256         int index = SEQ_TO_INDEX(sequence);
1257         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1258         struct ieee80211_tx_info *info;
1259         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1260         u32  status = le16_to_cpu(tx_resp->status.status);
1261         int tid;
1262         int sta_id;
1263         int freed;
1264
1265         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1266                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1267                           "is out of range [0-%d] %d %d\n", txq_id,
1268                           index, txq->q.n_bd, txq->q.write_ptr,
1269                           txq->q.read_ptr);
1270                 return;
1271         }
1272
1273         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1274         memset(&info->status, 0, sizeof(info->status));
1275
1276         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1277         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1278
1279         if (txq->sched_retry) {
1280                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1281                 struct iwl_ht_agg *agg = NULL;
1282
1283                 agg = &priv->stations[sta_id].tid[tid].agg;
1284
1285                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1286
1287                 /* check if BAR is needed */
1288                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1289                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1290
1291                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1292                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1293                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1294                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1295                                         scd_ssn , index, txq_id, txq->swq_id);
1296
1297                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1298                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1299
1300                         if (priv->mac80211_registered &&
1301                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1302                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1303                                 if (agg->state == IWL_AGG_OFF)
1304                                         ieee80211_wake_queue(priv->hw, txq_id);
1305                                 else
1306                                         ieee80211_wake_queue(priv->hw,
1307                                                              txq->swq_id);
1308                         }
1309                 }
1310         } else {
1311                 BUG_ON(txq_id != txq->swq_id);
1312
1313                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1314                 info->flags |= iwl_is_tx_success(status) ?
1315                                         IEEE80211_TX_STAT_ACK : 0;
1316                 iwl_hwrate_to_tx_control(priv,
1317                                         le32_to_cpu(tx_resp->rate_n_flags),
1318                                         info);
1319
1320                 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1321                                    "0x%x retries %d\n",
1322                                    txq_id,
1323                                    iwl_get_tx_fail_reason(status), status,
1324                                    le32_to_cpu(tx_resp->rate_n_flags),
1325                                    tx_resp->failure_frame);
1326
1327                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1328                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1329                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1330
1331                 if (priv->mac80211_registered &&
1332                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1333                         ieee80211_wake_queue(priv->hw, txq_id);
1334         }
1335
1336         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1337                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1338
1339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1340                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1341 }
1342
1343 /* Currently 5000 is the superset of everything */
1344 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1345 {
1346         return len;
1347 }
1348
1349 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1350 {
1351         /* in 5000 the tx power calibration is done in uCode */
1352         priv->disable_tx_power_cal = 1;
1353 }
1354
1355 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1356 {
1357         /* init calibration handlers */
1358         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1359                                         iwl5000_rx_calib_result;
1360         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1361                                         iwl5000_rx_calib_complete;
1362         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1363 }
1364
1365
1366 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1367 {
1368         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1369                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1370 }
1371
1372 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1373 {
1374         int ret = 0;
1375         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1376         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1377         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1378
1379         if ((rxon1->flags == rxon2->flags) &&
1380             (rxon1->filter_flags == rxon2->filter_flags) &&
1381             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1382             (rxon1->ofdm_ht_single_stream_basic_rates ==
1383              rxon2->ofdm_ht_single_stream_basic_rates) &&
1384             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1385              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1386             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1387              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1388             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1389             (rxon1->rx_chain == rxon2->rx_chain) &&
1390             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1391                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1392                 return 0;
1393         }
1394
1395         rxon_assoc.flags = priv->staging_rxon.flags;
1396         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1397         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1398         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1399         rxon_assoc.reserved1 = 0;
1400         rxon_assoc.reserved2 = 0;
1401         rxon_assoc.reserved3 = 0;
1402         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1403             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1404         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1405             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1406         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1407         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1408                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1409         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1410
1411         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1412                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1413         if (ret)
1414                 return ret;
1415
1416         return ret;
1417 }
1418 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1419 {
1420         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1421
1422         /* half dBm need to multiply */
1423         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1424         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1425         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1426         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1427                                        sizeof(tx_power_cmd), &tx_power_cmd,
1428                                        NULL);
1429 }
1430
1431 static void iwl5000_temperature(struct iwl_priv *priv)
1432 {
1433         /* store temperature from statistics (in Celsius) */
1434         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1435 }
1436
1437 /* Calc max signal level (dBm) among 3 possible receivers */
1438 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1439                              struct iwl_rx_phy_res *rx_resp)
1440 {
1441         /* data from PHY/DSP regarding signal strength, etc.,
1442          *   contents are always there, not configurable by host
1443          */
1444         struct iwl5000_non_cfg_phy *ncphy =
1445                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1446         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1447         u8 agc;
1448
1449         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1450         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1451
1452         /* Find max rssi among 3 possible receivers.
1453          * These values are measured by the digital signal processor (DSP).
1454          * They should stay fairly constant even as the signal strength varies,
1455          *   if the radio's automatic gain control (AGC) is working right.
1456          * AGC value (see below) will provide the "interesting" info.
1457          */
1458         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1459         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1460         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1461         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1462         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1463
1464         max_rssi = max_t(u32, rssi_a, rssi_b);
1465         max_rssi = max_t(u32, max_rssi, rssi_c);
1466
1467         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1468                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1469
1470         /* dBm = max_rssi dB - agc dB - constant.
1471          * Higher AGC (higher radio gain) means lower signal. */
1472         return max_rssi - agc - IWL49_RSSI_OFFSET;
1473 }
1474
1475 static struct iwl_hcmd_ops iwl5000_hcmd = {
1476         .rxon_assoc = iwl5000_send_rxon_assoc,
1477 };
1478
1479 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1480         .get_hcmd_size = iwl5000_get_hcmd_size,
1481         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1482         .gain_computation = iwl5000_gain_computation,
1483         .chain_noise_reset = iwl5000_chain_noise_reset,
1484         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1485         .calc_rssi = iwl5000_calc_rssi,
1486 };
1487
1488 static struct iwl_lib_ops iwl5000_lib = {
1489         .set_hw_params = iwl5000_hw_set_hw_params,
1490         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1491         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1492         .txq_set_sched = iwl5000_txq_set_sched,
1493         .txq_agg_enable = iwl5000_txq_agg_enable,
1494         .txq_agg_disable = iwl5000_txq_agg_disable,
1495         .rx_handler_setup = iwl5000_rx_handler_setup,
1496         .setup_deferred_work = iwl5000_setup_deferred_work,
1497         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1498         .load_ucode = iwl5000_load_ucode,
1499         .init_alive_start = iwl5000_init_alive_start,
1500         .alive_notify = iwl5000_alive_notify,
1501         .send_tx_power = iwl5000_send_tx_power,
1502         .temperature = iwl5000_temperature,
1503         .update_chain_flags = iwl_update_chain_flags,
1504         .apm_ops = {
1505                 .init = iwl5000_apm_init,
1506                 .reset = iwl5000_apm_reset,
1507                 .stop = iwl5000_apm_stop,
1508                 .config = iwl5000_nic_config,
1509                 .set_pwr_src = iwl_set_pwr_src,
1510         },
1511         .eeprom_ops = {
1512                 .regulatory_bands = {
1513                         EEPROM_5000_REG_BAND_1_CHANNELS,
1514                         EEPROM_5000_REG_BAND_2_CHANNELS,
1515                         EEPROM_5000_REG_BAND_3_CHANNELS,
1516                         EEPROM_5000_REG_BAND_4_CHANNELS,
1517                         EEPROM_5000_REG_BAND_5_CHANNELS,
1518                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1519                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1520                 },
1521                 .verify_signature  = iwlcore_eeprom_verify_signature,
1522                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1523                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1524                 .calib_version  = iwl5000_eeprom_calib_version,
1525                 .query_addr = iwl5000_eeprom_query_addr,
1526         },
1527 };
1528
1529 static struct iwl_ops iwl5000_ops = {
1530         .lib = &iwl5000_lib,
1531         .hcmd = &iwl5000_hcmd,
1532         .utils = &iwl5000_hcmd_utils,
1533 };
1534
1535 static struct iwl_mod_params iwl50_mod_params = {
1536         .num_of_queues = IWL50_NUM_QUEUES,
1537         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1538         .amsdu_size_8K = 1,
1539         .restart_fw = 1,
1540         /* the rest are 0 by default */
1541 };
1542
1543
1544 struct iwl_cfg iwl5300_agn_cfg = {
1545         .name = "5300AGN",
1546         .fw_name_pre = IWL5000_FW_PRE,
1547         .ucode_api_max = IWL5000_UCODE_API_MAX,
1548         .ucode_api_min = IWL5000_UCODE_API_MIN,
1549         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1550         .ops = &iwl5000_ops,
1551         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1552         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1553         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1554         .mod_params = &iwl50_mod_params,
1555 };
1556
1557 struct iwl_cfg iwl5100_bg_cfg = {
1558         .name = "5100BG",
1559         .fw_name_pre = IWL5000_FW_PRE,
1560         .ucode_api_max = IWL5000_UCODE_API_MAX,
1561         .ucode_api_min = IWL5000_UCODE_API_MIN,
1562         .sku = IWL_SKU_G,
1563         .ops = &iwl5000_ops,
1564         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1565         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1566         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1567         .mod_params = &iwl50_mod_params,
1568 };
1569
1570 struct iwl_cfg iwl5100_abg_cfg = {
1571         .name = "5100ABG",
1572         .fw_name_pre = IWL5000_FW_PRE,
1573         .ucode_api_max = IWL5000_UCODE_API_MAX,
1574         .ucode_api_min = IWL5000_UCODE_API_MIN,
1575         .sku = IWL_SKU_A|IWL_SKU_G,
1576         .ops = &iwl5000_ops,
1577         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1578         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1579         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1580         .mod_params = &iwl50_mod_params,
1581 };
1582
1583 struct iwl_cfg iwl5100_agn_cfg = {
1584         .name = "5100AGN",
1585         .fw_name_pre = IWL5000_FW_PRE,
1586         .ucode_api_max = IWL5000_UCODE_API_MAX,
1587         .ucode_api_min = IWL5000_UCODE_API_MIN,
1588         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1589         .ops = &iwl5000_ops,
1590         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1591         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1592         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1593         .mod_params = &iwl50_mod_params,
1594 };
1595
1596 struct iwl_cfg iwl5350_agn_cfg = {
1597         .name = "5350AGN",
1598         .fw_name_pre = IWL5000_FW_PRE,
1599         .ucode_api_max = IWL5000_UCODE_API_MAX,
1600         .ucode_api_min = IWL5000_UCODE_API_MIN,
1601         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1602         .ops = &iwl5000_ops,
1603         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1604         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1605         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1606         .mod_params = &iwl50_mod_params,
1607 };
1608
1609 struct iwl_cfg iwl5150_agn_cfg = {
1610         .name = "5150AGN",
1611         .fw_name_pre = IWL5150_FW_PRE,
1612         .ucode_api_max = IWL5150_UCODE_API_MAX,
1613         .ucode_api_min = IWL5150_UCODE_API_MIN,
1614         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1615         .ops = &iwl5000_ops,
1616         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1617         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1618         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1619         .mod_params = &iwl50_mod_params,
1620 };
1621
1622 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1623 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1624
1625 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1626 MODULE_PARM_DESC(disable50,
1627                   "manually disable the 50XX radio (default 0 [radio on])");
1628 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1629 MODULE_PARM_DESC(swcrypto50,
1630                   "using software crypto engine (default 0 [hardware])\n");
1631 module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
1632 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1633 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1634 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1635 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1636 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1637 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1638 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1639 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1640 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");