drivers/net/wireless/iwlwifi/iwl-4965.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/wireless.h>
  37 #include <net/mac80211.h>
  38 #include <linux/etherdevice.h>
  39 #include <asm/unaligned.h>
  40
  41 #include "iwl-eeprom.h"
  42 #include "iwl-dev.h"
  43 #include "iwl-core.h"
  44 #include "iwl-io.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-calib.h"
  47
  48 /* module parameters */
  49 static struct iwl_mod_params iwl4965_mod_params = {
  50         .num_of_queues = IWL49_NUM_QUEUES,
  51         .enable_qos = 1,
  52         .amsdu_size_8K = 1,
  53         /* the rest are 0 by default */
  54 };
  55
  56 static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
  57
  58 #ifdef CONFIG_IWL4965_HT
  59
  60 static const u16 default_tid_to_tx_fifo[] = {
  61         IWL_TX_FIFO_AC1,
  62         IWL_TX_FIFO_AC0,
  63         IWL_TX_FIFO_AC0,
  64         IWL_TX_FIFO_AC1,
  65         IWL_TX_FIFO_AC2,
  66         IWL_TX_FIFO_AC2,
  67         IWL_TX_FIFO_AC3,
  68         IWL_TX_FIFO_AC3,
  69         IWL_TX_FIFO_NONE,
  70         IWL_TX_FIFO_NONE,
  71         IWL_TX_FIFO_NONE,
  72         IWL_TX_FIFO_NONE,
  73         IWL_TX_FIFO_NONE,
  74         IWL_TX_FIFO_NONE,
  75         IWL_TX_FIFO_NONE,
  76         IWL_TX_FIFO_NONE,
  77         IWL_TX_FIFO_AC3
  78 };
  79
  80 #endif  /*CONFIG_IWL4965_HT */
  81
  82 /* check contents of special bootstrap uCode SRAM */
  83 static int iwl4965_verify_bsm(struct iwl_priv *priv)
  84 {
  85         __le32 *image = priv->ucode_boot.v_addr;
  86         u32 len = priv->ucode_boot.len;
  87         u32 reg;
  88         u32 val;
  89
  90         IWL_DEBUG_INFO("Begin verify bsm\n");
  91
  92         /* verify BSM SRAM contents */
  93         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  94         for (reg = BSM_SRAM_LOWER_BOUND;
  95              reg < BSM_SRAM_LOWER_BOUND + len;
  96              reg += sizeof(u32), image++) {
  97                 val = iwl_read_prph(priv, reg);
  98                 if (val != le32_to_cpu(*image)) {
  99                         IWL_ERROR("BSM uCode verification failed at "
 100                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
 101                                   BSM_SRAM_LOWER_BOUND,
 102                                   reg - BSM_SRAM_LOWER_BOUND, len,
 103                                   val, le32_to_cpu(*image));
 104                         return -EIO;
 105                 }
 106         }
 107
 108         IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
 109
 110         return 0;
 111 }
 112
 113 /**
 114  * iwl4965_load_bsm - Load bootstrap instructions
 115  *
 116  * BSM operation:
 117  *
 118  * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
 119  * in special SRAM that does not power down during RFKILL.  When powering back
 120  * up after power-saving sleeps (or during initial uCode load), the BSM loads
 121  * the bootstrap program into the on-board processor, and starts it.
 122  *
 123  * The bootstrap program loads (via DMA) instructions and data for a new
 124  * program from host DRAM locations indicated by the host driver in the
 125  * BSM_DRAM_* registers.  Once the new program is loaded, it starts
 126  * automatically.
 127  *
 128  * When initializing the NIC, the host driver points the BSM to the
 129  * "initialize" uCode image.  This uCode sets up some internal data, then
 130  * notifies host via "initialize alive" that it is complete.
 131  *
 132  * The host then replaces the BSM_DRAM_* pointer values to point to the
 133  * normal runtime uCode instructions and a backup uCode data cache buffer
 134  * (filled initially with starting data values for the on-board processor),
 135  * then triggers the "initialize" uCode to load and launch the runtime uCode,
 136  * which begins normal operation.
 137  *
 138  * When doing a power-save shutdown, runtime uCode saves data SRAM into
 139  * the backup data cache in DRAM before SRAM is powered down.
 140  *
 141  * When powering back up, the BSM loads the bootstrap program.  This reloads
 142  * the runtime uCode instructions and the backup data cache into SRAM,
 143  * and re-launches the runtime uCode from where it left off.
 144  */
 145 static int iwl4965_load_bsm(struct iwl_priv *priv)
 146 {
 147         __le32 *image = priv->ucode_boot.v_addr;
 148         u32 len = priv->ucode_boot.len;
 149         dma_addr_t pinst;
 150         dma_addr_t pdata;
 151         u32 inst_len;
 152         u32 data_len;
 153         int i;
 154         u32 done;
 155         u32 reg_offset;
 156         int ret;
 157
 158         IWL_DEBUG_INFO("Begin load bsm\n");
 159
 160         /* make sure bootstrap program is no larger than BSM's SRAM size */
 161         if (len > IWL_MAX_BSM_SIZE)
 162                 return -EINVAL;
 163
 164         /* Tell bootstrap uCode where to find the "Initialize" uCode
 165          *   in host DRAM ... host DRAM physical address bits 35:4 for 4965.
 166          * NOTE:  iwl4965_initialize_alive_start() will replace these values,
 167          *        after the "initialize" uCode has run, to point to
 168          *        runtime/protocol instructions and backup data cache. */
 169         pinst = priv->ucode_init.p_addr >> 4;
 170         pdata = priv->ucode_init_data.p_addr >> 4;
 171         inst_len = priv->ucode_init.len;
 172         data_len = priv->ucode_init_data.len;
 173
 174         ret = iwl_grab_nic_access(priv);
 175         if (ret)
 176                 return ret;
 177
 178         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
 179         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
 180         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
 181         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
 182
 183         /* Fill BSM memory with bootstrap instructions */
 184         for (reg_offset = BSM_SRAM_LOWER_BOUND;
 185              reg_offset < BSM_SRAM_LOWER_BOUND + len;
 186              reg_offset += sizeof(u32), image++)
 187                 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
 188
 189         ret = iwl4965_verify_bsm(priv);
 190         if (ret) {
 191                 iwl_release_nic_access(priv);
 192                 return ret;
 193         }
 194
 195         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
 196         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
 197         iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
 198         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
 199
 200         /* Load bootstrap code into instruction SRAM now,
 201          *   to prepare to load "initialize" uCode */
 202         iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
 203
 204         /* Wait for load of bootstrap uCode to finish */
 205         for (i = 0; i < 100; i++) {
 206                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
 207                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
 208                         break;
 209                 udelay(10);
 210         }
 211         if (i < 100)
 212                 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
 213         else {
 214                 IWL_ERROR("BSM write did not complete!\n");
 215                 return -EIO;
 216         }
 217
 218         /* Enable future boot loads whenever power management unit triggers it
 219          *   (e.g. when powering back up after power-save shutdown) */
 220         iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
 221
 222         iwl_release_nic_access(priv);
 223
 224         return 0;
 225 }
 226
 227 static int is_fat_channel(__le32 rxon_flags)
 228 {
 229         return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
 230                 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
 231 }
 232
 233 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
 234 {
 235         int idx = 0;
 236
 237         /* 4965 HT rate format */
 238         if (rate_n_flags & RATE_MCS_HT_MSK) {
 239                 idx = (rate_n_flags & 0xff);
 240
 241                 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
 242                         idx = idx - IWL_RATE_MIMO2_6M_PLCP;
 243
 244                 idx += IWL_FIRST_OFDM_RATE;
 245                 /* skip 9M not supported in ht*/
 246                 if (idx >= IWL_RATE_9M_INDEX)
 247                         idx += 1;
 248                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
 249                         return idx;
 250
 251         /* 4965 legacy rate format, search for match in table */
 252         } else {
 253                 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
 254                         if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
 255                                 return idx;
 256         }
 257
 258         return -1;
 259 }
 260
 261 /**
 262  * translate ucode response to mac80211 tx status control values
 263  */
 264 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
 265                                   struct ieee80211_tx_control *control)
 266 {
 267         int rate_index;
 268
 269         control->antenna_sel_tx =
 270                 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
 271         if (rate_n_flags & RATE_MCS_HT_MSK)
 272                 control->flags |= IEEE80211_TXCTL_OFDM_HT;
 273         if (rate_n_flags & RATE_MCS_GF_MSK)
 274                 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
 275         if (rate_n_flags & RATE_MCS_FAT_MSK)
 276                 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
 277         if (rate_n_flags & RATE_MCS_DUP_MSK)
 278                 control->flags |= IEEE80211_TXCTL_DUP_DATA;
 279         if (rate_n_flags & RATE_MCS_SGI_MSK)
 280                 control->flags |= IEEE80211_TXCTL_SHORT_GI;
 281         /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
 282          * IEEE80211_BAND_2GHZ band as it contains all the rates */
 283         rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
 284         if (rate_index == -1)
 285                 control->tx_rate = NULL;
 286         else
 287                 control->tx_rate =
 288                         &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
 289 }
 290
 291 int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
 292 {
 293         int rc;
 294         unsigned long flags;
 295
 296         spin_lock_irqsave(&priv->lock, flags);
 297         rc = iwl_grab_nic_access(priv);
 298         if (rc) {
 299                 spin_unlock_irqrestore(&priv->lock, flags);
 300                 return rc;
 301         }
 302
 303         /* stop Rx DMA */
 304         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 305         rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 306                                      (1 << 24), 1000);
 307         if (rc < 0)
 308                 IWL_ERROR("Can't stop Rx DMA.\n");
 309
 310         iwl_release_nic_access(priv);
 311         spin_unlock_irqrestore(&priv->lock, flags);
 312
 313         return 0;
 314 }
 315
 316 /*
 317  * EEPROM handlers
 318  */
 319
 320 static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
 321 {
 322         u16 eeprom_ver;
 323         u16 calib_ver;
 324
 325         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 326
 327         calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
 328
 329         if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
 330             calib_ver < EEPROM_4965_TX_POWER_VERSION)
 331                 goto err;
 332
 333         return 0;
 334 err:
 335         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 336                   eeprom_ver, EEPROM_4965_EEPROM_VERSION,
 337                   calib_ver, EEPROM_4965_TX_POWER_VERSION);
 338         return -EINVAL;
 339
 340 }
 341 int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 342 {
 343         int ret;
 344         unsigned long flags;
 345
 346         spin_lock_irqsave(&priv->lock, flags);
 347         ret = iwl_grab_nic_access(priv);
 348         if (ret) {
 349                 spin_unlock_irqrestore(&priv->lock, flags);
 350                 return ret;
 351         }
 352
 353         if (src == IWL_PWR_SRC_VAUX) {
 354                 u32 val;
 355                 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
 356                                             &val);
 357
 358                 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
 359                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 360                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 361                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 362                 }
 363         } else {
 364                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 365                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 366                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 367         }
 368
 369         iwl_release_nic_access(priv);
 370         spin_unlock_irqrestore(&priv->lock, flags);
 371
 372         return ret;
 373 }
 374
 375 static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 376 {
 377         int ret;
 378         unsigned long flags;
 379         unsigned int rb_size;
 380
 381         spin_lock_irqsave(&priv->lock, flags);
 382         ret = iwl_grab_nic_access(priv);
 383         if (ret) {
 384                 spin_unlock_irqrestore(&priv->lock, flags);
 385                 return ret;
 386         }
 387
 388         if (priv->cfg->mod_params->amsdu_size_8K)
 389                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 390         else
 391                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 392
 393         /* Stop Rx DMA */
 394         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 395
 396         /* Reset driver's Rx queue write index */
 397         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 398
 399         /* Tell device where to find RBD circular buffer in DRAM */
 400         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 401                            rxq->dma_addr >> 8);
 402
 403         /* Tell device where in DRAM to update its Rx status */
 404         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 405                            (priv->shared_phys +
 406                             offsetof(struct iwl4965_shared, rb_closed)) >> 4);
 407
 408         /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
 409         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 410                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 411                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 412                            rb_size |
 413                              /* 0x10 << 4 | */
 414                            (RX_QUEUE_SIZE_LOG <<
 415                               FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
 416
 417         /*
 418          * iwl_write32(priv,CSR_INT_COAL_REG,0);
 419          */
 420
 421         iwl_release_nic_access(priv);
 422         spin_unlock_irqrestore(&priv->lock, flags);
 423
 424         return 0;
 425 }
 426
 427 /* Tell 4965 where to find the "keep warm" buffer */
 428 static int iwl4965_kw_init(struct iwl_priv *priv)
 429 {
 430         unsigned long flags;
 431         int rc;
 432
 433         spin_lock_irqsave(&priv->lock, flags);
 434         rc = iwl_grab_nic_access(priv);
 435         if (rc)
 436                 goto out;
 437
 438         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
 439                              priv->kw.dma_addr >> 4);
 440         iwl_release_nic_access(priv);
 441 out:
 442         spin_unlock_irqrestore(&priv->lock, flags);
 443         return rc;
 444 }
 445
 446 static int iwl4965_kw_alloc(struct iwl_priv *priv)
 447 {
 448         struct pci_dev *dev = priv->pci_dev;
 449         struct iwl4965_kw *kw = &priv->kw;
 450
 451         kw->size = IWL4965_KW_SIZE;     /* TBW need set somewhere else */
 452         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 453         if (!kw->v_addr)
 454                 return -ENOMEM;
 455
 456         return 0;
 457 }
 458
 459 /**
 460  * iwl4965_kw_free - Free the "keep warm" buffer
 461  */
 462 static void iwl4965_kw_free(struct iwl_priv *priv)
 463 {
 464         struct pci_dev *dev = priv->pci_dev;
 465         struct iwl4965_kw *kw = &priv->kw;
 466
 467         if (kw->v_addr) {
 468                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 469                 memset(kw, 0, sizeof(*kw));
 470         }
 471 }
 472
 473 /**
 474  * iwl4965_txq_ctx_reset - Reset TX queue context
 475  * Destroys all DMA structures and initialise them again
 476  *
 477  * @param priv
 478  * @return error code
 479  */
 480 static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
 481 {
 482         int rc = 0;
 483         int txq_id, slots_num;
 484         unsigned long flags;
 485
 486         iwl4965_kw_free(priv);
 487
 488         /* Free all tx/cmd queues and keep-warm buffer */
 489         iwl4965_hw_txq_ctx_free(priv);
 490
 491         /* Alloc keep-warm buffer */
 492         rc = iwl4965_kw_alloc(priv);
 493         if (rc) {
 494                 IWL_ERROR("Keep Warm allocation failed");
 495                 goto error_kw;
 496         }
 497
 498         spin_lock_irqsave(&priv->lock, flags);
 499
 500         rc = iwl_grab_nic_access(priv);
 501         if (unlikely(rc)) {
 502                 IWL_ERROR("TX reset failed");
 503                 spin_unlock_irqrestore(&priv->lock, flags);
 504                 goto error_reset;
 505         }
 506
 507         /* Turn off all Tx DMA channels */
 508         iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
 509         iwl_release_nic_access(priv);
 510         spin_unlock_irqrestore(&priv->lock, flags);
 511
 512         /* Tell 4965 where to find the keep-warm buffer */
 513         rc = iwl4965_kw_init(priv);
 514         if (rc) {
 515                 IWL_ERROR("kw_init failed\n");
 516                 goto error_reset;
 517         }
 518
 519         /* Alloc and init all (default 16) Tx queues,
 520          * including the command queue (#4) */
 521         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 522                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 523                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 524                 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 525                                        txq_id);
 526                 if (rc) {
 527                         IWL_ERROR("Tx %d queue init failed\n", txq_id);
 528                         goto error;
 529                 }
 530         }
 531
 532         return rc;
 533
 534  error:
 535         iwl4965_hw_txq_ctx_free(priv);
 536  error_reset:
 537         iwl4965_kw_free(priv);
 538  error_kw:
 539         return rc;
 540 }
 541 static int iwl4965_apm_init(struct iwl_priv *priv)
 542 {
 543         unsigned long flags;
 544         int ret = 0;
 545
 546         spin_lock_irqsave(&priv->lock, flags);
 547         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 548                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 549
 550         /* set "initialization complete" bit to move adapter
 551          * D0U* --> D0A* state */
 552         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 553
 554         /* wait for clock stabilization */
 555         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 556                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 557                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 558         if (ret < 0) {
 559                 IWL_DEBUG_INFO("Failed to init the card\n");
 560                 goto out;
 561         }
 562
 563         ret = iwl_grab_nic_access(priv);
 564         if (ret)
 565                 goto out;
 566
 567         /* enable DMA */
 568         iwl_write_prph(priv, APMG_CLK_CTRL_REG,
 569                         APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
 570
 571         udelay(20);
 572
 573         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 574                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 575
 576         iwl_release_nic_access(priv);
 577 out:
 578         spin_unlock_irqrestore(&priv->lock, flags);
 579         return ret;
 580 }
 581
 582
 583 static void iwl4965_nic_config(struct iwl_priv *priv)
 584 {
 585         unsigned long flags;
 586         u32 val;
 587         u16 radio_cfg;
 588         u8 val_link;
 589
 590         spin_lock_irqsave(&priv->lock, flags);
 591
 592         if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
 593                 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
 594                 /* Enable No Snoop field */
 595                 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
 596                                        val & ~(1 << 11));
 597         }
 598
 599         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
 600
 601         /* disable L1 entry -- workaround for pre-B1 */
 602         pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
 603
 604         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 605
 606         /* write radio config values to register */
 607         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
 608                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 609                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 610                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 611                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 612
 613         /* set CSR_HW_CONFIG_REG for uCode use */
 614         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 615                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 616                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 617
 618         priv->calib_info = (struct iwl_eeprom_calib_info *)
 619                 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
 620
 621         spin_unlock_irqrestore(&priv->lock, flags);
 622 }
 623
 624
 625 int iwl4965_hw_nic_init(struct iwl_priv *priv)
 626 {
 627         unsigned long flags;
 628         struct iwl_rx_queue *rxq = &priv->rxq;
 629         int ret;
 630
 631         /* nic_init */
 632         priv->cfg->ops->lib->apm_ops.init(priv);
 633
 634         spin_lock_irqsave(&priv->lock, flags);
 635         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 636         spin_unlock_irqrestore(&priv->lock, flags);
 637
 638         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 639
 640         priv->cfg->ops->lib->apm_ops.config(priv);
 641
 642         iwl4965_hw_card_show_info(priv);
 643
 644         /* end nic_init */
 645
 646         /* Allocate the RX queue, or reset if it is already allocated */
 647         if (!rxq->bd) {
 648                 ret = iwl_rx_queue_alloc(priv);
 649                 if (ret) {
 650                         IWL_ERROR("Unable to initialize Rx queue\n");
 651                         return -ENOMEM;
 652                 }
 653         } else
 654                 iwl_rx_queue_reset(priv, rxq);
 655
 656         iwl_rx_replenish(priv);
 657
 658         iwl4965_rx_init(priv, rxq);
 659
 660         spin_lock_irqsave(&priv->lock, flags);
 661
 662         rxq->need_update = 1;
 663         iwl_rx_queue_update_write_ptr(priv, rxq);
 664
 665         spin_unlock_irqrestore(&priv->lock, flags);
 666
 667         /* Allocate and init all Tx and Command queues */
 668         ret = iwl4965_txq_ctx_reset(priv);
 669         if (ret)
 670                 return ret;
 671
 672         set_bit(STATUS_INIT, &priv->status);
 673
 674         return 0;
 675 }
 676
 677 int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
 678 {
 679         int rc = 0;
 680         u32 reg_val;
 681         unsigned long flags;
 682
 683         spin_lock_irqsave(&priv->lock, flags);
 684
 685         /* set stop master bit */
 686         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 687
 688         reg_val = iwl_read32(priv, CSR_GP_CNTRL);
 689
 690         if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
 691             (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
 692                 IWL_DEBUG_INFO("Card in power save, master is already "
 693                                "stopped\n");
 694         else {
 695                 rc = iwl_poll_bit(priv, CSR_RESET,
 696                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
 697                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 698                 if (rc < 0) {
 699                         spin_unlock_irqrestore(&priv->lock, flags);
 700                         return rc;
 701                 }
 702         }
 703
 704         spin_unlock_irqrestore(&priv->lock, flags);
 705         IWL_DEBUG_INFO("stop master\n");
 706
 707         return rc;
 708 }
 709
 710 /**
 711  * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
 712  */
 713 void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
 714 {
 715
 716         int txq_id;
 717         unsigned long flags;
 718
 719         /* Stop each Tx DMA channel, and wait for it to be idle */
 720         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 721                 spin_lock_irqsave(&priv->lock, flags);
 722                 if (iwl_grab_nic_access(priv)) {
 723                         spin_unlock_irqrestore(&priv->lock, flags);
 724                         continue;
 725                 }
 726
 727                 iwl_write_direct32(priv,
 728                                    FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
 729                 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
 730                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
 731                                     (txq_id), 200);
 732                 iwl_release_nic_access(priv);
 733                 spin_unlock_irqrestore(&priv->lock, flags);
 734         }
 735
 736         /* Deallocate memory for all Tx queues */
 737         iwl4965_hw_txq_ctx_free(priv);
 738 }
 739
 740 int iwl4965_hw_nic_reset(struct iwl_priv *priv)
 741 {
 742         int rc = 0;
 743         unsigned long flags;
 744
 745         iwl4965_hw_nic_stop_master(priv);
 746
 747         spin_lock_irqsave(&priv->lock, flags);
 748
 749         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 750
 751         udelay(10);
 752
 753         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 754         rc = iwl_poll_bit(priv, CSR_RESET,
 755                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 756                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
 757
 758         udelay(10);
 759
 760         rc = iwl_grab_nic_access(priv);
 761         if (!rc) {
 762                 iwl_write_prph(priv, APMG_CLK_EN_REG,
 763                                 APMG_CLK_VAL_DMA_CLK_RQT |
 764                                 APMG_CLK_VAL_BSM_CLK_RQT);
 765
 766                 udelay(10);
 767
 768                 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 769                                         APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 770
 771                 iwl_release_nic_access(priv);
 772         }
 773
 774         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
 775         wake_up_interruptible(&priv->wait_command_queue);
 776
 777         spin_unlock_irqrestore(&priv->lock, flags);
 778
 779         return rc;
 780
 781 }
 782
 783 #define REG_RECALIB_PERIOD (60)
 784
 785 /**
 786  * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
 787  *
 788  * This callback is provided in order to send a statistics request.
 789  *
 790  * This timer function is continually reset to execute within
 791  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 792  * was received.  We need to ensure we receive the statistics in order
 793  * to update the temperature used for calibrating the TXPOWER.
 794  */
 795 static void iwl4965_bg_statistics_periodic(unsigned long data)
 796 {
 797         struct iwl_priv *priv = (struct iwl_priv *)data;
 798
 799         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 800                 return;
 801
 802         iwl_send_statistics_request(priv, CMD_ASYNC);
 803 }
 804
 805 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
 806 {
 807         struct iwl4965_ct_kill_config cmd;
 808         unsigned long flags;
 809         int ret = 0;
 810
 811         spin_lock_irqsave(&priv->lock, flags);
 812         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 813                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
 814         spin_unlock_irqrestore(&priv->lock, flags);
 815
 816         cmd.critical_temperature_R =
 817                 cpu_to_le32(priv->hw_params.ct_kill_threshold);
 818
 819         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
 820                                sizeof(cmd), &cmd);
 821         if (ret)
 822                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
 823         else
 824                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
 825                         "critical temperature is %d\n",
 826                         cmd.critical_temperature_R);
 827 }
 828
 829 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
 830
 831 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
 832  * Called after every association, but this runs only once!
 833  *  ... once chain noise is calibrated the first time, it's good forever.  */
 834 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
 835 {
 836         struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
 837
 838         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 839                 struct iwl4965_calibration_cmd cmd;
 840
 841                 memset(&cmd, 0, sizeof(cmd));
 842                 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
 843                 cmd.diff_gain_a = 0;
 844                 cmd.diff_gain_b = 0;
 845                 cmd.diff_gain_c = 0;
 846                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 847                                  sizeof(cmd), &cmd))
 848                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 849                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 850                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 851         }
 852 }
 853
 854 static void iwl4965_gain_computation(struct iwl_priv *priv,
 855                 u32 *average_noise,
 856                 u16 min_average_noise_antenna_i,
 857                 u32 min_average_noise)
 858 {
 859         int i, ret;
 860         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 861
 862         data->delta_gain_code[min_average_noise_antenna_i] = 0;
 863
 864         for (i = 0; i < NUM_RX_CHAINS; i++) {
 865                 s32 delta_g = 0;
 866
 867                 if (!(data->disconn_array[i]) &&
 868                     (data->delta_gain_code[i] ==
 869                              CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
 870                         delta_g = average_noise[i] - min_average_noise;
 871                         data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
 872                         data->delta_gain_code[i] =
 873                                 min(data->delta_gain_code[i],
 874                                 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 875
 876                         data->delta_gain_code[i] =
 877                                 (data->delta_gain_code[i] | (1 << 2));
 878                 } else {
 879                         data->delta_gain_code[i] = 0;
 880                 }
 881         }
 882         IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
 883                      data->delta_gain_code[0],
 884                      data->delta_gain_code[1],
 885                      data->delta_gain_code[2]);
 886
 887         /* Differential gain gets sent to uCode only once */
 888         if (!data->radio_write) {
 889                 struct iwl4965_calibration_cmd cmd;
 890                 data->radio_write = 1;
 891
 892                 memset(&cmd, 0, sizeof(cmd));
 893                 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
 894                 cmd.diff_gain_a = data->delta_gain_code[0];
 895                 cmd.diff_gain_b = data->delta_gain_code[1];
 896                 cmd.diff_gain_c = data->delta_gain_code[2];
 897                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 898                                       sizeof(cmd), &cmd);
 899                 if (ret)
 900                         IWL_DEBUG_CALIB("fail sending cmd "
 901                                      "REPLY_PHY_CALIBRATION_CMD \n");
 902
 903                 /* TODO we might want recalculate
 904                  * rx_chain in rxon cmd */
 905
 906                 /* Mark so we run this algo only once! */
 907                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 908         }
 909         data->chain_noise_a = 0;
 910         data->chain_noise_b = 0;
 911         data->chain_noise_c = 0;
 912         data->chain_signal_a = 0;
 913         data->chain_signal_b = 0;
 914         data->chain_signal_c = 0;
 915         data->beacon_count = 0;
 916 }
 917
 918 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
 919 {
 920         struct iwl_priv *priv = container_of(work, struct iwl_priv,
 921                         sensitivity_work);
 922
 923         mutex_lock(&priv->mutex);
 924
 925         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
 926             test_bit(STATUS_SCANNING, &priv->status)) {
 927                 mutex_unlock(&priv->mutex);
 928                 return;
 929         }
 930
 931         if (priv->start_calib) {
 932                 iwl_chain_noise_calibration(priv, &priv->statistics);
 933
 934                 iwl_sensitivity_calibration(priv, &priv->statistics);
 935         }
 936
 937         mutex_unlock(&priv->mutex);
 938         return;
 939 }
 940 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
 941
 942 static void iwl4965_bg_txpower_work(struct work_struct *work)
 943 {
 944         struct iwl_priv *priv = container_of(work, struct iwl_priv,
 945                         txpower_work);
 946
 947         /* If a scan happened to start before we got here
 948          * then just return; the statistics notification will
 949          * kick off another scheduled work to compensate for
 950          * any temperature delta we missed here. */
 951         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
 952             test_bit(STATUS_SCANNING, &priv->status))
 953                 return;
 954
 955         mutex_lock(&priv->mutex);
 956
 957         /* Regardless of if we are assocaited, we must reconfigure the
 958          * TX power since frames can be sent on non-radar channels while
 959          * not associated */
 960         iwl4965_hw_reg_send_txpower(priv);
 961
 962         /* Update last_temperature to keep is_calib_needed from running
 963          * when it isn't needed... */
 964         priv->last_temperature = priv->temperature;
 965
 966         mutex_unlock(&priv->mutex);
 967 }
 968
 969 /*
 970  * Acquire priv->lock before calling this function !
 971  */
 972 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
 973 {
 974         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 975                              (index & 0xff) | (txq_id << 8));
 976         iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
 977 }
 978
 979 /**
 980  * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
 981  * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
 982  * @scd_retry: (1) Indicates queue will be used in aggregation mode
 983  *
 984  * NOTE:  Acquire priv->lock before calling this function !
 985  */
 986 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
 987                                         struct iwl4965_tx_queue *txq,
 988                                         int tx_fifo_id, int scd_retry)
 989 {
 990         int txq_id = txq->q.id;
 991
 992         /* Find out whether to activate Tx queue */
 993         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
 994
 995         /* Set up and activate */
 996         iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
 997                          (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 998                          (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
 999                          (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
1000                          (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1001                          IWL49_SCD_QUEUE_STTS_REG_MSK);
1002
1003         txq->sched_retry = scd_retry;
1004
1005         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
1006                        active ? "Activate" : "Deactivate",
1007                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1008 }
1009
1010 static const u16 default_queue_to_tx_fifo[] = {
1011         IWL_TX_FIFO_AC3,
1012         IWL_TX_FIFO_AC2,
1013         IWL_TX_FIFO_AC1,
1014         IWL_TX_FIFO_AC0,
1015         IWL49_CMD_FIFO_NUM,
1016         IWL_TX_FIFO_HCCA_1,
1017         IWL_TX_FIFO_HCCA_2
1018 };
1019
1020 static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1021 {
1022         set_bit(txq_id, &priv->txq_ctx_active_msk);
1023 }
1024
1025 static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1026 {
1027         clear_bit(txq_id, &priv->txq_ctx_active_msk);
1028 }
1029
1030 int iwl4965_alive_notify(struct iwl_priv *priv)
1031 {
1032         u32 a;
1033         int i = 0;
1034         unsigned long flags;
1035         int ret;
1036
1037         spin_lock_irqsave(&priv->lock, flags);
1038
1039 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1040         memset(&(priv->sensitivity_data), 0,
1041                sizeof(struct iwl_sensitivity_data));
1042         memset(&(priv->chain_noise_data), 0,
1043                sizeof(struct iwl_chain_noise_data));
1044         for (i = 0; i < NUM_RX_CHAINS; i++)
1045                 priv->chain_noise_data.delta_gain_code[i] =
1046                                 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1047 #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
1048         ret = iwl_grab_nic_access(priv);
1049         if (ret) {
1050                 spin_unlock_irqrestore(&priv->lock, flags);
1051                 return ret;
1052         }
1053
1054         /* Clear 4965's internal Tx Scheduler data base */
1055         priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1056         a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
1057         for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1058                 iwl_write_targ_mem(priv, a, 0);
1059         for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
1060                 iwl_write_targ_mem(priv, a, 0);
1061         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1062                 iwl_write_targ_mem(priv, a, 0);
1063
1064         /* Tel 4965 where to find Tx byte count tables */
1065         iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1066                 (priv->shared_phys +
1067                  offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1068
1069         /* Disable chain mode for all queues */
1070         iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1071
1072         /* Initialize each Tx queue (including the command queue) */
1073         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1074
1075                 /* TFD circular buffer read/write indexes */
1076                 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1077                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1078
1079                 /* Max Tx Window size for Scheduler-ACK mode */
1080                 iwl_write_targ_mem(priv, priv->scd_base_addr +
1081                                 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
1082                                 (SCD_WIN_SIZE <<
1083                                 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1084                                 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1085
1086                 /* Frame limit */
1087                 iwl_write_targ_mem(priv, priv->scd_base_addr +
1088                                 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
1089                                 sizeof(u32),
1090                                 (SCD_FRAME_LIMIT <<
1091                                 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1092                                 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1093
1094         }
1095         iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1096                                  (1 << priv->hw_params.max_txq_num) - 1);
1097
1098         /* Activate all Tx DMA/FIFO channels */
1099         iwl_write_prph(priv, IWL49_SCD_TXFACT,
1100                                  SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1101
1102         iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1103
1104         /* Map each Tx/cmd queue to its corresponding fifo */
1105         for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1106                 int ac = default_queue_to_tx_fifo[i];
1107                 iwl4965_txq_ctx_activate(priv, i);
1108                 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1109         }
1110
1111         iwl_release_nic_access(priv);
1112         spin_unlock_irqrestore(&priv->lock, flags);
1113
1114         /* Ask for statistics now, the uCode will send statistics notification
1115          * periodically after association */
1116         iwl_send_statistics_request(priv, CMD_ASYNC);
1117         return ret;
1118 }
1119
1120 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1121 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1122         .min_nrg_cck = 97,
1123         .max_nrg_cck = 0,
1124
1125         .auto_corr_min_ofdm = 85,
1126         .auto_corr_min_ofdm_mrc = 170,
1127         .auto_corr_min_ofdm_x1 = 105,
1128         .auto_corr_min_ofdm_mrc_x1 = 220,
1129
1130         .auto_corr_max_ofdm = 120,
1131         .auto_corr_max_ofdm_mrc = 210,
1132         .auto_corr_max_ofdm_x1 = 140,
1133         .auto_corr_max_ofdm_mrc_x1 = 270,
1134
1135         .auto_corr_min_cck = 125,
1136         .auto_corr_max_cck = 200,
1137         .auto_corr_min_cck_mrc = 200,
1138         .auto_corr_max_cck_mrc = 400,
1139
1140         .nrg_th_cck = 100,
1141         .nrg_th_ofdm = 100,
1142 };
1143 #endif
1144
1145 /**
1146  * iwl4965_hw_set_hw_params
1147  *
1148  * Called when initializing driver
1149  */
1150 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
1151 {
1152
1153         if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1154             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
1155                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1156                           IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
1157                 return -EINVAL;
1158         }
1159
1160         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
1161         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
1162         priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1163         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1164         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1165         if (priv->cfg->mod_params->amsdu_size_8K)
1166                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1167         else
1168                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1169         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1170         priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1171         priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
1172
1173         priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1174         priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1175         priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1176         priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1177
1178         priv->hw_params.tx_chains_num = 2;
1179         priv->hw_params.rx_chains_num = 2;
1180         priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1181         priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
1182         priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1183
1184 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1185         priv->hw_params.sens = &iwl4965_sensitivity;
1186 #endif
1187
1188         return 0;
1189 }
1190
1191 /**
1192  * iwl4965_hw_txq_ctx_free - Free TXQ Context
1193  *
1194  * Destroy all TX DMA queues and structures
1195  */
1196 void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
1197 {
1198         int txq_id;
1199
1200         /* Tx queues */
1201         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1202                 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
1203
1204         /* Keep-warm buffer */
1205         iwl4965_kw_free(priv);
1206 }
1207
1208 /**
1209  * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
1210  *
1211  * Does NOT advance any TFD circular buffer read/write indexes
1212  * Does NOT free the TFD itself (which is within circular buffer)
1213  */
1214 int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
1215 {
1216         struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1217         struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
1218         struct pci_dev *dev = priv->pci_dev;
1219         int i;
1220         int counter = 0;
1221         int index, is_odd;
1222
1223         /* Host command buffers stay mapped in memory, nothing to clean */
1224         if (txq->q.id == IWL_CMD_QUEUE_NUM)
1225                 return 0;
1226
1227         /* Sanity check on number of chunks */
1228         counter = IWL_GET_BITS(*bd, num_tbs);
1229         if (counter > MAX_NUM_OF_TBS) {
1230                 IWL_ERROR("Too many chunks: %i\n", counter);
1231                 /* @todo issue fatal error, it is quite serious situation */
1232                 return 0;
1233         }
1234
1235         /* Unmap chunks, if any.
1236          * TFD info for odd chunks is different format than for even chunks. */
1237         for (i = 0; i < counter; i++) {
1238                 index = i / 2;
1239                 is_odd = i & 0x1;
1240
1241                 if (is_odd)
1242                         pci_unmap_single(
1243                                 dev,
1244                                 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1245                                 (IWL_GET_BITS(bd->pa[index],
1246                                               tb2_addr_hi20) << 16),
1247                                 IWL_GET_BITS(bd->pa[index], tb2_len),
1248                                 PCI_DMA_TODEVICE);
1249
1250                 else if (i > 0)
1251                         pci_unmap_single(dev,
1252                                          le32_to_cpu(bd->pa[index].tb1_addr),
1253                                          IWL_GET_BITS(bd->pa[index], tb1_len),
1254                                          PCI_DMA_TODEVICE);
1255
1256                 /* Free SKB, if any, for this chunk */
1257                 if (txq->txb[txq->q.read_ptr].skb[i]) {
1258                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
1259
1260                         dev_kfree_skb(skb);
1261                         txq->txb[txq->q.read_ptr].skb[i] = NULL;
1262                 }
1263         }
1264         return 0;
1265 }
1266
1267 /* set card power command */
1268 static int iwl4965_set_power(struct iwl_priv *priv,
1269                       void *cmd)
1270 {
1271         int ret = 0;
1272
1273         ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1274                                     sizeof(struct iwl4965_powertable_cmd),
1275                                     cmd, NULL);
1276         return ret;
1277 }
1278 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1279 {
1280         IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1281         return -EINVAL;
1282 }
1283
1284 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1285 {
1286         s32 sign = 1;
1287
1288         if (num < 0) {
1289                 sign = -sign;
1290                 num = -num;
1291         }
1292         if (denom < 0) {
1293                 sign = -sign;
1294                 denom = -denom;
1295         }
1296         *res = 1;
1297         *res = ((num * 2 + denom) / (denom * 2)) * sign;
1298
1299         return 1;
1300 }
1301
1302 /**
1303  * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1304  *
1305  * Determines power supply voltage compensation for txpower calculations.
1306  * Returns number of 1/2-dB steps to subtract from gain table index,
1307  * to compensate for difference between power supply voltage during
1308  * factory measurements, vs. current power supply voltage.
1309  *
1310  * Voltage indication is higher for lower voltage.
1311  * Lower voltage requires more gain (lower gain table index).
1312  */
1313 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1314                                             s32 current_voltage)
1315 {
1316         s32 comp = 0;
1317
1318         if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1319             (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1320                 return 0;
1321
1322         iwl4965_math_div_round(current_voltage - eeprom_voltage,
1323                                TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1324
1325         if (current_voltage > eeprom_voltage)
1326                 comp *= 2;
1327         if ((comp < -2) || (comp > 2))
1328                 comp = 0;
1329
1330         return comp;
1331 }
1332
1333 static const struct iwl_channel_info *
1334 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1335                                  enum ieee80211_band band, u16 channel)
1336 {
1337         const struct iwl_channel_info *ch_info;
1338
1339         ch_info = iwl_get_channel_info(priv, band, channel);
1340
1341         if (!is_channel_valid(ch_info))
1342                 return NULL;
1343
1344         return ch_info;
1345 }
1346
1347 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1348 {
1349         if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1350             channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1351                 return CALIB_CH_GROUP_5;
1352
1353         if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1354             channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1355                 return CALIB_CH_GROUP_1;
1356
1357         if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1358             channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1359                 return CALIB_CH_GROUP_2;
1360
1361         if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1362             channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1363                 return CALIB_CH_GROUP_3;
1364
1365         if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1366             channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1367                 return CALIB_CH_GROUP_4;
1368
1369         IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1370         return -1;
1371 }
1372
1373 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1374 {
1375         s32 b = -1;
1376
1377         for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1378                 if (priv->calib_info->band_info[b].ch_from == 0)
1379                         continue;
1380
1381                 if ((channel >= priv->calib_info->band_info[b].ch_from)
1382                     && (channel <= priv->calib_info->band_info[b].ch_to))
1383                         break;
1384         }
1385
1386         return b;
1387 }
1388
1389 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1390 {
1391         s32 val;
1392
1393         if (x2 == x1)
1394                 return y1;
1395         else {
1396                 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1397                 return val + y2;
1398         }
1399 }
1400
1401 /**
1402  * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1403  *
1404  * Interpolates factory measurements from the two sample channels within a
1405  * sub-band, to apply to channel of interest.  Interpolation is proportional to
1406  * differences in channel frequencies, which is proportional to differences
1407  * in channel number.
1408  */
1409 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1410                                     struct iwl_eeprom_calib_ch_info *chan_info)
1411 {
1412         s32 s = -1;
1413         u32 c;
1414         u32 m;
1415         const struct iwl_eeprom_calib_measure *m1;
1416         const struct iwl_eeprom_calib_measure *m2;
1417         struct iwl_eeprom_calib_measure *omeas;
1418         u32 ch_i1;
1419         u32 ch_i2;
1420
1421         s = iwl4965_get_sub_band(priv, channel);
1422         if (s >= EEPROM_TX_POWER_BANDS) {
1423                 IWL_ERROR("Tx Power can not find channel %d ", channel);
1424                 return -1;
1425         }
1426
1427         ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1428         ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
1429         chan_info->ch_num = (u8) channel;
1430
1431         IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1432                           channel, s, ch_i1, ch_i2);
1433
1434         for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1435                 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1436                         m1 = &(priv->calib_info->band_info[s].ch1.
1437                                measurements[c][m]);
1438                         m2 = &(priv->calib_info->band_info[s].ch2.
1439                                measurements[c][m]);
1440                         omeas = &(chan_info->measurements[c][m]);
1441
1442                         omeas->actual_pow =
1443                             (u8) iwl4965_interpolate_value(channel, ch_i1,
1444                                                            m1->actual_pow,
1445                                                            ch_i2,
1446                                                            m2->actual_pow);
1447                         omeas->gain_idx =
1448                             (u8) iwl4965_interpolate_value(channel, ch_i1,
1449                                                            m1->gain_idx, ch_i2,
1450                                                            m2->gain_idx);
1451                         omeas->temperature =
1452                             (u8) iwl4965_interpolate_value(channel, ch_i1,
1453                                                            m1->temperature,
1454                                                            ch_i2,
1455                                                            m2->temperature);
1456                         omeas->pa_det =
1457                             (s8) iwl4965_interpolate_value(channel, ch_i1,
1458                                                            m1->pa_det, ch_i2,
1459                                                            m2->pa_det);
1460
1461                         IWL_DEBUG_TXPOWER
1462                             ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1463                              m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1464                         IWL_DEBUG_TXPOWER
1465                             ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1466                              m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1467                         IWL_DEBUG_TXPOWER
1468                             ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1469                              m1->pa_det, m2->pa_det, omeas->pa_det);
1470                         IWL_DEBUG_TXPOWER
1471                             ("chain %d meas %d  T1=%d  T2=%d  T=%d\n", c, m,
1472                              m1->temperature, m2->temperature,
1473                              omeas->temperature);
1474                 }
1475         }
1476
1477         return 0;
1478 }
1479
1480 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1481  * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1482 static s32 back_off_table[] = {
1483         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1484         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1485         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1486         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1487         10                      /* CCK */
1488 };
1489
1490 /* Thermal compensation values for txpower for various frequency ranges ...
1491  *   ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1492 static struct iwl4965_txpower_comp_entry {
1493         s32 degrees_per_05db_a;
1494         s32 degrees_per_05db_a_denom;
1495 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1496         {9, 2},                 /* group 0 5.2, ch  34-43 */
1497         {4, 1},                 /* group 1 5.2, ch  44-70 */
1498         {4, 1},                 /* group 2 5.2, ch  71-124 */
1499         {4, 1},                 /* group 3 5.2, ch 125-200 */
1500         {3, 1}                  /* group 4 2.4, ch   all */
1501 };
1502
1503 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1504 {
1505         if (!band) {
1506                 if ((rate_power_index & 7) <= 4)
1507                         return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1508         }
1509         return MIN_TX_GAIN_INDEX;
1510 }
1511
1512 struct gain_entry {
1513         u8 dsp;
1514         u8 radio;
1515 };
1516
1517 static const struct gain_entry gain_table[2][108] = {
1518         /* 5.2GHz power gain index table */
1519         {
1520          {123, 0x3F},           /* highest txpower */
1521          {117, 0x3F},
1522          {110, 0x3F},
1523          {104, 0x3F},
1524          {98, 0x3F},
1525          {110, 0x3E},
1526          {104, 0x3E},
1527          {98, 0x3E},
1528          {110, 0x3D},
1529          {104, 0x3D},
1530          {98, 0x3D},
1531          {110, 0x3C},
1532          {104, 0x3C},
1533          {98, 0x3C},
1534          {110, 0x3B},
1535          {104, 0x3B},
1536          {98, 0x3B},
1537          {110, 0x3A},
1538          {104, 0x3A},
1539          {98, 0x3A},
1540          {110, 0x39},
1541          {104, 0x39},
1542          {98, 0x39},
1543          {110, 0x38},
1544          {104, 0x38},
1545          {98, 0x38},
1546          {110, 0x37},
1547          {104, 0x37},
1548          {98, 0x37},
1549          {110, 0x36},
1550          {104, 0x36},
1551          {98, 0x36},
1552          {110, 0x35},
1553          {104, 0x35},
1554          {98, 0x35},
1555          {110, 0x34},
1556          {104, 0x34},
1557          {98, 0x34},
1558          {110, 0x33},
1559          {104, 0x33},
1560          {98, 0x33},
1561          {110, 0x32},
1562          {104, 0x32},
1563          {98, 0x32},
1564          {110, 0x31},
1565          {104, 0x31},
1566          {98, 0x31},
1567          {110, 0x30},
1568          {104, 0x30},
1569          {98, 0x30},
1570          {110, 0x25},
1571          {104, 0x25},
1572          {98, 0x25},
1573          {110, 0x24},
1574          {104, 0x24},
1575          {98, 0x24},
1576          {110, 0x23},
1577          {104, 0x23},
1578          {98, 0x23},
1579          {110, 0x22},
1580          {104, 0x18},
1581          {98, 0x18},
1582          {110, 0x17},
1583          {104, 0x17},
1584          {98, 0x17},
1585          {110, 0x16},
1586          {104, 0x16},
1587          {98, 0x16},
1588          {110, 0x15},
1589          {104, 0x15},
1590          {98, 0x15},
1591          {110, 0x14},
1592          {104, 0x14},
1593          {98, 0x14},
1594          {110, 0x13},
1595          {104, 0x13},
1596          {98, 0x13},
1597          {110, 0x12},
1598          {104, 0x08},
1599          {98, 0x08},
1600          {110, 0x07},
1601          {104, 0x07},
1602          {98, 0x07},
1603          {110, 0x06},
1604          {104, 0x06},
1605          {98, 0x06},
1606          {110, 0x05},
1607          {104, 0x05},
1608          {98, 0x05},
1609          {110, 0x04},
1610          {104, 0x04},
1611          {98, 0x04},
1612          {110, 0x03},
1613          {104, 0x03},
1614          {98, 0x03},
1615          {110, 0x02},
1616          {104, 0x02},
1617          {98, 0x02},
1618          {110, 0x01},
1619          {104, 0x01},
1620          {98, 0x01},
1621          {110, 0x00},
1622          {104, 0x00},
1623          {98, 0x00},
1624          {93, 0x00},
1625          {88, 0x00},
1626          {83, 0x00},
1627          {78, 0x00},
1628          },
1629         /* 2.4GHz power gain index table */
1630         {
1631          {110, 0x3f},           /* highest txpower */
1632          {104, 0x3f},
1633          {98, 0x3f},
1634          {110, 0x3e},
1635          {104, 0x3e},
1636          {98, 0x3e},
1637          {110, 0x3d},
1638          {104, 0x3d},
1639          {98, 0x3d},
1640          {110, 0x3c},
1641          {104, 0x3c},
1642          {98, 0x3c},
1643          {110, 0x3b},
1644          {104, 0x3b},
1645          {98, 0x3b},
1646          {110, 0x3a},
1647          {104, 0x3a},
1648          {98, 0x3a},
1649          {110, 0x39},
1650          {104, 0x39},
1651          {98, 0x39},
1652          {110, 0x38},
1653          {104, 0x38},
1654          {98, 0x38},
1655          {110, 0x37},
1656          {104, 0x37},
1657          {98, 0x37},
1658          {110, 0x36},
1659          {104, 0x36},
1660          {98, 0x36},
1661          {110, 0x35},
1662          {104, 0x35},
1663          {98, 0x35},
1664          {110, 0x34},
1665          {104, 0x34},
1666          {98, 0x34},
1667          {110, 0x33},
1668          {104, 0x33},
1669          {98, 0x33},
1670          {110, 0x32},
1671          {104, 0x32},
1672          {98, 0x32},
1673          {110, 0x31},
1674          {104, 0x31},
1675          {98, 0x31},
1676          {110, 0x30},
1677          {104, 0x30},
1678          {98, 0x30},
1679          {110, 0x6},
1680          {104, 0x6},
1681          {98, 0x6},
1682          {110, 0x5},
1683          {104, 0x5},
1684          {98, 0x5},
1685          {110, 0x4},
1686          {104, 0x4},
1687          {98, 0x4},
1688          {110, 0x3},
1689          {104, 0x3},
1690          {98, 0x3},
1691          {110, 0x2},
1692          {104, 0x2},
1693          {98, 0x2},
1694          {110, 0x1},
1695          {104, 0x1},
1696          {98, 0x1},
1697          {110, 0x0},
1698          {104, 0x0},
1699          {98, 0x0},
1700          {97, 0},
1701          {96, 0},
1702          {95, 0},
1703          {94, 0},
1704          {93, 0},
1705          {92, 0},
1706          {91, 0},
1707          {90, 0},
1708          {89, 0},
1709          {88, 0},
1710          {87, 0},
1711          {86, 0},
1712          {85, 0},
1713          {84, 0},
1714          {83, 0},
1715          {82, 0},
1716          {81, 0},
1717          {80, 0},
1718          {79, 0},
1719          {78, 0},
1720          {77, 0},
1721          {76, 0},
1722          {75, 0},
1723          {74, 0},
1724          {73, 0},
1725          {72, 0},
1726          {71, 0},
1727          {70, 0},
1728          {69, 0},
1729          {68, 0},
1730          {67, 0},
1731          {66, 0},
1732          {65, 0},
1733          {64, 0},
1734          {63, 0},
1735          {62, 0},
1736          {61, 0},
1737          {60, 0},
1738          {59, 0},
1739          }
1740 };
1741
1742 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1743                                     u8 is_fat, u8 ctrl_chan_high,
1744                                     struct iwl4965_tx_power_db *tx_power_tbl)
1745 {
1746         u8 saturation_power;
1747         s32 target_power;
1748         s32 user_target_power;
1749         s32 power_limit;
1750         s32 current_temp;
1751         s32 reg_limit;
1752         s32 current_regulatory;
1753         s32 txatten_grp = CALIB_CH_GROUP_MAX;
1754         int i;
1755         int c;
1756         const struct iwl_channel_info *ch_info = NULL;
1757         struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1758         const struct iwl_eeprom_calib_measure *measurement;
1759         s16 voltage;
1760         s32 init_voltage;
1761         s32 voltage_compensation;
1762         s32 degrees_per_05db_num;
1763         s32 degrees_per_05db_denom;
1764         s32 factory_temp;
1765         s32 temperature_comp[2];
1766         s32 factory_gain_index[2];
1767         s32 factory_actual_pwr[2];
1768         s32 power_index;
1769
1770         /* Sanity check requested level (dBm) */
1771         if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1772                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1773                             priv->user_txpower_limit);
1774                 return -EINVAL;
1775         }
1776         if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1777                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1778                             priv->user_txpower_limit);
1779                 return -EINVAL;
1780         }
1781
1782         /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1783          *   are used for indexing into txpower table) */
1784         user_target_power = 2 * priv->user_txpower_limit;
1785
1786         /* Get current (RXON) channel, band, width */
1787         ch_info =
1788                 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1789
1790         IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1791                           is_fat);
1792
1793         if (!ch_info)
1794                 return -EINVAL;
1795
1796         /* get txatten group, used to select 1) thermal txpower adjustment
1797          *   and 2) mimo txpower balance between Tx chains. */
1798         txatten_grp = iwl4965_get_tx_atten_grp(channel);
1799         if (txatten_grp < 0)
1800                 return -EINVAL;
1801
1802         IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1803                           channel, txatten_grp);
1804
1805         if (is_fat) {
1806                 if (ctrl_chan_high)
1807                         channel -= 2;
1808                 else
1809                         channel += 2;
1810         }
1811
1812         /* hardware txpower limits ...
1813          * saturation (clipping distortion) txpowers are in half-dBm */
1814         if (band)
1815                 saturation_power = priv->calib_info->saturation_power24;
1816         else
1817                 saturation_power = priv->calib_info->saturation_power52;
1818
1819         if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1820             saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1821                 if (band)
1822                         saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1823                 else
1824                         saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1825         }
1826
1827         /* regulatory txpower limits ... reg_limit values are in half-dBm,
1828          *   max_power_avg values are in dBm, convert * 2 */
1829         if (is_fat)
1830                 reg_limit = ch_info->fat_max_power_avg * 2;
1831         else
1832                 reg_limit = ch_info->max_power_avg * 2;
1833
1834         if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1835             (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1836                 if (band)
1837                         reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1838                 else
1839                         reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1840         }
1841
1842         /* Interpolate txpower calibration values for this channel,
1843          *   based on factory calibration tests on spaced channels. */
1844         iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1845
1846         /* calculate tx gain adjustment based on power supply voltage */
1847         voltage = priv->calib_info->voltage;
1848         init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1849         voltage_compensation =
1850             iwl4965_get_voltage_compensation(voltage, init_voltage);
1851
1852         IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1853                           init_voltage,
1854                           voltage, voltage_compensation);
1855
1856         /* get current temperature (Celsius) */
1857         current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1858         current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1859         current_temp = KELVIN_TO_CELSIUS(current_temp);
1860
1861         /* select thermal txpower adjustment params, based on channel group
1862          *   (same frequency group used for mimo txatten adjustment) */
1863         degrees_per_05db_num =
1864             tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1865         degrees_per_05db_denom =
1866             tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1867
1868         /* get per-chain txpower values from factory measurements */
1869         for (c = 0; c < 2; c++) {
1870                 measurement = &ch_eeprom_info.measurements[c][1];
1871
1872                 /* txgain adjustment (in half-dB steps) based on difference
1873                  *   between factory and current temperature */
1874                 factory_temp = measurement->temperature;
1875                 iwl4965_math_div_round((current_temp - factory_temp) *
1876                                        degrees_per_05db_denom,
1877                                        degrees_per_05db_num,
1878                                        &temperature_comp[c]);
1879
1880                 factory_gain_index[c] = measurement->gain_idx;
1881                 factory_actual_pwr[c] = measurement->actual_pow;
1882
1883                 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1884                 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1885                                   "curr tmp %d, comp %d steps\n",
1886                                   factory_temp, current_temp,
1887                                   temperature_comp[c]);
1888
1889                 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1890                                   factory_gain_index[c],
1891                                   factory_actual_pwr[c]);
1892         }
1893
1894         /* for each of 33 bit-rates (including 1 for CCK) */
1895         for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1896                 u8 is_mimo_rate;
1897                 union iwl4965_tx_power_dual_stream tx_power;
1898
1899                 /* for mimo, reduce each chain's txpower by half
1900                  * (3dB, 6 steps), so total output power is regulatory
1901                  * compliant. */
1902                 if (i & 0x8) {
1903                         current_regulatory = reg_limit -
1904                             IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1905                         is_mimo_rate = 1;
1906                 } else {
1907                         current_regulatory = reg_limit;
1908                         is_mimo_rate = 0;
1909                 }
1910
1911                 /* find txpower limit, either hardware or regulatory */
1912                 power_limit = saturation_power - back_off_table[i];
1913                 if (power_limit > current_regulatory)
1914                         power_limit = current_regulatory;
1915
1916                 /* reduce user's txpower request if necessary
1917                  * for this rate on this channel */
1918                 target_power = user_target_power;
1919                 if (target_power > power_limit)
1920                         target_power = power_limit;
1921
1922                 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1923                                   i, saturation_power - back_off_table[i],
1924                                   current_regulatory, user_target_power,
1925                                   target_power);
1926
1927                 /* for each of 2 Tx chains (radio transmitters) */
1928                 for (c = 0; c < 2; c++) {
1929                         s32 atten_value;
1930
1931                         if (is_mimo_rate)
1932                                 atten_value =
1933                                     (s32)le32_to_cpu(priv->card_alive_init.
1934                                     tx_atten[txatten_grp][c]);
1935                         else
1936                                 atten_value = 0;
1937
1938                         /* calculate index; higher index means lower txpower */
1939                         power_index = (u8) (factory_gain_index[c] -
1940                                             (target_power -
1941                                              factory_actual_pwr[c]) -
1942                                             temperature_comp[c] -
1943                                             voltage_compensation +
1944                                             atten_value);
1945
1946 /*                      IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1947                                                 power_index); */
1948
1949                         if (power_index < get_min_power_index(i, band))
1950                                 power_index = get_min_power_index(i, band);
1951
1952                         /* adjust 5 GHz index to support negative indexes */
1953                         if (!band)
1954                                 power_index += 9;
1955
1956                         /* CCK, rate 32, reduce txpower for CCK */
1957                         if (i == POWER_TABLE_CCK_ENTRY)
1958                                 power_index +=
1959                                     IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1960
1961                         /* stay within the table! */
1962                         if (power_index > 107) {
1963                                 IWL_WARNING("txpower index %d > 107\n",
1964                                             power_index);
1965                                 power_index = 107;
1966                         }
1967                         if (power_index < 0) {
1968                                 IWL_WARNING("txpower index %d < 0\n",
1969                                             power_index);
1970                                 power_index = 0;
1971                         }
1972
1973                         /* fill txpower command for this rate/chain */
1974                         tx_power.s.radio_tx_gain[c] =
1975                                 gain_table[band][power_index].radio;
1976                         tx_power.s.dsp_predis_atten[c] =
1977                                 gain_table[band][power_index].dsp;
1978
1979                         IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1980                                           "gain 0x%02x dsp %d\n",
1981                                           c, atten_value, power_index,
1982                                         tx_power.s.radio_tx_gain[c],
1983                                         tx_power.s.dsp_predis_atten[c]);
1984                 }/* for each chain */
1985
1986                 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1987
1988         }/* for each rate */
1989
1990         return 0;
1991 }
1992
1993 /**
1994  * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
1995  *
1996  * Uses the active RXON for channel, band, and characteristics (fat, high)
1997  * The power limit is taken from priv->user_txpower_limit.
1998  */
1999 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
2000 {
2001         struct iwl4965_txpowertable_cmd cmd = { 0 };
2002         int ret;
2003         u8 band = 0;
2004         u8 is_fat = 0;
2005         u8 ctrl_chan_high = 0;
2006
2007         if (test_bit(STATUS_SCANNING, &priv->status)) {
2008                 /* If this gets hit a lot, switch it to a BUG() and catch
2009                  * the stack trace to find out who is calling this during
2010                  * a scan. */
2011                 IWL_WARNING("TX Power requested while scanning!\n");
2012                 return -EAGAIN;
2013         }
2014
2015         band = priv->band == IEEE80211_BAND_2GHZ;
2016
2017         is_fat =  is_fat_channel(priv->active_rxon.flags);
2018
2019         if (is_fat &&
2020             (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2021                 ctrl_chan_high = 1;
2022
2023         cmd.band = band;
2024         cmd.channel = priv->active_rxon.channel;
2025
2026         ret = iwl4965_fill_txpower_tbl(priv, band,
2027                                 le16_to_cpu(priv->active_rxon.channel),
2028                                 is_fat, ctrl_chan_high, &cmd.tx_power);
2029         if (ret)
2030                 goto out;
2031
2032         ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2033
2034 out:
2035         return ret;
2036 }
2037
2038 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2039 {
2040         int ret = 0;
2041         struct iwl4965_rxon_assoc_cmd rxon_assoc;
2042         const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2043         const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2044
2045         if ((rxon1->flags == rxon2->flags) &&
2046             (rxon1->filter_flags == rxon2->filter_flags) &&
2047             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2048             (rxon1->ofdm_ht_single_stream_basic_rates ==
2049              rxon2->ofdm_ht_single_stream_basic_rates) &&
2050             (rxon1->ofdm_ht_dual_stream_basic_rates ==
2051              rxon2->ofdm_ht_dual_stream_basic_rates) &&
2052             (rxon1->rx_chain == rxon2->rx_chain) &&
2053             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2054                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
2055                 return 0;
2056         }
2057
2058         rxon_assoc.flags = priv->staging_rxon.flags;
2059         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2060         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2061         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2062         rxon_assoc.reserved = 0;
2063         rxon_assoc.ofdm_ht_single_stream_basic_rates =
2064             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2065         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2066             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2067         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2068
2069         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2070                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
2071         if (ret)
2072                 return ret;
2073
2074         return ret;
2075 }
2076
2077
2078 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2079 {
2080         int rc;
2081         u8 band = 0;
2082         u8 is_fat = 0;
2083         u8 ctrl_chan_high = 0;
2084         struct iwl4965_channel_switch_cmd cmd = { 0 };
2085         const struct iwl_channel_info *ch_info;
2086
2087         band = priv->band == IEEE80211_BAND_2GHZ;
2088
2089         ch_info = iwl_get_channel_info(priv, priv->band, channel);
2090
2091         is_fat = is_fat_channel(priv->staging_rxon.flags);
2092
2093         if (is_fat &&
2094             (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2095                 ctrl_chan_high = 1;
2096
2097         cmd.band = band;
2098         cmd.expect_beacon = 0;
2099         cmd.channel = cpu_to_le16(channel);
2100         cmd.rxon_flags = priv->active_rxon.flags;
2101         cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2102         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2103         if (ch_info)
2104                 cmd.expect_beacon = is_channel_radar(ch_info);
2105         else
2106                 cmd.expect_beacon = 1;
2107
2108         rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2109                                       ctrl_chan_high, &cmd.tx_power);
2110         if (rc) {
2111                 IWL_DEBUG_11H("error:%d  fill txpower_tbl\n", rc);
2112                 return rc;
2113         }
2114
2115         rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
2116         return rc;
2117 }
2118
2119 #define RTS_HCCA_RETRY_LIMIT            3
2120 #define RTS_DFAULT_RETRY_LIMIT          60
2121
2122 void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2123                               struct iwl_cmd *cmd,
2124                               struct ieee80211_tx_control *ctrl,
2125                               struct ieee80211_hdr *hdr, int sta_id,
2126                               int is_hcca)
2127 {
2128         struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2129         u8 rts_retry_limit = 0;
2130         u8 data_retry_limit = 0;
2131         u16 fc = le16_to_cpu(hdr->frame_control);
2132         u8 rate_plcp;
2133         u16 rate_flags = 0;
2134         int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2135
2136         rate_plcp = iwl4965_rates[rate_idx].plcp;
2137
2138         rts_retry_limit = (is_hcca) ?
2139             RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2140
2141         if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2142                 rate_flags |= RATE_MCS_CCK_MSK;
2143
2144
2145         if (ieee80211_is_probe_response(fc)) {
2146                 data_retry_limit = 3;
2147                 if (data_retry_limit < rts_retry_limit)
2148                         rts_retry_limit = data_retry_limit;
2149         } else
2150                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2151
2152         if (priv->data_retry_limit != -1)
2153                 data_retry_limit = priv->data_retry_limit;
2154
2155
2156         if (ieee80211_is_data(fc)) {
2157                 tx->initial_rate_index = 0;
2158                 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2159         } else {
2160                 switch (fc & IEEE80211_FCTL_STYPE) {
2161                 case IEEE80211_STYPE_AUTH:
2162                 case IEEE80211_STYPE_DEAUTH:
2163                 case IEEE80211_STYPE_ASSOC_REQ:
2164                 case IEEE80211_STYPE_REASSOC_REQ:
2165                         if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2166                                 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2167                                 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
2168                         }
2169                         break;
2170                 default:
2171                         break;
2172                 }
2173
2174                 /* Alternate between antenna A and B for successive frames */
2175                 if (priv->use_ant_b_for_management_frame) {
2176                         priv->use_ant_b_for_management_frame = 0;
2177                         rate_flags |= RATE_MCS_ANT_B_MSK;
2178                 } else {
2179                         priv->use_ant_b_for_management_frame = 1;
2180                         rate_flags |= RATE_MCS_ANT_A_MSK;
2181                 }
2182         }
2183
2184         tx->rts_retry_limit = rts_retry_limit;
2185         tx->data_retry_limit = data_retry_limit;
2186         tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
2187 }
2188
2189 int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
2190 {
2191         struct iwl4965_shared *s = priv->shared_virt;
2192         return le32_to_cpu(s->rb_closed) & 0xFFF;
2193 }
2194
2195 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
2196 {
2197         return priv->temperature;
2198 }
2199
2200 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
2201                           struct iwl4965_frame *frame, u8 rate)
2202 {
2203         struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
2204         unsigned int frame_size;
2205
2206         tx_beacon_cmd = &frame->u.beacon;
2207         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2208
2209         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2210         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2211
2212         frame_size = iwl4965_fill_beacon_frame(priv,
2213                                 tx_beacon_cmd->frame,
2214                                 iwl4965_broadcast_addr,
2215                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2216
2217         BUG_ON(frame_size > MAX_MPDU_SIZE);
2218         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2219
2220         if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2221                 tx_beacon_cmd->tx.rate_n_flags =
2222                         iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
2223         else
2224                 tx_beacon_cmd->tx.rate_n_flags =
2225                         iwl4965_hw_set_rate_n_flags(rate, 0);
2226
2227         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2228                                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2229         return (sizeof(*tx_beacon_cmd) + frame_size);
2230 }
2231
2232 /*
2233  * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2234  * given Tx queue, and enable the DMA channel used for that queue.
2235  *
2236  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2237  * channels supported in hardware.
2238  */
2239 int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2240 {
2241         int rc;
2242         unsigned long flags;
2243         int txq_id = txq->q.id;
2244
2245         spin_lock_irqsave(&priv->lock, flags);
2246         rc = iwl_grab_nic_access(priv);
2247         if (rc) {
2248                 spin_unlock_irqrestore(&priv->lock, flags);
2249                 return rc;
2250         }
2251
2252         /* Circular buffer (TFD queue in DRAM) physical base address */
2253         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2254                              txq->q.dma_addr >> 8);
2255
2256         /* Enable DMA channel, using same id as for TFD queue */
2257         iwl_write_direct32(
2258                 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2259                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2260                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2261         iwl_release_nic_access(priv);
2262         spin_unlock_irqrestore(&priv->lock, flags);
2263
2264         return 0;
2265 }
2266
2267 int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
2268                                  dma_addr_t addr, u16 len)
2269 {
2270         int index, is_odd;
2271         struct iwl4965_tfd_frame *tfd = ptr;
2272         u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2273
2274         /* Each TFD can point to a maximum 20 Tx buffers */
2275         if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2276                 IWL_ERROR("Error can not send more than %d chunks\n",
2277                           MAX_NUM_OF_TBS);
2278                 return -EINVAL;
2279         }
2280
2281         index = num_tbs / 2;
2282         is_odd = num_tbs & 0x1;
2283
2284         if (!is_odd) {
2285                 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2286                 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
2287                              iwl_get_dma_hi_address(addr));
2288                 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2289         } else {
2290                 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2291                              (u32) (addr & 0xffff));
2292                 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2293                 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2294         }
2295
2296         IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2297
2298         return 0;
2299 }
2300
2301 static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
2302 {
2303         u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
2304
2305         IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2306                        ((hw_version >> 8) & 0x0F),
2307                        ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2308
2309         IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2310                        &priv->eeprom[EEPROM_4965_BOARD_PBA]);
2311 }
2312
2313 static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
2314 {
2315         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
2316                                         sizeof(struct iwl4965_shared),
2317                                         &priv->shared_phys);
2318         if (!priv->shared_virt)
2319                 return -ENOMEM;
2320
2321         memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
2322
2323         return 0;
2324 }
2325
2326 static void iwl4965_free_shared_mem(struct iwl_priv *priv)
2327 {
2328         if (priv->shared_virt)
2329                 pci_free_consistent(priv->pci_dev,
2330                                     sizeof(struct iwl4965_shared),
2331                                     priv->shared_virt,
2332                                     priv->shared_phys);
2333 }
2334
2335 /**
2336  * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2337  */
2338 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2339                                             struct iwl4965_tx_queue *txq,
2340                                             u16 byte_cnt)
2341 {
2342         int len;
2343         int txq_id = txq->q.id;
2344         struct iwl4965_shared *shared_data = priv->shared_virt;
2345
2346         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2347
2348         /* Set up byte count within first 256 entries */
2349         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2350                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
2351
2352         /* If within first 64 entries, duplicate at end */
2353         if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
2354                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2355                         tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
2356                         byte_cnt, len);
2357 }
2358
2359 /**
2360  * sign_extend - Sign extend a value using specified bit as sign-bit
2361  *
2362  * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2363  * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2364  *
2365  * @param oper value to sign extend
2366  * @param index 0 based bit index (0<=index<32) to sign bit
2367  */
2368 static s32 sign_extend(u32 oper, int index)
2369 {
2370         u8 shift = 31 - index;
2371
2372         return (s32)(oper << shift) >> shift;
2373 }
2374
2375 /**
2376  * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2377  * @statistics: Provides the temperature reading from the uCode
2378  *
2379  * A return of <0 indicates bogus data in the statistics
2380  */
2381 int iwl4965_get_temperature(const struct iwl_priv *priv)
2382 {
2383         s32 temperature;
2384         s32 vt;
2385         s32 R1, R2, R3;
2386         u32 R4;
2387
2388         if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2389                 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2390                 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2391                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2392                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2393                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2394                 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2395         } else {
2396                 IWL_DEBUG_TEMP("Running temperature calibration\n");
2397                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2398                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2399                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2400                 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2401         }
2402
2403         /*
2404          * Temperature is only 23 bits, so sign extend out to 32.
2405          *
2406          * NOTE If we haven't received a statistics notification yet
2407          * with an updated temperature, use R4 provided to us in the
2408          * "initialize" ALIVE response.
2409          */
2410         if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2411                 vt = sign_extend(R4, 23);
2412         else
2413                 vt = sign_extend(
2414                         le32_to_cpu(priv->statistics.general.temperature), 23);
2415
2416         IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2417                        R1, R2, R3, vt);
2418
2419         if (R3 == R1) {
2420                 IWL_ERROR("Calibration conflict R1 == R3\n");
2421                 return -1;
2422         }
2423
2424         /* Calculate temperature in degrees Kelvin, adjust by 97%.
2425          * Add offset to center the adjustment around 0 degrees Centigrade. */
2426         temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2427         temperature /= (R3 - R1);
2428         temperature = (temperature * 97) / 100 +
2429             TEMPERATURE_CALIB_KELVIN_OFFSET;
2430
2431         IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2432             KELVIN_TO_CELSIUS(temperature));
2433
2434         return temperature;
2435 }
2436
2437 /* Adjust Txpower only if temperature variance is greater than threshold. */
2438 #define IWL_TEMPERATURE_THRESHOLD   3
2439
2440 /**
2441  * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2442  *
2443  * If the temperature changed has changed sufficiently, then a recalibration
2444  * is needed.
2445  *
2446  * Assumes caller will replace priv->last_temperature once calibration
2447  * executed.
2448  */
2449 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2450 {
2451         int temp_diff;
2452
2453         if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2454                 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2455                 return 0;
2456         }
2457
2458         temp_diff = priv->temperature - priv->last_temperature;
2459
2460         /* get absolute value */
2461         if (temp_diff < 0) {
2462                 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2463                 temp_diff = -temp_diff;
2464         } else if (temp_diff == 0)
2465                 IWL_DEBUG_POWER("Same temp, \n");
2466         else
2467                 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2468
2469         if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2470                 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2471                 return 0;
2472         }
2473
2474         IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2475
2476         return 1;
2477 }
2478
2479 /* Calculate noise level, based on measurements during network silence just
2480  *   before arriving beacon.  This measurement can be done only if we know
2481  *   exactly when to expect beacons, therefore only when we're associated. */
2482 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2483 {
2484         struct statistics_rx_non_phy *rx_info
2485                                 = &(priv->statistics.rx.general);
2486         int num_active_rx = 0;
2487         int total_silence = 0;
2488         int bcn_silence_a =
2489                 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2490         int bcn_silence_b =
2491                 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2492         int bcn_silence_c =
2493                 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2494
2495         if (bcn_silence_a) {
2496                 total_silence += bcn_silence_a;
2497                 num_active_rx++;
2498         }
2499         if (bcn_silence_b) {
2500                 total_silence += bcn_silence_b;
2501                 num_active_rx++;
2502         }
2503         if (bcn_silence_c) {
2504                 total_silence += bcn_silence_c;
2505                 num_active_rx++;
2506         }
2507
2508         /* Average among active antennas */
2509         if (num_active_rx)
2510                 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2511         else
2512                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2513
2514         IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2515                         bcn_silence_a, bcn_silence_b, bcn_silence_c,
2516                         priv->last_rx_noise);
2517 }
2518
2519 void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
2520                               struct iwl_rx_mem_buffer *rxb)
2521 {
2522         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2523         int change;
2524         s32 temp;
2525
2526         IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2527                      (int)sizeof(priv->statistics), pkt->len);
2528
2529         change = ((priv->statistics.general.temperature !=
2530                    pkt->u.stats.general.temperature) ||
2531                   ((priv->statistics.flag &
2532                     STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2533                    (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2534
2535         memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2536
2537         set_bit(STATUS_STATISTICS, &priv->status);
2538
2539         /* Reschedule the statistics timer to occur in
2540          * REG_RECALIB_PERIOD seconds to ensure we get a
2541          * thermal update even if the uCode doesn't give
2542          * us one */
2543         mod_timer(&priv->statistics_periodic, jiffies +
2544                   msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2545
2546         if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2547             (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2548                 iwl4965_rx_calc_noise(priv);
2549 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2550                 queue_work(priv->workqueue, &priv->sensitivity_work);
2551 #endif
2552         }
2553
2554         iwl_leds_background(priv);
2555
2556         /* If the hardware hasn't reported a change in
2557          * temperature then don't bother computing a
2558          * calibrated temperature value */
2559         if (!change)
2560                 return;
2561
2562         temp = iwl4965_get_temperature(priv);
2563         if (temp < 0)
2564                 return;
2565
2566         if (priv->temperature != temp) {
2567                 if (priv->temperature)
2568                         IWL_DEBUG_TEMP("Temperature changed "
2569                                        "from %dC to %dC\n",
2570                                        KELVIN_TO_CELSIUS(priv->temperature),
2571                                        KELVIN_TO_CELSIUS(temp));
2572                 else
2573                         IWL_DEBUG_TEMP("Temperature "
2574                                        "initialized to %dC\n",
2575                                        KELVIN_TO_CELSIUS(temp));
2576         }
2577
2578         priv->temperature = temp;
2579         set_bit(STATUS_TEMPERATURE, &priv->status);
2580
2581         if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2582                      iwl4965_is_temp_calib_needed(priv))
2583                 queue_work(priv->workqueue, &priv->txpower_work);
2584 }
2585
2586 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2587                                  struct sk_buff *skb,
2588                                  struct iwl4965_rx_phy_res *rx_start,
2589                                  struct ieee80211_rx_status *stats,
2590                                  u32 ampdu_status)
2591 {
2592         s8 signal = stats->ssi;
2593         s8 noise = 0;
2594         int rate = stats->rate_idx;
2595         u64 tsf = stats->mactime;
2596         __le16 antenna;
2597         __le16 phy_flags_hw = rx_start->phy_flags;
2598         struct iwl4965_rt_rx_hdr {
2599                 struct ieee80211_radiotap_header rt_hdr;
2600                 __le64 rt_tsf;          /* TSF */
2601                 u8 rt_flags;            /* radiotap packet flags */
2602                 u8 rt_rate;             /* rate in 500kb/s */
2603                 __le16 rt_channelMHz;   /* channel in MHz */
2604                 __le16 rt_chbitmask;    /* channel bitfield */
2605                 s8 rt_dbmsignal;        /* signal in dBm, kluged to signed */
2606                 s8 rt_dbmnoise;
2607                 u8 rt_antenna;          /* antenna number */
2608         } __attribute__ ((packed)) *iwl4965_rt;
2609
2610         /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2611         if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2612                 if (net_ratelimit())
2613                         printk(KERN_ERR "not enough headroom [%d] for "
2614                                "radiotap head [%zd]\n",
2615                                skb_headroom(skb), sizeof(*iwl4965_rt));
2616                 return;
2617         }
2618
2619         /* put radiotap header in front of 802.11 header and data */
2620         iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2621
2622         /* initialise radiotap header */
2623         iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2624         iwl4965_rt->rt_hdr.it_pad = 0;
2625
2626         /* total header + data */
2627         put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2628                       &iwl4965_rt->rt_hdr.it_len);
2629
2630         /* Indicate all the fields we add to the radiotap header */
2631         put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2632                                   (1 << IEEE80211_RADIOTAP_FLAGS) |
2633                                   (1 << IEEE80211_RADIOTAP_RATE) |
2634                                   (1 << IEEE80211_RADIOTAP_CHANNEL) |
2635                                   (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2636                                   (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2637                                   (1 << IEEE80211_RADIOTAP_ANTENNA)),
2638                       &iwl4965_rt->rt_hdr.it_present);
2639
2640         /* Zero the flags, we'll add to them as we go */
2641         iwl4965_rt->rt_flags = 0;
2642
2643         put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2644
2645         iwl4965_rt->rt_dbmsignal = signal;
2646         iwl4965_rt->rt_dbmnoise = noise;
2647
2648         /* Convert the channel frequency and set the flags */
2649         put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2650         if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2651                 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2652                                           IEEE80211_CHAN_5GHZ),
2653                               &iwl4965_rt->rt_chbitmask);
2654         else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2655                 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2656                                           IEEE80211_CHAN_2GHZ),
2657                               &iwl4965_rt->rt_chbitmask);
2658         else    /* 802.11g */
2659                 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2660                                           IEEE80211_CHAN_2GHZ),
2661                               &iwl4965_rt->rt_chbitmask);
2662
2663         if (rate == -1)
2664                 iwl4965_rt->rt_rate = 0;
2665         else
2666                 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2667
2668         /*
2669          * "antenna number"
2670          *
2671          * It seems that the antenna field in the phy flags value
2672          * is actually a bitfield. This is undefined by radiotap,
2673          * it wants an actual antenna number but I always get "7"
2674          * for most legacy frames I receive indicating that the
2675          * same frame was received on all three RX chains.
2676          *
2677          * I think this field should be removed in favour of a
2678          * new 802.11n radiotap field "RX chains" that is defined
2679          * as a bitmask.
2680          */
2681         antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2682         iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2683
2684         /* set the preamble flag if appropriate */
2685         if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2686                 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2687
2688         stats->flag |= RX_FLAG_RADIOTAP;
2689 }
2690
2691 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2692 {
2693         /* 0 - mgmt, 1 - cnt, 2 - data */
2694         int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2695         priv->rx_stats[idx].cnt++;
2696         priv->rx_stats[idx].bytes += len;
2697 }
2698
2699 /*
2700  * returns non-zero if packet should be dropped
2701  */
2702 static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2703                                       struct ieee80211_hdr *hdr,
2704                                       u32 decrypt_res,
2705                                       struct ieee80211_rx_status *stats)
2706 {
2707         u16 fc = le16_to_cpu(hdr->frame_control);
2708
2709         if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2710                 return 0;
2711
2712         if (!(fc & IEEE80211_FCTL_PROTECTED))
2713                 return 0;
2714
2715         IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2716         switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2717         case RX_RES_STATUS_SEC_TYPE_TKIP:
2718                 /* The uCode has got a bad phase 1 Key, pushes the packet.
2719                  * Decryption will be done in SW. */
2720                 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2721                     RX_RES_STATUS_BAD_KEY_TTAK)
2722                         break;
2723
2724                 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2725                     RX_RES_STATUS_BAD_ICV_MIC) {
2726                         /* bad ICV, the packet is destroyed since the
2727                          * decryption is inplace, drop it */
2728                         IWL_DEBUG_RX("Packet destroyed\n");
2729                         return -1;
2730                 }
2731         case RX_RES_STATUS_SEC_TYPE_WEP:
2732         case RX_RES_STATUS_SEC_TYPE_CCMP:
2733                 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2734                     RX_RES_STATUS_DECRYPT_OK) {
2735                         IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2736                         stats->flag |= RX_FLAG_DECRYPTED;
2737                 }
2738                 break;
2739
2740         default:
2741                 break;
2742         }
2743         return 0;
2744 }
2745
2746 static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
2747 {
2748         u32 decrypt_out = 0;
2749
2750         if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2751                                         RX_RES_STATUS_STATION_FOUND)
2752                 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2753                                 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2754
2755         decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2756
2757         /* packet was not encrypted */
2758         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2759                                         RX_RES_STATUS_SEC_TYPE_NONE)
2760                 return decrypt_out;
2761
2762         /* packet was encrypted with unknown alg */
2763         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2764                                         RX_RES_STATUS_SEC_TYPE_ERR)
2765                 return decrypt_out;
2766
2767         /* decryption was not done in HW */
2768         if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2769                                         RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2770                 return decrypt_out;
2771
2772         switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2773
2774         case RX_RES_STATUS_SEC_TYPE_CCMP:
2775                 /* alg is CCM: check MIC only */
2776                 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2777                         /* Bad MIC */
2778                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2779                 else
2780                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2781
2782                 break;
2783
2784         case RX_RES_STATUS_SEC_TYPE_TKIP:
2785                 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2786                         /* Bad TTAK */
2787                         decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2788                         break;
2789                 }
2790                 /* fall through if TTAK OK */
2791         default:
2792                 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2793                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2794                 else
2795                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2796                 break;
2797         };
2798
2799         IWL_DEBUG_RX("decrypt_in:0x%x  decrypt_out = 0x%x\n",
2800                                         decrypt_in, decrypt_out);
2801
2802         return decrypt_out;
2803 }
2804
2805 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
2806                                        int include_phy,
2807                                        struct iwl_rx_mem_buffer *rxb,
2808                                        struct ieee80211_rx_status *stats)
2809 {
2810         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2811         struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2812             (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2813         struct ieee80211_hdr *hdr;
2814         u16 len;
2815         __le32 *rx_end;
2816         unsigned int skblen;
2817         u32 ampdu_status;
2818         u32 ampdu_status_legacy;
2819
2820         if (!include_phy && priv->last_phy_res[0])
2821                 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2822
2823         if (!rx_start) {
2824                 IWL_ERROR("MPDU frame without a PHY data\n");
2825                 return;
2826         }
2827         if (include_phy) {
2828                 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2829                                                rx_start->cfg_phy_cnt);
2830
2831                 len = le16_to_cpu(rx_start->byte_count);
2832
2833                 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2834                                   sizeof(struct iwl4965_rx_phy_res) +
2835                                   rx_start->cfg_phy_cnt + len);
2836
2837         } else {
2838                 struct iwl4965_rx_mpdu_res_start *amsdu =
2839                     (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2840
2841                 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2842                                sizeof(struct iwl4965_rx_mpdu_res_start));
2843                 len =  le16_to_cpu(amsdu->byte_count);
2844                 rx_start->byte_count = amsdu->byte_count;
2845                 rx_end = (__le32 *) (((u8 *) hdr) + len);
2846         }
2847         if (len > priv->hw_params.max_pkt_size || len < 16) {
2848                 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
2849                 return;
2850         }
2851
2852         ampdu_status = le32_to_cpu(*rx_end);
2853         skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2854
2855         if (!include_phy) {
2856                 /* New status scheme, need to translate */
2857                 ampdu_status_legacy = ampdu_status;
2858                 ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
2859         }
2860
2861         /* start from MAC */
2862         skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2863         skb_put(rxb->skb, len); /* end where data ends */
2864
2865         /* We only process data packets if the interface is open */
2866         if (unlikely(!priv->is_open)) {
2867                 IWL_DEBUG_DROP_LIMIT
2868                     ("Dropping packet while interface is not open.\n");
2869                 return;
2870         }
2871
2872         stats->flag = 0;
2873         hdr = (struct ieee80211_hdr *)rxb->skb->data;
2874
2875         /*  in case of HW accelerated crypto and bad decryption, drop */
2876         if (!priv->hw_params.sw_crypto &&
2877             iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
2878                 return;
2879
2880         if (priv->add_radiotap)
2881                 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
2882
2883         iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
2884         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
2885         priv->alloc_rxb_skb--;
2886         rxb->skb = NULL;
2887 }
2888
2889 /* Calc max signal level (dBm) among 3 possible receivers */
2890 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2891                              struct iwl4965_rx_phy_res *rx_resp)
2892 {
2893         /* data from PHY/DSP regarding signal strength, etc.,
2894          *   contents are always there, not configurable by host.  */
2895         struct iwl4965_rx_non_cfg_phy *ncphy =
2896             (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
2897         u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
2898                         >> IWL_AGC_DB_POS;
2899
2900         u32 valid_antennae =
2901             (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
2902                         >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
2903         u8 max_rssi = 0;
2904         u32 i;
2905
2906         /* Find max rssi among 3 possible receivers.
2907          * These values are measured by the digital signal processor (DSP).
2908          * They should stay fairly constant even as the signal strength varies,
2909          *   if the radio's automatic gain control (AGC) is working right.
2910          * AGC value (see below) will provide the "interesting" info. */
2911         for (i = 0; i < 3; i++)
2912                 if (valid_antennae & (1 << i))
2913                         max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2914
2915         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2916                 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2917                 max_rssi, agc);
2918
2919         /* dBm = max_rssi dB - agc dB - constant.
2920          * Higher AGC (higher radio gain) means lower signal. */
2921         return (max_rssi - agc - IWL_RSSI_OFFSET);
2922 }
2923
2924 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
2925 {
2926         unsigned long flags;
2927
2928         spin_lock_irqsave(&priv->sta_lock, flags);
2929         priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
2930         priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
2931         priv->stations[sta_id].sta.sta.modify_mask = 0;
2932         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2933         spin_unlock_irqrestore(&priv->sta_lock, flags);
2934
2935         iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
2936 }
2937
2938 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
2939 {
2940         /* FIXME: need locking over ps_status ??? */
2941         u8 sta_id = iwl_find_station(priv, addr);
2942
2943         if (sta_id != IWL_INVALID_STATION) {
2944                 u8 sta_awake = priv->stations[sta_id].
2945                                 ps_status == STA_PS_STATUS_WAKE;
2946
2947                 if (sta_awake && ps_bit)
2948                         priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
2949                 else if (!sta_awake && !ps_bit) {
2950                         iwl4965_sta_modify_ps_wake(priv, sta_id);
2951                         priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
2952                 }
2953         }
2954 }
2955 #ifdef CONFIG_IWLWIFI_DEBUG
2956
2957 /**
2958  * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
2959  *
2960  * You may hack this function to show different aspects of received frames,
2961  * including selective frame dumps.
2962  * group100 parameter selects whether to show 1 out of 100 good frames.
2963  *
2964  * TODO:  This was originally written for 3945, need to audit for
2965  *        proper operation with 4965.
2966  */
2967 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
2968                       struct iwl_rx_packet *pkt,
2969                       struct ieee80211_hdr *header, int group100)
2970 {
2971         u32 to_us;
2972         u32 print_summary = 0;
2973         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
2974         u32 hundred = 0;
2975         u32 dataframe = 0;
2976         u16 fc;
2977         u16 seq_ctl;
2978         u16 channel;
2979         u16 phy_flags;
2980         int rate_sym;
2981         u16 length;
2982         u16 status;
2983         u16 bcn_tmr;
2984         u32 tsf_low;
2985         u64 tsf;
2986         u8 rssi;
2987         u8 agc;
2988         u16 sig_avg;
2989         u16 noise_diff;
2990         struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
2991         struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
2992         struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
2993         u8 *data = IWL_RX_DATA(pkt);
2994
2995         if (likely(!(priv->debug_level & IWL_DL_RX)))
2996                 return;
2997
2998         /* MAC header */
2999         fc = le16_to_cpu(header->frame_control);
3000         seq_ctl = le16_to_cpu(header->seq_ctrl);
3001
3002         /* metadata */
3003         channel = le16_to_cpu(rx_hdr->channel);
3004         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3005         rate_sym = rx_hdr->rate;
3006         length = le16_to_cpu(rx_hdr->len);
3007
3008         /* end-of-frame status and timestamp */
3009         status = le32_to_cpu(rx_end->status);
3010         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3011         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3012         tsf = le64_to_cpu(rx_end->timestamp);
3013
3014         /* signal statistics */
3015         rssi = rx_stats->rssi;
3016         agc = rx_stats->agc;
3017         sig_avg = le16_to_cpu(rx_stats->sig_avg);
3018         noise_diff = le16_to_cpu(rx_stats->noise_diff);
3019
3020         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3021
3022         /* if data frame is to us and all is good,
3023          *   (optionally) print summary for only 1 out of every 100 */
3024         if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3025             (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3026                 dataframe = 1;
3027                 if (!group100)
3028                         print_summary = 1;      /* print each frame */
3029                 else if (priv->framecnt_to_us < 100) {
3030                         priv->framecnt_to_us++;
3031                         print_summary = 0;
3032                 } else {
3033                         priv->framecnt_to_us = 0;
3034                         print_summary = 1;
3035                         hundred = 1;
3036                 }
3037         } else {
3038                 /* print summary for all other frames */
3039                 print_summary = 1;
3040         }
3041
3042         if (print_summary) {
3043                 char *title;
3044                 int rate_idx;
3045                 u32 bitrate;
3046
3047                 if (hundred)
3048                         title = "100Frames";
3049                 else if (fc & IEEE80211_FCTL_RETRY)
3050                         title = "Retry";
3051                 else if (ieee80211_is_assoc_response(fc))
3052                         title = "AscRsp";
3053                 else if (ieee80211_is_reassoc_response(fc))
3054                         title = "RasRsp";
3055                 else if (ieee80211_is_probe_response(fc)) {
3056                         title = "PrbRsp";
3057                         print_dump = 1; /* dump frame contents */
3058                 } else if (ieee80211_is_beacon(fc)) {
3059                         title = "Beacon";
3060                         print_dump = 1; /* dump frame contents */
3061                 } else if (ieee80211_is_atim(fc))
3062                         title = "ATIM";
3063                 else if (ieee80211_is_auth(fc))
3064                         title = "Auth";
3065                 else if (ieee80211_is_deauth(fc))
3066                         title = "DeAuth";
3067                 else if (ieee80211_is_disassoc(fc))
3068                         title = "DisAssoc";
3069                 else
3070                         title = "Frame";
3071
3072                 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3073                 if (unlikely(rate_idx == -1))
3074                         bitrate = 0;
3075                 else
3076                         bitrate = iwl4965_rates[rate_idx].ieee / 2;
3077
3078                 /* print frame summary.
3079                  * MAC addresses show just the last byte (for brevity),
3080                  *    but you can hack it to show more, if you'd like to. */
3081                 if (dataframe)
3082                         IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3083                                      "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3084                                      title, fc, header->addr1[5],
3085                                      length, rssi, channel, bitrate);
3086                 else {
3087                         /* src/dst addresses assume managed mode */
3088                         IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3089                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
3090                                      "phy=0x%02x, chnl=%d\n",
3091                                      title, fc, header->addr1[5],
3092                                      header->addr3[5], rssi,
3093                                      tsf_low - priv->scan_start_tsf,
3094                                      phy_flags, channel);
3095                 }
3096         }
3097         if (print_dump)
3098                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
3099 }
3100 #else
3101 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3102                                             struct iwl_rx_packet *pkt,
3103                                             struct ieee80211_hdr *header,
3104                                             int group100)
3105 {
3106 }
3107 #endif
3108
3109
3110
3111 /* Called for REPLY_RX (legacy ABG frames), or
3112  * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3113 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3114                                 struct iwl_rx_mem_buffer *rxb)
3115 {
3116         struct ieee80211_hdr *header;
3117         struct ieee80211_rx_status rx_status;
3118         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3119         /* Use phy data (Rx signal strength, etc.) contained within
3120          *   this rx packet for legacy frames,
3121          *   or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3122         int include_phy = (pkt->hdr.cmd == REPLY_RX);
3123         struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3124                 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3125                 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3126         __le32 *rx_end;
3127         unsigned int len = 0;
3128         u16 fc;
3129         u8 network_packet;
3130
3131         rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3132         rx_status.freq =
3133                 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
3134         rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3135                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3136         rx_status.rate_idx =
3137                 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3138         if (rx_status.band == IEEE80211_BAND_5GHZ)
3139                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3140
3141         rx_status.antenna = 0;
3142         rx_status.flag = 0;
3143
3144         if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3145                 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3146                                 rx_start->cfg_phy_cnt);
3147                 return;
3148         }
3149
3150         if (!include_phy) {
3151                 if (priv->last_phy_res[0])
3152                         rx_start = (struct iwl4965_rx_phy_res *)
3153                                 &priv->last_phy_res[1];
3154                 else
3155                         rx_start = NULL;
3156         }
3157
3158         if (!rx_start) {
3159                 IWL_ERROR("MPDU frame without a PHY data\n");
3160                 return;
3161         }
3162
3163         if (include_phy) {
3164                 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3165                                                   + rx_start->cfg_phy_cnt);
3166
3167                 len = le16_to_cpu(rx_start->byte_count);
3168                 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
3169                                   sizeof(struct iwl4965_rx_phy_res) + len);
3170         } else {
3171                 struct iwl4965_rx_mpdu_res_start *amsdu =
3172                         (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3173
3174                 header = (void *)(pkt->u.raw +
3175                         sizeof(struct iwl4965_rx_mpdu_res_start));
3176                 len = le16_to_cpu(amsdu->byte_count);
3177                 rx_end = (__le32 *) (pkt->u.raw +
3178                         sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3179         }
3180
3181         if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3182             !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3183                 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3184                                 le32_to_cpu(*rx_end));
3185                 return;
3186         }
3187
3188         priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3189
3190         /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3191         rx_status.ssi = iwl4965_calc_rssi(priv, rx_start);
3192
3193         /* Meaningful noise values are available only from beacon statistics,
3194          *   which are gathered only when associated, and indicate noise
3195          *   only for the associated network channel ...
3196          * Ignore these noise values while scanning (other channels) */
3197         if (iwl_is_associated(priv) &&
3198             !test_bit(STATUS_SCANNING, &priv->status)) {
3199                 rx_status.noise = priv->last_rx_noise;
3200                 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3201                                                          rx_status.noise);
3202         } else {
3203                 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3204                 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
3205         }
3206
3207         /* Reset beacon noise level if not associated. */
3208         if (!iwl_is_associated(priv))
3209                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3210
3211         /* Set "1" to report good data frames in groups of 100 */
3212         /* FIXME: need to optimze the call: */
3213         iwl4965_dbg_report_frame(priv, pkt, header, 1);
3214
3215         IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3216                               rx_status.ssi, rx_status.noise, rx_status.signal,
3217                               (unsigned long long)rx_status.mactime);
3218
3219         network_packet = iwl4965_is_network_packet(priv, header);
3220         if (network_packet) {
3221                 priv->last_rx_rssi = rx_status.ssi;
3222                 priv->last_beacon_time =  priv->ucode_beacon_time;
3223                 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3224         }
3225
3226         fc = le16_to_cpu(header->frame_control);
3227         switch (fc & IEEE80211_FCTL_FTYPE) {
3228         case IEEE80211_FTYPE_MGMT:
3229                 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3230                         iwl4965_update_ps_mode(priv, fc  & IEEE80211_FCTL_PM,
3231                                                 header->addr2);
3232                 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
3233                 break;
3234
3235         case IEEE80211_FTYPE_CTL:
3236 #ifdef CONFIG_IWL4965_HT
3237                 switch (fc & IEEE80211_FCTL_STYPE) {
3238                 case IEEE80211_STYPE_BACK_REQ:
3239                         IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3240                         iwl4965_handle_data_packet(priv, 0, include_phy,
3241                                                 rxb, &rx_status);
3242                         break;
3243                 default:
3244                         break;
3245                 }
3246 #endif
3247                 break;
3248
3249         case IEEE80211_FTYPE_DATA: {
3250                 DECLARE_MAC_BUF(mac1);
3251                 DECLARE_MAC_BUF(mac2);
3252                 DECLARE_MAC_BUF(mac3);
3253
3254                 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3255                         iwl4965_update_ps_mode(priv, fc  & IEEE80211_FCTL_PM,
3256                                                 header->addr2);
3257
3258                 if (unlikely(!network_packet))
3259                         IWL_DEBUG_DROP("Dropping (non network): "
3260                                        "%s, %s, %s\n",
3261                                        print_mac(mac1, header->addr1),
3262                                        print_mac(mac2, header->addr2),
3263                                        print_mac(mac3, header->addr3));
3264                 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
3265                         IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3266                                        print_mac(mac1, header->addr1),
3267                                        print_mac(mac2, header->addr2),
3268                                        print_mac(mac3, header->addr3));
3269                 else
3270                         iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3271                                                    &rx_status);
3272                 break;
3273         }
3274         default:
3275                 break;
3276
3277         }
3278 }
3279
3280 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3281  * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
3282 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
3283                                     struct iwl_rx_mem_buffer *rxb)
3284 {
3285         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3286         priv->last_phy_res[0] = 1;
3287         memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3288                sizeof(struct iwl4965_rx_phy_res));
3289 }
3290 static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
3291                                            struct iwl_rx_mem_buffer *rxb)
3292
3293 {
3294 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3295         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3296         struct iwl4965_missed_beacon_notif *missed_beacon;
3297
3298         missed_beacon = &pkt->u.missed_beacon;
3299         if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3300                 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3301                     le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3302                     le32_to_cpu(missed_beacon->total_missed_becons),
3303                     le32_to_cpu(missed_beacon->num_recvd_beacons),
3304                     le32_to_cpu(missed_beacon->num_expected_beacons));
3305                 if (!test_bit(STATUS_SCANNING, &priv->status))
3306                         iwl_init_sensitivity(priv);
3307         }
3308 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
3309 }
3310 #ifdef CONFIG_IWL4965_HT
3311
3312 /**
3313  * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3314  */
3315 static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
3316                                          int sta_id, int tid)
3317 {
3318         unsigned long flags;
3319
3320         /* Remove "disable" flag, to enable Tx for this TID */
3321         spin_lock_irqsave(&priv->sta_lock, flags);
3322         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3323         priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3324         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3325         spin_unlock_irqrestore(&priv->sta_lock, flags);
3326
3327         iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3328 }
3329
3330 /**
3331  * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3332  *
3333  * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3334  * ACK vs. not.  This gets sent to mac80211, then to rate scaling algo.
3335  */
3336 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
3337                                                  struct iwl_ht_agg *agg,
3338                                                  struct iwl4965_compressed_ba_resp*
3339                                                  ba_resp)
3340
3341 {
3342         int i, sh, ack;
3343         u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3344         u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3345         u64 bitmap;
3346         int successes = 0;
3347         struct ieee80211_tx_status *tx_status;
3348
3349         if (unlikely(!agg->wait_for_ba))  {
3350                 IWL_ERROR("Received BA when not expected\n");
3351                 return -EINVAL;
3352         }
3353
3354         /* Mark that the expected block-ack response arrived */
3355         agg->wait_for_ba = 0;
3356         IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
3357
3358         /* Calculate shift to align block-ack bits with our Tx window bits */
3359         sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
3360         if (sh < 0) /* tbw something is wrong with indices */
3361                 sh += 0x100;
3362
3363         /* don't use 64-bit values for now */
3364         bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
3365
3366         if (agg->frame_count > (64 - sh)) {
3367                 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3368                 return -1;
3369         }
3370
3371         /* check for success or failure according to the
3372          * transmitted bitmap and block-ack bitmap */
3373         bitmap &= agg->bitmap;
3374
3375         /* For each frame attempted in aggregation,
3376          * update driver's record of tx frame's status. */
3377         for (i = 0; i < agg->frame_count ; i++) {
3378                 ack = bitmap & (1 << i);
3379                 successes += !!ack;
3380                 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
3381                         ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3382                         agg->start_idx + i);
3383         }
3384
3385         tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3386         tx_status->flags = IEEE80211_TX_STATUS_ACK;
3387         tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3388         tx_status->ampdu_ack_map = successes;
3389         tx_status->ampdu_ack_len = agg->frame_count;
3390         iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3391                                      &tx_status->control);
3392
3393         IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
3394
3395         return 0;
3396 }
3397
3398 /**
3399  * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3400  */
3401 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
3402                                             u16 txq_id)
3403 {
3404         /* Simply stop the queue, but don't change any configuration;
3405          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3406         iwl_write_prph(priv,
3407                 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
3408                 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3409                 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3410 }
3411
3412 /**
3413  * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3414  * priv->lock must be held by the caller
3415  */
3416 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
3417                                         u16 ssn_idx, u8 tx_fifo)
3418 {
3419         int ret = 0;
3420
3421         if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3422                 IWL_WARNING("queue number too small: %d, must be > %d\n",
3423                                 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3424                 return -EINVAL;
3425         }
3426
3427         ret = iwl_grab_nic_access(priv);
3428         if (ret)
3429                 return ret;
3430
3431         iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3432
3433         iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3434
3435         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3436         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3437         /* supposes that ssn_idx is valid (!= 0xFFF) */
3438         iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3439
3440         iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3441         iwl4965_txq_ctx_deactivate(priv, txq_id);
3442         iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3443
3444         iwl_release_nic_access(priv);
3445
3446         return 0;
3447 }
3448
3449 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3450                                          u8 tid, int txq_id)
3451 {
3452         struct iwl4965_queue *q = &priv->txq[txq_id].q;
3453         u8 *addr = priv->stations[sta_id].sta.sta.addr;
3454         struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3455
3456         switch (priv->stations[sta_id].tid[tid].agg.state) {
3457         case IWL_EMPTYING_HW_QUEUE_DELBA:
3458                 /* We are reclaiming the last packet of the */
3459                 /* aggregated HW queue */
3460                 if (txq_id  == tid_data->agg.txq_id &&
3461                     q->read_ptr == q->write_ptr) {
3462                         u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3463                         int tx_fifo = default_tid_to_tx_fifo[tid];
3464                         IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3465                         iwl4965_tx_queue_agg_disable(priv, txq_id,
3466                                                      ssn, tx_fifo);
3467                         tid_data->agg.state = IWL_AGG_OFF;
3468                         ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3469                 }
3470                 break;
3471         case IWL_EMPTYING_HW_QUEUE_ADDBA:
3472                 /* We are reclaiming the last packet of the queue */
3473                 if (tid_data->tfds_in_queue == 0) {
3474                         IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3475                         tid_data->agg.state = IWL_AGG_ON;
3476                         ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3477                 }
3478                 break;
3479         }
3480         return 0;
3481 }
3482
3483 /**
3484  * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3485  * @index -- current index
3486  * @n_bd -- total number of entries in queue (s/b power of 2)
3487  */
3488 static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
3489 {
3490         return (index == 0) ? n_bd - 1 : index - 1;
3491 }
3492
3493 /**
3494  * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3495  *
3496  * Handles block-acknowledge notification from device, which reports success
3497  * of frames sent via aggregation.
3498  */
3499 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3500                                            struct iwl_rx_mem_buffer *rxb)
3501 {
3502         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3503         struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3504         int index;
3505         struct iwl4965_tx_queue *txq = NULL;
3506         struct iwl_ht_agg *agg;
3507         DECLARE_MAC_BUF(mac);
3508
3509         /* "flow" corresponds to Tx queue */
3510         u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3511
3512         /* "ssn" is start of block-ack Tx window, corresponds to index
3513          * (in Tx queue's circular buffer) of first TFD/frame in window */
3514         u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3515
3516         if (scd_flow >= priv->hw_params.max_txq_num) {
3517                 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3518                 return;
3519         }
3520
3521         txq = &priv->txq[scd_flow];
3522         agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3523
3524         /* Find index just before block-ack window */
3525         index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3526
3527         /* TODO: Need to get this copy more safely - now good for debug */
3528
3529         IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3530                            "sta_id = %d\n",
3531                            agg->wait_for_ba,
3532                            print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3533                            ba_resp->sta_id);
3534         IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3535                            "%d, scd_ssn = %d\n",
3536                            ba_resp->tid,
3537                            ba_resp->seq_ctl,
3538                            (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3539                            ba_resp->scd_flow,
3540                            ba_resp->scd_ssn);
3541         IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3542                            agg->start_idx,
3543                            (unsigned long long)agg->bitmap);
3544
3545         /* Update driver's record of ACK vs. not for each frame in window */
3546         iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3547
3548         /* Release all TFDs before the SSN, i.e. all TFDs in front of
3549          * block-ack window (we assume that they've been successfully
3550          * transmitted ... if not, it's too late anyway). */
3551         if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3552                 /* calculate mac80211 ampdu sw queue to wake */
3553                 int ampdu_q =
3554                    scd_flow - IWL_BACK_QUEUE_FIRST_ID + priv->hw->queues;
3555                 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3556                 priv->stations[ba_resp->sta_id].
3557                         tid[ba_resp->tid].tfds_in_queue -= freed;
3558                 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3559                         priv->mac80211_registered &&
3560                         agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3561                         ieee80211_wake_queue(priv->hw, ampdu_q);
3562                 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3563                         ba_resp->tid, scd_flow);
3564         }
3565 }
3566
3567 /**
3568  * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3569  */
3570 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3571                                         u16 txq_id)
3572 {
3573         u32 tbl_dw_addr;
3574         u32 tbl_dw;
3575         u16 scd_q2ratid;
3576
3577         scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3578
3579         tbl_dw_addr = priv->scd_base_addr +
3580                         IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3581
3582         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3583
3584         if (txq_id & 0x1)
3585                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3586         else
3587                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3588
3589         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3590
3591         return 0;
3592 }
3593
3594
3595 /**
3596  * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3597  *
3598  * NOTE:  txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3599  *        i.e. it must be one of the higher queues used for aggregation
3600  */
3601 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3602                                        int tx_fifo, int sta_id, int tid,
3603                                        u16 ssn_idx)
3604 {
3605         unsigned long flags;
3606         int rc;
3607         u16 ra_tid;
3608
3609         if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3610                 IWL_WARNING("queue number too small: %d, must be > %d\n",
3611                         txq_id, IWL_BACK_QUEUE_FIRST_ID);
3612
3613         ra_tid = BUILD_RAxTID(sta_id, tid);
3614
3615         /* Modify device's station table to Tx this TID */
3616         iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
3617
3618         spin_lock_irqsave(&priv->lock, flags);
3619         rc = iwl_grab_nic_access(priv);
3620         if (rc) {
3621                 spin_unlock_irqrestore(&priv->lock, flags);
3622                 return rc;
3623         }
3624
3625         /* Stop this Tx queue before configuring it */
3626         iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3627
3628         /* Map receiver-address / traffic-ID to this queue */
3629         iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3630
3631         /* Set this queue as a chain-building queue */
3632         iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3633
3634         /* Place first TFD at index corresponding to start sequence number.
3635          * Assumes that ssn_idx is valid (!= 0xFFF) */
3636         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3637         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3638         iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3639
3640         /* Set up Tx window size and frame limit for this queue */
3641         iwl_write_targ_mem(priv,
3642                 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3643                 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3644                 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3645
3646         iwl_write_targ_mem(priv, priv->scd_base_addr +
3647                 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3648                 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3649                 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3650
3651         iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3652
3653         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3654         iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3655
3656         iwl_release_nic_access(priv);
3657         spin_unlock_irqrestore(&priv->lock, flags);
3658
3659         return 0;
3660 }
3661
3662 #endif /* CONFIG_IWL4965_HT */
3663
3664 /**
3665  * iwl4965_add_station - Initialize a station's hardware rate table
3666  *
3667  * The uCode's station table contains a table of fallback rates
3668  * for automatic fallback during transmission.
3669  *
3670  * NOTE: This sets up a default set of values.  These will be replaced later
3671  *       if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3672  *       rc80211_simple.
3673  *
3674  * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3675  *       calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3676  *       which requires station table entry to exist).
3677  */
3678 void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
3679 {
3680         int i, r;
3681         struct iwl_link_quality_cmd link_cmd = {
3682                 .reserved1 = 0,
3683         };
3684         u16 rate_flags;
3685
3686         /* Set up the rate scaling to start at selected rate, fall back
3687          * all the way down to 1M in IEEE order, and then spin on 1M */
3688         if (is_ap)
3689                 r = IWL_RATE_54M_INDEX;
3690         else if (priv->band == IEEE80211_BAND_5GHZ)
3691                 r = IWL_RATE_6M_INDEX;
3692         else
3693                 r = IWL_RATE_1M_INDEX;
3694
3695         for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3696                 rate_flags = 0;
3697                 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3698                         rate_flags |= RATE_MCS_CCK_MSK;
3699
3700                 /* Use Tx antenna B only */
3701                 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
3702
3703                 link_cmd.rs_table[i].rate_n_flags =
3704                         iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3705                 r = iwl4965_get_prev_ieee_rate(r);
3706         }
3707
3708         link_cmd.general_params.single_stream_ant_msk = 2;
3709         link_cmd.general_params.dual_stream_ant_msk = 3;
3710         link_cmd.agg_params.agg_dis_start_th = 3;
3711         link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3712
3713         /* Update the rate scaling for control frame Tx to AP */
3714         link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
3715
3716         iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3717                                sizeof(link_cmd), &link_cmd, NULL);
3718 }
3719
3720 #ifdef CONFIG_IWL4965_HT
3721
3722 static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
3723                                        enum ieee80211_band band,
3724                                        u16 channel, u8 extension_chan_offset)
3725 {
3726         const struct iwl_channel_info *ch_info;
3727
3728         ch_info = iwl_get_channel_info(priv, band, channel);
3729         if (!is_channel_valid(ch_info))
3730                 return 0;
3731
3732         if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
3733                 return 0;
3734
3735         if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3736             (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3737                 return 1;
3738
3739         return 0;
3740 }
3741
3742 static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
3743                                 struct ieee80211_ht_info *sta_ht_inf)
3744 {
3745         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
3746
3747         if ((!iwl_ht_conf->is_ht) ||
3748            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
3749            (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
3750                 return 0;
3751
3752         if (sta_ht_inf) {
3753                 if ((!sta_ht_inf->ht_supported) ||
3754                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
3755                         return 0;
3756         }
3757
3758         return (iwl4965_is_channel_extension(priv, priv->band,
3759                                          iwl_ht_conf->control_channel,
3760                                          iwl_ht_conf->extension_chan_offset));
3761 }
3762
3763 void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
3764 {
3765         struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
3766         u32 val;
3767
3768         if (!ht_info->is_ht)
3769                 return;
3770
3771         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
3772         if (iwl4965_is_fat_tx_allowed(priv, NULL))
3773                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3774         else
3775                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3776                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3777
3778         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3779                 IWL_ERROR("control diff than current %d %d\n",
3780                                 le16_to_cpu(rxon->channel),
3781                                 ht_info->control_channel);
3782                 WARN_ON(1);
3783                 return;
3784         }
3785
3786         /* Note: control channel is opposite of extension channel */
3787         switch (ht_info->extension_chan_offset) {
3788         case IWL_EXT_CHANNEL_OFFSET_ABOVE:
3789                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3790                 break;
3791         case IWL_EXT_CHANNEL_OFFSET_BELOW:
3792                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3793                 break;
3794         case IWL_EXT_CHANNEL_OFFSET_NONE:
3795         default:
3796                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3797                 break;
3798         }
3799
3800         val = ht_info->ht_protection;
3801
3802         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
3803
3804         iwl_set_rxon_chain(priv);
3805
3806         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
3807                         "rxon flags 0x%X operation mode :0x%X "
3808                         "extension channel offset 0x%x "
3809                         "control chan %d\n",
3810                         ht_info->supp_mcs_set[0],
3811                         ht_info->supp_mcs_set[1],
3812                         ht_info->supp_mcs_set[2],
3813                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
3814                         ht_info->extension_chan_offset,
3815                         ht_info->control_channel);
3816         return;
3817 }
3818
3819 void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
3820                                 struct ieee80211_ht_info *sta_ht_inf)
3821 {
3822         __le32 sta_flags;
3823         u8 mimo_ps_mode;
3824
3825         if (!sta_ht_inf || !sta_ht_inf->ht_supported)
3826                 goto done;
3827
3828         mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
3829
3830         sta_flags = priv->stations[index].sta.station_flags;
3831
3832         sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
3833
3834         switch (mimo_ps_mode) {
3835         case WLAN_HT_CAP_MIMO_PS_STATIC:
3836                 sta_flags |= STA_FLG_MIMO_DIS_MSK;
3837                 break;
3838         case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
3839                 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
3840                 break;
3841         case WLAN_HT_CAP_MIMO_PS_DISABLED:
3842                 break;
3843         default:
3844                 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
3845                 break;
3846         }
3847
3848         sta_flags |= cpu_to_le32(
3849               (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
3850
3851         sta_flags |= cpu_to_le32(
3852               (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
3853
3854         if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
3855                 sta_flags |= STA_FLG_FAT_EN_MSK;
3856         else
3857                 sta_flags &= ~STA_FLG_FAT_EN_MSK;
3858
3859         priv->stations[index].sta.station_flags = sta_flags;
3860  done:
3861         return;
3862 }
3863
3864 static int iwl4965_rx_agg_start(struct iwl_priv *priv,
3865                                 const u8 *addr, int tid, u16 ssn)
3866 {
3867         unsigned long flags;
3868         int sta_id;
3869
3870         sta_id = iwl_find_station(priv, addr);
3871         if (sta_id == IWL_INVALID_STATION)
3872                 return -ENXIO;
3873
3874         spin_lock_irqsave(&priv->sta_lock, flags);
3875         priv->stations[sta_id].sta.station_flags_msk = 0;
3876         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3877         priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3878         priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3879         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3880         spin_unlock_irqrestore(&priv->sta_lock, flags);
3881
3882         return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
3883                                         CMD_ASYNC);
3884 }
3885
3886 static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
3887                                const u8 *addr, int tid)
3888 {
3889         unsigned long flags;
3890         int sta_id;
3891
3892         sta_id = iwl_find_station(priv, addr);
3893         if (sta_id == IWL_INVALID_STATION)
3894                 return -ENXIO;
3895
3896         spin_lock_irqsave(&priv->sta_lock, flags);
3897         priv->stations[sta_id].sta.station_flags_msk = 0;
3898         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3899         priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3900         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3901         spin_unlock_irqrestore(&priv->sta_lock, flags);
3902
3903         return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
3904                                         CMD_ASYNC);
3905 }
3906
3907 /*
3908  * Find first available (lowest unused) Tx Queue, mark it "active".
3909  * Called only when finding queue for aggregation.
3910  * Should never return anything < 7, because they should already
3911  * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
3912  */
3913 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
3914 {
3915         int txq_id;
3916
3917         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
3918                 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
3919                         return txq_id;
3920         return -1;
3921 }
3922
3923 static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
3924                                 u16 tid, u16 *start_seq_num)
3925 {
3926         struct iwl_priv *priv = hw->priv;
3927         int sta_id;
3928         int tx_fifo;
3929         int txq_id;
3930         int ssn = -1;
3931         int ret = 0;
3932         unsigned long flags;
3933         struct iwl_tid_data *tid_data;
3934         DECLARE_MAC_BUF(mac);
3935
3936         if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3937                 tx_fifo = default_tid_to_tx_fifo[tid];
3938         else
3939                 return -EINVAL;
3940
3941         IWL_WARNING("%s on ra = %s tid = %d\n",
3942                         __func__, print_mac(mac, ra), tid);
3943
3944         sta_id = iwl_find_station(priv, ra);
3945         if (sta_id == IWL_INVALID_STATION)
3946                 return -ENXIO;
3947
3948         if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
3949                 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
3950                 return -ENXIO;
3951         }
3952
3953         txq_id = iwl4965_txq_ctx_activate_free(priv);
3954         if (txq_id == -1)
3955                 return -ENXIO;
3956
3957         spin_lock_irqsave(&priv->sta_lock, flags);
3958         tid_data = &priv->stations[sta_id].tid[tid];
3959         ssn = SEQ_TO_SN(tid_data->seq_number);
3960         tid_data->agg.txq_id = txq_id;
3961         spin_unlock_irqrestore(&priv->sta_lock, flags);
3962
3963         *start_seq_num = ssn;
3964         ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
3965                                           sta_id, tid, ssn);
3966         if (ret)
3967                 return ret;
3968
3969         ret = 0;
3970         if (tid_data->tfds_in_queue == 0) {
3971                 printk(KERN_ERR "HW queue is empty\n");
3972                 tid_data->agg.state = IWL_AGG_ON;
3973                 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
3974         } else {
3975                 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
3976                                 tid_data->tfds_in_queue);
3977                 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
3978         }
3979         return ret;
3980 }
3981
3982 static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
3983 {
3984         struct iwl_priv *priv = hw->priv;
3985         int tx_fifo_id, txq_id, sta_id, ssn = -1;
3986         struct iwl_tid_data *tid_data;
3987         int ret, write_ptr, read_ptr;
3988         unsigned long flags;
3989         DECLARE_MAC_BUF(mac);
3990
3991         if (!ra) {
3992                 IWL_ERROR("ra = NULL\n");
3993                 return -EINVAL;
3994         }
3995
3996         if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3997                 tx_fifo_id = default_tid_to_tx_fifo[tid];
3998         else
3999                 return -EINVAL;
4000
4001         sta_id = iwl_find_station(priv, ra);
4002
4003         if (sta_id == IWL_INVALID_STATION)
4004                 return -ENXIO;
4005
4006         if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4007                 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4008
4009         tid_data = &priv->stations[sta_id].tid[tid];
4010         ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4011         txq_id = tid_data->agg.txq_id;
4012         write_ptr = priv->txq[txq_id].q.write_ptr;
4013         read_ptr = priv->txq[txq_id].q.read_ptr;
4014
4015         /* The queue is not empty */
4016         if (write_ptr != read_ptr) {
4017                 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4018                 priv->stations[sta_id].tid[tid].agg.state =
4019                                 IWL_EMPTYING_HW_QUEUE_DELBA;
4020                 return 0;
4021         }
4022
4023         IWL_DEBUG_HT("HW queue is empty\n");
4024         priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4025
4026         spin_lock_irqsave(&priv->lock, flags);
4027         ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
4028         spin_unlock_irqrestore(&priv->lock, flags);
4029
4030         if (ret)
4031                 return ret;
4032
4033         ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
4034
4035         return 0;
4036 }
4037
4038 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4039                              enum ieee80211_ampdu_mlme_action action,
4040                              const u8 *addr, u16 tid, u16 *ssn)
4041 {
4042         struct iwl_priv *priv = hw->priv;
4043         DECLARE_MAC_BUF(mac);
4044
4045         IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4046                      print_mac(mac, addr), tid);
4047
4048         switch (action) {
4049         case IEEE80211_AMPDU_RX_START:
4050                 IWL_DEBUG_HT("start Rx\n");
4051                 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
4052         case IEEE80211_AMPDU_RX_STOP:
4053                 IWL_DEBUG_HT("stop Rx\n");
4054                 return iwl4965_rx_agg_stop(priv, addr, tid);
4055         case IEEE80211_AMPDU_TX_START:
4056                 IWL_DEBUG_HT("start Tx\n");
4057                 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
4058         case IEEE80211_AMPDU_TX_STOP:
4059                 IWL_DEBUG_HT("stop Tx\n");
4060                 return iwl4965_tx_agg_stop(hw, addr, tid);
4061         default:
4062                 IWL_DEBUG_HT("unknown\n");
4063                 return -EINVAL;
4064                 break;
4065         }
4066         return 0;
4067 }
4068 #endif /* CONFIG_IWL4965_HT */
4069
4070
4071 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
4072 {
4073         struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
4074         addsta->mode = cmd->mode;
4075         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
4076         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
4077         addsta->station_flags = cmd->station_flags;
4078         addsta->station_flags_msk = cmd->station_flags_msk;
4079         addsta->tid_disable_tx = cmd->tid_disable_tx;
4080         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
4081         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
4082         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
4083         addsta->reserved1 = __constant_cpu_to_le16(0);
4084         addsta->reserved2 = __constant_cpu_to_le32(0);
4085
4086         return (u16)sizeof(struct iwl4965_addsta_cmd);
4087 }
4088 /* Set up 4965-specific Rx frame reply handlers */
4089 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
4090 {
4091         /* Legacy Rx frames */
4092         priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
4093
4094         /* High-throughput (HT) Rx frames */
4095         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4096         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4097
4098         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4099             iwl4965_rx_missed_beacon_notif;
4100
4101 #ifdef CONFIG_IWL4965_HT
4102         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4103 #endif /* CONFIG_IWL4965_HT */
4104 }
4105
4106 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
4107 {
4108         INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4109 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4110         INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4111 #endif
4112         init_timer(&priv->statistics_periodic);
4113         priv->statistics_periodic.data = (unsigned long)priv;
4114         priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4115 }
4116
4117 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
4118 {
4119         del_timer_sync(&priv->statistics_periodic);
4120
4121         cancel_delayed_work(&priv->init_alive_start);
4122 }
4123
4124
4125 static struct iwl_hcmd_ops iwl4965_hcmd = {
4126         .rxon_assoc = iwl4965_send_rxon_assoc,
4127 };
4128
4129 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4130         .enqueue_hcmd = iwl4965_enqueue_hcmd,
4131         .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
4132 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4133         .chain_noise_reset = iwl4965_chain_noise_reset,
4134         .gain_computation = iwl4965_gain_computation,
4135 #endif
4136 };
4137
4138 static struct iwl_lib_ops iwl4965_lib = {
4139         .set_hw_params = iwl4965_hw_set_hw_params,
4140         .alloc_shared_mem = iwl4965_alloc_shared_mem,
4141         .free_shared_mem = iwl4965_free_shared_mem,
4142         .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4143         .hw_nic_init = iwl4965_hw_nic_init,
4144         .rx_handler_setup = iwl4965_rx_handler_setup,
4145         .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4146         .alive_notify = iwl4965_alive_notify,
4147         .load_ucode = iwl4965_load_bsm,
4148         .apm_ops = {
4149                 .init = iwl4965_apm_init,
4150                 .config = iwl4965_nic_config,
4151                 .set_pwr_src = iwl4965_set_pwr_src,
4152         },
4153         .eeprom_ops = {
4154                 .regulatory_bands = {
4155                         EEPROM_REGULATORY_BAND_1_CHANNELS,
4156                         EEPROM_REGULATORY_BAND_2_CHANNELS,
4157                         EEPROM_REGULATORY_BAND_3_CHANNELS,
4158                         EEPROM_REGULATORY_BAND_4_CHANNELS,
4159                         EEPROM_REGULATORY_BAND_5_CHANNELS,
4160                         EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4161                         EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4162                 },
4163                 .verify_signature  = iwlcore_eeprom_verify_signature,
4164                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4165                 .release_semaphore = iwlcore_eeprom_release_semaphore,
4166                 .check_version = iwl4965_eeprom_check_version,
4167                 .query_addr = iwlcore_eeprom_query_addr,
4168         },
4169         .radio_kill_sw = iwl4965_radio_kill_sw,
4170         .set_power = iwl4965_set_power,
4171         .update_chain_flags = iwl4965_update_chain_flags,
4172 };
4173
4174 static struct iwl_ops iwl4965_ops = {
4175         .lib = &iwl4965_lib,
4176         .hcmd = &iwl4965_hcmd,
4177         .utils = &iwl4965_hcmd_utils,
4178 };
4179
4180 struct iwl_cfg iwl4965_agn_cfg = {
4181         .name = "4965AGN",
4182         .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4183         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
4184         .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
4185         .ops = &iwl4965_ops,
4186         .mod_params = &iwl4965_mod_params,
4187 };
4188
4189 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4190 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4191 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4192 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4193 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4194 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
4195 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4196 MODULE_PARM_DESC(debug, "debug output mask");
4197 module_param_named(
4198         disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4199 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4200
4201 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4202 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4203
4204 /* QoS */
4205 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4206 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4207 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4208 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4209