3 Broadcom B43 wireless driver
7 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
32 #include <linux/delay.h>
35 static u16 generate_cookie(struct b43_pio_txqueue *q,
36 struct b43_pio_txpacket *pack)
40 /* Use the upper 4 bits of the cookie as
41 * PIO controller ID and store the packet index number
42 * in the lower 12 bits.
43 * Note that the cookie must never be 0, as this
44 * is a special value used in RX path.
45 * It can also not be 0xFFFF because that is special
46 * for multicast frames.
48 cookie = (((u16)q->index + 1) << 12);
49 cookie |= pack->index;
55 struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev,
57 struct b43_pio_txpacket **pack)
59 struct b43_pio *pio = &dev->pio;
60 struct b43_pio_txqueue *q = NULL;
61 unsigned int pack_index;
63 switch (cookie & 0xF000) {
65 q = pio->tx_queue_AC_BK;
68 q = pio->tx_queue_AC_BE;
71 q = pio->tx_queue_AC_VI;
74 q = pio->tx_queue_AC_VO;
77 q = pio->tx_queue_mcast;
82 pack_index = (cookie & 0x0FFF);
83 if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
85 *pack = &q->packets[pack_index];
90 static u16 index_to_pioqueue_base(struct b43_wldev *dev,
93 static const u16 bases[] = {
103 static const u16 bases_rev11[] = {
104 B43_MMIO_PIO11_BASE0,
105 B43_MMIO_PIO11_BASE1,
106 B43_MMIO_PIO11_BASE2,
107 B43_MMIO_PIO11_BASE3,
108 B43_MMIO_PIO11_BASE4,
109 B43_MMIO_PIO11_BASE5,
112 if (dev->dev->id.revision >= 11) {
113 B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
114 return bases_rev11[index];
116 B43_WARN_ON(index >= ARRAY_SIZE(bases));
120 static u16 pio_txqueue_offset(struct b43_wldev *dev)
122 if (dev->dev->id.revision >= 11)
127 static u16 pio_rxqueue_offset(struct b43_wldev *dev)
129 if (dev->dev->id.revision >= 11)
134 static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
137 struct b43_pio_txqueue *q;
138 struct b43_pio_txpacket *p;
141 q = kzalloc(sizeof(*q), GFP_KERNEL);
145 q->rev = dev->dev->id.revision;
146 q->mmio_base = index_to_pioqueue_base(dev, index) +
147 pio_txqueue_offset(dev);
150 q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
152 q->buffer_size = 1920; //FIXME this constant is wrong.
154 q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
155 q->buffer_size -= 80;
158 INIT_LIST_HEAD(&q->packets_list);
159 for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
160 p = &(q->packets[i]);
161 INIT_LIST_HEAD(&p->list);
164 list_add(&p->list, &q->packets_list);
170 static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
173 struct b43_pio_rxqueue *q;
175 q = kzalloc(sizeof(*q), GFP_KERNEL);
179 q->rev = dev->dev->id.revision;
180 q->mmio_base = index_to_pioqueue_base(dev, index) +
181 pio_rxqueue_offset(dev);
183 /* Enable Direct FIFO RX (PIO) on the engine. */
184 b43_dma_direct_fifo_rx(dev, index, 1);
189 static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
191 struct b43_pio_txpacket *pack;
194 for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
195 pack = &(q->packets[i]);
197 dev_kfree_skb_any(pack->skb);
203 static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
208 b43_pio_cancel_tx_packets(q);
212 static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
220 #define destroy_queue_tx(pio, queue) do { \
221 b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
222 (pio)->queue = NULL; \
225 #define destroy_queue_rx(pio, queue) do { \
226 b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
227 (pio)->queue = NULL; \
230 void b43_pio_free(struct b43_wldev *dev)
234 if (!b43_using_pio_transfers(dev))
238 destroy_queue_rx(pio, rx_queue);
239 destroy_queue_tx(pio, tx_queue_mcast);
240 destroy_queue_tx(pio, tx_queue_AC_VO);
241 destroy_queue_tx(pio, tx_queue_AC_VI);
242 destroy_queue_tx(pio, tx_queue_AC_BE);
243 destroy_queue_tx(pio, tx_queue_AC_BK);
246 int b43_pio_init(struct b43_wldev *dev)
248 struct b43_pio *pio = &dev->pio;
251 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
253 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
255 pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
256 if (!pio->tx_queue_AC_BK)
259 pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
260 if (!pio->tx_queue_AC_BE)
263 pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
264 if (!pio->tx_queue_AC_VI)
267 pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
268 if (!pio->tx_queue_AC_VO)
271 pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
272 if (!pio->tx_queue_mcast)
275 pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
277 goto err_destroy_mcast;
279 b43dbg(dev->wl, "PIO initialized\n");
285 destroy_queue_tx(pio, tx_queue_mcast);
287 destroy_queue_tx(pio, tx_queue_AC_VO);
289 destroy_queue_tx(pio, tx_queue_AC_VI);
291 destroy_queue_tx(pio, tx_queue_AC_BE);
293 destroy_queue_tx(pio, tx_queue_AC_BK);
297 /* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
298 static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev,
301 struct b43_pio_txqueue *q;
303 if (dev->qos_enabled) {
304 /* 0 = highest priority */
305 switch (queue_prio) {
310 q = dev->pio.tx_queue_AC_VO;
313 q = dev->pio.tx_queue_AC_VI;
316 q = dev->pio.tx_queue_AC_BE;
319 q = dev->pio.tx_queue_AC_BK;
323 q = dev->pio.tx_queue_AC_BE;
328 static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
331 unsigned int data_len)
333 struct b43_wldev *dev = q->dev;
334 struct b43_wl *wl = dev->wl;
335 const u8 *data = _data;
337 ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
338 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
340 ssb_block_write(dev->dev, data, (data_len & ~1),
341 q->mmio_base + B43_PIO_TXDATA,
344 /* Write the last byte. */
345 ctl &= ~B43_PIO_TXCTL_WRITEHI;
346 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
347 wl->tx_tail[0] = data[data_len - 1];
349 ssb_block_write(dev->dev, wl->tx_tail, 2,
350 q->mmio_base + B43_PIO_TXDATA,
357 static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
358 const u8 *hdr, unsigned int hdrlen)
360 struct b43_pio_txqueue *q = pack->queue;
361 const char *frame = pack->skb->data;
362 unsigned int frame_len = pack->skb->len;
365 ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
366 ctl |= B43_PIO_TXCTL_FREADY;
367 ctl &= ~B43_PIO_TXCTL_EOF;
369 /* Transfer the header data. */
370 ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
371 /* Transfer the frame data. */
372 ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
374 ctl |= B43_PIO_TXCTL_EOF;
375 b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
378 static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
381 unsigned int data_len)
383 struct b43_wldev *dev = q->dev;
384 struct b43_wl *wl = dev->wl;
385 const u8 *data = _data;
387 ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
388 B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
389 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
391 ssb_block_write(dev->dev, data, (data_len & ~3),
392 q->mmio_base + B43_PIO8_TXDATA,
396 /* Write the last few bytes. */
397 ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
398 B43_PIO8_TXCTL_24_31);
399 switch (data_len & 3) {
401 ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15;
402 wl->tx_tail[0] = data[data_len - 3];
403 wl->tx_tail[1] = data[data_len - 2];
404 wl->tx_tail[2] = data[data_len - 1];
407 ctl |= B43_PIO8_TXCTL_8_15;
408 wl->tx_tail[0] = data[data_len - 2];
409 wl->tx_tail[1] = data[data_len - 1];
413 wl->tx_tail[0] = data[data_len - 1];
418 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
419 ssb_block_write(dev->dev, wl->tx_tail, 4,
420 q->mmio_base + B43_PIO8_TXDATA,
427 static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
428 const u8 *hdr, unsigned int hdrlen)
430 struct b43_pio_txqueue *q = pack->queue;
431 const char *frame = pack->skb->data;
432 unsigned int frame_len = pack->skb->len;
435 ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
436 ctl |= B43_PIO8_TXCTL_FREADY;
437 ctl &= ~B43_PIO8_TXCTL_EOF;
439 /* Transfer the header data. */
440 ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
441 /* Transfer the frame data. */
442 ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
444 ctl |= B43_PIO8_TXCTL_EOF;
445 b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
448 static int pio_tx_frame(struct b43_pio_txqueue *q,
451 struct b43_wldev *dev = q->dev;
452 struct b43_wl *wl = dev->wl;
453 struct b43_pio_txpacket *pack;
457 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
459 B43_WARN_ON(list_empty(&q->packets_list));
460 pack = list_entry(q->packets_list.next,
461 struct b43_pio_txpacket, list);
463 cookie = generate_cookie(q, pack);
464 hdrlen = b43_txhdr_size(dev);
465 err = b43_generate_txhdr(dev, (u8 *)&wl->txhdr, skb,
470 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
471 /* Tell the firmware about the cookie of the last
472 * mcast frame, so it can clear the more-data bit in it. */
473 b43_shm_write16(dev, B43_SHM_SHARED,
474 B43_SHM_SH_MCASTCOOKIE, cookie);
479 pio_tx_frame_4byte_queue(pack, (const u8 *)&wl->txhdr, hdrlen);
481 pio_tx_frame_2byte_queue(pack, (const u8 *)&wl->txhdr, hdrlen);
483 /* Remove it from the list of available packet slots.
484 * It will be put back when we receive the status report. */
485 list_del(&pack->list);
487 /* Update the queue statistics. */
488 q->buffer_used += roundup(skb->len + hdrlen, 4);
489 q->free_packet_slots -= 1;
494 int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
496 struct b43_pio_txqueue *q;
497 struct ieee80211_hdr *hdr;
498 unsigned int hdrlen, total_len;
500 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
502 hdr = (struct ieee80211_hdr *)skb->data;
504 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
505 /* The multicast queue will be sent after the DTIM. */
506 q = dev->pio.tx_queue_mcast;
507 /* Set the frame More-Data bit. Ucode will clear it
508 * for us on the last frame. */
509 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
511 /* Decide by priority where to put this frame. */
512 q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
515 hdrlen = b43_txhdr_size(dev);
516 total_len = roundup(skb->len + hdrlen, 4);
518 if (unlikely(total_len > q->buffer_size)) {
520 b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
523 if (unlikely(q->free_packet_slots == 0)) {
525 b43warn(dev->wl, "PIO: TX packet overflow.\n");
528 B43_WARN_ON(q->buffer_used > q->buffer_size);
530 if (total_len > (q->buffer_size - q->buffer_used)) {
531 /* Not enough memory on the queue. */
533 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
538 /* Assign the queue number to the ring (if not already done before)
539 * so TX status handling can use it. The mac80211-queue to b43-queue
540 * mapping is static, so we don't need to store it per frame. */
541 q->queue_prio = skb_get_queue_mapping(skb);
543 err = pio_tx_frame(q, skb);
544 if (unlikely(err == -ENOKEY)) {
545 /* Drop this packet, as we don't have the encryption key
546 * anymore and must not transmit it unencrypted. */
547 dev_kfree_skb_any(skb);
552 b43err(dev->wl, "PIO transmission failure\n");
557 B43_WARN_ON(q->buffer_used > q->buffer_size);
558 if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
559 (q->free_packet_slots == 0)) {
560 /* The queue is full. */
561 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
569 void b43_pio_handle_txstatus(struct b43_wldev *dev,
570 const struct b43_txstatus *status)
572 struct b43_pio_txqueue *q;
573 struct b43_pio_txpacket *pack = NULL;
574 unsigned int total_len;
575 struct ieee80211_tx_info *info;
577 q = parse_cookie(dev, status->cookie, &pack);
582 info = IEEE80211_SKB_CB(pack->skb);
584 b43_fill_txstatus_report(dev, info, status);
586 total_len = pack->skb->len + b43_txhdr_size(dev);
587 total_len = roundup(total_len, 4);
588 q->buffer_used -= total_len;
589 q->free_packet_slots += 1;
591 ieee80211_tx_status(dev->wl->hw, pack->skb);
593 list_add(&pack->list, &q->packets_list);
596 ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
601 void b43_pio_get_tx_stats(struct b43_wldev *dev,
602 struct ieee80211_tx_queue_stats *stats)
604 const int nr_queues = dev->wl->hw->queues;
605 struct b43_pio_txqueue *q;
608 for (i = 0; i < nr_queues; i++) {
609 q = select_queue_by_priority(dev, i);
611 stats[i].len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots;
612 stats[i].limit = B43_PIO_MAX_NR_TXPACKETS;
613 stats[i].count = q->nr_tx_packets;
617 /* Returns whether we should fetch another frame. */
618 static bool pio_rx_frame(struct b43_pio_rxqueue *q)
620 struct b43_wldev *dev = q->dev;
621 struct b43_wl *wl = dev->wl;
624 unsigned int i, padding;
626 const char *err_msg = NULL;
628 memset(&wl->rxhdr, 0, sizeof(wl->rxhdr));
630 /* Check if we have data and wait for it to get ready. */
634 ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
635 if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
637 b43_piorx_write32(q, B43_PIO8_RXCTL,
638 B43_PIO8_RXCTL_FRAMERDY);
639 for (i = 0; i < 10; i++) {
640 ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
641 if (ctl & B43_PIO8_RXCTL_DATARDY)
648 ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
649 if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
651 b43_piorx_write16(q, B43_PIO_RXCTL,
652 B43_PIO_RXCTL_FRAMERDY);
653 for (i = 0; i < 10; i++) {
654 ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
655 if (ctl & B43_PIO_RXCTL_DATARDY)
660 b43dbg(q->dev->wl, "PIO RX timed out\n");
664 /* Get the preamble (RX header) */
666 ssb_block_read(dev->dev, &wl->rxhdr, sizeof(wl->rxhdr),
667 q->mmio_base + B43_PIO8_RXDATA,
670 ssb_block_read(dev->dev, &wl->rxhdr, sizeof(wl->rxhdr),
671 q->mmio_base + B43_PIO_RXDATA,
675 len = le16_to_cpu(wl->rxhdr.frame_len);
676 if (unlikely(len > 0x700)) {
677 err_msg = "len > 0x700";
680 if (unlikely(len == 0)) {
681 err_msg = "len == 0";
685 macstat = le32_to_cpu(wl->rxhdr.mac_status);
686 if (macstat & B43_RX_MAC_FCSERR) {
687 if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
688 /* Drop frames with failed FCS. */
689 err_msg = "Frame FCS error";
694 /* We always pad 2 bytes, as that's what upstream code expects
695 * due to the RX-header being 30 bytes. In case the frame is
696 * unaligned, we pad another 2 bytes. */
697 padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
698 skb = dev_alloc_skb(len + padding + 2);
699 if (unlikely(!skb)) {
700 err_msg = "Out of memory";
704 skb_put(skb, len + padding);
706 ssb_block_read(dev->dev, skb->data + padding, (len & ~3),
707 q->mmio_base + B43_PIO8_RXDATA,
710 /* Read the last few bytes. */
711 ssb_block_read(dev->dev, wl->rx_tail, 4,
712 q->mmio_base + B43_PIO8_RXDATA,
716 skb->data[len + padding - 3] = wl->rx_tail[0];
717 skb->data[len + padding - 2] = wl->rx_tail[1];
718 skb->data[len + padding - 1] = wl->rx_tail[2];
721 skb->data[len + padding - 2] = wl->rx_tail[0];
722 skb->data[len + padding - 1] = wl->rx_tail[1];
725 skb->data[len + padding - 1] = wl->rx_tail[0];
730 ssb_block_read(dev->dev, skb->data + padding, (len & ~1),
731 q->mmio_base + B43_PIO_RXDATA,
734 /* Read the last byte. */
735 ssb_block_read(dev->dev, wl->rx_tail, 2,
736 q->mmio_base + B43_PIO_RXDATA,
738 skb->data[len + padding - 1] = wl->rx_tail[0];
742 b43_rx(q->dev, skb, &wl->rxhdr);
748 b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
749 b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
753 void b43_pio_rx(struct b43_pio_rxqueue *q)
755 unsigned int count = 0;
759 stop = (pio_rx_frame(q) == 0);
763 if (WARN_ON_ONCE(++count > 10000))
768 static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
771 b43_piotx_write32(q, B43_PIO8_TXCTL,
772 b43_piotx_read32(q, B43_PIO8_TXCTL)
773 | B43_PIO8_TXCTL_SUSPREQ);
775 b43_piotx_write16(q, B43_PIO_TXCTL,
776 b43_piotx_read16(q, B43_PIO_TXCTL)
777 | B43_PIO_TXCTL_SUSPREQ);
781 static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
784 b43_piotx_write32(q, B43_PIO8_TXCTL,
785 b43_piotx_read32(q, B43_PIO8_TXCTL)
786 & ~B43_PIO8_TXCTL_SUSPREQ);
788 b43_piotx_write16(q, B43_PIO_TXCTL,
789 b43_piotx_read16(q, B43_PIO_TXCTL)
790 & ~B43_PIO_TXCTL_SUSPREQ);
794 void b43_pio_tx_suspend(struct b43_wldev *dev)
796 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
797 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
798 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
799 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
800 b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
801 b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
804 void b43_pio_tx_resume(struct b43_wldev *dev)
806 b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
807 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
808 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
809 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
810 b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
811 b43_power_saving_ctl_bits(dev, 0);