drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "radio_2055.h"
  33 #include "radio_2056.h"
  34 #include "main.h"
  35
  36 struct nphy_txgains {
  37         u16 txgm[2];
  38         u16 pga[2];
  39         u16 pad[2];
  40         u16 ipa[2];
  41 };
  42
  43 struct nphy_iqcal_params {
  44         u16 txgm;
  45         u16 pga;
  46         u16 pad;
  47         u16 ipa;
  48         u16 cal_gain;
  49         u16 ncorr[5];
  50 };
  51
  52 struct nphy_iq_est {
  53         s32 iq0_prod;
  54         u32 i0_pwr;
  55         u32 q0_pwr;
  56         s32 iq1_prod;
  57         u32 i1_pwr;
  58         u32 q1_pwr;
  59 };
  60
  61 enum b43_nphy_rf_sequence {
  62         B43_RFSEQ_RX2TX,
  63         B43_RFSEQ_TX2RX,
  64         B43_RFSEQ_RESET2RX,
  65         B43_RFSEQ_UPDATE_GAINH,
  66         B43_RFSEQ_UPDATE_GAINL,
  67         B43_RFSEQ_UPDATE_GAINU,
  68 };
  69
  70 enum b43_nphy_rssi_type {
  71         B43_NPHY_RSSI_X = 0,
  72         B43_NPHY_RSSI_Y,
  73         B43_NPHY_RSSI_Z,
  74         B43_NPHY_RSSI_PWRDET,
  75         B43_NPHY_RSSI_TSSI_I,
  76         B43_NPHY_RSSI_TSSI_Q,
  77         B43_NPHY_RSSI_TBD,
  78 };
  79
  80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  81                                                 bool enable);
  82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  83                                         u8 *events, u8 *delays, u8 length);
  84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  85                                        enum b43_nphy_rf_sequence seq);
  86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  87                                                 u16 value, u8 core, bool off);
  88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  89                                                 u16 value, u8 core);
  90
  91 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  92 {//TODO
  93 }
  94
  95 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  96 {//TODO
  97 }
  98
  99 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 100                                                         bool ignore_tssi)
 101 {//TODO
 102         return B43_TXPWR_RES_DONE;
 103 }
 104
 105 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 106                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 107 {
 108         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 109         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 110         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 111         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 112         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 113
 114         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 115         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 116         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 117         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 118         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 119
 120         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 121         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 122         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 123         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 124         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 125
 126         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 127         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 128         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 129         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 130         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 131
 132         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 133         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 134         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 135         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 136         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 137
 138         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 139         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 140 }
 141
 142 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 143                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 144 {
 145         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 146         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 147         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 148         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 149         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 150         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 151                                         e->radio_syn_pll_loopfilter1);
 152         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 153                                         e->radio_syn_pll_loopfilter2);
 154         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 155                                         e->radio_syn_pll_loopfilter3);
 156         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 157                                         e->radio_syn_pll_loopfilter4);
 158         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 159                                         e->radio_syn_pll_loopfilter5);
 160         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 161                                         e->radio_syn_reserved_addr27);
 162         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 163                                         e->radio_syn_reserved_addr28);
 164         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 165                                         e->radio_syn_reserved_addr29);
 166         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 167                                         e->radio_syn_logen_vcobuf1);
 168         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 169         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 170         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 171
 172         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 173                                         e->radio_rx0_lnaa_tune);
 174         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 175                                         e->radio_rx0_lnag_tune);
 176
 177         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 178                                         e->radio_tx0_intpaa_boost_tune);
 179         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 180                                         e->radio_tx0_intpag_boost_tune);
 181         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 182                                         e->radio_tx0_pada_boost_tune);
 183         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 184                                         e->radio_tx0_padg_boost_tune);
 185         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 186                                         e->radio_tx0_pgaa_boost_tune);
 187         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 188                                         e->radio_tx0_pgag_boost_tune);
 189         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 190                                         e->radio_tx0_mixa_boost_tune);
 191         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 192                                         e->radio_tx0_mixg_boost_tune);
 193
 194         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 195                                         e->radio_rx1_lnaa_tune);
 196         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 197                                         e->radio_rx1_lnag_tune);
 198
 199         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 200                                         e->radio_tx1_intpaa_boost_tune);
 201         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 202                                         e->radio_tx1_intpag_boost_tune);
 203         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 204                                         e->radio_tx1_pada_boost_tune);
 205         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 206                                         e->radio_tx1_padg_boost_tune);
 207         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 208                                         e->radio_tx1_pgaa_boost_tune);
 209         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 210                                         e->radio_tx1_pgag_boost_tune);
 211         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 212                                         e->radio_tx1_mixa_boost_tune);
 213         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 214                                         e->radio_tx1_mixg_boost_tune);
 215 }
 216
 217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 218 static void b43_radio_2056_setup(struct b43_wldev *dev,
 219                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 220 {
 221         B43_WARN_ON(dev->phy.rev < 3);
 222
 223         b43_chantab_radio_2056_upload(dev, e);
 224         /* TODO */
 225         udelay(50);
 226         /* VCO calibration */
 227         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 228         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 229         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 230         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 231         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 232         udelay(300);
 233 }
 234
 235 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 236                                    const struct b43_phy_n_sfo_cfg *e)
 237 {
 238         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 239         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 240         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 241         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 242         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 243         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 244 }
 245
 246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 247 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 248 {
 249         struct b43_phy_n *nphy = dev->phy.n;
 250         u8 i;
 251         u16 tmp;
 252
 253         if (nphy->hang_avoid)
 254                 b43_nphy_stay_in_carrier_search(dev, 1);
 255
 256         nphy->txpwrctrl = enable;
 257         if (!enable) {
 258                 if (dev->phy.rev >= 3)
 259                         ; /* TODO */
 260
 261                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 262                 for (i = 0; i < 84; i++)
 263                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 264
 265                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 266                 for (i = 0; i < 84; i++)
 267                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 268
 269                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 270                 if (dev->phy.rev >= 3)
 271                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 272                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 273
 274                 if (dev->phy.rev >= 3) {
 275                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 276                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 277                 } else {
 278                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 279                 }
 280
 281                 if (dev->phy.rev == 2)
 282                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 283                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 284                 else if (dev->phy.rev < 2)
 285                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 286                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 287
 288                 if (dev->phy.rev < 2 && 0)
 289                         ; /* TODO */
 290         } else {
 291                 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
 292         }
 293
 294         if (nphy->hang_avoid)
 295                 b43_nphy_stay_in_carrier_search(dev, 0);
 296 }
 297
 298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 299 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 300 {
 301         struct b43_phy_n *nphy = dev->phy.n;
 302         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 303
 304         u8 txpi[2], bbmult, i;
 305         u16 tmp, radio_gain, dac_gain;
 306         u16 freq = dev->phy.channel_freq;
 307         u32 txgain;
 308         /* u32 gaintbl; rev3+ */
 309
 310         if (nphy->hang_avoid)
 311                 b43_nphy_stay_in_carrier_search(dev, 1);
 312
 313         if (dev->phy.rev >= 3) {
 314                 txpi[0] = 40;
 315                 txpi[1] = 40;
 316         } else if (sprom->revision < 4) {
 317                 txpi[0] = 72;
 318                 txpi[1] = 72;
 319         } else {
 320                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 321                         txpi[0] = sprom->txpid2g[0];
 322                         txpi[1] = sprom->txpid2g[1];
 323                 } else if (freq >= 4900 && freq < 5100) {
 324                         txpi[0] = sprom->txpid5gl[0];
 325                         txpi[1] = sprom->txpid5gl[1];
 326                 } else if (freq >= 5100 && freq < 5500) {
 327                         txpi[0] = sprom->txpid5g[0];
 328                         txpi[1] = sprom->txpid5g[1];
 329                 } else if (freq >= 5500) {
 330                         txpi[0] = sprom->txpid5gh[0];
 331                         txpi[1] = sprom->txpid5gh[1];
 332                 } else {
 333                         txpi[0] = 91;
 334                         txpi[1] = 91;
 335                 }
 336         }
 337
 338         /*
 339         for (i = 0; i < 2; i++) {
 340                 nphy->txpwrindex[i].index_internal = txpi[i];
 341                 nphy->txpwrindex[i].index_internal_save = txpi[i];
 342         }
 343         */
 344
 345         for (i = 0; i < 2; i++) {
 346                 if (dev->phy.rev >= 3) {
 347                         /* FIXME: support 5GHz */
 348                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 349                         radio_gain = (txgain >> 16) & 0x1FFFF;
 350                 } else {
 351                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 352                         radio_gain = (txgain >> 16) & 0x1FFF;
 353                 }
 354
 355                 dac_gain = (txgain >> 8) & 0x3F;
 356                 bbmult = txgain & 0xFF;
 357
 358                 if (dev->phy.rev >= 3) {
 359                         if (i == 0)
 360                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 361                         else
 362                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 363                 } else {
 364                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 365                 }
 366
 367                 if (i == 0)
 368                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 369                 else
 370                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 371
 372                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
 373                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
 374
 375                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 376                 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 377
 378                 if (i == 0)
 379                         tmp = (tmp & 0x00FF) | (bbmult << 8);
 380                 else
 381                         tmp = (tmp & 0xFF00) | bbmult;
 382
 383                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 384                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
 385
 386                 if (0)
 387                         ; /* TODO */
 388         }
 389
 390         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 391
 392         if (nphy->hang_avoid)
 393                 b43_nphy_stay_in_carrier_search(dev, 0);
 394 }
 395
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 398 static void b43_radio_2055_setup(struct b43_wldev *dev,
 399                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 400 {
 401         B43_WARN_ON(dev->phy.rev >= 3);
 402
 403         b43_chantab_radio_upload(dev, e);
 404         udelay(50);
 405         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 406         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 407         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 408         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 409         udelay(300);
 410 }
 411
 412 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 413 {
 414         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 415                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 416         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 417                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 418                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 419         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 420                     B43_NPHY_RFCTL_CMD_PORFORCE);
 421 }
 422
 423 static void b43_radio_init2055_post(struct b43_wldev *dev)
 424 {
 425         struct b43_phy_n *nphy = dev->phy.n;
 426         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 427         int i;
 428         u16 val;
 429         bool workaround = false;
 430
 431         if (sprom->revision < 4)
 432                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 433                               && dev->dev->board_type == 0x46D
 434                               && dev->dev->board_rev >= 0x41);
 435         else
 436                 workaround =
 437                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 438
 439         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 440         if (workaround) {
 441                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 442                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 443         }
 444         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 445         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 446         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 447         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 448         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 449         msleep(1);
 450         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 451         for (i = 0; i < 200; i++) {
 452                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 453                 if (val & 0x80) {
 454                         i = 0;
 455                         break;
 456                 }
 457                 udelay(10);
 458         }
 459         if (i)
 460                 b43err(dev->wl, "radio post init timeout\n");
 461         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 462         b43_switch_channel(dev, dev->phy.channel);
 463         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 464         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 465         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 466         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 467         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 468         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 469         if (!nphy->gain_boost) {
 470                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 471                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 472         } else {
 473                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 474                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 475         }
 476         udelay(2);
 477 }
 478
 479 /*
 480  * Initialize a Broadcom 2055 N-radio
 481  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 482  */
 483 static void b43_radio_init2055(struct b43_wldev *dev)
 484 {
 485         b43_radio_init2055_pre(dev);
 486         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 487                 /* Follow wl, not specs. Do not force uploading all regs */
 488                 b2055_upload_inittab(dev, 0, 0);
 489         } else {
 490                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 491                 b2055_upload_inittab(dev, ghz5, 0);
 492         }
 493         b43_radio_init2055_post(dev);
 494 }
 495
 496 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 497 {
 498         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 499                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 500         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 501         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 502                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 503         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 504                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 505         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 506                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 507 }
 508
 509 static void b43_radio_init2056_post(struct b43_wldev *dev)
 510 {
 511         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 512         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 513         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 514         msleep(1);
 515         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 516         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 517         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 518         /*
 519         if (nphy->init_por)
 520                 Call Radio 2056 Recalibrate
 521         */
 522 }
 523
 524 /*
 525  * Initialize a Broadcom 2056 N-radio
 526  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 527  */
 528 static void b43_radio_init2056(struct b43_wldev *dev)
 529 {
 530         b43_radio_init2056_pre(dev);
 531         b2056_upload_inittabs(dev, 0, 0);
 532         b43_radio_init2056_post(dev);
 533 }
 534
 535 /*
 536  * Upload the N-PHY tables.
 537  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 538  */
 539 static void b43_nphy_tables_init(struct b43_wldev *dev)
 540 {
 541         if (dev->phy.rev < 3)
 542                 b43_nphy_rev0_1_2_tables_init(dev);
 543         else
 544                 b43_nphy_rev3plus_tables_init(dev);
 545 }
 546
 547 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 548 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 549 {
 550         struct b43_phy_n *nphy = dev->phy.n;
 551         enum ieee80211_band band;
 552         u16 tmp;
 553
 554         if (!enable) {
 555                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 556                                                        B43_NPHY_RFCTL_INTC1);
 557                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 558                                                        B43_NPHY_RFCTL_INTC2);
 559                 band = b43_current_band(dev->wl);
 560                 if (dev->phy.rev >= 3) {
 561                         if (band == IEEE80211_BAND_5GHZ)
 562                                 tmp = 0x600;
 563                         else
 564                                 tmp = 0x480;
 565                 } else {
 566                         if (band == IEEE80211_BAND_5GHZ)
 567                                 tmp = 0x180;
 568                         else
 569                                 tmp = 0x120;
 570                 }
 571                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 572                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 573         } else {
 574                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 575                                 nphy->rfctrl_intc1_save);
 576                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 577                                 nphy->rfctrl_intc2_save);
 578         }
 579 }
 580
 581 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 582 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 583 {
 584         struct b43_phy_n *nphy = dev->phy.n;
 585         u16 tmp;
 586         enum ieee80211_band band = b43_current_band(dev->wl);
 587         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 588                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 589
 590         if (dev->phy.rev >= 3) {
 591                 if (ipa) {
 592                         tmp = 4;
 593                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 594                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 595                 }
 596
 597                 tmp = 1;
 598                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 599                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 600         }
 601 }
 602
 603 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 604 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 605 {
 606         u32 tmslow;
 607
 608         if (dev->phy.type != B43_PHYTYPE_N)
 609                 return;
 610
 611         tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
 612         if (force)
 613                 tmslow |= SSB_TMSLOW_FGC;
 614         else
 615                 tmslow &= ~SSB_TMSLOW_FGC;
 616         ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
 617 }
 618
 619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 620 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 621 {
 622         u16 bbcfg;
 623
 624         b43_nphy_bmac_clock_fgc(dev, 1);
 625         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 626         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 627         udelay(1);
 628         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 629         b43_nphy_bmac_clock_fgc(dev, 0);
 630         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 631 }
 632
 633 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 634 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 635 {
 636         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 637
 638         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 639         if (preamble == 1)
 640                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 641         else
 642                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 643
 644         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 645 }
 646
 647 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 648 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 649 {
 650         struct b43_phy_n *nphy = dev->phy.n;
 651
 652         bool override = false;
 653         u16 chain = 0x33;
 654
 655         if (nphy->txrx_chain == 0) {
 656                 chain = 0x11;
 657                 override = true;
 658         } else if (nphy->txrx_chain == 1) {
 659                 chain = 0x22;
 660                 override = true;
 661         }
 662
 663         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 664                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 665                         chain);
 666
 667         if (override)
 668                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 669                                 B43_NPHY_RFSEQMODE_CAOVER);
 670         else
 671                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 672                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 673 }
 674
 675 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 676 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 677                                 u16 samps, u8 time, bool wait)
 678 {
 679         int i;
 680         u16 tmp;
 681
 682         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 683         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 684         if (wait)
 685                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 686         else
 687                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 688
 689         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 690
 691         for (i = 1000; i; i--) {
 692                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 693                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 694                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 695                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 696                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 697                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 698                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 699                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 700
 701                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 702                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 703                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 704                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 705                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 706                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 707                         return;
 708                 }
 709                 udelay(10);
 710         }
 711         memset(est, 0, sizeof(*est));
 712 }
 713
 714 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 715 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 716                                         struct b43_phy_n_iq_comp *pcomp)
 717 {
 718         if (write) {
 719                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 720                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 721                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 722                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 723         } else {
 724                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 725                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 726                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 727                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 728         }
 729 }
 730
 731 #if 0
 732 /* Ready but not used anywhere */
 733 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 734 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 735 {
 736         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 737
 738         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 739         if (core == 0) {
 740                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 741                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 742         } else {
 743                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 744                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 745         }
 746         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 747         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 748         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 749         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 750         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 751         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 752         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 753         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 754 }
 755
 756 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 757 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 758 {
 759         u8 rxval, txval;
 760         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 761
 762         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 763         if (core == 0) {
 764                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 765                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 766         } else {
 767                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 768                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 769         }
 770         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 771         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 772         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 773         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 774         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 775         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 776         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 777         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 778
 779         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 780         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 781
 782         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 783                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 784                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 785         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 786                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 787         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 788                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 789         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 790                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 791
 792         if (core == 0) {
 793                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 794                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 795         } else {
 796                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 797                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 798         }
 799
 800         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 801         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 802         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 803
 804         if (core == 0) {
 805                 rxval = 1;
 806                 txval = 8;
 807         } else {
 808                 rxval = 4;
 809                 txval = 2;
 810         }
 811         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 812         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 813 }
 814 #endif
 815
 816 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 817 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 818 {
 819         int i;
 820         s32 iq;
 821         u32 ii;
 822         u32 qq;
 823         int iq_nbits, qq_nbits;
 824         int arsh, brsh;
 825         u16 tmp, a, b;
 826
 827         struct nphy_iq_est est;
 828         struct b43_phy_n_iq_comp old;
 829         struct b43_phy_n_iq_comp new = { };
 830         bool error = false;
 831
 832         if (mask == 0)
 833                 return;
 834
 835         b43_nphy_rx_iq_coeffs(dev, false, &old);
 836         b43_nphy_rx_iq_coeffs(dev, true, &new);
 837         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 838         new = old;
 839
 840         for (i = 0; i < 2; i++) {
 841                 if (i == 0 && (mask & 1)) {
 842                         iq = est.iq0_prod;
 843                         ii = est.i0_pwr;
 844                         qq = est.q0_pwr;
 845                 } else if (i == 1 && (mask & 2)) {
 846                         iq = est.iq1_prod;
 847                         ii = est.i1_pwr;
 848                         qq = est.q1_pwr;
 849                 } else {
 850                         continue;
 851                 }
 852
 853                 if (ii + qq < 2) {
 854                         error = true;
 855                         break;
 856                 }
 857
 858                 iq_nbits = fls(abs(iq));
 859                 qq_nbits = fls(qq);
 860
 861                 arsh = iq_nbits - 20;
 862                 if (arsh >= 0) {
 863                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 864                         tmp = ii >> arsh;
 865                 } else {
 866                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 867                         tmp = ii << -arsh;
 868                 }
 869                 if (tmp == 0) {
 870                         error = true;
 871                         break;
 872                 }
 873                 a /= tmp;
 874
 875                 brsh = qq_nbits - 11;
 876                 if (brsh >= 0) {
 877                         b = (qq << (31 - qq_nbits));
 878                         tmp = ii >> brsh;
 879                 } else {
 880                         b = (qq << (31 - qq_nbits));
 881                         tmp = ii << -brsh;
 882                 }
 883                 if (tmp == 0) {
 884                         error = true;
 885                         break;
 886                 }
 887                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 888
 889                 if (i == 0 && (mask & 0x1)) {
 890                         if (dev->phy.rev >= 3) {
 891                                 new.a0 = a & 0x3FF;
 892                                 new.b0 = b & 0x3FF;
 893                         } else {
 894                                 new.a0 = b & 0x3FF;
 895                                 new.b0 = a & 0x3FF;
 896                         }
 897                 } else if (i == 1 && (mask & 0x2)) {
 898                         if (dev->phy.rev >= 3) {
 899                                 new.a1 = a & 0x3FF;
 900                                 new.b1 = b & 0x3FF;
 901                         } else {
 902                                 new.a1 = b & 0x3FF;
 903                                 new.b1 = a & 0x3FF;
 904                         }
 905                 }
 906         }
 907
 908         if (error)
 909                 new = old;
 910
 911         b43_nphy_rx_iq_coeffs(dev, true, &new);
 912 }
 913
 914 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 915 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 916 {
 917         u16 array[4];
 918         int i;
 919
 920         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 921         for (i = 0; i < 4; i++)
 922                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 923
 924         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 925         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 926         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 927         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 928 }
 929
 930 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 931 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 932                                           const u16 *clip_st)
 933 {
 934         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 935         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 936 }
 937
 938 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 939 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 940 {
 941         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 942         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 943 }
 944
 945 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 946 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 947 {
 948         if (dev->phy.rev >= 3) {
 949                 if (!init)
 950                         return;
 951                 if (0 /* FIXME */) {
 952                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 953                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 954                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 955                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 956                 }
 957         } else {
 958                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 959                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 960
 961                 ssb_chipco_gpio_control(&dev->sdev->bus->chipco, 0xFC00,
 962                                         0xFC00);
 963                 b43_write32(dev, B43_MMIO_MACCTL,
 964                         b43_read32(dev, B43_MMIO_MACCTL) &
 965                         ~B43_MACCTL_GPOUTSMSK);
 966                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 967                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 968                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 969                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 970
 971                 if (init) {
 972                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 973                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 974                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 975                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 976                 }
 977         }
 978 }
 979
 980 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 981 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 982 {
 983         u16 tmp;
 984
 985         if (dev->dev->core_rev == 16)
 986                 b43_mac_suspend(dev);
 987
 988         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 989         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 990                 B43_NPHY_CLASSCTL_WAITEDEN);
 991         tmp &= ~mask;
 992         tmp |= (val & mask);
 993         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 994
 995         if (dev->dev->core_rev == 16)
 996                 b43_mac_enable(dev);
 997
 998         return tmp;
 999 }
1000
1001 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1002 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1003 {
1004         struct b43_phy *phy = &dev->phy;
1005         struct b43_phy_n *nphy = phy->n;
1006
1007         if (enable) {
1008                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1009                 if (nphy->deaf_count++ == 0) {
1010                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1011                         b43_nphy_classifier(dev, 0x7, 0);
1012                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1013                         b43_nphy_write_clip_detection(dev, clip);
1014                 }
1015                 b43_nphy_reset_cca(dev);
1016         } else {
1017                 if (--nphy->deaf_count == 0) {
1018                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1019                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1020                 }
1021         }
1022 }
1023
1024 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1025 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1026 {
1027         struct b43_phy_n *nphy = dev->phy.n;
1028         u16 tmp;
1029
1030         if (nphy->hang_avoid)
1031                 b43_nphy_stay_in_carrier_search(dev, 1);
1032
1033         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1034         if (tmp & 0x1)
1035                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1036         else if (tmp & 0x2)
1037                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1038
1039         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1040
1041         if (nphy->bb_mult_save & 0x80000000) {
1042                 tmp = nphy->bb_mult_save & 0xFFFF;
1043                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1044                 nphy->bb_mult_save = 0;
1045         }
1046
1047         if (nphy->hang_avoid)
1048                 b43_nphy_stay_in_carrier_search(dev, 0);
1049 }
1050
1051 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1052 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1053 {
1054         struct b43_phy_n *nphy = dev->phy.n;
1055
1056         u8 channel = dev->phy.channel;
1057         int tone[2] = { 57, 58 };
1058         u32 noise[2] = { 0x3FF, 0x3FF };
1059
1060         B43_WARN_ON(dev->phy.rev < 3);
1061
1062         if (nphy->hang_avoid)
1063                 b43_nphy_stay_in_carrier_search(dev, 1);
1064
1065         if (nphy->gband_spurwar_en) {
1066                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1067                 if (channel == 11 && dev->phy.is_40mhz)
1068                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1069                 else
1070                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1071                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1072         }
1073
1074         if (nphy->aband_spurwar_en) {
1075                 if (channel == 54) {
1076                         tone[0] = 0x20;
1077                         noise[0] = 0x25F;
1078                 } else if (channel == 38 || channel == 102 || channel == 118) {
1079                         if (0 /* FIXME */) {
1080                                 tone[0] = 0x20;
1081                                 noise[0] = 0x21F;
1082                         } else {
1083                                 tone[0] = 0;
1084                                 noise[0] = 0;
1085                         }
1086                 } else if (channel == 134) {
1087                         tone[0] = 0x20;
1088                         noise[0] = 0x21F;
1089                 } else if (channel == 151) {
1090                         tone[0] = 0x10;
1091                         noise[0] = 0x23F;
1092                 } else if (channel == 153 || channel == 161) {
1093                         tone[0] = 0x30;
1094                         noise[0] = 0x23F;
1095                 } else {
1096                         tone[0] = 0;
1097                         noise[0] = 0;
1098                 }
1099
1100                 if (!tone[0] && !noise[0])
1101                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1102                 else
1103                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1104         }
1105
1106         if (nphy->hang_avoid)
1107                 b43_nphy_stay_in_carrier_search(dev, 0);
1108 }
1109
1110 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1111 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1112 {
1113         struct b43_phy_n *nphy = dev->phy.n;
1114
1115         u8 i;
1116         s16 tmp;
1117         u16 data[4];
1118         s16 gain[2];
1119         u16 minmax[2];
1120         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1121
1122         if (nphy->hang_avoid)
1123                 b43_nphy_stay_in_carrier_search(dev, 1);
1124
1125         if (nphy->gain_boost) {
1126                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1127                         gain[0] = 6;
1128                         gain[1] = 6;
1129                 } else {
1130                         tmp = 40370 - 315 * dev->phy.channel;
1131                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1132                         tmp = 23242 - 224 * dev->phy.channel;
1133                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1134                 }
1135         } else {
1136                 gain[0] = 0;
1137                 gain[1] = 0;
1138         }
1139
1140         for (i = 0; i < 2; i++) {
1141                 if (nphy->elna_gain_config) {
1142                         data[0] = 19 + gain[i];
1143                         data[1] = 25 + gain[i];
1144                         data[2] = 25 + gain[i];
1145                         data[3] = 25 + gain[i];
1146                 } else {
1147                         data[0] = lna_gain[0] + gain[i];
1148                         data[1] = lna_gain[1] + gain[i];
1149                         data[2] = lna_gain[2] + gain[i];
1150                         data[3] = lna_gain[3] + gain[i];
1151                 }
1152                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1153
1154                 minmax[i] = 23 + gain[i];
1155         }
1156
1157         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1158                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1159         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1160                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1161
1162         if (nphy->hang_avoid)
1163                 b43_nphy_stay_in_carrier_search(dev, 0);
1164 }
1165
1166 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1167 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1168 {
1169         struct b43_phy_n *nphy = dev->phy.n;
1170         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1171
1172         /* PHY rev 0, 1, 2 */
1173         u8 i, j;
1174         u8 code;
1175         u16 tmp;
1176         u8 rfseq_events[3] = { 6, 8, 7 };
1177         u8 rfseq_delays[3] = { 10, 30, 1 };
1178
1179         /* PHY rev >= 3 */
1180         bool ghz5;
1181         bool ext_lna;
1182         u16 rssi_gain;
1183         struct nphy_gain_ctl_workaround_entry *e;
1184         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1185         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1186
1187         if (dev->phy.rev >= 3) {
1188                 /* Prepare values */
1189                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1190                         & B43_NPHY_BANDCTL_5GHZ;
1191                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1192                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1193                 if (ghz5 && dev->phy.rev >= 5)
1194                         rssi_gain = 0x90;
1195                 else
1196                         rssi_gain = 0x50;
1197
1198                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1199
1200                 /* Set Clip 2 detect */
1201                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1202                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1203                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1204                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1205
1206                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1207                                 0x17);
1208                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1209                                 0x17);
1210                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1211                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1212                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1213                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1214                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1215                                 rssi_gain);
1216                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1217                                 rssi_gain);
1218                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1219                                 0x17);
1220                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1221                                 0x17);
1222                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1223                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1224
1225                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1226                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1227                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1228                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1229                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1230                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1231                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1232                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1233                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1234                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1235                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1236                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1237
1238                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1239                 b43_phy_write(dev, 0x2A7, e->init_gain);
1240                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1241                                         e->rfseq_init);
1242                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1243
1244                 /* TODO: check defines. Do not match variables names */
1245                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1246                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1247                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1248                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1249                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1250                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1251
1252                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1253                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1254                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1255                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1256                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1257                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1258                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1259                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1260                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1261                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1262         } else {
1263                 /* Set Clip 2 detect */
1264                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1265                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1266                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1267                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1268
1269                 /* Set narrowband clip threshold */
1270                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1271                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1272
1273                 if (!dev->phy.is_40mhz) {
1274                         /* Set dwell lengths */
1275                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1276                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1277                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1278                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1279                 }
1280
1281                 /* Set wideband clip 2 threshold */
1282                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1283                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1284                                 21);
1285                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1286                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1287                                 21);
1288
1289                 if (!dev->phy.is_40mhz) {
1290                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1291                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1292                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1293                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1294                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1295                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1296                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1297                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1298                 }
1299
1300                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1301
1302                 if (nphy->gain_boost) {
1303                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1304                             dev->phy.is_40mhz)
1305                                 code = 4;
1306                         else
1307                                 code = 5;
1308                 } else {
1309                         code = dev->phy.is_40mhz ? 6 : 7;
1310                 }
1311
1312                 /* Set HPVGA2 index */
1313                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1314                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1315                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1316                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1317                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1318                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1319
1320                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1321                 /* specs say about 2 loops, but wl does 4 */
1322                 for (i = 0; i < 4; i++)
1323                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1324                                                         (code << 8 | 0x7C));
1325
1326                 b43_nphy_adjust_lna_gain_table(dev);
1327
1328                 if (nphy->elna_gain_config) {
1329                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1330                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1331                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1332                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1333                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1334
1335                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1336                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1337                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1338                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1339                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1340
1341                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1342                         /* specs say about 2 loops, but wl does 4 */
1343                         for (i = 0; i < 4; i++)
1344                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1345                                                         (code << 8 | 0x74));
1346                 }
1347
1348                 if (dev->phy.rev == 2) {
1349                         for (i = 0; i < 4; i++) {
1350                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1351                                                 (0x0400 * i) + 0x0020);
1352                                 for (j = 0; j < 21; j++) {
1353                                         tmp = j * (i < 2 ? 3 : 1);
1354                                         b43_phy_write(dev,
1355                                                 B43_NPHY_TABLE_DATALO, tmp);
1356                                 }
1357                         }
1358                 }
1359
1360                 b43_nphy_set_rf_sequence(dev, 5,
1361                                 rfseq_events, rfseq_delays, 3);
1362                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1363                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1364                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1365
1366                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1367                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1368                                         0xFF80, 4);
1369         }
1370 }
1371
1372 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1373 static void b43_nphy_workarounds(struct b43_wldev *dev)
1374 {
1375         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1376         struct b43_phy *phy = &dev->phy;
1377         struct b43_phy_n *nphy = phy->n;
1378
1379         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1380         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1381
1382         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1383         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1384
1385         u16 tmp16;
1386         u32 tmp32;
1387
1388         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1389                 b43_nphy_classifier(dev, 1, 0);
1390         else
1391                 b43_nphy_classifier(dev, 1, 1);
1392
1393         if (nphy->hang_avoid)
1394                 b43_nphy_stay_in_carrier_search(dev, 1);
1395
1396         b43_phy_set(dev, B43_NPHY_IQFLIP,
1397                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1398
1399         if (dev->phy.rev >= 3) {
1400                 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1401                 tmp32 &= 0xffffff;
1402                 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1403
1404                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1405                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1406                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1407                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1408                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1409                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1410
1411                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1412                 b43_phy_write(dev, 0x2AE, 0x000C);
1413
1414                 /* TODO */
1415
1416                 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1417                         0x2 : 0x9C40;
1418                 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1419
1420                 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1421
1422                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1423                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1424
1425                 b43_nphy_gain_ctrl_workarounds(dev);
1426
1427                 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1428                 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1429
1430                 /* TODO */
1431
1432                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1433                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1434                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1435                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1436                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1437                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1438                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1439                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1440                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1441                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1442
1443                 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1444
1445                 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1446                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1447                     (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1448                     b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1449                         tmp32 = 0x00088888;
1450                 else
1451                         tmp32 = 0x88888888;
1452                 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1453                 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1454                 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1455
1456                 if (dev->phy.rev == 4 &&
1457                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1458                         b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1459                                         0x70);
1460                         b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1461                                         0x70);
1462                 }
1463
1464                 b43_phy_write(dev, 0x224, 0x039C);
1465                 b43_phy_write(dev, 0x225, 0x0357);
1466                 b43_phy_write(dev, 0x226, 0x0317);
1467                 b43_phy_write(dev, 0x227, 0x02D7);
1468                 b43_phy_write(dev, 0x228, 0x039C);
1469                 b43_phy_write(dev, 0x229, 0x0357);
1470                 b43_phy_write(dev, 0x22A, 0x0317);
1471                 b43_phy_write(dev, 0x22B, 0x02D7);
1472                 b43_phy_write(dev, 0x22C, 0x039C);
1473                 b43_phy_write(dev, 0x22D, 0x0357);
1474                 b43_phy_write(dev, 0x22E, 0x0317);
1475                 b43_phy_write(dev, 0x22F, 0x02D7);
1476         } else {
1477                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1478                     nphy->band5g_pwrgain) {
1479                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1480                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1481                 } else {
1482                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1483                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1484                 }
1485
1486                 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1487                 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1488                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1489                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1490
1491                 if (dev->phy.rev < 2) {
1492                         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1493                         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1494                         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1495                         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1496                         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1497                         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1498                 }
1499
1500                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1501                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1502                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1503                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1504
1505                 if (sprom->boardflags2_lo & 0x100 &&
1506                     dev->dev->board_type == 0x8B) {
1507                         delays1[0] = 0x1;
1508                         delays1[5] = 0x14;
1509                 }
1510                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1511                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1512
1513                 b43_nphy_gain_ctrl_workarounds(dev);
1514
1515                 if (dev->phy.rev < 2) {
1516                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1517                                 b43_hf_write(dev, b43_hf_read(dev) |
1518                                                 B43_HF_MLADVW);
1519                 } else if (dev->phy.rev == 2) {
1520                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1521                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1522                 }
1523
1524                 if (dev->phy.rev < 2)
1525                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1526                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1527
1528                 /* Set phase track alpha and beta */
1529                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1530                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1531                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1532                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1533                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1534                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1535
1536                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1537                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1538                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1539                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1540                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1541
1542                 if (dev->phy.rev == 2)
1543                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1544                                         B43_NPHY_FINERX2_CGC_DECGC);
1545         }
1546
1547         if (nphy->hang_avoid)
1548                 b43_nphy_stay_in_carrier_search(dev, 0);
1549 }
1550
1551 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1552 static int b43_nphy_load_samples(struct b43_wldev *dev,
1553                                         struct b43_c32 *samples, u16 len) {
1554         struct b43_phy_n *nphy = dev->phy.n;
1555         u16 i;
1556         u32 *data;
1557
1558         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1559         if (!data) {
1560                 b43err(dev->wl, "allocation for samples loading failed\n");
1561                 return -ENOMEM;
1562         }
1563         if (nphy->hang_avoid)
1564                 b43_nphy_stay_in_carrier_search(dev, 1);
1565
1566         for (i = 0; i < len; i++) {
1567                 data[i] = (samples[i].i & 0x3FF << 10);
1568                 data[i] |= samples[i].q & 0x3FF;
1569         }
1570         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1571
1572         kfree(data);
1573         if (nphy->hang_avoid)
1574                 b43_nphy_stay_in_carrier_search(dev, 0);
1575         return 0;
1576 }
1577
1578 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1579 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1580                                         bool test)
1581 {
1582         int i;
1583         u16 bw, len, rot, angle;
1584         struct b43_c32 *samples;
1585
1586
1587         bw = (dev->phy.is_40mhz) ? 40 : 20;
1588         len = bw << 3;
1589
1590         if (test) {
1591                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1592                         bw = 82;
1593                 else
1594                         bw = 80;
1595
1596                 if (dev->phy.is_40mhz)
1597                         bw <<= 1;
1598
1599                 len = bw << 1;
1600         }
1601
1602         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1603         if (!samples) {
1604                 b43err(dev->wl, "allocation for samples generation failed\n");
1605                 return 0;
1606         }
1607         rot = (((freq * 36) / bw) << 16) / 100;
1608         angle = 0;
1609
1610         for (i = 0; i < len; i++) {
1611                 samples[i] = b43_cordic(angle);
1612                 angle += rot;
1613                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1614                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1615         }
1616
1617         i = b43_nphy_load_samples(dev, samples, len);
1618         kfree(samples);
1619         return (i < 0) ? 0 : len;
1620 }
1621
1622 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1623 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1624                                         u16 wait, bool iqmode, bool dac_test)
1625 {
1626         struct b43_phy_n *nphy = dev->phy.n;
1627         int i;
1628         u16 seq_mode;
1629         u32 tmp;
1630
1631         if (nphy->hang_avoid)
1632                 b43_nphy_stay_in_carrier_search(dev, true);
1633
1634         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1635                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1636                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1637         }
1638
1639         if (!dev->phy.is_40mhz)
1640                 tmp = 0x6464;
1641         else
1642                 tmp = 0x4747;
1643         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1644
1645         if (nphy->hang_avoid)
1646                 b43_nphy_stay_in_carrier_search(dev, false);
1647
1648         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1649
1650         if (loops != 0xFFFF)
1651                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1652         else
1653                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1654
1655         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1656
1657         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1658
1659         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1660         if (iqmode) {
1661                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1662                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1663         } else {
1664                 if (dac_test)
1665                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1666                 else
1667                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1668         }
1669         for (i = 0; i < 100; i++) {
1670                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1671                         i = 0;
1672                         break;
1673                 }
1674                 udelay(10);
1675         }
1676         if (i)
1677                 b43err(dev->wl, "run samples timeout\n");
1678
1679         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1680 }
1681
1682 /*
1683  * Transmits a known value for LO calibration
1684  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1685  */
1686 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1687                                 bool iqmode, bool dac_test)
1688 {
1689         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1690         if (samp == 0)
1691                 return -1;
1692         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1693         return 0;
1694 }
1695
1696 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1697 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1698 {
1699         struct b43_phy_n *nphy = dev->phy.n;
1700         int i, j;
1701         u32 tmp;
1702         u32 cur_real, cur_imag, real_part, imag_part;
1703
1704         u16 buffer[7];
1705
1706         if (nphy->hang_avoid)
1707                 b43_nphy_stay_in_carrier_search(dev, true);
1708
1709         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1710
1711         for (i = 0; i < 2; i++) {
1712                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1713                         (buffer[i * 2 + 1] & 0x3FF);
1714                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1715                                 (((i + 26) << 10) | 320));
1716                 for (j = 0; j < 128; j++) {
1717                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1718                                         ((tmp >> 16) & 0xFFFF));
1719                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1720                                         (tmp & 0xFFFF));
1721                 }
1722         }
1723
1724         for (i = 0; i < 2; i++) {
1725                 tmp = buffer[5 + i];
1726                 real_part = (tmp >> 8) & 0xFF;
1727                 imag_part = (tmp & 0xFF);
1728                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1729                                 (((i + 26) << 10) | 448));
1730
1731                 if (dev->phy.rev >= 3) {
1732                         cur_real = real_part;
1733                         cur_imag = imag_part;
1734                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1735                 }
1736
1737                 for (j = 0; j < 128; j++) {
1738                         if (dev->phy.rev < 3) {
1739                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1740                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1741                                 tmp = ((cur_real & 0xFF) << 8) |
1742                                         (cur_imag & 0xFF);
1743                         }
1744                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1745                                         ((tmp >> 16) & 0xFFFF));
1746                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1747                                         (tmp & 0xFFFF));
1748                 }
1749         }
1750
1751         if (dev->phy.rev >= 3) {
1752                 b43_shm_write16(dev, B43_SHM_SHARED,
1753                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1754                 b43_shm_write16(dev, B43_SHM_SHARED,
1755                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1756         }
1757
1758         if (nphy->hang_avoid)
1759                 b43_nphy_stay_in_carrier_search(dev, false);
1760 }
1761
1762 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1763 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1764                                         u8 *events, u8 *delays, u8 length)
1765 {
1766         struct b43_phy_n *nphy = dev->phy.n;
1767         u8 i;
1768         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1769         u16 offset1 = cmd << 4;
1770         u16 offset2 = offset1 + 0x80;
1771
1772         if (nphy->hang_avoid)
1773                 b43_nphy_stay_in_carrier_search(dev, true);
1774
1775         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1776         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1777
1778         for (i = length; i < 16; i++) {
1779                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1780                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1781         }
1782
1783         if (nphy->hang_avoid)
1784                 b43_nphy_stay_in_carrier_search(dev, false);
1785 }
1786
1787 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1788 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1789                                        enum b43_nphy_rf_sequence seq)
1790 {
1791         static const u16 trigger[] = {
1792                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1793                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1794                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1795                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1796                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1797                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1798         };
1799         int i;
1800         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1801
1802         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1803
1804         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1805                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1806         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1807         for (i = 0; i < 200; i++) {
1808                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1809                         goto ok;
1810                 msleep(1);
1811         }
1812         b43err(dev->wl, "RF sequence status timeout\n");
1813 ok:
1814         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1815 }
1816
1817 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1818 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1819                                                 u16 value, u8 core, bool off)
1820 {
1821         int i;
1822         u8 index = fls(field);
1823         u8 addr, en_addr, val_addr;
1824         /* we expect only one bit set */
1825         B43_WARN_ON(field & (~(1 << (index - 1))));
1826
1827         if (dev->phy.rev >= 3) {
1828                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1829                 for (i = 0; i < 2; i++) {
1830                         if (index == 0 || index == 16) {
1831                                 b43err(dev->wl,
1832                                         "Unsupported RF Ctrl Override call\n");
1833                                 return;
1834                         }
1835
1836                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1837                         en_addr = B43_PHY_N((i == 0) ?
1838                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1839                         val_addr = B43_PHY_N((i == 0) ?
1840                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1841
1842                         if (off) {
1843                                 b43_phy_mask(dev, en_addr, ~(field));
1844                                 b43_phy_mask(dev, val_addr,
1845                                                 ~(rf_ctrl->val_mask));
1846                         } else {
1847                                 if (core == 0 || ((1 << core) & i) != 0) {
1848                                         b43_phy_set(dev, en_addr, field);
1849                                         b43_phy_maskset(dev, val_addr,
1850                                                 ~(rf_ctrl->val_mask),
1851                                                 (value << rf_ctrl->val_shift));
1852                                 }
1853                         }
1854                 }
1855         } else {
1856                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1857                 if (off) {
1858                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1859                         value = 0;
1860                 } else {
1861                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1862                 }
1863
1864                 for (i = 0; i < 2; i++) {
1865                         if (index <= 1 || index == 16) {
1866                                 b43err(dev->wl,
1867                                         "Unsupported RF Ctrl Override call\n");
1868                                 return;
1869                         }
1870
1871                         if (index == 2 || index == 10 ||
1872                             (index >= 13 && index <= 15)) {
1873                                 core = 1;
1874                         }
1875
1876                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1877                         addr = B43_PHY_N((i == 0) ?
1878                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1879
1880                         if ((core & (1 << i)) != 0)
1881                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1882                                                 (value << rf_ctrl->shift));
1883
1884                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1885                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1886                                         B43_NPHY_RFCTL_CMD_START);
1887                         udelay(1);
1888                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1889                 }
1890         }
1891 }
1892
1893 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1894 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1895                                                 u16 value, u8 core)
1896 {
1897         u8 i, j;
1898         u16 reg, tmp, val;
1899
1900         B43_WARN_ON(dev->phy.rev < 3);
1901         B43_WARN_ON(field > 4);
1902
1903         for (i = 0; i < 2; i++) {
1904                 if ((core == 1 && i == 1) || (core == 2 && !i))
1905                         continue;
1906
1907                 reg = (i == 0) ?
1908                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1909                 b43_phy_mask(dev, reg, 0xFBFF);
1910
1911                 switch (field) {
1912                 case 0:
1913                         b43_phy_write(dev, reg, 0);
1914                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1915                         break;
1916                 case 1:
1917                         if (!i) {
1918                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1919                                                 0xFC3F, (value << 6));
1920                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1921                                                 0xFFFE, 1);
1922                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1923                                                 B43_NPHY_RFCTL_CMD_START);
1924                                 for (j = 0; j < 100; j++) {
1925                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1926                                                 j = 0;
1927                                                 break;
1928                                         }
1929                                         udelay(10);
1930                                 }
1931                                 if (j)
1932                                         b43err(dev->wl,
1933                                                 "intc override timeout\n");
1934                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1935                                                 0xFFFE);
1936                         } else {
1937                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1938                                                 0xFC3F, (value << 6));
1939                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1940                                                 0xFFFE, 1);
1941                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1942                                                 B43_NPHY_RFCTL_CMD_RXTX);
1943                                 for (j = 0; j < 100; j++) {
1944                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1945                                                 j = 0;
1946                                                 break;
1947                                         }
1948                                         udelay(10);
1949                                 }
1950                                 if (j)
1951                                         b43err(dev->wl,
1952                                                 "intc override timeout\n");
1953                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1954                                                 0xFFFE);
1955                         }
1956                         break;
1957                 case 2:
1958                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1959                                 tmp = 0x0020;
1960                                 val = value << 5;
1961                         } else {
1962                                 tmp = 0x0010;
1963                                 val = value << 4;
1964                         }
1965                         b43_phy_maskset(dev, reg, ~tmp, val);
1966                         break;
1967                 case 3:
1968                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1969                                 tmp = 0x0001;
1970                                 val = value;
1971                         } else {
1972                                 tmp = 0x0004;
1973                                 val = value << 2;
1974                         }
1975                         b43_phy_maskset(dev, reg, ~tmp, val);
1976                         break;
1977                 case 4:
1978                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1979                                 tmp = 0x0002;
1980                                 val = value << 1;
1981                         } else {
1982                                 tmp = 0x0008;
1983                                 val = value << 3;
1984                         }
1985                         b43_phy_maskset(dev, reg, ~tmp, val);
1986                         break;
1987                 }
1988         }
1989 }
1990
1991 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
1992 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1993 {
1994         unsigned int i;
1995         u16 val;
1996
1997         val = 0x1E1F;
1998         for (i = 0; i < 16; i++) {
1999                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2000                 val -= 0x202;
2001         }
2002         val = 0x3E3F;
2003         for (i = 0; i < 16; i++) {
2004                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2005                 val -= 0x202;
2006         }
2007         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2008 }
2009
2010 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2011 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2012                                         s8 offset, u8 core, u8 rail,
2013                                         enum b43_nphy_rssi_type type)
2014 {
2015         u16 tmp;
2016         bool core1or5 = (core == 1) || (core == 5);
2017         bool core2or5 = (core == 2) || (core == 5);
2018
2019         offset = clamp_val(offset, -32, 31);
2020         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2021
2022         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2023                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2024         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2025                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2026         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2027                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2028         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2029                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2030
2031         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2032                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2033         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2034                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2035         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2036                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2037         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2038                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2039
2040         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2041                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2042         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2043                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2044         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2045                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2046         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2047                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2048
2049         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2050                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2051         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2052                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2053         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2054                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2055         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2056                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2057
2058         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2059                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2060         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2061                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2062         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2063                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2064         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2065                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2066
2067         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2068                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2069         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2070                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2071
2072         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2073                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2074         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2075                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2076 }
2077
2078 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2079 {
2080         u16 val;
2081
2082         if (type < 3)
2083                 val = 0;
2084         else if (type == 6)
2085                 val = 1;
2086         else if (type == 3)
2087                 val = 2;
2088         else
2089                 val = 3;
2090
2091         val = (val << 12) | (val << 14);
2092         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2093         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2094
2095         if (type < 3) {
2096                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2097                                 (type + 1) << 4);
2098                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2099                                 (type + 1) << 4);
2100         }
2101
2102         if (code == 0) {
2103                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2104                 if (type < 3) {
2105                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2106                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2107                                   B43_NPHY_RFCTL_CMD_CORESEL));
2108                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2109                                 ~(0x1 << 12 |
2110                                   0x1 << 5 |
2111                                   0x1 << 1 |
2112                                   0x1));
2113                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2114                                 ~B43_NPHY_RFCTL_CMD_START);
2115                         udelay(20);
2116                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2117                 }
2118         } else {
2119                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2120                 if (type < 3) {
2121                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2122                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2123                                   B43_NPHY_RFCTL_CMD_CORESEL),
2124                                 (B43_NPHY_RFCTL_CMD_RXEN |
2125                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2126                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2127                                 (0x1 << 12 |
2128                                   0x1 << 5 |
2129                                   0x1 << 1 |
2130                                   0x1));
2131                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2132                                 B43_NPHY_RFCTL_CMD_START);
2133                         udelay(20);
2134                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2135                 }
2136         }
2137 }
2138
2139 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2140 {
2141         struct b43_phy_n *nphy = dev->phy.n;
2142         u8 i;
2143         u16 reg, val;
2144
2145         if (code == 0) {
2146                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2147                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2148                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2149                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2150                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2151                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2152                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2153                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2154         } else {
2155                 for (i = 0; i < 2; i++) {
2156                         if ((code == 1 && i == 1) || (code == 2 && !i))
2157                                 continue;
2158
2159                         reg = (i == 0) ?
2160                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2161                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2162
2163                         if (type < 3) {
2164                                 reg = (i == 0) ?
2165                                         B43_NPHY_AFECTL_C1 :
2166                                         B43_NPHY_AFECTL_C2;
2167                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2168
2169                                 reg = (i == 0) ?
2170                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2171                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2172                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2173
2174                                 if (type == 0)
2175                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2176                                 else if (type == 1)
2177                                         val = 16;
2178                                 else
2179                                         val = 32;
2180                                 b43_phy_set(dev, reg, val);
2181
2182                                 reg = (i == 0) ?
2183                                         B43_NPHY_TXF_40CO_B1S0 :
2184                                         B43_NPHY_TXF_40CO_B32S1;
2185                                 b43_phy_set(dev, reg, 0x0020);
2186                         } else {
2187                                 if (type == 6)
2188                                         val = 0x0100;
2189                                 else if (type == 3)
2190                                         val = 0x0200;
2191                                 else
2192                                         val = 0x0300;
2193
2194                                 reg = (i == 0) ?
2195                                         B43_NPHY_AFECTL_C1 :
2196                                         B43_NPHY_AFECTL_C2;
2197
2198                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2199                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2200
2201                                 if (type != 3 && type != 6) {
2202                                         enum ieee80211_band band =
2203                                                 b43_current_band(dev->wl);
2204
2205                                         if ((nphy->ipa2g_on &&
2206                                                 band == IEEE80211_BAND_2GHZ) ||
2207                                                 (nphy->ipa5g_on &&
2208                                                 band == IEEE80211_BAND_5GHZ))
2209                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2210                                         else
2211                                                 val = 0x11;
2212                                         reg = (i == 0) ? 0x2000 : 0x3000;
2213                                         reg |= B2055_PADDRV;
2214                                         b43_radio_write16(dev, reg, val);
2215
2216                                         reg = (i == 0) ?
2217                                                 B43_NPHY_AFECTL_OVER1 :
2218                                                 B43_NPHY_AFECTL_OVER;
2219                                         b43_phy_set(dev, reg, 0x0200);
2220                                 }
2221                         }
2222                 }
2223         }
2224 }
2225
2226 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2227 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2228 {
2229         if (dev->phy.rev >= 3)
2230                 b43_nphy_rev3_rssi_select(dev, code, type);
2231         else
2232                 b43_nphy_rev2_rssi_select(dev, code, type);
2233 }
2234
2235 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2236 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2237 {
2238         int i;
2239         for (i = 0; i < 2; i++) {
2240                 if (type == 2) {
2241                         if (i == 0) {
2242                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2243                                                   0xFC, buf[0]);
2244                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2245                                                   0xFC, buf[1]);
2246                         } else {
2247                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2248                                                   0xFC, buf[2 * i]);
2249                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2250                                                   0xFC, buf[2 * i + 1]);
2251                         }
2252                 } else {
2253                         if (i == 0)
2254                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2255                                                   0xF3, buf[0] << 2);
2256                         else
2257                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2258                                                   0xF3, buf[2 * i + 1] << 2);
2259                 }
2260         }
2261 }
2262
2263 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2264 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2265                                 u8 nsamp)
2266 {
2267         int i;
2268         int out;
2269         u16 save_regs_phy[9];
2270         u16 s[2];
2271
2272         if (dev->phy.rev >= 3) {
2273                 save_regs_phy[0] = b43_phy_read(dev,
2274                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2275                 save_regs_phy[1] = b43_phy_read(dev,
2276                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2277                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2278                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2279                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2280                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2281                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2282                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2283                 save_regs_phy[8] = 0;
2284         } else {
2285                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2286                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2287                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2288                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2289                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2290                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2291                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2292                 save_regs_phy[7] = 0;
2293                 save_regs_phy[8] = 0;
2294         }
2295
2296         b43_nphy_rssi_select(dev, 5, type);
2297
2298         if (dev->phy.rev < 2) {
2299                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2300                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2301         }
2302
2303         for (i = 0; i < 4; i++)
2304                 buf[i] = 0;
2305
2306         for (i = 0; i < nsamp; i++) {
2307                 if (dev->phy.rev < 2) {
2308                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2309                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2310                 } else {
2311                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2312                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2313                 }
2314
2315                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2316                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2317                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2318                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2319         }
2320         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2321                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2322
2323         if (dev->phy.rev < 2)
2324                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2325
2326         if (dev->phy.rev >= 3) {
2327                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2328                                 save_regs_phy[0]);
2329                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2330                                 save_regs_phy[1]);
2331                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2332                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2333                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2334                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2335                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2336                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2337         } else {
2338                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2339                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2340                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2341                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2342                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2343                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2344                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2345         }
2346
2347         return out;
2348 }
2349
2350 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2351 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2352 {
2353         int i, j;
2354         u8 state[4];
2355         u8 code, val;
2356         u16 class, override;
2357         u8 regs_save_radio[2];
2358         u16 regs_save_phy[2];
2359
2360         s8 offset[4];
2361         u8 core;
2362         u8 rail;
2363
2364         u16 clip_state[2];
2365         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2366         s32 results_min[4] = { };
2367         u8 vcm_final[4] = { };
2368         s32 results[4][4] = { };
2369         s32 miniq[4][2] = { };
2370
2371         if (type == 2) {
2372                 code = 0;
2373                 val = 6;
2374         } else if (type < 2) {
2375                 code = 25;
2376                 val = 4;
2377         } else {
2378                 B43_WARN_ON(1);
2379                 return;
2380         }
2381
2382         class = b43_nphy_classifier(dev, 0, 0);
2383         b43_nphy_classifier(dev, 7, 4);
2384         b43_nphy_read_clip_detection(dev, clip_state);
2385         b43_nphy_write_clip_detection(dev, clip_off);
2386
2387         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2388                 override = 0x140;
2389         else
2390                 override = 0x110;
2391
2392         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2393         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2394         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2395         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2396
2397         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2398         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2399         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2400         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2401
2402         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2403         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2404         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2405         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2406         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2407         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2408
2409         b43_nphy_rssi_select(dev, 5, type);
2410         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2411         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2412
2413         for (i = 0; i < 4; i++) {
2414                 u8 tmp[4];
2415                 for (j = 0; j < 4; j++)
2416                         tmp[j] = i;
2417                 if (type != 1)
2418                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2419                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2420                 if (type < 2)
2421                         for (j = 0; j < 2; j++)
2422                                 miniq[i][j] = min(results[i][2 * j],
2423                                                 results[i][2 * j + 1]);
2424         }
2425
2426         for (i = 0; i < 4; i++) {
2427                 s32 mind = 40;
2428                 u8 minvcm = 0;
2429                 s32 minpoll = 249;
2430                 s32 curr;
2431                 for (j = 0; j < 4; j++) {
2432                         if (type == 2)
2433                                 curr = abs(results[j][i]);
2434                         else
2435                                 curr = abs(miniq[j][i / 2] - code * 8);
2436
2437                         if (curr < mind) {
2438                                 mind = curr;
2439                                 minvcm = j;
2440                         }
2441
2442                         if (results[j][i] < minpoll)
2443                                 minpoll = results[j][i];
2444                 }
2445                 results_min[i] = minpoll;
2446                 vcm_final[i] = minvcm;
2447         }
2448
2449         if (type != 1)
2450                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2451
2452         for (i = 0; i < 4; i++) {
2453                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2454
2455                 if (offset[i] < 0)
2456                         offset[i] = -((abs(offset[i]) + 4) / 8);
2457                 else
2458                         offset[i] = (offset[i] + 4) / 8;
2459
2460                 if (results_min[i] == 248)
2461                         offset[i] = code - 32;
2462
2463                 core = (i / 2) ? 2 : 1;
2464                 rail = (i % 2) ? 1 : 0;
2465
2466                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2467                                                 type);
2468         }
2469
2470         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2471         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2472
2473         switch (state[2]) {
2474         case 1:
2475                 b43_nphy_rssi_select(dev, 1, 2);
2476                 break;
2477         case 4:
2478                 b43_nphy_rssi_select(dev, 1, 0);
2479                 break;
2480         case 2:
2481                 b43_nphy_rssi_select(dev, 1, 1);
2482                 break;
2483         default:
2484                 b43_nphy_rssi_select(dev, 1, 1);
2485                 break;
2486         }
2487
2488         switch (state[3]) {
2489         case 1:
2490                 b43_nphy_rssi_select(dev, 2, 2);
2491                 break;
2492         case 4:
2493                 b43_nphy_rssi_select(dev, 2, 0);
2494                 break;
2495         default:
2496                 b43_nphy_rssi_select(dev, 2, 1);
2497                 break;
2498         }
2499
2500         b43_nphy_rssi_select(dev, 0, type);
2501
2502         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2503         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2504         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2505         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2506
2507         b43_nphy_classifier(dev, 7, class);
2508         b43_nphy_write_clip_detection(dev, clip_state);
2509         /* Specs don't say about reset here, but it makes wl and b43 dumps
2510            identical, it really seems wl performs this */
2511         b43_nphy_reset_cca(dev);
2512 }
2513
2514 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2515 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2516 {
2517         /* TODO */
2518 }
2519
2520 /*
2521  * RSSI Calibration
2522  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2523  */
2524 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2525 {
2526         if (dev->phy.rev >= 3) {
2527                 b43_nphy_rev3_rssi_cal(dev);
2528         } else {
2529                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2530                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2531                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2532         }
2533 }
2534
2535 /*
2536  * Restore RSSI Calibration
2537  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2538  */
2539 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2540 {
2541         struct b43_phy_n *nphy = dev->phy.n;
2542
2543         u16 *rssical_radio_regs = NULL;
2544         u16 *rssical_phy_regs = NULL;
2545
2546         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2547                 if (!nphy->rssical_chanspec_2G.center_freq)
2548                         return;
2549                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2550                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2551         } else {
2552                 if (!nphy->rssical_chanspec_5G.center_freq)
2553                         return;
2554                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2555                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2556         }
2557
2558         /* TODO use some definitions */
2559         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2560         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2561
2562         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2563         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2564         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2565         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2566
2567         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2568         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2569         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2570         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2571
2572         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2573         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2574         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2575         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2576 }
2577
2578 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2579 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2580 {
2581         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2582                 if (dev->phy.rev >= 6) {
2583                         /* TODO If the chip is 47162
2584                                 return txpwrctrl_tx_gain_ipa_rev5 */
2585                         return txpwrctrl_tx_gain_ipa_rev6;
2586                 } else if (dev->phy.rev >= 5) {
2587                         return txpwrctrl_tx_gain_ipa_rev5;
2588                 } else {
2589                         return txpwrctrl_tx_gain_ipa;
2590                 }
2591         } else {
2592                 return txpwrctrl_tx_gain_ipa_5g;
2593         }
2594 }
2595
2596 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2597 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2598 {
2599         struct b43_phy_n *nphy = dev->phy.n;
2600         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2601         u16 tmp;
2602         u8 offset, i;
2603
2604         if (dev->phy.rev >= 3) {
2605             for (i = 0; i < 2; i++) {
2606                 tmp = (i == 0) ? 0x2000 : 0x3000;
2607                 offset = i * 11;
2608
2609                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2610                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2611                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2612                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2613                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2614                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2615                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2616                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2617                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2618                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2619                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2620
2621                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2622                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2623                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2624                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2625                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2626                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2627                         if (nphy->ipa5g_on) {
2628                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2629                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2630                         } else {
2631                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2632                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2633                         }
2634                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2635                 } else {
2636                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2637                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2638                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2639                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2640                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2641                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2642                         if (nphy->ipa2g_on) {
2643                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2644                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2645                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2646                         } else {
2647                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2648                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2649                         }
2650                 }
2651                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2652                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2653                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2654             }
2655         } else {
2656                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2657                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2658
2659                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2660                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2661
2662                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2663                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2664
2665                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2666                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2667
2668                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2669                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2670
2671                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2672                     B43_NPHY_BANDCTL_5GHZ)) {
2673                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2674                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2675                 } else {
2676                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2677                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2678                 }
2679
2680                 if (dev->phy.rev < 2) {
2681                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2682                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2683                 } else {
2684                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2685                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2686                 }
2687         }
2688 }
2689
2690 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2691 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2692                                         struct nphy_txgains target,
2693                                         struct nphy_iqcal_params *params)
2694 {
2695         int i, j, indx;
2696         u16 gain;
2697
2698         if (dev->phy.rev >= 3) {
2699                 params->txgm = target.txgm[core];
2700                 params->pga = target.pga[core];
2701                 params->pad = target.pad[core];
2702                 params->ipa = target.ipa[core];
2703                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2704                                         (params->pad << 4) | (params->ipa);
2705                 for (j = 0; j < 5; j++)
2706                         params->ncorr[j] = 0x79;
2707         } else {
2708                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2709                         (target.txgm[core] << 8);
2710
2711                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2712                         1 : 0;
2713                 for (i = 0; i < 9; i++)
2714                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2715                                 break;
2716                 i = min(i, 8);
2717
2718                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2719                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2720                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2721                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2722                                         (params->pad << 2);
2723                 for (j = 0; j < 4; j++)
2724                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2725         }
2726 }
2727
2728 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2729 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2730 {
2731         struct b43_phy_n *nphy = dev->phy.n;
2732         int i;
2733         u16 scale, entry;
2734
2735         u16 tmp = nphy->txcal_bbmult;
2736         if (core == 0)
2737                 tmp >>= 8;
2738         tmp &= 0xff;
2739
2740         for (i = 0; i < 18; i++) {
2741                 scale = (ladder_lo[i].percent * tmp) / 100;
2742                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2743                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2744
2745                 scale = (ladder_iq[i].percent * tmp) / 100;
2746                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2747                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2748         }
2749 }
2750
2751 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2752 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2753 {
2754         int i;
2755         for (i = 0; i < 15; i++)
2756                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2757                                 tbl_tx_filter_coef_rev4[2][i]);
2758 }
2759
2760 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2761 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2762 {
2763         int i, j;
2764         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2765         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2766
2767         for (i = 0; i < 3; i++)
2768                 for (j = 0; j < 15; j++)
2769                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2770                                         tbl_tx_filter_coef_rev4[i][j]);
2771
2772         if (dev->phy.is_40mhz) {
2773                 for (j = 0; j < 15; j++)
2774                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2775                                         tbl_tx_filter_coef_rev4[3][j]);
2776         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2777                 for (j = 0; j < 15; j++)
2778                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2779                                         tbl_tx_filter_coef_rev4[5][j]);
2780         }
2781
2782         if (dev->phy.channel == 14)
2783                 for (j = 0; j < 15; j++)
2784                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2785                                         tbl_tx_filter_coef_rev4[6][j]);
2786 }
2787
2788 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2789 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2790 {
2791         struct b43_phy_n *nphy = dev->phy.n;
2792
2793         u16 curr_gain[2];
2794         struct nphy_txgains target;
2795         const u32 *table = NULL;
2796
2797         if (!nphy->txpwrctrl) {
2798                 int i;
2799
2800                 if (nphy->hang_avoid)
2801                         b43_nphy_stay_in_carrier_search(dev, true);
2802                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2803                 if (nphy->hang_avoid)
2804                         b43_nphy_stay_in_carrier_search(dev, false);
2805
2806                 for (i = 0; i < 2; ++i) {
2807                         if (dev->phy.rev >= 3) {
2808                                 target.ipa[i] = curr_gain[i] & 0x000F;
2809                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2810                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2811                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2812                         } else {
2813                                 target.ipa[i] = curr_gain[i] & 0x0003;
2814                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2815                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2816                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2817                         }
2818                 }
2819         } else {
2820                 int i;
2821                 u16 index[2];
2822                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2823                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2824                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2825                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2826                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2827                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2828
2829                 for (i = 0; i < 2; ++i) {
2830                         if (dev->phy.rev >= 3) {
2831                                 enum ieee80211_band band =
2832                                         b43_current_band(dev->wl);
2833
2834                                 if ((nphy->ipa2g_on &&
2835                                      band == IEEE80211_BAND_2GHZ) ||
2836                                     (nphy->ipa5g_on &&
2837                                      band == IEEE80211_BAND_5GHZ)) {
2838                                         table = b43_nphy_get_ipa_gain_table(dev);
2839                                 } else {
2840                                         if (band == IEEE80211_BAND_5GHZ) {
2841                                                 if (dev->phy.rev == 3)
2842                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2843                                                 else if (dev->phy.rev == 4)
2844                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2845                                                 else
2846                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2847                                         } else {
2848                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2849                                         }
2850                                 }
2851
2852                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2853                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2854                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2855                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2856                         } else {
2857                                 table = b43_ntab_tx_gain_rev0_1_2;
2858
2859                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2860                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2861                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2862                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2863                         }
2864                 }
2865         }
2866
2867         return target;
2868 }
2869
2870 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2871 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2872 {
2873         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2874
2875         if (dev->phy.rev >= 3) {
2876                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2877                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2878                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2879                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2880                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2881                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2882                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2883                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2884                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2885                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2886                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2887                 b43_nphy_reset_cca(dev);
2888         } else {
2889                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2890                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2891                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2892                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2893                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2894                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2895                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2896         }
2897 }
2898
2899 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2900 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2901 {
2902         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2903         u16 tmp;
2904
2905         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2906         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2907         if (dev->phy.rev >= 3) {
2908                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2909                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2910
2911                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2912                 regs[2] = tmp;
2913                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2914
2915                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2916                 regs[3] = tmp;
2917                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2918
2919                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2920                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2921                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2922
2923                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2924                 regs[5] = tmp;
2925                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2926
2927                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2928                 regs[6] = tmp;
2929                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2930                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2931                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2932
2933                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2934                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2935                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2936
2937                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2938                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2939                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2940                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2941         } else {
2942                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2943                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2944                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2945                 regs[2] = tmp;
2946                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2947                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2948                 regs[3] = tmp;
2949                 tmp |= 0x2000;
2950                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2951                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2952                 regs[4] = tmp;
2953                 tmp |= 0x2000;
2954                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2955                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2956                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2957                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2958                         tmp = 0x0180;
2959                 else
2960                         tmp = 0x0120;
2961                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2962                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2963         }
2964 }
2965
2966 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2967 static void b43_nphy_save_cal(struct b43_wldev *dev)
2968 {
2969         struct b43_phy_n *nphy = dev->phy.n;
2970
2971         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2972         u16 *txcal_radio_regs = NULL;
2973         struct b43_chanspec *iqcal_chanspec;
2974         u16 *table = NULL;
2975
2976         if (nphy->hang_avoid)
2977                 b43_nphy_stay_in_carrier_search(dev, 1);
2978
2979         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2980                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2981                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2982                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2983                 table = nphy->cal_cache.txcal_coeffs_2G;
2984         } else {
2985                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2986                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2987                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2988                 table = nphy->cal_cache.txcal_coeffs_5G;
2989         }
2990
2991         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2992         /* TODO use some definitions */
2993         if (dev->phy.rev >= 3) {
2994                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2995                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2996                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2997                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2998                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2999                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3000                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3001                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3002         } else {
3003                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3004                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3005                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3006                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3007         }
3008         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3009         iqcal_chanspec->channel_type = dev->phy.channel_type;
3010         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3011
3012         if (nphy->hang_avoid)
3013                 b43_nphy_stay_in_carrier_search(dev, 0);
3014 }
3015
3016 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3017 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3018 {
3019         struct b43_phy_n *nphy = dev->phy.n;
3020
3021         u16 coef[4];
3022         u16 *loft = NULL;
3023         u16 *table = NULL;
3024
3025         int i;
3026         u16 *txcal_radio_regs = NULL;
3027         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3028
3029         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3030                 if (!nphy->iqcal_chanspec_2G.center_freq)
3031                         return;
3032                 table = nphy->cal_cache.txcal_coeffs_2G;
3033                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3034         } else {
3035                 if (!nphy->iqcal_chanspec_5G.center_freq)
3036                         return;
3037                 table = nphy->cal_cache.txcal_coeffs_5G;
3038                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3039         }
3040
3041         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3042
3043         for (i = 0; i < 4; i++) {
3044                 if (dev->phy.rev >= 3)
3045                         table[i] = coef[i];
3046                 else
3047                         coef[i] = 0;
3048         }
3049
3050         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3051         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3052         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3053
3054         if (dev->phy.rev < 2)
3055                 b43_nphy_tx_iq_workaround(dev);
3056
3057         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3058                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3059                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3060         } else {
3061                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3062                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3063         }
3064
3065         /* TODO use some definitions */
3066         if (dev->phy.rev >= 3) {
3067                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3068                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3069                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3070                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3071                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3072                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3073                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3074                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3075         } else {
3076                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3077                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3078                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3079                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3080         }
3081         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3082 }
3083
3084 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3085 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3086                                 struct nphy_txgains target,
3087                                 bool full, bool mphase)
3088 {
3089         struct b43_phy_n *nphy = dev->phy.n;
3090         int i;
3091         int error = 0;
3092         int freq;
3093         bool avoid = false;
3094         u8 length;
3095         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3096         const u16 *table;
3097         bool phy6or5x;
3098
3099         u16 buffer[11];
3100         u16 diq_start = 0;
3101         u16 save[2];
3102         u16 gain[2];
3103         struct nphy_iqcal_params params[2];
3104         bool updated[2] = { };
3105
3106         b43_nphy_stay_in_carrier_search(dev, true);
3107
3108         if (dev->phy.rev >= 4) {
3109                 avoid = nphy->hang_avoid;
3110                 nphy->hang_avoid = 0;
3111         }
3112
3113         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3114
3115         for (i = 0; i < 2; i++) {
3116                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3117                 gain[i] = params[i].cal_gain;
3118         }
3119
3120         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3121
3122         b43_nphy_tx_cal_radio_setup(dev);
3123         b43_nphy_tx_cal_phy_setup(dev);
3124
3125         phy6or5x = dev->phy.rev >= 6 ||
3126                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3127                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3128         if (phy6or5x) {
3129                 if (dev->phy.is_40mhz) {
3130                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3131                                         tbl_tx_iqlo_cal_loft_ladder_40);
3132                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3133                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3134                 } else {
3135                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3136                                         tbl_tx_iqlo_cal_loft_ladder_20);
3137                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3138                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3139                 }
3140         }
3141
3142         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3143
3144         if (!dev->phy.is_40mhz)
3145                 freq = 2500;
3146         else
3147                 freq = 5000;
3148
3149         if (nphy->mphase_cal_phase_id > 2)
3150                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3151                                         0xFFFF, 0, true, false);
3152         else
3153                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3154
3155         if (error == 0) {
3156                 if (nphy->mphase_cal_phase_id > 2) {
3157                         table = nphy->mphase_txcal_bestcoeffs;
3158                         length = 11;
3159                         if (dev->phy.rev < 3)
3160                                 length -= 2;
3161                 } else {
3162                         if (!full && nphy->txiqlocal_coeffsvalid) {
3163                                 table = nphy->txiqlocal_bestc;
3164                                 length = 11;
3165                                 if (dev->phy.rev < 3)
3166                                         length -= 2;
3167                         } else {
3168                                 full = true;
3169                                 if (dev->phy.rev >= 3) {
3170                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3171                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3172                                 } else {
3173                                         table = tbl_tx_iqlo_cal_startcoefs;
3174                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3175                                 }
3176                         }
3177                 }
3178
3179                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3180
3181                 if (full) {
3182                         if (dev->phy.rev >= 3)
3183                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3184                         else
3185                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3186                 } else {
3187                         if (dev->phy.rev >= 3)
3188                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3189                         else
3190                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3191                 }
3192
3193                 if (mphase) {
3194                         count = nphy->mphase_txcal_cmdidx;
3195                         numb = min(max,
3196                                 (u16)(count + nphy->mphase_txcal_numcmds));
3197                 } else {
3198                         count = 0;
3199                         numb = max;
3200                 }
3201
3202                 for (; count < numb; count++) {
3203                         if (full) {
3204                                 if (dev->phy.rev >= 3)
3205                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3206                                 else
3207                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3208                         } else {
3209                                 if (dev->phy.rev >= 3)
3210                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3211                                 else
3212                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3213                         }
3214
3215                         core = (cmd & 0x3000) >> 12;
3216                         type = (cmd & 0x0F00) >> 8;
3217
3218                         if (phy6or5x && updated[core] == 0) {
3219                                 b43_nphy_update_tx_cal_ladder(dev, core);
3220                                 updated[core] = 1;
3221                         }
3222
3223                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3224                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3225
3226                         if (type == 1 || type == 3 || type == 4) {
3227                                 buffer[0] = b43_ntab_read(dev,
3228                                                 B43_NTAB16(15, 69 + core));
3229                                 diq_start = buffer[0];
3230                                 buffer[0] = 0;
3231                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3232                                                 0);
3233                         }
3234
3235                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3236                         for (i = 0; i < 2000; i++) {
3237                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3238                                 if (tmp & 0xC000)
3239                                         break;
3240                                 udelay(10);
3241                         }
3242
3243                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3244                                                 buffer);
3245                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3246                                                 buffer);
3247
3248                         if (type == 1 || type == 3 || type == 4)
3249                                 buffer[0] = diq_start;
3250                 }
3251
3252                 if (mphase)
3253                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3254
3255                 last = (dev->phy.rev < 3) ? 6 : 7;
3256
3257                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3258                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3259                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3260                         if (dev->phy.rev < 3) {
3261                                 buffer[0] = 0;
3262                                 buffer[1] = 0;
3263                                 buffer[2] = 0;
3264                                 buffer[3] = 0;
3265                         }
3266                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3267                                                 buffer);
3268                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3269                                                 buffer);
3270                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3271                                                 buffer);
3272                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3273                                                 buffer);
3274                         length = 11;
3275                         if (dev->phy.rev < 3)
3276                                 length -= 2;
3277                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3278                                                 nphy->txiqlocal_bestc);
3279                         nphy->txiqlocal_coeffsvalid = true;
3280                         nphy->txiqlocal_chanspec.center_freq =
3281                                                         dev->phy.channel_freq;
3282                         nphy->txiqlocal_chanspec.channel_type =
3283                                                         dev->phy.channel_type;
3284                 } else {
3285                         length = 11;
3286                         if (dev->phy.rev < 3)
3287                                 length -= 2;
3288                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3289                                                 nphy->mphase_txcal_bestcoeffs);
3290                 }
3291
3292                 b43_nphy_stop_playback(dev);
3293                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3294         }
3295
3296         b43_nphy_tx_cal_phy_cleanup(dev);
3297         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3298
3299         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3300                 b43_nphy_tx_iq_workaround(dev);
3301
3302         if (dev->phy.rev >= 4)
3303                 nphy->hang_avoid = avoid;
3304
3305         b43_nphy_stay_in_carrier_search(dev, false);
3306
3307         return error;
3308 }
3309
3310 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3311 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3312 {
3313         struct b43_phy_n *nphy = dev->phy.n;
3314         u8 i;
3315         u16 buffer[7];
3316         bool equal = true;
3317
3318         if (!nphy->txiqlocal_coeffsvalid ||
3319             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3320             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3321                 return;
3322
3323         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3324         for (i = 0; i < 4; i++) {
3325                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3326                         equal = false;
3327                         break;
3328                 }
3329         }
3330
3331         if (!equal) {
3332                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3333                                         nphy->txiqlocal_bestc);
3334                 for (i = 0; i < 4; i++)
3335                         buffer[i] = 0;
3336                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3337                                         buffer);
3338                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3339                                         &nphy->txiqlocal_bestc[5]);
3340                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3341                                         &nphy->txiqlocal_bestc[5]);
3342         }
3343 }
3344
3345 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3346 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3347                         struct nphy_txgains target, u8 type, bool debug)
3348 {
3349         struct b43_phy_n *nphy = dev->phy.n;
3350         int i, j, index;
3351         u8 rfctl[2];
3352         u8 afectl_core;
3353         u16 tmp[6];
3354         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3355         u32 real, imag;
3356         enum ieee80211_band band;
3357
3358         u8 use;
3359         u16 cur_hpf;
3360         u16 lna[3] = { 3, 3, 1 };
3361         u16 hpf1[3] = { 7, 2, 0 };
3362         u16 hpf2[3] = { 2, 0, 0 };
3363         u32 power[3] = { };
3364         u16 gain_save[2];
3365         u16 cal_gain[2];
3366         struct nphy_iqcal_params cal_params[2];
3367         struct nphy_iq_est est;
3368         int ret = 0;
3369         bool playtone = true;
3370         int desired = 13;
3371
3372         b43_nphy_stay_in_carrier_search(dev, 1);
3373
3374         if (dev->phy.rev < 2)
3375                 b43_nphy_reapply_tx_cal_coeffs(dev);
3376         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3377         for (i = 0; i < 2; i++) {
3378                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3379                 cal_gain[i] = cal_params[i].cal_gain;
3380         }
3381         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3382
3383         for (i = 0; i < 2; i++) {
3384                 if (i == 0) {
3385                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3386                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3387                         afectl_core = B43_NPHY_AFECTL_C1;
3388                 } else {
3389                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3390                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3391                         afectl_core = B43_NPHY_AFECTL_C2;
3392                 }
3393
3394                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3395                 tmp[2] = b43_phy_read(dev, afectl_core);
3396                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3397                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3398                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3399
3400                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3401                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3402                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3403                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3404                                 (1 - i));
3405                 b43_phy_set(dev, afectl_core, 0x0006);
3406                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3407
3408                 band = b43_current_band(dev->wl);
3409
3410                 if (nphy->rxcalparams & 0xFF000000) {
3411                         if (band == IEEE80211_BAND_5GHZ)
3412                                 b43_phy_write(dev, rfctl[0], 0x140);
3413                         else
3414                                 b43_phy_write(dev, rfctl[0], 0x110);
3415                 } else {
3416                         if (band == IEEE80211_BAND_5GHZ)
3417                                 b43_phy_write(dev, rfctl[0], 0x180);
3418                         else
3419                                 b43_phy_write(dev, rfctl[0], 0x120);
3420                 }
3421
3422                 if (band == IEEE80211_BAND_5GHZ)
3423                         b43_phy_write(dev, rfctl[1], 0x148);
3424                 else
3425                         b43_phy_write(dev, rfctl[1], 0x114);
3426
3427                 if (nphy->rxcalparams & 0x10000) {
3428                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3429                                         (i + 1));
3430                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3431                                         (2 - i));
3432                 }
3433
3434                 for (j = 0; j < 4; j++) {
3435                         if (j < 3) {
3436                                 cur_lna = lna[j];
3437                                 cur_hpf1 = hpf1[j];
3438                                 cur_hpf2 = hpf2[j];
3439                         } else {
3440                                 if (power[1] > 10000) {
3441                                         use = 1;
3442                                         cur_hpf = cur_hpf1;
3443                                         index = 2;
3444                                 } else {
3445                                         if (power[0] > 10000) {
3446                                                 use = 1;
3447                                                 cur_hpf = cur_hpf1;
3448                                                 index = 1;
3449                                         } else {
3450                                                 index = 0;
3451                                                 use = 2;
3452                                                 cur_hpf = cur_hpf2;
3453                                         }
3454                                 }
3455                                 cur_lna = lna[index];
3456                                 cur_hpf1 = hpf1[index];
3457                                 cur_hpf2 = hpf2[index];
3458                                 cur_hpf += desired - hweight32(power[index]);
3459                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3460                                 if (use == 1)
3461                                         cur_hpf1 = cur_hpf;
3462                                 else
3463                                         cur_hpf2 = cur_hpf;
3464                         }
3465
3466                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3467                                         (cur_lna << 2));
3468                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3469                                                                         false);
3470                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3471                         b43_nphy_stop_playback(dev);
3472
3473                         if (playtone) {
3474                                 ret = b43_nphy_tx_tone(dev, 4000,
3475                                                 (nphy->rxcalparams & 0xFFFF),
3476                                                 false, false);
3477                                 playtone = false;
3478                         } else {
3479                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3480                                                         false, false);
3481                         }
3482
3483                         if (ret == 0) {
3484                                 if (j < 3) {
3485                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3486                                                                         false);
3487                                         if (i == 0) {
3488                                                 real = est.i0_pwr;
3489                                                 imag = est.q0_pwr;
3490                                         } else {
3491                                                 real = est.i1_pwr;
3492                                                 imag = est.q1_pwr;
3493                                         }
3494                                         power[i] = ((real + imag) / 1024) + 1;
3495                                 } else {
3496                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3497                                 }
3498                                 b43_nphy_stop_playback(dev);
3499                         }
3500
3501                         if (ret != 0)
3502                                 break;
3503                 }
3504
3505                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3506                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3507                 b43_phy_write(dev, rfctl[1], tmp[5]);
3508                 b43_phy_write(dev, rfctl[0], tmp[4]);
3509                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3510                 b43_phy_write(dev, afectl_core, tmp[2]);
3511                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3512
3513                 if (ret != 0)
3514                         break;
3515         }
3516
3517         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3518         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3519         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3520
3521         b43_nphy_stay_in_carrier_search(dev, 0);
3522
3523         return ret;
3524 }
3525
3526 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3527                         struct nphy_txgains target, u8 type, bool debug)
3528 {
3529         return -1;
3530 }
3531
3532 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3533 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3534                         struct nphy_txgains target, u8 type, bool debug)
3535 {
3536         if (dev->phy.rev >= 3)
3537                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3538         else
3539                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3540 }
3541
3542 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3543 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3544 {
3545         struct b43_phy *phy = &dev->phy;
3546         struct b43_phy_n *nphy = phy->n;
3547         /* u16 buf[16]; it's rev3+ */
3548
3549         nphy->phyrxchain = mask;
3550
3551         if (0 /* FIXME clk */)
3552                 return;
3553
3554         b43_mac_suspend(dev);
3555
3556         if (nphy->hang_avoid)
3557                 b43_nphy_stay_in_carrier_search(dev, true);
3558
3559         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3560                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3561
3562         if ((mask & 0x3) != 0x3) {
3563                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3564                 if (dev->phy.rev >= 3) {
3565                         /* TODO */
3566                 }
3567         } else {
3568                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3569                 if (dev->phy.rev >= 3) {
3570                         /* TODO */
3571                 }
3572         }
3573
3574         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3575
3576         if (nphy->hang_avoid)
3577                 b43_nphy_stay_in_carrier_search(dev, false);
3578
3579         b43_mac_enable(dev);
3580 }
3581
3582 /*
3583  * Init N-PHY
3584  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3585  */
3586 int b43_phy_initn(struct b43_wldev *dev)
3587 {
3588         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3589         struct b43_phy *phy = &dev->phy;
3590         struct b43_phy_n *nphy = phy->n;
3591         u8 tx_pwr_state;
3592         struct nphy_txgains target;
3593         u16 tmp;
3594         enum ieee80211_band tmp2;
3595         bool do_rssi_cal;
3596
3597         u16 clip[2];
3598         bool do_cal = false;
3599
3600         if ((dev->phy.rev >= 3) &&
3601            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3602            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3603                 chipco_set32(&dev->sdev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3604         }
3605         nphy->deaf_count = 0;
3606         b43_nphy_tables_init(dev);
3607         nphy->crsminpwr_adjusted = false;
3608         nphy->noisevars_adjusted = false;
3609
3610         /* Clear all overrides */
3611         if (dev->phy.rev >= 3) {
3612                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3613                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3614                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3615                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3616         } else {
3617                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3618         }
3619         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3620         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3621         if (dev->phy.rev < 6) {
3622                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3623                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3624         }
3625         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3626                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3627                        B43_NPHY_RFSEQMODE_TROVER));
3628         if (dev->phy.rev >= 3)
3629                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3630         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3631
3632         if (dev->phy.rev <= 2) {
3633                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3634                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3635                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3636                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3637         }
3638         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3639         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3640
3641         if (sprom->boardflags2_lo & 0x100 ||
3642             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3643              dev->dev->board_type == 0x8B))
3644                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3645         else
3646                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3647         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3648         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3649         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3650
3651         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3652         b43_nphy_update_txrx_chain(dev);
3653
3654         if (phy->rev < 2) {
3655                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3656                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3657         }
3658
3659         tmp2 = b43_current_band(dev->wl);
3660         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3661             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3662                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3663                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3664                                 nphy->papd_epsilon_offset[0] << 7);
3665                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3666                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3667                                 nphy->papd_epsilon_offset[1] << 7);
3668                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3669         } else if (phy->rev >= 5) {
3670                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3671         }
3672
3673         b43_nphy_workarounds(dev);
3674
3675         /* Reset CCA, in init code it differs a little from standard way */
3676         b43_nphy_bmac_clock_fgc(dev, 1);
3677         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3678         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3679         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3680         b43_nphy_bmac_clock_fgc(dev, 0);
3681
3682         b43_mac_phy_clock_set(dev, true);
3683
3684         b43_nphy_pa_override(dev, false);
3685         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3686         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3687         b43_nphy_pa_override(dev, true);
3688
3689         b43_nphy_classifier(dev, 0, 0);
3690         b43_nphy_read_clip_detection(dev, clip);
3691         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3692                 b43_nphy_bphy_init(dev);
3693
3694         tx_pwr_state = nphy->txpwrctrl;
3695         b43_nphy_tx_power_ctrl(dev, false);
3696         b43_nphy_tx_power_fix(dev);
3697         /* TODO N PHY TX Power Control Idle TSSI */
3698         /* TODO N PHY TX Power Control Setup */
3699
3700         if (phy->rev >= 3) {
3701                 /* TODO */
3702         } else {
3703                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3704                                         b43_ntab_tx_gain_rev0_1_2);
3705                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3706                                         b43_ntab_tx_gain_rev0_1_2);
3707         }
3708
3709         if (nphy->phyrxchain != 3)
3710                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3711         if (nphy->mphase_cal_phase_id > 0)
3712                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3713
3714         do_rssi_cal = false;
3715         if (phy->rev >= 3) {
3716                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3717                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3718                 else
3719                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3720
3721                 if (do_rssi_cal)
3722                         b43_nphy_rssi_cal(dev);
3723                 else
3724                         b43_nphy_restore_rssi_cal(dev);
3725         } else {
3726                 b43_nphy_rssi_cal(dev);
3727         }
3728
3729         if (!((nphy->measure_hold & 0x6) != 0)) {
3730                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3731                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3732                 else
3733                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3734
3735                 if (nphy->mute)
3736                         do_cal = false;
3737
3738                 if (do_cal) {
3739                         target = b43_nphy_get_tx_gains(dev);
3740
3741                         if (nphy->antsel_type == 2)
3742                                 b43_nphy_superswitch_init(dev, true);
3743                         if (nphy->perical != 2) {
3744                                 b43_nphy_rssi_cal(dev);
3745                                 if (phy->rev >= 3) {
3746                                         nphy->cal_orig_pwr_idx[0] =
3747                                             nphy->txpwrindex[0].index_internal;
3748                                         nphy->cal_orig_pwr_idx[1] =
3749                                             nphy->txpwrindex[1].index_internal;
3750                                         /* TODO N PHY Pre Calibrate TX Gain */
3751                                         target = b43_nphy_get_tx_gains(dev);
3752                                 }
3753                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3754                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3755                                                 b43_nphy_save_cal(dev);
3756                         } else if (nphy->mphase_cal_phase_id == 0)
3757                                 ;/* N PHY Periodic Calibration with arg 3 */
3758                 } else {
3759                         b43_nphy_restore_cal(dev);
3760                 }
3761         }
3762
3763         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3764         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3765         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3766         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3767         if (phy->rev >= 3 && phy->rev <= 6)
3768                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3769         b43_nphy_tx_lp_fbw(dev);
3770         if (phy->rev >= 3)
3771                 b43_nphy_spur_workaround(dev);
3772
3773         return 0;
3774 }
3775
3776 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3777 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3778                                 const struct b43_phy_n_sfo_cfg *e,
3779                                 struct ieee80211_channel *new_channel)
3780 {
3781         struct b43_phy *phy = &dev->phy;
3782         struct b43_phy_n *nphy = dev->phy.n;
3783
3784         u16 old_band_5ghz;
3785         u32 tmp32;
3786
3787         old_band_5ghz =
3788                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3789         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3790                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3791                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3792                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3793                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3794                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3795         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3796                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3797                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3798                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3799                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3800                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3801         }
3802
3803         b43_chantab_phy_upload(dev, e);
3804
3805         if (new_channel->hw_value == 14) {
3806                 b43_nphy_classifier(dev, 2, 0);
3807                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3808         } else {
3809                 b43_nphy_classifier(dev, 2, 2);
3810                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3811                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3812         }
3813
3814         if (!nphy->txpwrctrl)
3815                 b43_nphy_tx_power_fix(dev);
3816
3817         if (dev->phy.rev < 3)
3818                 b43_nphy_adjust_lna_gain_table(dev);
3819
3820         b43_nphy_tx_lp_fbw(dev);
3821
3822         if (dev->phy.rev >= 3 && 0) {
3823                 /* TODO */
3824         }
3825
3826         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3827
3828         if (phy->rev >= 3)
3829                 b43_nphy_spur_workaround(dev);
3830 }
3831
3832 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3833 static int b43_nphy_set_channel(struct b43_wldev *dev,
3834                                 struct ieee80211_channel *channel,
3835                                 enum nl80211_channel_type channel_type)
3836 {
3837         struct b43_phy *phy = &dev->phy;
3838
3839         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3840         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3841
3842         u8 tmp;
3843
3844         if (dev->phy.rev >= 3) {
3845                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3846                                                         channel->center_freq);
3847                 if (!tabent_r3)
3848                         return -ESRCH;
3849         } else {
3850                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3851                                                         channel->hw_value);
3852                 if (!tabent_r2)
3853                         return -ESRCH;
3854         }
3855
3856         /* Channel is set later in common code, but we need to set it on our
3857            own to let this function's subcalls work properly. */
3858         phy->channel = channel->hw_value;
3859         phy->channel_freq = channel->center_freq;
3860
3861         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3862                 b43_channel_type_is_40mhz(channel_type))
3863                 ; /* TODO: BMAC BW Set (channel_type) */
3864
3865         if (channel_type == NL80211_CHAN_HT40PLUS)
3866                 b43_phy_set(dev, B43_NPHY_RXCTL,
3867                                 B43_NPHY_RXCTL_BSELU20);
3868         else if (channel_type == NL80211_CHAN_HT40MINUS)
3869                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3870                                 ~B43_NPHY_RXCTL_BSELU20);
3871
3872         if (dev->phy.rev >= 3) {
3873                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3874                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3875                 b43_radio_2056_setup(dev, tabent_r3);
3876                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3877         } else {
3878                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3879                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3880                 b43_radio_2055_setup(dev, tabent_r2);
3881                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3882         }
3883
3884         return 0;
3885 }
3886
3887 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3888 {
3889         struct b43_phy_n *nphy;
3890
3891         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3892         if (!nphy)
3893                 return -ENOMEM;
3894         dev->phy.n = nphy;
3895
3896         return 0;
3897 }
3898
3899 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3900 {
3901         struct b43_phy *phy = &dev->phy;
3902         struct b43_phy_n *nphy = phy->n;
3903
3904         memset(nphy, 0, sizeof(*nphy));
3905
3906         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3907         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3908         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3909         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3910         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3911 }
3912
3913 static void b43_nphy_op_free(struct b43_wldev *dev)
3914 {
3915         struct b43_phy *phy = &dev->phy;
3916         struct b43_phy_n *nphy = phy->n;
3917
3918         kfree(nphy);
3919         phy->n = NULL;
3920 }
3921
3922 static int b43_nphy_op_init(struct b43_wldev *dev)
3923 {
3924         return b43_phy_initn(dev);
3925 }
3926
3927 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3928 {
3929 #if B43_DEBUG
3930         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3931                 /* OFDM registers are onnly available on A/G-PHYs */
3932                 b43err(dev->wl, "Invalid OFDM PHY access at "
3933                        "0x%04X on N-PHY\n", offset);
3934                 dump_stack();
3935         }
3936         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3937                 /* Ext-G registers are only available on G-PHYs */
3938                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3939                        "0x%04X on N-PHY\n", offset);
3940                 dump_stack();
3941         }
3942 #endif /* B43_DEBUG */
3943 }
3944
3945 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3946 {
3947         check_phyreg(dev, reg);
3948         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3949         return b43_read16(dev, B43_MMIO_PHY_DATA);
3950 }
3951
3952 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3953 {
3954         check_phyreg(dev, reg);
3955         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3956         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3957 }
3958
3959 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3960                                  u16 set)
3961 {
3962         check_phyreg(dev, reg);
3963         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3964         b43_write16(dev, B43_MMIO_PHY_DATA,
3965                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3966 }
3967
3968 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3969 {
3970         /* Register 1 is a 32-bit register. */
3971         B43_WARN_ON(reg == 1);
3972         /* N-PHY needs 0x100 for read access */
3973         reg |= 0x100;
3974
3975         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3976         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3977 }
3978
3979 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3980 {
3981         /* Register 1 is a 32-bit register. */
3982         B43_WARN_ON(reg == 1);
3983
3984         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3985         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3986 }
3987
3988 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3989 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3990                                         bool blocked)
3991 {
3992         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3993                 b43err(dev->wl, "MAC not suspended\n");
3994
3995         if (blocked) {
3996                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3997                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3998                 if (dev->phy.rev >= 3) {
3999                         b43_radio_mask(dev, 0x09, ~0x2);
4000
4001                         b43_radio_write(dev, 0x204D, 0);
4002                         b43_radio_write(dev, 0x2053, 0);
4003                         b43_radio_write(dev, 0x2058, 0);
4004                         b43_radio_write(dev, 0x205E, 0);
4005                         b43_radio_mask(dev, 0x2062, ~0xF0);
4006                         b43_radio_write(dev, 0x2064, 0);
4007
4008                         b43_radio_write(dev, 0x304D, 0);
4009                         b43_radio_write(dev, 0x3053, 0);
4010                         b43_radio_write(dev, 0x3058, 0);
4011                         b43_radio_write(dev, 0x305E, 0);
4012                         b43_radio_mask(dev, 0x3062, ~0xF0);
4013                         b43_radio_write(dev, 0x3064, 0);
4014                 }
4015         } else {
4016                 if (dev->phy.rev >= 3) {
4017                         b43_radio_init2056(dev);
4018                         b43_switch_channel(dev, dev->phy.channel);
4019                 } else {
4020                         b43_radio_init2055(dev);
4021                 }
4022         }
4023 }
4024
4025 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4026 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4027 {
4028         u16 override = on ? 0x0 : 0x7FFF;
4029         u16 core = on ? 0xD : 0x00FD;
4030
4031         if (dev->phy.rev >= 3) {
4032                 if (on) {
4033                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4034                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4035                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4036                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4037                 } else {
4038                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4039                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4040                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4041                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4042                 }
4043         } else {
4044                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4045         }
4046 }
4047
4048 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4049                                       unsigned int new_channel)
4050 {
4051         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4052         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4053
4054         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4055                 if ((new_channel < 1) || (new_channel > 14))
4056                         return -EINVAL;
4057         } else {
4058                 if (new_channel > 200)
4059                         return -EINVAL;
4060         }
4061
4062         return b43_nphy_set_channel(dev, channel, channel_type);
4063 }
4064
4065 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4066 {
4067         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4068                 return 1;
4069         return 36;
4070 }
4071
4072 const struct b43_phy_operations b43_phyops_n = {
4073         .allocate               = b43_nphy_op_allocate,
4074         .free                   = b43_nphy_op_free,
4075         .prepare_structs        = b43_nphy_op_prepare_structs,
4076         .init                   = b43_nphy_op_init,
4077         .phy_read               = b43_nphy_op_read,
4078         .phy_write              = b43_nphy_op_write,
4079         .phy_maskset            = b43_nphy_op_maskset,
4080         .radio_read             = b43_nphy_op_radio_read,
4081         .radio_write            = b43_nphy_op_radio_write,
4082         .software_rfkill        = b43_nphy_op_software_rfkill,
4083         .switch_analog          = b43_nphy_op_switch_analog,
4084         .switch_channel         = b43_nphy_op_switch_channel,
4085         .get_default_chan       = b43_nphy_op_get_default_chan,
4086         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4087         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4088 };