drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "radio_2055.h"
  33 #include "radio_2056.h"
  34 #include "main.h"
  35
  36 struct nphy_txgains {
  37         u16 txgm[2];
  38         u16 pga[2];
  39         u16 pad[2];
  40         u16 ipa[2];
  41 };
  42
  43 struct nphy_iqcal_params {
  44         u16 txgm;
  45         u16 pga;
  46         u16 pad;
  47         u16 ipa;
  48         u16 cal_gain;
  49         u16 ncorr[5];
  50 };
  51
  52 struct nphy_iq_est {
  53         s32 iq0_prod;
  54         u32 i0_pwr;
  55         u32 q0_pwr;
  56         s32 iq1_prod;
  57         u32 i1_pwr;
  58         u32 q1_pwr;
  59 };
  60
  61 enum b43_nphy_rf_sequence {
  62         B43_RFSEQ_RX2TX,
  63         B43_RFSEQ_TX2RX,
  64         B43_RFSEQ_RESET2RX,
  65         B43_RFSEQ_UPDATE_GAINH,
  66         B43_RFSEQ_UPDATE_GAINL,
  67         B43_RFSEQ_UPDATE_GAINU,
  68 };
  69
  70 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  71                                         u8 *events, u8 *delays, u8 length);
  72 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  73                                        enum b43_nphy_rf_sequence seq);
  74 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  75                                                 u16 value, u8 core, bool off);
  76 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  77                                                 u16 value, u8 core);
  78
  79 static inline bool b43_channel_type_is_40mhz(
  80                                         enum nl80211_channel_type channel_type)
  81 {
  82         return (channel_type == NL80211_CHAN_HT40MINUS ||
  83                 channel_type == NL80211_CHAN_HT40PLUS);
  84 }
  85
  86 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  87 {//TODO
  88 }
  89
  90 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  91 {//TODO
  92 }
  93
  94 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  95                                                         bool ignore_tssi)
  96 {//TODO
  97         return B43_TXPWR_RES_DONE;
  98 }
  99
 100 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 101                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 102 {
 103         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 104         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 105         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 106         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 107         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 108
 109         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 110         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 111         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 112         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 113         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 114
 115         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 116         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 117         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 118         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 119         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 120
 121         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 122         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 123         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 124         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 125         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 126
 127         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 128         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 129         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 130         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 131         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 132
 133         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 134         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 135 }
 136
 137 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 138                                    const struct b43_phy_n_sfo_cfg *e)
 139 {
 140         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 141         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 142         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 143         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 144         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 145         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 146 }
 147
 148 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 149 {
 150         //TODO
 151 }
 152
 153
 154 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 155 static void b43_radio_2055_setup(struct b43_wldev *dev,
 156                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 157 {
 158         B43_WARN_ON(dev->phy.rev >= 3);
 159
 160         b43_chantab_radio_upload(dev, e);
 161         udelay(50);
 162         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 163         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 164         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 165         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 166         udelay(300);
 167 }
 168
 169 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 170 {
 171         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 172                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 173         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 174                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 175                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 176         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 177                     B43_NPHY_RFCTL_CMD_PORFORCE);
 178 }
 179
 180 static void b43_radio_init2055_post(struct b43_wldev *dev)
 181 {
 182         struct b43_phy_n *nphy = dev->phy.n;
 183         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 184         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 185         int i;
 186         u16 val;
 187         bool workaround = false;
 188
 189         if (sprom->revision < 4)
 190                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
 191                                 binfo->type != 0x46D ||
 192                                 binfo->rev < 0x41);
 193         else
 194                 workaround =
 195                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 196
 197         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 198         if (workaround) {
 199                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 200                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 201         }
 202         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 203         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 204         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 205         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 206         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 207         msleep(1);
 208         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 209         for (i = 0; i < 200; i++) {
 210                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 211                 if (val & 0x80) {
 212                         i = 0;
 213                         break;
 214                 }
 215                 udelay(10);
 216         }
 217         if (i)
 218                 b43err(dev->wl, "radio post init timeout\n");
 219         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 220         b43_switch_channel(dev, dev->phy.channel);
 221         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 222         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 223         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 224         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 225         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 226         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 227         if (!nphy->gain_boost) {
 228                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 229                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 230         } else {
 231                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 232                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 233         }
 234         udelay(2);
 235 }
 236
 237 /*
 238  * Initialize a Broadcom 2055 N-radio
 239  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 240  */
 241 static void b43_radio_init2055(struct b43_wldev *dev)
 242 {
 243         b43_radio_init2055_pre(dev);
 244         if (b43_status(dev) < B43_STAT_INITIALIZED)
 245                 b2055_upload_inittab(dev, 0, 1);
 246         else
 247                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 248         b43_radio_init2055_post(dev);
 249 }
 250
 251 /*
 252  * Initialize a Broadcom 2056 N-radio
 253  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 254  */
 255 static void b43_radio_init2056(struct b43_wldev *dev)
 256 {
 257         /* TODO */
 258 }
 259
 260
 261 /*
 262  * Upload the N-PHY tables.
 263  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 264  */
 265 static void b43_nphy_tables_init(struct b43_wldev *dev)
 266 {
 267         if (dev->phy.rev < 3)
 268                 b43_nphy_rev0_1_2_tables_init(dev);
 269         else
 270                 b43_nphy_rev3plus_tables_init(dev);
 271 }
 272
 273 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 274 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 275 {
 276         struct b43_phy_n *nphy = dev->phy.n;
 277         enum ieee80211_band band;
 278         u16 tmp;
 279
 280         if (!enable) {
 281                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 282                                                        B43_NPHY_RFCTL_INTC1);
 283                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 284                                                        B43_NPHY_RFCTL_INTC2);
 285                 band = b43_current_band(dev->wl);
 286                 if (dev->phy.rev >= 3) {
 287                         if (band == IEEE80211_BAND_5GHZ)
 288                                 tmp = 0x600;
 289                         else
 290                                 tmp = 0x480;
 291                 } else {
 292                         if (band == IEEE80211_BAND_5GHZ)
 293                                 tmp = 0x180;
 294                         else
 295                                 tmp = 0x120;
 296                 }
 297                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 298                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 299         } else {
 300                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 301                                 nphy->rfctrl_intc1_save);
 302                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 303                                 nphy->rfctrl_intc2_save);
 304         }
 305 }
 306
 307 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 308 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 309 {
 310         struct b43_phy_n *nphy = dev->phy.n;
 311         u16 tmp;
 312         enum ieee80211_band band = b43_current_band(dev->wl);
 313         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 314                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 315
 316         if (dev->phy.rev >= 3) {
 317                 if (ipa) {
 318                         tmp = 4;
 319                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 320                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 321                 }
 322
 323                 tmp = 1;
 324                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 325                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 326         }
 327 }
 328
 329 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 330 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 331 {
 332         u32 tmslow;
 333
 334         if (dev->phy.type != B43_PHYTYPE_N)
 335                 return;
 336
 337         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 338         if (force)
 339                 tmslow |= SSB_TMSLOW_FGC;
 340         else
 341                 tmslow &= ~SSB_TMSLOW_FGC;
 342         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 343 }
 344
 345 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 346 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 347 {
 348         u16 bbcfg;
 349
 350         b43_nphy_bmac_clock_fgc(dev, 1);
 351         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 352         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 353         udelay(1);
 354         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 355         b43_nphy_bmac_clock_fgc(dev, 0);
 356         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 357 }
 358
 359 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 360 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 361 {
 362         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 363
 364         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 365         if (preamble == 1)
 366                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 367         else
 368                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 369
 370         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 371 }
 372
 373 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 374 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 375 {
 376         struct b43_phy_n *nphy = dev->phy.n;
 377
 378         bool override = false;
 379         u16 chain = 0x33;
 380
 381         if (nphy->txrx_chain == 0) {
 382                 chain = 0x11;
 383                 override = true;
 384         } else if (nphy->txrx_chain == 1) {
 385                 chain = 0x22;
 386                 override = true;
 387         }
 388
 389         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 390                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 391                         chain);
 392
 393         if (override)
 394                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 395                                 B43_NPHY_RFSEQMODE_CAOVER);
 396         else
 397                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 398                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 399 }
 400
 401 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 402 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 403                                 u16 samps, u8 time, bool wait)
 404 {
 405         int i;
 406         u16 tmp;
 407
 408         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 409         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 410         if (wait)
 411                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 412         else
 413                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 414
 415         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 416
 417         for (i = 1000; i; i--) {
 418                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 419                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 420                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 421                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 422                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 423                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 424                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 425                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 426
 427                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 428                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 429                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 430                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 431                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 432                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 433                         return;
 434                 }
 435                 udelay(10);
 436         }
 437         memset(est, 0, sizeof(*est));
 438 }
 439
 440 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 441 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 442                                         struct b43_phy_n_iq_comp *pcomp)
 443 {
 444         if (write) {
 445                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 446                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 447                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 448                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 449         } else {
 450                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 451                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 452                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 453                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 454         }
 455 }
 456
 457 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 458 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 459 {
 460         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 461
 462         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 463         if (core == 0) {
 464                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 465                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 466         } else {
 467                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 468                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 469         }
 470         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 471         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 472         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 473         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 474         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 475         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 476         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 477         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 478 }
 479
 480 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 481 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 482 {
 483         u8 rxval, txval;
 484         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 485
 486         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 487         if (core == 0) {
 488                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 489                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 490         } else {
 491                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 492                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 493         }
 494         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 495         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 496         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 497         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 498         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 499         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 500         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 501         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 502
 503         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 504         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 505
 506         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 507                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 508                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 509         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 510                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 511         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 512                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 513         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 514                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 515
 516         if (core == 0) {
 517                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 518                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 519         } else {
 520                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 521                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 522         }
 523
 524         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 525         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 526         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 527
 528         if (core == 0) {
 529                 rxval = 1;
 530                 txval = 8;
 531         } else {
 532                 rxval = 4;
 533                 txval = 2;
 534         }
 535         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 536         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 537 }
 538
 539 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 540 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 541 {
 542         int i;
 543         s32 iq;
 544         u32 ii;
 545         u32 qq;
 546         int iq_nbits, qq_nbits;
 547         int arsh, brsh;
 548         u16 tmp, a, b;
 549
 550         struct nphy_iq_est est;
 551         struct b43_phy_n_iq_comp old;
 552         struct b43_phy_n_iq_comp new = { };
 553         bool error = false;
 554
 555         if (mask == 0)
 556                 return;
 557
 558         b43_nphy_rx_iq_coeffs(dev, false, &old);
 559         b43_nphy_rx_iq_coeffs(dev, true, &new);
 560         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 561         new = old;
 562
 563         for (i = 0; i < 2; i++) {
 564                 if (i == 0 && (mask & 1)) {
 565                         iq = est.iq0_prod;
 566                         ii = est.i0_pwr;
 567                         qq = est.q0_pwr;
 568                 } else if (i == 1 && (mask & 2)) {
 569                         iq = est.iq1_prod;
 570                         ii = est.i1_pwr;
 571                         qq = est.q1_pwr;
 572                 } else {
 573                         B43_WARN_ON(1);
 574                         continue;
 575                 }
 576
 577                 if (ii + qq < 2) {
 578                         error = true;
 579                         break;
 580                 }
 581
 582                 iq_nbits = fls(abs(iq));
 583                 qq_nbits = fls(qq);
 584
 585                 arsh = iq_nbits - 20;
 586                 if (arsh >= 0) {
 587                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 588                         tmp = ii >> arsh;
 589                 } else {
 590                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 591                         tmp = ii << -arsh;
 592                 }
 593                 if (tmp == 0) {
 594                         error = true;
 595                         break;
 596                 }
 597                 a /= tmp;
 598
 599                 brsh = qq_nbits - 11;
 600                 if (brsh >= 0) {
 601                         b = (qq << (31 - qq_nbits));
 602                         tmp = ii >> brsh;
 603                 } else {
 604                         b = (qq << (31 - qq_nbits));
 605                         tmp = ii << -brsh;
 606                 }
 607                 if (tmp == 0) {
 608                         error = true;
 609                         break;
 610                 }
 611                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 612
 613                 if (i == 0 && (mask & 0x1)) {
 614                         if (dev->phy.rev >= 3) {
 615                                 new.a0 = a & 0x3FF;
 616                                 new.b0 = b & 0x3FF;
 617                         } else {
 618                                 new.a0 = b & 0x3FF;
 619                                 new.b0 = a & 0x3FF;
 620                         }
 621                 } else if (i == 1 && (mask & 0x2)) {
 622                         if (dev->phy.rev >= 3) {
 623                                 new.a1 = a & 0x3FF;
 624                                 new.b1 = b & 0x3FF;
 625                         } else {
 626                                 new.a1 = b & 0x3FF;
 627                                 new.b1 = a & 0x3FF;
 628                         }
 629                 }
 630         }
 631
 632         if (error)
 633                 new = old;
 634
 635         b43_nphy_rx_iq_coeffs(dev, true, &new);
 636 }
 637
 638 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 639 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 640 {
 641         u16 array[4];
 642         int i;
 643
 644         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 645         for (i = 0; i < 4; i++)
 646                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 647
 648         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 649         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 650         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 651         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 652 }
 653
 654 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 655 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 656 {
 657         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 658         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 659 }
 660
 661 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 662 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 663 {
 664         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 665         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 666 }
 667
 668 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 669 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 670 {
 671         if (dev->phy.rev >= 3) {
 672                 if (!init)
 673                         return;
 674                 if (0 /* FIXME */) {
 675                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 676                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 677                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 678                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 679                 }
 680         } else {
 681                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 682                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 683
 684                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 685                                         0xFC00);
 686                 b43_write32(dev, B43_MMIO_MACCTL,
 687                         b43_read32(dev, B43_MMIO_MACCTL) &
 688                         ~B43_MACCTL_GPOUTSMSK);
 689                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 690                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 691                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 692                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 693
 694                 if (init) {
 695                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 696                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 697                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 698                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 699                 }
 700         }
 701 }
 702
 703 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 704 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 705 {
 706         u16 tmp;
 707
 708         if (dev->dev->id.revision == 16)
 709                 b43_mac_suspend(dev);
 710
 711         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 712         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 713                 B43_NPHY_CLASSCTL_WAITEDEN);
 714         tmp &= ~mask;
 715         tmp |= (val & mask);
 716         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 717
 718         if (dev->dev->id.revision == 16)
 719                 b43_mac_enable(dev);
 720
 721         return tmp;
 722 }
 723
 724 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 725 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 726 {
 727         struct b43_phy *phy = &dev->phy;
 728         struct b43_phy_n *nphy = phy->n;
 729
 730         if (enable) {
 731                 u16 clip[] = { 0xFFFF, 0xFFFF };
 732                 if (nphy->deaf_count++ == 0) {
 733                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 734                         b43_nphy_classifier(dev, 0x7, 0);
 735                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 736                         b43_nphy_write_clip_detection(dev, clip);
 737                 }
 738                 b43_nphy_reset_cca(dev);
 739         } else {
 740                 if (--nphy->deaf_count == 0) {
 741                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 742                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 743                 }
 744         }
 745 }
 746
 747 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 748 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 749 {
 750         struct b43_phy_n *nphy = dev->phy.n;
 751         u16 tmp;
 752
 753         if (nphy->hang_avoid)
 754                 b43_nphy_stay_in_carrier_search(dev, 1);
 755
 756         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 757         if (tmp & 0x1)
 758                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 759         else if (tmp & 0x2)
 760                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
 761
 762         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 763
 764         if (nphy->bb_mult_save & 0x80000000) {
 765                 tmp = nphy->bb_mult_save & 0xFFFF;
 766                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 767                 nphy->bb_mult_save = 0;
 768         }
 769
 770         if (nphy->hang_avoid)
 771                 b43_nphy_stay_in_carrier_search(dev, 0);
 772 }
 773
 774 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 775 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 776 {
 777         struct b43_phy_n *nphy = dev->phy.n;
 778
 779         u8 channel = dev->phy.channel;
 780         int tone[2] = { 57, 58 };
 781         u32 noise[2] = { 0x3FF, 0x3FF };
 782
 783         B43_WARN_ON(dev->phy.rev < 3);
 784
 785         if (nphy->hang_avoid)
 786                 b43_nphy_stay_in_carrier_search(dev, 1);
 787
 788         if (nphy->gband_spurwar_en) {
 789                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 790                 if (channel == 11 && dev->phy.is_40mhz)
 791                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 792                 else
 793                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 794                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 795         }
 796
 797         if (nphy->aband_spurwar_en) {
 798                 if (channel == 54) {
 799                         tone[0] = 0x20;
 800                         noise[0] = 0x25F;
 801                 } else if (channel == 38 || channel == 102 || channel == 118) {
 802                         if (0 /* FIXME */) {
 803                                 tone[0] = 0x20;
 804                                 noise[0] = 0x21F;
 805                         } else {
 806                                 tone[0] = 0;
 807                                 noise[0] = 0;
 808                         }
 809                 } else if (channel == 134) {
 810                         tone[0] = 0x20;
 811                         noise[0] = 0x21F;
 812                 } else if (channel == 151) {
 813                         tone[0] = 0x10;
 814                         noise[0] = 0x23F;
 815                 } else if (channel == 153 || channel == 161) {
 816                         tone[0] = 0x30;
 817                         noise[0] = 0x23F;
 818                 } else {
 819                         tone[0] = 0;
 820                         noise[0] = 0;
 821                 }
 822
 823                 if (!tone[0] && !noise[0])
 824                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 825                 else
 826                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 827         }
 828
 829         if (nphy->hang_avoid)
 830                 b43_nphy_stay_in_carrier_search(dev, 0);
 831 }
 832
 833 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 834 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 835 {
 836         struct b43_phy_n *nphy = dev->phy.n;
 837
 838         u8 i;
 839         s16 tmp;
 840         u16 data[4];
 841         s16 gain[2];
 842         u16 minmax[2];
 843         u16 lna_gain[4] = { -2, 10, 19, 25 };
 844
 845         if (nphy->hang_avoid)
 846                 b43_nphy_stay_in_carrier_search(dev, 1);
 847
 848         if (nphy->gain_boost) {
 849                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 850                         gain[0] = 6;
 851                         gain[1] = 6;
 852                 } else {
 853                         tmp = 40370 - 315 * dev->phy.channel;
 854                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 855                         tmp = 23242 - 224 * dev->phy.channel;
 856                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 857                 }
 858         } else {
 859                 gain[0] = 0;
 860                 gain[1] = 0;
 861         }
 862
 863         for (i = 0; i < 2; i++) {
 864                 if (nphy->elna_gain_config) {
 865                         data[0] = 19 + gain[i];
 866                         data[1] = 25 + gain[i];
 867                         data[2] = 25 + gain[i];
 868                         data[3] = 25 + gain[i];
 869                 } else {
 870                         data[0] = lna_gain[0] + gain[i];
 871                         data[1] = lna_gain[1] + gain[i];
 872                         data[2] = lna_gain[2] + gain[i];
 873                         data[3] = lna_gain[3] + gain[i];
 874                 }
 875                 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
 876
 877                 minmax[i] = 23 + gain[i];
 878         }
 879
 880         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 881                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 882         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 883                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 884
 885         if (nphy->hang_avoid)
 886                 b43_nphy_stay_in_carrier_search(dev, 0);
 887 }
 888
 889 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 890 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
 891 {
 892         struct b43_phy_n *nphy = dev->phy.n;
 893         u8 i, j;
 894         u8 code;
 895
 896         /* TODO: for PHY >= 3
 897         s8 *lna1_gain, *lna2_gain;
 898         u8 *gain_db, *gain_bits;
 899         u16 *rfseq_init;
 900         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 901         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 902         */
 903
 904         u8 rfseq_events[3] = { 6, 8, 7 };
 905         u8 rfseq_delays[3] = { 10, 30, 1 };
 906
 907         if (dev->phy.rev >= 3) {
 908                 /* TODO */
 909         } else {
 910                 /* Set Clip 2 detect */
 911                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 912                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 913                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 914                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 915
 916                 /* Set narrowband clip threshold */
 917                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 918                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 919
 920                 if (!dev->phy.is_40mhz) {
 921                         /* Set dwell lengths */
 922                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 923                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 924                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 925                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 926                 }
 927
 928                 /* Set wideband clip 2 threshold */
 929                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 930                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 931                                 21);
 932                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 933                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 934                                 21);
 935
 936                 if (!dev->phy.is_40mhz) {
 937                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 938                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 939                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 940                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 941                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 942                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 943                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 944                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 945                 }
 946
 947                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 948
 949                 if (nphy->gain_boost) {
 950                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 951                             dev->phy.is_40mhz)
 952                                 code = 4;
 953                         else
 954                                 code = 5;
 955                 } else {
 956                         code = dev->phy.is_40mhz ? 6 : 7;
 957                 }
 958
 959                 /* Set HPVGA2 index */
 960                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 961                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 962                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 963                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 964                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 965                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 966
 967                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 968                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 969                                         (code << 8 | 0x7C));
 970                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 971                                         (code << 8 | 0x7C));
 972
 973                 b43_nphy_adjust_lna_gain_table(dev);
 974
 975                 if (nphy->elna_gain_config) {
 976                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 977                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 978                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 979                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 980                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 981
 982                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 983                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 984                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 985                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 986                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 987
 988                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 989                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 990                                         (code << 8 | 0x74));
 991                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 992                                         (code << 8 | 0x74));
 993                 }
 994
 995                 if (dev->phy.rev == 2) {
 996                         for (i = 0; i < 4; i++) {
 997                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 998                                                 (0x0400 * i) + 0x0020);
 999                                 for (j = 0; j < 21; j++)
1000                                         b43_phy_write(dev,
1001                                                 B43_NPHY_TABLE_DATALO, 3 * j);
1002                         }
1003
1004                         b43_nphy_set_rf_sequence(dev, 5,
1005                                         rfseq_events, rfseq_delays, 3);
1006                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1007                                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1008                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1009
1010                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1011                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1012                                                 0xFF80, 4);
1013                 }
1014         }
1015 }
1016
1017 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1018 static void b43_nphy_workarounds(struct b43_wldev *dev)
1019 {
1020         struct ssb_bus *bus = dev->dev->bus;
1021         struct b43_phy *phy = &dev->phy;
1022         struct b43_phy_n *nphy = phy->n;
1023
1024         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1025         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1026
1027         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1028         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1029
1030         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1031                 b43_nphy_classifier(dev, 1, 0);
1032         else
1033                 b43_nphy_classifier(dev, 1, 1);
1034
1035         if (nphy->hang_avoid)
1036                 b43_nphy_stay_in_carrier_search(dev, 1);
1037
1038         b43_phy_set(dev, B43_NPHY_IQFLIP,
1039                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1040
1041         if (dev->phy.rev >= 3) {
1042                 /* TODO */
1043         } else {
1044                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1045                     nphy->band5g_pwrgain) {
1046                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1047                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1048                 } else {
1049                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1050                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1051                 }
1052
1053                 /* TODO: convert to b43_ntab_write? */
1054                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1055                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1056                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1057                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1058                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1059                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1060                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1061                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1062
1063                 if (dev->phy.rev < 2) {
1064                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1065                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1066                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1067                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1068                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1069                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1070                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1071                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1072                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1073                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1074                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1075                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1076                 }
1077
1078                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1079                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1080                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1081                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1082
1083                 if (bus->sprom.boardflags2_lo & 0x100 &&
1084                     bus->boardinfo.type == 0x8B) {
1085                         delays1[0] = 0x1;
1086                         delays1[5] = 0x14;
1087                 }
1088                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1089                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1090
1091                 b43_nphy_gain_ctrl_workarounds(dev);
1092
1093                 if (dev->phy.rev < 2) {
1094                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1095                                 b43_hf_write(dev, b43_hf_read(dev) |
1096                                                 B43_HF_MLADVW);
1097                 } else if (dev->phy.rev == 2) {
1098                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1099                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1100                 }
1101
1102                 if (dev->phy.rev < 2)
1103                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1104                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1105
1106                 /* Set phase track alpha and beta */
1107                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1108                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1109                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1110                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1111                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1112                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1113
1114                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1115                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1116                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1117                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1118                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1119
1120                 if (dev->phy.rev == 2)
1121                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1122                                         B43_NPHY_FINERX2_CGC_DECGC);
1123         }
1124
1125         if (nphy->hang_avoid)
1126                 b43_nphy_stay_in_carrier_search(dev, 0);
1127 }
1128
1129 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1130 static int b43_nphy_load_samples(struct b43_wldev *dev,
1131                                         struct b43_c32 *samples, u16 len) {
1132         struct b43_phy_n *nphy = dev->phy.n;
1133         u16 i;
1134         u32 *data;
1135
1136         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1137         if (!data) {
1138                 b43err(dev->wl, "allocation for samples loading failed\n");
1139                 return -ENOMEM;
1140         }
1141         if (nphy->hang_avoid)
1142                 b43_nphy_stay_in_carrier_search(dev, 1);
1143
1144         for (i = 0; i < len; i++) {
1145                 data[i] = (samples[i].i & 0x3FF << 10);
1146                 data[i] |= samples[i].q & 0x3FF;
1147         }
1148         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1149
1150         kfree(data);
1151         if (nphy->hang_avoid)
1152                 b43_nphy_stay_in_carrier_search(dev, 0);
1153         return 0;
1154 }
1155
1156 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1157 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1158                                         bool test)
1159 {
1160         int i;
1161         u16 bw, len, rot, angle;
1162         struct b43_c32 *samples;
1163
1164
1165         bw = (dev->phy.is_40mhz) ? 40 : 20;
1166         len = bw << 3;
1167
1168         if (test) {
1169                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1170                         bw = 82;
1171                 else
1172                         bw = 80;
1173
1174                 if (dev->phy.is_40mhz)
1175                         bw <<= 1;
1176
1177                 len = bw << 1;
1178         }
1179
1180         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1181         if (!samples) {
1182                 b43err(dev->wl, "allocation for samples generation failed\n");
1183                 return 0;
1184         }
1185         rot = (((freq * 36) / bw) << 16) / 100;
1186         angle = 0;
1187
1188         for (i = 0; i < len; i++) {
1189                 samples[i] = b43_cordic(angle);
1190                 angle += rot;
1191                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1192                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1193         }
1194
1195         i = b43_nphy_load_samples(dev, samples, len);
1196         kfree(samples);
1197         return (i < 0) ? 0 : len;
1198 }
1199
1200 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1201 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1202                                         u16 wait, bool iqmode, bool dac_test)
1203 {
1204         struct b43_phy_n *nphy = dev->phy.n;
1205         int i;
1206         u16 seq_mode;
1207         u32 tmp;
1208
1209         if (nphy->hang_avoid)
1210                 b43_nphy_stay_in_carrier_search(dev, true);
1211
1212         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1213                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1214                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1215         }
1216
1217         if (!dev->phy.is_40mhz)
1218                 tmp = 0x6464;
1219         else
1220                 tmp = 0x4747;
1221         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1222
1223         if (nphy->hang_avoid)
1224                 b43_nphy_stay_in_carrier_search(dev, false);
1225
1226         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1227
1228         if (loops != 0xFFFF)
1229                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1230         else
1231                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1232
1233         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1234
1235         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1236
1237         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1238         if (iqmode) {
1239                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1240                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1241         } else {
1242                 if (dac_test)
1243                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1244                 else
1245                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1246         }
1247         for (i = 0; i < 100; i++) {
1248                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1249                         i = 0;
1250                         break;
1251                 }
1252                 udelay(10);
1253         }
1254         if (i)
1255                 b43err(dev->wl, "run samples timeout\n");
1256
1257         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1258 }
1259
1260 /*
1261  * Transmits a known value for LO calibration
1262  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1263  */
1264 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1265                                 bool iqmode, bool dac_test)
1266 {
1267         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1268         if (samp == 0)
1269                 return -1;
1270         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1271         return 0;
1272 }
1273
1274 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1275 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1276 {
1277         struct b43_phy_n *nphy = dev->phy.n;
1278         int i, j;
1279         u32 tmp;
1280         u32 cur_real, cur_imag, real_part, imag_part;
1281
1282         u16 buffer[7];
1283
1284         if (nphy->hang_avoid)
1285                 b43_nphy_stay_in_carrier_search(dev, true);
1286
1287         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1288
1289         for (i = 0; i < 2; i++) {
1290                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1291                         (buffer[i * 2 + 1] & 0x3FF);
1292                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1293                                 (((i + 26) << 10) | 320));
1294                 for (j = 0; j < 128; j++) {
1295                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1296                                         ((tmp >> 16) & 0xFFFF));
1297                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1298                                         (tmp & 0xFFFF));
1299                 }
1300         }
1301
1302         for (i = 0; i < 2; i++) {
1303                 tmp = buffer[5 + i];
1304                 real_part = (tmp >> 8) & 0xFF;
1305                 imag_part = (tmp & 0xFF);
1306                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1307                                 (((i + 26) << 10) | 448));
1308
1309                 if (dev->phy.rev >= 3) {
1310                         cur_real = real_part;
1311                         cur_imag = imag_part;
1312                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1313                 }
1314
1315                 for (j = 0; j < 128; j++) {
1316                         if (dev->phy.rev < 3) {
1317                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1318                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1319                                 tmp = ((cur_real & 0xFF) << 8) |
1320                                         (cur_imag & 0xFF);
1321                         }
1322                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1323                                         ((tmp >> 16) & 0xFFFF));
1324                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1325                                         (tmp & 0xFFFF));
1326                 }
1327         }
1328
1329         if (dev->phy.rev >= 3) {
1330                 b43_shm_write16(dev, B43_SHM_SHARED,
1331                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1332                 b43_shm_write16(dev, B43_SHM_SHARED,
1333                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1334         }
1335
1336         if (nphy->hang_avoid)
1337                 b43_nphy_stay_in_carrier_search(dev, false);
1338 }
1339
1340 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1341 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1342                                         u8 *events, u8 *delays, u8 length)
1343 {
1344         struct b43_phy_n *nphy = dev->phy.n;
1345         u8 i;
1346         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1347         u16 offset1 = cmd << 4;
1348         u16 offset2 = offset1 + 0x80;
1349
1350         if (nphy->hang_avoid)
1351                 b43_nphy_stay_in_carrier_search(dev, true);
1352
1353         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1354         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1355
1356         for (i = length; i < 16; i++) {
1357                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1358                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1359         }
1360
1361         if (nphy->hang_avoid)
1362                 b43_nphy_stay_in_carrier_search(dev, false);
1363 }
1364
1365 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1366 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1367                                        enum b43_nphy_rf_sequence seq)
1368 {
1369         static const u16 trigger[] = {
1370                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1371                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1372                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1373                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1374                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1375                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1376         };
1377         int i;
1378         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1379
1380         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1381
1382         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1383                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1384         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1385         for (i = 0; i < 200; i++) {
1386                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1387                         goto ok;
1388                 msleep(1);
1389         }
1390         b43err(dev->wl, "RF sequence status timeout\n");
1391 ok:
1392         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1393 }
1394
1395 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1396 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1397                                                 u16 value, u8 core, bool off)
1398 {
1399         int i;
1400         u8 index = fls(field);
1401         u8 addr, en_addr, val_addr;
1402         /* we expect only one bit set */
1403         B43_WARN_ON(field & (~(1 << (index - 1))));
1404
1405         if (dev->phy.rev >= 3) {
1406                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1407                 for (i = 0; i < 2; i++) {
1408                         if (index == 0 || index == 16) {
1409                                 b43err(dev->wl,
1410                                         "Unsupported RF Ctrl Override call\n");
1411                                 return;
1412                         }
1413
1414                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1415                         en_addr = B43_PHY_N((i == 0) ?
1416                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1417                         val_addr = B43_PHY_N((i == 0) ?
1418                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1419
1420                         if (off) {
1421                                 b43_phy_mask(dev, en_addr, ~(field));
1422                                 b43_phy_mask(dev, val_addr,
1423                                                 ~(rf_ctrl->val_mask));
1424                         } else {
1425                                 if (core == 0 || ((1 << core) & i) != 0) {
1426                                         b43_phy_set(dev, en_addr, field);
1427                                         b43_phy_maskset(dev, val_addr,
1428                                                 ~(rf_ctrl->val_mask),
1429                                                 (value << rf_ctrl->val_shift));
1430                                 }
1431                         }
1432                 }
1433         } else {
1434                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1435                 if (off) {
1436                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1437                         value = 0;
1438                 } else {
1439                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1440                 }
1441
1442                 for (i = 0; i < 2; i++) {
1443                         if (index <= 1 || index == 16) {
1444                                 b43err(dev->wl,
1445                                         "Unsupported RF Ctrl Override call\n");
1446                                 return;
1447                         }
1448
1449                         if (index == 2 || index == 10 ||
1450                             (index >= 13 && index <= 15)) {
1451                                 core = 1;
1452                         }
1453
1454                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1455                         addr = B43_PHY_N((i == 0) ?
1456                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1457
1458                         if ((core & (1 << i)) != 0)
1459                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1460                                                 (value << rf_ctrl->shift));
1461
1462                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1463                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1464                                         B43_NPHY_RFCTL_CMD_START);
1465                         udelay(1);
1466                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1467                 }
1468         }
1469 }
1470
1471 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1472 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1473                                                 u16 value, u8 core)
1474 {
1475         u8 i, j;
1476         u16 reg, tmp, val;
1477
1478         B43_WARN_ON(dev->phy.rev < 3);
1479         B43_WARN_ON(field > 4);
1480
1481         for (i = 0; i < 2; i++) {
1482                 if ((core == 1 && i == 1) || (core == 2 && !i))
1483                         continue;
1484
1485                 reg = (i == 0) ?
1486                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1487                 b43_phy_mask(dev, reg, 0xFBFF);
1488
1489                 switch (field) {
1490                 case 0:
1491                         b43_phy_write(dev, reg, 0);
1492                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1493                         break;
1494                 case 1:
1495                         if (!i) {
1496                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1497                                                 0xFC3F, (value << 6));
1498                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1499                                                 0xFFFE, 1);
1500                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1501                                                 B43_NPHY_RFCTL_CMD_START);
1502                                 for (j = 0; j < 100; j++) {
1503                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1504                                                 j = 0;
1505                                                 break;
1506                                         }
1507                                         udelay(10);
1508                                 }
1509                                 if (j)
1510                                         b43err(dev->wl,
1511                                                 "intc override timeout\n");
1512                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1513                                                 0xFFFE);
1514                         } else {
1515                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1516                                                 0xFC3F, (value << 6));
1517                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1518                                                 0xFFFE, 1);
1519                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1520                                                 B43_NPHY_RFCTL_CMD_RXTX);
1521                                 for (j = 0; j < 100; j++) {
1522                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1523                                                 j = 0;
1524                                                 break;
1525                                         }
1526                                         udelay(10);
1527                                 }
1528                                 if (j)
1529                                         b43err(dev->wl,
1530                                                 "intc override timeout\n");
1531                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1532                                                 0xFFFE);
1533                         }
1534                         break;
1535                 case 2:
1536                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1537                                 tmp = 0x0020;
1538                                 val = value << 5;
1539                         } else {
1540                                 tmp = 0x0010;
1541                                 val = value << 4;
1542                         }
1543                         b43_phy_maskset(dev, reg, ~tmp, val);
1544                         break;
1545                 case 3:
1546                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1547                                 tmp = 0x0001;
1548                                 val = value;
1549                         } else {
1550                                 tmp = 0x0004;
1551                                 val = value << 2;
1552                         }
1553                         b43_phy_maskset(dev, reg, ~tmp, val);
1554                         break;
1555                 case 4:
1556                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1557                                 tmp = 0x0002;
1558                                 val = value << 1;
1559                         } else {
1560                                 tmp = 0x0008;
1561                                 val = value << 3;
1562                         }
1563                         b43_phy_maskset(dev, reg, ~tmp, val);
1564                         break;
1565                 }
1566         }
1567 }
1568
1569 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1570 {
1571         unsigned int i;
1572         u16 val;
1573
1574         val = 0x1E1F;
1575         for (i = 0; i < 14; i++) {
1576                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1577                 val -= 0x202;
1578         }
1579         val = 0x3E3F;
1580         for (i = 0; i < 16; i++) {
1581                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1582                 val -= 0x202;
1583         }
1584         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1585 }
1586
1587 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1588 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1589                                        s8 offset, u8 core, u8 rail, u8 type)
1590 {
1591         u16 tmp;
1592         bool core1or5 = (core == 1) || (core == 5);
1593         bool core2or5 = (core == 2) || (core == 5);
1594
1595         offset = clamp_val(offset, -32, 31);
1596         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1597
1598         if (core1or5 && (rail == 0) && (type == 2))
1599                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1600         if (core1or5 && (rail == 1) && (type == 2))
1601                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1602         if (core2or5 && (rail == 0) && (type == 2))
1603                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1604         if (core2or5 && (rail == 1) && (type == 2))
1605                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1606         if (core1or5 && (rail == 0) && (type == 0))
1607                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1608         if (core1or5 && (rail == 1) && (type == 0))
1609                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1610         if (core2or5 && (rail == 0) && (type == 0))
1611                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1612         if (core2or5 && (rail == 1) && (type == 0))
1613                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1614         if (core1or5 && (rail == 0) && (type == 1))
1615                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1616         if (core1or5 && (rail == 1) && (type == 1))
1617                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1618         if (core2or5 && (rail == 0) && (type == 1))
1619                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1620         if (core2or5 && (rail == 1) && (type == 1))
1621                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1622         if (core1or5 && (rail == 0) && (type == 6))
1623                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1624         if (core1or5 && (rail == 1) && (type == 6))
1625                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1626         if (core2or5 && (rail == 0) && (type == 6))
1627                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1628         if (core2or5 && (rail == 1) && (type == 6))
1629                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1630         if (core1or5 && (rail == 0) && (type == 3))
1631                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1632         if (core1or5 && (rail == 1) && (type == 3))
1633                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1634         if (core2or5 && (rail == 0) && (type == 3))
1635                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1636         if (core2or5 && (rail == 1) && (type == 3))
1637                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1638         if (core1or5 && (type == 4))
1639                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1640         if (core2or5 && (type == 4))
1641                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1642         if (core1or5 && (type == 5))
1643                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1644         if (core2or5 && (type == 5))
1645                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1646 }
1647
1648 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1649 {
1650         u16 val;
1651
1652         if (type < 3)
1653                 val = 0;
1654         else if (type == 6)
1655                 val = 1;
1656         else if (type == 3)
1657                 val = 2;
1658         else
1659                 val = 3;
1660
1661         val = (val << 12) | (val << 14);
1662         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1663         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1664
1665         if (type < 3) {
1666                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1667                                 (type + 1) << 4);
1668                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1669                                 (type + 1) << 4);
1670         }
1671
1672         /* TODO use some definitions */
1673         if (code == 0) {
1674                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1675                 if (type < 3) {
1676                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1677                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1678                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1679                         udelay(20);
1680                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1681                 }
1682         } else {
1683                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1684                                 0x3000);
1685                 if (type < 3) {
1686                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1687                                         0xFEC7, 0x0180);
1688                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1689                                         0xEFDC, (code << 1 | 0x1021));
1690                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1691                         udelay(20);
1692                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1693                 }
1694         }
1695 }
1696
1697 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1698 {
1699         struct b43_phy_n *nphy = dev->phy.n;
1700         u8 i;
1701         u16 reg, val;
1702
1703         if (code == 0) {
1704                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1705                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1706                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1707                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1708                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1709                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1710                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1711                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1712         } else {
1713                 for (i = 0; i < 2; i++) {
1714                         if ((code == 1 && i == 1) || (code == 2 && !i))
1715                                 continue;
1716
1717                         reg = (i == 0) ?
1718                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1719                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1720
1721                         if (type < 3) {
1722                                 reg = (i == 0) ?
1723                                         B43_NPHY_AFECTL_C1 :
1724                                         B43_NPHY_AFECTL_C2;
1725                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1726
1727                                 reg = (i == 0) ?
1728                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1729                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1730                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1731
1732                                 if (type == 0)
1733                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1734                                 else if (type == 1)
1735                                         val = 16;
1736                                 else
1737                                         val = 32;
1738                                 b43_phy_set(dev, reg, val);
1739
1740                                 reg = (i == 0) ?
1741                                         B43_NPHY_TXF_40CO_B1S0 :
1742                                         B43_NPHY_TXF_40CO_B32S1;
1743                                 b43_phy_set(dev, reg, 0x0020);
1744                         } else {
1745                                 if (type == 6)
1746                                         val = 0x0100;
1747                                 else if (type == 3)
1748                                         val = 0x0200;
1749                                 else
1750                                         val = 0x0300;
1751
1752                                 reg = (i == 0) ?
1753                                         B43_NPHY_AFECTL_C1 :
1754                                         B43_NPHY_AFECTL_C2;
1755
1756                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1757                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1758
1759                                 if (type != 3 && type != 6) {
1760                                         enum ieee80211_band band =
1761                                                 b43_current_band(dev->wl);
1762
1763                                         if ((nphy->ipa2g_on &&
1764                                                 band == IEEE80211_BAND_2GHZ) ||
1765                                                 (nphy->ipa5g_on &&
1766                                                 band == IEEE80211_BAND_5GHZ))
1767                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1768                                         else
1769                                                 val = 0x11;
1770                                         reg = (i == 0) ? 0x2000 : 0x3000;
1771                                         reg |= B2055_PADDRV;
1772                                         b43_radio_write16(dev, reg, val);
1773
1774                                         reg = (i == 0) ?
1775                                                 B43_NPHY_AFECTL_OVER1 :
1776                                                 B43_NPHY_AFECTL_OVER;
1777                                         b43_phy_set(dev, reg, 0x0200);
1778                                 }
1779                         }
1780                 }
1781         }
1782 }
1783
1784 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1785 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1786 {
1787         if (dev->phy.rev >= 3)
1788                 b43_nphy_rev3_rssi_select(dev, code, type);
1789         else
1790                 b43_nphy_rev2_rssi_select(dev, code, type);
1791 }
1792
1793 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1794 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1795 {
1796         int i;
1797         for (i = 0; i < 2; i++) {
1798                 if (type == 2) {
1799                         if (i == 0) {
1800                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1801                                                   0xFC, buf[0]);
1802                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1803                                                   0xFC, buf[1]);
1804                         } else {
1805                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1806                                                   0xFC, buf[2 * i]);
1807                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1808                                                   0xFC, buf[2 * i + 1]);
1809                         }
1810                 } else {
1811                         if (i == 0)
1812                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1813                                                   0xF3, buf[0] << 2);
1814                         else
1815                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1816                                                   0xF3, buf[2 * i + 1] << 2);
1817                 }
1818         }
1819 }
1820
1821 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1822 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1823                                 u8 nsamp)
1824 {
1825         int i;
1826         int out;
1827         u16 save_regs_phy[9];
1828         u16 s[2];
1829
1830         if (dev->phy.rev >= 3) {
1831                 save_regs_phy[0] = b43_phy_read(dev,
1832                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1833                 save_regs_phy[1] = b43_phy_read(dev,
1834                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1835                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1836                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1837                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1838                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1839                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1840                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1841         }
1842
1843         b43_nphy_rssi_select(dev, 5, type);
1844
1845         if (dev->phy.rev < 2) {
1846                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1847                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1848         }
1849
1850         for (i = 0; i < 4; i++)
1851                 buf[i] = 0;
1852
1853         for (i = 0; i < nsamp; i++) {
1854                 if (dev->phy.rev < 2) {
1855                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1856                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1857                 } else {
1858                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1859                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1860                 }
1861
1862                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1863                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1864                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1865                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1866         }
1867         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1868                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1869
1870         if (dev->phy.rev < 2)
1871                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1872
1873         if (dev->phy.rev >= 3) {
1874                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1875                                 save_regs_phy[0]);
1876                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1877                                 save_regs_phy[1]);
1878                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1879                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1880                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1881                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1882                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1883                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1884         }
1885
1886         return out;
1887 }
1888
1889 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1890 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1891 {
1892         int i, j;
1893         u8 state[4];
1894         u8 code, val;
1895         u16 class, override;
1896         u8 regs_save_radio[2];
1897         u16 regs_save_phy[2];
1898         s8 offset[4];
1899
1900         u16 clip_state[2];
1901         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1902         s32 results_min[4] = { };
1903         u8 vcm_final[4] = { };
1904         s32 results[4][4] = { };
1905         s32 miniq[4][2] = { };
1906
1907         if (type == 2) {
1908                 code = 0;
1909                 val = 6;
1910         } else if (type < 2) {
1911                 code = 25;
1912                 val = 4;
1913         } else {
1914                 B43_WARN_ON(1);
1915                 return;
1916         }
1917
1918         class = b43_nphy_classifier(dev, 0, 0);
1919         b43_nphy_classifier(dev, 7, 4);
1920         b43_nphy_read_clip_detection(dev, clip_state);
1921         b43_nphy_write_clip_detection(dev, clip_off);
1922
1923         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1924                 override = 0x140;
1925         else
1926                 override = 0x110;
1927
1928         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1929         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1930         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1931         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1932
1933         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1934         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1935         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1936         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1937
1938         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1939         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1940         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1941         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1942         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1943         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1944
1945         b43_nphy_rssi_select(dev, 5, type);
1946         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1947         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1948
1949         for (i = 0; i < 4; i++) {
1950                 u8 tmp[4];
1951                 for (j = 0; j < 4; j++)
1952                         tmp[j] = i;
1953                 if (type != 1)
1954                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1955                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1956                 if (type < 2)
1957                         for (j = 0; j < 2; j++)
1958                                 miniq[i][j] = min(results[i][2 * j],
1959                                                 results[i][2 * j + 1]);
1960         }
1961
1962         for (i = 0; i < 4; i++) {
1963                 s32 mind = 40;
1964                 u8 minvcm = 0;
1965                 s32 minpoll = 249;
1966                 s32 curr;
1967                 for (j = 0; j < 4; j++) {
1968                         if (type == 2)
1969                                 curr = abs(results[j][i]);
1970                         else
1971                                 curr = abs(miniq[j][i / 2] - code * 8);
1972
1973                         if (curr < mind) {
1974                                 mind = curr;
1975                                 minvcm = j;
1976                         }
1977
1978                         if (results[j][i] < minpoll)
1979                                 minpoll = results[j][i];
1980                 }
1981                 results_min[i] = minpoll;
1982                 vcm_final[i] = minvcm;
1983         }
1984
1985         if (type != 1)
1986                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1987
1988         for (i = 0; i < 4; i++) {
1989                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1990
1991                 if (offset[i] < 0)
1992                         offset[i] = -((abs(offset[i]) + 4) / 8);
1993                 else
1994                         offset[i] = (offset[i] + 4) / 8;
1995
1996                 if (results_min[i] == 248)
1997                         offset[i] = code - 32;
1998
1999                 if (i % 2 == 0)
2000                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2001                                                         type);
2002                 else
2003                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2004                                                         type);
2005         }
2006
2007         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2008         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2009
2010         switch (state[2]) {
2011         case 1:
2012                 b43_nphy_rssi_select(dev, 1, 2);
2013                 break;
2014         case 4:
2015                 b43_nphy_rssi_select(dev, 1, 0);
2016                 break;
2017         case 2:
2018                 b43_nphy_rssi_select(dev, 1, 1);
2019                 break;
2020         default:
2021                 b43_nphy_rssi_select(dev, 1, 1);
2022                 break;
2023         }
2024
2025         switch (state[3]) {
2026         case 1:
2027                 b43_nphy_rssi_select(dev, 2, 2);
2028                 break;
2029         case 4:
2030                 b43_nphy_rssi_select(dev, 2, 0);
2031                 break;
2032         default:
2033                 b43_nphy_rssi_select(dev, 2, 1);
2034                 break;
2035         }
2036
2037         b43_nphy_rssi_select(dev, 0, type);
2038
2039         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2040         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2041         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2042         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2043
2044         b43_nphy_classifier(dev, 7, class);
2045         b43_nphy_write_clip_detection(dev, clip_state);
2046 }
2047
2048 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2049 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2050 {
2051         /* TODO */
2052 }
2053
2054 /*
2055  * RSSI Calibration
2056  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2057  */
2058 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2059 {
2060         if (dev->phy.rev >= 3) {
2061                 b43_nphy_rev3_rssi_cal(dev);
2062         } else {
2063                 b43_nphy_rev2_rssi_cal(dev, 2);
2064                 b43_nphy_rev2_rssi_cal(dev, 0);
2065                 b43_nphy_rev2_rssi_cal(dev, 1);
2066         }
2067 }
2068
2069 /*
2070  * Restore RSSI Calibration
2071  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2072  */
2073 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2074 {
2075         struct b43_phy_n *nphy = dev->phy.n;
2076
2077         u16 *rssical_radio_regs = NULL;
2078         u16 *rssical_phy_regs = NULL;
2079
2080         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2081                 if (!nphy->rssical_chanspec_2G.center_freq)
2082                         return;
2083                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2084                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2085         } else {
2086                 if (!nphy->rssical_chanspec_5G.center_freq)
2087                         return;
2088                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2089                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2090         }
2091
2092         /* TODO use some definitions */
2093         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2094         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2095
2096         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2097         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2098         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2099         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2100
2101         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2102         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2103         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2104         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2105
2106         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2107         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2108         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2109         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2110 }
2111
2112 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2113 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2114 {
2115         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2116                 if (dev->phy.rev >= 6) {
2117                         /* TODO If the chip is 47162
2118                                 return txpwrctrl_tx_gain_ipa_rev5 */
2119                         return txpwrctrl_tx_gain_ipa_rev6;
2120                 } else if (dev->phy.rev >= 5) {
2121                         return txpwrctrl_tx_gain_ipa_rev5;
2122                 } else {
2123                         return txpwrctrl_tx_gain_ipa;
2124                 }
2125         } else {
2126                 return txpwrctrl_tx_gain_ipa_5g;
2127         }
2128 }
2129
2130 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2131 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2132 {
2133         struct b43_phy_n *nphy = dev->phy.n;
2134         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2135         u16 tmp;
2136         u8 offset, i;
2137
2138         if (dev->phy.rev >= 3) {
2139             for (i = 0; i < 2; i++) {
2140                 tmp = (i == 0) ? 0x2000 : 0x3000;
2141                 offset = i * 11;
2142
2143                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2144                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2145                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2146                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2147                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2148                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2149                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2150                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2151                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2152                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2153                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2154
2155                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2156                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2157                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2158                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2159                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2160                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2161                         if (nphy->ipa5g_on) {
2162                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2163                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2164                         } else {
2165                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2166                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2167                         }
2168                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2169                 } else {
2170                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2171                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2172                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2173                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2174                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2175                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2176                         if (nphy->ipa2g_on) {
2177                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2178                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2179                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2180                         } else {
2181                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2182                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2183                         }
2184                 }
2185                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2186                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2187                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2188             }
2189         } else {
2190                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2191                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2192
2193                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2194                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2195
2196                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2197                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2198
2199                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2200                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2201
2202                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2203                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2204
2205                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2206                     B43_NPHY_BANDCTL_5GHZ)) {
2207                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2208                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2209                 } else {
2210                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2211                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2212                 }
2213
2214                 if (dev->phy.rev < 2) {
2215                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2216                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2217                 } else {
2218                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2219                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2220                 }
2221         }
2222 }
2223
2224 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2225 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2226                                         struct nphy_txgains target,
2227                                         struct nphy_iqcal_params *params)
2228 {
2229         int i, j, indx;
2230         u16 gain;
2231
2232         if (dev->phy.rev >= 3) {
2233                 params->txgm = target.txgm[core];
2234                 params->pga = target.pga[core];
2235                 params->pad = target.pad[core];
2236                 params->ipa = target.ipa[core];
2237                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2238                                         (params->pad << 4) | (params->ipa);
2239                 for (j = 0; j < 5; j++)
2240                         params->ncorr[j] = 0x79;
2241         } else {
2242                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2243                         (target.txgm[core] << 8);
2244
2245                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2246                         1 : 0;
2247                 for (i = 0; i < 9; i++)
2248                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2249                                 break;
2250                 i = min(i, 8);
2251
2252                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2253                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2254                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2255                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2256                                         (params->pad << 2);
2257                 for (j = 0; j < 4; j++)
2258                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2259         }
2260 }
2261
2262 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2263 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2264 {
2265         struct b43_phy_n *nphy = dev->phy.n;
2266         int i;
2267         u16 scale, entry;
2268
2269         u16 tmp = nphy->txcal_bbmult;
2270         if (core == 0)
2271                 tmp >>= 8;
2272         tmp &= 0xff;
2273
2274         for (i = 0; i < 18; i++) {
2275                 scale = (ladder_lo[i].percent * tmp) / 100;
2276                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2277                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2278
2279                 scale = (ladder_iq[i].percent * tmp) / 100;
2280                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2281                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2282         }
2283 }
2284
2285 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2286 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2287 {
2288         int i;
2289         for (i = 0; i < 15; i++)
2290                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2291                                 tbl_tx_filter_coef_rev4[2][i]);
2292 }
2293
2294 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2295 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2296 {
2297         int i, j;
2298         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2299         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2300
2301         for (i = 0; i < 3; i++)
2302                 for (j = 0; j < 15; j++)
2303                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2304                                         tbl_tx_filter_coef_rev4[i][j]);
2305
2306         if (dev->phy.is_40mhz) {
2307                 for (j = 0; j < 15; j++)
2308                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2309                                         tbl_tx_filter_coef_rev4[3][j]);
2310         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2311                 for (j = 0; j < 15; j++)
2312                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2313                                         tbl_tx_filter_coef_rev4[5][j]);
2314         }
2315
2316         if (dev->phy.channel == 14)
2317                 for (j = 0; j < 15; j++)
2318                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2319                                         tbl_tx_filter_coef_rev4[6][j]);
2320 }
2321
2322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2323 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2324 {
2325         struct b43_phy_n *nphy = dev->phy.n;
2326
2327         u16 curr_gain[2];
2328         struct nphy_txgains target;
2329         const u32 *table = NULL;
2330
2331         if (nphy->txpwrctrl == 0) {
2332                 int i;
2333
2334                 if (nphy->hang_avoid)
2335                         b43_nphy_stay_in_carrier_search(dev, true);
2336                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2337                 if (nphy->hang_avoid)
2338                         b43_nphy_stay_in_carrier_search(dev, false);
2339
2340                 for (i = 0; i < 2; ++i) {
2341                         if (dev->phy.rev >= 3) {
2342                                 target.ipa[i] = curr_gain[i] & 0x000F;
2343                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2344                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2345                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2346                         } else {
2347                                 target.ipa[i] = curr_gain[i] & 0x0003;
2348                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2349                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2350                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2351                         }
2352                 }
2353         } else {
2354                 int i;
2355                 u16 index[2];
2356                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2357                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2358                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2359                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2360                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2361                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2362
2363                 for (i = 0; i < 2; ++i) {
2364                         if (dev->phy.rev >= 3) {
2365                                 enum ieee80211_band band =
2366                                         b43_current_band(dev->wl);
2367
2368                                 if ((nphy->ipa2g_on &&
2369                                      band == IEEE80211_BAND_2GHZ) ||
2370                                     (nphy->ipa5g_on &&
2371                                      band == IEEE80211_BAND_5GHZ)) {
2372                                         table = b43_nphy_get_ipa_gain_table(dev);
2373                                 } else {
2374                                         if (band == IEEE80211_BAND_5GHZ) {
2375                                                 if (dev->phy.rev == 3)
2376                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2377                                                 else if (dev->phy.rev == 4)
2378                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2379                                                 else
2380                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2381                                         } else {
2382                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2383                                         }
2384                                 }
2385
2386                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2387                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2388                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2389                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2390                         } else {
2391                                 table = b43_ntab_tx_gain_rev0_1_2;
2392
2393                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2394                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2395                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2396                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2397                         }
2398                 }
2399         }
2400
2401         return target;
2402 }
2403
2404 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2405 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2406 {
2407         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2408
2409         if (dev->phy.rev >= 3) {
2410                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2411                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2412                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2413                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2414                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2415                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2416                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2417                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2418                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2419                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2420                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2421                 b43_nphy_reset_cca(dev);
2422         } else {
2423                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2424                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2425                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2426                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2427                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2428                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2429                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2430         }
2431 }
2432
2433 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2434 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2435 {
2436         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2437         u16 tmp;
2438
2439         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2440         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2441         if (dev->phy.rev >= 3) {
2442                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2443                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2444
2445                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2446                 regs[2] = tmp;
2447                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2448
2449                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2450                 regs[3] = tmp;
2451                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2452
2453                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2454                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2455                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2456
2457                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2458                 regs[5] = tmp;
2459                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2460
2461                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2462                 regs[6] = tmp;
2463                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2464                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2465                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2466
2467                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2468                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2469                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2470
2471                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2472                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2473                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2474                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2475         } else {
2476                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2477                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2478                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2479                 regs[2] = tmp;
2480                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2481                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2482                 regs[3] = tmp;
2483                 tmp |= 0x2000;
2484                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2485                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2486                 regs[4] = tmp;
2487                 tmp |= 0x2000;
2488                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2489                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2490                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2491                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2492                         tmp = 0x0180;
2493                 else
2494                         tmp = 0x0120;
2495                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2496                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2497         }
2498 }
2499
2500 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2501 static void b43_nphy_save_cal(struct b43_wldev *dev)
2502 {
2503         struct b43_phy_n *nphy = dev->phy.n;
2504
2505         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2506         u16 *txcal_radio_regs = NULL;
2507         struct b43_chanspec *iqcal_chanspec;
2508         u16 *table = NULL;
2509
2510         if (nphy->hang_avoid)
2511                 b43_nphy_stay_in_carrier_search(dev, 1);
2512
2513         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2514                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2515                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2516                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2517                 table = nphy->cal_cache.txcal_coeffs_2G;
2518         } else {
2519                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2520                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2521                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2522                 table = nphy->cal_cache.txcal_coeffs_5G;
2523         }
2524
2525         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2526         /* TODO use some definitions */
2527         if (dev->phy.rev >= 3) {
2528                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2529                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2530                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2531                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2532                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2533                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2534                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2535                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2536         } else {
2537                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2538                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2539                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2540                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2541         }
2542         iqcal_chanspec->center_freq = dev->phy.channel_freq;
2543         iqcal_chanspec->channel_type = dev->phy.channel_type;
2544         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
2545
2546         if (nphy->hang_avoid)
2547                 b43_nphy_stay_in_carrier_search(dev, 0);
2548 }
2549
2550 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2551 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2552 {
2553         struct b43_phy_n *nphy = dev->phy.n;
2554
2555         u16 coef[4];
2556         u16 *loft = NULL;
2557         u16 *table = NULL;
2558
2559         int i;
2560         u16 *txcal_radio_regs = NULL;
2561         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2562
2563         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2564                 if (!nphy->iqcal_chanspec_2G.center_freq)
2565                         return;
2566                 table = nphy->cal_cache.txcal_coeffs_2G;
2567                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2568         } else {
2569                 if (!nphy->iqcal_chanspec_5G.center_freq)
2570                         return;
2571                 table = nphy->cal_cache.txcal_coeffs_5G;
2572                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2573         }
2574
2575         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2576
2577         for (i = 0; i < 4; i++) {
2578                 if (dev->phy.rev >= 3)
2579                         table[i] = coef[i];
2580                 else
2581                         coef[i] = 0;
2582         }
2583
2584         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2585         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2586         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2587
2588         if (dev->phy.rev < 2)
2589                 b43_nphy_tx_iq_workaround(dev);
2590
2591         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2592                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2593                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2594         } else {
2595                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2596                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2597         }
2598
2599         /* TODO use some definitions */
2600         if (dev->phy.rev >= 3) {
2601                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2602                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2603                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2604                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2605                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2606                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2607                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2608                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2609         } else {
2610                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2611                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2612                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2613                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2614         }
2615         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2616 }
2617
2618 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2619 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2620                                 struct nphy_txgains target,
2621                                 bool full, bool mphase)
2622 {
2623         struct b43_phy_n *nphy = dev->phy.n;
2624         int i;
2625         int error = 0;
2626         int freq;
2627         bool avoid = false;
2628         u8 length;
2629         u16 tmp, core, type, count, max, numb, last, cmd;
2630         const u16 *table;
2631         bool phy6or5x;
2632
2633         u16 buffer[11];
2634         u16 diq_start = 0;
2635         u16 save[2];
2636         u16 gain[2];
2637         struct nphy_iqcal_params params[2];
2638         bool updated[2] = { };
2639
2640         b43_nphy_stay_in_carrier_search(dev, true);
2641
2642         if (dev->phy.rev >= 4) {
2643                 avoid = nphy->hang_avoid;
2644                 nphy->hang_avoid = 0;
2645         }
2646
2647         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2648
2649         for (i = 0; i < 2; i++) {
2650                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2651                 gain[i] = params[i].cal_gain;
2652         }
2653
2654         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2655
2656         b43_nphy_tx_cal_radio_setup(dev);
2657         b43_nphy_tx_cal_phy_setup(dev);
2658
2659         phy6or5x = dev->phy.rev >= 6 ||
2660                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2661                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2662         if (phy6or5x) {
2663                 if (dev->phy.is_40mhz) {
2664                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2665                                         tbl_tx_iqlo_cal_loft_ladder_40);
2666                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2667                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2668                 } else {
2669                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2670                                         tbl_tx_iqlo_cal_loft_ladder_20);
2671                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2672                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2673                 }
2674         }
2675
2676         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2677
2678         if (!dev->phy.is_40mhz)
2679                 freq = 2500;
2680         else
2681                 freq = 5000;
2682
2683         if (nphy->mphase_cal_phase_id > 2)
2684                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2685                                         0xFFFF, 0, true, false);
2686         else
2687                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2688
2689         if (error == 0) {
2690                 if (nphy->mphase_cal_phase_id > 2) {
2691                         table = nphy->mphase_txcal_bestcoeffs;
2692                         length = 11;
2693                         if (dev->phy.rev < 3)
2694                                 length -= 2;
2695                 } else {
2696                         if (!full && nphy->txiqlocal_coeffsvalid) {
2697                                 table = nphy->txiqlocal_bestc;
2698                                 length = 11;
2699                                 if (dev->phy.rev < 3)
2700                                         length -= 2;
2701                         } else {
2702                                 full = true;
2703                                 if (dev->phy.rev >= 3) {
2704                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2705                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2706                                 } else {
2707                                         table = tbl_tx_iqlo_cal_startcoefs;
2708                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2709                                 }
2710                         }
2711                 }
2712
2713                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2714
2715                 if (full) {
2716                         if (dev->phy.rev >= 3)
2717                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2718                         else
2719                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2720                 } else {
2721                         if (dev->phy.rev >= 3)
2722                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2723                         else
2724                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2725                 }
2726
2727                 if (mphase) {
2728                         count = nphy->mphase_txcal_cmdidx;
2729                         numb = min(max,
2730                                 (u16)(count + nphy->mphase_txcal_numcmds));
2731                 } else {
2732                         count = 0;
2733                         numb = max;
2734                 }
2735
2736                 for (; count < numb; count++) {
2737                         if (full) {
2738                                 if (dev->phy.rev >= 3)
2739                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2740                                 else
2741                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2742                         } else {
2743                                 if (dev->phy.rev >= 3)
2744                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2745                                 else
2746                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2747                         }
2748
2749                         core = (cmd & 0x3000) >> 12;
2750                         type = (cmd & 0x0F00) >> 8;
2751
2752                         if (phy6or5x && updated[core] == 0) {
2753                                 b43_nphy_update_tx_cal_ladder(dev, core);
2754                                 updated[core] = 1;
2755                         }
2756
2757                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2758                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2759
2760                         if (type == 1 || type == 3 || type == 4) {
2761                                 buffer[0] = b43_ntab_read(dev,
2762                                                 B43_NTAB16(15, 69 + core));
2763                                 diq_start = buffer[0];
2764                                 buffer[0] = 0;
2765                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2766                                                 0);
2767                         }
2768
2769                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2770                         for (i = 0; i < 2000; i++) {
2771                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2772                                 if (tmp & 0xC000)
2773                                         break;
2774                                 udelay(10);
2775                         }
2776
2777                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2778                                                 buffer);
2779                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2780                                                 buffer);
2781
2782                         if (type == 1 || type == 3 || type == 4)
2783                                 buffer[0] = diq_start;
2784                 }
2785
2786                 if (mphase)
2787                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2788
2789                 last = (dev->phy.rev < 3) ? 6 : 7;
2790
2791                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2792                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2793                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2794                         if (dev->phy.rev < 3) {
2795                                 buffer[0] = 0;
2796                                 buffer[1] = 0;
2797                                 buffer[2] = 0;
2798                                 buffer[3] = 0;
2799                         }
2800                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2801                                                 buffer);
2802                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2803                                                 buffer);
2804                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2805                                                 buffer);
2806                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2807                                                 buffer);
2808                         length = 11;
2809                         if (dev->phy.rev < 3)
2810                                 length -= 2;
2811                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2812                                                 nphy->txiqlocal_bestc);
2813                         nphy->txiqlocal_coeffsvalid = true;
2814                         nphy->txiqlocal_chanspec.center_freq =
2815                                                         dev->phy.channel_freq;
2816                         nphy->txiqlocal_chanspec.channel_type =
2817                                                         dev->phy.channel_type;
2818                 } else {
2819                         length = 11;
2820                         if (dev->phy.rev < 3)
2821                                 length -= 2;
2822                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2823                                                 nphy->mphase_txcal_bestcoeffs);
2824                 }
2825
2826                 b43_nphy_stop_playback(dev);
2827                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2828         }
2829
2830         b43_nphy_tx_cal_phy_cleanup(dev);
2831         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2832
2833         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2834                 b43_nphy_tx_iq_workaround(dev);
2835
2836         if (dev->phy.rev >= 4)
2837                 nphy->hang_avoid = avoid;
2838
2839         b43_nphy_stay_in_carrier_search(dev, false);
2840
2841         return error;
2842 }
2843
2844 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2845 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2846 {
2847         struct b43_phy_n *nphy = dev->phy.n;
2848         u8 i;
2849         u16 buffer[7];
2850         bool equal = true;
2851
2852         if (!nphy->txiqlocal_coeffsvalid ||
2853             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
2854             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
2855                 return;
2856
2857         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2858         for (i = 0; i < 4; i++) {
2859                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2860                         equal = false;
2861                         break;
2862                 }
2863         }
2864
2865         if (!equal) {
2866                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2867                                         nphy->txiqlocal_bestc);
2868                 for (i = 0; i < 4; i++)
2869                         buffer[i] = 0;
2870                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2871                                         buffer);
2872                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2873                                         &nphy->txiqlocal_bestc[5]);
2874                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2875                                         &nphy->txiqlocal_bestc[5]);
2876         }
2877 }
2878
2879 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2880 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2881                         struct nphy_txgains target, u8 type, bool debug)
2882 {
2883         struct b43_phy_n *nphy = dev->phy.n;
2884         int i, j, index;
2885         u8 rfctl[2];
2886         u8 afectl_core;
2887         u16 tmp[6];
2888         u16 cur_hpf1, cur_hpf2, cur_lna;
2889         u32 real, imag;
2890         enum ieee80211_band band;
2891
2892         u8 use;
2893         u16 cur_hpf;
2894         u16 lna[3] = { 3, 3, 1 };
2895         u16 hpf1[3] = { 7, 2, 0 };
2896         u16 hpf2[3] = { 2, 0, 0 };
2897         u32 power[3] = { };
2898         u16 gain_save[2];
2899         u16 cal_gain[2];
2900         struct nphy_iqcal_params cal_params[2];
2901         struct nphy_iq_est est;
2902         int ret = 0;
2903         bool playtone = true;
2904         int desired = 13;
2905
2906         b43_nphy_stay_in_carrier_search(dev, 1);
2907
2908         if (dev->phy.rev < 2)
2909                 b43_nphy_reapply_tx_cal_coeffs(dev);
2910         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2911         for (i = 0; i < 2; i++) {
2912                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2913                 cal_gain[i] = cal_params[i].cal_gain;
2914         }
2915         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2916
2917         for (i = 0; i < 2; i++) {
2918                 if (i == 0) {
2919                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2920                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2921                         afectl_core = B43_NPHY_AFECTL_C1;
2922                 } else {
2923                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2924                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2925                         afectl_core = B43_NPHY_AFECTL_C2;
2926                 }
2927
2928                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2929                 tmp[2] = b43_phy_read(dev, afectl_core);
2930                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2931                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2932                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2933
2934                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2935                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2936                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2937                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2938                                 (1 - i));
2939                 b43_phy_set(dev, afectl_core, 0x0006);
2940                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2941
2942                 band = b43_current_band(dev->wl);
2943
2944                 if (nphy->rxcalparams & 0xFF000000) {
2945                         if (band == IEEE80211_BAND_5GHZ)
2946                                 b43_phy_write(dev, rfctl[0], 0x140);
2947                         else
2948                                 b43_phy_write(dev, rfctl[0], 0x110);
2949                 } else {
2950                         if (band == IEEE80211_BAND_5GHZ)
2951                                 b43_phy_write(dev, rfctl[0], 0x180);
2952                         else
2953                                 b43_phy_write(dev, rfctl[0], 0x120);
2954                 }
2955
2956                 if (band == IEEE80211_BAND_5GHZ)
2957                         b43_phy_write(dev, rfctl[1], 0x148);
2958                 else
2959                         b43_phy_write(dev, rfctl[1], 0x114);
2960
2961                 if (nphy->rxcalparams & 0x10000) {
2962                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2963                                         (i + 1));
2964                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2965                                         (2 - i));
2966                 }
2967
2968                 for (j = 0; j < 4; j++) {
2969                         if (j < 3) {
2970                                 cur_lna = lna[j];
2971                                 cur_hpf1 = hpf1[j];
2972                                 cur_hpf2 = hpf2[j];
2973                         } else {
2974                                 if (power[1] > 10000) {
2975                                         use = 1;
2976                                         cur_hpf = cur_hpf1;
2977                                         index = 2;
2978                                 } else {
2979                                         if (power[0] > 10000) {
2980                                                 use = 1;
2981                                                 cur_hpf = cur_hpf1;
2982                                                 index = 1;
2983                                         } else {
2984                                                 index = 0;
2985                                                 use = 2;
2986                                                 cur_hpf = cur_hpf2;
2987                                         }
2988                                 }
2989                                 cur_lna = lna[index];
2990                                 cur_hpf1 = hpf1[index];
2991                                 cur_hpf2 = hpf2[index];
2992                                 cur_hpf += desired - hweight32(power[index]);
2993                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2994                                 if (use == 1)
2995                                         cur_hpf1 = cur_hpf;
2996                                 else
2997                                         cur_hpf2 = cur_hpf;
2998                         }
2999
3000                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3001                                         (cur_lna << 2));
3002                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3003                                                                         false);
3004                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3005                         b43_nphy_stop_playback(dev);
3006
3007                         if (playtone) {
3008                                 ret = b43_nphy_tx_tone(dev, 4000,
3009                                                 (nphy->rxcalparams & 0xFFFF),
3010                                                 false, false);
3011                                 playtone = false;
3012                         } else {
3013                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3014                                                         false, false);
3015                         }
3016
3017                         if (ret == 0) {
3018                                 if (j < 3) {
3019                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3020                                                                         false);
3021                                         if (i == 0) {
3022                                                 real = est.i0_pwr;
3023                                                 imag = est.q0_pwr;
3024                                         } else {
3025                                                 real = est.i1_pwr;
3026                                                 imag = est.q1_pwr;
3027                                         }
3028                                         power[i] = ((real + imag) / 1024) + 1;
3029                                 } else {
3030                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3031                                 }
3032                                 b43_nphy_stop_playback(dev);
3033                         }
3034
3035                         if (ret != 0)
3036                                 break;
3037                 }
3038
3039                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3040                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3041                 b43_phy_write(dev, rfctl[1], tmp[5]);
3042                 b43_phy_write(dev, rfctl[0], tmp[4]);
3043                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3044                 b43_phy_write(dev, afectl_core, tmp[2]);
3045                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3046
3047                 if (ret != 0)
3048                         break;
3049         }
3050
3051         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3052         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3053         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3054
3055         b43_nphy_stay_in_carrier_search(dev, 0);
3056
3057         return ret;
3058 }
3059
3060 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3061                         struct nphy_txgains target, u8 type, bool debug)
3062 {
3063         return -1;
3064 }
3065
3066 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3067 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3068                         struct nphy_txgains target, u8 type, bool debug)
3069 {
3070         if (dev->phy.rev >= 3)
3071                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3072         else
3073                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3074 }
3075
3076 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3077 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3078 {
3079         u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3080         if (on)
3081                 tmslow |= SSB_TMSLOW_PHYCLK;
3082         else
3083                 tmslow &= ~SSB_TMSLOW_PHYCLK;
3084         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3085 }
3086
3087 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3088 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3089 {
3090         struct b43_phy *phy = &dev->phy;
3091         struct b43_phy_n *nphy = phy->n;
3092         u16 buf[16];
3093
3094         nphy->phyrxchain = mask;
3095
3096         if (0 /* FIXME clk */)
3097                 return;
3098
3099         b43_mac_suspend(dev);
3100
3101         if (nphy->hang_avoid)
3102                 b43_nphy_stay_in_carrier_search(dev, true);
3103
3104         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3105                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3106
3107         if ((mask & 0x3) != 0x3) {
3108                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3109                 if (dev->phy.rev >= 3) {
3110                         /* TODO */
3111                 }
3112         } else {
3113                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3114                 if (dev->phy.rev >= 3) {
3115                         /* TODO */
3116                 }
3117         }
3118
3119         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3120
3121         if (nphy->hang_avoid)
3122                 b43_nphy_stay_in_carrier_search(dev, false);
3123
3124         b43_mac_enable(dev);
3125 }
3126
3127 /*
3128  * Init N-PHY
3129  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3130  */
3131 int b43_phy_initn(struct b43_wldev *dev)
3132 {
3133         struct ssb_bus *bus = dev->dev->bus;
3134         struct b43_phy *phy = &dev->phy;
3135         struct b43_phy_n *nphy = phy->n;
3136         u8 tx_pwr_state;
3137         struct nphy_txgains target;
3138         u16 tmp;
3139         enum ieee80211_band tmp2;
3140         bool do_rssi_cal;
3141
3142         u16 clip[2];
3143         bool do_cal = false;
3144
3145         if ((dev->phy.rev >= 3) &&
3146            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3147            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3148                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3149         }
3150         nphy->deaf_count = 0;
3151         b43_nphy_tables_init(dev);
3152         nphy->crsminpwr_adjusted = false;
3153         nphy->noisevars_adjusted = false;
3154
3155         /* Clear all overrides */
3156         if (dev->phy.rev >= 3) {
3157                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3158                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3159                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3160                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3161         } else {
3162                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3163         }
3164         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3165         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3166         if (dev->phy.rev < 6) {
3167                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3168                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3169         }
3170         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3171                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3172                        B43_NPHY_RFSEQMODE_TROVER));
3173         if (dev->phy.rev >= 3)
3174                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3175         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3176
3177         if (dev->phy.rev <= 2) {
3178                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3179                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3180                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3181                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3182         }
3183         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3184         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3185
3186         if (bus->sprom.boardflags2_lo & 0x100 ||
3187             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3188              bus->boardinfo.type == 0x8B))
3189                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3190         else
3191                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3192         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3193         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3194         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3195
3196         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3197         b43_nphy_update_txrx_chain(dev);
3198
3199         if (phy->rev < 2) {
3200                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3201                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3202         }
3203
3204         tmp2 = b43_current_band(dev->wl);
3205         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3206             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3207                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3208                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3209                                 nphy->papd_epsilon_offset[0] << 7);
3210                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3211                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3212                                 nphy->papd_epsilon_offset[1] << 7);
3213                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3214         } else if (phy->rev >= 5) {
3215                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3216         }
3217
3218         b43_nphy_workarounds(dev);
3219
3220         /* Reset CCA, in init code it differs a little from standard way */
3221         b43_nphy_bmac_clock_fgc(dev, 1);
3222         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3223         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3224         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3225         b43_nphy_bmac_clock_fgc(dev, 0);
3226
3227         b43_nphy_mac_phy_clock_set(dev, true);
3228
3229         b43_nphy_pa_override(dev, false);
3230         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3231         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3232         b43_nphy_pa_override(dev, true);
3233
3234         b43_nphy_classifier(dev, 0, 0);
3235         b43_nphy_read_clip_detection(dev, clip);
3236         tx_pwr_state = nphy->txpwrctrl;
3237         /* TODO N PHY TX power control with argument 0
3238                 (turning off power control) */
3239         /* TODO Fix the TX Power Settings */
3240         /* TODO N PHY TX Power Control Idle TSSI */
3241         /* TODO N PHY TX Power Control Setup */
3242
3243         if (phy->rev >= 3) {
3244                 /* TODO */
3245         } else {
3246                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3247                                         b43_ntab_tx_gain_rev0_1_2);
3248                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3249                                         b43_ntab_tx_gain_rev0_1_2);
3250         }
3251
3252         if (nphy->phyrxchain != 3)
3253                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3254         if (nphy->mphase_cal_phase_id > 0)
3255                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3256
3257         do_rssi_cal = false;
3258         if (phy->rev >= 3) {
3259                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3260                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3261                 else
3262                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3263
3264                 if (do_rssi_cal)
3265                         b43_nphy_rssi_cal(dev);
3266                 else
3267                         b43_nphy_restore_rssi_cal(dev);
3268         } else {
3269                 b43_nphy_rssi_cal(dev);
3270         }
3271
3272         if (!((nphy->measure_hold & 0x6) != 0)) {
3273                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3274                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3275                 else
3276                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3277
3278                 if (nphy->mute)
3279                         do_cal = false;
3280
3281                 if (do_cal) {
3282                         target = b43_nphy_get_tx_gains(dev);
3283
3284                         if (nphy->antsel_type == 2)
3285                                 b43_nphy_superswitch_init(dev, true);
3286                         if (nphy->perical != 2) {
3287                                 b43_nphy_rssi_cal(dev);
3288                                 if (phy->rev >= 3) {
3289                                         nphy->cal_orig_pwr_idx[0] =
3290                                             nphy->txpwrindex[0].index_internal;
3291                                         nphy->cal_orig_pwr_idx[1] =
3292                                             nphy->txpwrindex[1].index_internal;
3293                                         /* TODO N PHY Pre Calibrate TX Gain */
3294                                         target = b43_nphy_get_tx_gains(dev);
3295                                 }
3296                         }
3297                 }
3298         }
3299
3300         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3301                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3302                         b43_nphy_save_cal(dev);
3303                 else if (nphy->mphase_cal_phase_id == 0)
3304                         ;/* N PHY Periodic Calibration with argument 3 */
3305         } else {
3306                 b43_nphy_restore_cal(dev);
3307         }
3308
3309         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3310         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3311         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3312         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3313         if (phy->rev >= 3 && phy->rev <= 6)
3314                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3315         b43_nphy_tx_lp_fbw(dev);
3316         if (phy->rev >= 3)
3317                 b43_nphy_spur_workaround(dev);
3318
3319         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3320         return 0;
3321 }
3322
3323 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3324 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3325                                 const struct b43_phy_n_sfo_cfg *e,
3326                                 struct ieee80211_channel *new_channel)
3327 {
3328         struct b43_phy *phy = &dev->phy;
3329         struct b43_phy_n *nphy = dev->phy.n;
3330
3331         u16 old_band_5ghz;
3332         u32 tmp32;
3333
3334         old_band_5ghz =
3335                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3336         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3337                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3338                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3339                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3340                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3341                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3342         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3343                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3344                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3345                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3346                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3347                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3348         }
3349
3350         b43_chantab_phy_upload(dev, e);
3351
3352         if (new_channel->hw_value == 14) {
3353                 b43_nphy_classifier(dev, 2, 0);
3354                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3355         } else {
3356                 b43_nphy_classifier(dev, 2, 2);
3357                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3358                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3359         }
3360
3361         if (nphy->txpwrctrl)
3362                 b43_nphy_tx_power_fix(dev);
3363
3364         if (dev->phy.rev < 3)
3365                 b43_nphy_adjust_lna_gain_table(dev);
3366
3367         b43_nphy_tx_lp_fbw(dev);
3368
3369         if (dev->phy.rev >= 3 && 0) {
3370                 /* TODO */
3371         }
3372
3373         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3374
3375         if (phy->rev >= 3)
3376                 b43_nphy_spur_workaround(dev);
3377 }
3378
3379 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3380 static int b43_nphy_set_channel(struct b43_wldev *dev,
3381                                 struct ieee80211_channel *channel,
3382                                 enum nl80211_channel_type channel_type)
3383 {
3384         struct b43_phy *phy = &dev->phy;
3385         struct b43_phy_n *nphy = dev->phy.n;
3386
3387         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3388         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3389
3390         u8 tmp;
3391
3392         if (dev->phy.rev >= 3) {
3393                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3394                                                         channel->center_freq);
3395                 tabent_r3 = NULL;
3396                 if (!tabent_r3)
3397                         return -ESRCH;
3398         } else {
3399                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3400                                                         channel->hw_value);
3401                 if (!tabent_r2)
3402                         return -ESRCH;
3403         }
3404
3405         /* Channel is set later in common code, but we need to set it on our
3406            own to let this function's subcalls work properly. */
3407         phy->channel = channel->hw_value;
3408         phy->channel_freq = channel->center_freq;
3409
3410         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3411                 b43_channel_type_is_40mhz(channel_type))
3412                 ; /* TODO: BMAC BW Set (channel_type) */
3413
3414         if (channel_type == NL80211_CHAN_HT40PLUS)
3415                 b43_phy_set(dev, B43_NPHY_RXCTL,
3416                                 B43_NPHY_RXCTL_BSELU20);
3417         else if (channel_type == NL80211_CHAN_HT40MINUS)
3418                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3419                                 ~B43_NPHY_RXCTL_BSELU20);
3420
3421         if (dev->phy.rev >= 3) {
3422                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3423                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3424                 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3425                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3426         } else {
3427                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3428                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3429                 b43_radio_2055_setup(dev, tabent_r2);
3430                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3431         }
3432
3433         return 0;
3434 }
3435
3436 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3437 {
3438         struct b43_phy_n *nphy;
3439
3440         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3441         if (!nphy)
3442                 return -ENOMEM;
3443         dev->phy.n = nphy;
3444
3445         return 0;
3446 }
3447
3448 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3449 {
3450         struct b43_phy *phy = &dev->phy;
3451         struct b43_phy_n *nphy = phy->n;
3452
3453         memset(nphy, 0, sizeof(*nphy));
3454
3455         //TODO init struct b43_phy_n
3456 }
3457
3458 static void b43_nphy_op_free(struct b43_wldev *dev)
3459 {
3460         struct b43_phy *phy = &dev->phy;
3461         struct b43_phy_n *nphy = phy->n;
3462
3463         kfree(nphy);
3464         phy->n = NULL;
3465 }
3466
3467 static int b43_nphy_op_init(struct b43_wldev *dev)
3468 {
3469         return b43_phy_initn(dev);
3470 }
3471
3472 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3473 {
3474 #if B43_DEBUG
3475         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3476                 /* OFDM registers are onnly available on A/G-PHYs */
3477                 b43err(dev->wl, "Invalid OFDM PHY access at "
3478                        "0x%04X on N-PHY\n", offset);
3479                 dump_stack();
3480         }
3481         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3482                 /* Ext-G registers are only available on G-PHYs */
3483                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3484                        "0x%04X on N-PHY\n", offset);
3485                 dump_stack();
3486         }
3487 #endif /* B43_DEBUG */
3488 }
3489
3490 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3491 {
3492         check_phyreg(dev, reg);
3493         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3494         return b43_read16(dev, B43_MMIO_PHY_DATA);
3495 }
3496
3497 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3498 {
3499         check_phyreg(dev, reg);
3500         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3501         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3502 }
3503
3504 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3505 {
3506         /* Register 1 is a 32-bit register. */
3507         B43_WARN_ON(reg == 1);
3508         /* N-PHY needs 0x100 for read access */
3509         reg |= 0x100;
3510
3511         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3512         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3513 }
3514
3515 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3516 {
3517         /* Register 1 is a 32-bit register. */
3518         B43_WARN_ON(reg == 1);
3519
3520         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3521         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3522 }
3523
3524 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3525 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3526                                         bool blocked)
3527 {
3528         struct b43_phy_n *nphy = dev->phy.n;
3529
3530         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3531                 b43err(dev->wl, "MAC not suspended\n");
3532
3533         if (blocked) {
3534                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3535                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3536                 if (dev->phy.rev >= 3) {
3537                         b43_radio_mask(dev, 0x09, ~0x2);
3538
3539                         b43_radio_write(dev, 0x204D, 0);
3540                         b43_radio_write(dev, 0x2053, 0);
3541                         b43_radio_write(dev, 0x2058, 0);
3542                         b43_radio_write(dev, 0x205E, 0);
3543                         b43_radio_mask(dev, 0x2062, ~0xF0);
3544                         b43_radio_write(dev, 0x2064, 0);
3545
3546                         b43_radio_write(dev, 0x304D, 0);
3547                         b43_radio_write(dev, 0x3053, 0);
3548                         b43_radio_write(dev, 0x3058, 0);
3549                         b43_radio_write(dev, 0x305E, 0);
3550                         b43_radio_mask(dev, 0x3062, ~0xF0);
3551                         b43_radio_write(dev, 0x3064, 0);
3552                 }
3553         } else {
3554                 if (dev->phy.rev >= 3) {
3555                         b43_radio_init2056(dev);
3556                         b43_switch_channel(dev, dev->phy.channel);
3557                 } else {
3558                         b43_radio_init2055(dev);
3559                 }
3560         }
3561 }
3562
3563 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3564 {
3565         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3566                       on ? 0 : 0x7FFF);
3567 }
3568
3569 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3570                                       unsigned int new_channel)
3571 {
3572         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3573         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
3574
3575         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3576                 if ((new_channel < 1) || (new_channel > 14))
3577                         return -EINVAL;
3578         } else {
3579                 if (new_channel > 200)
3580                         return -EINVAL;
3581         }
3582
3583         return b43_nphy_set_channel(dev, channel, channel_type);
3584 }
3585
3586 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3587 {
3588         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3589                 return 1;
3590         return 36;
3591 }
3592
3593 const struct b43_phy_operations b43_phyops_n = {
3594         .allocate               = b43_nphy_op_allocate,
3595         .free                   = b43_nphy_op_free,
3596         .prepare_structs        = b43_nphy_op_prepare_structs,
3597         .init                   = b43_nphy_op_init,
3598         .phy_read               = b43_nphy_op_read,
3599         .phy_write              = b43_nphy_op_write,
3600         .radio_read             = b43_nphy_op_radio_read,
3601         .radio_write            = b43_nphy_op_radio_write,
3602         .software_rfkill        = b43_nphy_op_software_rfkill,
3603         .switch_analog          = b43_nphy_op_switch_analog,
3604         .switch_channel         = b43_nphy_op_switch_channel,
3605         .get_default_chan       = b43_nphy_op_get_default_chan,
3606         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3607         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3608 };