drivers/net/wireless/b43/phy_lp.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g LP-PHY driver
   5
   6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "b43.h"
  26 #include "main.h"
  27 #include "phy_lp.h"
  28 #include "phy_common.h"
  29 #include "tables_lpphy.h"
  30
  31
  32 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
  33 {
  34         struct b43_phy_lp *lpphy;
  35
  36         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
  37         if (!lpphy)
  38                 return -ENOMEM;
  39         dev->phy.lp = lpphy;
  40
  41         return 0;
  42 }
  43
  44 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
  45 {
  46         struct b43_phy *phy = &dev->phy;
  47         struct b43_phy_lp *lpphy = phy->lp;
  48
  49         memset(lpphy, 0, sizeof(*lpphy));
  50
  51         //TODO
  52 }
  53
  54 static void b43_lpphy_op_free(struct b43_wldev *dev)
  55 {
  56         struct b43_phy_lp *lpphy = dev->phy.lp;
  57
  58         kfree(lpphy);
  59         dev->phy.lp = NULL;
  60 }
  61
  62 static void lpphy_adjust_gain_table(struct b43_wldev *dev)
  63 {
  64         struct b43_phy_lp *lpphy = dev->phy.lp;
  65         u32 freq = dev->wl->hw->conf.channel->center_freq;
  66         u16 temp[3];
  67         u16 isolation;
  68
  69         B43_WARN_ON(dev->phy.rev >= 2);
  70
  71         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  72                 isolation = lpphy->tx_isolation_med_band;
  73         else if (freq <= 5320)
  74                 isolation = lpphy->tx_isolation_low_band;
  75         else if (freq <= 5700)
  76                 isolation = lpphy->tx_isolation_med_band;
  77         else
  78                 isolation = lpphy->tx_isolation_hi_band;
  79
  80         temp[0] = ((isolation - 26) / 12) << 12;
  81         temp[1] = temp[0] + 0x1000;
  82         temp[2] = temp[0] + 0x2000;
  83
  84         b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
  85         b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
  86 }
  87
  88 static void lpphy_table_init(struct b43_wldev *dev)
  89 {
  90         if (dev->phy.rev < 2)
  91                 lpphy_rev0_1_table_init(dev);
  92         else
  93                 lpphy_rev2plus_table_init(dev);
  94
  95         lpphy_init_tx_gain_table(dev);
  96
  97         if (dev->phy.rev < 2)
  98                 lpphy_adjust_gain_table(dev);
  99 }
 100
 101 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
 102 {
 103         struct ssb_bus *bus = dev->dev->bus;
 104         u16 tmp, tmp2;
 105
 106         if (dev->phy.rev == 1 &&
 107            (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
 108                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
 109                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
 110                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
 111                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
 112                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
 113                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
 114                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
 115                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
 116                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
 117                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
 118                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
 119                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
 120                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
 121                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
 122                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
 123                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
 124         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
 125                   (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
 126                   (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
 127                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
 128                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
 129                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
 130                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
 131                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
 132                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
 133                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
 134                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
 135         } else if (dev->phy.rev == 1 ||
 136                   (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
 137                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
 138                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
 139                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
 140                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
 141                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
 142                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
 143                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
 144                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
 145         } else {
 146                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
 147                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
 148                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
 149                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
 150                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
 151                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
 152                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
 153                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
 154         }
 155         if (dev->phy.rev == 1) {
 156                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
 157                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
 158                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
 159                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
 160         }
 161         if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
 162             (bus->chip_id == 0x5354) &&
 163             (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
 164                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
 165                 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
 166                 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
 167                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
 168         }
 169         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 170                 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
 171                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
 172                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
 173                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
 174                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
 175                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
 176                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
 177                 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
 178         } else { /* 5GHz */
 179                 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
 180                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
 181         }
 182         if (dev->phy.rev == 1) {
 183                 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
 184                 tmp2 = (tmp & 0x03E0) >> 5;
 185                 tmp2 |= tmp << 5;
 186                 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
 187                 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
 188                 tmp2 = (tmp & 0x1F00) >> 8;
 189                 tmp2 |= tmp << 5;
 190                 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
 191                 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
 192                 tmp2 = tmp & 0x00FF;
 193                 tmp2 |= tmp << 8;
 194                 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
 195         }
 196 }
 197
 198 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
 199 {
 200         struct ssb_bus *bus = dev->dev->bus;
 201         struct b43_phy_lp *lpphy = dev->phy.lp;
 202
 203         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
 204         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
 205         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
 206         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
 207         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
 208         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
 209         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
 210         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
 211         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
 212         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x78);
 213         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
 214         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
 215         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
 216         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
 217         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
 218         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
 219         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
 220         b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
 221         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
 222         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
 223         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
 224         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
 225         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
 226         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
 227         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
 228         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
 229         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
 230         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
 231         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
 232         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
 233                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
 234                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
 235         } else {
 236                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
 237                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
 238         }
 239         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
 240         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 241         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
 242         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
 243         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
 244         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 245         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
 246         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
 247         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
 248         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
 249
 250         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
 251         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
 252
 253         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 254                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
 255                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
 256                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
 257                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
 258                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
 259         } else /* 5GHz */
 260                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
 261
 262         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
 263         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
 264         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
 265         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
 266         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
 267         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
 268         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
 269                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
 270                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
 271 }
 272
 273 static void lpphy_baseband_init(struct b43_wldev *dev)
 274 {
 275         lpphy_table_init(dev);
 276         if (dev->phy.rev >= 2)
 277                 lpphy_baseband_rev2plus_init(dev);
 278         else
 279                 lpphy_baseband_rev0_1_init(dev);
 280 }
 281
 282 struct b2062_freqdata {
 283         u16 freq;
 284         u8 data[6];
 285 };
 286
 287 /* Initialize the 2062 radio. */
 288 static void lpphy_2062_init(struct b43_wldev *dev)
 289 {
 290         struct ssb_bus *bus = dev->dev->bus;
 291         u32 crystalfreq, pdiv, tmp, ref;
 292         unsigned int i;
 293         const struct b2062_freqdata *fd = NULL;
 294
 295         static const struct b2062_freqdata freqdata_tab[] = {
 296                 { .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
 297                                  .data[3] =  6, .data[4] = 10, .data[5] =  6, },
 298                 { .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
 299                                  .data[3] =  4, .data[4] = 11, .data[5] =  7, },
 300                 { .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 301                                  .data[3] =  3, .data[4] = 12, .data[5] =  7, },
 302                 { .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 303                                  .data[3] =  3, .data[4] = 13, .data[5] =  8, },
 304                 { .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
 305                                  .data[3] =  2, .data[4] = 14, .data[5] =  8, },
 306                 { .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
 307                                  .data[3] =  1, .data[4] = 14, .data[5] =  9, },
 308         };
 309
 310         b2062_upload_init_table(dev);
 311
 312         b43_radio_write(dev, B2062_N_TX_CTL3, 0);
 313         b43_radio_write(dev, B2062_N_TX_CTL4, 0);
 314         b43_radio_write(dev, B2062_N_TX_CTL5, 0);
 315         b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
 316         b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
 317         b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
 318         b43_radio_write(dev, B2062_N_CALIB_TS, 0);
 319         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 320                 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
 321         else
 322                 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
 323
 324         /* Get the crystal freq, in Hz. */
 325         crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
 326
 327         B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
 328         B43_WARN_ON(crystalfreq == 0);
 329
 330         if (crystalfreq >= 30000000) {
 331                 pdiv = 1;
 332                 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
 333         } else {
 334                 pdiv = 2;
 335                 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
 336         }
 337
 338         tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
 339         tmp = (tmp - 1) & 0xFF;
 340         b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
 341
 342         tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
 343         tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
 344         b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
 345
 346         ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
 347         ref &= 0xFFFF;
 348         for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
 349                 if (ref < freqdata_tab[i].freq) {
 350                         fd = &freqdata_tab[i];
 351                         break;
 352                 }
 353         }
 354         if (!fd)
 355                 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
 356         b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
 357                fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
 358
 359         b43_radio_write(dev, B2062_S_RFPLL_CTL8,
 360                         ((u16)(fd->data[1]) << 4) | fd->data[0]);
 361         b43_radio_write(dev, B2062_S_RFPLL_CTL9,
 362                         ((u16)(fd->data[3]) << 4) | fd->data[2]);
 363         b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
 364         b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
 365 }
 366
 367 /* Initialize the 2063 radio. */
 368 static void lpphy_2063_init(struct b43_wldev *dev)
 369 {
 370         b2063_upload_init_table(dev);
 371         b43_radio_write(dev, B2063_LOGEN_SP5, 0);
 372         b43_radio_set(dev, B2063_COMM8, 0x38);
 373         b43_radio_write(dev, B2063_REG_SP1, 0x56);
 374         b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
 375         b43_radio_write(dev, B2063_PA_SP7, 0);
 376         b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
 377         b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
 378         b43_radio_write(dev, B2063_PA_SP3, 0xa0);
 379         b43_radio_write(dev, B2063_PA_SP4, 0xa0);
 380         b43_radio_write(dev, B2063_PA_SP2, 0x18);
 381 }
 382
 383 struct lpphy_stx_table_entry {
 384         u16 phy_offset;
 385         u16 phy_shift;
 386         u16 rf_addr;
 387         u16 rf_shift;
 388         u16 mask;
 389 };
 390
 391 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
 392         { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
 393         { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
 394         { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
 395         { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
 396         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
 397         { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
 398         { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
 399         { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
 400         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
 401         { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
 402         { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
 403         { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
 404         { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
 405         { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
 406         { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
 407         { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
 408         { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
 409         { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
 410         { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
 411         { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
 412         { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
 413         { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
 414         { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
 415         { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
 416         { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
 417         { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
 418         { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
 419         { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
 420         { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
 421 };
 422
 423 static void lpphy_sync_stx(struct b43_wldev *dev)
 424 {
 425         const struct lpphy_stx_table_entry *e;
 426         unsigned int i;
 427         u16 tmp;
 428
 429         for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
 430                 e = &lpphy_stx_table[i];
 431                 tmp = b43_radio_read(dev, e->rf_addr);
 432                 tmp >>= e->rf_shift;
 433                 tmp <<= e->phy_shift;
 434                 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
 435                                 e->mask << e->phy_shift, tmp);
 436         }
 437 }
 438
 439 static void lpphy_radio_init(struct b43_wldev *dev)
 440 {
 441         /* The radio is attached through the 4wire bus. */
 442         b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
 443         udelay(1);
 444         b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
 445         udelay(1);
 446
 447         if (dev->phy.rev < 2) {
 448                 lpphy_2062_init(dev);
 449         } else {
 450                 lpphy_2063_init(dev);
 451                 lpphy_sync_stx(dev);
 452                 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
 453                 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
 454                 if (dev->dev->bus->chip_id == 0x4325) {
 455                         // TODO SSB PMU recalibration
 456                 }
 457         }
 458 }
 459
 460 /* Read the TX power control mode from hardware. */
 461 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
 462 {
 463         struct b43_phy_lp *lpphy = dev->phy.lp;
 464         u16 ctl;
 465
 466         ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
 467         switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
 468         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
 469                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
 470                 break;
 471         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
 472                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
 473                 break;
 474         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
 475                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
 476                 break;
 477         default:
 478                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
 479                 B43_WARN_ON(1);
 480                 break;
 481         }
 482 }
 483
 484 /* Set the TX power control mode in hardware. */
 485 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
 486 {
 487         struct b43_phy_lp *lpphy = dev->phy.lp;
 488         u16 ctl;
 489
 490         switch (lpphy->txpctl_mode) {
 491         case B43_LPPHY_TXPCTL_OFF:
 492                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
 493                 break;
 494         case B43_LPPHY_TXPCTL_HW:
 495                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
 496                 break;
 497         case B43_LPPHY_TXPCTL_SW:
 498                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
 499                 break;
 500         default:
 501                 ctl = 0;
 502                 B43_WARN_ON(1);
 503         }
 504         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
 505                         (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
 506 }
 507
 508 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
 509                                        enum b43_lpphy_txpctl_mode mode)
 510 {
 511         struct b43_phy_lp *lpphy = dev->phy.lp;
 512         enum b43_lpphy_txpctl_mode oldmode;
 513
 514         oldmode = lpphy->txpctl_mode;
 515         lpphy_read_tx_pctl_mode_from_hardware(dev);
 516         if (lpphy->txpctl_mode == mode)
 517                 return;
 518         lpphy->txpctl_mode = mode;
 519
 520         if (oldmode == B43_LPPHY_TXPCTL_HW) {
 521                 //TODO Update TX Power NPT
 522                 //TODO Clear all TX Power offsets
 523         } else {
 524                 if (mode == B43_LPPHY_TXPCTL_HW) {
 525                         //TODO Recalculate target TX power
 526                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
 527                                         0xFF80, lpphy->tssi_idx);
 528                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
 529                                         0x8FFF, ((u16)lpphy->tssi_npt << 16));
 530                         //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
 531                         //TODO Disable TX gain override
 532                         lpphy->tx_pwr_idx_over = -1;
 533                 }
 534         }
 535         if (dev->phy.rev >= 2) {
 536                 if (mode == B43_LPPHY_TXPCTL_HW)
 537                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
 538                 else
 539                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
 540         }
 541         lpphy_write_tx_pctl_mode_to_hardware(dev);
 542 }
 543
 544 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
 545 {
 546         struct b43_phy_lp *lpphy = dev->phy.lp;
 547
 548         lpphy->tx_pwr_idx_over = index;
 549         if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
 550                 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
 551
 552         //TODO
 553 }
 554
 555 static void lpphy_btcoex_override(struct b43_wldev *dev)
 556 {
 557         b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
 558         b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
 559 }
 560
 561 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
 562 {
 563         struct b43_phy_lp *lpphy = dev->phy.lp;
 564         u32 *saved_tab;
 565         const unsigned int saved_tab_size = 256;
 566         enum b43_lpphy_txpctl_mode txpctl_mode;
 567         s8 tx_pwr_idx_over;
 568         u16 tssi_npt, tssi_idx;
 569
 570         saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
 571         if (!saved_tab) {
 572                 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
 573                 return;
 574         }
 575
 576         lpphy_read_tx_pctl_mode_from_hardware(dev);
 577         txpctl_mode = lpphy->txpctl_mode;
 578         tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
 579         tssi_npt = lpphy->tssi_npt;
 580         tssi_idx = lpphy->tssi_idx;
 581
 582         if (dev->phy.rev < 2) {
 583                 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
 584                                     saved_tab_size, saved_tab);
 585         } else {
 586                 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
 587                                     saved_tab_size, saved_tab);
 588         }
 589         //TODO
 590
 591         kfree(saved_tab);
 592 }
 593
 594 static void lpphy_calibration(struct b43_wldev *dev)
 595 {
 596         struct b43_phy_lp *lpphy = dev->phy.lp;
 597         enum b43_lpphy_txpctl_mode saved_pctl_mode;
 598
 599         b43_mac_suspend(dev);
 600
 601         lpphy_btcoex_override(dev);
 602         lpphy_read_tx_pctl_mode_from_hardware(dev);
 603         saved_pctl_mode = lpphy->txpctl_mode;
 604         lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
 605         //TODO Perform transmit power table I/Q LO calibration
 606         if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
 607                 lpphy_pr41573_workaround(dev);
 608         //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
 609         lpphy_set_tx_power_control(dev, saved_pctl_mode);
 610         //TODO Perform I/Q calibration with a single control value set
 611
 612         b43_mac_enable(dev);
 613 }
 614
 615 /* Initialize TX power control */
 616 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
 617 {
 618         if (0/*FIXME HWPCTL capable */) {
 619                 //TODO
 620         } else { /* This device is only software TX power control capable. */
 621                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 622                         //TODO
 623                 } else {
 624                         //TODO
 625                 }
 626                 //TODO set BB multiplier to 0x0096
 627         }
 628 }
 629
 630 static int b43_lpphy_op_init(struct b43_wldev *dev)
 631 {
 632         /* TODO: band SPROM */
 633         lpphy_baseband_init(dev);
 634         lpphy_radio_init(dev);
 635         //TODO calibrate RC
 636         //TODO set channel
 637         lpphy_tx_pctl_init(dev);
 638         lpphy_calibration(dev);
 639         //TODO ACI init
 640
 641         return 0;
 642 }
 643
 644 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
 645 {
 646         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 647         return b43_read16(dev, B43_MMIO_PHY_DATA);
 648 }
 649
 650 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 651 {
 652         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 653         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 654 }
 655
 656 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 657 {
 658         /* Register 1 is a 32-bit register. */
 659         B43_WARN_ON(reg == 1);
 660         /* LP-PHY needs a special bit set for read access */
 661         if (dev->phy.rev < 2) {
 662                 if (reg != 0x4001)
 663                         reg |= 0x100;
 664         } else
 665                 reg |= 0x200;
 666
 667         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 668         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 669 }
 670
 671 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 672 {
 673         /* Register 1 is a 32-bit register. */
 674         B43_WARN_ON(reg == 1);
 675
 676         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 677         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 678 }
 679
 680 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
 681                                          bool blocked)
 682 {
 683         //TODO
 684 }
 685
 686 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
 687                                        unsigned int new_channel)
 688 {
 689         //TODO
 690         return 0;
 691 }
 692
 693 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
 694 {
 695         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 696                 return 1;
 697         return 36;
 698 }
 699
 700 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 701 {
 702         //TODO
 703 }
 704
 705 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
 706 {
 707         //TODO
 708 }
 709
 710 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
 711                                                          bool ignore_tssi)
 712 {
 713         //TODO
 714         return B43_TXPWR_RES_DONE;
 715 }
 716
 717 const struct b43_phy_operations b43_phyops_lp = {
 718         .allocate               = b43_lpphy_op_allocate,
 719         .free                   = b43_lpphy_op_free,
 720         .prepare_structs        = b43_lpphy_op_prepare_structs,
 721         .init                   = b43_lpphy_op_init,
 722         .phy_read               = b43_lpphy_op_read,
 723         .phy_write              = b43_lpphy_op_write,
 724         .radio_read             = b43_lpphy_op_radio_read,
 725         .radio_write            = b43_lpphy_op_radio_write,
 726         .software_rfkill        = b43_lpphy_op_software_rfkill,
 727         .switch_analog          = b43_phyop_switch_analog_generic,
 728         .switch_channel         = b43_lpphy_op_switch_channel,
 729         .get_default_chan       = b43_lpphy_op_get_default_chan,
 730         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
 731         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
 732         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
 733 };