drivers/net/wireless/b43/phy_lp.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g LP-PHY driver
   5
   6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "b43.h"
  26 #include "main.h"
  27 #include "phy_lp.h"
  28 #include "phy_common.h"
  29 #include "tables_lpphy.h"
  30
  31
  32 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
  33 {
  34         struct b43_phy_lp *lpphy;
  35
  36         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
  37         if (!lpphy)
  38                 return -ENOMEM;
  39         dev->phy.lp = lpphy;
  40
  41         return 0;
  42 }
  43
  44 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
  45 {
  46         struct b43_phy *phy = &dev->phy;
  47         struct b43_phy_lp *lpphy = phy->lp;
  48
  49         memset(lpphy, 0, sizeof(*lpphy));
  50
  51         //TODO
  52 }
  53
  54 static void b43_lpphy_op_free(struct b43_wldev *dev)
  55 {
  56         struct b43_phy_lp *lpphy = dev->phy.lp;
  57
  58         kfree(lpphy);
  59         dev->phy.lp = NULL;
  60 }
  61
  62 static void lpphy_adjust_gain_table(struct b43_wldev *dev)
  63 {
  64         struct b43_phy_lp *lpphy = dev->phy.lp;
  65         u32 freq = dev->wl->hw->conf.channel->center_freq;
  66         u16 temp[3];
  67         u16 isolation;
  68
  69         B43_WARN_ON(dev->phy.rev >= 2);
  70
  71         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
  72                 isolation = lpphy->tx_isolation_med_band;
  73         else if (freq <= 5320)
  74                 isolation = lpphy->tx_isolation_low_band;
  75         else if (freq <= 5700)
  76                 isolation = lpphy->tx_isolation_med_band;
  77         else
  78                 isolation = lpphy->tx_isolation_hi_band;
  79
  80         temp[0] = ((isolation - 26) / 12) << 12;
  81         temp[1] = temp[0] + 0x1000;
  82         temp[2] = temp[0] + 0x2000;
  83
  84         b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
  85         b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
  86 }
  87
  88 static void lpphy_table_init(struct b43_wldev *dev)
  89 {
  90         if (dev->phy.rev < 2)
  91                 lpphy_rev0_1_table_init(dev);
  92         else
  93                 lpphy_rev2plus_table_init(dev);
  94
  95         lpphy_init_tx_gain_table(dev);
  96
  97         if (dev->phy.rev < 2)
  98                 lpphy_adjust_gain_table(dev);
  99 }
 100
 101 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
 102 {
 103         struct ssb_bus *bus = dev->dev->bus;
 104         u16 tmp, tmp2;
 105
 106         if (dev->phy.rev == 1 &&
 107            (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
 108                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
 109                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
 110                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
 111                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
 112                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
 113                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
 114                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
 115                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
 116                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
 117                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
 118                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
 119                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
 120                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
 121                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
 122                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
 123                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
 124         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
 125                   (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
 126                   (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
 127                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
 128                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
 129                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
 130                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
 131                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
 132                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
 133                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
 134                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
 135         } else if (dev->phy.rev == 1 ||
 136                   (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
 137                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
 138                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
 139                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
 140                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
 141                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
 142                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
 143                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
 144                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
 145         } else {
 146                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
 147                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
 148                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
 149                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
 150                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
 151                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
 152                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
 153                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
 154         }
 155         if (dev->phy.rev == 1) {
 156                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
 157                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
 158                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
 159                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
 160         }
 161         if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
 162             (bus->chip_id == 0x5354) &&
 163             (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
 164                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
 165                 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
 166                 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
 167                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
 168         }
 169         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 170                 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
 171                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
 172                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
 173                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
 174                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
 175                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
 176                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
 177                 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
 178         } else { /* 5GHz */
 179                 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
 180                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
 181         }
 182         if (dev->phy.rev == 1) {
 183                 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
 184                 tmp2 = (tmp & 0x03E0) >> 5;
 185                 tmp2 |= tmp << 5;
 186                 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
 187                 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
 188                 tmp2 = (tmp & 0x1F00) >> 8;
 189                 tmp2 |= tmp << 5;
 190                 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
 191                 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
 192                 tmp2 = tmp & 0x00FF;
 193                 tmp2 |= tmp << 8;
 194                 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
 195         }
 196 }
 197
 198 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
 199 {
 200         static const u16 addr[] = {
 201                 B43_PHY_OFDM(0xC1),
 202                 B43_PHY_OFDM(0xC2),
 203                 B43_PHY_OFDM(0xC3),
 204                 B43_PHY_OFDM(0xC4),
 205                 B43_PHY_OFDM(0xC5),
 206                 B43_PHY_OFDM(0xC6),
 207                 B43_PHY_OFDM(0xC7),
 208                 B43_PHY_OFDM(0xC8),
 209                 B43_PHY_OFDM(0xCF),
 210         };
 211
 212         static const u16 coefs[] = {
 213                 0xDE5E, 0xE832, 0xE331, 0x4D26,
 214                 0x0026, 0x1420, 0x0020, 0xFE08,
 215                 0x0008,
 216         };
 217
 218         struct b43_phy_lp *lpphy = dev->phy.lp;
 219         int i;
 220
 221         for (i = 0; i < ARRAY_SIZE(addr); i++) {
 222                 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
 223                 b43_phy_write(dev, addr[i], coefs[i]);
 224         }
 225 }
 226
 227 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
 228 {
 229         static const u16 addr[] = {
 230                 B43_PHY_OFDM(0xC1),
 231                 B43_PHY_OFDM(0xC2),
 232                 B43_PHY_OFDM(0xC3),
 233                 B43_PHY_OFDM(0xC4),
 234                 B43_PHY_OFDM(0xC5),
 235                 B43_PHY_OFDM(0xC6),
 236                 B43_PHY_OFDM(0xC7),
 237                 B43_PHY_OFDM(0xC8),
 238                 B43_PHY_OFDM(0xCF),
 239         };
 240
 241         struct b43_phy_lp *lpphy = dev->phy.lp;
 242         int i;
 243
 244         for (i = 0; i < ARRAY_SIZE(addr); i++)
 245                 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
 246 }
 247
 248 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
 249 {
 250         struct ssb_bus *bus = dev->dev->bus;
 251         struct b43_phy_lp *lpphy = dev->phy.lp;
 252
 253         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
 254         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
 255         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
 256         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
 257         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
 258         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
 259         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
 260         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
 261         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
 262         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
 263         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
 264         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
 265         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
 266         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
 267         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
 268         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
 269         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
 270         if (bus->boardinfo.rev >= 0x18) {
 271                 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
 272                 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
 273         } else {
 274                 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
 275         }
 276         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
 277         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
 278         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
 279         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
 280         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
 281         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
 282         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
 283         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
 284         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
 285         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
 286         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
 287         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
 288                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
 289                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
 290         } else {
 291                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
 292                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
 293         }
 294         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
 295         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 296         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
 297         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
 298         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
 299         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
 300         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
 301         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
 302         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
 303         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
 304
 305         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 1)) {
 306                 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
 307                 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
 308         }
 309
 310         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 311                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
 312                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
 313                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
 314                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
 315                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
 316         } else /* 5GHz */
 317                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
 318
 319         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
 320         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
 321         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
 322         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
 323         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
 324         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
 325         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
 326                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
 327                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
 328
 329         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
 330                 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
 331                 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
 332                 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
 333         }
 334
 335         lpphy_save_dig_flt_state(dev);
 336 }
 337
 338 static void lpphy_baseband_init(struct b43_wldev *dev)
 339 {
 340         lpphy_table_init(dev);
 341         if (dev->phy.rev >= 2)
 342                 lpphy_baseband_rev2plus_init(dev);
 343         else
 344                 lpphy_baseband_rev0_1_init(dev);
 345 }
 346
 347 struct b2062_freqdata {
 348         u16 freq;
 349         u8 data[6];
 350 };
 351
 352 /* Initialize the 2062 radio. */
 353 static void lpphy_2062_init(struct b43_wldev *dev)
 354 {
 355         struct ssb_bus *bus = dev->dev->bus;
 356         u32 crystalfreq, pdiv, tmp, ref;
 357         unsigned int i;
 358         const struct b2062_freqdata *fd = NULL;
 359
 360         static const struct b2062_freqdata freqdata_tab[] = {
 361                 { .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
 362                                  .data[3] =  6, .data[4] = 10, .data[5] =  6, },
 363                 { .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
 364                                  .data[3] =  4, .data[4] = 11, .data[5] =  7, },
 365                 { .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 366                                  .data[3] =  3, .data[4] = 12, .data[5] =  7, },
 367                 { .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
 368                                  .data[3] =  3, .data[4] = 13, .data[5] =  8, },
 369                 { .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
 370                                  .data[3] =  2, .data[4] = 14, .data[5] =  8, },
 371                 { .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
 372                                  .data[3] =  1, .data[4] = 14, .data[5] =  9, },
 373         };
 374
 375         b2062_upload_init_table(dev);
 376
 377         b43_radio_write(dev, B2062_N_TX_CTL3, 0);
 378         b43_radio_write(dev, B2062_N_TX_CTL4, 0);
 379         b43_radio_write(dev, B2062_N_TX_CTL5, 0);
 380         b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
 381         b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
 382         b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
 383         b43_radio_write(dev, B2062_N_CALIB_TS, 0);
 384         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 385                 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
 386         else
 387                 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
 388
 389         /* Get the crystal freq, in Hz. */
 390         crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
 391
 392         B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
 393         B43_WARN_ON(crystalfreq == 0);
 394
 395         if (crystalfreq >= 30000000) {
 396                 pdiv = 1;
 397                 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
 398         } else {
 399                 pdiv = 2;
 400                 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
 401         }
 402
 403         tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
 404         tmp = (tmp - 1) & 0xFF;
 405         b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
 406
 407         tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
 408         tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
 409         b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
 410
 411         ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
 412         ref &= 0xFFFF;
 413         for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
 414                 if (ref < freqdata_tab[i].freq) {
 415                         fd = &freqdata_tab[i];
 416                         break;
 417                 }
 418         }
 419         if (!fd)
 420                 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
 421         b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
 422                fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
 423
 424         b43_radio_write(dev, B2062_S_RFPLL_CTL8,
 425                         ((u16)(fd->data[1]) << 4) | fd->data[0]);
 426         b43_radio_write(dev, B2062_S_RFPLL_CTL9,
 427                         ((u16)(fd->data[3]) << 4) | fd->data[2]);
 428         b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
 429         b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
 430 }
 431
 432 /* Initialize the 2063 radio. */
 433 static void lpphy_2063_init(struct b43_wldev *dev)
 434 {
 435         b2063_upload_init_table(dev);
 436         b43_radio_write(dev, B2063_LOGEN_SP5, 0);
 437         b43_radio_set(dev, B2063_COMM8, 0x38);
 438         b43_radio_write(dev, B2063_REG_SP1, 0x56);
 439         b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
 440         b43_radio_write(dev, B2063_PA_SP7, 0);
 441         b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
 442         b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
 443         b43_radio_write(dev, B2063_PA_SP3, 0xa0);
 444         b43_radio_write(dev, B2063_PA_SP4, 0xa0);
 445         b43_radio_write(dev, B2063_PA_SP2, 0x18);
 446 }
 447
 448 struct lpphy_stx_table_entry {
 449         u16 phy_offset;
 450         u16 phy_shift;
 451         u16 rf_addr;
 452         u16 rf_shift;
 453         u16 mask;
 454 };
 455
 456 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
 457         { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
 458         { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
 459         { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
 460         { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
 461         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
 462         { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
 463         { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
 464         { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
 465         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
 466         { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
 467         { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
 468         { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
 469         { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
 470         { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
 471         { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
 472         { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
 473         { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
 474         { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
 475         { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
 476         { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
 477         { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
 478         { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
 479         { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
 480         { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
 481         { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
 482         { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
 483         { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
 484         { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
 485         { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
 486 };
 487
 488 static void lpphy_sync_stx(struct b43_wldev *dev)
 489 {
 490         const struct lpphy_stx_table_entry *e;
 491         unsigned int i;
 492         u16 tmp;
 493
 494         for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
 495                 e = &lpphy_stx_table[i];
 496                 tmp = b43_radio_read(dev, e->rf_addr);
 497                 tmp >>= e->rf_shift;
 498                 tmp <<= e->phy_shift;
 499                 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
 500                                 e->mask << e->phy_shift, tmp);
 501         }
 502 }
 503
 504 static void lpphy_radio_init(struct b43_wldev *dev)
 505 {
 506         /* The radio is attached through the 4wire bus. */
 507         b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
 508         udelay(1);
 509         b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
 510         udelay(1);
 511
 512         if (dev->phy.rev < 2) {
 513                 lpphy_2062_init(dev);
 514         } else {
 515                 lpphy_2063_init(dev);
 516                 lpphy_sync_stx(dev);
 517                 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
 518                 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
 519                 if (dev->dev->bus->chip_id == 0x4325) {
 520                         // TODO SSB PMU recalibration
 521                 }
 522         }
 523 }
 524
 525 /* Read the TX power control mode from hardware. */
 526 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
 527 {
 528         struct b43_phy_lp *lpphy = dev->phy.lp;
 529         u16 ctl;
 530
 531         ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
 532         switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
 533         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
 534                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
 535                 break;
 536         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
 537                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
 538                 break;
 539         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
 540                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
 541                 break;
 542         default:
 543                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
 544                 B43_WARN_ON(1);
 545                 break;
 546         }
 547 }
 548
 549 /* Set the TX power control mode in hardware. */
 550 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
 551 {
 552         struct b43_phy_lp *lpphy = dev->phy.lp;
 553         u16 ctl;
 554
 555         switch (lpphy->txpctl_mode) {
 556         case B43_LPPHY_TXPCTL_OFF:
 557                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
 558                 break;
 559         case B43_LPPHY_TXPCTL_HW:
 560                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
 561                 break;
 562         case B43_LPPHY_TXPCTL_SW:
 563                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
 564                 break;
 565         default:
 566                 ctl = 0;
 567                 B43_WARN_ON(1);
 568         }
 569         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
 570                         (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
 571 }
 572
 573 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
 574                                        enum b43_lpphy_txpctl_mode mode)
 575 {
 576         struct b43_phy_lp *lpphy = dev->phy.lp;
 577         enum b43_lpphy_txpctl_mode oldmode;
 578
 579         oldmode = lpphy->txpctl_mode;
 580         lpphy_read_tx_pctl_mode_from_hardware(dev);
 581         if (lpphy->txpctl_mode == mode)
 582                 return;
 583         lpphy->txpctl_mode = mode;
 584
 585         if (oldmode == B43_LPPHY_TXPCTL_HW) {
 586                 //TODO Update TX Power NPT
 587                 //TODO Clear all TX Power offsets
 588         } else {
 589                 if (mode == B43_LPPHY_TXPCTL_HW) {
 590                         //TODO Recalculate target TX power
 591                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
 592                                         0xFF80, lpphy->tssi_idx);
 593                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
 594                                         0x8FFF, ((u16)lpphy->tssi_npt << 16));
 595                         //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
 596                         //TODO Disable TX gain override
 597                         lpphy->tx_pwr_idx_over = -1;
 598                 }
 599         }
 600         if (dev->phy.rev >= 2) {
 601                 if (mode == B43_LPPHY_TXPCTL_HW)
 602                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
 603                 else
 604                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
 605         }
 606         lpphy_write_tx_pctl_mode_to_hardware(dev);
 607 }
 608
 609 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
 610 {
 611         struct b43_phy_lp *lpphy = dev->phy.lp;
 612
 613         lpphy->tx_pwr_idx_over = index;
 614         if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
 615                 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
 616
 617         //TODO
 618 }
 619
 620 static void lpphy_btcoex_override(struct b43_wldev *dev)
 621 {
 622         b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
 623         b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
 624 }
 625
 626 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
 627 {
 628         struct b43_phy_lp *lpphy = dev->phy.lp;
 629         u32 *saved_tab;
 630         const unsigned int saved_tab_size = 256;
 631         enum b43_lpphy_txpctl_mode txpctl_mode;
 632         s8 tx_pwr_idx_over;
 633         u16 tssi_npt, tssi_idx;
 634
 635         saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
 636         if (!saved_tab) {
 637                 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
 638                 return;
 639         }
 640
 641         lpphy_read_tx_pctl_mode_from_hardware(dev);
 642         txpctl_mode = lpphy->txpctl_mode;
 643         tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
 644         tssi_npt = lpphy->tssi_npt;
 645         tssi_idx = lpphy->tssi_idx;
 646
 647         if (dev->phy.rev < 2) {
 648                 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
 649                                     saved_tab_size, saved_tab);
 650         } else {
 651                 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
 652                                     saved_tab_size, saved_tab);
 653         }
 654         //TODO
 655
 656         kfree(saved_tab);
 657 }
 658
 659 static void lpphy_calibration(struct b43_wldev *dev)
 660 {
 661         struct b43_phy_lp *lpphy = dev->phy.lp;
 662         enum b43_lpphy_txpctl_mode saved_pctl_mode;
 663
 664         b43_mac_suspend(dev);
 665
 666         lpphy_btcoex_override(dev);
 667         lpphy_read_tx_pctl_mode_from_hardware(dev);
 668         saved_pctl_mode = lpphy->txpctl_mode;
 669         lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
 670         //TODO Perform transmit power table I/Q LO calibration
 671         if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
 672                 lpphy_pr41573_workaround(dev);
 673         //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
 674         lpphy_set_tx_power_control(dev, saved_pctl_mode);
 675         //TODO Perform I/Q calibration with a single control value set
 676
 677         b43_mac_enable(dev);
 678 }
 679
 680 /* Initialize TX power control */
 681 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
 682 {
 683         if (0/*FIXME HWPCTL capable */) {
 684                 //TODO
 685         } else { /* This device is only software TX power control capable. */
 686                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 687                         //TODO
 688                 } else {
 689                         //TODO
 690                 }
 691                 //TODO set BB multiplier to 0x0096
 692         }
 693 }
 694
 695 static int b43_lpphy_op_init(struct b43_wldev *dev)
 696 {
 697         /* TODO: band SPROM */
 698         lpphy_baseband_init(dev);
 699         lpphy_radio_init(dev);
 700         //TODO calibrate RC
 701         //TODO set channel
 702         lpphy_tx_pctl_init(dev);
 703         lpphy_calibration(dev);
 704         //TODO ACI init
 705
 706         return 0;
 707 }
 708
 709 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
 710 {
 711         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 712         return b43_read16(dev, B43_MMIO_PHY_DATA);
 713 }
 714
 715 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 716 {
 717         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 718         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 719 }
 720
 721 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 722 {
 723         /* Register 1 is a 32-bit register. */
 724         B43_WARN_ON(reg == 1);
 725         /* LP-PHY needs a special bit set for read access */
 726         if (dev->phy.rev < 2) {
 727                 if (reg != 0x4001)
 728                         reg |= 0x100;
 729         } else
 730                 reg |= 0x200;
 731
 732         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 733         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 734 }
 735
 736 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 737 {
 738         /* Register 1 is a 32-bit register. */
 739         B43_WARN_ON(reg == 1);
 740
 741         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 742         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 743 }
 744
 745 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
 746                                          bool blocked)
 747 {
 748         //TODO
 749 }
 750
 751 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
 752                                        unsigned int new_channel)
 753 {
 754         //TODO
 755         return 0;
 756 }
 757
 758 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
 759 {
 760         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 761                 return 1;
 762         return 36;
 763 }
 764
 765 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 766 {
 767         //TODO
 768 }
 769
 770 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
 771 {
 772         //TODO
 773 }
 774
 775 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
 776                                                          bool ignore_tssi)
 777 {
 778         //TODO
 779         return B43_TXPWR_RES_DONE;
 780 }
 781
 782 const struct b43_phy_operations b43_phyops_lp = {
 783         .allocate               = b43_lpphy_op_allocate,
 784         .free                   = b43_lpphy_op_free,
 785         .prepare_structs        = b43_lpphy_op_prepare_structs,
 786         .init                   = b43_lpphy_op_init,
 787         .phy_read               = b43_lpphy_op_read,
 788         .phy_write              = b43_lpphy_op_write,
 789         .radio_read             = b43_lpphy_op_radio_read,
 790         .radio_write            = b43_lpphy_op_radio_write,
 791         .software_rfkill        = b43_lpphy_op_software_rfkill,
 792         .switch_analog          = b43_phyop_switch_analog_generic,
 793         .switch_channel         = b43_lpphy_op_switch_channel,
 794         .get_default_chan       = b43_lpphy_op_get_default_chan,
 795         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
 796         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
 797         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
 798 };