drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   This program is free software; you can redistribute it and/or modify
   7   it under the terms of the GNU General Public License as published by
   8   the Free Software Foundation; either version 2 of the License, or
   9   (at your option) any later version.
  10
  11   This program is distributed in the hope that it will be useful,
  12   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14   GNU General Public License for more details.
  15
  16   You should have received a copy of the GNU General Public License
  17   along with this program; see the file COPYING.  If not, write to
  18   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  19   Boston, MA 02110-1301, USA.
  20
  21 */
  22
  23 #include <linux/slab.h>
  24
  25 #include "b43.h"
  26 #include "phy_ht.h"
  27 #include "tables_phy_ht.h"
  28 #include "radio_2059.h"
  29 #include "main.h"
  30
  31 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  32                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  33 {
  34         u8 i;
  35         u16 routing;
  36
  37         b43_radio_write(dev, 0x16, e->radio_syn16);
  38         b43_radio_write(dev, 0x17, e->radio_syn17);
  39         b43_radio_write(dev, 0x22, e->radio_syn22);
  40         b43_radio_write(dev, 0x25, e->radio_syn25);
  41         b43_radio_write(dev, 0x27, e->radio_syn27);
  42         b43_radio_write(dev, 0x28, e->radio_syn28);
  43         b43_radio_write(dev, 0x29, e->radio_syn29);
  44         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  45         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  46         b43_radio_write(dev, 0x37, e->radio_syn37);
  47         b43_radio_write(dev, 0x41, e->radio_syn41);
  48         b43_radio_write(dev, 0x43, e->radio_syn43);
  49         b43_radio_write(dev, 0x47, e->radio_syn47);
  50         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  51         b43_radio_write(dev, 0x58, e->radio_syn58);
  52         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  53         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  54         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  55         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  56         b43_radio_write(dev, 0x92, e->radio_syn92);
  57         b43_radio_write(dev, 0x98, e->radio_syn98);
  58
  59         for (i = 0; i < 2; i++) {
  60                 routing = i ? 0x800 : 0x400;
  61                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  62                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  63                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  64                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  65                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  66                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  67                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  68                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  69         }
  70
  71         udelay(50);
  72
  73         /* Calibration */
  74         b43_radio_mask(dev, 0x2b, ~0x1);
  75         b43_radio_mask(dev, 0x2e, ~0x4);
  76         b43_radio_set(dev, 0x2e, 0x4);
  77         b43_radio_set(dev, 0x2b, 0x1);
  78
  79         udelay(300);
  80 }
  81
  82 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
  83                                 const struct b43_phy_ht_channeltab_e_phy *e,
  84                                 struct ieee80211_channel *new_channel)
  85 {
  86         bool old_band_5ghz;
  87         u8 i;
  88
  89         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
  90         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
  91                 /* TODO */
  92         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
  93                 /* TODO */
  94         }
  95
  96         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
  97         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
  98         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
  99         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 100         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 101         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 102
 103         /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
 104
 105         /* TODO: separated function? */
 106         for (i = 0; i < 3; i++) {
 107                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 108
 109                 /* TODO: some op on PHY reg 0x908 */
 110
 111                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 112                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 113                                 tmp & 0xFF);
 114                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 115                                 tmp & 0xFF);
 116         }
 117
 118         b43_phy_write(dev, 0x017e, 0x3830);
 119 }
 120
 121 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 122                                   struct ieee80211_channel *channel,
 123                                   enum nl80211_channel_type channel_type)
 124 {
 125         struct b43_phy *phy = &dev->phy;
 126
 127         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 128
 129         if (phy->radio_ver == 0x2059) {
 130                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 131                                                         channel->center_freq);
 132                 if (!chent_r2059)
 133                         return -ESRCH;
 134         } else {
 135                 return -ESRCH;
 136         }
 137
 138         /* TODO: In case of N-PHY some bandwidth switching goes here */
 139
 140         if (phy->radio_ver == 0x2059) {
 141                 b43_radio_2059_channel_setup(dev, chent_r2059);
 142                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 143                                          channel);
 144         } else {
 145                 return -ESRCH;
 146         }
 147
 148         return 0;
 149 }
 150
 151 /**************************************************
 152  * Basic PHY ops.
 153  **************************************************/
 154
 155 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 156 {
 157         struct b43_phy_ht *phy_ht;
 158
 159         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 160         if (!phy_ht)
 161                 return -ENOMEM;
 162         dev->phy.ht = phy_ht;
 163
 164         return 0;
 165 }
 166
 167 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 168 {
 169         struct b43_phy *phy = &dev->phy;
 170         struct b43_phy_ht *phy_ht = phy->ht;
 171
 172         memset(phy_ht, 0, sizeof(*phy_ht));
 173 }
 174
 175 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 176 {
 177         struct b43_phy *phy = &dev->phy;
 178         struct b43_phy_ht *phy_ht = phy->ht;
 179
 180         kfree(phy_ht);
 181         phy->ht = NULL;
 182 }
 183
 184 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 185 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 186                                         bool blocked)
 187 {
 188         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 189                 b43err(dev->wl, "MAC not suspended\n");
 190
 191         if (blocked) {
 192                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 193         } else {
 194                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 195                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x1);
 196                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 197                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x2);
 198         }
 199 }
 200
 201 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 202 {
 203         if (on) {
 204                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd);
 205                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000);
 206                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd);
 207                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000);
 208                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd);
 209                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000);
 210         } else {
 211                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff);
 212                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd);
 213                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff);
 214                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd);
 215                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff);
 216                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd);
 217         }
 218 }
 219
 220 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 221                                         unsigned int new_channel)
 222 {
 223         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 224         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 225
 226         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 227                 if ((new_channel < 1) || (new_channel > 14))
 228                         return -EINVAL;
 229         } else {
 230                 return -EINVAL;
 231         }
 232
 233         return b43_phy_ht_set_channel(dev, channel, channel_type);
 234 }
 235
 236 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 237 {
 238         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 239                 return 1;
 240         return 36;
 241 }
 242
 243 /**************************************************
 244  * R/W ops.
 245  **************************************************/
 246
 247 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 248 {
 249         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 250         return b43_read16(dev, B43_MMIO_PHY_DATA);
 251 }
 252
 253 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 254 {
 255         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 256         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 257 }
 258
 259 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 260                                  u16 set)
 261 {
 262         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 263         b43_write16(dev, B43_MMIO_PHY_DATA,
 264                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 265 }
 266
 267 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 268 {
 269         /* HT-PHY needs 0x200 for read access */
 270         reg |= 0x200;
 271
 272         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 273         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 274 }
 275
 276 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 277                                       u16 value)
 278 {
 279         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 280         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 281 }
 282
 283 /**************************************************
 284  * PHY ops struct.
 285  **************************************************/
 286
 287 const struct b43_phy_operations b43_phyops_ht = {
 288         .allocate               = b43_phy_ht_op_allocate,
 289         .free                   = b43_phy_ht_op_free,
 290         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 291         /*
 292         .init                   = b43_phy_ht_op_init,
 293         */
 294         .phy_read               = b43_phy_ht_op_read,
 295         .phy_write              = b43_phy_ht_op_write,
 296         .phy_maskset            = b43_phy_ht_op_maskset,
 297         .radio_read             = b43_phy_ht_op_radio_read,
 298         .radio_write            = b43_phy_ht_op_radio_write,
 299         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 300         .switch_analog          = b43_phy_ht_op_switch_analog,
 301         .switch_channel         = b43_phy_ht_op_switch_channel,
 302         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 303         /*
 304         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 305         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 306         */
 307 };