drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   This program is free software; you can redistribute it and/or modify
   7   it under the terms of the GNU General Public License as published by
   8   the Free Software Foundation; either version 2 of the License, or
   9   (at your option) any later version.
  10
  11   This program is distributed in the hope that it will be useful,
  12   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14   GNU General Public License for more details.
  15
  16   You should have received a copy of the GNU General Public License
  17   along with this program; see the file COPYING.  If not, write to
  18   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  19   Boston, MA 02110-1301, USA.
  20
  21 */
  22
  23 #include <linux/slab.h>
  24
  25 #include "b43.h"
  26 #include "phy_ht.h"
  27 #include "radio_2059.h"
  28 #include "main.h"
  29
  30 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  31                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  32 {
  33         u8 i;
  34         u16 routing;
  35
  36         b43_radio_write(dev, 0x16, e->radio_syn16);
  37         b43_radio_write(dev, 0x17, e->radio_syn17);
  38         b43_radio_write(dev, 0x22, e->radio_syn22);
  39         b43_radio_write(dev, 0x25, e->radio_syn25);
  40         b43_radio_write(dev, 0x27, e->radio_syn27);
  41         b43_radio_write(dev, 0x28, e->radio_syn28);
  42         b43_radio_write(dev, 0x29, e->radio_syn29);
  43         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  44         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  45         b43_radio_write(dev, 0x37, e->radio_syn37);
  46         b43_radio_write(dev, 0x41, e->radio_syn41);
  47         b43_radio_write(dev, 0x43, e->radio_syn43);
  48         b43_radio_write(dev, 0x47, e->radio_syn47);
  49         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  50         b43_radio_write(dev, 0x58, e->radio_syn58);
  51         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  52         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  53         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  54         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  55         b43_radio_write(dev, 0x92, e->radio_syn92);
  56         b43_radio_write(dev, 0x98, e->radio_syn98);
  57
  58         for (i = 0; i < 2; i++) {
  59                 routing = i ? 0x800 : 0x400;
  60                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  61                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  62                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  63                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  64                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  65                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  66                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  67                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  68         }
  69
  70         udelay(50);
  71
  72         /* Calibration */
  73         b43_radio_mask(dev, 0x2b, ~0x1);
  74         b43_radio_mask(dev, 0x2e, ~0x4);
  75         b43_radio_set(dev, 0x2e, 0x4);
  76         b43_radio_set(dev, 0x2b, 0x1);
  77
  78         udelay(300);
  79 }
  80
  81 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
  82                                 const struct b43_phy_ht_channeltab_e_phy *e,
  83                                 struct ieee80211_channel *new_channel)
  84 {
  85         bool old_band_5ghz;
  86
  87         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
  88         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
  89                 /* TODO */
  90         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
  91                 /* TODO */
  92         }
  93
  94         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
  95         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
  96         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
  97         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
  98         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
  99         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 100 }
 101
 102 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 103                                   struct ieee80211_channel *channel,
 104                                   enum nl80211_channel_type channel_type)
 105 {
 106         struct b43_phy *phy = &dev->phy;
 107
 108         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 109
 110         if (phy->radio_ver == 0x2059) {
 111                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 112                                                         channel->center_freq);
 113                 if (!chent_r2059)
 114                         return -ESRCH;
 115         } else {
 116                 return -ESRCH;
 117         }
 118
 119         /* TODO: In case of N-PHY some bandwidth switching goes here */
 120
 121         if (phy->radio_ver == 0x2059) {
 122                 b43_radio_2059_channel_setup(dev, chent_r2059);
 123                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 124                                          channel);
 125         } else {
 126                 return -ESRCH;
 127         }
 128
 129         return 0;
 130 }
 131
 132 /**************************************************
 133  * Basic PHY ops.
 134  **************************************************/
 135
 136 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 137 {
 138         struct b43_phy_ht *phy_ht;
 139
 140         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 141         if (!phy_ht)
 142                 return -ENOMEM;
 143         dev->phy.ht = phy_ht;
 144
 145         return 0;
 146 }
 147
 148 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 149 {
 150         struct b43_phy *phy = &dev->phy;
 151         struct b43_phy_ht *phy_ht = phy->ht;
 152
 153         memset(phy_ht, 0, sizeof(*phy_ht));
 154 }
 155
 156 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 157 {
 158         struct b43_phy *phy = &dev->phy;
 159         struct b43_phy_ht *phy_ht = phy->ht;
 160
 161         kfree(phy_ht);
 162         phy->ht = NULL;
 163 }
 164
 165 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 166 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 167                                         bool blocked)
 168 {
 169         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 170                 b43err(dev->wl, "MAC not suspended\n");
 171
 172         if (blocked) {
 173                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 174         } else {
 175                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 176                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x1);
 177                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 178                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x2);
 179         }
 180 }
 181
 182 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 183 {
 184         if (on) {
 185                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd);
 186                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000);
 187                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd);
 188                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000);
 189                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd);
 190                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000);
 191         } else {
 192                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff);
 193                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd);
 194                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff);
 195                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd);
 196                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff);
 197                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd);
 198         }
 199 }
 200
 201 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 202                                         unsigned int new_channel)
 203 {
 204         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 205         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 206
 207         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 208                 if ((new_channel < 1) || (new_channel > 14))
 209                         return -EINVAL;
 210         } else {
 211                 return -EINVAL;
 212         }
 213
 214         return b43_phy_ht_set_channel(dev, channel, channel_type);
 215 }
 216
 217 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 218 {
 219         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 220                 return 1;
 221         return 36;
 222 }
 223
 224 /**************************************************
 225  * R/W ops.
 226  **************************************************/
 227
 228 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 229 {
 230         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 231         return b43_read16(dev, B43_MMIO_PHY_DATA);
 232 }
 233
 234 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 235 {
 236         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 237         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 238 }
 239
 240 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 241                                  u16 set)
 242 {
 243         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 244         b43_write16(dev, B43_MMIO_PHY_DATA,
 245                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 246 }
 247
 248 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 249 {
 250         /* HT-PHY needs 0x200 for read access */
 251         reg |= 0x200;
 252
 253         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 254         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 255 }
 256
 257 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 258                                       u16 value)
 259 {
 260         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 261         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 262 }
 263
 264 /**************************************************
 265  * PHY ops struct.
 266  **************************************************/
 267
 268 const struct b43_phy_operations b43_phyops_ht = {
 269         .allocate               = b43_phy_ht_op_allocate,
 270         .free                   = b43_phy_ht_op_free,
 271         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 272         /*
 273         .init                   = b43_phy_ht_op_init,
 274         */
 275         .phy_read               = b43_phy_ht_op_read,
 276         .phy_write              = b43_phy_ht_op_write,
 277         .phy_maskset            = b43_phy_ht_op_maskset,
 278         .radio_read             = b43_phy_ht_op_radio_read,
 279         .radio_write            = b43_phy_ht_op_radio_write,
 280         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 281         .switch_analog          = b43_phy_ht_op_switch_analog,
 282         .switch_channel         = b43_phy_ht_op_switch_channel,
 283         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 284         /*
 285         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 286         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 287         */
 288 };