drivers/net/wireless/b43/phy_ht.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n HT-PHY support
   5
   6   This program is free software; you can redistribute it and/or modify
   7   it under the terms of the GNU General Public License as published by
   8   the Free Software Foundation; either version 2 of the License, or
   9   (at your option) any later version.
  10
  11   This program is distributed in the hope that it will be useful,
  12   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14   GNU General Public License for more details.
  15
  16   You should have received a copy of the GNU General Public License
  17   along with this program; see the file COPYING.  If not, write to
  18   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  19   Boston, MA 02110-1301, USA.
  20
  21 */
  22
  23 #include <linux/slab.h>
  24
  25 #include "b43.h"
  26 #include "phy_ht.h"
  27 #include "tables_phy_ht.h"
  28 #include "radio_2059.h"
  29 #include "main.h"
  30
  31 /**************************************************
  32  * Radio 2059.
  33  **************************************************/
  34
  35 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
  36                         const struct b43_phy_ht_channeltab_e_radio2059 *e)
  37 {
  38         u8 i;
  39         u16 routing;
  40
  41         b43_radio_write(dev, 0x16, e->radio_syn16);
  42         b43_radio_write(dev, 0x17, e->radio_syn17);
  43         b43_radio_write(dev, 0x22, e->radio_syn22);
  44         b43_radio_write(dev, 0x25, e->radio_syn25);
  45         b43_radio_write(dev, 0x27, e->radio_syn27);
  46         b43_radio_write(dev, 0x28, e->radio_syn28);
  47         b43_radio_write(dev, 0x29, e->radio_syn29);
  48         b43_radio_write(dev, 0x2c, e->radio_syn2c);
  49         b43_radio_write(dev, 0x2d, e->radio_syn2d);
  50         b43_radio_write(dev, 0x37, e->radio_syn37);
  51         b43_radio_write(dev, 0x41, e->radio_syn41);
  52         b43_radio_write(dev, 0x43, e->radio_syn43);
  53         b43_radio_write(dev, 0x47, e->radio_syn47);
  54         b43_radio_write(dev, 0x4a, e->radio_syn4a);
  55         b43_radio_write(dev, 0x58, e->radio_syn58);
  56         b43_radio_write(dev, 0x5a, e->radio_syn5a);
  57         b43_radio_write(dev, 0x6a, e->radio_syn6a);
  58         b43_radio_write(dev, 0x6d, e->radio_syn6d);
  59         b43_radio_write(dev, 0x6e, e->radio_syn6e);
  60         b43_radio_write(dev, 0x92, e->radio_syn92);
  61         b43_radio_write(dev, 0x98, e->radio_syn98);
  62
  63         for (i = 0; i < 2; i++) {
  64                 routing = i ? R2059_RXRX1 : R2059_TXRX0;
  65                 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
  66                 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
  67                 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
  68                 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
  69                 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
  70                 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
  71                 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
  72                 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
  73         }
  74
  75         udelay(50);
  76
  77         /* Calibration */
  78         b43_radio_mask(dev, 0x2b, ~0x1);
  79         b43_radio_mask(dev, 0x2e, ~0x4);
  80         b43_radio_set(dev, 0x2e, 0x4);
  81         b43_radio_set(dev, 0x2b, 0x1);
  82
  83         udelay(300);
  84 }
  85
  86 static void b43_radio_2059_init(struct b43_wldev *dev)
  87 {
  88         const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
  89         u8 i;
  90
  91         b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
  92         b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
  93
  94         for (i = 0; i < ARRAY_SIZE(routing); i++)
  95                 b43_radio_set(dev, routing[i] | 0x146, 0x3);
  96
  97         b43_radio_set(dev, 0x2e, 0x0078);
  98         b43_radio_set(dev, 0xc0, 0x0080);
  99         msleep(2);
 100         b43_radio_mask(dev, 0x2e, ~0x0078);
 101         b43_radio_mask(dev, 0xc0, ~0x0080);
 102
 103         b43_radio_mask(dev, 0x11, 0x0008);
 104 }
 105
 106 /**************************************************
 107  * Channel switching ops.
 108  **************************************************/
 109
 110 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
 111                                 const struct b43_phy_ht_channeltab_e_phy *e,
 112                                 struct ieee80211_channel *new_channel)
 113 {
 114         bool old_band_5ghz;
 115         u8 i;
 116
 117         old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
 118         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
 119                 /* TODO */
 120         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
 121                 /* TODO */
 122         }
 123
 124         b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
 125         b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
 126         b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
 127         b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
 128         b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
 129         b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
 130
 131         /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
 132
 133         /* TODO: separated function? */
 134         for (i = 0; i < 3; i++) {
 135                 u16 mask;
 136                 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
 137
 138                 if (0) /* FIXME */
 139                         mask = 0x2 << (i * 4);
 140                 else
 141                         mask = 0;
 142                 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
 143
 144                 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
 145                 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
 146                                 tmp & 0xFF);
 147                 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
 148                                 tmp & 0xFF);
 149         }
 150
 151         b43_phy_write(dev, 0x017e, 0x3830);
 152 }
 153
 154 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
 155                                   struct ieee80211_channel *channel,
 156                                   enum nl80211_channel_type channel_type)
 157 {
 158         struct b43_phy *phy = &dev->phy;
 159
 160         const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
 161
 162         if (phy->radio_ver == 0x2059) {
 163                 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
 164                                                         channel->center_freq);
 165                 if (!chent_r2059)
 166                         return -ESRCH;
 167         } else {
 168                 return -ESRCH;
 169         }
 170
 171         /* TODO: In case of N-PHY some bandwidth switching goes here */
 172
 173         if (phy->radio_ver == 0x2059) {
 174                 b43_radio_2059_channel_setup(dev, chent_r2059);
 175                 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
 176                                          channel);
 177         } else {
 178                 return -ESRCH;
 179         }
 180
 181         return 0;
 182 }
 183
 184 /**************************************************
 185  * Basic PHY ops.
 186  **************************************************/
 187
 188 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
 189 {
 190         struct b43_phy_ht *phy_ht;
 191
 192         phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
 193         if (!phy_ht)
 194                 return -ENOMEM;
 195         dev->phy.ht = phy_ht;
 196
 197         return 0;
 198 }
 199
 200 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
 201 {
 202         struct b43_phy *phy = &dev->phy;
 203         struct b43_phy_ht *phy_ht = phy->ht;
 204
 205         memset(phy_ht, 0, sizeof(*phy_ht));
 206 }
 207
 208 static int b43_phy_ht_op_init(struct b43_wldev *dev)
 209 {
 210         b43_phy_ht_tables_init(dev);
 211
 212         return 0;
 213 }
 214
 215 static void b43_phy_ht_op_free(struct b43_wldev *dev)
 216 {
 217         struct b43_phy *phy = &dev->phy;
 218         struct b43_phy_ht *phy_ht = phy->ht;
 219
 220         kfree(phy_ht);
 221         phy->ht = NULL;
 222 }
 223
 224 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
 225 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
 226                                         bool blocked)
 227 {
 228         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 229                 b43err(dev->wl, "MAC not suspended\n");
 230
 231         if (blocked) {
 232                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 233         } else {
 234                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 235                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x1);
 236                 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, ~0);
 237                 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, ~0, 0x2);
 238
 239                 if (dev->phy.radio_ver == 0x2059)
 240                         b43_radio_2059_init(dev);
 241                 else
 242                         B43_WARN_ON(1);
 243         }
 244 }
 245
 246 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
 247 {
 248         if (on) {
 249                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd);
 250                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000);
 251                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd);
 252                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000);
 253                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd);
 254                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000);
 255         } else {
 256                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff);
 257                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd);
 258                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff);
 259                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd);
 260                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff);
 261                 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd);
 262         }
 263 }
 264
 265 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
 266                                         unsigned int new_channel)
 267 {
 268         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 269         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 270
 271         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 272                 if ((new_channel < 1) || (new_channel > 14))
 273                         return -EINVAL;
 274         } else {
 275                 return -EINVAL;
 276         }
 277
 278         return b43_phy_ht_set_channel(dev, channel, channel_type);
 279 }
 280
 281 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
 282 {
 283         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 284                 return 1;
 285         return 36;
 286 }
 287
 288 /**************************************************
 289  * R/W ops.
 290  **************************************************/
 291
 292 static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
 293 {
 294         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 295         return b43_read16(dev, B43_MMIO_PHY_DATA);
 296 }
 297
 298 static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 299 {
 300         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 301         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 302 }
 303
 304 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 305                                  u16 set)
 306 {
 307         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 308         b43_write16(dev, B43_MMIO_PHY_DATA,
 309                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 310 }
 311
 312 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
 313 {
 314         /* HT-PHY needs 0x200 for read access */
 315         reg |= 0x200;
 316
 317         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 318         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 319 }
 320
 321 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
 322                                       u16 value)
 323 {
 324         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 325         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 326 }
 327
 328 /**************************************************
 329  * PHY ops struct.
 330  **************************************************/
 331
 332 const struct b43_phy_operations b43_phyops_ht = {
 333         .allocate               = b43_phy_ht_op_allocate,
 334         .free                   = b43_phy_ht_op_free,
 335         .prepare_structs        = b43_phy_ht_op_prepare_structs,
 336         .init                   = b43_phy_ht_op_init,
 337         .phy_read               = b43_phy_ht_op_read,
 338         .phy_write              = b43_phy_ht_op_write,
 339         .phy_maskset            = b43_phy_ht_op_maskset,
 340         .radio_read             = b43_phy_ht_op_radio_read,
 341         .radio_write            = b43_phy_ht_op_radio_write,
 342         .software_rfkill        = b43_phy_ht_op_software_rfkill,
 343         .switch_analog          = b43_phy_ht_op_switch_analog,
 344         .switch_channel         = b43_phy_ht_op_switch_channel,
 345         .get_default_chan       = b43_phy_ht_op_get_default_chan,
 346         /*
 347         .recalc_txpower         = b43_phy_ht_op_recalc_txpower,
 348         .adjust_txpower         = b43_phy_ht_op_adjust_txpower,
 349         */
 350 };