drivers/net/wireless/b43/phy_g.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g PHY driver
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include "b43.h"
  30 #include "phy_g.h"
  31 #include "phy_common.h"
  32 #include "lo.h"
  33 #include "main.h"
  34
  35 #include <linux/bitrev.h>
  36
  37
  38 static const s8 b43_tssi2dbm_g_table[] = {
  39         77, 77, 77, 76,
  40         76, 76, 75, 75,
  41         74, 74, 73, 73,
  42         73, 72, 72, 71,
  43         71, 70, 70, 69,
  44         68, 68, 67, 67,
  45         66, 65, 65, 64,
  46         63, 63, 62, 61,
  47         60, 59, 58, 57,
  48         56, 55, 54, 53,
  49         52, 50, 49, 47,
  50         45, 43, 40, 37,
  51         33, 28, 22, 14,
  52         5, -7, -20, -20,
  53         -20, -20, -20, -20,
  54         -20, -20, -20, -20,
  55 };
  56
  57 static const u8 b43_radio_channel_codes_bg[] = {
  58         12, 17, 22, 27,
  59         32, 37, 42, 47,
  60         52, 57, 62, 67,
  61         72, 84,
  62 };
  63
  64
  65 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
  66
  67
  68 #define bitrev4(tmp) (bitrev8(tmp) >> 4)
  69
  70
  71 /* Get the freq, as it has to be written to the device. */
  72 static inline u16 channel2freq_bg(u8 channel)
  73 {
  74         B43_WARN_ON(!(channel >= 1 && channel <= 14));
  75
  76         return b43_radio_channel_codes_bg[channel - 1];
  77 }
  78
  79 static void generate_rfatt_list(struct b43_wldev *dev,
  80                                 struct b43_rfatt_list *list)
  81 {
  82         struct b43_phy *phy = &dev->phy;
  83
  84         /* APHY.rev < 5 || GPHY.rev < 6 */
  85         static const struct b43_rfatt rfatt_0[] = {
  86                 {.att = 3,.with_padmix = 0,},
  87                 {.att = 1,.with_padmix = 0,},
  88                 {.att = 5,.with_padmix = 0,},
  89                 {.att = 7,.with_padmix = 0,},
  90                 {.att = 9,.with_padmix = 0,},
  91                 {.att = 2,.with_padmix = 0,},
  92                 {.att = 0,.with_padmix = 0,},
  93                 {.att = 4,.with_padmix = 0,},
  94                 {.att = 6,.with_padmix = 0,},
  95                 {.att = 8,.with_padmix = 0,},
  96                 {.att = 1,.with_padmix = 1,},
  97                 {.att = 2,.with_padmix = 1,},
  98                 {.att = 3,.with_padmix = 1,},
  99                 {.att = 4,.with_padmix = 1,},
 100         };
 101         /* Radio.rev == 8 && Radio.version == 0x2050 */
 102         static const struct b43_rfatt rfatt_1[] = {
 103                 {.att = 2,.with_padmix = 1,},
 104                 {.att = 4,.with_padmix = 1,},
 105                 {.att = 6,.with_padmix = 1,},
 106                 {.att = 8,.with_padmix = 1,},
 107                 {.att = 10,.with_padmix = 1,},
 108                 {.att = 12,.with_padmix = 1,},
 109                 {.att = 14,.with_padmix = 1,},
 110         };
 111         /* Otherwise */
 112         static const struct b43_rfatt rfatt_2[] = {
 113                 {.att = 0,.with_padmix = 1,},
 114                 {.att = 2,.with_padmix = 1,},
 115                 {.att = 4,.with_padmix = 1,},
 116                 {.att = 6,.with_padmix = 1,},
 117                 {.att = 8,.with_padmix = 1,},
 118                 {.att = 9,.with_padmix = 1,},
 119                 {.att = 9,.with_padmix = 1,},
 120         };
 121
 122         if (!b43_has_hardware_pctl(dev)) {
 123                 /* Software pctl */
 124                 list->list = rfatt_0;
 125                 list->len = ARRAY_SIZE(rfatt_0);
 126                 list->min_val = 0;
 127                 list->max_val = 9;
 128                 return;
 129         }
 130         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 131                 /* Hardware pctl */
 132                 list->list = rfatt_1;
 133                 list->len = ARRAY_SIZE(rfatt_1);
 134                 list->min_val = 0;
 135                 list->max_val = 14;
 136                 return;
 137         }
 138         /* Hardware pctl */
 139         list->list = rfatt_2;
 140         list->len = ARRAY_SIZE(rfatt_2);
 141         list->min_val = 0;
 142         list->max_val = 9;
 143 }
 144
 145 static void generate_bbatt_list(struct b43_wldev *dev,
 146                                 struct b43_bbatt_list *list)
 147 {
 148         static const struct b43_bbatt bbatt_0[] = {
 149                 {.att = 0,},
 150                 {.att = 1,},
 151                 {.att = 2,},
 152                 {.att = 3,},
 153                 {.att = 4,},
 154                 {.att = 5,},
 155                 {.att = 6,},
 156                 {.att = 7,},
 157                 {.att = 8,},
 158         };
 159
 160         list->list = bbatt_0;
 161         list->len = ARRAY_SIZE(bbatt_0);
 162         list->min_val = 0;
 163         list->max_val = 8;
 164 }
 165
 166 static void b43_shm_clear_tssi(struct b43_wldev *dev)
 167 {
 168         b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
 169         b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
 170         b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
 171         b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
 172 }
 173
 174 /* Synthetic PU workaround */
 175 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
 176 {
 177         struct b43_phy *phy = &dev->phy;
 178
 179         might_sleep();
 180
 181         if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
 182                 /* We do not need the workaround. */
 183                 return;
 184         }
 185
 186         if (channel <= 10) {
 187                 b43_write16(dev, B43_MMIO_CHANNEL,
 188                             channel2freq_bg(channel + 4));
 189         } else {
 190                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
 191         }
 192         msleep(1);
 193         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
 194 }
 195
 196 /* Set the baseband attenuation value on chip. */
 197 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
 198                                        u16 baseband_attenuation)
 199 {
 200         struct b43_phy *phy = &dev->phy;
 201
 202         if (phy->analog == 0) {
 203                 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
 204                                                  & 0xFFF0) |
 205                             baseband_attenuation);
 206         } else if (phy->analog > 1) {
 207                 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2));
 208         } else {
 209                 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3));
 210         }
 211 }
 212
 213 /* Adjust the transmission power output (G-PHY) */
 214 static void b43_set_txpower_g(struct b43_wldev *dev,
 215                               const struct b43_bbatt *bbatt,
 216                               const struct b43_rfatt *rfatt, u8 tx_control)
 217 {
 218         struct b43_phy *phy = &dev->phy;
 219         struct b43_phy_g *gphy = phy->g;
 220         struct b43_txpower_lo_control *lo = gphy->lo_control;
 221         u16 bb, rf;
 222         u16 tx_bias, tx_magn;
 223
 224         bb = bbatt->att;
 225         rf = rfatt->att;
 226         tx_bias = lo->tx_bias;
 227         tx_magn = lo->tx_magn;
 228         if (unlikely(tx_bias == 0xFF))
 229                 tx_bias = 0;
 230
 231         /* Save the values for later. Use memmove, because it's valid
 232          * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */
 233         gphy->tx_control = tx_control;
 234         memmove(&gphy->rfatt, rfatt, sizeof(*rfatt));
 235         gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
 236         memmove(&gphy->bbatt, bbatt, sizeof(*bbatt));
 237
 238         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
 239                 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
 240                        "rfatt(%u), tx_control(0x%02X), "
 241                        "tx_bias(0x%02X), tx_magn(0x%02X)\n",
 242                        bb, rf, tx_control, tx_bias, tx_magn);
 243         }
 244
 245         b43_gphy_set_baseband_attenuation(dev, bb);
 246         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
 247         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 248                 b43_radio_write16(dev, 0x43,
 249                                   (rf & 0x000F) | (tx_control & 0x0070));
 250         } else {
 251                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
 252                                               & 0xFFF0) | (rf & 0x000F));
 253                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 254                                               & ~0x0070) | (tx_control &
 255                                                             0x0070));
 256         }
 257         if (has_tx_magnification(phy)) {
 258                 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
 259         } else {
 260                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 261                                               & 0xFFF0) | (tx_bias & 0x000F));
 262         }
 263         b43_lo_g_adjust(dev);
 264 }
 265
 266 /* GPHY_TSSI_Power_Lookup_Table_Init */
 267 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
 268 {
 269         struct b43_phy_g *gphy = dev->phy.g;
 270         int i;
 271         u16 value;
 272
 273         for (i = 0; i < 32; i++)
 274                 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
 275         for (i = 32; i < 64; i++)
 276                 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
 277         for (i = 0; i < 64; i += 2) {
 278                 value = (u16) gphy->tssi2dbm[i];
 279                 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
 280                 b43_phy_write(dev, 0x380 + (i / 2), value);
 281         }
 282 }
 283
 284 /* GPHY_Gain_Lookup_Table_Init */
 285 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
 286 {
 287         struct b43_phy *phy = &dev->phy;
 288         struct b43_phy_g *gphy = phy->g;
 289         struct b43_txpower_lo_control *lo = gphy->lo_control;
 290         u16 nr_written = 0;
 291         u16 tmp;
 292         u8 rf, bb;
 293
 294         for (rf = 0; rf < lo->rfatt_list.len; rf++) {
 295                 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
 296                         if (nr_written >= 0x40)
 297                                 return;
 298                         tmp = lo->bbatt_list.list[bb].att;
 299                         tmp <<= 8;
 300                         if (phy->radio_rev == 8)
 301                                 tmp |= 0x50;
 302                         else
 303                                 tmp |= 0x40;
 304                         tmp |= lo->rfatt_list.list[rf].att;
 305                         b43_phy_write(dev, 0x3C0 + nr_written, tmp);
 306                         nr_written++;
 307                 }
 308         }
 309 }
 310
 311 static void b43_set_all_gains(struct b43_wldev *dev,
 312                               s16 first, s16 second, s16 third)
 313 {
 314         struct b43_phy *phy = &dev->phy;
 315         u16 i;
 316         u16 start = 0x08, end = 0x18;
 317         u16 tmp;
 318         u16 table;
 319
 320         if (phy->rev <= 1) {
 321                 start = 0x10;
 322                 end = 0x20;
 323         }
 324
 325         table = B43_OFDMTAB_GAINX;
 326         if (phy->rev <= 1)
 327                 table = B43_OFDMTAB_GAINX_R1;
 328         for (i = 0; i < 4; i++)
 329                 b43_ofdmtab_write16(dev, table, i, first);
 330
 331         for (i = start; i < end; i++)
 332                 b43_ofdmtab_write16(dev, table, i, second);
 333
 334         if (third != -1) {
 335                 tmp = ((u16) third << 14) | ((u16) third << 6);
 336                 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp);
 337                 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp);
 338                 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp);
 339         }
 340         b43_dummy_transmission(dev);
 341 }
 342
 343 static void b43_set_original_gains(struct b43_wldev *dev)
 344 {
 345         struct b43_phy *phy = &dev->phy;
 346         u16 i, tmp;
 347         u16 table;
 348         u16 start = 0x0008, end = 0x0018;
 349
 350         if (phy->rev <= 1) {
 351                 start = 0x0010;
 352                 end = 0x0020;
 353         }
 354
 355         table = B43_OFDMTAB_GAINX;
 356         if (phy->rev <= 1)
 357                 table = B43_OFDMTAB_GAINX_R1;
 358         for (i = 0; i < 4; i++) {
 359                 tmp = (i & 0xFFFC);
 360                 tmp |= (i & 0x0001) << 1;
 361                 tmp |= (i & 0x0002) >> 1;
 362
 363                 b43_ofdmtab_write16(dev, table, i, tmp);
 364         }
 365
 366         for (i = start; i < end; i++)
 367                 b43_ofdmtab_write16(dev, table, i, i - start);
 368
 369         b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040);
 370         b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040);
 371         b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000);
 372         b43_dummy_transmission(dev);
 373 }
 374
 375 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 376 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
 377 {
 378         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
 379         b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
 380 }
 381
 382 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 383 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
 384 {
 385         u16 val;
 386
 387         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
 388         val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
 389
 390         return (s16) val;
 391 }
 392
 393 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 394 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
 395 {
 396         u16 i;
 397         s16 tmp;
 398
 399         for (i = 0; i < 64; i++) {
 400                 tmp = b43_nrssi_hw_read(dev, i);
 401                 tmp -= val;
 402                 tmp = clamp_val(tmp, -32, 31);
 403                 b43_nrssi_hw_write(dev, i, tmp);
 404         }
 405 }
 406
 407 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 408 static void b43_nrssi_mem_update(struct b43_wldev *dev)
 409 {
 410         struct b43_phy_g *gphy = dev->phy.g;
 411         s16 i, delta;
 412         s32 tmp;
 413
 414         delta = 0x1F - gphy->nrssi[0];
 415         for (i = 0; i < 64; i++) {
 416                 tmp = (i - delta) * gphy->nrssislope;
 417                 tmp /= 0x10000;
 418                 tmp += 0x3A;
 419                 tmp = clamp_val(tmp, 0, 0x3F);
 420                 gphy->nrssi_lt[i] = tmp;
 421         }
 422 }
 423
 424 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
 425 {
 426         struct b43_phy *phy = &dev->phy;
 427         u16 backup[20] = { 0 };
 428         s16 v47F;
 429         u16 i;
 430         u16 saved = 0xFFFF;
 431
 432         backup[0] = b43_phy_read(dev, 0x0001);
 433         backup[1] = b43_phy_read(dev, 0x0811);
 434         backup[2] = b43_phy_read(dev, 0x0812);
 435         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 436                 backup[3] = b43_phy_read(dev, 0x0814);
 437                 backup[4] = b43_phy_read(dev, 0x0815);
 438         }
 439         backup[5] = b43_phy_read(dev, 0x005A);
 440         backup[6] = b43_phy_read(dev, 0x0059);
 441         backup[7] = b43_phy_read(dev, 0x0058);
 442         backup[8] = b43_phy_read(dev, 0x000A);
 443         backup[9] = b43_phy_read(dev, 0x0003);
 444         backup[10] = b43_radio_read16(dev, 0x007A);
 445         backup[11] = b43_radio_read16(dev, 0x0043);
 446
 447         b43_phy_mask(dev, 0x0429, 0x7FFF);
 448         b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000);
 449         b43_phy_set(dev, 0x0811, 0x000C);
 450         b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004);
 451         b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
 452         if (phy->rev >= 6) {
 453                 backup[12] = b43_phy_read(dev, 0x002E);
 454                 backup[13] = b43_phy_read(dev, 0x002F);
 455                 backup[14] = b43_phy_read(dev, 0x080F);
 456                 backup[15] = b43_phy_read(dev, 0x0810);
 457                 backup[16] = b43_phy_read(dev, 0x0801);
 458                 backup[17] = b43_phy_read(dev, 0x0060);
 459                 backup[18] = b43_phy_read(dev, 0x0014);
 460                 backup[19] = b43_phy_read(dev, 0x0478);
 461
 462                 b43_phy_write(dev, 0x002E, 0);
 463                 b43_phy_write(dev, 0x002F, 0);
 464                 b43_phy_write(dev, 0x080F, 0);
 465                 b43_phy_write(dev, 0x0810, 0);
 466                 b43_phy_set(dev, 0x0478, 0x0100);
 467                 b43_phy_set(dev, 0x0801, 0x0040);
 468                 b43_phy_set(dev, 0x0060, 0x0040);
 469                 b43_phy_set(dev, 0x0014, 0x0200);
 470         }
 471         b43_radio_set(dev, 0x007A, 0x0070);
 472         b43_radio_set(dev, 0x007A, 0x0080);
 473         udelay(30);
 474
 475         v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 476         if (v47F >= 0x20)
 477                 v47F -= 0x40;
 478         if (v47F == 31) {
 479                 for (i = 7; i >= 4; i--) {
 480                         b43_radio_write16(dev, 0x007B, i);
 481                         udelay(20);
 482                         v47F =
 483                             (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 484                         if (v47F >= 0x20)
 485                                 v47F -= 0x40;
 486                         if (v47F < 31 && saved == 0xFFFF)
 487                                 saved = i;
 488                 }
 489                 if (saved == 0xFFFF)
 490                         saved = 4;
 491         } else {
 492                 b43_radio_write16(dev, 0x007A,
 493                                   b43_radio_read16(dev, 0x007A) & 0x007F);
 494                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 495                         b43_phy_set(dev, 0x0814, 0x0001);
 496                         b43_phy_mask(dev, 0x0815, 0xFFFE);
 497                 }
 498                 b43_phy_set(dev, 0x0811, 0x000C);
 499                 b43_phy_set(dev, 0x0812, 0x000C);
 500                 b43_phy_set(dev, 0x0811, 0x0030);
 501                 b43_phy_set(dev, 0x0812, 0x0030);
 502                 b43_phy_write(dev, 0x005A, 0x0480);
 503                 b43_phy_write(dev, 0x0059, 0x0810);
 504                 b43_phy_write(dev, 0x0058, 0x000D);
 505                 if (phy->rev == 0) {
 506                         b43_phy_write(dev, 0x0003, 0x0122);
 507                 } else {
 508                         b43_phy_set(dev, 0x000A, 0x2000);
 509                 }
 510                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 511                         b43_phy_set(dev, 0x0814, 0x0004);
 512                         b43_phy_mask(dev, 0x0815, 0xFFFB);
 513                 }
 514                 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
 515                 b43_radio_set(dev, 0x007A, 0x000F);
 516                 b43_set_all_gains(dev, 3, 0, 1);
 517                 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
 518                                                 & 0x00F0) | 0x000F);
 519                 udelay(30);
 520                 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 521                 if (v47F >= 0x20)
 522                         v47F -= 0x40;
 523                 if (v47F == -32) {
 524                         for (i = 0; i < 4; i++) {
 525                                 b43_radio_write16(dev, 0x007B, i);
 526                                 udelay(20);
 527                                 v47F =
 528                                     (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
 529                                            0x003F);
 530                                 if (v47F >= 0x20)
 531                                         v47F -= 0x40;
 532                                 if (v47F > -31 && saved == 0xFFFF)
 533                                         saved = i;
 534                         }
 535                         if (saved == 0xFFFF)
 536                                 saved = 3;
 537                 } else
 538                         saved = 0;
 539         }
 540         b43_radio_write16(dev, 0x007B, saved);
 541
 542         if (phy->rev >= 6) {
 543                 b43_phy_write(dev, 0x002E, backup[12]);
 544                 b43_phy_write(dev, 0x002F, backup[13]);
 545                 b43_phy_write(dev, 0x080F, backup[14]);
 546                 b43_phy_write(dev, 0x0810, backup[15]);
 547         }
 548         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 549                 b43_phy_write(dev, 0x0814, backup[3]);
 550                 b43_phy_write(dev, 0x0815, backup[4]);
 551         }
 552         b43_phy_write(dev, 0x005A, backup[5]);
 553         b43_phy_write(dev, 0x0059, backup[6]);
 554         b43_phy_write(dev, 0x0058, backup[7]);
 555         b43_phy_write(dev, 0x000A, backup[8]);
 556         b43_phy_write(dev, 0x0003, backup[9]);
 557         b43_radio_write16(dev, 0x0043, backup[11]);
 558         b43_radio_write16(dev, 0x007A, backup[10]);
 559         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
 560         b43_phy_set(dev, 0x0429, 0x8000);
 561         b43_set_original_gains(dev);
 562         if (phy->rev >= 6) {
 563                 b43_phy_write(dev, 0x0801, backup[16]);
 564                 b43_phy_write(dev, 0x0060, backup[17]);
 565                 b43_phy_write(dev, 0x0014, backup[18]);
 566                 b43_phy_write(dev, 0x0478, backup[19]);
 567         }
 568         b43_phy_write(dev, 0x0001, backup[0]);
 569         b43_phy_write(dev, 0x0812, backup[2]);
 570         b43_phy_write(dev, 0x0811, backup[1]);
 571 }
 572
 573 static void b43_calc_nrssi_slope(struct b43_wldev *dev)
 574 {
 575         struct b43_phy *phy = &dev->phy;
 576         struct b43_phy_g *gphy = phy->g;
 577         u16 backup[18] = { 0 };
 578         u16 tmp;
 579         s16 nrssi0, nrssi1;
 580
 581         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 582
 583         if (phy->radio_rev >= 9)
 584                 return;
 585         if (phy->radio_rev == 8)
 586                 b43_calc_nrssi_offset(dev);
 587
 588         b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
 589         b43_phy_mask(dev, 0x0802, 0xFFFC);
 590         backup[7] = b43_read16(dev, 0x03E2);
 591         b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
 592         backup[0] = b43_radio_read16(dev, 0x007A);
 593         backup[1] = b43_radio_read16(dev, 0x0052);
 594         backup[2] = b43_radio_read16(dev, 0x0043);
 595         backup[3] = b43_phy_read(dev, 0x0015);
 596         backup[4] = b43_phy_read(dev, 0x005A);
 597         backup[5] = b43_phy_read(dev, 0x0059);
 598         backup[6] = b43_phy_read(dev, 0x0058);
 599         backup[8] = b43_read16(dev, 0x03E6);
 600         backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
 601         if (phy->rev >= 3) {
 602                 backup[10] = b43_phy_read(dev, 0x002E);
 603                 backup[11] = b43_phy_read(dev, 0x002F);
 604                 backup[12] = b43_phy_read(dev, 0x080F);
 605                 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
 606                 backup[14] = b43_phy_read(dev, 0x0801);
 607                 backup[15] = b43_phy_read(dev, 0x0060);
 608                 backup[16] = b43_phy_read(dev, 0x0014);
 609                 backup[17] = b43_phy_read(dev, 0x0478);
 610                 b43_phy_write(dev, 0x002E, 0);
 611                 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
 612                 switch (phy->rev) {
 613                 case 4:
 614                 case 6:
 615                 case 7:
 616                         b43_phy_set(dev, 0x0478, 0x0100);
 617                         b43_phy_set(dev, 0x0801, 0x0040);
 618                         break;
 619                 case 3:
 620                 case 5:
 621                         b43_phy_mask(dev, 0x0801, 0xFFBF);
 622                         break;
 623                 }
 624                 b43_phy_set(dev, 0x0060, 0x0040);
 625                 b43_phy_set(dev, 0x0014, 0x0200);
 626         }
 627         b43_radio_set(dev, 0x007A, 0x0070);
 628         b43_set_all_gains(dev, 0, 8, 0);
 629         b43_radio_write16(dev, 0x007A,
 630                           b43_radio_read16(dev, 0x007A) & 0x00F7);
 631         if (phy->rev >= 2) {
 632                 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030);
 633                 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010);
 634         }
 635         b43_radio_set(dev, 0x007A, 0x0080);
 636         udelay(20);
 637
 638         nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 639         if (nrssi0 >= 0x0020)
 640                 nrssi0 -= 0x0040;
 641
 642         b43_radio_write16(dev, 0x007A,
 643                           b43_radio_read16(dev, 0x007A) & 0x007F);
 644         if (phy->rev >= 2) {
 645                 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
 646         }
 647
 648         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
 649                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
 650                     | 0x2000);
 651         b43_radio_set(dev, 0x007A, 0x000F);
 652         b43_phy_write(dev, 0x0015, 0xF330);
 653         if (phy->rev >= 2) {
 654                 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020);
 655                 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020);
 656         }
 657
 658         b43_set_all_gains(dev, 3, 0, 1);
 659         if (phy->radio_rev == 8) {
 660                 b43_radio_write16(dev, 0x0043, 0x001F);
 661         } else {
 662                 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
 663                 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
 664                 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
 665                 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
 666         }
 667         b43_phy_write(dev, 0x005A, 0x0480);
 668         b43_phy_write(dev, 0x0059, 0x0810);
 669         b43_phy_write(dev, 0x0058, 0x000D);
 670         udelay(20);
 671         nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 672         if (nrssi1 >= 0x0020)
 673                 nrssi1 -= 0x0040;
 674         if (nrssi0 == nrssi1)
 675                 gphy->nrssislope = 0x00010000;
 676         else
 677                 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
 678         if (nrssi0 >= -4) {
 679                 gphy->nrssi[0] = nrssi1;
 680                 gphy->nrssi[1] = nrssi0;
 681         }
 682         if (phy->rev >= 3) {
 683                 b43_phy_write(dev, 0x002E, backup[10]);
 684                 b43_phy_write(dev, 0x002F, backup[11]);
 685                 b43_phy_write(dev, 0x080F, backup[12]);
 686                 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
 687         }
 688         if (phy->rev >= 2) {
 689                 b43_phy_mask(dev, 0x0812, 0xFFCF);
 690                 b43_phy_mask(dev, 0x0811, 0xFFCF);
 691         }
 692
 693         b43_radio_write16(dev, 0x007A, backup[0]);
 694         b43_radio_write16(dev, 0x0052, backup[1]);
 695         b43_radio_write16(dev, 0x0043, backup[2]);
 696         b43_write16(dev, 0x03E2, backup[7]);
 697         b43_write16(dev, 0x03E6, backup[8]);
 698         b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
 699         b43_phy_write(dev, 0x0015, backup[3]);
 700         b43_phy_write(dev, 0x005A, backup[4]);
 701         b43_phy_write(dev, 0x0059, backup[5]);
 702         b43_phy_write(dev, 0x0058, backup[6]);
 703         b43_synth_pu_workaround(dev, phy->channel);
 704         b43_phy_set(dev, 0x0802, (0x0001 | 0x0002));
 705         b43_set_original_gains(dev);
 706         b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
 707         if (phy->rev >= 3) {
 708                 b43_phy_write(dev, 0x0801, backup[14]);
 709                 b43_phy_write(dev, 0x0060, backup[15]);
 710                 b43_phy_write(dev, 0x0014, backup[16]);
 711                 b43_phy_write(dev, 0x0478, backup[17]);
 712         }
 713         b43_nrssi_mem_update(dev);
 714         b43_calc_nrssi_threshold(dev);
 715 }
 716
 717 static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
 718 {
 719         struct b43_phy *phy = &dev->phy;
 720         struct b43_phy_g *gphy = phy->g;
 721         s32 a, b;
 722         s16 tmp16;
 723         u16 tmp_u16;
 724
 725         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 726
 727         if (!phy->gmode ||
 728             !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
 729                 tmp16 = b43_nrssi_hw_read(dev, 0x20);
 730                 if (tmp16 >= 0x20)
 731                         tmp16 -= 0x40;
 732                 if (tmp16 < 3) {
 733                         b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB);
 734                 } else {
 735                         b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED);
 736                 }
 737         } else {
 738                 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
 739                         a = 0xE;
 740                         b = 0xA;
 741                 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
 742                         a = 0x13;
 743                         b = 0x12;
 744                 } else {
 745                         a = 0xE;
 746                         b = 0x11;
 747                 }
 748
 749                 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
 750                 a += (gphy->nrssi[0] << 6);
 751                 if (a < 32)
 752                         a += 31;
 753                 else
 754                         a += 32;
 755                 a = a >> 6;
 756                 a = clamp_val(a, -31, 31);
 757
 758                 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
 759                 b += (gphy->nrssi[0] << 6);
 760                 if (b < 32)
 761                         b += 31;
 762                 else
 763                         b += 32;
 764                 b = b >> 6;
 765                 b = clamp_val(b, -31, 31);
 766
 767                 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
 768                 tmp_u16 |= ((u32) b & 0x0000003F);
 769                 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
 770                 b43_phy_write(dev, 0x048A, tmp_u16);
 771         }
 772 }
 773
 774 /* Stack implementation to save/restore values from the
 775  * interference mitigation code.
 776  * It is save to restore values in random order.
 777  */
 778 static void _stack_save(u32 * _stackptr, size_t * stackidx,
 779                         u8 id, u16 offset, u16 value)
 780 {
 781         u32 *stackptr = &(_stackptr[*stackidx]);
 782
 783         B43_WARN_ON(offset & 0xF000);
 784         B43_WARN_ON(id & 0xF0);
 785         *stackptr = offset;
 786         *stackptr |= ((u32) id) << 12;
 787         *stackptr |= ((u32) value) << 16;
 788         (*stackidx)++;
 789         B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
 790 }
 791
 792 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
 793 {
 794         size_t i;
 795
 796         B43_WARN_ON(offset & 0xF000);
 797         B43_WARN_ON(id & 0xF0);
 798         for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
 799                 if ((*stackptr & 0x00000FFF) != offset)
 800                         continue;
 801                 if (((*stackptr & 0x0000F000) >> 12) != id)
 802                         continue;
 803                 return ((*stackptr & 0xFFFF0000) >> 16);
 804         }
 805         B43_WARN_ON(1);
 806
 807         return 0;
 808 }
 809
 810 #define phy_stacksave(offset)                                   \
 811         do {                                                    \
 812                 _stack_save(stack, &stackidx, 0x1, (offset),    \
 813                             b43_phy_read(dev, (offset)));       \
 814         } while (0)
 815 #define phy_stackrestore(offset)                                \
 816         do {                                                    \
 817                 b43_phy_write(dev, (offset),            \
 818                                   _stack_restore(stack, 0x1,    \
 819                                                  (offset)));    \
 820         } while (0)
 821 #define radio_stacksave(offset)                                         \
 822         do {                                                            \
 823                 _stack_save(stack, &stackidx, 0x2, (offset),            \
 824                             b43_radio_read16(dev, (offset)));   \
 825         } while (0)
 826 #define radio_stackrestore(offset)                                      \
 827         do {                                                            \
 828                 b43_radio_write16(dev, (offset),                        \
 829                                       _stack_restore(stack, 0x2,        \
 830                                                      (offset)));        \
 831         } while (0)
 832 #define ofdmtab_stacksave(table, offset)                        \
 833         do {                                                    \
 834                 _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
 835                             b43_ofdmtab_read16(dev, (table), (offset)));        \
 836         } while (0)
 837 #define ofdmtab_stackrestore(table, offset)                     \
 838         do {                                                    \
 839                 b43_ofdmtab_write16(dev, (table),       (offset),       \
 840                                   _stack_restore(stack, 0x3,    \
 841                                                  (offset)|(table)));    \
 842         } while (0)
 843
 844 static void
 845 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
 846 {
 847         struct b43_phy *phy = &dev->phy;
 848         struct b43_phy_g *gphy = phy->g;
 849         u16 tmp, flipped;
 850         size_t stackidx = 0;
 851         u32 *stack = gphy->interfstack;
 852
 853         switch (mode) {
 854         case B43_INTERFMODE_NONWLAN:
 855                 if (phy->rev != 1) {
 856                         b43_phy_set(dev, 0x042B, 0x0800);
 857                         b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
 858                         break;
 859                 }
 860                 radio_stacksave(0x0078);
 861                 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
 862                 B43_WARN_ON(tmp > 15);
 863                 flipped = bitrev4(tmp);
 864                 if (flipped < 10 && flipped >= 8)
 865                         flipped = 7;
 866                 else if (flipped >= 10)
 867                         flipped -= 3;
 868                 flipped = (bitrev4(flipped) << 1) | 0x0020;
 869                 b43_radio_write16(dev, 0x0078, flipped);
 870
 871                 b43_calc_nrssi_threshold(dev);
 872
 873                 phy_stacksave(0x0406);
 874                 b43_phy_write(dev, 0x0406, 0x7E28);
 875
 876                 b43_phy_set(dev, 0x042B, 0x0800);
 877                 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
 878
 879                 phy_stacksave(0x04A0);
 880                 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008);
 881                 phy_stacksave(0x04A1);
 882                 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605);
 883                 phy_stacksave(0x04A2);
 884                 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204);
 885                 phy_stacksave(0x04A8);
 886                 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803);
 887                 phy_stacksave(0x04AB);
 888                 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605);
 889
 890                 phy_stacksave(0x04A7);
 891                 b43_phy_write(dev, 0x04A7, 0x0002);
 892                 phy_stacksave(0x04A3);
 893                 b43_phy_write(dev, 0x04A3, 0x287A);
 894                 phy_stacksave(0x04A9);
 895                 b43_phy_write(dev, 0x04A9, 0x2027);
 896                 phy_stacksave(0x0493);
 897                 b43_phy_write(dev, 0x0493, 0x32F5);
 898                 phy_stacksave(0x04AA);
 899                 b43_phy_write(dev, 0x04AA, 0x2027);
 900                 phy_stacksave(0x04AC);
 901                 b43_phy_write(dev, 0x04AC, 0x32F5);
 902                 break;
 903         case B43_INTERFMODE_MANUALWLAN:
 904                 if (b43_phy_read(dev, 0x0033) & 0x0800)
 905                         break;
 906
 907                 gphy->aci_enable = 1;
 908
 909                 phy_stacksave(B43_PHY_RADIO_BITFIELD);
 910                 phy_stacksave(B43_PHY_G_CRS);
 911                 if (phy->rev < 2) {
 912                         phy_stacksave(0x0406);
 913                 } else {
 914                         phy_stacksave(0x04C0);
 915                         phy_stacksave(0x04C1);
 916                 }
 917                 phy_stacksave(0x0033);
 918                 phy_stacksave(0x04A7);
 919                 phy_stacksave(0x04A3);
 920                 phy_stacksave(0x04A9);
 921                 phy_stacksave(0x04AA);
 922                 phy_stacksave(0x04AC);
 923                 phy_stacksave(0x0493);
 924                 phy_stacksave(0x04A1);
 925                 phy_stacksave(0x04A0);
 926                 phy_stacksave(0x04A2);
 927                 phy_stacksave(0x048A);
 928                 phy_stacksave(0x04A8);
 929                 phy_stacksave(0x04AB);
 930                 if (phy->rev == 2) {
 931                         phy_stacksave(0x04AD);
 932                         phy_stacksave(0x04AE);
 933                 } else if (phy->rev >= 3) {
 934                         phy_stacksave(0x04AD);
 935                         phy_stacksave(0x0415);
 936                         phy_stacksave(0x0416);
 937                         phy_stacksave(0x0417);
 938                         ofdmtab_stacksave(0x1A00, 0x2);
 939                         ofdmtab_stacksave(0x1A00, 0x3);
 940                 }
 941                 phy_stacksave(0x042B);
 942                 phy_stacksave(0x048C);
 943
 944                 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
 945                 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002);
 946
 947                 b43_phy_write(dev, 0x0033, 0x0800);
 948                 b43_phy_write(dev, 0x04A3, 0x2027);
 949                 b43_phy_write(dev, 0x04A9, 0x1CA8);
 950                 b43_phy_write(dev, 0x0493, 0x287A);
 951                 b43_phy_write(dev, 0x04AA, 0x1CA8);
 952                 b43_phy_write(dev, 0x04AC, 0x287A);
 953
 954                 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A);
 955                 b43_phy_write(dev, 0x04A7, 0x000D);
 956
 957                 if (phy->rev < 2) {
 958                         b43_phy_write(dev, 0x0406, 0xFF0D);
 959                 } else if (phy->rev == 2) {
 960                         b43_phy_write(dev, 0x04C0, 0xFFFF);
 961                         b43_phy_write(dev, 0x04C1, 0x00A9);
 962                 } else {
 963                         b43_phy_write(dev, 0x04C0, 0x00C1);
 964                         b43_phy_write(dev, 0x04C1, 0x0059);
 965                 }
 966
 967                 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800);
 968                 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015);
 969                 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000);
 970                 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00);
 971                 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000);
 972                 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800);
 973                 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010);
 974                 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005);
 975                 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010);
 976                 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006);
 977                 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800);
 978                 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500);
 979                 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B);
 980
 981                 if (phy->rev >= 3) {
 982                         b43_phy_mask(dev, 0x048A, ~0x8000);
 983                         b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8);
 984                         b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8);
 985                         b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D);
 986                 } else {
 987                         b43_phy_set(dev, 0x048A, 0x1000);
 988                         b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000);
 989                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
 990                 }
 991                 if (phy->rev >= 2) {
 992                         b43_phy_set(dev, 0x042B, 0x0800);
 993                 }
 994                 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200);
 995                 if (phy->rev == 2) {
 996                         b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F);
 997                         b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300);
 998                 } else if (phy->rev >= 6) {
 999                         b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1000                         b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
1001                         b43_phy_mask(dev, 0x04AD, 0x00FF);
1002                 }
1003                 b43_calc_nrssi_slope(dev);
1004                 break;
1005         default:
1006                 B43_WARN_ON(1);
1007         }
1008 }
1009
1010 static void
1011 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1012 {
1013         struct b43_phy *phy = &dev->phy;
1014         struct b43_phy_g *gphy = phy->g;
1015         u32 *stack = gphy->interfstack;
1016
1017         switch (mode) {
1018         case B43_INTERFMODE_NONWLAN:
1019                 if (phy->rev != 1) {
1020                         b43_phy_mask(dev, 0x042B, ~0x0800);
1021                         b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1022                         break;
1023                 }
1024                 radio_stackrestore(0x0078);
1025                 b43_calc_nrssi_threshold(dev);
1026                 phy_stackrestore(0x0406);
1027                 b43_phy_mask(dev, 0x042B, ~0x0800);
1028                 if (!dev->bad_frames_preempt) {
1029                         b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1030                 }
1031                 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1032                 phy_stackrestore(0x04A0);
1033                 phy_stackrestore(0x04A1);
1034                 phy_stackrestore(0x04A2);
1035                 phy_stackrestore(0x04A8);
1036                 phy_stackrestore(0x04AB);
1037                 phy_stackrestore(0x04A7);
1038                 phy_stackrestore(0x04A3);
1039                 phy_stackrestore(0x04A9);
1040                 phy_stackrestore(0x0493);
1041                 phy_stackrestore(0x04AA);
1042                 phy_stackrestore(0x04AC);
1043                 break;
1044         case B43_INTERFMODE_MANUALWLAN:
1045                 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1046                         break;
1047
1048                 gphy->aci_enable = 0;
1049
1050                 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1051                 phy_stackrestore(B43_PHY_G_CRS);
1052                 phy_stackrestore(0x0033);
1053                 phy_stackrestore(0x04A3);
1054                 phy_stackrestore(0x04A9);
1055                 phy_stackrestore(0x0493);
1056                 phy_stackrestore(0x04AA);
1057                 phy_stackrestore(0x04AC);
1058                 phy_stackrestore(0x04A0);
1059                 phy_stackrestore(0x04A7);
1060                 if (phy->rev >= 2) {
1061                         phy_stackrestore(0x04C0);
1062                         phy_stackrestore(0x04C1);
1063                 } else
1064                         phy_stackrestore(0x0406);
1065                 phy_stackrestore(0x04A1);
1066                 phy_stackrestore(0x04AB);
1067                 phy_stackrestore(0x04A8);
1068                 if (phy->rev == 2) {
1069                         phy_stackrestore(0x04AD);
1070                         phy_stackrestore(0x04AE);
1071                 } else if (phy->rev >= 3) {
1072                         phy_stackrestore(0x04AD);
1073                         phy_stackrestore(0x0415);
1074                         phy_stackrestore(0x0416);
1075                         phy_stackrestore(0x0417);
1076                         ofdmtab_stackrestore(0x1A00, 0x2);
1077                         ofdmtab_stackrestore(0x1A00, 0x3);
1078                 }
1079                 phy_stackrestore(0x04A2);
1080                 phy_stackrestore(0x048A);
1081                 phy_stackrestore(0x042B);
1082                 phy_stackrestore(0x048C);
1083                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1084                 b43_calc_nrssi_slope(dev);
1085                 break;
1086         default:
1087                 B43_WARN_ON(1);
1088         }
1089 }
1090
1091 #undef phy_stacksave
1092 #undef phy_stackrestore
1093 #undef radio_stacksave
1094 #undef radio_stackrestore
1095 #undef ofdmtab_stacksave
1096 #undef ofdmtab_stackrestore
1097
1098 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1099 {
1100         u16 reg, index, ret;
1101
1102         static const u8 rcc_table[] = {
1103                 0x02, 0x03, 0x01, 0x0F,
1104                 0x06, 0x07, 0x05, 0x0F,
1105                 0x0A, 0x0B, 0x09, 0x0F,
1106                 0x0E, 0x0F, 0x0D, 0x0F,
1107         };
1108
1109         reg = b43_radio_read16(dev, 0x60);
1110         index = (reg & 0x001E) >> 1;
1111         ret = rcc_table[index] << 1;
1112         ret |= (reg & 0x0001);
1113         ret |= 0x0020;
1114
1115         return ret;
1116 }
1117
1118 #define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
1119 static u16 radio2050_rfover_val(struct b43_wldev *dev,
1120                                 u16 phy_register, unsigned int lpd)
1121 {
1122         struct b43_phy *phy = &dev->phy;
1123         struct b43_phy_g *gphy = phy->g;
1124         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1125
1126         if (!phy->gmode)
1127                 return 0;
1128
1129         if (has_loopback_gain(phy)) {
1130                 int max_lb_gain = gphy->max_lb_gain;
1131                 u16 extlna;
1132                 u16 i;
1133
1134                 if (phy->radio_rev == 8)
1135                         max_lb_gain += 0x3E;
1136                 else
1137                         max_lb_gain += 0x26;
1138                 if (max_lb_gain >= 0x46) {
1139                         extlna = 0x3000;
1140                         max_lb_gain -= 0x46;
1141                 } else if (max_lb_gain >= 0x3A) {
1142                         extlna = 0x1000;
1143                         max_lb_gain -= 0x3A;
1144                 } else if (max_lb_gain >= 0x2E) {
1145                         extlna = 0x2000;
1146                         max_lb_gain -= 0x2E;
1147                 } else {
1148                         extlna = 0;
1149                         max_lb_gain -= 0x10;
1150                 }
1151
1152                 for (i = 0; i < 16; i++) {
1153                         max_lb_gain -= (i * 6);
1154                         if (max_lb_gain < 6)
1155                                 break;
1156                 }
1157
1158                 if ((phy->rev < 7) ||
1159                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1160                         if (phy_register == B43_PHY_RFOVER) {
1161                                 return 0x1B3;
1162                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1163                                 extlna |= (i << 8);
1164                                 switch (lpd) {
1165                                 case LPD(0, 1, 1):
1166                                         return 0x0F92;
1167                                 case LPD(0, 0, 1):
1168                                 case LPD(1, 0, 1):
1169                                         return (0x0092 | extlna);
1170                                 case LPD(1, 0, 0):
1171                                         return (0x0093 | extlna);
1172                                 }
1173                                 B43_WARN_ON(1);
1174                         }
1175                         B43_WARN_ON(1);
1176                 } else {
1177                         if (phy_register == B43_PHY_RFOVER) {
1178                                 return 0x9B3;
1179                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1180                                 if (extlna)
1181                                         extlna |= 0x8000;
1182                                 extlna |= (i << 8);
1183                                 switch (lpd) {
1184                                 case LPD(0, 1, 1):
1185                                         return 0x8F92;
1186                                 case LPD(0, 0, 1):
1187                                         return (0x8092 | extlna);
1188                                 case LPD(1, 0, 1):
1189                                         return (0x2092 | extlna);
1190                                 case LPD(1, 0, 0):
1191                                         return (0x2093 | extlna);
1192                                 }
1193                                 B43_WARN_ON(1);
1194                         }
1195                         B43_WARN_ON(1);
1196                 }
1197         } else {
1198                 if ((phy->rev < 7) ||
1199                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1200                         if (phy_register == B43_PHY_RFOVER) {
1201                                 return 0x1B3;
1202                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1203                                 switch (lpd) {
1204                                 case LPD(0, 1, 1):
1205                                         return 0x0FB2;
1206                                 case LPD(0, 0, 1):
1207                                         return 0x00B2;
1208                                 case LPD(1, 0, 1):
1209                                         return 0x30B2;
1210                                 case LPD(1, 0, 0):
1211                                         return 0x30B3;
1212                                 }
1213                                 B43_WARN_ON(1);
1214                         }
1215                         B43_WARN_ON(1);
1216                 } else {
1217                         if (phy_register == B43_PHY_RFOVER) {
1218                                 return 0x9B3;
1219                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1220                                 switch (lpd) {
1221                                 case LPD(0, 1, 1):
1222                                         return 0x8FB2;
1223                                 case LPD(0, 0, 1):
1224                                         return 0x80B2;
1225                                 case LPD(1, 0, 1):
1226                                         return 0x20B2;
1227                                 case LPD(1, 0, 0):
1228                                         return 0x20B3;
1229                                 }
1230                                 B43_WARN_ON(1);
1231                         }
1232                         B43_WARN_ON(1);
1233                 }
1234         }
1235         return 0;
1236 }
1237
1238 struct init2050_saved_values {
1239         /* Core registers */
1240         u16 reg_3EC;
1241         u16 reg_3E6;
1242         u16 reg_3F4;
1243         /* Radio registers */
1244         u16 radio_43;
1245         u16 radio_51;
1246         u16 radio_52;
1247         /* PHY registers */
1248         u16 phy_pgactl;
1249         u16 phy_cck_5A;
1250         u16 phy_cck_59;
1251         u16 phy_cck_58;
1252         u16 phy_cck_30;
1253         u16 phy_rfover;
1254         u16 phy_rfoverval;
1255         u16 phy_analogover;
1256         u16 phy_analogoverval;
1257         u16 phy_crs0;
1258         u16 phy_classctl;
1259         u16 phy_lo_mask;
1260         u16 phy_lo_ctl;
1261         u16 phy_syncctl;
1262 };
1263
1264 static u16 b43_radio_init2050(struct b43_wldev *dev)
1265 {
1266         struct b43_phy *phy = &dev->phy;
1267         struct init2050_saved_values sav;
1268         u16 rcc;
1269         u16 radio78;
1270         u16 ret;
1271         u16 i, j;
1272         u32 tmp1 = 0, tmp2 = 0;
1273
1274         memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
1275
1276         sav.radio_43 = b43_radio_read16(dev, 0x43);
1277         sav.radio_51 = b43_radio_read16(dev, 0x51);
1278         sav.radio_52 = b43_radio_read16(dev, 0x52);
1279         sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1280         sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1281         sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1282         sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1283
1284         if (phy->type == B43_PHYTYPE_B) {
1285                 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1286                 sav.reg_3EC = b43_read16(dev, 0x3EC);
1287
1288                 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1289                 b43_write16(dev, 0x3EC, 0x3F3F);
1290         } else if (phy->gmode || phy->rev >= 2) {
1291                 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1292                 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1293                 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1294                 sav.phy_analogoverval =
1295                     b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1296                 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1297                 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1298
1299                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1300                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1301                 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1302                 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1303                 if (has_loopback_gain(phy)) {
1304                         sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1305                         sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1306
1307                         if (phy->rev >= 3)
1308                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1309                         else
1310                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1311                         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1312                 }
1313
1314                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1315                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1316                                                    LPD(0, 1, 1)));
1317                 b43_phy_write(dev, B43_PHY_RFOVER,
1318                               radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1319         }
1320         b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1321
1322         sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1323         b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1324         sav.reg_3E6 = b43_read16(dev, 0x3E6);
1325         sav.reg_3F4 = b43_read16(dev, 0x3F4);
1326
1327         if (phy->analog == 0) {
1328                 b43_write16(dev, 0x03E6, 0x0122);
1329         } else {
1330                 if (phy->analog >= 2) {
1331                         b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40);
1332                 }
1333                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1334                             (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1335         }
1336
1337         rcc = b43_radio_core_calibration_value(dev);
1338
1339         if (phy->type == B43_PHYTYPE_B)
1340                 b43_radio_write16(dev, 0x78, 0x26);
1341         if (phy->gmode || phy->rev >= 2) {
1342                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1343                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1344                                                    LPD(0, 1, 1)));
1345         }
1346         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1347         b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1348         if (phy->gmode || phy->rev >= 2) {
1349                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1350                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1351                                                    LPD(0, 0, 1)));
1352         }
1353         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1354         b43_radio_set(dev, 0x51, 0x0004);
1355         if (phy->radio_rev == 8) {
1356                 b43_radio_write16(dev, 0x43, 0x1F);
1357         } else {
1358                 b43_radio_write16(dev, 0x52, 0);
1359                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1360                                               & 0xFFF0) | 0x0009);
1361         }
1362         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1363
1364         for (i = 0; i < 16; i++) {
1365                 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1366                 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1367                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1368                 if (phy->gmode || phy->rev >= 2) {
1369                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1370                                       radio2050_rfover_val(dev,
1371                                                            B43_PHY_RFOVERVAL,
1372                                                            LPD(1, 0, 1)));
1373                 }
1374                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1375                 udelay(10);
1376                 if (phy->gmode || phy->rev >= 2) {
1377                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1378                                       radio2050_rfover_val(dev,
1379                                                            B43_PHY_RFOVERVAL,
1380                                                            LPD(1, 0, 1)));
1381                 }
1382                 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1383                 udelay(10);
1384                 if (phy->gmode || phy->rev >= 2) {
1385                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1386                                       radio2050_rfover_val(dev,
1387                                                            B43_PHY_RFOVERVAL,
1388                                                            LPD(1, 0, 0)));
1389                 }
1390                 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1391                 udelay(20);
1392                 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1393                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1394                 if (phy->gmode || phy->rev >= 2) {
1395                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1396                                       radio2050_rfover_val(dev,
1397                                                            B43_PHY_RFOVERVAL,
1398                                                            LPD(1, 0, 1)));
1399                 }
1400                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1401         }
1402         udelay(10);
1403
1404         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1405         tmp1++;
1406         tmp1 >>= 9;
1407
1408         for (i = 0; i < 16; i++) {
1409                 radio78 = (bitrev4(i) << 1) | 0x0020;
1410                 b43_radio_write16(dev, 0x78, radio78);
1411                 udelay(10);
1412                 for (j = 0; j < 16; j++) {
1413                         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1414                         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1415                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1416                         if (phy->gmode || phy->rev >= 2) {
1417                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1418                                               radio2050_rfover_val(dev,
1419                                                                    B43_PHY_RFOVERVAL,
1420                                                                    LPD(1, 0,
1421                                                                        1)));
1422                         }
1423                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1424                         udelay(10);
1425                         if (phy->gmode || phy->rev >= 2) {
1426                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1427                                               radio2050_rfover_val(dev,
1428                                                                    B43_PHY_RFOVERVAL,
1429                                                                    LPD(1, 0,
1430                                                                        1)));
1431                         }
1432                         b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1433                         udelay(10);
1434                         if (phy->gmode || phy->rev >= 2) {
1435                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1436                                               radio2050_rfover_val(dev,
1437                                                                    B43_PHY_RFOVERVAL,
1438                                                                    LPD(1, 0,
1439                                                                        0)));
1440                         }
1441                         b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1442                         udelay(10);
1443                         tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1444                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1445                         if (phy->gmode || phy->rev >= 2) {
1446                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1447                                               radio2050_rfover_val(dev,
1448                                                                    B43_PHY_RFOVERVAL,
1449                                                                    LPD(1, 0,
1450                                                                        1)));
1451                         }
1452                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1453                 }
1454                 tmp2++;
1455                 tmp2 >>= 8;
1456                 if (tmp1 < tmp2)
1457                         break;
1458         }
1459
1460         /* Restore the registers */
1461         b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1462         b43_radio_write16(dev, 0x51, sav.radio_51);
1463         b43_radio_write16(dev, 0x52, sav.radio_52);
1464         b43_radio_write16(dev, 0x43, sav.radio_43);
1465         b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1466         b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1467         b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1468         b43_write16(dev, 0x3E6, sav.reg_3E6);
1469         if (phy->analog != 0)
1470                 b43_write16(dev, 0x3F4, sav.reg_3F4);
1471         b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1472         b43_synth_pu_workaround(dev, phy->channel);
1473         if (phy->type == B43_PHYTYPE_B) {
1474                 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1475                 b43_write16(dev, 0x3EC, sav.reg_3EC);
1476         } else if (phy->gmode) {
1477                 b43_write16(dev, B43_MMIO_PHY_RADIO,
1478                             b43_read16(dev, B43_MMIO_PHY_RADIO)
1479                             & 0x7FFF);
1480                 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1481                 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1482                 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1483                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1484                               sav.phy_analogoverval);
1485                 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1486                 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1487                 if (has_loopback_gain(phy)) {
1488                         b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1489                         b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1490                 }
1491         }
1492         if (i > 15)
1493                 ret = radio78;
1494         else
1495                 ret = rcc;
1496
1497         return ret;
1498 }
1499
1500 static void b43_phy_initb5(struct b43_wldev *dev)
1501 {
1502         struct ssb_bus *bus = dev->dev->bus;
1503         struct b43_phy *phy = &dev->phy;
1504         struct b43_phy_g *gphy = phy->g;
1505         u16 offset, value;
1506         u8 old_channel;
1507
1508         if (phy->analog == 1) {
1509                 b43_radio_set(dev, 0x007A, 0x0050);
1510         }
1511         if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1512             (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1513                 value = 0x2120;
1514                 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1515                         b43_phy_write(dev, offset, value);
1516                         value += 0x202;
1517                 }
1518         }
1519         b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700);
1520         if (phy->radio_ver == 0x2050)
1521                 b43_phy_write(dev, 0x0038, 0x0667);
1522
1523         if (phy->gmode || phy->rev >= 2) {
1524                 if (phy->radio_ver == 0x2050) {
1525                         b43_radio_set(dev, 0x007A, 0x0020);
1526                         b43_radio_set(dev, 0x0051, 0x0004);
1527                 }
1528                 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1529
1530                 b43_phy_set(dev, 0x0802, 0x0100);
1531                 b43_phy_set(dev, 0x042B, 0x2000);
1532
1533                 b43_phy_write(dev, 0x001C, 0x186A);
1534
1535                 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900);
1536                 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064);
1537                 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A);
1538         }
1539
1540         if (dev->bad_frames_preempt) {
1541                 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11));
1542         }
1543
1544         if (phy->analog == 1) {
1545                 b43_phy_write(dev, 0x0026, 0xCE00);
1546                 b43_phy_write(dev, 0x0021, 0x3763);
1547                 b43_phy_write(dev, 0x0022, 0x1BC3);
1548                 b43_phy_write(dev, 0x0023, 0x06F9);
1549                 b43_phy_write(dev, 0x0024, 0x037E);
1550         } else
1551                 b43_phy_write(dev, 0x0026, 0xCC00);
1552         b43_phy_write(dev, 0x0030, 0x00C6);
1553         b43_write16(dev, 0x03EC, 0x3F22);
1554
1555         if (phy->analog == 1)
1556                 b43_phy_write(dev, 0x0020, 0x3E1C);
1557         else
1558                 b43_phy_write(dev, 0x0020, 0x301C);
1559
1560         if (phy->analog == 0)
1561                 b43_write16(dev, 0x03E4, 0x3000);
1562
1563         old_channel = phy->channel;
1564         /* Force to channel 7, even if not supported. */
1565         b43_gphy_channel_switch(dev, 7, 0);
1566
1567         if (phy->radio_ver != 0x2050) {
1568                 b43_radio_write16(dev, 0x0075, 0x0080);
1569                 b43_radio_write16(dev, 0x0079, 0x0081);
1570         }
1571
1572         b43_radio_write16(dev, 0x0050, 0x0020);
1573         b43_radio_write16(dev, 0x0050, 0x0023);
1574
1575         if (phy->radio_ver == 0x2050) {
1576                 b43_radio_write16(dev, 0x0050, 0x0020);
1577                 b43_radio_write16(dev, 0x005A, 0x0070);
1578         }
1579
1580         b43_radio_write16(dev, 0x005B, 0x007B);
1581         b43_radio_write16(dev, 0x005C, 0x00B0);
1582
1583         b43_radio_set(dev, 0x007A, 0x0007);
1584
1585         b43_gphy_channel_switch(dev, old_channel, 0);
1586
1587         b43_phy_write(dev, 0x0014, 0x0080);
1588         b43_phy_write(dev, 0x0032, 0x00CA);
1589         b43_phy_write(dev, 0x002A, 0x88A3);
1590
1591         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1592
1593         if (phy->radio_ver == 0x2050)
1594                 b43_radio_write16(dev, 0x005D, 0x000D);
1595
1596         b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1597 }
1598
1599 static void b43_phy_initb6(struct b43_wldev *dev)
1600 {
1601         struct b43_phy *phy = &dev->phy;
1602         struct b43_phy_g *gphy = phy->g;
1603         u16 offset, val;
1604         u8 old_channel;
1605
1606         b43_phy_write(dev, 0x003E, 0x817A);
1607         b43_radio_write16(dev, 0x007A,
1608                           (b43_radio_read16(dev, 0x007A) | 0x0058));
1609         if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1610                 b43_radio_write16(dev, 0x51, 0x37);
1611                 b43_radio_write16(dev, 0x52, 0x70);
1612                 b43_radio_write16(dev, 0x53, 0xB3);
1613                 b43_radio_write16(dev, 0x54, 0x9B);
1614                 b43_radio_write16(dev, 0x5A, 0x88);
1615                 b43_radio_write16(dev, 0x5B, 0x88);
1616                 b43_radio_write16(dev, 0x5D, 0x88);
1617                 b43_radio_write16(dev, 0x5E, 0x88);
1618                 b43_radio_write16(dev, 0x7D, 0x88);
1619                 b43_hf_write(dev, b43_hf_read(dev)
1620                              | B43_HF_TSSIRPSMW);
1621         }
1622         B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
1623         if (phy->radio_rev == 8) {
1624                 b43_radio_write16(dev, 0x51, 0);
1625                 b43_radio_write16(dev, 0x52, 0x40);
1626                 b43_radio_write16(dev, 0x53, 0xB7);
1627                 b43_radio_write16(dev, 0x54, 0x98);
1628                 b43_radio_write16(dev, 0x5A, 0x88);
1629                 b43_radio_write16(dev, 0x5B, 0x6B);
1630                 b43_radio_write16(dev, 0x5C, 0x0F);
1631                 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1632                         b43_radio_write16(dev, 0x5D, 0xFA);
1633                         b43_radio_write16(dev, 0x5E, 0xD8);
1634                 } else {
1635                         b43_radio_write16(dev, 0x5D, 0xF5);
1636                         b43_radio_write16(dev, 0x5E, 0xB8);
1637                 }
1638                 b43_radio_write16(dev, 0x0073, 0x0003);
1639                 b43_radio_write16(dev, 0x007D, 0x00A8);
1640                 b43_radio_write16(dev, 0x007C, 0x0001);
1641                 b43_radio_write16(dev, 0x007E, 0x0008);
1642         }
1643         val = 0x1E1F;
1644         for (offset = 0x0088; offset < 0x0098; offset++) {
1645                 b43_phy_write(dev, offset, val);
1646                 val -= 0x0202;
1647         }
1648         val = 0x3E3F;
1649         for (offset = 0x0098; offset < 0x00A8; offset++) {
1650                 b43_phy_write(dev, offset, val);
1651                 val -= 0x0202;
1652         }
1653         val = 0x2120;
1654         for (offset = 0x00A8; offset < 0x00C8; offset++) {
1655                 b43_phy_write(dev, offset, (val & 0x3F3F));
1656                 val += 0x0202;
1657         }
1658         if (phy->type == B43_PHYTYPE_G) {
1659                 b43_radio_set(dev, 0x007A, 0x0020);
1660                 b43_radio_set(dev, 0x0051, 0x0004);
1661                 b43_phy_set(dev, 0x0802, 0x0100);
1662                 b43_phy_set(dev, 0x042B, 0x2000);
1663                 b43_phy_write(dev, 0x5B, 0);
1664                 b43_phy_write(dev, 0x5C, 0);
1665         }
1666
1667         old_channel = phy->channel;
1668         if (old_channel >= 8)
1669                 b43_gphy_channel_switch(dev, 1, 0);
1670         else
1671                 b43_gphy_channel_switch(dev, 13, 0);
1672
1673         b43_radio_write16(dev, 0x0050, 0x0020);
1674         b43_radio_write16(dev, 0x0050, 0x0023);
1675         udelay(40);
1676         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1677                 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1678                                               | 0x0002));
1679                 b43_radio_write16(dev, 0x50, 0x20);
1680         }
1681         if (phy->radio_rev <= 2) {
1682                 b43_radio_write16(dev, 0x7C, 0x20);
1683                 b43_radio_write16(dev, 0x5A, 0x70);
1684                 b43_radio_write16(dev, 0x5B, 0x7B);
1685                 b43_radio_write16(dev, 0x5C, 0xB0);
1686         }
1687         b43_radio_write16(dev, 0x007A,
1688                           (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1689
1690         b43_gphy_channel_switch(dev, old_channel, 0);
1691
1692         b43_phy_write(dev, 0x0014, 0x0200);
1693         if (phy->radio_rev >= 6)
1694                 b43_phy_write(dev, 0x2A, 0x88C2);
1695         else
1696                 b43_phy_write(dev, 0x2A, 0x8AC0);
1697         b43_phy_write(dev, 0x0038, 0x0668);
1698         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1699         if (phy->radio_rev <= 5) {
1700                 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003);
1701         }
1702         if (phy->radio_rev <= 2)
1703                 b43_radio_write16(dev, 0x005D, 0x000D);
1704
1705         if (phy->analog == 4) {
1706                 b43_write16(dev, 0x3E4, 9);
1707                 b43_phy_mask(dev, 0x61, 0x0FFF);
1708         } else {
1709                 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004);
1710         }
1711         if (phy->type == B43_PHYTYPE_B)
1712                 B43_WARN_ON(1);
1713         else if (phy->type == B43_PHYTYPE_G)
1714                 b43_write16(dev, 0x03E6, 0x0);
1715 }
1716
1717 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1718 {
1719         struct b43_phy *phy = &dev->phy;
1720         struct b43_phy_g *gphy = phy->g;
1721         u16 backup_phy[16] = { 0 };
1722         u16 backup_radio[3];
1723         u16 backup_bband;
1724         u16 i, j, loop_i_max;
1725         u16 trsw_rx;
1726         u16 loop1_outer_done, loop1_inner_done;
1727
1728         backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1729         backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1730         backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1731         backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1732         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1733                 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1734                 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1735         }
1736         backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1737         backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1738         backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1739         backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1740         backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1741         backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1742         backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1743         backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1744         backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1745         backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1746         backup_bband = gphy->bbatt.att;
1747         backup_radio[0] = b43_radio_read16(dev, 0x52);
1748         backup_radio[1] = b43_radio_read16(dev, 0x43);
1749         backup_radio[2] = b43_radio_read16(dev, 0x7A);
1750
1751         b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1752         b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1753         b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1754         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1755         b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1756         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1757         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1758                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1759                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1760                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1761                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1762         }
1763         b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1764         b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1765         b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1766         b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10);
1767
1768         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1769         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1770         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1771
1772         b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1773         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1774                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1775                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1776         }
1777         b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40);
1778
1779         if (phy->radio_rev == 8) {
1780                 b43_radio_write16(dev, 0x43, 0x000F);
1781         } else {
1782                 b43_radio_write16(dev, 0x52, 0);
1783                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1784                                               & 0xFFF0) | 0x9);
1785         }
1786         b43_gphy_set_baseband_attenuation(dev, 11);
1787
1788         if (phy->rev >= 3)
1789                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1790         else
1791                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1792         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1793
1794         b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01);
1795         b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800);
1796
1797         b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1798         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1799
1800         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1801                 if (phy->rev >= 7) {
1802                         b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1803                         b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
1804                 }
1805         }
1806         b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1807                           & 0x00F7);
1808
1809         j = 0;
1810         loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1811         for (i = 0; i < loop_i_max; i++) {
1812                 for (j = 0; j < 16; j++) {
1813                         b43_radio_write16(dev, 0x43, i);
1814                         b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1815                         b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1816                         b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1817                         udelay(20);
1818                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1819                                 goto exit_loop1;
1820                 }
1821         }
1822       exit_loop1:
1823         loop1_outer_done = i;
1824         loop1_inner_done = j;
1825         if (j >= 8) {
1826                 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1827                 trsw_rx = 0x1B;
1828                 for (j = j - 8; j < 16; j++) {
1829                         b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1830                         b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1831                         b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1832                         udelay(20);
1833                         trsw_rx -= 3;
1834                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1835                                 goto exit_loop2;
1836                 }
1837         } else
1838                 trsw_rx = 0x18;
1839       exit_loop2:
1840
1841         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1842                 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1843                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1844         }
1845         b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1846         b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1847         b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1848         b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1849         b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1850         b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1851         b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1852         b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1853         b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1854
1855         b43_gphy_set_baseband_attenuation(dev, backup_bband);
1856
1857         b43_radio_write16(dev, 0x52, backup_radio[0]);
1858         b43_radio_write16(dev, 0x43, backup_radio[1]);
1859         b43_radio_write16(dev, 0x7A, backup_radio[2]);
1860
1861         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1862         udelay(10);
1863         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1864         b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1865         b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1866         b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1867
1868         gphy->max_lb_gain =
1869             ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1870         gphy->trsw_rx_gain = trsw_rx * 2;
1871 }
1872
1873 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1874 {
1875         struct b43_phy *phy = &dev->phy;
1876
1877         if (!b43_has_hardware_pctl(dev)) {
1878                 b43_phy_write(dev, 0x047A, 0xC111);
1879                 return;
1880         }
1881
1882         b43_phy_mask(dev, 0x0036, 0xFEFF);
1883         b43_phy_write(dev, 0x002F, 0x0202);
1884         b43_phy_set(dev, 0x047C, 0x0002);
1885         b43_phy_set(dev, 0x047A, 0xF000);
1886         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
1887                 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1888                 b43_phy_set(dev, 0x005D, 0x8000);
1889                 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1890                 b43_phy_write(dev, 0x002E, 0xC07F);
1891                 b43_phy_set(dev, 0x0036, 0x0400);
1892         } else {
1893                 b43_phy_set(dev, 0x0036, 0x0200);
1894                 b43_phy_set(dev, 0x0036, 0x0400);
1895                 b43_phy_mask(dev, 0x005D, 0x7FFF);
1896                 b43_phy_mask(dev, 0x004F, 0xFFFE);
1897                 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1898                 b43_phy_write(dev, 0x002E, 0xC07F);
1899                 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1900         }
1901 }
1902
1903 /* Hardware power control for G-PHY */
1904 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1905 {
1906         struct b43_phy *phy = &dev->phy;
1907         struct b43_phy_g *gphy = phy->g;
1908
1909         if (!b43_has_hardware_pctl(dev)) {
1910                 /* No hardware power control */
1911                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
1912                 return;
1913         }
1914
1915         b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1916         b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1917         b43_gphy_tssi_power_lt_init(dev);
1918         b43_gphy_gain_lt_init(dev);
1919         b43_phy_mask(dev, 0x0060, 0xFFBF);
1920         b43_phy_write(dev, 0x0014, 0x0000);
1921
1922         B43_WARN_ON(phy->rev < 6);
1923         b43_phy_set(dev, 0x0478, 0x0800);
1924         b43_phy_mask(dev, 0x0478, 0xFEFF);
1925         b43_phy_mask(dev, 0x0801, 0xFFBF);
1926
1927         b43_gphy_dc_lt_init(dev, 1);
1928
1929         /* Enable hardware pctl in firmware. */
1930         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
1931 }
1932
1933 /* Intialize B/G PHY power control */
1934 static void b43_phy_init_pctl(struct b43_wldev *dev)
1935 {
1936         struct ssb_bus *bus = dev->dev->bus;
1937         struct b43_phy *phy = &dev->phy;
1938         struct b43_phy_g *gphy = phy->g;
1939         struct b43_rfatt old_rfatt;
1940         struct b43_bbatt old_bbatt;
1941         u8 old_tx_control = 0;
1942
1943         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
1944
1945         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1946             (bus->boardinfo.type == SSB_BOARD_BU4306))
1947                 return;
1948
1949         b43_phy_write(dev, 0x0028, 0x8018);
1950
1951         /* This does something with the Analog... */
1952         b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
1953                     & 0xFFDF);
1954
1955         if (!phy->gmode)
1956                 return;
1957         b43_hardware_pctl_early_init(dev);
1958         if (gphy->cur_idle_tssi == 0) {
1959                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1960                         b43_radio_write16(dev, 0x0076,
1961                                           (b43_radio_read16(dev, 0x0076)
1962                                            & 0x00F7) | 0x0084);
1963                 } else {
1964                         struct b43_rfatt rfatt;
1965                         struct b43_bbatt bbatt;
1966
1967                         memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
1968                         memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
1969                         old_tx_control = gphy->tx_control;
1970
1971                         bbatt.att = 11;
1972                         if (phy->radio_rev == 8) {
1973                                 rfatt.att = 15;
1974                                 rfatt.with_padmix = 1;
1975                         } else {
1976                                 rfatt.att = 9;
1977                                 rfatt.with_padmix = 0;
1978                         }
1979                         b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
1980                 }
1981                 b43_dummy_transmission(dev);
1982                 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
1983                 if (B43_DEBUG) {
1984                         /* Current-Idle-TSSI sanity check. */
1985                         if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
1986                                 b43dbg(dev->wl,
1987                                        "!WARNING! Idle-TSSI phy->cur_idle_tssi "
1988                                        "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
1989                                        "adjustment.\n", gphy->cur_idle_tssi,
1990                                        gphy->tgt_idle_tssi);
1991                                 gphy->cur_idle_tssi = 0;
1992                         }
1993                 }
1994                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1995                         b43_radio_write16(dev, 0x0076,
1996                                           b43_radio_read16(dev, 0x0076)
1997                                           & 0xFF7B);
1998                 } else {
1999                         b43_set_txpower_g(dev, &old_bbatt,
2000                                           &old_rfatt, old_tx_control);
2001                 }
2002         }
2003         b43_hardware_pctl_init_gphy(dev);
2004         b43_shm_clear_tssi(dev);
2005 }
2006
2007 static void b43_phy_initg(struct b43_wldev *dev)
2008 {
2009         struct b43_phy *phy = &dev->phy;
2010         struct b43_phy_g *gphy = phy->g;
2011         u16 tmp;
2012
2013         if (phy->rev == 1)
2014                 b43_phy_initb5(dev);
2015         else
2016                 b43_phy_initb6(dev);
2017
2018         if (phy->rev >= 2 || phy->gmode)
2019                 b43_phy_inita(dev);
2020
2021         if (phy->rev >= 2) {
2022                 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2023                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2024         }
2025         if (phy->rev == 2) {
2026                 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2027                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2028         }
2029         if (phy->rev > 5) {
2030                 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2031                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2032         }
2033         if (phy->gmode || phy->rev >= 2) {
2034                 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2035                 tmp &= B43_PHYVER_VERSION;
2036                 if (tmp == 3 || tmp == 5) {
2037                         b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2038                         b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2039                 }
2040                 if (tmp == 5) {
2041                         b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00);
2042                 }
2043         }
2044         if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2045                 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2046         if (phy->radio_rev == 8) {
2047                 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80);
2048                 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4);
2049         }
2050         if (has_loopback_gain(phy))
2051                 b43_calc_loopback_gain(dev);
2052
2053         if (phy->radio_rev != 8) {
2054                 if (gphy->initval == 0xFFFF)
2055                         gphy->initval = b43_radio_init2050(dev);
2056                 else
2057                         b43_radio_write16(dev, 0x0078, gphy->initval);
2058         }
2059         b43_lo_g_init(dev);
2060         if (has_tx_magnification(phy)) {
2061                 b43_radio_write16(dev, 0x52,
2062                                   (b43_radio_read16(dev, 0x52) & 0xFF00)
2063                                   | gphy->lo_control->tx_bias | gphy->
2064                                   lo_control->tx_magn);
2065         } else {
2066                 b43_radio_write16(dev, 0x52,
2067                                   (b43_radio_read16(dev, 0x52) & 0xFFF0)
2068                                   | gphy->lo_control->tx_bias);
2069         }
2070         if (phy->rev >= 6) {
2071                 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2072         }
2073         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2074                 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2075         else
2076                 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2077         if (phy->rev < 2)
2078                 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2079         else
2080                 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2081         if (phy->gmode || phy->rev >= 2) {
2082                 b43_lo_g_adjust(dev);
2083                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2084         }
2085
2086         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2087                 /* The specs state to update the NRSSI LT with
2088                  * the value 0x7FFFFFFF here. I think that is some weird
2089                  * compiler optimization in the original driver.
2090                  * Essentially, what we do here is resetting all NRSSI LT
2091                  * entries to -32 (see the clamp_val() in nrssi_hw_update())
2092                  */
2093                 b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
2094                 b43_calc_nrssi_threshold(dev);
2095         } else if (phy->gmode || phy->rev >= 2) {
2096                 if (gphy->nrssi[0] == -1000) {
2097                         B43_WARN_ON(gphy->nrssi[1] != -1000);
2098                         b43_calc_nrssi_slope(dev);
2099                 } else
2100                         b43_calc_nrssi_threshold(dev);
2101         }
2102         if (phy->radio_rev == 8)
2103                 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2104         b43_phy_init_pctl(dev);
2105         /* FIXME: The spec says in the following if, the 0 should be replaced
2106            'if OFDM may not be used in the current locale'
2107            but OFDM is legal everywhere */
2108         if ((dev->dev->bus->chip_id == 0x4306
2109              && dev->dev->bus->chip_package == 2) || 0) {
2110                 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2111                 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2112         }
2113 }
2114
2115 void b43_gphy_channel_switch(struct b43_wldev *dev,
2116                              unsigned int channel,
2117                              bool synthetic_pu_workaround)
2118 {
2119         if (synthetic_pu_workaround)
2120                 b43_synth_pu_workaround(dev, channel);
2121
2122         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2123
2124         if (channel == 14) {
2125                 if (dev->dev->bus->sprom.country_code ==
2126                     SSB_SPROM1CCODE_JAPAN)
2127                         b43_hf_write(dev,
2128                                      b43_hf_read(dev) & ~B43_HF_ACPR);
2129                 else
2130                         b43_hf_write(dev,
2131                                      b43_hf_read(dev) | B43_HF_ACPR);
2132                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2133                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2134                             | (1 << 11));
2135         } else {
2136                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2137                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2138                             & 0xF7BF);
2139         }
2140 }
2141
2142 static void default_baseband_attenuation(struct b43_wldev *dev,
2143                                          struct b43_bbatt *bb)
2144 {
2145         struct b43_phy *phy = &dev->phy;
2146
2147         if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2148                 bb->att = 0;
2149         else
2150                 bb->att = 2;
2151 }
2152
2153 static void default_radio_attenuation(struct b43_wldev *dev,
2154                                       struct b43_rfatt *rf)
2155 {
2156         struct ssb_bus *bus = dev->dev->bus;
2157         struct b43_phy *phy = &dev->phy;
2158
2159         rf->with_padmix = 0;
2160
2161         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2162             bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2163                 if (bus->boardinfo.rev < 0x43) {
2164                         rf->att = 2;
2165                         return;
2166                 } else if (bus->boardinfo.rev < 0x51) {
2167                         rf->att = 3;
2168                         return;
2169                 }
2170         }
2171
2172         if (phy->type == B43_PHYTYPE_A) {
2173                 rf->att = 0x60;
2174                 return;
2175         }
2176
2177         switch (phy->radio_ver) {
2178         case 0x2053:
2179                 switch (phy->radio_rev) {
2180                 case 1:
2181                         rf->att = 6;
2182                         return;
2183                 }
2184                 break;
2185         case 0x2050:
2186                 switch (phy->radio_rev) {
2187                 case 0:
2188                         rf->att = 5;
2189                         return;
2190                 case 1:
2191                         if (phy->type == B43_PHYTYPE_G) {
2192                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2193                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2194                                     && bus->boardinfo.rev >= 30)
2195                                         rf->att = 3;
2196                                 else if (bus->boardinfo.vendor ==
2197                                          SSB_BOARDVENDOR_BCM
2198                                          && bus->boardinfo.type ==
2199                                          SSB_BOARD_BU4306)
2200                                         rf->att = 3;
2201                                 else
2202                                         rf->att = 1;
2203                         } else {
2204                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2205                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2206                                     && bus->boardinfo.rev >= 30)
2207                                         rf->att = 7;
2208                                 else
2209                                         rf->att = 6;
2210                         }
2211                         return;
2212                 case 2:
2213                         if (phy->type == B43_PHYTYPE_G) {
2214                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2215                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2216                                     && bus->boardinfo.rev >= 30)
2217                                         rf->att = 3;
2218                                 else if (bus->boardinfo.vendor ==
2219                                          SSB_BOARDVENDOR_BCM
2220                                          && bus->boardinfo.type ==
2221                                          SSB_BOARD_BU4306)
2222                                         rf->att = 5;
2223                                 else if (bus->chip_id == 0x4320)
2224                                         rf->att = 4;
2225                                 else
2226                                         rf->att = 3;
2227                         } else
2228                                 rf->att = 6;
2229                         return;
2230                 case 3:
2231                         rf->att = 5;
2232                         return;
2233                 case 4:
2234                 case 5:
2235                         rf->att = 1;
2236                         return;
2237                 case 6:
2238                 case 7:
2239                         rf->att = 5;
2240                         return;
2241                 case 8:
2242                         rf->att = 0xA;
2243                         rf->with_padmix = 1;
2244                         return;
2245                 case 9:
2246                 default:
2247                         rf->att = 5;
2248                         return;
2249                 }
2250         }
2251         rf->att = 5;
2252 }
2253
2254 static u16 default_tx_control(struct b43_wldev *dev)
2255 {
2256         struct b43_phy *phy = &dev->phy;
2257
2258         if (phy->radio_ver != 0x2050)
2259                 return 0;
2260         if (phy->radio_rev == 1)
2261                 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2262         if (phy->radio_rev < 6)
2263                 return B43_TXCTL_PA2DB;
2264         if (phy->radio_rev == 8)
2265                 return B43_TXCTL_TXMIX;
2266         return 0;
2267 }
2268
2269 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2270 {
2271         struct b43_phy *phy = &dev->phy;
2272         struct b43_phy_g *gphy = phy->g;
2273         u8 ret = 0;
2274         u16 saved, rssi, temp;
2275         int i, j = 0;
2276
2277         saved = b43_phy_read(dev, 0x0403);
2278         b43_switch_channel(dev, channel);
2279         b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2280         if (gphy->aci_hw_rssi)
2281                 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2282         else
2283                 rssi = saved & 0x3F;
2284         /* clamp temp to signed 5bit */
2285         if (rssi > 32)
2286                 rssi -= 64;
2287         for (i = 0; i < 100; i++) {
2288                 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2289                 if (temp > 32)
2290                         temp -= 64;
2291                 if (temp < rssi)
2292                         j++;
2293                 if (j >= 20)
2294                         ret = 1;
2295         }
2296         b43_phy_write(dev, 0x0403, saved);
2297
2298         return ret;
2299 }
2300
2301 static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2302 {
2303         struct b43_phy *phy = &dev->phy;
2304         u8 ret[13];
2305         unsigned int channel = phy->channel;
2306         unsigned int i, j, start, end;
2307
2308         if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2309                 return 0;
2310
2311         b43_phy_lock(dev);
2312         b43_radio_lock(dev);
2313         b43_phy_mask(dev, 0x0802, 0xFFFC);
2314         b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2315         b43_set_all_gains(dev, 3, 8, 1);
2316
2317         start = (channel - 5 > 0) ? channel - 5 : 1;
2318         end = (channel + 5 < 14) ? channel + 5 : 13;
2319
2320         for (i = start; i <= end; i++) {
2321                 if (abs(channel - i) > 2)
2322                         ret[i - 1] = b43_gphy_aci_detect(dev, i);
2323         }
2324         b43_switch_channel(dev, channel);
2325         b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003);
2326         b43_phy_mask(dev, 0x0403, 0xFFF8);
2327         b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2328         b43_set_original_gains(dev);
2329         for (i = 0; i < 13; i++) {
2330                 if (!ret[i])
2331                         continue;
2332                 end = (i + 5 < 13) ? i + 5 : 13;
2333                 for (j = i; j < end; j++)
2334                         ret[j] = 1;
2335         }
2336         b43_radio_unlock(dev);
2337         b43_phy_unlock(dev);
2338
2339         return ret[channel - 1];
2340 }
2341
2342 static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2343 {
2344         if (num < 0)
2345                 return num / den;
2346         else
2347                 return (num + den / 2) / den;
2348 }
2349
2350 static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2351                              s16 pab0, s16 pab1, s16 pab2)
2352 {
2353         s32 m1, m2, f = 256, q, delta;
2354         s8 i = 0;
2355
2356         m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2357         m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2358         do {
2359                 if (i > 15)
2360                         return -EINVAL;
2361                 q = b43_tssi2dbm_ad(f * 4096 -
2362                                     b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2363                 delta = abs(q - f);
2364                 f = q;
2365                 i++;
2366         } while (delta >= 2);
2367         entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2368         return 0;
2369 }
2370
2371 u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2372                                    s16 pab0, s16 pab1, s16 pab2)
2373 {
2374         unsigned int i;
2375         u8 *tab;
2376         int err;
2377
2378         tab = kmalloc(64, GFP_KERNEL);
2379         if (!tab) {
2380                 b43err(dev->wl, "Could not allocate memory "
2381                        "for tssi2dbm table\n");
2382                 return NULL;
2383         }
2384         for (i = 0; i < 64; i++) {
2385                 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2386                 if (err) {
2387                         b43err(dev->wl, "Could not generate "
2388                                "tssi2dBm table\n");
2389                         kfree(tab);
2390                         return NULL;
2391                 }
2392         }
2393
2394         return tab;
2395 }
2396
2397 /* Initialise the TSSI->dBm lookup table */
2398 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2399 {
2400         struct b43_phy *phy = &dev->phy;
2401         struct b43_phy_g *gphy = phy->g;
2402         s16 pab0, pab1, pab2;
2403
2404         pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
2405         pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
2406         pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
2407
2408         B43_WARN_ON((dev->dev->bus->chip_id == 0x4301) &&
2409                     (phy->radio_ver != 0x2050)); /* Not supported anymore */
2410
2411         gphy->dyn_tssi_tbl = 0;
2412
2413         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2414             pab0 != -1 && pab1 != -1 && pab2 != -1) {
2415                 /* The pabX values are set in SPROM. Use them. */
2416                 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
2417                     (s8) dev->dev->bus->sprom.itssi_bg != -1) {
2418                         gphy->tgt_idle_tssi =
2419                                 (s8) (dev->dev->bus->sprom.itssi_bg);
2420                 } else
2421                         gphy->tgt_idle_tssi = 62;
2422                 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2423                                                                pab1, pab2);
2424                 if (!gphy->tssi2dbm)
2425                         return -ENOMEM;
2426                 gphy->dyn_tssi_tbl = 1;
2427         } else {
2428                 /* pabX values not set in SPROM. */
2429                 gphy->tgt_idle_tssi = 52;
2430                 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int b43_gphy_op_allocate(struct b43_wldev *dev)
2437 {
2438         struct b43_phy_g *gphy;
2439         struct b43_txpower_lo_control *lo;
2440         int err;
2441
2442         gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2443         if (!gphy) {
2444                 err = -ENOMEM;
2445                 goto error;
2446         }
2447         dev->phy.g = gphy;
2448
2449         lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2450         if (!lo) {
2451                 err = -ENOMEM;
2452                 goto err_free_gphy;
2453         }
2454         gphy->lo_control = lo;
2455
2456         err = b43_gphy_init_tssi2dbm_table(dev);
2457         if (err)
2458                 goto err_free_lo;
2459
2460         return 0;
2461
2462 err_free_lo:
2463         kfree(lo);
2464 err_free_gphy:
2465         kfree(gphy);
2466 error:
2467         return err;
2468 }
2469
2470 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev)
2471 {
2472         struct b43_phy *phy = &dev->phy;
2473         struct b43_phy_g *gphy = phy->g;
2474         const void *tssi2dbm;
2475         int tgt_idle_tssi;
2476         struct b43_txpower_lo_control *lo;
2477         unsigned int i;
2478
2479         /* tssi2dbm table is constant, so it is initialized at alloc time.
2480          * Save a copy of the pointer. */
2481         tssi2dbm = gphy->tssi2dbm;
2482         tgt_idle_tssi = gphy->tgt_idle_tssi;
2483         /* Save the LO pointer. */
2484         lo = gphy->lo_control;
2485
2486         /* Zero out the whole PHY structure. */
2487         memset(gphy, 0, sizeof(*gphy));
2488
2489         /* Restore pointers. */
2490         gphy->tssi2dbm = tssi2dbm;
2491         gphy->tgt_idle_tssi = tgt_idle_tssi;
2492         gphy->lo_control = lo;
2493
2494         memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2495
2496         /* NRSSI */
2497         for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2498                 gphy->nrssi[i] = -1000;
2499         for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2500                 gphy->nrssi_lt[i] = i;
2501
2502         gphy->lofcal = 0xFFFF;
2503         gphy->initval = 0xFFFF;
2504
2505         gphy->interfmode = B43_INTERFMODE_NONE;
2506
2507         /* OFDM-table address caching. */
2508         gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2509
2510         gphy->average_tssi = 0xFF;
2511
2512         /* Local Osciallator structure */
2513         lo->tx_bias = 0xFF;
2514         INIT_LIST_HEAD(&lo->calib_list);
2515 }
2516
2517 static void b43_gphy_op_free(struct b43_wldev *dev)
2518 {
2519         struct b43_phy *phy = &dev->phy;
2520         struct b43_phy_g *gphy = phy->g;
2521
2522         kfree(gphy->lo_control);
2523
2524         if (gphy->dyn_tssi_tbl)
2525                 kfree(gphy->tssi2dbm);
2526         gphy->dyn_tssi_tbl = 0;
2527         gphy->tssi2dbm = NULL;
2528
2529         kfree(gphy);
2530         dev->phy.g = NULL;
2531 }
2532
2533 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2534 {
2535         struct b43_phy *phy = &dev->phy;
2536         struct b43_phy_g *gphy = phy->g;
2537         struct b43_txpower_lo_control *lo = gphy->lo_control;
2538
2539         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2540
2541         default_baseband_attenuation(dev, &gphy->bbatt);
2542         default_radio_attenuation(dev, &gphy->rfatt);
2543         gphy->tx_control = (default_tx_control(dev) << 4);
2544         generate_rfatt_list(dev, &lo->rfatt_list);
2545         generate_bbatt_list(dev, &lo->bbatt_list);
2546
2547         /* Commit previous writes */
2548         b43_read32(dev, B43_MMIO_MACCTL);
2549
2550         if (phy->rev == 1) {
2551                 /* Workaround: Temporarly disable gmode through the early init
2552                  * phase, as the gmode stuff is not needed for phy rev 1 */
2553                 phy->gmode = 0;
2554                 b43_wireless_core_reset(dev, 0);
2555                 b43_phy_initg(dev);
2556                 phy->gmode = 1;
2557                 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2558         }
2559
2560         return 0;
2561 }
2562
2563 static int b43_gphy_op_init(struct b43_wldev *dev)
2564 {
2565         b43_phy_initg(dev);
2566
2567         return 0;
2568 }
2569
2570 static void b43_gphy_op_exit(struct b43_wldev *dev)
2571 {
2572         b43_lo_g_cleanup(dev);
2573 }
2574
2575 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2576 {
2577         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2578         return b43_read16(dev, B43_MMIO_PHY_DATA);
2579 }
2580
2581 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2582 {
2583         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2584         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2585 }
2586
2587 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2588 {
2589         /* Register 1 is a 32-bit register. */
2590         B43_WARN_ON(reg == 1);
2591         /* G-PHY needs 0x80 for read access. */
2592         reg |= 0x80;
2593
2594         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2595         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2596 }
2597
2598 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2599 {
2600         /* Register 1 is a 32-bit register. */
2601         B43_WARN_ON(reg == 1);
2602
2603         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2604         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2605 }
2606
2607 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2608 {
2609         return (dev->phy.rev >= 6);
2610 }
2611
2612 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2613                                         enum rfkill_state state)
2614 {
2615         struct b43_phy *phy = &dev->phy;
2616         struct b43_phy_g *gphy = phy->g;
2617         unsigned int channel;
2618
2619         might_sleep();
2620
2621         if (state == RFKILL_STATE_UNBLOCKED) {
2622                 /* Turn radio ON */
2623                 if (phy->radio_on)
2624                         return;
2625
2626                 b43_phy_write(dev, 0x0015, 0x8000);
2627                 b43_phy_write(dev, 0x0015, 0xCC00);
2628                 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2629                 if (gphy->radio_off_context.valid) {
2630                         /* Restore the RFover values. */
2631                         b43_phy_write(dev, B43_PHY_RFOVER,
2632                                       gphy->radio_off_context.rfover);
2633                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
2634                                       gphy->radio_off_context.rfoverval);
2635                         gphy->radio_off_context.valid = 0;
2636                 }
2637                 channel = phy->channel;
2638                 b43_gphy_channel_switch(dev, 6, 1);
2639                 b43_gphy_channel_switch(dev, channel, 0);
2640         } else {
2641                 /* Turn radio OFF */
2642                 u16 rfover, rfoverval;
2643
2644                 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2645                 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2646                 gphy->radio_off_context.rfover = rfover;
2647                 gphy->radio_off_context.rfoverval = rfoverval;
2648                 gphy->radio_off_context.valid = 1;
2649                 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2650                 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2651         }
2652 }
2653
2654 static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2655                                       unsigned int new_channel)
2656 {
2657         if ((new_channel < 1) || (new_channel > 14))
2658                 return -EINVAL;
2659         b43_gphy_channel_switch(dev, new_channel, 0);
2660
2661         return 0;
2662 }
2663
2664 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2665 {
2666         return 1; /* Default to channel 1 */
2667 }
2668
2669 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2670 {
2671         struct b43_phy *phy = &dev->phy;
2672         u64 hf;
2673         u16 tmp;
2674         int autodiv = 0;
2675
2676         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2677                 autodiv = 1;
2678
2679         hf = b43_hf_read(dev);
2680         hf &= ~B43_HF_ANTDIVHELP;
2681         b43_hf_write(dev, hf);
2682
2683         tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2684         tmp &= ~B43_PHY_BBANDCFG_RXANT;
2685         tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2686                         << B43_PHY_BBANDCFG_RXANT_SHIFT;
2687         b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2688
2689         if (autodiv) {
2690                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2691                 if (antenna == B43_ANTENNA_AUTO0)
2692                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2693                 else
2694                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2695                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2696         }
2697         tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2698         if (autodiv)
2699                 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2700         else
2701                 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2702         b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2703         if (phy->rev >= 2) {
2704                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2705                 tmp |= B43_PHY_OFDM61_10;
2706                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2707
2708                 tmp =
2709                     b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2710                 tmp = (tmp & 0xFF00) | 0x15;
2711                 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2712                               tmp);
2713
2714                 if (phy->rev == 2) {
2715                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2716                                       8);
2717                 } else {
2718                         tmp =
2719                             b43_phy_read(dev,
2720                                          B43_PHY_ADIVRELATED);
2721                         tmp = (tmp & 0xFF00) | 8;
2722                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2723                                       tmp);
2724                 }
2725         }
2726         if (phy->rev >= 6)
2727                 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2728
2729         hf |= B43_HF_ANTDIVHELP;
2730         b43_hf_write(dev, hf);
2731 }
2732
2733 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2734                                          enum b43_interference_mitigation mode)
2735 {
2736         struct b43_phy *phy = &dev->phy;
2737         struct b43_phy_g *gphy = phy->g;
2738         int currentmode;
2739
2740         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2741         if ((phy->rev == 0) || (!phy->gmode))
2742                 return -ENODEV;
2743
2744         gphy->aci_wlan_automatic = 0;
2745         switch (mode) {
2746         case B43_INTERFMODE_AUTOWLAN:
2747                 gphy->aci_wlan_automatic = 1;
2748                 if (gphy->aci_enable)
2749                         mode = B43_INTERFMODE_MANUALWLAN;
2750                 else
2751                         mode = B43_INTERFMODE_NONE;
2752                 break;
2753         case B43_INTERFMODE_NONE:
2754         case B43_INTERFMODE_NONWLAN:
2755         case B43_INTERFMODE_MANUALWLAN:
2756                 break;
2757         default:
2758                 return -EINVAL;
2759         }
2760
2761         currentmode = gphy->interfmode;
2762         if (currentmode == mode)
2763                 return 0;
2764         if (currentmode != B43_INTERFMODE_NONE)
2765                 b43_radio_interference_mitigation_disable(dev, currentmode);
2766
2767         if (mode == B43_INTERFMODE_NONE) {
2768                 gphy->aci_enable = 0;
2769                 gphy->aci_hw_rssi = 0;
2770         } else
2771                 b43_radio_interference_mitigation_enable(dev, mode);
2772         gphy->interfmode = mode;
2773
2774         return 0;
2775 }
2776
2777 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2778  * This function converts a TSSI value to dBm in Q5.2
2779  */
2780 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2781 {
2782         struct b43_phy_g *gphy = dev->phy.g;
2783         s8 dbm;
2784         s32 tmp;
2785
2786         tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2787         tmp = clamp_val(tmp, 0x00, 0x3F);
2788         dbm = gphy->tssi2dbm[tmp];
2789
2790         return dbm;
2791 }
2792
2793 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2794                                             int *_bbatt, int *_rfatt)
2795 {
2796         int rfatt = *_rfatt;
2797         int bbatt = *_bbatt;
2798         struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2799
2800         /* Get baseband and radio attenuation values into their permitted ranges.
2801          * Radio attenuation affects power level 4 times as much as baseband. */
2802
2803         /* Range constants */
2804         const int rf_min = lo->rfatt_list.min_val;
2805         const int rf_max = lo->rfatt_list.max_val;
2806         const int bb_min = lo->bbatt_list.min_val;
2807         const int bb_max = lo->bbatt_list.max_val;
2808
2809         while (1) {
2810                 if (rfatt > rf_max && bbatt > bb_max - 4)
2811                         break;  /* Can not get it into ranges */
2812                 if (rfatt < rf_min && bbatt < bb_min + 4)
2813                         break;  /* Can not get it into ranges */
2814                 if (bbatt > bb_max && rfatt > rf_max - 1)
2815                         break;  /* Can not get it into ranges */
2816                 if (bbatt < bb_min && rfatt < rf_min + 1)
2817                         break;  /* Can not get it into ranges */
2818
2819                 if (bbatt > bb_max) {
2820                         bbatt -= 4;
2821                         rfatt += 1;
2822                         continue;
2823                 }
2824                 if (bbatt < bb_min) {
2825                         bbatt += 4;
2826                         rfatt -= 1;
2827                         continue;
2828                 }
2829                 if (rfatt > rf_max) {
2830                         rfatt -= 1;
2831                         bbatt += 4;
2832                         continue;
2833                 }
2834                 if (rfatt < rf_min) {
2835                         rfatt += 1;
2836                         bbatt -= 4;
2837                         continue;
2838                 }
2839                 break;
2840         }
2841
2842         *_rfatt = clamp_val(rfatt, rf_min, rf_max);
2843         *_bbatt = clamp_val(bbatt, bb_min, bb_max);
2844 }
2845
2846 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2847 {
2848         struct b43_phy *phy = &dev->phy;
2849         struct b43_phy_g *gphy = phy->g;
2850         int rfatt, bbatt;
2851         u8 tx_control;
2852
2853         b43_mac_suspend(dev);
2854
2855         spin_lock_irq(&dev->wl->irq_lock);
2856
2857         /* Calculate the new attenuation values. */
2858         bbatt = gphy->bbatt.att;
2859         bbatt += gphy->bbatt_delta;
2860         rfatt = gphy->rfatt.att;
2861         rfatt += gphy->rfatt_delta;
2862
2863         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2864         tx_control = gphy->tx_control;
2865         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2866                 if (rfatt <= 1) {
2867                         if (tx_control == 0) {
2868                                 tx_control =
2869                                     B43_TXCTL_PA2DB |
2870                                     B43_TXCTL_TXMIX;
2871                                 rfatt += 2;
2872                                 bbatt += 2;
2873                         } else if (dev->dev->bus->sprom.
2874                                    boardflags_lo &
2875                                    B43_BFL_PACTRL) {
2876                                 bbatt += 4 * (rfatt - 2);
2877                                 rfatt = 2;
2878                         }
2879                 } else if (rfatt > 4 && tx_control) {
2880                         tx_control = 0;
2881                         if (bbatt < 3) {
2882                                 rfatt -= 3;
2883                                 bbatt += 2;
2884                         } else {
2885                                 rfatt -= 2;
2886                                 bbatt -= 2;
2887                         }
2888                 }
2889         }
2890         /* Save the control values */
2891         gphy->tx_control = tx_control;
2892         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2893         gphy->rfatt.att = rfatt;
2894         gphy->bbatt.att = bbatt;
2895
2896         /* We drop the lock early, so we can sleep during hardware
2897          * adjustment. Possible races with op_recalc_txpower are harmless,
2898          * as we will be called once again in case we raced. */
2899         spin_unlock_irq(&dev->wl->irq_lock);
2900
2901         if (b43_debug(dev, B43_DBG_XMITPOWER))
2902                 b43dbg(dev->wl, "Adjusting TX power\n");
2903
2904         /* Adjust the hardware */
2905         b43_phy_lock(dev);
2906         b43_radio_lock(dev);
2907         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
2908                           gphy->tx_control);
2909         b43_radio_unlock(dev);
2910         b43_phy_unlock(dev);
2911
2912         b43_mac_enable(dev);
2913 }
2914
2915 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
2916                                                         bool ignore_tssi)
2917 {
2918         struct b43_phy *phy = &dev->phy;
2919         struct b43_phy_g *gphy = phy->g;
2920         unsigned int average_tssi;
2921         int cck_result, ofdm_result;
2922         int estimated_pwr, desired_pwr, pwr_adjust;
2923         int rfatt_delta, bbatt_delta;
2924         unsigned int max_pwr;
2925
2926         /* First get the average TSSI */
2927         cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK);
2928         ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G);
2929         if ((cck_result < 0) && (ofdm_result < 0)) {
2930                 /* No TSSI information available */
2931                 if (!ignore_tssi)
2932                         goto no_adjustment_needed;
2933                 cck_result = 0;
2934                 ofdm_result = 0;
2935         }
2936         if (cck_result < 0)
2937                 average_tssi = ofdm_result;
2938         else if (ofdm_result < 0)
2939                 average_tssi = cck_result;
2940         else
2941                 average_tssi = (cck_result + ofdm_result) / 2;
2942         /* Merge the average with the stored value. */
2943         if (likely(gphy->average_tssi != 0xFF))
2944                 average_tssi = (average_tssi + gphy->average_tssi) / 2;
2945         gphy->average_tssi = average_tssi;
2946         B43_WARN_ON(average_tssi >= B43_TSSI_MAX);
2947
2948         /* Estimate the TX power emission based on the TSSI */
2949         estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
2950
2951         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2952         max_pwr = dev->dev->bus->sprom.maxpwr_bg;
2953         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2954                 max_pwr -= 3; /* minus 0.75 */
2955         if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) {
2956                 b43warn(dev->wl,
2957                         "Invalid max-TX-power value in SPROM.\n");
2958                 max_pwr = INT_TO_Q52(20); /* fake it */
2959                 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
2960         }
2961
2962         /* Get desired power (in Q5.2) */
2963         if (phy->desired_txpower < 0)
2964                 desired_pwr = INT_TO_Q52(0);
2965         else
2966                 desired_pwr = INT_TO_Q52(phy->desired_txpower);
2967         /* And limit it. max_pwr already is Q5.2 */
2968         desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
2969         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2970                 b43dbg(dev->wl,
2971                        "[TX power]  current = " Q52_FMT
2972                        " dBm,  desired = " Q52_FMT
2973                        " dBm,  max = " Q52_FMT "\n",
2974                        Q52_ARG(estimated_pwr),
2975                        Q52_ARG(desired_pwr),
2976                        Q52_ARG(max_pwr));
2977         }
2978
2979         /* Calculate the adjustment delta. */
2980         pwr_adjust = desired_pwr - estimated_pwr;
2981         if (pwr_adjust == 0)
2982                 goto no_adjustment_needed;
2983
2984         /* RF attenuation delta. */
2985         rfatt_delta = ((pwr_adjust + 7) / 8);
2986         /* Lower attenuation => Bigger power output. Negate it. */
2987         rfatt_delta = -rfatt_delta;
2988
2989         /* Baseband attenuation delta. */
2990         bbatt_delta = pwr_adjust / 2;
2991         /* Lower attenuation => Bigger power output. Negate it. */
2992         bbatt_delta = -bbatt_delta;
2993         /* RF att affects power level 4 times as much as
2994          * Baseband attennuation. Subtract it. */
2995         bbatt_delta -= 4 * rfatt_delta;
2996
2997 #if B43_DEBUG
2998         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2999                 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust;
3000                 b43dbg(dev->wl,
3001                        "[TX power deltas]  %s" Q52_FMT " dBm   =>   "
3002                        "bbatt-delta = %d,  rfatt-delta = %d\n",
3003                        (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm),
3004                        bbatt_delta, rfatt_delta);
3005         }
3006 #endif /* DEBUG */
3007
3008         /* So do we finally need to adjust something in hardware? */
3009         if ((rfatt_delta == 0) && (bbatt_delta == 0))
3010                 goto no_adjustment_needed;
3011
3012         /* Save the deltas for later when we adjust the power. */
3013         gphy->bbatt_delta = bbatt_delta;
3014         gphy->rfatt_delta = rfatt_delta;
3015
3016         /* We need to adjust the TX power on the device. */
3017         return B43_TXPWR_RES_NEED_ADJUST;
3018
3019 no_adjustment_needed:
3020         return B43_TXPWR_RES_DONE;
3021 }
3022
3023 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
3024 {
3025         struct b43_phy *phy = &dev->phy;
3026         struct b43_phy_g *gphy = phy->g;
3027
3028         b43_mac_suspend(dev);
3029         //TODO: update_aci_moving_average
3030         if (gphy->aci_enable && gphy->aci_wlan_automatic) {
3031                 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) {
3032                         if (0 /*TODO: bunch of conditions */ ) {
3033                                 phy->ops->interf_mitigation(dev,
3034                                         B43_INTERFMODE_MANUALWLAN);
3035                         }
3036                 } else if (0 /*TODO*/) {
3037                            if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3038                                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3039                 }
3040         } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3041                    phy->rev == 1) {
3042                 //TODO: implement rev1 workaround
3043         }
3044         b43_lo_g_maintanance_work(dev);
3045         b43_mac_enable(dev);
3046 }
3047
3048 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3049 {
3050         struct b43_phy *phy = &dev->phy;
3051
3052         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI))
3053                 return;
3054
3055         b43_mac_suspend(dev);
3056         b43_calc_nrssi_slope(dev);
3057         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3058                 u8 old_chan = phy->channel;
3059
3060                 /* VCO Calibration */
3061                 if (old_chan >= 8)
3062                         b43_switch_channel(dev, 1);
3063                 else
3064                         b43_switch_channel(dev, 13);
3065                 b43_switch_channel(dev, old_chan);
3066         }
3067         b43_mac_enable(dev);
3068 }
3069
3070 const struct b43_phy_operations b43_phyops_g = {
3071         .allocate               = b43_gphy_op_allocate,
3072         .free                   = b43_gphy_op_free,
3073         .prepare_structs        = b43_gphy_op_prepare_structs,
3074         .prepare_hardware       = b43_gphy_op_prepare_hardware,
3075         .init                   = b43_gphy_op_init,
3076         .exit                   = b43_gphy_op_exit,
3077         .phy_read               = b43_gphy_op_read,
3078         .phy_write              = b43_gphy_op_write,
3079         .radio_read             = b43_gphy_op_radio_read,
3080         .radio_write            = b43_gphy_op_radio_write,
3081         .supports_hwpctl        = b43_gphy_op_supports_hwpctl,
3082         .software_rfkill        = b43_gphy_op_software_rfkill,
3083         .switch_analog          = b43_phyop_switch_analog_generic,
3084         .switch_channel         = b43_gphy_op_switch_channel,
3085         .get_default_chan       = b43_gphy_op_get_default_chan,
3086         .set_rx_antenna         = b43_gphy_op_set_rx_antenna,
3087         .interf_mitigation      = b43_gphy_op_interf_mitigation,
3088         .recalc_txpower         = b43_gphy_op_recalc_txpower,
3089         .adjust_txpower         = b43_gphy_op_adjust_txpower,
3090         .pwork_15sec            = b43_gphy_op_pwork_15sec,
3091         .pwork_60sec            = b43_gphy_op_pwork_60sec,
3092 };