drivers/net/wireless/b43/phy.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   6   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   This program is free software; you can redistribute it and/or modify
  12   it under the terms of the GNU General Public License as published by
  13   the Free Software Foundation; either version 2 of the License, or
  14   (at your option) any later version.
  15
  16   This program is distributed in the hope that it will be useful,
  17   but WITHOUT ANY WARRANTY; without even the implied warranty of
  18   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19   GNU General Public License for more details.
  20
  21   You should have received a copy of the GNU General Public License
  22   along with this program; see the file COPYING.  If not, write to
  23   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  24   Boston, MA 02110-1301, USA.
  25
  26 */
  27
  28 #include <linux/delay.h>
  29 #include <linux/io.h>
  30 #include <linux/types.h>
  31
  32 #include "b43.h"
  33 #include "phy.h"
  34 #include "nphy.h"
  35 #include "main.h"
  36 #include "tables.h"
  37 #include "lo.h"
  38 #include "wa.h"
  39
  40
  41 static const s8 b43_tssi2dbm_b_table[] = {
  42         0x4D, 0x4C, 0x4B, 0x4A,
  43         0x4A, 0x49, 0x48, 0x47,
  44         0x47, 0x46, 0x45, 0x45,
  45         0x44, 0x43, 0x42, 0x42,
  46         0x41, 0x40, 0x3F, 0x3E,
  47         0x3D, 0x3C, 0x3B, 0x3A,
  48         0x39, 0x38, 0x37, 0x36,
  49         0x35, 0x34, 0x32, 0x31,
  50         0x30, 0x2F, 0x2D, 0x2C,
  51         0x2B, 0x29, 0x28, 0x26,
  52         0x25, 0x23, 0x21, 0x1F,
  53         0x1D, 0x1A, 0x17, 0x14,
  54         0x10, 0x0C, 0x06, 0x00,
  55         -7, -7, -7, -7,
  56         -7, -7, -7, -7,
  57         -7, -7, -7, -7,
  58 };
  59
  60 static const s8 b43_tssi2dbm_g_table[] = {
  61         77, 77, 77, 76,
  62         76, 76, 75, 75,
  63         74, 74, 73, 73,
  64         73, 72, 72, 71,
  65         71, 70, 70, 69,
  66         68, 68, 67, 67,
  67         66, 65, 65, 64,
  68         63, 63, 62, 61,
  69         60, 59, 58, 57,
  70         56, 55, 54, 53,
  71         52, 50, 49, 47,
  72         45, 43, 40, 37,
  73         33, 28, 22, 14,
  74         5, -7, -20, -20,
  75         -20, -20, -20, -20,
  76         -20, -20, -20, -20,
  77 };
  78
  79 const u8 b43_radio_channel_codes_bg[] = {
  80         12, 17, 22, 27,
  81         32, 37, 42, 47,
  82         52, 57, 62, 67,
  83         72, 84,
  84 };
  85
  86 static void b43_phy_initg(struct b43_wldev *dev);
  87
  88 /* Reverse the bits of a 4bit value.
  89  * Example:  1101 is flipped 1011
  90  */
  91 static u16 flip_4bit(u16 value)
  92 {
  93         u16 flipped = 0x0000;
  94
  95         B43_WARN_ON(value & ~0x000F);
  96
  97         flipped |= (value & 0x0001) << 3;
  98         flipped |= (value & 0x0002) << 1;
  99         flipped |= (value & 0x0004) >> 1;
 100         flipped |= (value & 0x0008) >> 3;
 101
 102         return flipped;
 103 }
 104
 105 static void generate_rfatt_list(struct b43_wldev *dev,
 106                                 struct b43_rfatt_list *list)
 107 {
 108         struct b43_phy *phy = &dev->phy;
 109
 110         /* APHY.rev < 5 || GPHY.rev < 6 */
 111         static const struct b43_rfatt rfatt_0[] = {
 112                 {.att = 3,.with_padmix = 0,},
 113                 {.att = 1,.with_padmix = 0,},
 114                 {.att = 5,.with_padmix = 0,},
 115                 {.att = 7,.with_padmix = 0,},
 116                 {.att = 9,.with_padmix = 0,},
 117                 {.att = 2,.with_padmix = 0,},
 118                 {.att = 0,.with_padmix = 0,},
 119                 {.att = 4,.with_padmix = 0,},
 120                 {.att = 6,.with_padmix = 0,},
 121                 {.att = 8,.with_padmix = 0,},
 122                 {.att = 1,.with_padmix = 1,},
 123                 {.att = 2,.with_padmix = 1,},
 124                 {.att = 3,.with_padmix = 1,},
 125                 {.att = 4,.with_padmix = 1,},
 126         };
 127         /* Radio.rev == 8 && Radio.version == 0x2050 */
 128         static const struct b43_rfatt rfatt_1[] = {
 129                 {.att = 2,.with_padmix = 1,},
 130                 {.att = 4,.with_padmix = 1,},
 131                 {.att = 6,.with_padmix = 1,},
 132                 {.att = 8,.with_padmix = 1,},
 133                 {.att = 10,.with_padmix = 1,},
 134                 {.att = 12,.with_padmix = 1,},
 135                 {.att = 14,.with_padmix = 1,},
 136         };
 137         /* Otherwise */
 138         static const struct b43_rfatt rfatt_2[] = {
 139                 {.att = 0,.with_padmix = 1,},
 140                 {.att = 2,.with_padmix = 1,},
 141                 {.att = 4,.with_padmix = 1,},
 142                 {.att = 6,.with_padmix = 1,},
 143                 {.att = 8,.with_padmix = 1,},
 144                 {.att = 9,.with_padmix = 1,},
 145                 {.att = 9,.with_padmix = 1,},
 146         };
 147
 148         if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
 149             (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
 150                 /* Software pctl */
 151                 list->list = rfatt_0;
 152                 list->len = ARRAY_SIZE(rfatt_0);
 153                 list->min_val = 0;
 154                 list->max_val = 9;
 155                 return;
 156         }
 157         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 158                 /* Hardware pctl */
 159                 list->list = rfatt_1;
 160                 list->len = ARRAY_SIZE(rfatt_1);
 161                 list->min_val = 2;
 162                 list->max_val = 14;
 163                 return;
 164         }
 165         /* Hardware pctl */
 166         list->list = rfatt_2;
 167         list->len = ARRAY_SIZE(rfatt_2);
 168         list->min_val = 0;
 169         list->max_val = 9;
 170 }
 171
 172 static void generate_bbatt_list(struct b43_wldev *dev,
 173                                 struct b43_bbatt_list *list)
 174 {
 175         static const struct b43_bbatt bbatt_0[] = {
 176                 {.att = 0,},
 177                 {.att = 1,},
 178                 {.att = 2,},
 179                 {.att = 3,},
 180                 {.att = 4,},
 181                 {.att = 5,},
 182                 {.att = 6,},
 183                 {.att = 7,},
 184                 {.att = 8,},
 185         };
 186
 187         list->list = bbatt_0;
 188         list->len = ARRAY_SIZE(bbatt_0);
 189         list->min_val = 0;
 190         list->max_val = 8;
 191 }
 192
 193 bool b43_has_hardware_pctl(struct b43_phy *phy)
 194 {
 195         if (!phy->hardware_power_control)
 196                 return 0;
 197         switch (phy->type) {
 198         case B43_PHYTYPE_A:
 199                 if (phy->rev >= 5)
 200                         return 1;
 201                 break;
 202         case B43_PHYTYPE_G:
 203                 if (phy->rev >= 6)
 204                         return 1;
 205                 break;
 206         default:
 207                 B43_WARN_ON(1);
 208         }
 209         return 0;
 210 }
 211
 212 static void b43_shm_clear_tssi(struct b43_wldev *dev)
 213 {
 214         struct b43_phy *phy = &dev->phy;
 215
 216         switch (phy->type) {
 217         case B43_PHYTYPE_A:
 218                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
 219                 b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
 220                 break;
 221         case B43_PHYTYPE_B:
 222         case B43_PHYTYPE_G:
 223                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
 224                 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
 225                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
 226                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
 227                 break;
 228         }
 229 }
 230
 231 /* Lock the PHY registers against concurrent access from the microcode.
 232  * This lock is nonrecursive. */
 233 void b43_phy_lock(struct b43_wldev *dev)
 234 {
 235 #if B43_DEBUG
 236         B43_WARN_ON(dev->phy.phy_locked);
 237         dev->phy.phy_locked = 1;
 238 #endif
 239         B43_WARN_ON(dev->dev->id.revision < 3);
 240
 241         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
 242                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
 243 }
 244
 245 void b43_phy_unlock(struct b43_wldev *dev)
 246 {
 247 #if B43_DEBUG
 248         B43_WARN_ON(!dev->phy.phy_locked);
 249         dev->phy.phy_locked = 0;
 250 #endif
 251         B43_WARN_ON(dev->dev->id.revision < 3);
 252
 253         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
 254                 b43_power_saving_ctl_bits(dev, 0);
 255 }
 256
 257 /* Different PHYs require different register routing flags.
 258  * This adjusts (and does sanity checks on) the routing flags.
 259  */
 260 static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
 261                                             u16 offset, struct b43_wldev *dev)
 262 {
 263         if (phy->type == B43_PHYTYPE_A) {
 264                 /* OFDM registers are base-registers for the A-PHY. */
 265                 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
 266                         offset &= ~B43_PHYROUTE;
 267                         offset |= B43_PHYROUTE_BASE;
 268                 }
 269         }
 270
 271 #if B43_DEBUG
 272         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
 273                 /* Ext-G registers are only available on G-PHYs */
 274                 if (phy->type != B43_PHYTYPE_G) {
 275                         b43err(dev->wl, "Invalid EXT-G PHY access at "
 276                                "0x%04X on PHY type %u\n", offset, phy->type);
 277                         dump_stack();
 278                 }
 279         }
 280         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
 281                 /* N-BMODE registers are only available on N-PHYs */
 282                 if (phy->type != B43_PHYTYPE_N) {
 283                         b43err(dev->wl, "Invalid N-BMODE PHY access at "
 284                                "0x%04X on PHY type %u\n", offset, phy->type);
 285                         dump_stack();
 286                 }
 287         }
 288 #endif /* B43_DEBUG */
 289
 290         return offset;
 291 }
 292
 293 u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
 294 {
 295         struct b43_phy *phy = &dev->phy;
 296
 297         offset = adjust_phyreg_for_phytype(phy, offset, dev);
 298         b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
 299         return b43_read16(dev, B43_MMIO_PHY_DATA);
 300 }
 301
 302 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
 303 {
 304         struct b43_phy *phy = &dev->phy;
 305
 306         offset = adjust_phyreg_for_phytype(phy, offset, dev);
 307         b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
 308         b43_write16(dev, B43_MMIO_PHY_DATA, val);
 309 }
 310
 311 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
 312 {
 313         b43_phy_write(dev, offset,
 314                       b43_phy_read(dev, offset) & mask);
 315 }
 316
 317 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
 318 {
 319         b43_phy_write(dev, offset,
 320                       b43_phy_read(dev, offset) | set);
 321 }
 322
 323 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
 324 {
 325         b43_phy_write(dev, offset,
 326                       (b43_phy_read(dev, offset) & mask) | set);
 327 }
 328
 329 /* Adjust the transmission power output (G-PHY) */
 330 void b43_set_txpower_g(struct b43_wldev *dev,
 331                        const struct b43_bbatt *bbatt,
 332                        const struct b43_rfatt *rfatt, u8 tx_control)
 333 {
 334         struct b43_phy *phy = &dev->phy;
 335         struct b43_txpower_lo_control *lo = phy->lo_control;
 336         u16 bb, rf;
 337         u16 tx_bias, tx_magn;
 338
 339         bb = bbatt->att;
 340         rf = rfatt->att;
 341         tx_bias = lo->tx_bias;
 342         tx_magn = lo->tx_magn;
 343         if (unlikely(tx_bias == 0xFF))
 344                 tx_bias = 0;
 345
 346         /* Save the values for later */
 347         phy->tx_control = tx_control;
 348         memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
 349         memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
 350
 351         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
 352                 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
 353                        "rfatt(%u), tx_control(0x%02X), "
 354                        "tx_bias(0x%02X), tx_magn(0x%02X)\n",
 355                        bb, rf, tx_control, tx_bias, tx_magn);
 356         }
 357
 358         b43_phy_set_baseband_attenuation(dev, bb);
 359         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
 360         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 361                 b43_radio_write16(dev, 0x43,
 362                                   (rf & 0x000F) | (tx_control & 0x0070));
 363         } else {
 364                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
 365                                               & 0xFFF0) | (rf & 0x000F));
 366                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 367                                               & ~0x0070) | (tx_control &
 368                                                             0x0070));
 369         }
 370         if (has_tx_magnification(phy)) {
 371                 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
 372         } else {
 373                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 374                                               & 0xFFF0) | (tx_bias & 0x000F));
 375         }
 376         if (phy->type == B43_PHYTYPE_G)
 377                 b43_lo_g_adjust(dev);
 378 }
 379
 380 static void default_baseband_attenuation(struct b43_wldev *dev,
 381                                          struct b43_bbatt *bb)
 382 {
 383         struct b43_phy *phy = &dev->phy;
 384
 385         if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
 386                 bb->att = 0;
 387         else
 388                 bb->att = 2;
 389 }
 390
 391 static void default_radio_attenuation(struct b43_wldev *dev,
 392                                       struct b43_rfatt *rf)
 393 {
 394         struct ssb_bus *bus = dev->dev->bus;
 395         struct b43_phy *phy = &dev->phy;
 396
 397         rf->with_padmix = 0;
 398
 399         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
 400             bus->boardinfo.type == SSB_BOARD_BCM4309G) {
 401                 if (bus->boardinfo.rev < 0x43) {
 402                         rf->att = 2;
 403                         return;
 404                 } else if (bus->boardinfo.rev < 0x51) {
 405                         rf->att = 3;
 406                         return;
 407                 }
 408         }
 409
 410         if (phy->type == B43_PHYTYPE_A) {
 411                 rf->att = 0x60;
 412                 return;
 413         }
 414
 415         switch (phy->radio_ver) {
 416         case 0x2053:
 417                 switch (phy->radio_rev) {
 418                 case 1:
 419                         rf->att = 6;
 420                         return;
 421                 }
 422                 break;
 423         case 0x2050:
 424                 switch (phy->radio_rev) {
 425                 case 0:
 426                         rf->att = 5;
 427                         return;
 428                 case 1:
 429                         if (phy->type == B43_PHYTYPE_G) {
 430                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 431                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 432                                     && bus->boardinfo.rev >= 30)
 433                                         rf->att = 3;
 434                                 else if (bus->boardinfo.vendor ==
 435                                          SSB_BOARDVENDOR_BCM
 436                                          && bus->boardinfo.type ==
 437                                          SSB_BOARD_BU4306)
 438                                         rf->att = 3;
 439                                 else
 440                                         rf->att = 1;
 441                         } else {
 442                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 443                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 444                                     && bus->boardinfo.rev >= 30)
 445                                         rf->att = 7;
 446                                 else
 447                                         rf->att = 6;
 448                         }
 449                         return;
 450                 case 2:
 451                         if (phy->type == B43_PHYTYPE_G) {
 452                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 453                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 454                                     && bus->boardinfo.rev >= 30)
 455                                         rf->att = 3;
 456                                 else if (bus->boardinfo.vendor ==
 457                                          SSB_BOARDVENDOR_BCM
 458                                          && bus->boardinfo.type ==
 459                                          SSB_BOARD_BU4306)
 460                                         rf->att = 5;
 461                                 else if (bus->chip_id == 0x4320)
 462                                         rf->att = 4;
 463                                 else
 464                                         rf->att = 3;
 465                         } else
 466                                 rf->att = 6;
 467                         return;
 468                 case 3:
 469                         rf->att = 5;
 470                         return;
 471                 case 4:
 472                 case 5:
 473                         rf->att = 1;
 474                         return;
 475                 case 6:
 476                 case 7:
 477                         rf->att = 5;
 478                         return;
 479                 case 8:
 480                         rf->att = 0xA;
 481                         rf->with_padmix = 1;
 482                         return;
 483                 case 9:
 484                 default:
 485                         rf->att = 5;
 486                         return;
 487                 }
 488         }
 489         rf->att = 5;
 490 }
 491
 492 static u16 default_tx_control(struct b43_wldev *dev)
 493 {
 494         struct b43_phy *phy = &dev->phy;
 495
 496         if (phy->radio_ver != 0x2050)
 497                 return 0;
 498         if (phy->radio_rev == 1)
 499                 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
 500         if (phy->radio_rev < 6)
 501                 return B43_TXCTL_PA2DB;
 502         if (phy->radio_rev == 8)
 503                 return B43_TXCTL_TXMIX;
 504         return 0;
 505 }
 506
 507 /* This func is called "PHY calibrate" in the specs... */
 508 void b43_phy_early_init(struct b43_wldev *dev)
 509 {
 510         struct b43_phy *phy = &dev->phy;
 511         struct b43_txpower_lo_control *lo = phy->lo_control;
 512
 513         default_baseband_attenuation(dev, &phy->bbatt);
 514         default_radio_attenuation(dev, &phy->rfatt);
 515         phy->tx_control = (default_tx_control(dev) << 4);
 516
 517         /* Commit previous writes */
 518         b43_read32(dev, B43_MMIO_MACCTL);
 519
 520         if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
 521                 generate_rfatt_list(dev, &lo->rfatt_list);
 522                 generate_bbatt_list(dev, &lo->bbatt_list);
 523         }
 524         if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
 525                 /* Workaround: Temporarly disable gmode through the early init
 526                  * phase, as the gmode stuff is not needed for phy rev 1 */
 527                 phy->gmode = 0;
 528                 b43_wireless_core_reset(dev, 0);
 529                 b43_phy_initg(dev);
 530                 phy->gmode = 1;
 531                 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
 532         }
 533 }
 534
 535 /* GPHY_TSSI_Power_Lookup_Table_Init */
 536 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
 537 {
 538         struct b43_phy *phy = &dev->phy;
 539         int i;
 540         u16 value;
 541
 542         for (i = 0; i < 32; i++)
 543                 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
 544         for (i = 32; i < 64; i++)
 545                 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
 546         for (i = 0; i < 64; i += 2) {
 547                 value = (u16) phy->tssi2dbm[i];
 548                 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
 549                 b43_phy_write(dev, 0x380 + (i / 2), value);
 550         }
 551 }
 552
 553 /* GPHY_Gain_Lookup_Table_Init */
 554 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
 555 {
 556         struct b43_phy *phy = &dev->phy;
 557         struct b43_txpower_lo_control *lo = phy->lo_control;
 558         u16 nr_written = 0;
 559         u16 tmp;
 560         u8 rf, bb;
 561
 562         if (!lo->lo_measured) {
 563                 b43_phy_write(dev, 0x3FF, 0);
 564                 return;
 565         }
 566
 567         for (rf = 0; rf < lo->rfatt_list.len; rf++) {
 568                 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
 569                         if (nr_written >= 0x40)
 570                                 return;
 571                         tmp = lo->bbatt_list.list[bb].att;
 572                         tmp <<= 8;
 573                         if (phy->radio_rev == 8)
 574                                 tmp |= 0x50;
 575                         else
 576                                 tmp |= 0x40;
 577                         tmp |= lo->rfatt_list.list[rf].att;
 578                         b43_phy_write(dev, 0x3C0 + nr_written, tmp);
 579                         nr_written++;
 580                 }
 581         }
 582 }
 583
 584 /* GPHY_DC_Lookup_Table */
 585 void b43_gphy_dc_lt_init(struct b43_wldev *dev)
 586 {
 587         struct b43_phy *phy = &dev->phy;
 588         struct b43_txpower_lo_control *lo = phy->lo_control;
 589         struct b43_loctl *loctl0;
 590         struct b43_loctl *loctl1;
 591         int i;
 592         int rf_offset, bb_offset;
 593         u16 tmp;
 594
 595         for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
 596                 rf_offset = i / lo->rfatt_list.len;
 597                 bb_offset = i % lo->rfatt_list.len;
 598
 599                 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
 600                                           &lo->bbatt_list.list[bb_offset]);
 601                 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
 602                         rf_offset = (i + 1) / lo->rfatt_list.len;
 603                         bb_offset = (i + 1) % lo->rfatt_list.len;
 604
 605                         loctl1 =
 606                             b43_get_lo_g_ctl(dev,
 607                                              &lo->rfatt_list.list[rf_offset],
 608                                              &lo->bbatt_list.list[bb_offset]);
 609                 } else
 610                         loctl1 = loctl0;
 611
 612                 tmp = ((u16) loctl0->q & 0xF);
 613                 tmp |= ((u16) loctl0->i & 0xF) << 4;
 614                 tmp |= ((u16) loctl1->q & 0xF) << 8;
 615                 tmp |= ((u16) loctl1->i & 0xF) << 12;   //FIXME?
 616                 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
 617         }
 618 }
 619
 620 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
 621 {
 622         //TODO
 623 }
 624
 625 static void hardware_pctl_init_gphy(struct b43_wldev *dev)
 626 {
 627         struct b43_phy *phy = &dev->phy;
 628
 629         b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
 630                       | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
 631         b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
 632                       | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
 633         b43_gphy_tssi_power_lt_init(dev);
 634         b43_gphy_gain_lt_init(dev);
 635         b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
 636         b43_phy_write(dev, 0x0014, 0x0000);
 637
 638         B43_WARN_ON(phy->rev < 6);
 639         b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
 640                       | 0x0800);
 641         b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
 642                       & 0xFEFF);
 643         b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
 644                       & 0xFFBF);
 645
 646         b43_gphy_dc_lt_init(dev);
 647 }
 648
 649 /* HardwarePowerControl init for A and G PHY */
 650 static void b43_hardware_pctl_init(struct b43_wldev *dev)
 651 {
 652         struct b43_phy *phy = &dev->phy;
 653
 654         if (!b43_has_hardware_pctl(phy)) {
 655                 /* No hardware power control */
 656                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
 657                 return;
 658         }
 659         /* Init the hwpctl related hardware */
 660         switch (phy->type) {
 661         case B43_PHYTYPE_A:
 662                 hardware_pctl_init_aphy(dev);
 663                 break;
 664         case B43_PHYTYPE_G:
 665                 hardware_pctl_init_gphy(dev);
 666                 break;
 667         default:
 668                 B43_WARN_ON(1);
 669         }
 670         /* Enable hardware pctl in firmware. */
 671         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
 672 }
 673
 674 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
 675 {
 676         struct b43_phy *phy = &dev->phy;
 677
 678         if (!b43_has_hardware_pctl(phy)) {
 679                 b43_phy_write(dev, 0x047A, 0xC111);
 680                 return;
 681         }
 682
 683         b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
 684         b43_phy_write(dev, 0x002F, 0x0202);
 685         b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
 686         b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
 687         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 688                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
 689                                             & 0xFF0F) | 0x0010);
 690                 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
 691                               | 0x8000);
 692                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
 693                                             & 0xFFC0) | 0x0010);
 694                 b43_phy_write(dev, 0x002E, 0xC07F);
 695                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 696                               | 0x0400);
 697         } else {
 698                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 699                               | 0x0200);
 700                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 701                               | 0x0400);
 702                 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
 703                               & 0x7FFF);
 704                 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
 705                               & 0xFFFE);
 706                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
 707                                             & 0xFFC0) | 0x0010);
 708                 b43_phy_write(dev, 0x002E, 0xC07F);
 709                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
 710                                             & 0xFF0F) | 0x0010);
 711         }
 712 }
 713
 714 /* Intialize B/G PHY power control
 715  * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
 716  */
 717 static void b43_phy_init_pctl(struct b43_wldev *dev)
 718 {
 719         struct ssb_bus *bus = dev->dev->bus;
 720         struct b43_phy *phy = &dev->phy;
 721         struct b43_rfatt old_rfatt;
 722         struct b43_bbatt old_bbatt;
 723         u8 old_tx_control = 0;
 724
 725         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 726             (bus->boardinfo.type == SSB_BOARD_BU4306))
 727                 return;
 728
 729         b43_phy_write(dev, 0x0028, 0x8018);
 730
 731         /* This does something with the Analog... */
 732         b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
 733                     & 0xFFDF);
 734
 735         if (phy->type == B43_PHYTYPE_G && !phy->gmode)
 736                 return;
 737         b43_hardware_pctl_early_init(dev);
 738         if (phy->cur_idle_tssi == 0) {
 739                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
 740                         b43_radio_write16(dev, 0x0076,
 741                                           (b43_radio_read16(dev, 0x0076)
 742                                            & 0x00F7) | 0x0084);
 743                 } else {
 744                         struct b43_rfatt rfatt;
 745                         struct b43_bbatt bbatt;
 746
 747                         memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
 748                         memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
 749                         old_tx_control = phy->tx_control;
 750
 751                         bbatt.att = 11;
 752                         if (phy->radio_rev == 8) {
 753                                 rfatt.att = 15;
 754                                 rfatt.with_padmix = 1;
 755                         } else {
 756                                 rfatt.att = 9;
 757                                 rfatt.with_padmix = 0;
 758                         }
 759                         b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
 760                 }
 761                 b43_dummy_transmission(dev);
 762                 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
 763                 if (B43_DEBUG) {
 764                         /* Current-Idle-TSSI sanity check. */
 765                         if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
 766                                 b43dbg(dev->wl,
 767                                        "!WARNING! Idle-TSSI phy->cur_idle_tssi "
 768                                        "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
 769                                        "adjustment.\n", phy->cur_idle_tssi,
 770                                        phy->tgt_idle_tssi);
 771                                 phy->cur_idle_tssi = 0;
 772                         }
 773                 }
 774                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
 775                         b43_radio_write16(dev, 0x0076,
 776                                           b43_radio_read16(dev, 0x0076)
 777                                           & 0xFF7B);
 778                 } else {
 779                         b43_set_txpower_g(dev, &old_bbatt,
 780                                           &old_rfatt, old_tx_control);
 781                 }
 782         }
 783         b43_hardware_pctl_init(dev);
 784         b43_shm_clear_tssi(dev);
 785 }
 786
 787 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
 788 {
 789         int i;
 790
 791         if (dev->phy.rev < 3) {
 792                 if (enable)
 793                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 794                                 b43_ofdmtab_write16(dev,
 795                                         B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
 796                                 b43_ofdmtab_write16(dev,
 797                                         B43_OFDMTAB_WRSSI, i, 0xFFF8);
 798                         }
 799                 else
 800                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 801                                 b43_ofdmtab_write16(dev,
 802                                         B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
 803                                 b43_ofdmtab_write16(dev,
 804                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
 805                         }
 806         } else {
 807                 if (enable)
 808                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
 809                                 b43_ofdmtab_write16(dev,
 810                                         B43_OFDMTAB_WRSSI, i, 0x0820);
 811                 else
 812                         for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
 813                                 b43_ofdmtab_write16(dev,
 814                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
 815         }
 816 }
 817
 818 static void b43_phy_ww(struct b43_wldev *dev)
 819 {
 820         u16 b, curr_s, best_s = 0xFFFF;
 821         int i;
 822
 823         b43_phy_write(dev, B43_PHY_CRS0,
 824                 b43_phy_read(dev, B43_PHY_CRS0) & ~B43_PHY_CRS0_EN);
 825         b43_phy_write(dev, B43_PHY_OFDM(0x1B),
 826                 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) | 0x1000);
 827         b43_phy_write(dev, B43_PHY_OFDM(0x82),
 828                 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
 829         b43_radio_write16(dev, 0x0009,
 830                 b43_radio_read16(dev, 0x0009) | 0x0080);
 831         b43_radio_write16(dev, 0x0012,
 832                 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
 833         b43_wa_initgains(dev);
 834         b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
 835         b = b43_phy_read(dev, B43_PHY_PWRDOWN);
 836         b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
 837         b43_radio_write16(dev, 0x0004,
 838                 b43_radio_read16(dev, 0x0004) | 0x0004);
 839         for (i = 0x10; i <= 0x20; i++) {
 840                 b43_radio_write16(dev, 0x0013, i);
 841                 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
 842                 if (!curr_s) {
 843                         best_s = 0x0000;
 844                         break;
 845                 } else if (curr_s >= 0x0080)
 846                         curr_s = 0x0100 - curr_s;
 847                 if (curr_s < best_s)
 848                         best_s = curr_s;
 849         }
 850         b43_phy_write(dev, B43_PHY_PWRDOWN, b);
 851         b43_radio_write16(dev, 0x0004,
 852                 b43_radio_read16(dev, 0x0004) & 0xFFFB);
 853         b43_radio_write16(dev, 0x0013, best_s);
 854         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
 855         b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
 856         b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
 857         b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
 858         b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
 859         b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
 860         b43_phy_write(dev, B43_PHY_OFDM(0xBB),
 861                 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
 862         b43_phy_write(dev, B43_PHY_OFDM61,
 863                 (b43_phy_read(dev, B43_PHY_OFDM61) & 0xFE1F) | 0x0120);
 864         b43_phy_write(dev, B43_PHY_OFDM(0x13),
 865                 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
 866         b43_phy_write(dev, B43_PHY_OFDM(0x14),
 867                 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
 868         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
 869         for (i = 0; i < 6; i++)
 870                 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
 871         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
 872         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
 873         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
 874         b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
 875         b43_phy_write(dev, B43_PHY_CRS0,
 876                 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
 877 }
 878
 879 /* Initialize APHY. This is also called for the GPHY in some cases. */
 880 static void b43_phy_inita(struct b43_wldev *dev)
 881 {
 882         struct ssb_bus *bus = dev->dev->bus;
 883         struct b43_phy *phy = &dev->phy;
 884
 885         might_sleep();
 886
 887         if (phy->rev >= 6) {
 888                 if (phy->type == B43_PHYTYPE_A)
 889                         b43_phy_write(dev, B43_PHY_OFDM(0x1B),
 890                                 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x1000);
 891                 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
 892                         b43_phy_write(dev, B43_PHY_ENCORE,
 893                                 b43_phy_read(dev, B43_PHY_ENCORE) | 0x0010);
 894                 else
 895                         b43_phy_write(dev, B43_PHY_ENCORE,
 896                                 b43_phy_read(dev, B43_PHY_ENCORE) & ~0x1010);
 897         }
 898
 899         b43_wa_all(dev);
 900
 901         if (phy->type == B43_PHYTYPE_A) {
 902                 if (phy->gmode && (phy->rev < 3))
 903                         b43_phy_write(dev, 0x0034,
 904                                 b43_phy_read(dev, 0x0034) | 0x0001);
 905                 b43_phy_rssiagc(dev, 0);
 906
 907                 b43_phy_write(dev, B43_PHY_CRS0,
 908                         b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
 909
 910                 b43_radio_init2060(dev);
 911
 912                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 913                     ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
 914                      (bus->boardinfo.type == SSB_BOARD_BU4309))) {
 915                         ; //TODO: A PHY LO
 916                 }
 917
 918                 if (phy->rev >= 3)
 919                         b43_phy_ww(dev);
 920
 921                 hardware_pctl_init_aphy(dev);
 922
 923                 //TODO: radar detection
 924         }
 925
 926         if ((phy->type == B43_PHYTYPE_G) &&
 927             (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
 928                 b43_phy_write(dev, B43_PHY_OFDM(0x6E),
 929                                   (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
 930                                    & 0xE000) | 0x3CF);
 931         }
 932 }
 933
 934 static void b43_phy_initb2(struct b43_wldev *dev)
 935 {
 936         struct b43_phy *phy = &dev->phy;
 937         u16 offset, val;
 938
 939         b43_write16(dev, 0x03EC, 0x3F22);
 940         b43_phy_write(dev, 0x0020, 0x301C);
 941         b43_phy_write(dev, 0x0026, 0x0000);
 942         b43_phy_write(dev, 0x0030, 0x00C6);
 943         b43_phy_write(dev, 0x0088, 0x3E00);
 944         val = 0x3C3D;
 945         for (offset = 0x0089; offset < 0x00A7; offset++) {
 946                 b43_phy_write(dev, offset, val);
 947                 val -= 0x0202;
 948         }
 949         b43_phy_write(dev, 0x03E4, 0x3000);
 950         b43_radio_selectchannel(dev, phy->channel, 0);
 951         if (phy->radio_ver != 0x2050) {
 952                 b43_radio_write16(dev, 0x0075, 0x0080);
 953                 b43_radio_write16(dev, 0x0079, 0x0081);
 954         }
 955         b43_radio_write16(dev, 0x0050, 0x0020);
 956         b43_radio_write16(dev, 0x0050, 0x0023);
 957         if (phy->radio_ver == 0x2050) {
 958                 b43_radio_write16(dev, 0x0050, 0x0020);
 959                 b43_radio_write16(dev, 0x005A, 0x0070);
 960                 b43_radio_write16(dev, 0x005B, 0x007B);
 961                 b43_radio_write16(dev, 0x005C, 0x00B0);
 962                 b43_radio_write16(dev, 0x007A, 0x000F);
 963                 b43_phy_write(dev, 0x0038, 0x0677);
 964                 b43_radio_init2050(dev);
 965         }
 966         b43_phy_write(dev, 0x0014, 0x0080);
 967         b43_phy_write(dev, 0x0032, 0x00CA);
 968         b43_phy_write(dev, 0x0032, 0x00CC);
 969         b43_phy_write(dev, 0x0035, 0x07C2);
 970         b43_lo_b_measure(dev);
 971         b43_phy_write(dev, 0x0026, 0xCC00);
 972         if (phy->radio_ver != 0x2050)
 973                 b43_phy_write(dev, 0x0026, 0xCE00);
 974         b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
 975         b43_phy_write(dev, 0x002A, 0x88A3);
 976         if (phy->radio_ver != 0x2050)
 977                 b43_phy_write(dev, 0x002A, 0x88C2);
 978         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
 979         b43_phy_init_pctl(dev);
 980 }
 981
 982 static void b43_phy_initb4(struct b43_wldev *dev)
 983 {
 984         struct b43_phy *phy = &dev->phy;
 985         u16 offset, val;
 986
 987         b43_write16(dev, 0x03EC, 0x3F22);
 988         b43_phy_write(dev, 0x0020, 0x301C);
 989         b43_phy_write(dev, 0x0026, 0x0000);
 990         b43_phy_write(dev, 0x0030, 0x00C6);
 991         b43_phy_write(dev, 0x0088, 0x3E00);
 992         val = 0x3C3D;
 993         for (offset = 0x0089; offset < 0x00A7; offset++) {
 994                 b43_phy_write(dev, offset, val);
 995                 val -= 0x0202;
 996         }
 997         b43_phy_write(dev, 0x03E4, 0x3000);
 998         b43_radio_selectchannel(dev, phy->channel, 0);
 999         if (phy->radio_ver != 0x2050) {
1000                 b43_radio_write16(dev, 0x0075, 0x0080);
1001                 b43_radio_write16(dev, 0x0079, 0x0081);
1002         }
1003         b43_radio_write16(dev, 0x0050, 0x0020);
1004         b43_radio_write16(dev, 0x0050, 0x0023);
1005         if (phy->radio_ver == 0x2050) {
1006                 b43_radio_write16(dev, 0x0050, 0x0020);
1007                 b43_radio_write16(dev, 0x005A, 0x0070);
1008                 b43_radio_write16(dev, 0x005B, 0x007B);
1009                 b43_radio_write16(dev, 0x005C, 0x00B0);
1010                 b43_radio_write16(dev, 0x007A, 0x000F);
1011                 b43_phy_write(dev, 0x0038, 0x0677);
1012                 b43_radio_init2050(dev);
1013         }
1014         b43_phy_write(dev, 0x0014, 0x0080);
1015         b43_phy_write(dev, 0x0032, 0x00CA);
1016         if (phy->radio_ver == 0x2050)
1017                 b43_phy_write(dev, 0x0032, 0x00E0);
1018         b43_phy_write(dev, 0x0035, 0x07C2);
1019
1020         b43_lo_b_measure(dev);
1021
1022         b43_phy_write(dev, 0x0026, 0xCC00);
1023         if (phy->radio_ver == 0x2050)
1024                 b43_phy_write(dev, 0x0026, 0xCE00);
1025         b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1026         b43_phy_write(dev, 0x002A, 0x88A3);
1027         if (phy->radio_ver == 0x2050)
1028                 b43_phy_write(dev, 0x002A, 0x88C2);
1029         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1030         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
1031                 b43_calc_nrssi_slope(dev);
1032                 b43_calc_nrssi_threshold(dev);
1033         }
1034         b43_phy_init_pctl(dev);
1035 }
1036
1037 static void b43_phy_initb5(struct b43_wldev *dev)
1038 {
1039         struct ssb_bus *bus = dev->dev->bus;
1040         struct b43_phy *phy = &dev->phy;
1041         u16 offset, value;
1042         u8 old_channel;
1043
1044         if (phy->analog == 1) {
1045                 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1046                                   | 0x0050);
1047         }
1048         if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1049             (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1050                 value = 0x2120;
1051                 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1052                         b43_phy_write(dev, offset, value);
1053                         value += 0x202;
1054                 }
1055         }
1056         b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1057                       | 0x0700);
1058         if (phy->radio_ver == 0x2050)
1059                 b43_phy_write(dev, 0x0038, 0x0667);
1060
1061         if (phy->gmode || phy->rev >= 2) {
1062                 if (phy->radio_ver == 0x2050) {
1063                         b43_radio_write16(dev, 0x007A,
1064                                           b43_radio_read16(dev, 0x007A)
1065                                           | 0x0020);
1066                         b43_radio_write16(dev, 0x0051,
1067                                           b43_radio_read16(dev, 0x0051)
1068                                           | 0x0004);
1069                 }
1070                 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1071
1072                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1073                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1074
1075                 b43_phy_write(dev, 0x001C, 0x186A);
1076
1077                 b43_phy_write(dev, 0x0013,
1078                               (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1079                 b43_phy_write(dev, 0x0035,
1080                               (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1081                 b43_phy_write(dev, 0x005D,
1082                               (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1083         }
1084
1085         if (dev->bad_frames_preempt) {
1086                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1087                               b43_phy_read(dev,
1088                                            B43_PHY_RADIO_BITFIELD) | (1 << 11));
1089         }
1090
1091         if (phy->analog == 1) {
1092                 b43_phy_write(dev, 0x0026, 0xCE00);
1093                 b43_phy_write(dev, 0x0021, 0x3763);
1094                 b43_phy_write(dev, 0x0022, 0x1BC3);
1095                 b43_phy_write(dev, 0x0023, 0x06F9);
1096                 b43_phy_write(dev, 0x0024, 0x037E);
1097         } else
1098                 b43_phy_write(dev, 0x0026, 0xCC00);
1099         b43_phy_write(dev, 0x0030, 0x00C6);
1100         b43_write16(dev, 0x03EC, 0x3F22);
1101
1102         if (phy->analog == 1)
1103                 b43_phy_write(dev, 0x0020, 0x3E1C);
1104         else
1105                 b43_phy_write(dev, 0x0020, 0x301C);
1106
1107         if (phy->analog == 0)
1108                 b43_write16(dev, 0x03E4, 0x3000);
1109
1110         old_channel = phy->channel;
1111         /* Force to channel 7, even if not supported. */
1112         b43_radio_selectchannel(dev, 7, 0);
1113
1114         if (phy->radio_ver != 0x2050) {
1115                 b43_radio_write16(dev, 0x0075, 0x0080);
1116                 b43_radio_write16(dev, 0x0079, 0x0081);
1117         }
1118
1119         b43_radio_write16(dev, 0x0050, 0x0020);
1120         b43_radio_write16(dev, 0x0050, 0x0023);
1121
1122         if (phy->radio_ver == 0x2050) {
1123                 b43_radio_write16(dev, 0x0050, 0x0020);
1124                 b43_radio_write16(dev, 0x005A, 0x0070);
1125         }
1126
1127         b43_radio_write16(dev, 0x005B, 0x007B);
1128         b43_radio_write16(dev, 0x005C, 0x00B0);
1129
1130         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1131
1132         b43_radio_selectchannel(dev, old_channel, 0);
1133
1134         b43_phy_write(dev, 0x0014, 0x0080);
1135         b43_phy_write(dev, 0x0032, 0x00CA);
1136         b43_phy_write(dev, 0x002A, 0x88A3);
1137
1138         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1139
1140         if (phy->radio_ver == 0x2050)
1141                 b43_radio_write16(dev, 0x005D, 0x000D);
1142
1143         b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1144 }
1145
1146 static void b43_phy_initb6(struct b43_wldev *dev)
1147 {
1148         struct b43_phy *phy = &dev->phy;
1149         u16 offset, val;
1150         u8 old_channel;
1151
1152         b43_phy_write(dev, 0x003E, 0x817A);
1153         b43_radio_write16(dev, 0x007A,
1154                           (b43_radio_read16(dev, 0x007A) | 0x0058));
1155         if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1156                 b43_radio_write16(dev, 0x51, 0x37);
1157                 b43_radio_write16(dev, 0x52, 0x70);
1158                 b43_radio_write16(dev, 0x53, 0xB3);
1159                 b43_radio_write16(dev, 0x54, 0x9B);
1160                 b43_radio_write16(dev, 0x5A, 0x88);
1161                 b43_radio_write16(dev, 0x5B, 0x88);
1162                 b43_radio_write16(dev, 0x5D, 0x88);
1163                 b43_radio_write16(dev, 0x5E, 0x88);
1164                 b43_radio_write16(dev, 0x7D, 0x88);
1165                 b43_hf_write(dev, b43_hf_read(dev)
1166                              | B43_HF_TSSIRPSMW);
1167         }
1168         B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
1169         if (phy->radio_rev == 8) {
1170                 b43_radio_write16(dev, 0x51, 0);
1171                 b43_radio_write16(dev, 0x52, 0x40);
1172                 b43_radio_write16(dev, 0x53, 0xB7);
1173                 b43_radio_write16(dev, 0x54, 0x98);
1174                 b43_radio_write16(dev, 0x5A, 0x88);
1175                 b43_radio_write16(dev, 0x5B, 0x6B);
1176                 b43_radio_write16(dev, 0x5C, 0x0F);
1177                 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1178                         b43_radio_write16(dev, 0x5D, 0xFA);
1179                         b43_radio_write16(dev, 0x5E, 0xD8);
1180                 } else {
1181                         b43_radio_write16(dev, 0x5D, 0xF5);
1182                         b43_radio_write16(dev, 0x5E, 0xB8);
1183                 }
1184                 b43_radio_write16(dev, 0x0073, 0x0003);
1185                 b43_radio_write16(dev, 0x007D, 0x00A8);
1186                 b43_radio_write16(dev, 0x007C, 0x0001);
1187                 b43_radio_write16(dev, 0x007E, 0x0008);
1188         }
1189         val = 0x1E1F;
1190         for (offset = 0x0088; offset < 0x0098; offset++) {
1191                 b43_phy_write(dev, offset, val);
1192                 val -= 0x0202;
1193         }
1194         val = 0x3E3F;
1195         for (offset = 0x0098; offset < 0x00A8; offset++) {
1196                 b43_phy_write(dev, offset, val);
1197                 val -= 0x0202;
1198         }
1199         val = 0x2120;
1200         for (offset = 0x00A8; offset < 0x00C8; offset++) {
1201                 b43_phy_write(dev, offset, (val & 0x3F3F));
1202                 val += 0x0202;
1203         }
1204         if (phy->type == B43_PHYTYPE_G) {
1205                 b43_radio_write16(dev, 0x007A,
1206                                   b43_radio_read16(dev, 0x007A) | 0x0020);
1207                 b43_radio_write16(dev, 0x0051,
1208                                   b43_radio_read16(dev, 0x0051) | 0x0004);
1209                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1210                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1211                 b43_phy_write(dev, 0x5B, 0);
1212                 b43_phy_write(dev, 0x5C, 0);
1213         }
1214
1215         old_channel = phy->channel;
1216         if (old_channel >= 8)
1217                 b43_radio_selectchannel(dev, 1, 0);
1218         else
1219                 b43_radio_selectchannel(dev, 13, 0);
1220
1221         b43_radio_write16(dev, 0x0050, 0x0020);
1222         b43_radio_write16(dev, 0x0050, 0x0023);
1223         udelay(40);
1224         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1225                 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1226                                               | 0x0002));
1227                 b43_radio_write16(dev, 0x50, 0x20);
1228         }
1229         if (phy->radio_rev <= 2) {
1230                 b43_radio_write16(dev, 0x7C, 0x20);
1231                 b43_radio_write16(dev, 0x5A, 0x70);
1232                 b43_radio_write16(dev, 0x5B, 0x7B);
1233                 b43_radio_write16(dev, 0x5C, 0xB0);
1234         }
1235         b43_radio_write16(dev, 0x007A,
1236                           (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1237
1238         b43_radio_selectchannel(dev, old_channel, 0);
1239
1240         b43_phy_write(dev, 0x0014, 0x0200);
1241         if (phy->radio_rev >= 6)
1242                 b43_phy_write(dev, 0x2A, 0x88C2);
1243         else
1244                 b43_phy_write(dev, 0x2A, 0x8AC0);
1245         b43_phy_write(dev, 0x0038, 0x0668);
1246         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1247         if (phy->radio_rev <= 5) {
1248                 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1249                                           & 0xFF80) | 0x0003);
1250         }
1251         if (phy->radio_rev <= 2)
1252                 b43_radio_write16(dev, 0x005D, 0x000D);
1253
1254         if (phy->analog == 4) {
1255                 b43_write16(dev, 0x3E4, 9);
1256                 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1257                               & 0x0FFF);
1258         } else {
1259                 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1260                               | 0x0004);
1261         }
1262         if (phy->type == B43_PHYTYPE_B) {
1263                 b43_write16(dev, 0x03E6, 0x8140);
1264                 b43_phy_write(dev, 0x0016, 0x0410);
1265                 b43_phy_write(dev, 0x0017, 0x0820);
1266                 b43_phy_write(dev, 0x0062, 0x0007);
1267                 b43_radio_init2050(dev);
1268                 b43_lo_g_measure(dev);
1269                 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
1270                         b43_calc_nrssi_slope(dev);
1271                         b43_calc_nrssi_threshold(dev);
1272                 }
1273                 b43_phy_init_pctl(dev);
1274         } else if (phy->type == B43_PHYTYPE_G)
1275                 b43_write16(dev, 0x03E6, 0x0);
1276 }
1277
1278 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1279 {
1280         struct b43_phy *phy = &dev->phy;
1281         u16 backup_phy[16] = { 0 };
1282         u16 backup_radio[3];
1283         u16 backup_bband;
1284         u16 i, j, loop_i_max;
1285         u16 trsw_rx;
1286         u16 loop1_outer_done, loop1_inner_done;
1287
1288         backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1289         backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1290         backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1291         backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1292         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1293                 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1294                 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1295         }
1296         backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1297         backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1298         backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1299         backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1300         backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1301         backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1302         backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1303         backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1304         backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1305         backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1306         backup_bband = phy->bbatt.att;
1307         backup_radio[0] = b43_radio_read16(dev, 0x52);
1308         backup_radio[1] = b43_radio_read16(dev, 0x43);
1309         backup_radio[2] = b43_radio_read16(dev, 0x7A);
1310
1311         b43_phy_write(dev, B43_PHY_CRS0,
1312                       b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1313         b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1314                       b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1315         b43_phy_write(dev, B43_PHY_RFOVER,
1316                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1317         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1318                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1319         b43_phy_write(dev, B43_PHY_RFOVER,
1320                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1321         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1322                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1323         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1324                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1325                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1326                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1327                               b43_phy_read(dev,
1328                                            B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1329                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1330                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1331                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1332                               b43_phy_read(dev,
1333                                            B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1334         }
1335         b43_phy_write(dev, B43_PHY_RFOVER,
1336                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1337         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1338                       b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1339         b43_phy_write(dev, B43_PHY_RFOVER,
1340                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1341         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1342                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1343                        & 0xFFCF) | 0x10);
1344
1345         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1346         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1347         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1348
1349         b43_phy_write(dev, B43_PHY_CCK(0x0A),
1350                       b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
1351         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1352                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1353                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1354                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1355                               b43_phy_read(dev,
1356                                            B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1357         }
1358         b43_phy_write(dev, B43_PHY_CCK(0x03),
1359                       (b43_phy_read(dev, B43_PHY_CCK(0x03))
1360                        & 0xFF9F) | 0x40);
1361
1362         if (phy->radio_rev == 8) {
1363                 b43_radio_write16(dev, 0x43, 0x000F);
1364         } else {
1365                 b43_radio_write16(dev, 0x52, 0);
1366                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1367                                               & 0xFFF0) | 0x9);
1368         }
1369         b43_phy_set_baseband_attenuation(dev, 11);
1370
1371         if (phy->rev >= 3)
1372                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1373         else
1374                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1375         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1376
1377         b43_phy_write(dev, B43_PHY_CCK(0x2B),
1378                       (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1379                        & 0xFFC0) | 0x01);
1380         b43_phy_write(dev, B43_PHY_CCK(0x2B),
1381                       (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1382                        & 0xC0FF) | 0x800);
1383
1384         b43_phy_write(dev, B43_PHY_RFOVER,
1385                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1386         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1387                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1388
1389         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1390                 if (phy->rev >= 7) {
1391                         b43_phy_write(dev, B43_PHY_RFOVER,
1392                                       b43_phy_read(dev, B43_PHY_RFOVER)
1393                                       | 0x0800);
1394                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1395                                       b43_phy_read(dev, B43_PHY_RFOVERVAL)
1396                                       | 0x8000);
1397                 }
1398         }
1399         b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1400                           & 0x00F7);
1401
1402         j = 0;
1403         loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1404         for (i = 0; i < loop_i_max; i++) {
1405                 for (j = 0; j < 16; j++) {
1406                         b43_radio_write16(dev, 0x43, i);
1407                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1408                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1409                                        & 0xF0FF) | (j << 8));
1410                         b43_phy_write(dev, B43_PHY_PGACTL,
1411                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1412                                        & 0x0FFF) | 0xA000);
1413                         b43_phy_write(dev, B43_PHY_PGACTL,
1414                                       b43_phy_read(dev, B43_PHY_PGACTL)
1415                                       | 0xF000);
1416                         udelay(20);
1417                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1418                                 goto exit_loop1;
1419                 }
1420         }
1421       exit_loop1:
1422         loop1_outer_done = i;
1423         loop1_inner_done = j;
1424         if (j >= 8) {
1425                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1426                               b43_phy_read(dev, B43_PHY_RFOVERVAL)
1427                               | 0x30);
1428                 trsw_rx = 0x1B;
1429                 for (j = j - 8; j < 16; j++) {
1430                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1431                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1432                                        & 0xF0FF) | (j << 8));
1433                         b43_phy_write(dev, B43_PHY_PGACTL,
1434                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1435                                        & 0x0FFF) | 0xA000);
1436                         b43_phy_write(dev, B43_PHY_PGACTL,
1437                                       b43_phy_read(dev, B43_PHY_PGACTL)
1438                                       | 0xF000);
1439                         udelay(20);
1440                         trsw_rx -= 3;
1441                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1442                                 goto exit_loop2;
1443                 }
1444         } else
1445                 trsw_rx = 0x18;
1446       exit_loop2:
1447
1448         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1449                 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1450                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1451         }
1452         b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1453         b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1454         b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1455         b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1456         b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1457         b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1458         b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1459         b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1460         b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1461
1462         b43_phy_set_baseband_attenuation(dev, backup_bband);
1463
1464         b43_radio_write16(dev, 0x52, backup_radio[0]);
1465         b43_radio_write16(dev, 0x43, backup_radio[1]);
1466         b43_radio_write16(dev, 0x7A, backup_radio[2]);
1467
1468         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1469         udelay(10);
1470         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1471         b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1472         b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1473         b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1474
1475         phy->max_lb_gain =
1476             ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1477         phy->trsw_rx_gain = trsw_rx * 2;
1478 }
1479
1480 static void b43_phy_initg(struct b43_wldev *dev)
1481 {
1482         struct b43_phy *phy = &dev->phy;
1483         u16 tmp;
1484
1485         if (phy->rev == 1)
1486                 b43_phy_initb5(dev);
1487         else
1488                 b43_phy_initb6(dev);
1489
1490         if (phy->rev >= 2 || phy->gmode)
1491                 b43_phy_inita(dev);
1492
1493         if (phy->rev >= 2) {
1494                 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1495                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1496         }
1497         if (phy->rev == 2) {
1498                 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1499                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1500         }
1501         if (phy->rev > 5) {
1502                 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1503                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1504         }
1505         if (phy->gmode || phy->rev >= 2) {
1506                 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1507                 tmp &= B43_PHYVER_VERSION;
1508                 if (tmp == 3 || tmp == 5) {
1509                         b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1510                         b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1511                 }
1512                 if (tmp == 5) {
1513                         b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1514                                       (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1515                                        & 0x00FF) | 0x1F00);
1516                 }
1517         }
1518         if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1519                 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1520         if (phy->radio_rev == 8) {
1521                 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1522                               b43_phy_read(dev, B43_PHY_EXTG(0x01))
1523                               | 0x80);
1524                 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1525                               b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1526                               | 0x4);
1527         }
1528         if (has_loopback_gain(phy))
1529                 b43_calc_loopback_gain(dev);
1530
1531         if (phy->radio_rev != 8) {
1532                 if (phy->initval == 0xFFFF)
1533                         phy->initval = b43_radio_init2050(dev);
1534                 else
1535                         b43_radio_write16(dev, 0x0078, phy->initval);
1536         }
1537         if (phy->lo_control->tx_bias == 0xFF) {
1538                 b43_lo_g_measure(dev);
1539         } else {
1540                 if (has_tx_magnification(phy)) {
1541                         b43_radio_write16(dev, 0x52,
1542                                           (b43_radio_read16(dev, 0x52) & 0xFF00)
1543                                           | phy->lo_control->tx_bias | phy->
1544                                           lo_control->tx_magn);
1545                 } else {
1546                         b43_radio_write16(dev, 0x52,
1547                                           (b43_radio_read16(dev, 0x52) & 0xFFF0)
1548                                           | phy->lo_control->tx_bias);
1549                 }
1550                 if (phy->rev >= 6) {
1551                         b43_phy_write(dev, B43_PHY_CCK(0x36),
1552                                       (b43_phy_read(dev, B43_PHY_CCK(0x36))
1553                                        & 0x0FFF) | (phy->lo_control->
1554                                                     tx_bias << 12));
1555                 }
1556                 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
1557                         b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
1558                 else
1559                         b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
1560                 if (phy->rev < 2)
1561                         b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
1562                 else
1563                         b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
1564         }
1565         if (phy->gmode || phy->rev >= 2) {
1566                 b43_lo_g_adjust(dev);
1567                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1568         }
1569
1570         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
1571                 /* The specs state to update the NRSSI LT with
1572                  * the value 0x7FFFFFFF here. I think that is some weird
1573                  * compiler optimization in the original driver.
1574                  * Essentially, what we do here is resetting all NRSSI LT
1575                  * entries to -32 (see the limit_value() in nrssi_hw_update())
1576                  */
1577                 b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
1578                 b43_calc_nrssi_threshold(dev);
1579         } else if (phy->gmode || phy->rev >= 2) {
1580                 if (phy->nrssi[0] == -1000) {
1581                         B43_WARN_ON(phy->nrssi[1] != -1000);
1582                         b43_calc_nrssi_slope(dev);
1583                 } else
1584                         b43_calc_nrssi_threshold(dev);
1585         }
1586         if (phy->radio_rev == 8)
1587                 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1588         b43_phy_init_pctl(dev);
1589         /* FIXME: The spec says in the following if, the 0 should be replaced
1590            'if OFDM may not be used in the current locale'
1591            but OFDM is legal everywhere */
1592         if ((dev->dev->bus->chip_id == 0x4306
1593              && dev->dev->bus->chip_package == 2) || 0) {
1594                 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1595                               & 0xBFFF);
1596                 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1597                               b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1598                               & 0x7FFF);
1599         }
1600 }
1601
1602 /* Set the baseband attenuation value on chip. */
1603 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1604                                       u16 baseband_attenuation)
1605 {
1606         struct b43_phy *phy = &dev->phy;
1607
1608         if (phy->analog == 0) {
1609                 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1610                                                  & 0xFFF0) |
1611                             baseband_attenuation);
1612         } else if (phy->analog > 1) {
1613                 b43_phy_write(dev, B43_PHY_DACCTL,
1614                               (b43_phy_read(dev, B43_PHY_DACCTL)
1615                                & 0xFFC3) | (baseband_attenuation << 2));
1616         } else {
1617                 b43_phy_write(dev, B43_PHY_DACCTL,
1618                               (b43_phy_read(dev, B43_PHY_DACCTL)
1619                                & 0xFF87) | (baseband_attenuation << 3));
1620         }
1621 }
1622
1623 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1624  * This function converts a TSSI value to dBm in Q5.2
1625  */
1626 static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1627 {
1628         struct b43_phy *phy = &dev->phy;
1629         s8 dbm = 0;
1630         s32 tmp;
1631
1632         tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1633
1634         switch (phy->type) {
1635         case B43_PHYTYPE_A:
1636                 tmp += 0x80;
1637                 tmp = limit_value(tmp, 0x00, 0xFF);
1638                 dbm = phy->tssi2dbm[tmp];
1639                 //TODO: There's a FIXME on the specs
1640                 break;
1641         case B43_PHYTYPE_B:
1642         case B43_PHYTYPE_G:
1643                 tmp = limit_value(tmp, 0x00, 0x3F);
1644                 dbm = phy->tssi2dbm[tmp];
1645                 break;
1646         default:
1647                 B43_WARN_ON(1);
1648         }
1649
1650         return dbm;
1651 }
1652
1653 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1654                                      int *_bbatt, int *_rfatt)
1655 {
1656         int rfatt = *_rfatt;
1657         int bbatt = *_bbatt;
1658         struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1659
1660         /* Get baseband and radio attenuation values into their permitted ranges.
1661          * Radio attenuation affects power level 4 times as much as baseband. */
1662
1663         /* Range constants */
1664         const int rf_min = lo->rfatt_list.min_val;
1665         const int rf_max = lo->rfatt_list.max_val;
1666         const int bb_min = lo->bbatt_list.min_val;
1667         const int bb_max = lo->bbatt_list.max_val;
1668
1669         while (1) {
1670                 if (rfatt > rf_max && bbatt > bb_max - 4)
1671                         break;  /* Can not get it into ranges */
1672                 if (rfatt < rf_min && bbatt < bb_min + 4)
1673                         break;  /* Can not get it into ranges */
1674                 if (bbatt > bb_max && rfatt > rf_max - 1)
1675                         break;  /* Can not get it into ranges */
1676                 if (bbatt < bb_min && rfatt < rf_min + 1)
1677                         break;  /* Can not get it into ranges */
1678
1679                 if (bbatt > bb_max) {
1680                         bbatt -= 4;
1681                         rfatt += 1;
1682                         continue;
1683                 }
1684                 if (bbatt < bb_min) {
1685                         bbatt += 4;
1686                         rfatt -= 1;
1687                         continue;
1688                 }
1689                 if (rfatt > rf_max) {
1690                         rfatt -= 1;
1691                         bbatt += 4;
1692                         continue;
1693                 }
1694                 if (rfatt < rf_min) {
1695                         rfatt += 1;
1696                         bbatt -= 4;
1697                         continue;
1698                 }
1699                 break;
1700         }
1701
1702         *_rfatt = limit_value(rfatt, rf_min, rf_max);
1703         *_bbatt = limit_value(bbatt, bb_min, bb_max);
1704 }
1705
1706 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1707 void b43_phy_xmitpower(struct b43_wldev *dev)
1708 {
1709         struct ssb_bus *bus = dev->dev->bus;
1710         struct b43_phy *phy = &dev->phy;
1711
1712         if (phy->cur_idle_tssi == 0)
1713                 return;
1714         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1715             (bus->boardinfo.type == SSB_BOARD_BU4306))
1716                 return;
1717 #ifdef CONFIG_B43_DEBUG
1718         if (phy->manual_txpower_control)
1719                 return;
1720 #endif
1721
1722         switch (phy->type) {
1723         case B43_PHYTYPE_A:{
1724
1725                         //TODO: Nothing for A PHYs yet :-/
1726
1727                         break;
1728                 }
1729         case B43_PHYTYPE_B:
1730         case B43_PHYTYPE_G:{
1731                         u16 tmp;
1732                         s8 v0, v1, v2, v3;
1733                         s8 average;
1734                         int max_pwr;
1735                         int desired_pwr, estimated_pwr, pwr_adjust;
1736                         int rfatt_delta, bbatt_delta;
1737                         int rfatt, bbatt;
1738                         u8 tx_control;
1739
1740                         tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
1741                         v0 = (s8) (tmp & 0x00FF);
1742                         v1 = (s8) ((tmp & 0xFF00) >> 8);
1743                         tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
1744                         v2 = (s8) (tmp & 0x00FF);
1745                         v3 = (s8) ((tmp & 0xFF00) >> 8);
1746                         tmp = 0;
1747
1748                         if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
1749                             || v3 == 0x7F) {
1750                                 tmp =
1751                                     b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
1752                                 v0 = (s8) (tmp & 0x00FF);
1753                                 v1 = (s8) ((tmp & 0xFF00) >> 8);
1754                                 tmp =
1755                                     b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
1756                                 v2 = (s8) (tmp & 0x00FF);
1757                                 v3 = (s8) ((tmp & 0xFF00) >> 8);
1758                                 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
1759                                     || v3 == 0x7F)
1760                                         return;
1761                                 v0 = (v0 + 0x20) & 0x3F;
1762                                 v1 = (v1 + 0x20) & 0x3F;
1763                                 v2 = (v2 + 0x20) & 0x3F;
1764                                 v3 = (v3 + 0x20) & 0x3F;
1765                                 tmp = 1;
1766                         }
1767                         b43_shm_clear_tssi(dev);
1768
1769                         average = (v0 + v1 + v2 + v3 + 2) / 4;
1770
1771                         if (tmp
1772                             && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
1773                                 0x8))
1774                                 average -= 13;
1775
1776                         estimated_pwr =
1777                             b43_phy_estimate_power_out(dev, average);
1778
1779                         max_pwr = dev->dev->bus->sprom.maxpwr_bg;
1780                         if ((dev->dev->bus->sprom.boardflags_lo
1781                             & B43_BFL_PACTRL) && (phy->type == B43_PHYTYPE_G))
1782                                 max_pwr -= 0x3;
1783                         if (unlikely(max_pwr <= 0)) {
1784                                 b43warn(dev->wl,
1785                                         "Invalid max-TX-power value in SPROM.\n");
1786                                 max_pwr = 60;   /* fake it */
1787                                 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
1788                         }
1789
1790                         /*TODO:
1791                            max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
1792                            where REG is the max power as per the regulatory domain
1793                          */
1794
1795                         /* Get desired power (in Q5.2) */
1796                         desired_pwr = INT_TO_Q52(phy->power_level);
1797                         /* And limit it. max_pwr already is Q5.2 */
1798                         desired_pwr = limit_value(desired_pwr, 0, max_pwr);
1799                         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
1800                                 b43dbg(dev->wl,
1801                                        "Current TX power output: " Q52_FMT
1802                                        " dBm, " "Desired TX power output: "
1803                                        Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
1804                                        Q52_ARG(desired_pwr));
1805                         }
1806
1807                         /* Calculate the adjustment delta. */
1808                         pwr_adjust = desired_pwr - estimated_pwr;
1809
1810                         /* RF attenuation delta. */
1811                         rfatt_delta = ((pwr_adjust + 7) / 8);
1812                         /* Lower attenuation => Bigger power output. Negate it. */
1813                         rfatt_delta = -rfatt_delta;
1814
1815                         /* Baseband attenuation delta. */
1816                         bbatt_delta = pwr_adjust / 2;
1817                         /* Lower attenuation => Bigger power output. Negate it. */
1818                         bbatt_delta = -bbatt_delta;
1819                         /* RF att affects power level 4 times as much as
1820                          * Baseband attennuation. Subtract it. */
1821                         bbatt_delta -= 4 * rfatt_delta;
1822
1823                         /* So do we finally need to adjust something? */
1824                         if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
1825                                 b43_lo_g_ctl_mark_cur_used(dev);
1826                                 return;
1827                         }
1828
1829                         /* Calculate the new attenuation values. */
1830                         bbatt = phy->bbatt.att;
1831                         bbatt += bbatt_delta;
1832                         rfatt = phy->rfatt.att;
1833                         rfatt += rfatt_delta;
1834
1835                         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
1836                         tx_control = phy->tx_control;
1837                         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
1838                                 if (rfatt <= 1) {
1839                                         if (tx_control == 0) {
1840                                                 tx_control =
1841                                                     B43_TXCTL_PA2DB |
1842                                                     B43_TXCTL_TXMIX;
1843                                                 rfatt += 2;
1844                                                 bbatt += 2;
1845                                         } else if (dev->dev->bus->sprom.
1846                                                    boardflags_lo &
1847                                                    B43_BFL_PACTRL) {
1848                                                 bbatt += 4 * (rfatt - 2);
1849                                                 rfatt = 2;
1850                                         }
1851                                 } else if (rfatt > 4 && tx_control) {
1852                                         tx_control = 0;
1853                                         if (bbatt < 3) {
1854                                                 rfatt -= 3;
1855                                                 bbatt += 2;
1856                                         } else {
1857                                                 rfatt -= 2;
1858                                                 bbatt -= 2;
1859                                         }
1860                                 }
1861                         }
1862                         /* Save the control values */
1863                         phy->tx_control = tx_control;
1864                         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
1865                         phy->rfatt.att = rfatt;
1866                         phy->bbatt.att = bbatt;
1867
1868                         /* Adjust the hardware */
1869                         b43_phy_lock(dev);
1870                         b43_radio_lock(dev);
1871                         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
1872                                           phy->tx_control);
1873                         b43_lo_g_ctl_mark_cur_used(dev);
1874                         b43_radio_unlock(dev);
1875                         b43_phy_unlock(dev);
1876                         break;
1877                 }
1878         case B43_PHYTYPE_N:
1879                 b43_nphy_xmitpower(dev);
1880                 break;
1881         default:
1882                 B43_WARN_ON(1);
1883         }
1884 }
1885
1886 static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
1887 {
1888         if (num < 0)
1889                 return num / den;
1890         else
1891                 return (num + den / 2) / den;
1892 }
1893
1894 static inline
1895     s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
1896 {
1897         s32 m1, m2, f = 256, q, delta;
1898         s8 i = 0;
1899
1900         m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
1901         m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
1902         do {
1903                 if (i > 15)
1904                         return -EINVAL;
1905                 q = b43_tssi2dbm_ad(f * 4096 -
1906                                     b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
1907                 delta = abs(q - f);
1908                 f = q;
1909                 i++;
1910         } while (delta >= 2);
1911         entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
1912         return 0;
1913 }
1914
1915 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1916 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
1917 {
1918         struct b43_phy *phy = &dev->phy;
1919         s16 pab0, pab1, pab2;
1920         u8 idx;
1921         s8 *dyn_tssi2dbm;
1922
1923         if (phy->type == B43_PHYTYPE_A) {
1924                 pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
1925                 pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
1926                 pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
1927         } else {
1928                 pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
1929                 pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
1930                 pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
1931         }
1932
1933         if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
1934                 phy->tgt_idle_tssi = 0x34;
1935                 phy->tssi2dbm = b43_tssi2dbm_b_table;
1936                 return 0;
1937         }
1938
1939         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
1940             pab0 != -1 && pab1 != -1 && pab2 != -1) {
1941                 /* The pabX values are set in SPROM. Use them. */
1942                 if (phy->type == B43_PHYTYPE_A) {
1943                         if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
1944                             (s8) dev->dev->bus->sprom.itssi_a != -1)
1945                                 phy->tgt_idle_tssi =
1946                                     (s8) (dev->dev->bus->sprom.itssi_a);
1947                         else
1948                                 phy->tgt_idle_tssi = 62;
1949                 } else {
1950                         if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
1951                             (s8) dev->dev->bus->sprom.itssi_bg != -1)
1952                                 phy->tgt_idle_tssi =
1953                                     (s8) (dev->dev->bus->sprom.itssi_bg);
1954                         else
1955                                 phy->tgt_idle_tssi = 62;
1956                 }
1957                 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
1958                 if (dyn_tssi2dbm == NULL) {
1959                         b43err(dev->wl, "Could not allocate memory "
1960                                "for tssi2dbm table\n");
1961                         return -ENOMEM;
1962                 }
1963                 for (idx = 0; idx < 64; idx++)
1964                         if (b43_tssi2dbm_entry
1965                             (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
1966                                 phy->tssi2dbm = NULL;
1967                                 b43err(dev->wl, "Could not generate "
1968                                        "tssi2dBm table\n");
1969                                 kfree(dyn_tssi2dbm);
1970                                 return -ENODEV;
1971                         }
1972                 phy->tssi2dbm = dyn_tssi2dbm;
1973                 phy->dyn_tssi_tbl = 1;
1974         } else {
1975                 /* pabX values not set in SPROM. */
1976                 switch (phy->type) {
1977                 case B43_PHYTYPE_A:
1978                         /* APHY needs a generated table. */
1979                         phy->tssi2dbm = NULL;
1980                         b43err(dev->wl, "Could not generate tssi2dBm "
1981                                "table (wrong SPROM info)!\n");
1982                         return -ENODEV;
1983                 case B43_PHYTYPE_B:
1984                         phy->tgt_idle_tssi = 0x34;
1985                         phy->tssi2dbm = b43_tssi2dbm_b_table;
1986                         break;
1987                 case B43_PHYTYPE_G:
1988                         phy->tgt_idle_tssi = 0x34;
1989                         phy->tssi2dbm = b43_tssi2dbm_g_table;
1990                         break;
1991                 }
1992         }
1993
1994         return 0;
1995 }
1996
1997 int b43_phy_init(struct b43_wldev *dev)
1998 {
1999         struct b43_phy *phy = &dev->phy;
2000         bool unsupported = 0;
2001         int err = 0;
2002
2003         switch (phy->type) {
2004         case B43_PHYTYPE_A:
2005                 if (phy->rev == 2 || phy->rev == 3)
2006                         b43_phy_inita(dev);
2007                 else
2008                         unsupported = 1;
2009                 break;
2010         case B43_PHYTYPE_B:
2011                 switch (phy->rev) {
2012                 case 2:
2013                         b43_phy_initb2(dev);
2014                         break;
2015                 case 4:
2016                         b43_phy_initb4(dev);
2017                         break;
2018                 case 5:
2019                         b43_phy_initb5(dev);
2020                         break;
2021                 case 6:
2022                         b43_phy_initb6(dev);
2023                         break;
2024                 default:
2025                         unsupported = 1;
2026                 }
2027                 break;
2028         case B43_PHYTYPE_G:
2029                 b43_phy_initg(dev);
2030                 break;
2031         case B43_PHYTYPE_N:
2032                 err = b43_phy_initn(dev);
2033                 break;
2034         default:
2035                 unsupported = 1;
2036         }
2037         if (unsupported)
2038                 b43err(dev->wl, "Unknown PHYTYPE found\n");
2039
2040         return err;
2041 }
2042
2043 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2044 {
2045         struct b43_phy *phy = &dev->phy;
2046         u64 hf;
2047         u16 tmp;
2048         int autodiv = 0;
2049
2050         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2051                 autodiv = 1;
2052
2053         hf = b43_hf_read(dev);
2054         hf &= ~B43_HF_ANTDIVHELP;
2055         b43_hf_write(dev, hf);
2056
2057         switch (phy->type) {
2058         case B43_PHYTYPE_A:
2059         case B43_PHYTYPE_G:
2060                 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2061                 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2062                 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2063                     << B43_PHY_BBANDCFG_RXANT_SHIFT;
2064                 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2065
2066                 if (autodiv) {
2067                         tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2068                         if (antenna == B43_ANTENNA_AUTO0)
2069                                 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2070                         else
2071                                 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2072                         b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2073                 }
2074                 if (phy->type == B43_PHYTYPE_G) {
2075                         tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2076                         if (autodiv)
2077                                 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2078                         else
2079                                 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2080                         b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2081                         if (phy->rev >= 2) {
2082                                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2083                                 tmp |= B43_PHY_OFDM61_10;
2084                                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2085
2086                                 tmp =
2087                                     b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2088                                 tmp = (tmp & 0xFF00) | 0x15;
2089                                 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2090                                               tmp);
2091
2092                                 if (phy->rev == 2) {
2093                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2094                                                       8);
2095                                 } else {
2096                                         tmp =
2097                                             b43_phy_read(dev,
2098                                                          B43_PHY_ADIVRELATED);
2099                                         tmp = (tmp & 0xFF00) | 8;
2100                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2101                                                       tmp);
2102                                 }
2103                         }
2104                         if (phy->rev >= 6)
2105                                 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2106                 } else {
2107                         if (phy->rev < 3) {
2108                                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2109                                 tmp = (tmp & 0xFF00) | 0x24;
2110                                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2111                         } else {
2112                                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2113                                 tmp |= 0x10;
2114                                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2115                                 if (phy->analog == 3) {
2116                                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2117                                                       0x1D);
2118                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2119                                                       8);
2120                                 } else {
2121                                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2122                                                       0x3A);
2123                                         tmp =
2124                                             b43_phy_read(dev,
2125                                                          B43_PHY_ADIVRELATED);
2126                                         tmp = (tmp & 0xFF00) | 8;
2127                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2128                                                       tmp);
2129                                 }
2130                         }
2131                 }
2132                 break;
2133         case B43_PHYTYPE_B:
2134                 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
2135                 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2136                 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2137                     << B43_PHY_BBANDCFG_RXANT_SHIFT;
2138                 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2139                 break;
2140         case B43_PHYTYPE_N:
2141                 b43_nphy_set_rxantenna(dev, antenna);
2142                 break;
2143         default:
2144                 B43_WARN_ON(1);
2145         }
2146
2147         hf |= B43_HF_ANTDIVHELP;
2148         b43_hf_write(dev, hf);
2149 }
2150
2151 /* Get the freq, as it has to be written to the device. */
2152 static inline u16 channel2freq_bg(u8 channel)
2153 {
2154         B43_WARN_ON(!(channel >= 1 && channel <= 14));
2155
2156         return b43_radio_channel_codes_bg[channel - 1];
2157 }
2158
2159 /* Get the freq, as it has to be written to the device. */
2160 static inline u16 channel2freq_a(u8 channel)
2161 {
2162         B43_WARN_ON(channel > 200);
2163
2164         return (5000 + 5 * channel);
2165 }
2166
2167 void b43_radio_lock(struct b43_wldev *dev)
2168 {
2169         u32 macctl;
2170
2171         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2172         B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
2173         macctl |= B43_MACCTL_RADIOLOCK;
2174         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2175         /* Commit the write and wait for the device
2176          * to exit any radio register access. */
2177         b43_read32(dev, B43_MMIO_MACCTL);
2178         udelay(10);
2179 }
2180
2181 void b43_radio_unlock(struct b43_wldev *dev)
2182 {
2183         u32 macctl;
2184
2185         /* Commit any write */
2186         b43_read16(dev, B43_MMIO_PHY_VER);
2187         /* unlock */
2188         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2189         B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
2190         macctl &= ~B43_MACCTL_RADIOLOCK;
2191         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2192 }
2193
2194 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2195 {
2196         struct b43_phy *phy = &dev->phy;
2197
2198         /* Offset 1 is a 32-bit register. */
2199         B43_WARN_ON(offset == 1);
2200
2201         switch (phy->type) {
2202         case B43_PHYTYPE_A:
2203                 offset |= 0x40;
2204                 break;
2205         case B43_PHYTYPE_B:
2206                 if (phy->radio_ver == 0x2053) {
2207                         if (offset < 0x70)
2208                                 offset += 0x80;
2209                         else if (offset < 0x80)
2210                                 offset += 0x70;
2211                 } else if (phy->radio_ver == 0x2050) {
2212                         offset |= 0x80;
2213                 } else
2214                         B43_WARN_ON(1);
2215                 break;
2216         case B43_PHYTYPE_G:
2217                 offset |= 0x80;
2218                 break;
2219         case B43_PHYTYPE_N:
2220                 offset |= 0x100;
2221                 break;
2222         case B43_PHYTYPE_LP:
2223                 /* No adjustment required. */
2224                 break;
2225         default:
2226                 B43_WARN_ON(1);
2227         }
2228
2229         b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2230         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2231 }
2232
2233 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2234 {
2235         /* Offset 1 is a 32-bit register. */
2236         B43_WARN_ON(offset == 1);
2237
2238         b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2239         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2240 }
2241
2242 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
2243 {
2244         b43_radio_write16(dev, offset,
2245                           b43_radio_read16(dev, offset) & mask);
2246 }
2247
2248 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
2249 {
2250         b43_radio_write16(dev, offset,
2251                           b43_radio_read16(dev, offset) | set);
2252 }
2253
2254 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
2255 {
2256         b43_radio_write16(dev, offset,
2257                           (b43_radio_read16(dev, offset) & mask) | set);
2258 }
2259
2260 static void b43_set_all_gains(struct b43_wldev *dev,
2261                               s16 first, s16 second, s16 third)
2262 {
2263         struct b43_phy *phy = &dev->phy;
2264         u16 i;
2265         u16 start = 0x08, end = 0x18;
2266         u16 tmp;
2267         u16 table;
2268
2269         if (phy->rev <= 1) {
2270                 start = 0x10;
2271                 end = 0x20;
2272         }
2273
2274         table = B43_OFDMTAB_GAINX;
2275         if (phy->rev <= 1)
2276                 table = B43_OFDMTAB_GAINX_R1;
2277         for (i = 0; i < 4; i++)
2278                 b43_ofdmtab_write16(dev, table, i, first);
2279
2280         for (i = start; i < end; i++)
2281                 b43_ofdmtab_write16(dev, table, i, second);
2282
2283         if (third != -1) {
2284                 tmp = ((u16) third << 14) | ((u16) third << 6);
2285                 b43_phy_write(dev, 0x04A0,
2286                               (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2287                 b43_phy_write(dev, 0x04A1,
2288                               (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2289                 b43_phy_write(dev, 0x04A2,
2290                               (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2291         }
2292         b43_dummy_transmission(dev);
2293 }
2294
2295 static void b43_set_original_gains(struct b43_wldev *dev)
2296 {
2297         struct b43_phy *phy = &dev->phy;
2298         u16 i, tmp;
2299         u16 table;
2300         u16 start = 0x0008, end = 0x0018;
2301
2302         if (phy->rev <= 1) {
2303                 start = 0x0010;
2304                 end = 0x0020;
2305         }
2306
2307         table = B43_OFDMTAB_GAINX;
2308         if (phy->rev <= 1)
2309                 table = B43_OFDMTAB_GAINX_R1;
2310         for (i = 0; i < 4; i++) {
2311                 tmp = (i & 0xFFFC);
2312                 tmp |= (i & 0x0001) << 1;
2313                 tmp |= (i & 0x0002) >> 1;
2314
2315                 b43_ofdmtab_write16(dev, table, i, tmp);
2316         }
2317
2318         for (i = start; i < end; i++)
2319                 b43_ofdmtab_write16(dev, table, i, i - start);
2320
2321         b43_phy_write(dev, 0x04A0,
2322                       (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2323         b43_phy_write(dev, 0x04A1,
2324                       (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2325         b43_phy_write(dev, 0x04A2,
2326                       (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2327         b43_dummy_transmission(dev);
2328 }
2329
2330 /* Synthetic PU workaround */
2331 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2332 {
2333         struct b43_phy *phy = &dev->phy;
2334
2335         might_sleep();
2336
2337         if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2338                 /* We do not need the workaround. */
2339                 return;
2340         }
2341
2342         if (channel <= 10) {
2343                 b43_write16(dev, B43_MMIO_CHANNEL,
2344                             channel2freq_bg(channel + 4));
2345         } else {
2346                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2347         }
2348         msleep(1);
2349         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2350 }
2351
2352 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2353 {
2354         struct b43_phy *phy = &dev->phy;
2355         u8 ret = 0;
2356         u16 saved, rssi, temp;
2357         int i, j = 0;
2358
2359         saved = b43_phy_read(dev, 0x0403);
2360         b43_radio_selectchannel(dev, channel, 0);
2361         b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2362         if (phy->aci_hw_rssi)
2363                 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2364         else
2365                 rssi = saved & 0x3F;
2366         /* clamp temp to signed 5bit */
2367         if (rssi > 32)
2368                 rssi -= 64;
2369         for (i = 0; i < 100; i++) {
2370                 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2371                 if (temp > 32)
2372                         temp -= 64;
2373                 if (temp < rssi)
2374                         j++;
2375                 if (j >= 20)
2376                         ret = 1;
2377         }
2378         b43_phy_write(dev, 0x0403, saved);
2379
2380         return ret;
2381 }
2382
2383 u8 b43_radio_aci_scan(struct b43_wldev * dev)
2384 {
2385         struct b43_phy *phy = &dev->phy;
2386         u8 ret[13];
2387         unsigned int channel = phy->channel;
2388         unsigned int i, j, start, end;
2389
2390         if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2391                 return 0;
2392
2393         b43_phy_lock(dev);
2394         b43_radio_lock(dev);
2395         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2396         b43_phy_write(dev, B43_PHY_G_CRS,
2397                       b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2398         b43_set_all_gains(dev, 3, 8, 1);
2399
2400         start = (channel - 5 > 0) ? channel - 5 : 1;
2401         end = (channel + 5 < 14) ? channel + 5 : 13;
2402
2403         for (i = start; i <= end; i++) {
2404                 if (abs(channel - i) > 2)
2405                         ret[i - 1] = b43_radio_aci_detect(dev, i);
2406         }
2407         b43_radio_selectchannel(dev, channel, 0);
2408         b43_phy_write(dev, 0x0802,
2409                       (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2410         b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2411         b43_phy_write(dev, B43_PHY_G_CRS,
2412                       b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2413         b43_set_original_gains(dev);
2414         for (i = 0; i < 13; i++) {
2415                 if (!ret[i])
2416                         continue;
2417                 end = (i + 5 < 13) ? i + 5 : 13;
2418                 for (j = i; j < end; j++)
2419                         ret[j] = 1;
2420         }
2421         b43_radio_unlock(dev);
2422         b43_phy_unlock(dev);
2423
2424         return ret[channel - 1];
2425 }
2426
2427 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2428 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2429 {
2430         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2431         mmiowb();
2432         b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2433 }
2434
2435 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2436 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2437 {
2438         u16 val;
2439
2440         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2441         val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2442
2443         return (s16) val;
2444 }
2445
2446 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2447 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2448 {
2449         u16 i;
2450         s16 tmp;
2451
2452         for (i = 0; i < 64; i++) {
2453                 tmp = b43_nrssi_hw_read(dev, i);
2454                 tmp -= val;
2455                 tmp = limit_value(tmp, -32, 31);
2456                 b43_nrssi_hw_write(dev, i, tmp);
2457         }
2458 }
2459
2460 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2461 void b43_nrssi_mem_update(struct b43_wldev *dev)
2462 {
2463         struct b43_phy *phy = &dev->phy;
2464         s16 i, delta;
2465         s32 tmp;
2466
2467         delta = 0x1F - phy->nrssi[0];
2468         for (i = 0; i < 64; i++) {
2469                 tmp = (i - delta) * phy->nrssislope;
2470                 tmp /= 0x10000;
2471                 tmp += 0x3A;
2472                 tmp = limit_value(tmp, 0, 0x3F);
2473                 phy->nrssi_lt[i] = tmp;
2474         }
2475 }
2476
2477 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2478 {
2479         struct b43_phy *phy = &dev->phy;
2480         u16 backup[20] = { 0 };
2481         s16 v47F;
2482         u16 i;
2483         u16 saved = 0xFFFF;
2484
2485         backup[0] = b43_phy_read(dev, 0x0001);
2486         backup[1] = b43_phy_read(dev, 0x0811);
2487         backup[2] = b43_phy_read(dev, 0x0812);
2488         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2489                 backup[3] = b43_phy_read(dev, 0x0814);
2490                 backup[4] = b43_phy_read(dev, 0x0815);
2491         }
2492         backup[5] = b43_phy_read(dev, 0x005A);
2493         backup[6] = b43_phy_read(dev, 0x0059);
2494         backup[7] = b43_phy_read(dev, 0x0058);
2495         backup[8] = b43_phy_read(dev, 0x000A);
2496         backup[9] = b43_phy_read(dev, 0x0003);
2497         backup[10] = b43_radio_read16(dev, 0x007A);
2498         backup[11] = b43_radio_read16(dev, 0x0043);
2499
2500         b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2501         b43_phy_write(dev, 0x0001,
2502                       (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2503         b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2504         b43_phy_write(dev, 0x0812,
2505                       (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2506         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2507         if (phy->rev >= 6) {
2508                 backup[12] = b43_phy_read(dev, 0x002E);
2509                 backup[13] = b43_phy_read(dev, 0x002F);
2510                 backup[14] = b43_phy_read(dev, 0x080F);
2511                 backup[15] = b43_phy_read(dev, 0x0810);
2512                 backup[16] = b43_phy_read(dev, 0x0801);
2513                 backup[17] = b43_phy_read(dev, 0x0060);
2514                 backup[18] = b43_phy_read(dev, 0x0014);
2515                 backup[19] = b43_phy_read(dev, 0x0478);
2516
2517                 b43_phy_write(dev, 0x002E, 0);
2518                 b43_phy_write(dev, 0x002F, 0);
2519                 b43_phy_write(dev, 0x080F, 0);
2520                 b43_phy_write(dev, 0x0810, 0);
2521                 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2522                 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2523                 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2524                 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2525         }
2526         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2527         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2528         udelay(30);
2529
2530         v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2531         if (v47F >= 0x20)
2532                 v47F -= 0x40;
2533         if (v47F == 31) {
2534                 for (i = 7; i >= 4; i--) {
2535                         b43_radio_write16(dev, 0x007B, i);
2536                         udelay(20);
2537                         v47F =
2538                             (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2539                         if (v47F >= 0x20)
2540                                 v47F -= 0x40;
2541                         if (v47F < 31 && saved == 0xFFFF)
2542                                 saved = i;
2543                 }
2544                 if (saved == 0xFFFF)
2545                         saved = 4;
2546         } else {
2547                 b43_radio_write16(dev, 0x007A,
2548                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2549                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2550                         b43_phy_write(dev, 0x0814,
2551                                       b43_phy_read(dev, 0x0814) | 0x0001);
2552                         b43_phy_write(dev, 0x0815,
2553                                       b43_phy_read(dev, 0x0815) & 0xFFFE);
2554                 }
2555                 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2556                 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2557                 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2558                 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2559                 b43_phy_write(dev, 0x005A, 0x0480);
2560                 b43_phy_write(dev, 0x0059, 0x0810);
2561                 b43_phy_write(dev, 0x0058, 0x000D);
2562                 if (phy->rev == 0) {
2563                         b43_phy_write(dev, 0x0003, 0x0122);
2564                 } else {
2565                         b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2566                                       | 0x2000);
2567                 }
2568                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2569                         b43_phy_write(dev, 0x0814,
2570                                       b43_phy_read(dev, 0x0814) | 0x0004);
2571                         b43_phy_write(dev, 0x0815,
2572                                       b43_phy_read(dev, 0x0815) & 0xFFFB);
2573                 }
2574                 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2575                               | 0x0040);
2576                 b43_radio_write16(dev, 0x007A,
2577                                   b43_radio_read16(dev, 0x007A) | 0x000F);
2578                 b43_set_all_gains(dev, 3, 0, 1);
2579                 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2580                                                 & 0x00F0) | 0x000F);
2581                 udelay(30);
2582                 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2583                 if (v47F >= 0x20)
2584                         v47F -= 0x40;
2585                 if (v47F == -32) {
2586                         for (i = 0; i < 4; i++) {
2587                                 b43_radio_write16(dev, 0x007B, i);
2588                                 udelay(20);
2589                                 v47F =
2590                                     (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2591                                            0x003F);
2592                                 if (v47F >= 0x20)
2593                                         v47F -= 0x40;
2594                                 if (v47F > -31 && saved == 0xFFFF)
2595                                         saved = i;
2596                         }
2597                         if (saved == 0xFFFF)
2598                                 saved = 3;
2599                 } else
2600                         saved = 0;
2601         }
2602         b43_radio_write16(dev, 0x007B, saved);
2603
2604         if (phy->rev >= 6) {
2605                 b43_phy_write(dev, 0x002E, backup[12]);
2606                 b43_phy_write(dev, 0x002F, backup[13]);
2607                 b43_phy_write(dev, 0x080F, backup[14]);
2608                 b43_phy_write(dev, 0x0810, backup[15]);
2609         }
2610         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2611                 b43_phy_write(dev, 0x0814, backup[3]);
2612                 b43_phy_write(dev, 0x0815, backup[4]);
2613         }
2614         b43_phy_write(dev, 0x005A, backup[5]);
2615         b43_phy_write(dev, 0x0059, backup[6]);
2616         b43_phy_write(dev, 0x0058, backup[7]);
2617         b43_phy_write(dev, 0x000A, backup[8]);
2618         b43_phy_write(dev, 0x0003, backup[9]);
2619         b43_radio_write16(dev, 0x0043, backup[11]);
2620         b43_radio_write16(dev, 0x007A, backup[10]);
2621         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2622         b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2623         b43_set_original_gains(dev);
2624         if (phy->rev >= 6) {
2625                 b43_phy_write(dev, 0x0801, backup[16]);
2626                 b43_phy_write(dev, 0x0060, backup[17]);
2627                 b43_phy_write(dev, 0x0014, backup[18]);
2628                 b43_phy_write(dev, 0x0478, backup[19]);
2629         }
2630         b43_phy_write(dev, 0x0001, backup[0]);
2631         b43_phy_write(dev, 0x0812, backup[2]);
2632         b43_phy_write(dev, 0x0811, backup[1]);
2633 }
2634
2635 void b43_calc_nrssi_slope(struct b43_wldev *dev)
2636 {
2637         struct b43_phy *phy = &dev->phy;
2638         u16 backup[18] = { 0 };
2639         u16 tmp;
2640         s16 nrssi0, nrssi1;
2641
2642         switch (phy->type) {
2643         case B43_PHYTYPE_B:
2644                 backup[0] = b43_radio_read16(dev, 0x007A);
2645                 backup[1] = b43_radio_read16(dev, 0x0052);
2646                 backup[2] = b43_radio_read16(dev, 0x0043);
2647                 backup[3] = b43_phy_read(dev, 0x0030);
2648                 backup[4] = b43_phy_read(dev, 0x0026);
2649                 backup[5] = b43_phy_read(dev, 0x0015);
2650                 backup[6] = b43_phy_read(dev, 0x002A);
2651                 backup[7] = b43_phy_read(dev, 0x0020);
2652                 backup[8] = b43_phy_read(dev, 0x005A);
2653                 backup[9] = b43_phy_read(dev, 0x0059);
2654                 backup[10] = b43_phy_read(dev, 0x0058);
2655                 backup[11] = b43_read16(dev, 0x03E2);
2656                 backup[12] = b43_read16(dev, 0x03E6);
2657                 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2658
2659                 tmp = b43_radio_read16(dev, 0x007A);
2660                 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2661                 b43_radio_write16(dev, 0x007A, tmp);
2662                 b43_phy_write(dev, 0x0030, 0x00FF);
2663                 b43_write16(dev, 0x03EC, 0x7F7F);
2664                 b43_phy_write(dev, 0x0026, 0x0000);
2665                 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2666                 b43_phy_write(dev, 0x002A, 0x08A3);
2667                 b43_radio_write16(dev, 0x007A,
2668                                   b43_radio_read16(dev, 0x007A) | 0x0080);
2669
2670                 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2671                 b43_radio_write16(dev, 0x007A,
2672                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2673                 if (phy->rev >= 2) {
2674                         b43_write16(dev, 0x03E6, 0x0040);
2675                 } else if (phy->rev == 0) {
2676                         b43_write16(dev, 0x03E6, 0x0122);
2677                 } else {
2678                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2679                                     b43_read16(dev,
2680                                                B43_MMIO_CHANNEL_EXT) & 0x2000);
2681                 }
2682                 b43_phy_write(dev, 0x0020, 0x3F3F);
2683                 b43_phy_write(dev, 0x0015, 0xF330);
2684                 b43_radio_write16(dev, 0x005A, 0x0060);
2685                 b43_radio_write16(dev, 0x0043,
2686                                   b43_radio_read16(dev, 0x0043) & 0x00F0);
2687                 b43_phy_write(dev, 0x005A, 0x0480);
2688                 b43_phy_write(dev, 0x0059, 0x0810);
2689                 b43_phy_write(dev, 0x0058, 0x000D);
2690                 udelay(20);
2691
2692                 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2693                 b43_phy_write(dev, 0x0030, backup[3]);
2694                 b43_radio_write16(dev, 0x007A, backup[0]);
2695                 b43_write16(dev, 0x03E2, backup[11]);
2696                 b43_phy_write(dev, 0x0026, backup[4]);
2697                 b43_phy_write(dev, 0x0015, backup[5]);
2698                 b43_phy_write(dev, 0x002A, backup[6]);
2699                 b43_synth_pu_workaround(dev, phy->channel);
2700                 if (phy->rev != 0)
2701                         b43_write16(dev, 0x03F4, backup[13]);
2702
2703                 b43_phy_write(dev, 0x0020, backup[7]);
2704                 b43_phy_write(dev, 0x005A, backup[8]);
2705                 b43_phy_write(dev, 0x0059, backup[9]);
2706                 b43_phy_write(dev, 0x0058, backup[10]);
2707                 b43_radio_write16(dev, 0x0052, backup[1]);
2708                 b43_radio_write16(dev, 0x0043, backup[2]);
2709
2710                 if (nrssi0 == nrssi1)
2711                         phy->nrssislope = 0x00010000;
2712                 else
2713                         phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2714
2715                 if (nrssi0 <= -4) {
2716                         phy->nrssi[0] = nrssi0;
2717                         phy->nrssi[1] = nrssi1;
2718                 }
2719                 break;
2720         case B43_PHYTYPE_G:
2721                 if (phy->radio_rev >= 9)
2722                         return;
2723                 if (phy->radio_rev == 8)
2724                         b43_calc_nrssi_offset(dev);
2725
2726                 b43_phy_write(dev, B43_PHY_G_CRS,
2727                               b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2728                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2729                 backup[7] = b43_read16(dev, 0x03E2);
2730                 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2731                 backup[0] = b43_radio_read16(dev, 0x007A);
2732                 backup[1] = b43_radio_read16(dev, 0x0052);
2733                 backup[2] = b43_radio_read16(dev, 0x0043);
2734                 backup[3] = b43_phy_read(dev, 0x0015);
2735                 backup[4] = b43_phy_read(dev, 0x005A);
2736                 backup[5] = b43_phy_read(dev, 0x0059);
2737                 backup[6] = b43_phy_read(dev, 0x0058);
2738                 backup[8] = b43_read16(dev, 0x03E6);
2739                 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2740                 if (phy->rev >= 3) {
2741                         backup[10] = b43_phy_read(dev, 0x002E);
2742                         backup[11] = b43_phy_read(dev, 0x002F);
2743                         backup[12] = b43_phy_read(dev, 0x080F);
2744                         backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2745                         backup[14] = b43_phy_read(dev, 0x0801);
2746                         backup[15] = b43_phy_read(dev, 0x0060);
2747                         backup[16] = b43_phy_read(dev, 0x0014);
2748                         backup[17] = b43_phy_read(dev, 0x0478);
2749                         b43_phy_write(dev, 0x002E, 0);
2750                         b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2751                         switch (phy->rev) {
2752                         case 4:
2753                         case 6:
2754                         case 7:
2755                                 b43_phy_write(dev, 0x0478,
2756                                               b43_phy_read(dev, 0x0478)
2757                                               | 0x0100);
2758                                 b43_phy_write(dev, 0x0801,
2759                                               b43_phy_read(dev, 0x0801)
2760                                               | 0x0040);
2761                                 break;
2762                         case 3:
2763                         case 5:
2764                                 b43_phy_write(dev, 0x0801,
2765                                               b43_phy_read(dev, 0x0801)
2766                                               & 0xFFBF);
2767                                 break;
2768                         }
2769                         b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2770                                       | 0x0040);
2771                         b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2772                                       | 0x0200);
2773                 }
2774                 b43_radio_write16(dev, 0x007A,
2775                                   b43_radio_read16(dev, 0x007A) | 0x0070);
2776                 b43_set_all_gains(dev, 0, 8, 0);
2777                 b43_radio_write16(dev, 0x007A,
2778                                   b43_radio_read16(dev, 0x007A) & 0x00F7);
2779                 if (phy->rev >= 2) {
2780                         b43_phy_write(dev, 0x0811,
2781                                       (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2782                                       0x0030);
2783                         b43_phy_write(dev, 0x0812,
2784                                       (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2785                                       0x0010);
2786                 }
2787                 b43_radio_write16(dev, 0x007A,
2788                                   b43_radio_read16(dev, 0x007A) | 0x0080);
2789                 udelay(20);
2790
2791                 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2792                 if (nrssi0 >= 0x0020)
2793                         nrssi0 -= 0x0040;
2794
2795                 b43_radio_write16(dev, 0x007A,
2796                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2797                 if (phy->rev >= 2) {
2798                         b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
2799                                                     & 0xFF9F) | 0x0040);
2800                 }
2801
2802                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2803                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2804                             | 0x2000);
2805                 b43_radio_write16(dev, 0x007A,
2806                                   b43_radio_read16(dev, 0x007A) | 0x000F);
2807                 b43_phy_write(dev, 0x0015, 0xF330);
2808                 if (phy->rev >= 2) {
2809                         b43_phy_write(dev, 0x0812,
2810                                       (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2811                                       0x0020);
2812                         b43_phy_write(dev, 0x0811,
2813                                       (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2814                                       0x0020);
2815                 }
2816
2817                 b43_set_all_gains(dev, 3, 0, 1);
2818                 if (phy->radio_rev == 8) {
2819                         b43_radio_write16(dev, 0x0043, 0x001F);
2820                 } else {
2821                         tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
2822                         b43_radio_write16(dev, 0x0052, tmp | 0x0060);
2823                         tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
2824                         b43_radio_write16(dev, 0x0043, tmp | 0x0009);
2825                 }
2826                 b43_phy_write(dev, 0x005A, 0x0480);
2827                 b43_phy_write(dev, 0x0059, 0x0810);
2828                 b43_phy_write(dev, 0x0058, 0x000D);
2829                 udelay(20);
2830                 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2831                 if (nrssi1 >= 0x0020)
2832                         nrssi1 -= 0x0040;
2833                 if (nrssi0 == nrssi1)
2834                         phy->nrssislope = 0x00010000;
2835                 else
2836                         phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2837                 if (nrssi0 >= -4) {
2838                         phy->nrssi[0] = nrssi1;
2839                         phy->nrssi[1] = nrssi0;
2840                 }
2841                 if (phy->rev >= 3) {
2842                         b43_phy_write(dev, 0x002E, backup[10]);
2843                         b43_phy_write(dev, 0x002F, backup[11]);
2844                         b43_phy_write(dev, 0x080F, backup[12]);
2845                         b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
2846                 }
2847                 if (phy->rev >= 2) {
2848                         b43_phy_write(dev, 0x0812,
2849                                       b43_phy_read(dev, 0x0812) & 0xFFCF);
2850                         b43_phy_write(dev, 0x0811,
2851                                       b43_phy_read(dev, 0x0811) & 0xFFCF);
2852                 }
2853
2854                 b43_radio_write16(dev, 0x007A, backup[0]);
2855                 b43_radio_write16(dev, 0x0052, backup[1]);
2856                 b43_radio_write16(dev, 0x0043, backup[2]);
2857                 b43_write16(dev, 0x03E2, backup[7]);
2858                 b43_write16(dev, 0x03E6, backup[8]);
2859                 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
2860                 b43_phy_write(dev, 0x0015, backup[3]);
2861                 b43_phy_write(dev, 0x005A, backup[4]);
2862                 b43_phy_write(dev, 0x0059, backup[5]);
2863                 b43_phy_write(dev, 0x0058, backup[6]);
2864                 b43_synth_pu_workaround(dev, phy->channel);
2865                 b43_phy_write(dev, 0x0802,
2866                               b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
2867                 b43_set_original_gains(dev);
2868                 b43_phy_write(dev, B43_PHY_G_CRS,
2869                               b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2870                 if (phy->rev >= 3) {
2871                         b43_phy_write(dev, 0x0801, backup[14]);
2872                         b43_phy_write(dev, 0x0060, backup[15]);
2873                         b43_phy_write(dev, 0x0014, backup[16]);
2874                         b43_phy_write(dev, 0x0478, backup[17]);
2875                 }
2876                 b43_nrssi_mem_update(dev);
2877                 b43_calc_nrssi_threshold(dev);
2878                 break;
2879         default:
2880                 B43_WARN_ON(1);
2881         }
2882 }
2883
2884 void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2885 {
2886         struct b43_phy *phy = &dev->phy;
2887         s32 threshold;
2888         s32 a, b;
2889         s16 tmp16;
2890         u16 tmp_u16;
2891
2892         switch (phy->type) {
2893         case B43_PHYTYPE_B:{
2894                         if (phy->radio_ver != 0x2050)
2895                                 return;
2896                         if (!
2897                             (dev->dev->bus->sprom.
2898                              boardflags_lo & B43_BFL_RSSI))
2899                                 return;
2900
2901                         if (phy->radio_rev >= 6) {
2902                                 threshold =
2903                                     (phy->nrssi[1] - phy->nrssi[0]) * 32;
2904                                 threshold += 20 * (phy->nrssi[0] + 1);
2905                                 threshold /= 40;
2906                         } else
2907                                 threshold = phy->nrssi[1] - 5;
2908
2909                         threshold = limit_value(threshold, 0, 0x3E);
2910                         b43_phy_read(dev, 0x0020);      /* dummy read */
2911                         b43_phy_write(dev, 0x0020,
2912                                       (((u16) threshold) << 8) | 0x001C);
2913
2914                         if (phy->radio_rev >= 6) {
2915                                 b43_phy_write(dev, 0x0087, 0x0E0D);
2916                                 b43_phy_write(dev, 0x0086, 0x0C0B);
2917                                 b43_phy_write(dev, 0x0085, 0x0A09);
2918                                 b43_phy_write(dev, 0x0084, 0x0808);
2919                                 b43_phy_write(dev, 0x0083, 0x0808);
2920                                 b43_phy_write(dev, 0x0082, 0x0604);
2921                                 b43_phy_write(dev, 0x0081, 0x0302);
2922                                 b43_phy_write(dev, 0x0080, 0x0100);
2923                         }
2924                         break;
2925                 }
2926         case B43_PHYTYPE_G:
2927                 if (!phy->gmode ||
2928                     !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2929                         tmp16 = b43_nrssi_hw_read(dev, 0x20);
2930                         if (tmp16 >= 0x20)
2931                                 tmp16 -= 0x40;
2932                         if (tmp16 < 3) {
2933                                 b43_phy_write(dev, 0x048A,
2934                                               (b43_phy_read(dev, 0x048A)
2935                                                & 0xF000) | 0x09EB);
2936                         } else {
2937                                 b43_phy_write(dev, 0x048A,
2938                                               (b43_phy_read(dev, 0x048A)
2939                                                & 0xF000) | 0x0AED);
2940                         }
2941                 } else {
2942                         if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
2943                                 a = 0xE;
2944                                 b = 0xA;
2945                         } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
2946                                 a = 0x13;
2947                                 b = 0x12;
2948                         } else {
2949                                 a = 0xE;
2950                                 b = 0x11;
2951                         }
2952
2953                         a = a * (phy->nrssi[1] - phy->nrssi[0]);
2954                         a += (phy->nrssi[0] << 6);
2955                         if (a < 32)
2956                                 a += 31;
2957                         else
2958                                 a += 32;
2959                         a = a >> 6;
2960                         a = limit_value(a, -31, 31);
2961
2962                         b = b * (phy->nrssi[1] - phy->nrssi[0]);
2963                         b += (phy->nrssi[0] << 6);
2964                         if (b < 32)
2965                                 b += 31;
2966                         else
2967                                 b += 32;
2968                         b = b >> 6;
2969                         b = limit_value(b, -31, 31);
2970
2971                         tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
2972                         tmp_u16 |= ((u32) b & 0x0000003F);
2973                         tmp_u16 |= (((u32) a & 0x0000003F) << 6);
2974                         b43_phy_write(dev, 0x048A, tmp_u16);
2975                 }
2976                 break;
2977         default:
2978                 B43_WARN_ON(1);
2979         }
2980 }
2981
2982 /* Stack implementation to save/restore values from the
2983  * interference mitigation code.
2984  * It is save to restore values in random order.
2985  */
2986 static void _stack_save(u32 * _stackptr, size_t * stackidx,
2987                         u8 id, u16 offset, u16 value)
2988 {
2989         u32 *stackptr = &(_stackptr[*stackidx]);
2990
2991         B43_WARN_ON(offset & 0xF000);
2992         B43_WARN_ON(id & 0xF0);
2993         *stackptr = offset;
2994         *stackptr |= ((u32) id) << 12;
2995         *stackptr |= ((u32) value) << 16;
2996         (*stackidx)++;
2997         B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
2998 }
2999
3000 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
3001 {
3002         size_t i;
3003
3004         B43_WARN_ON(offset & 0xF000);
3005         B43_WARN_ON(id & 0xF0);
3006         for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
3007                 if ((*stackptr & 0x00000FFF) != offset)
3008                         continue;
3009                 if (((*stackptr & 0x0000F000) >> 12) != id)
3010                         continue;
3011                 return ((*stackptr & 0xFFFF0000) >> 16);
3012         }
3013         B43_WARN_ON(1);
3014
3015         return 0;
3016 }
3017
3018 #define phy_stacksave(offset)                                   \
3019         do {                                                    \
3020                 _stack_save(stack, &stackidx, 0x1, (offset),    \
3021                             b43_phy_read(dev, (offset)));       \
3022         } while (0)
3023 #define phy_stackrestore(offset)                                \
3024         do {                                                    \
3025                 b43_phy_write(dev, (offset),            \
3026                                   _stack_restore(stack, 0x1,    \
3027                                                  (offset)));    \
3028         } while (0)
3029 #define radio_stacksave(offset)                                         \
3030         do {                                                            \
3031                 _stack_save(stack, &stackidx, 0x2, (offset),            \
3032                             b43_radio_read16(dev, (offset)));   \
3033         } while (0)
3034 #define radio_stackrestore(offset)                                      \
3035         do {                                                            \
3036                 b43_radio_write16(dev, (offset),                        \
3037                                       _stack_restore(stack, 0x2,        \
3038                                                      (offset)));        \
3039         } while (0)
3040 #define ofdmtab_stacksave(table, offset)                        \
3041         do {                                                    \
3042                 _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
3043                             b43_ofdmtab_read16(dev, (table), (offset)));        \
3044         } while (0)
3045 #define ofdmtab_stackrestore(table, offset)                     \
3046         do {                                                    \
3047                 b43_ofdmtab_write16(dev, (table),       (offset),       \
3048                                   _stack_restore(stack, 0x3,    \
3049                                                  (offset)|(table)));    \
3050         } while (0)
3051
3052 static void
3053 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
3054 {
3055         struct b43_phy *phy = &dev->phy;
3056         u16 tmp, flipped;
3057         size_t stackidx = 0;
3058         u32 *stack = phy->interfstack;
3059
3060         switch (mode) {
3061         case B43_INTERFMODE_NONWLAN:
3062                 if (phy->rev != 1) {
3063                         b43_phy_write(dev, 0x042B,
3064                                       b43_phy_read(dev, 0x042B) | 0x0800);
3065                         b43_phy_write(dev, B43_PHY_G_CRS,
3066                                       b43_phy_read(dev,
3067                                                    B43_PHY_G_CRS) & ~0x4000);
3068                         break;
3069                 }
3070                 radio_stacksave(0x0078);
3071                 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3072                 flipped = flip_4bit(tmp);
3073                 if (flipped < 10 && flipped >= 8)
3074                         flipped = 7;
3075                 else if (flipped >= 10)
3076                         flipped -= 3;
3077                 flipped = flip_4bit(flipped);
3078                 flipped = (flipped << 1) | 0x0020;
3079                 b43_radio_write16(dev, 0x0078, flipped);
3080
3081                 b43_calc_nrssi_threshold(dev);
3082
3083                 phy_stacksave(0x0406);
3084                 b43_phy_write(dev, 0x0406, 0x7E28);
3085
3086                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
3087                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3088                               b43_phy_read(dev,
3089                                            B43_PHY_RADIO_BITFIELD) | 0x1000);
3090
3091                 phy_stacksave(0x04A0);
3092                 b43_phy_write(dev, 0x04A0,
3093                               (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3094                 phy_stacksave(0x04A1);
3095                 b43_phy_write(dev, 0x04A1,
3096                               (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3097                 phy_stacksave(0x04A2);
3098                 b43_phy_write(dev, 0x04A2,
3099                               (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3100                 phy_stacksave(0x04A8);
3101                 b43_phy_write(dev, 0x04A8,
3102                               (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3103                 phy_stacksave(0x04AB);
3104                 b43_phy_write(dev, 0x04AB,
3105                               (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3106
3107                 phy_stacksave(0x04A7);
3108                 b43_phy_write(dev, 0x04A7, 0x0002);
3109                 phy_stacksave(0x04A3);
3110                 b43_phy_write(dev, 0x04A3, 0x287A);
3111                 phy_stacksave(0x04A9);
3112                 b43_phy_write(dev, 0x04A9, 0x2027);
3113                 phy_stacksave(0x0493);
3114                 b43_phy_write(dev, 0x0493, 0x32F5);
3115                 phy_stacksave(0x04AA);
3116                 b43_phy_write(dev, 0x04AA, 0x2027);
3117                 phy_stacksave(0x04AC);
3118                 b43_phy_write(dev, 0x04AC, 0x32F5);
3119                 break;
3120         case B43_INTERFMODE_MANUALWLAN:
3121                 if (b43_phy_read(dev, 0x0033) & 0x0800)
3122                         break;
3123
3124                 phy->aci_enable = 1;
3125
3126                 phy_stacksave(B43_PHY_RADIO_BITFIELD);
3127                 phy_stacksave(B43_PHY_G_CRS);
3128                 if (phy->rev < 2) {
3129                         phy_stacksave(0x0406);
3130                 } else {
3131                         phy_stacksave(0x04C0);
3132                         phy_stacksave(0x04C1);
3133                 }
3134                 phy_stacksave(0x0033);
3135                 phy_stacksave(0x04A7);
3136                 phy_stacksave(0x04A3);
3137                 phy_stacksave(0x04A9);
3138                 phy_stacksave(0x04AA);
3139                 phy_stacksave(0x04AC);
3140                 phy_stacksave(0x0493);
3141                 phy_stacksave(0x04A1);
3142                 phy_stacksave(0x04A0);
3143                 phy_stacksave(0x04A2);
3144                 phy_stacksave(0x048A);
3145                 phy_stacksave(0x04A8);
3146                 phy_stacksave(0x04AB);
3147                 if (phy->rev == 2) {
3148                         phy_stacksave(0x04AD);
3149                         phy_stacksave(0x04AE);
3150                 } else if (phy->rev >= 3) {
3151                         phy_stacksave(0x04AD);
3152                         phy_stacksave(0x0415);
3153                         phy_stacksave(0x0416);
3154                         phy_stacksave(0x0417);
3155                         ofdmtab_stacksave(0x1A00, 0x2);
3156                         ofdmtab_stacksave(0x1A00, 0x3);
3157                 }
3158                 phy_stacksave(0x042B);
3159                 phy_stacksave(0x048C);
3160
3161                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3162                               b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3163                               & ~0x1000);
3164                 b43_phy_write(dev, B43_PHY_G_CRS,
3165                               (b43_phy_read(dev, B43_PHY_G_CRS)
3166                                & 0xFFFC) | 0x0002);
3167
3168                 b43_phy_write(dev, 0x0033, 0x0800);
3169                 b43_phy_write(dev, 0x04A3, 0x2027);
3170                 b43_phy_write(dev, 0x04A9, 0x1CA8);
3171                 b43_phy_write(dev, 0x0493, 0x287A);
3172                 b43_phy_write(dev, 0x04AA, 0x1CA8);
3173                 b43_phy_write(dev, 0x04AC, 0x287A);
3174
3175                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3176                                             & 0xFFC0) | 0x001A);
3177                 b43_phy_write(dev, 0x04A7, 0x000D);
3178
3179                 if (phy->rev < 2) {
3180                         b43_phy_write(dev, 0x0406, 0xFF0D);
3181                 } else if (phy->rev == 2) {
3182                         b43_phy_write(dev, 0x04C0, 0xFFFF);
3183                         b43_phy_write(dev, 0x04C1, 0x00A9);
3184                 } else {
3185                         b43_phy_write(dev, 0x04C0, 0x00C1);
3186                         b43_phy_write(dev, 0x04C1, 0x0059);
3187                 }
3188
3189                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3190                                             & 0xC0FF) | 0x1800);
3191                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3192                                             & 0xFFC0) | 0x0015);
3193                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3194                                             & 0xCFFF) | 0x1000);
3195                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3196                                             & 0xF0FF) | 0x0A00);
3197                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3198                                             & 0xCFFF) | 0x1000);
3199                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3200                                             & 0xF0FF) | 0x0800);
3201                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3202                                             & 0xFFCF) | 0x0010);
3203                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3204                                             & 0xFFF0) | 0x0005);
3205                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3206                                             & 0xFFCF) | 0x0010);
3207                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3208                                             & 0xFFF0) | 0x0006);
3209                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3210                                             & 0xF0FF) | 0x0800);
3211                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3212                                             & 0xF0FF) | 0x0500);
3213                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3214                                             & 0xFFF0) | 0x000B);
3215
3216                 if (phy->rev >= 3) {
3217                         b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3218                                       & ~0x8000);
3219                         b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3220                                                     & 0x8000) | 0x36D8);
3221                         b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3222                                                     & 0x8000) | 0x36D8);
3223                         b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3224                                                     & 0xFE00) | 0x016D);
3225                 } else {
3226                         b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3227                                       | 0x1000);
3228                         b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3229                                                     & 0x9FFF) | 0x2000);
3230                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3231                 }
3232                 if (phy->rev >= 2) {
3233                         b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3234                                       | 0x0800);
3235                 }
3236                 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3237                                             & 0xF0FF) | 0x0200);
3238                 if (phy->rev == 2) {
3239                         b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3240                                                     & 0xFF00) | 0x007F);
3241                         b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3242                                                     & 0x00FF) | 0x1300);
3243                 } else if (phy->rev >= 6) {
3244                         b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3245                         b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3246                         b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3247                                       & 0x00FF);
3248                 }
3249                 b43_calc_nrssi_slope(dev);
3250                 break;
3251         default:
3252                 B43_WARN_ON(1);
3253         }
3254 }
3255
3256 static void
3257 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3258 {
3259         struct b43_phy *phy = &dev->phy;
3260         u32 *stack = phy->interfstack;
3261
3262         switch (mode) {
3263         case B43_INTERFMODE_NONWLAN:
3264                 if (phy->rev != 1) {
3265                         b43_phy_write(dev, 0x042B,
3266                                       b43_phy_read(dev, 0x042B) & ~0x0800);
3267                         b43_phy_write(dev, B43_PHY_G_CRS,
3268                                       b43_phy_read(dev,
3269                                                    B43_PHY_G_CRS) | 0x4000);
3270                         break;
3271                 }
3272                 radio_stackrestore(0x0078);
3273                 b43_calc_nrssi_threshold(dev);
3274                 phy_stackrestore(0x0406);
3275                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3276                 if (!dev->bad_frames_preempt) {
3277                         b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3278                                       b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3279                                       & ~(1 << 11));
3280                 }
3281                 b43_phy_write(dev, B43_PHY_G_CRS,
3282                               b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3283                 phy_stackrestore(0x04A0);
3284                 phy_stackrestore(0x04A1);
3285                 phy_stackrestore(0x04A2);
3286                 phy_stackrestore(0x04A8);
3287                 phy_stackrestore(0x04AB);
3288                 phy_stackrestore(0x04A7);
3289                 phy_stackrestore(0x04A3);
3290                 phy_stackrestore(0x04A9);
3291                 phy_stackrestore(0x0493);
3292                 phy_stackrestore(0x04AA);
3293                 phy_stackrestore(0x04AC);
3294                 break;
3295         case B43_INTERFMODE_MANUALWLAN:
3296                 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3297                         break;
3298
3299                 phy->aci_enable = 0;
3300
3301                 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3302                 phy_stackrestore(B43_PHY_G_CRS);
3303                 phy_stackrestore(0x0033);
3304                 phy_stackrestore(0x04A3);
3305                 phy_stackrestore(0x04A9);
3306                 phy_stackrestore(0x0493);
3307                 phy_stackrestore(0x04AA);
3308                 phy_stackrestore(0x04AC);
3309                 phy_stackrestore(0x04A0);
3310                 phy_stackrestore(0x04A7);
3311                 if (phy->rev >= 2) {
3312                         phy_stackrestore(0x04C0);
3313                         phy_stackrestore(0x04C1);
3314                 } else
3315                         phy_stackrestore(0x0406);
3316                 phy_stackrestore(0x04A1);
3317                 phy_stackrestore(0x04AB);
3318                 phy_stackrestore(0x04A8);
3319                 if (phy->rev == 2) {
3320                         phy_stackrestore(0x04AD);
3321                         phy_stackrestore(0x04AE);
3322                 } else if (phy->rev >= 3) {
3323                         phy_stackrestore(0x04AD);
3324                         phy_stackrestore(0x0415);
3325                         phy_stackrestore(0x0416);
3326                         phy_stackrestore(0x0417);
3327                         ofdmtab_stackrestore(0x1A00, 0x2);
3328                         ofdmtab_stackrestore(0x1A00, 0x3);
3329                 }
3330                 phy_stackrestore(0x04A2);
3331                 phy_stackrestore(0x048A);
3332                 phy_stackrestore(0x042B);
3333                 phy_stackrestore(0x048C);
3334                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3335                 b43_calc_nrssi_slope(dev);
3336                 break;
3337         default:
3338                 B43_WARN_ON(1);
3339         }
3340 }
3341
3342 #undef phy_stacksave
3343 #undef phy_stackrestore
3344 #undef radio_stacksave
3345 #undef radio_stackrestore
3346 #undef ofdmtab_stacksave
3347 #undef ofdmtab_stackrestore
3348
3349 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3350 {
3351         struct b43_phy *phy = &dev->phy;
3352         int currentmode;
3353
3354         if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3355                 return -ENODEV;
3356
3357         phy->aci_wlan_automatic = 0;
3358         switch (mode) {
3359         case B43_INTERFMODE_AUTOWLAN:
3360                 phy->aci_wlan_automatic = 1;
3361                 if (phy->aci_enable)
3362                         mode = B43_INTERFMODE_MANUALWLAN;
3363                 else
3364                         mode = B43_INTERFMODE_NONE;
3365                 break;
3366         case B43_INTERFMODE_NONE:
3367         case B43_INTERFMODE_NONWLAN:
3368         case B43_INTERFMODE_MANUALWLAN:
3369                 break;
3370         default:
3371                 return -EINVAL;
3372         }
3373
3374         currentmode = phy->interfmode;
3375         if (currentmode == mode)
3376                 return 0;
3377         if (currentmode != B43_INTERFMODE_NONE)
3378                 b43_radio_interference_mitigation_disable(dev, currentmode);
3379
3380         if (mode == B43_INTERFMODE_NONE) {
3381                 phy->aci_enable = 0;
3382                 phy->aci_hw_rssi = 0;
3383         } else
3384                 b43_radio_interference_mitigation_enable(dev, mode);
3385         phy->interfmode = mode;
3386
3387         return 0;
3388 }
3389
3390 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3391 {
3392         u16 reg, index, ret;
3393
3394         static const u8 rcc_table[] = {
3395                 0x02, 0x03, 0x01, 0x0F,
3396                 0x06, 0x07, 0x05, 0x0F,
3397                 0x0A, 0x0B, 0x09, 0x0F,
3398                 0x0E, 0x0F, 0x0D, 0x0F,
3399         };
3400
3401         reg = b43_radio_read16(dev, 0x60);
3402         index = (reg & 0x001E) >> 1;
3403         ret = rcc_table[index] << 1;
3404         ret |= (reg & 0x0001);
3405         ret |= 0x0020;
3406
3407         return ret;
3408 }
3409
3410 #define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
3411 static u16 radio2050_rfover_val(struct b43_wldev *dev,
3412                                 u16 phy_register, unsigned int lpd)
3413 {
3414         struct b43_phy *phy = &dev->phy;
3415         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3416
3417         if (!phy->gmode)
3418                 return 0;
3419
3420         if (has_loopback_gain(phy)) {
3421                 int max_lb_gain = phy->max_lb_gain;
3422                 u16 extlna;
3423                 u16 i;
3424
3425                 if (phy->radio_rev == 8)
3426                         max_lb_gain += 0x3E;
3427                 else
3428                         max_lb_gain += 0x26;
3429                 if (max_lb_gain >= 0x46) {
3430                         extlna = 0x3000;
3431                         max_lb_gain -= 0x46;
3432                 } else if (max_lb_gain >= 0x3A) {
3433                         extlna = 0x1000;
3434                         max_lb_gain -= 0x3A;
3435                 } else if (max_lb_gain >= 0x2E) {
3436                         extlna = 0x2000;
3437                         max_lb_gain -= 0x2E;
3438                 } else {
3439                         extlna = 0;
3440                         max_lb_gain -= 0x10;
3441                 }
3442
3443                 for (i = 0; i < 16; i++) {
3444                         max_lb_gain -= (i * 6);
3445                         if (max_lb_gain < 6)
3446                                 break;
3447                 }
3448
3449                 if ((phy->rev < 7) ||
3450                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
3451                         if (phy_register == B43_PHY_RFOVER) {
3452                                 return 0x1B3;
3453                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3454                                 extlna |= (i << 8);
3455                                 switch (lpd) {
3456                                 case LPD(0, 1, 1):
3457                                         return 0x0F92;
3458                                 case LPD(0, 0, 1):
3459                                 case LPD(1, 0, 1):
3460                                         return (0x0092 | extlna);
3461                                 case LPD(1, 0, 0):
3462                                         return (0x0093 | extlna);
3463                                 }
3464                                 B43_WARN_ON(1);
3465                         }
3466                         B43_WARN_ON(1);
3467                 } else {
3468                         if (phy_register == B43_PHY_RFOVER) {
3469                                 return 0x9B3;
3470                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3471                                 if (extlna)
3472                                         extlna |= 0x8000;
3473                                 extlna |= (i << 8);
3474                                 switch (lpd) {
3475                                 case LPD(0, 1, 1):
3476                                         return 0x8F92;
3477                                 case LPD(0, 0, 1):
3478                                         return (0x8092 | extlna);
3479                                 case LPD(1, 0, 1):
3480                                         return (0x2092 | extlna);
3481                                 case LPD(1, 0, 0):
3482                                         return (0x2093 | extlna);
3483                                 }
3484                                 B43_WARN_ON(1);
3485                         }
3486                         B43_WARN_ON(1);
3487                 }
3488         } else {
3489                 if ((phy->rev < 7) ||
3490                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
3491                         if (phy_register == B43_PHY_RFOVER) {
3492                                 return 0x1B3;
3493                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3494                                 switch (lpd) {
3495                                 case LPD(0, 1, 1):
3496                                         return 0x0FB2;
3497                                 case LPD(0, 0, 1):
3498                                         return 0x00B2;
3499                                 case LPD(1, 0, 1):
3500                                         return 0x30B2;
3501                                 case LPD(1, 0, 0):
3502                                         return 0x30B3;
3503                                 }
3504                                 B43_WARN_ON(1);
3505                         }
3506                         B43_WARN_ON(1);
3507                 } else {
3508                         if (phy_register == B43_PHY_RFOVER) {
3509                                 return 0x9B3;
3510                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3511                                 switch (lpd) {
3512                                 case LPD(0, 1, 1):
3513                                         return 0x8FB2;
3514                                 case LPD(0, 0, 1):
3515                                         return 0x80B2;
3516                                 case LPD(1, 0, 1):
3517                                         return 0x20B2;
3518                                 case LPD(1, 0, 0):
3519                                         return 0x20B3;
3520                                 }
3521                                 B43_WARN_ON(1);
3522                         }
3523                         B43_WARN_ON(1);
3524                 }
3525         }
3526         return 0;
3527 }
3528
3529 struct init2050_saved_values {
3530         /* Core registers */
3531         u16 reg_3EC;
3532         u16 reg_3E6;
3533         u16 reg_3F4;
3534         /* Radio registers */
3535         u16 radio_43;
3536         u16 radio_51;
3537         u16 radio_52;
3538         /* PHY registers */
3539         u16 phy_pgactl;
3540         u16 phy_cck_5A;
3541         u16 phy_cck_59;
3542         u16 phy_cck_58;
3543         u16 phy_cck_30;
3544         u16 phy_rfover;
3545         u16 phy_rfoverval;
3546         u16 phy_analogover;
3547         u16 phy_analogoverval;
3548         u16 phy_crs0;
3549         u16 phy_classctl;
3550         u16 phy_lo_mask;
3551         u16 phy_lo_ctl;
3552         u16 phy_syncctl;
3553 };
3554
3555 u16 b43_radio_init2050(struct b43_wldev *dev)
3556 {
3557         struct b43_phy *phy = &dev->phy;
3558         struct init2050_saved_values sav;
3559         u16 rcc;
3560         u16 radio78;
3561         u16 ret;
3562         u16 i, j;
3563         u32 tmp1 = 0, tmp2 = 0;
3564
3565         memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
3566
3567         sav.radio_43 = b43_radio_read16(dev, 0x43);
3568         sav.radio_51 = b43_radio_read16(dev, 0x51);
3569         sav.radio_52 = b43_radio_read16(dev, 0x52);
3570         sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3571         sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
3572         sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
3573         sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
3574
3575         if (phy->type == B43_PHYTYPE_B) {
3576                 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
3577                 sav.reg_3EC = b43_read16(dev, 0x3EC);
3578
3579                 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
3580                 b43_write16(dev, 0x3EC, 0x3F3F);
3581         } else if (phy->gmode || phy->rev >= 2) {
3582                 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3583                 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3584                 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3585                 sav.phy_analogoverval =
3586                     b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3587                 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3588                 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3589
3590                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3591                               b43_phy_read(dev, B43_PHY_ANALOGOVER)
3592                               | 0x0003);
3593                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3594                               b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3595                               & 0xFFFC);
3596                 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3597                               & 0x7FFF);
3598                 b43_phy_write(dev, B43_PHY_CLASSCTL,
3599                               b43_phy_read(dev, B43_PHY_CLASSCTL)
3600                               & 0xFFFC);
3601                 if (has_loopback_gain(phy)) {
3602                         sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3603                         sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3604
3605                         if (phy->rev >= 3)
3606                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3607                         else
3608                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3609                         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3610                 }
3611
3612                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3613                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3614                                                    LPD(0, 1, 1)));
3615                 b43_phy_write(dev, B43_PHY_RFOVER,
3616                               radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3617         }
3618         b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3619
3620         sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3621         b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3622                       & 0xFF7F);
3623         sav.reg_3E6 = b43_read16(dev, 0x3E6);
3624         sav.reg_3F4 = b43_read16(dev, 0x3F4);
3625
3626         if (phy->analog == 0) {
3627                 b43_write16(dev, 0x03E6, 0x0122);
3628         } else {
3629                 if (phy->analog >= 2) {
3630                         b43_phy_write(dev, B43_PHY_CCK(0x03),
3631                                       (b43_phy_read(dev, B43_PHY_CCK(0x03))
3632                                        & 0xFFBF) | 0x40);
3633                 }
3634                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3635                             (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3636         }
3637
3638         rcc = b43_radio_core_calibration_value(dev);
3639
3640         if (phy->type == B43_PHYTYPE_B)
3641                 b43_radio_write16(dev, 0x78, 0x26);
3642         if (phy->gmode || phy->rev >= 2) {
3643                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3644                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3645                                                    LPD(0, 1, 1)));
3646         }
3647         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3648         b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
3649         if (phy->gmode || phy->rev >= 2) {
3650                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3651                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3652                                                    LPD(0, 0, 1)));
3653         }
3654         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3655         b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3656                           | 0x0004);
3657         if (phy->radio_rev == 8) {
3658                 b43_radio_write16(dev, 0x43, 0x1F);
3659         } else {
3660                 b43_radio_write16(dev, 0x52, 0);
3661                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3662                                               & 0xFFF0) | 0x0009);
3663         }
3664         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3665
3666         for (i = 0; i < 16; i++) {
3667                 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
3668                 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3669                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3670                 if (phy->gmode || phy->rev >= 2) {
3671                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3672                                       radio2050_rfover_val(dev,
3673                                                            B43_PHY_RFOVERVAL,
3674                                                            LPD(1, 0, 1)));
3675                 }
3676                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3677                 udelay(10);
3678                 if (phy->gmode || phy->rev >= 2) {
3679                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3680                                       radio2050_rfover_val(dev,
3681                                                            B43_PHY_RFOVERVAL,
3682                                                            LPD(1, 0, 1)));
3683                 }
3684                 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3685                 udelay(10);
3686                 if (phy->gmode || phy->rev >= 2) {
3687                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3688                                       radio2050_rfover_val(dev,
3689                                                            B43_PHY_RFOVERVAL,
3690                                                            LPD(1, 0, 0)));
3691                 }
3692                 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3693                 udelay(20);
3694                 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3695                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3696                 if (phy->gmode || phy->rev >= 2) {
3697                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3698                                       radio2050_rfover_val(dev,
3699                                                            B43_PHY_RFOVERVAL,
3700                                                            LPD(1, 0, 1)));
3701                 }
3702                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3703         }
3704         udelay(10);
3705
3706         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3707         tmp1++;
3708         tmp1 >>= 9;
3709
3710         for (i = 0; i < 16; i++) {
3711                 radio78 = ((flip_4bit(i) << 1) | 0x20);
3712                 b43_radio_write16(dev, 0x78, radio78);
3713                 udelay(10);
3714                 for (j = 0; j < 16; j++) {
3715                         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
3716                         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3717                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3718                         if (phy->gmode || phy->rev >= 2) {
3719                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3720                                               radio2050_rfover_val(dev,
3721                                                                    B43_PHY_RFOVERVAL,
3722                                                                    LPD(1, 0,
3723                                                                        1)));
3724                         }
3725                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3726                         udelay(10);
3727                         if (phy->gmode || phy->rev >= 2) {
3728                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3729                                               radio2050_rfover_val(dev,
3730                                                                    B43_PHY_RFOVERVAL,
3731                                                                    LPD(1, 0,
3732                                                                        1)));
3733                         }
3734                         b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3735                         udelay(10);
3736                         if (phy->gmode || phy->rev >= 2) {
3737                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3738                                               radio2050_rfover_val(dev,
3739                                                                    B43_PHY_RFOVERVAL,
3740                                                                    LPD(1, 0,
3741                                                                        0)));
3742                         }
3743                         b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3744                         udelay(10);
3745                         tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3746                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3747                         if (phy->gmode || phy->rev >= 2) {
3748                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3749                                               radio2050_rfover_val(dev,
3750                                                                    B43_PHY_RFOVERVAL,
3751                                                                    LPD(1, 0,
3752                                                                        1)));
3753                         }
3754                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3755                 }
3756                 tmp2++;
3757                 tmp2 >>= 8;
3758                 if (tmp1 < tmp2)
3759                         break;
3760         }
3761
3762         /* Restore the registers */
3763         b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3764         b43_radio_write16(dev, 0x51, sav.radio_51);
3765         b43_radio_write16(dev, 0x52, sav.radio_52);
3766         b43_radio_write16(dev, 0x43, sav.radio_43);
3767         b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
3768         b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
3769         b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
3770         b43_write16(dev, 0x3E6, sav.reg_3E6);
3771         if (phy->analog != 0)
3772                 b43_write16(dev, 0x3F4, sav.reg_3F4);
3773         b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3774         b43_synth_pu_workaround(dev, phy->channel);
3775         if (phy->type == B43_PHYTYPE_B) {
3776                 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
3777                 b43_write16(dev, 0x3EC, sav.reg_3EC);
3778         } else if (phy->gmode) {
3779                 b43_write16(dev, B43_MMIO_PHY_RADIO,
3780                             b43_read16(dev, B43_MMIO_PHY_RADIO)
3781                             & 0x7FFF);
3782                 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
3783                 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
3784                 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
3785                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3786                               sav.phy_analogoverval);
3787                 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
3788                 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
3789                 if (has_loopback_gain(phy)) {
3790                         b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
3791                         b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
3792                 }
3793         }
3794         if (i > 15)
3795                 ret = radio78;
3796         else
3797                 ret = rcc;
3798
3799         return ret;
3800 }
3801
3802 void b43_radio_init2060(struct b43_wldev *dev)
3803 {
3804         int err;
3805
3806         b43_radio_write16(dev, 0x0004, 0x00C0);
3807         b43_radio_write16(dev, 0x0005, 0x0008);
3808         b43_radio_write16(dev, 0x0009, 0x0040);
3809         b43_radio_write16(dev, 0x0005, 0x00AA);
3810         b43_radio_write16(dev, 0x0032, 0x008F);
3811         b43_radio_write16(dev, 0x0006, 0x008F);
3812         b43_radio_write16(dev, 0x0034, 0x008F);
3813         b43_radio_write16(dev, 0x002C, 0x0007);
3814         b43_radio_write16(dev, 0x0082, 0x0080);
3815         b43_radio_write16(dev, 0x0080, 0x0000);
3816         b43_radio_write16(dev, 0x003F, 0x00DA);
3817         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3818         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
3819         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3820         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3821         msleep(1);              /* delay 400usec */
3822
3823         b43_radio_write16(dev, 0x0081,
3824                           (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
3825         msleep(1);              /* delay 400usec */
3826
3827         b43_radio_write16(dev, 0x0005,
3828                           (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
3829         b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
3830         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3831         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
3832         b43_radio_write16(dev, 0x0081,
3833                           (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
3834         b43_radio_write16(dev, 0x0005,
3835                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
3836         b43_phy_write(dev, 0x0063, 0xDDC6);
3837         b43_phy_write(dev, 0x0069, 0x07BE);
3838         b43_phy_write(dev, 0x006A, 0x0000);
3839
3840         err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
3841         B43_WARN_ON(err);
3842
3843         msleep(1);
3844 }
3845
3846 static inline u16 freq_r3A_value(u16 frequency)
3847 {
3848         u16 value;
3849
3850         if (frequency < 5091)
3851                 value = 0x0040;
3852         else if (frequency < 5321)
3853                 value = 0x0000;
3854         else if (frequency < 5806)
3855                 value = 0x0080;
3856         else
3857                 value = 0x0040;
3858
3859         return value;
3860 }
3861
3862 void b43_radio_set_tx_iq(struct b43_wldev *dev)
3863 {
3864         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
3865         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
3866         u16 tmp = b43_radio_read16(dev, 0x001E);
3867         int i, j;
3868
3869         for (i = 0; i < 5; i++) {
3870                 for (j = 0; j < 5; j++) {
3871                         if (tmp == (data_high[i] << 4 | data_low[j])) {
3872                                 b43_phy_write(dev, 0x0069,
3873                                               (i - j) << 8 | 0x00C0);
3874                                 return;
3875                         }
3876                 }
3877         }
3878 }
3879
3880 int b43_radio_selectchannel(struct b43_wldev *dev,
3881                             u8 channel, int synthetic_pu_workaround)
3882 {
3883         struct b43_phy *phy = &dev->phy;
3884         u16 r8, tmp;
3885         u16 freq;
3886         u16 channelcookie, savedcookie;
3887         int err = 0;
3888
3889         if (channel == 0xFF) {
3890                 switch (phy->type) {
3891                 case B43_PHYTYPE_A:
3892                         channel = B43_DEFAULT_CHANNEL_A;
3893                         break;
3894                 case B43_PHYTYPE_B:
3895                 case B43_PHYTYPE_G:
3896                         channel = B43_DEFAULT_CHANNEL_BG;
3897                         break;
3898                 case B43_PHYTYPE_N:
3899                         //FIXME check if we are on 2.4GHz or 5GHz and set a default channel.
3900                         channel = 1;
3901                         break;
3902                 default:
3903                         B43_WARN_ON(1);
3904                 }
3905         }
3906
3907         /* First we set the channel radio code to prevent the
3908          * firmware from sending ghost packets.
3909          */
3910         channelcookie = channel;
3911         if (0 /*FIXME on 5Ghz */)
3912                 channelcookie |= 0x100;
3913         //FIXME set 40Mhz flag if required
3914         savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
3915         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
3916
3917         switch (phy->type) {
3918         case B43_PHYTYPE_A:
3919                 if (channel > 200) {
3920                         err = -EINVAL;
3921                         goto out;
3922                 }
3923                 freq = channel2freq_a(channel);
3924
3925                 r8 = b43_radio_read16(dev, 0x0008);
3926                 b43_write16(dev, 0x03F0, freq);
3927                 b43_radio_write16(dev, 0x0008, r8);
3928
3929                 //TODO: write max channel TX power? to Radio 0x2D
3930                 tmp = b43_radio_read16(dev, 0x002E);
3931                 tmp &= 0x0080;
3932                 //TODO: OR tmp with the Power out estimation for this channel?
3933                 b43_radio_write16(dev, 0x002E, tmp);
3934
3935                 if (freq >= 4920 && freq <= 5500) {
3936                         /*
3937                          * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
3938                          *    = (freq * 0.025862069
3939                          */
3940                         r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
3941                 }
3942                 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
3943                 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
3944                 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
3945                 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
3946                                                 & 0x000F) | (r8 << 4));
3947                 b43_radio_write16(dev, 0x002A, (r8 << 4));
3948                 b43_radio_write16(dev, 0x002B, (r8 << 4));
3949                 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
3950                                                 & 0x00F0) | (r8 << 4));
3951                 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
3952                                                 & 0xFF0F) | 0x00B0);
3953                 b43_radio_write16(dev, 0x0035, 0x00AA);
3954                 b43_radio_write16(dev, 0x0036, 0x0085);
3955                 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
3956                                                 & 0xFF20) |
3957                                   freq_r3A_value(freq));
3958                 b43_radio_write16(dev, 0x003D,
3959                                   b43_radio_read16(dev, 0x003D) & 0x00FF);
3960                 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
3961                                                 & 0xFF7F) | 0x0080);
3962                 b43_radio_write16(dev, 0x0035,
3963                                   b43_radio_read16(dev, 0x0035) & 0xFFEF);
3964                 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
3965                                                 & 0xFFEF) | 0x0010);
3966                 b43_radio_set_tx_iq(dev);
3967                 //TODO: TSSI2dbm workaround
3968                 b43_phy_xmitpower(dev); //FIXME correct?
3969                 break;
3970         case B43_PHYTYPE_G:
3971                 if ((channel < 1) || (channel > 14)) {
3972                         err = -EINVAL;
3973                         goto out;
3974                 }
3975
3976                 if (synthetic_pu_workaround)
3977                         b43_synth_pu_workaround(dev, channel);
3978
3979                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
3980
3981                 if (channel == 14) {
3982                         if (dev->dev->bus->sprom.country_code ==
3983                             SSB_SPROM1CCODE_JAPAN)
3984                                 b43_hf_write(dev,
3985                                              b43_hf_read(dev) & ~B43_HF_ACPR);
3986                         else
3987                                 b43_hf_write(dev,
3988                                              b43_hf_read(dev) | B43_HF_ACPR);
3989                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3990                                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3991                                     | (1 << 11));
3992                 } else {
3993                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3994                                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3995                                     & 0xF7BF);
3996                 }
3997                 break;
3998         case B43_PHYTYPE_N:
3999                 err = b43_nphy_selectchannel(dev, channel);
4000                 if (err)
4001                         goto out;
4002                 break;
4003         default:
4004                 B43_WARN_ON(1);
4005         }
4006
4007         phy->channel = channel;
4008         /* Wait for the radio to tune to the channel and stabilize. */
4009         msleep(8);
4010 out:
4011         if (err) {
4012                 b43_shm_write16(dev, B43_SHM_SHARED,
4013                                 B43_SHM_SH_CHAN, savedcookie);
4014         }
4015         return err;
4016 }
4017
4018 void b43_radio_turn_on(struct b43_wldev *dev)
4019 {
4020         struct b43_phy *phy = &dev->phy;
4021         int err;
4022         u8 channel;
4023
4024         might_sleep();
4025
4026         if (phy->radio_on)
4027                 return;
4028
4029         switch (phy->type) {
4030         case B43_PHYTYPE_A:
4031                 b43_radio_write16(dev, 0x0004, 0x00C0);
4032                 b43_radio_write16(dev, 0x0005, 0x0008);
4033                 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
4034                 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
4035                 b43_radio_init2060(dev);
4036                 break;
4037         case B43_PHYTYPE_B:
4038         case B43_PHYTYPE_G:
4039                 b43_phy_write(dev, 0x0015, 0x8000);
4040                 b43_phy_write(dev, 0x0015, 0xCC00);
4041                 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
4042                 if (phy->radio_off_context.valid) {
4043                         /* Restore the RFover values. */
4044                         b43_phy_write(dev, B43_PHY_RFOVER,
4045                                       phy->radio_off_context.rfover);
4046                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
4047                                       phy->radio_off_context.rfoverval);
4048                         phy->radio_off_context.valid = 0;
4049                 }
4050                 channel = phy->channel;
4051                 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
4052                 err |= b43_radio_selectchannel(dev, channel, 0);
4053                 B43_WARN_ON(err);
4054                 break;
4055         case B43_PHYTYPE_N:
4056                 b43_nphy_radio_turn_on(dev);
4057                 break;
4058         default:
4059                 B43_WARN_ON(1);
4060         }
4061         phy->radio_on = 1;
4062 }
4063
4064 void b43_radio_turn_off(struct b43_wldev *dev, bool force)
4065 {
4066         struct b43_phy *phy = &dev->phy;
4067
4068         if (!phy->radio_on && !force)
4069                 return;
4070
4071         switch (phy->type) {
4072         case B43_PHYTYPE_N:
4073                 b43_nphy_radio_turn_off(dev);
4074                 break;
4075         case B43_PHYTYPE_A:
4076                 b43_radio_write16(dev, 0x0004, 0x00FF);
4077                 b43_radio_write16(dev, 0x0005, 0x00FB);
4078                 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
4079                 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
4080                 break;
4081         case B43_PHYTYPE_G: {
4082                 u16 rfover, rfoverval;
4083
4084                 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
4085                 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
4086                 if (!force) {
4087                         phy->radio_off_context.rfover = rfover;
4088                         phy->radio_off_context.rfoverval = rfoverval;
4089                         phy->radio_off_context.valid = 1;
4090                 }
4091                 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
4092                 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
4093                 break;
4094         }
4095         default:
4096                 B43_WARN_ON(1);
4097         }
4098         phy->radio_on = 0;
4099 }