drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/slab.h>
  42 #include <asm/div64.h>
  43
  44
  45 /* Required number of TX DMA slots per TX frame.
  46  * This currently is 2, because we put the header and the ieee80211 frame
  47  * into separate slots. */
  48 #define TX_SLOTS_PER_FRAME      2
  49
  50 static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr,
  51                            enum b43_addrtype addrtype)
  52 {
  53         u32 uninitialized_var(addr);
  54
  55         switch (addrtype) {
  56         case B43_DMA_ADDR_LOW:
  57                 addr = lower_32_bits(dmaaddr);
  58                 if (dma->translation_in_low) {
  59                         addr &= ~SSB_DMA_TRANSLATION_MASK;
  60                         addr |= dma->translation;
  61                 }
  62                 break;
  63         case B43_DMA_ADDR_HIGH:
  64                 addr = upper_32_bits(dmaaddr);
  65                 if (!dma->translation_in_low) {
  66                         addr &= ~SSB_DMA_TRANSLATION_MASK;
  67                         addr |= dma->translation;
  68                 }
  69                 break;
  70         case B43_DMA_ADDR_EXT:
  71                 if (dma->translation_in_low)
  72                         addr = lower_32_bits(dmaaddr);
  73                 else
  74                         addr = upper_32_bits(dmaaddr);
  75                 addr &= SSB_DMA_TRANSLATION_MASK;
  76                 addr >>= SSB_DMA_TRANSLATION_SHIFT;
  77                 break;
  78         }
  79
  80         return addr;
  81 }
  82
  83 /* 32bit DMA ops. */
  84 static
  85 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  86                                           int slot,
  87                                           struct b43_dmadesc_meta **meta)
  88 {
  89         struct b43_dmadesc32 *desc;
  90
  91         *meta = &(ring->meta[slot]);
  92         desc = ring->descbase;
  93         desc = &(desc[slot]);
  94
  95         return (struct b43_dmadesc_generic *)desc;
  96 }
  97
  98 static void op32_fill_descriptor(struct b43_dmaring *ring,
  99                                  struct b43_dmadesc_generic *desc,
 100                                  dma_addr_t dmaaddr, u16 bufsize,
 101                                  int start, int end, int irq)
 102 {
 103         struct b43_dmadesc32 *descbase = ring->descbase;
 104         int slot;
 105         u32 ctl;
 106         u32 addr;
 107         u32 addrext;
 108
 109         slot = (int)(&(desc->dma32) - descbase);
 110         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 111
 112         addr = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
 113         addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
 114
 115         ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
 116         if (slot == ring->nr_slots - 1)
 117                 ctl |= B43_DMA32_DCTL_DTABLEEND;
 118         if (start)
 119                 ctl |= B43_DMA32_DCTL_FRAMESTART;
 120         if (end)
 121                 ctl |= B43_DMA32_DCTL_FRAMEEND;
 122         if (irq)
 123                 ctl |= B43_DMA32_DCTL_IRQ;
 124         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
 125             & B43_DMA32_DCTL_ADDREXT_MASK;
 126
 127         desc->dma32.control = cpu_to_le32(ctl);
 128         desc->dma32.address = cpu_to_le32(addr);
 129 }
 130
 131 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
 132 {
 133         b43_dma_write(ring, B43_DMA32_TXINDEX,
 134                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 135 }
 136
 137 static void op32_tx_suspend(struct b43_dmaring *ring)
 138 {
 139         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 140                       | B43_DMA32_TXSUSPEND);
 141 }
 142
 143 static void op32_tx_resume(struct b43_dmaring *ring)
 144 {
 145         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 146                       & ~B43_DMA32_TXSUSPEND);
 147 }
 148
 149 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 150 {
 151         u32 val;
 152
 153         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 154         val &= B43_DMA32_RXDPTR;
 155
 156         return (val / sizeof(struct b43_dmadesc32));
 157 }
 158
 159 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 160 {
 161         b43_dma_write(ring, B43_DMA32_RXINDEX,
 162                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 163 }
 164
 165 static const struct b43_dma_ops dma32_ops = {
 166         .idx2desc = op32_idx2desc,
 167         .fill_descriptor = op32_fill_descriptor,
 168         .poke_tx = op32_poke_tx,
 169         .tx_suspend = op32_tx_suspend,
 170         .tx_resume = op32_tx_resume,
 171         .get_current_rxslot = op32_get_current_rxslot,
 172         .set_current_rxslot = op32_set_current_rxslot,
 173 };
 174
 175 /* 64bit DMA ops. */
 176 static
 177 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 178                                           int slot,
 179                                           struct b43_dmadesc_meta **meta)
 180 {
 181         struct b43_dmadesc64 *desc;
 182
 183         *meta = &(ring->meta[slot]);
 184         desc = ring->descbase;
 185         desc = &(desc[slot]);
 186
 187         return (struct b43_dmadesc_generic *)desc;
 188 }
 189
 190 static void op64_fill_descriptor(struct b43_dmaring *ring,
 191                                  struct b43_dmadesc_generic *desc,
 192                                  dma_addr_t dmaaddr, u16 bufsize,
 193                                  int start, int end, int irq)
 194 {
 195         struct b43_dmadesc64 *descbase = ring->descbase;
 196         int slot;
 197         u32 ctl0 = 0, ctl1 = 0;
 198         u32 addrlo, addrhi;
 199         u32 addrext;
 200
 201         slot = (int)(&(desc->dma64) - descbase);
 202         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 203
 204         addrlo = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
 205         addrhi = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_HIGH);
 206         addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
 207
 208         if (slot == ring->nr_slots - 1)
 209                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 210         if (start)
 211                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 212         if (end)
 213                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 214         if (irq)
 215                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 216         ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
 217         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 218             & B43_DMA64_DCTL1_ADDREXT_MASK;
 219
 220         desc->dma64.control0 = cpu_to_le32(ctl0);
 221         desc->dma64.control1 = cpu_to_le32(ctl1);
 222         desc->dma64.address_low = cpu_to_le32(addrlo);
 223         desc->dma64.address_high = cpu_to_le32(addrhi);
 224 }
 225
 226 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 227 {
 228         b43_dma_write(ring, B43_DMA64_TXINDEX,
 229                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 230 }
 231
 232 static void op64_tx_suspend(struct b43_dmaring *ring)
 233 {
 234         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 235                       | B43_DMA64_TXSUSPEND);
 236 }
 237
 238 static void op64_tx_resume(struct b43_dmaring *ring)
 239 {
 240         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 241                       & ~B43_DMA64_TXSUSPEND);
 242 }
 243
 244 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 245 {
 246         u32 val;
 247
 248         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 249         val &= B43_DMA64_RXSTATDPTR;
 250
 251         return (val / sizeof(struct b43_dmadesc64));
 252 }
 253
 254 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 255 {
 256         b43_dma_write(ring, B43_DMA64_RXINDEX,
 257                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 258 }
 259
 260 static const struct b43_dma_ops dma64_ops = {
 261         .idx2desc = op64_idx2desc,
 262         .fill_descriptor = op64_fill_descriptor,
 263         .poke_tx = op64_poke_tx,
 264         .tx_suspend = op64_tx_suspend,
 265         .tx_resume = op64_tx_resume,
 266         .get_current_rxslot = op64_get_current_rxslot,
 267         .set_current_rxslot = op64_set_current_rxslot,
 268 };
 269
 270 static inline int free_slots(struct b43_dmaring *ring)
 271 {
 272         return (ring->nr_slots - ring->used_slots);
 273 }
 274
 275 static inline int next_slot(struct b43_dmaring *ring, int slot)
 276 {
 277         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 278         if (slot == ring->nr_slots - 1)
 279                 return 0;
 280         return slot + 1;
 281 }
 282
 283 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 284 {
 285         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 286         if (slot == 0)
 287                 return ring->nr_slots - 1;
 288         return slot - 1;
 289 }
 290
 291 #ifdef CONFIG_B43_DEBUG
 292 static void update_max_used_slots(struct b43_dmaring *ring,
 293                                   int current_used_slots)
 294 {
 295         if (current_used_slots <= ring->max_used_slots)
 296                 return;
 297         ring->max_used_slots = current_used_slots;
 298         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 299                 b43dbg(ring->dev->wl,
 300                        "max_used_slots increased to %d on %s ring %d\n",
 301                        ring->max_used_slots,
 302                        ring->tx ? "TX" : "RX", ring->index);
 303         }
 304 }
 305 #else
 306 static inline
 307     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 308 {
 309 }
 310 #endif /* DEBUG */
 311
 312 /* Request a slot for usage. */
 313 static inline int request_slot(struct b43_dmaring *ring)
 314 {
 315         int slot;
 316
 317         B43_WARN_ON(!ring->tx);
 318         B43_WARN_ON(ring->stopped);
 319         B43_WARN_ON(free_slots(ring) == 0);
 320
 321         slot = next_slot(ring, ring->current_slot);
 322         ring->current_slot = slot;
 323         ring->used_slots++;
 324
 325         update_max_used_slots(ring, ring->used_slots);
 326
 327         return slot;
 328 }
 329
 330 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
 331 {
 332         static const u16 map64[] = {
 333                 B43_MMIO_DMA64_BASE0,
 334                 B43_MMIO_DMA64_BASE1,
 335                 B43_MMIO_DMA64_BASE2,
 336                 B43_MMIO_DMA64_BASE3,
 337                 B43_MMIO_DMA64_BASE4,
 338                 B43_MMIO_DMA64_BASE5,
 339         };
 340         static const u16 map32[] = {
 341                 B43_MMIO_DMA32_BASE0,
 342                 B43_MMIO_DMA32_BASE1,
 343                 B43_MMIO_DMA32_BASE2,
 344                 B43_MMIO_DMA32_BASE3,
 345                 B43_MMIO_DMA32_BASE4,
 346                 B43_MMIO_DMA32_BASE5,
 347         };
 348
 349         if (type == B43_DMA_64BIT) {
 350                 B43_WARN_ON(!(controller_idx >= 0 &&
 351                               controller_idx < ARRAY_SIZE(map64)));
 352                 return map64[controller_idx];
 353         }
 354         B43_WARN_ON(!(controller_idx >= 0 &&
 355                       controller_idx < ARRAY_SIZE(map32)));
 356         return map32[controller_idx];
 357 }
 358
 359 static inline
 360     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 361                               unsigned char *buf, size_t len, int tx)
 362 {
 363         dma_addr_t dmaaddr;
 364
 365         if (tx) {
 366                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
 367                                          buf, len, DMA_TO_DEVICE);
 368         } else {
 369                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
 370                                          buf, len, DMA_FROM_DEVICE);
 371         }
 372
 373         return dmaaddr;
 374 }
 375
 376 static inline
 377     void unmap_descbuffer(struct b43_dmaring *ring,
 378                           dma_addr_t addr, size_t len, int tx)
 379 {
 380         if (tx) {
 381                 dma_unmap_single(ring->dev->dev->dma_dev,
 382                                  addr, len, DMA_TO_DEVICE);
 383         } else {
 384                 dma_unmap_single(ring->dev->dev->dma_dev,
 385                                  addr, len, DMA_FROM_DEVICE);
 386         }
 387 }
 388
 389 static inline
 390     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 391                                  dma_addr_t addr, size_t len)
 392 {
 393         B43_WARN_ON(ring->tx);
 394         dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
 395                                     addr, len, DMA_FROM_DEVICE);
 396 }
 397
 398 static inline
 399     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 400                                     dma_addr_t addr, size_t len)
 401 {
 402         B43_WARN_ON(ring->tx);
 403         dma_sync_single_for_device(ring->dev->dev->dma_dev,
 404                                    addr, len, DMA_FROM_DEVICE);
 405 }
 406
 407 static inline
 408     void free_descriptor_buffer(struct b43_dmaring *ring,
 409                                 struct b43_dmadesc_meta *meta)
 410 {
 411         if (meta->skb) {
 412                 dev_kfree_skb_any(meta->skb);
 413                 meta->skb = NULL;
 414         }
 415 }
 416
 417 static int alloc_ringmemory(struct b43_dmaring *ring)
 418 {
 419         gfp_t flags = GFP_KERNEL;
 420
 421         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 422          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 423          * has shown that 4K is sufficient for the latter as long as the buffer
 424          * does not cross an 8K boundary.
 425          *
 426          * For unknown reasons - possibly a hardware error - the BCM4311 rev
 427          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
 428          * which accounts for the GFP_DMA flag below.
 429          *
 430          * The flags here must match the flags in free_ringmemory below!
 431          */
 432         if (ring->type == B43_DMA_64BIT)
 433                 flags |= GFP_DMA;
 434         ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
 435                                             B43_DMA_RINGMEMSIZE,
 436                                             &(ring->dmabase), flags);
 437         if (!ring->descbase) {
 438                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 439                 return -ENOMEM;
 440         }
 441         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 442
 443         return 0;
 444 }
 445
 446 static void free_ringmemory(struct b43_dmaring *ring)
 447 {
 448         dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
 449                           ring->descbase, ring->dmabase);
 450 }
 451
 452 /* Reset the RX DMA channel */
 453 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
 454                                       enum b43_dmatype type)
 455 {
 456         int i;
 457         u32 value;
 458         u16 offset;
 459
 460         might_sleep();
 461
 462         offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 463         b43_write32(dev, mmio_base + offset, 0);
 464         for (i = 0; i < 10; i++) {
 465                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
 466                                                    B43_DMA32_RXSTATUS;
 467                 value = b43_read32(dev, mmio_base + offset);
 468                 if (type == B43_DMA_64BIT) {
 469                         value &= B43_DMA64_RXSTAT;
 470                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 471                                 i = -1;
 472                                 break;
 473                         }
 474                 } else {
 475                         value &= B43_DMA32_RXSTATE;
 476                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 477                                 i = -1;
 478                                 break;
 479                         }
 480                 }
 481                 msleep(1);
 482         }
 483         if (i != -1) {
 484                 b43err(dev->wl, "DMA RX reset timed out\n");
 485                 return -ENODEV;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /* Reset the TX DMA channel */
 492 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
 493                                       enum b43_dmatype type)
 494 {
 495         int i;
 496         u32 value;
 497         u16 offset;
 498
 499         might_sleep();
 500
 501         for (i = 0; i < 10; i++) {
 502                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 503                                                    B43_DMA32_TXSTATUS;
 504                 value = b43_read32(dev, mmio_base + offset);
 505                 if (type == B43_DMA_64BIT) {
 506                         value &= B43_DMA64_TXSTAT;
 507                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 508                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 509                             value == B43_DMA64_TXSTAT_STOPPED)
 510                                 break;
 511                 } else {
 512                         value &= B43_DMA32_TXSTATE;
 513                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 514                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 515                             value == B43_DMA32_TXSTAT_STOPPED)
 516                                 break;
 517                 }
 518                 msleep(1);
 519         }
 520         offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 521         b43_write32(dev, mmio_base + offset, 0);
 522         for (i = 0; i < 10; i++) {
 523                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 524                                                    B43_DMA32_TXSTATUS;
 525                 value = b43_read32(dev, mmio_base + offset);
 526                 if (type == B43_DMA_64BIT) {
 527                         value &= B43_DMA64_TXSTAT;
 528                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 529                                 i = -1;
 530                                 break;
 531                         }
 532                 } else {
 533                         value &= B43_DMA32_TXSTATE;
 534                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 535                                 i = -1;
 536                                 break;
 537                         }
 538                 }
 539                 msleep(1);
 540         }
 541         if (i != -1) {
 542                 b43err(dev->wl, "DMA TX reset timed out\n");
 543                 return -ENODEV;
 544         }
 545         /* ensure the reset is completed. */
 546         msleep(1);
 547
 548         return 0;
 549 }
 550
 551 /* Check if a DMA mapping address is invalid. */
 552 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
 553                                   dma_addr_t addr,
 554                                   size_t buffersize, bool dma_to_device)
 555 {
 556         if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
 557                 return 1;
 558
 559         switch (ring->type) {
 560         case B43_DMA_30BIT:
 561                 if ((u64)addr + buffersize > (1ULL << 30))
 562                         goto address_error;
 563                 break;
 564         case B43_DMA_32BIT:
 565                 if ((u64)addr + buffersize > (1ULL << 32))
 566                         goto address_error;
 567                 break;
 568         case B43_DMA_64BIT:
 569                 /* Currently we can't have addresses beyond
 570                  * 64bit in the kernel. */
 571                 break;
 572         }
 573
 574         /* The address is OK. */
 575         return 0;
 576
 577 address_error:
 578         /* We can't support this address. Unmap it again. */
 579         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
 580
 581         return 1;
 582 }
 583
 584 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
 585 {
 586         unsigned char *f = skb->data + ring->frameoffset;
 587
 588         return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
 589 }
 590
 591 static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
 592 {
 593         struct b43_rxhdr_fw4 *rxhdr;
 594         unsigned char *frame;
 595
 596         /* This poisons the RX buffer to detect DMA failures. */
 597
 598         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 599         rxhdr->frame_len = 0;
 600
 601         B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
 602         frame = skb->data + ring->frameoffset;
 603         memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
 604 }
 605
 606 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 607                                struct b43_dmadesc_generic *desc,
 608                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 609 {
 610         dma_addr_t dmaaddr;
 611         struct sk_buff *skb;
 612
 613         B43_WARN_ON(ring->tx);
 614
 615         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 616         if (unlikely(!skb))
 617                 return -ENOMEM;
 618         b43_poison_rx_buffer(ring, skb);
 619         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 620         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 621                 /* ugh. try to realloc in zone_dma */
 622                 gfp_flags |= GFP_DMA;
 623
 624                 dev_kfree_skb_any(skb);
 625
 626                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 627                 if (unlikely(!skb))
 628                         return -ENOMEM;
 629                 b43_poison_rx_buffer(ring, skb);
 630                 dmaaddr = map_descbuffer(ring, skb->data,
 631                                          ring->rx_buffersize, 0);
 632                 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 633                         b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
 634                         dev_kfree_skb_any(skb);
 635                         return -EIO;
 636                 }
 637         }
 638
 639         meta->skb = skb;
 640         meta->dmaaddr = dmaaddr;
 641         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 642                                    ring->rx_buffersize, 0, 0, 0);
 643
 644         return 0;
 645 }
 646
 647 /* Allocate the initial descbuffers.
 648  * This is used for an RX ring only.
 649  */
 650 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 651 {
 652         int i, err = -ENOMEM;
 653         struct b43_dmadesc_generic *desc;
 654         struct b43_dmadesc_meta *meta;
 655
 656         for (i = 0; i < ring->nr_slots; i++) {
 657                 desc = ring->ops->idx2desc(ring, i, &meta);
 658
 659                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 660                 if (err) {
 661                         b43err(ring->dev->wl,
 662                                "Failed to allocate initial descbuffers\n");
 663                         goto err_unwind;
 664                 }
 665         }
 666         mb();
 667         ring->used_slots = ring->nr_slots;
 668         err = 0;
 669       out:
 670         return err;
 671
 672       err_unwind:
 673         for (i--; i >= 0; i--) {
 674                 desc = ring->ops->idx2desc(ring, i, &meta);
 675
 676                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 677                 dev_kfree_skb(meta->skb);
 678         }
 679         goto out;
 680 }
 681
 682 /* Do initial setup of the DMA controller.
 683  * Reset the controller, write the ring busaddress
 684  * and switch the "enable" bit on.
 685  */
 686 static int dmacontroller_setup(struct b43_dmaring *ring)
 687 {
 688         int err = 0;
 689         u32 value;
 690         u32 addrext;
 691         bool parity = ring->dev->dma.parity;
 692         u32 addrlo;
 693         u32 addrhi;
 694
 695         if (ring->tx) {
 696                 if (ring->type == B43_DMA_64BIT) {
 697                         u64 ringbase = (u64) (ring->dmabase);
 698                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 699                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 700                         addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
 701
 702                         value = B43_DMA64_TXENABLE;
 703                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 704                             & B43_DMA64_TXADDREXT_MASK;
 705                         if (!parity)
 706                                 value |= B43_DMA64_TXPARITYDISABLE;
 707                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 708                         b43_dma_write(ring, B43_DMA64_TXRINGLO, addrlo);
 709                         b43_dma_write(ring, B43_DMA64_TXRINGHI, addrhi);
 710                 } else {
 711                         u32 ringbase = (u32) (ring->dmabase);
 712                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 713                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 714
 715                         value = B43_DMA32_TXENABLE;
 716                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 717                             & B43_DMA32_TXADDREXT_MASK;
 718                         if (!parity)
 719                                 value |= B43_DMA32_TXPARITYDISABLE;
 720                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 721                         b43_dma_write(ring, B43_DMA32_TXRING, addrlo);
 722                 }
 723         } else {
 724                 err = alloc_initial_descbuffers(ring);
 725                 if (err)
 726                         goto out;
 727                 if (ring->type == B43_DMA_64BIT) {
 728                         u64 ringbase = (u64) (ring->dmabase);
 729                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 730                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 731                         addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
 732
 733                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 734                         value |= B43_DMA64_RXENABLE;
 735                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 736                             & B43_DMA64_RXADDREXT_MASK;
 737                         if (!parity)
 738                                 value |= B43_DMA64_RXPARITYDISABLE;
 739                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 740                         b43_dma_write(ring, B43_DMA64_RXRINGLO, addrlo);
 741                         b43_dma_write(ring, B43_DMA64_RXRINGHI, addrhi);
 742                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 743                                       sizeof(struct b43_dmadesc64));
 744                 } else {
 745                         u32 ringbase = (u32) (ring->dmabase);
 746                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 747                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 748
 749                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 750                         value |= B43_DMA32_RXENABLE;
 751                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 752                             & B43_DMA32_RXADDREXT_MASK;
 753                         if (!parity)
 754                                 value |= B43_DMA32_RXPARITYDISABLE;
 755                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 756                         b43_dma_write(ring, B43_DMA32_RXRING, addrlo);
 757                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 758                                       sizeof(struct b43_dmadesc32));
 759                 }
 760         }
 761
 762 out:
 763         return err;
 764 }
 765
 766 /* Shutdown the DMA controller. */
 767 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 768 {
 769         if (ring->tx) {
 770                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 771                                            ring->type);
 772                 if (ring->type == B43_DMA_64BIT) {
 773                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 774                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 775                 } else
 776                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 777         } else {
 778                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 779                                            ring->type);
 780                 if (ring->type == B43_DMA_64BIT) {
 781                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 782                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 783                 } else
 784                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 785         }
 786 }
 787
 788 static void free_all_descbuffers(struct b43_dmaring *ring)
 789 {
 790         struct b43_dmadesc_meta *meta;
 791         int i;
 792
 793         if (!ring->used_slots)
 794                 return;
 795         for (i = 0; i < ring->nr_slots; i++) {
 796                 /* get meta - ignore returned value */
 797                 ring->ops->idx2desc(ring, i, &meta);
 798
 799                 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
 800                         B43_WARN_ON(!ring->tx);
 801                         continue;
 802                 }
 803                 if (ring->tx) {
 804                         unmap_descbuffer(ring, meta->dmaaddr,
 805                                          meta->skb->len, 1);
 806                 } else {
 807                         unmap_descbuffer(ring, meta->dmaaddr,
 808                                          ring->rx_buffersize, 0);
 809                 }
 810                 free_descriptor_buffer(ring, meta);
 811         }
 812 }
 813
 814 static u64 supported_dma_mask(struct b43_wldev *dev)
 815 {
 816         u32 tmp;
 817         u16 mmio_base;
 818
 819         switch (dev->dev->bus_type) {
 820 #ifdef CONFIG_B43_BCMA
 821         case B43_BUS_BCMA:
 822                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
 823                 if (tmp & BCMA_IOST_DMA64)
 824                         return DMA_BIT_MASK(64);
 825                 break;
 826 #endif
 827 #ifdef CONFIG_B43_SSB
 828         case B43_BUS_SSB:
 829                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
 830                 if (tmp & SSB_TMSHIGH_DMA64)
 831                         return DMA_BIT_MASK(64);
 832                 break;
 833 #endif
 834         }
 835
 836         mmio_base = b43_dmacontroller_base(0, 0);
 837         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 838         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 839         if (tmp & B43_DMA32_TXADDREXT_MASK)
 840                 return DMA_BIT_MASK(32);
 841
 842         return DMA_BIT_MASK(30);
 843 }
 844
 845 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
 846 {
 847         if (dmamask == DMA_BIT_MASK(30))
 848                 return B43_DMA_30BIT;
 849         if (dmamask == DMA_BIT_MASK(32))
 850                 return B43_DMA_32BIT;
 851         if (dmamask == DMA_BIT_MASK(64))
 852                 return B43_DMA_64BIT;
 853         B43_WARN_ON(1);
 854         return B43_DMA_30BIT;
 855 }
 856
 857 /* Main initialization function. */
 858 static
 859 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 860                                       int controller_index,
 861                                       int for_tx,
 862                                       enum b43_dmatype type)
 863 {
 864         struct b43_dmaring *ring;
 865         int i, err;
 866         dma_addr_t dma_test;
 867
 868         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 869         if (!ring)
 870                 goto out;
 871
 872         ring->nr_slots = B43_RXRING_SLOTS;
 873         if (for_tx)
 874                 ring->nr_slots = B43_TXRING_SLOTS;
 875
 876         ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
 877                              GFP_KERNEL);
 878         if (!ring->meta)
 879                 goto err_kfree_ring;
 880         for (i = 0; i < ring->nr_slots; i++)
 881                 ring->meta->skb = B43_DMA_PTR_POISON;
 882
 883         ring->type = type;
 884         ring->dev = dev;
 885         ring->mmio_base = b43_dmacontroller_base(type, controller_index);
 886         ring->index = controller_index;
 887         if (type == B43_DMA_64BIT)
 888                 ring->ops = &dma64_ops;
 889         else
 890                 ring->ops = &dma32_ops;
 891         if (for_tx) {
 892                 ring->tx = 1;
 893                 ring->current_slot = -1;
 894         } else {
 895                 if (ring->index == 0) {
 896                         switch (dev->fw.hdr_format) {
 897                         case B43_FW_HDR_598:
 898                                 ring->rx_buffersize = B43_DMA0_RX_FW598_BUFSIZE;
 899                                 ring->frameoffset = B43_DMA0_RX_FW598_FO;
 900                                 break;
 901                         case B43_FW_HDR_410:
 902                         case B43_FW_HDR_351:
 903                                 ring->rx_buffersize = B43_DMA0_RX_FW351_BUFSIZE;
 904                                 ring->frameoffset = B43_DMA0_RX_FW351_FO;
 905                                 break;
 906                         }
 907                 } else
 908                         B43_WARN_ON(1);
 909         }
 910 #ifdef CONFIG_B43_DEBUG
 911         ring->last_injected_overflow = jiffies;
 912 #endif
 913
 914         if (for_tx) {
 915                 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
 916                 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
 917
 918                 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 919                                             b43_txhdr_size(dev),
 920                                             GFP_KERNEL);
 921                 if (!ring->txhdr_cache)
 922                         goto err_kfree_meta;
 923
 924                 /* test for ability to dma to txhdr_cache */
 925                 dma_test = dma_map_single(dev->dev->dma_dev,
 926                                           ring->txhdr_cache,
 927                                           b43_txhdr_size(dev),
 928                                           DMA_TO_DEVICE);
 929
 930                 if (b43_dma_mapping_error(ring, dma_test,
 931                                           b43_txhdr_size(dev), 1)) {
 932                         /* ugh realloc */
 933                         kfree(ring->txhdr_cache);
 934                         ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 935                                                     b43_txhdr_size(dev),
 936                                                     GFP_KERNEL | GFP_DMA);
 937                         if (!ring->txhdr_cache)
 938                                 goto err_kfree_meta;
 939
 940                         dma_test = dma_map_single(dev->dev->dma_dev,
 941                                                   ring->txhdr_cache,
 942                                                   b43_txhdr_size(dev),
 943                                                   DMA_TO_DEVICE);
 944
 945                         if (b43_dma_mapping_error(ring, dma_test,
 946                                                   b43_txhdr_size(dev), 1)) {
 947
 948                                 b43err(dev->wl,
 949                                        "TXHDR DMA allocation failed\n");
 950                                 goto err_kfree_txhdr_cache;
 951                         }
 952                 }
 953
 954                 dma_unmap_single(dev->dev->dma_dev,
 955                                  dma_test, b43_txhdr_size(dev),
 956                                  DMA_TO_DEVICE);
 957         }
 958
 959         err = alloc_ringmemory(ring);
 960         if (err)
 961                 goto err_kfree_txhdr_cache;
 962         err = dmacontroller_setup(ring);
 963         if (err)
 964                 goto err_free_ringmemory;
 965
 966       out:
 967         return ring;
 968
 969       err_free_ringmemory:
 970         free_ringmemory(ring);
 971       err_kfree_txhdr_cache:
 972         kfree(ring->txhdr_cache);
 973       err_kfree_meta:
 974         kfree(ring->meta);
 975       err_kfree_ring:
 976         kfree(ring);
 977         ring = NULL;
 978         goto out;
 979 }
 980
 981 #define divide(a, b)    ({      \
 982         typeof(a) __a = a;      \
 983         do_div(__a, b);         \
 984         __a;                    \
 985   })
 986
 987 #define modulo(a, b)    ({      \
 988         typeof(a) __a = a;      \
 989         do_div(__a, b);         \
 990   })
 991
 992 /* Main cleanup function. */
 993 static void b43_destroy_dmaring(struct b43_dmaring *ring,
 994                                 const char *ringname)
 995 {
 996         if (!ring)
 997                 return;
 998
 999 #ifdef CONFIG_B43_DEBUG
1000         {
1001                 /* Print some statistics. */
1002                 u64 failed_packets = ring->nr_failed_tx_packets;
1003                 u64 succeed_packets = ring->nr_succeed_tx_packets;
1004                 u64 nr_packets = failed_packets + succeed_packets;
1005                 u64 permille_failed = 0, average_tries = 0;
1006
1007                 if (nr_packets)
1008                         permille_failed = divide(failed_packets * 1000, nr_packets);
1009                 if (nr_packets)
1010                         average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
1011
1012                 b43dbg(ring->dev->wl, "DMA-%u %s: "
1013                        "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
1014                        "Average tries %llu.%02llu\n",
1015                        (unsigned int)(ring->type), ringname,
1016                        ring->max_used_slots,
1017                        ring->nr_slots,
1018                        (unsigned long long)failed_packets,
1019                        (unsigned long long)nr_packets,
1020                        (unsigned long long)divide(permille_failed, 10),
1021                        (unsigned long long)modulo(permille_failed, 10),
1022                        (unsigned long long)divide(average_tries, 100),
1023                        (unsigned long long)modulo(average_tries, 100));
1024         }
1025 #endif /* DEBUG */
1026
1027         /* Device IRQs are disabled prior entering this function,
1028          * so no need to take care of concurrency with rx handler stuff.
1029          */
1030         dmacontroller_cleanup(ring);
1031         free_all_descbuffers(ring);
1032         free_ringmemory(ring);
1033
1034         kfree(ring->txhdr_cache);
1035         kfree(ring->meta);
1036         kfree(ring);
1037 }
1038
1039 #define destroy_ring(dma, ring) do {                            \
1040         b43_destroy_dmaring((dma)->ring, __stringify(ring));    \
1041         (dma)->ring = NULL;                                     \
1042     } while (0)
1043
1044 void b43_dma_free(struct b43_wldev *dev)
1045 {
1046         struct b43_dma *dma;
1047
1048         if (b43_using_pio_transfers(dev))
1049                 return;
1050         dma = &dev->dma;
1051
1052         destroy_ring(dma, rx_ring);
1053         destroy_ring(dma, tx_ring_AC_BK);
1054         destroy_ring(dma, tx_ring_AC_BE);
1055         destroy_ring(dma, tx_ring_AC_VI);
1056         destroy_ring(dma, tx_ring_AC_VO);
1057         destroy_ring(dma, tx_ring_mcast);
1058 }
1059
1060 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1061 {
1062         u64 orig_mask = mask;
1063         bool fallback = 0;
1064         int err;
1065
1066         /* Try to set the DMA mask. If it fails, try falling back to a
1067          * lower mask, as we can always also support a lower one. */
1068         while (1) {
1069                 err = dma_set_mask(dev->dev->dma_dev, mask);
1070                 if (!err) {
1071                         err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1072                         if (!err)
1073                                 break;
1074                 }
1075                 if (mask == DMA_BIT_MASK(64)) {
1076                         mask = DMA_BIT_MASK(32);
1077                         fallback = 1;
1078                         continue;
1079                 }
1080                 if (mask == DMA_BIT_MASK(32)) {
1081                         mask = DMA_BIT_MASK(30);
1082                         fallback = 1;
1083                         continue;
1084                 }
1085                 b43err(dev->wl, "The machine/kernel does not support "
1086                        "the required %u-bit DMA mask\n",
1087                        (unsigned int)dma_mask_to_engine_type(orig_mask));
1088                 return -EOPNOTSUPP;
1089         }
1090         if (fallback) {
1091                 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1092                         (unsigned int)dma_mask_to_engine_type(orig_mask),
1093                         (unsigned int)dma_mask_to_engine_type(mask));
1094         }
1095
1096         return 0;
1097 }
1098
1099 /* Some hardware with 64-bit DMA seems to be bugged and looks for translation
1100  * bit in low address word instead of high one.
1101  */
1102 static bool b43_dma_translation_in_low_word(struct b43_wldev *dev,
1103                                             enum b43_dmatype type)
1104 {
1105         if (type != B43_DMA_64BIT)
1106                 return 1;
1107
1108 #ifdef CONFIG_B43_SSB
1109         if (dev->dev->bus_type == B43_BUS_SSB &&
1110             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
1111             !(dev->dev->sdev->bus->host_pci->is_pcie &&
1112               ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64))
1113                         return 1;
1114 #endif
1115         return 0;
1116 }
1117
1118 int b43_dma_init(struct b43_wldev *dev)
1119 {
1120         struct b43_dma *dma = &dev->dma;
1121         int err;
1122         u64 dmamask;
1123         enum b43_dmatype type;
1124
1125         dmamask = supported_dma_mask(dev);
1126         type = dma_mask_to_engine_type(dmamask);
1127         err = b43_dma_set_mask(dev, dmamask);
1128         if (err)
1129                 return err;
1130
1131         switch (dev->dev->bus_type) {
1132 #ifdef CONFIG_B43_BCMA
1133         case B43_BUS_BCMA:
1134                 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1135                 break;
1136 #endif
1137 #ifdef CONFIG_B43_SSB
1138         case B43_BUS_SSB:
1139                 dma->translation = ssb_dma_translation(dev->dev->sdev);
1140                 break;
1141 #endif
1142         }
1143         dma->translation_in_low = b43_dma_translation_in_low_word(dev, type);
1144
1145         dma->parity = true;
1146 #ifdef CONFIG_B43_BCMA
1147         /* TODO: find out which SSB devices need disabling parity */
1148         if (dev->dev->bus_type == B43_BUS_BCMA)
1149                 dma->parity = false;
1150 #endif
1151
1152         err = -ENOMEM;
1153         /* setup TX DMA channels. */
1154         dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1155         if (!dma->tx_ring_AC_BK)
1156                 goto out;
1157
1158         dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1159         if (!dma->tx_ring_AC_BE)
1160                 goto err_destroy_bk;
1161
1162         dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1163         if (!dma->tx_ring_AC_VI)
1164                 goto err_destroy_be;
1165
1166         dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1167         if (!dma->tx_ring_AC_VO)
1168                 goto err_destroy_vi;
1169
1170         dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1171         if (!dma->tx_ring_mcast)
1172                 goto err_destroy_vo;
1173
1174         /* setup RX DMA channel. */
1175         dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1176         if (!dma->rx_ring)
1177                 goto err_destroy_mcast;
1178
1179         /* No support for the TX status DMA ring. */
1180         B43_WARN_ON(dev->dev->core_rev < 5);
1181
1182         b43dbg(dev->wl, "%u-bit DMA initialized\n",
1183                (unsigned int)type);
1184         err = 0;
1185 out:
1186         return err;
1187
1188 err_destroy_mcast:
1189         destroy_ring(dma, tx_ring_mcast);
1190 err_destroy_vo:
1191         destroy_ring(dma, tx_ring_AC_VO);
1192 err_destroy_vi:
1193         destroy_ring(dma, tx_ring_AC_VI);
1194 err_destroy_be:
1195         destroy_ring(dma, tx_ring_AC_BE);
1196 err_destroy_bk:
1197         destroy_ring(dma, tx_ring_AC_BK);
1198         return err;
1199 }
1200
1201 /* Generate a cookie for the TX header. */
1202 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1203 {
1204         u16 cookie;
1205
1206         /* Use the upper 4 bits of the cookie as
1207          * DMA controller ID and store the slot number
1208          * in the lower 12 bits.
1209          * Note that the cookie must never be 0, as this
1210          * is a special value used in RX path.
1211          * It can also not be 0xFFFF because that is special
1212          * for multicast frames.
1213          */
1214         cookie = (((u16)ring->index + 1) << 12);
1215         B43_WARN_ON(slot & ~0x0FFF);
1216         cookie |= (u16)slot;
1217
1218         return cookie;
1219 }
1220
1221 /* Inspect a cookie and find out to which controller/slot it belongs. */
1222 static
1223 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1224 {
1225         struct b43_dma *dma = &dev->dma;
1226         struct b43_dmaring *ring = NULL;
1227
1228         switch (cookie & 0xF000) {
1229         case 0x1000:
1230                 ring = dma->tx_ring_AC_BK;
1231                 break;
1232         case 0x2000:
1233                 ring = dma->tx_ring_AC_BE;
1234                 break;
1235         case 0x3000:
1236                 ring = dma->tx_ring_AC_VI;
1237                 break;
1238         case 0x4000:
1239                 ring = dma->tx_ring_AC_VO;
1240                 break;
1241         case 0x5000:
1242                 ring = dma->tx_ring_mcast;
1243                 break;
1244         }
1245         *slot = (cookie & 0x0FFF);
1246         if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1247                 b43dbg(dev->wl, "TX-status contains "
1248                        "invalid cookie: 0x%04X\n", cookie);
1249                 return NULL;
1250         }
1251
1252         return ring;
1253 }
1254
1255 static int dma_tx_fragment(struct b43_dmaring *ring,
1256                            struct sk_buff *skb)
1257 {
1258         const struct b43_dma_ops *ops = ring->ops;
1259         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1260         struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1261         u8 *header;
1262         int slot, old_top_slot, old_used_slots;
1263         int err;
1264         struct b43_dmadesc_generic *desc;
1265         struct b43_dmadesc_meta *meta;
1266         struct b43_dmadesc_meta *meta_hdr;
1267         u16 cookie;
1268         size_t hdrsize = b43_txhdr_size(ring->dev);
1269
1270         /* Important note: If the number of used DMA slots per TX frame
1271          * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1272          * the file has to be updated, too!
1273          */
1274
1275         old_top_slot = ring->current_slot;
1276         old_used_slots = ring->used_slots;
1277
1278         /* Get a slot for the header. */
1279         slot = request_slot(ring);
1280         desc = ops->idx2desc(ring, slot, &meta_hdr);
1281         memset(meta_hdr, 0, sizeof(*meta_hdr));
1282
1283         header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1284         cookie = generate_cookie(ring, slot);
1285         err = b43_generate_txhdr(ring->dev, header,
1286                                  skb, info, cookie);
1287         if (unlikely(err)) {
1288                 ring->current_slot = old_top_slot;
1289                 ring->used_slots = old_used_slots;
1290                 return err;
1291         }
1292
1293         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1294                                            hdrsize, 1);
1295         if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1296                 ring->current_slot = old_top_slot;
1297                 ring->used_slots = old_used_slots;
1298                 return -EIO;
1299         }
1300         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1301                              hdrsize, 1, 0, 0);
1302
1303         /* Get a slot for the payload. */
1304         slot = request_slot(ring);
1305         desc = ops->idx2desc(ring, slot, &meta);
1306         memset(meta, 0, sizeof(*meta));
1307
1308         meta->skb = skb;
1309         meta->is_last_fragment = 1;
1310         priv_info->bouncebuffer = NULL;
1311
1312         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1313         /* create a bounce buffer in zone_dma on mapping failure. */
1314         if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1315                 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1316                                                   GFP_ATOMIC | GFP_DMA);
1317                 if (!priv_info->bouncebuffer) {
1318                         ring->current_slot = old_top_slot;
1319                         ring->used_slots = old_used_slots;
1320                         err = -ENOMEM;
1321                         goto out_unmap_hdr;
1322                 }
1323
1324                 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1325                 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1326                         kfree(priv_info->bouncebuffer);
1327                         priv_info->bouncebuffer = NULL;
1328                         ring->current_slot = old_top_slot;
1329                         ring->used_slots = old_used_slots;
1330                         err = -EIO;
1331                         goto out_unmap_hdr;
1332                 }
1333         }
1334
1335         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1336
1337         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1338                 /* Tell the firmware about the cookie of the last
1339                  * mcast frame, so it can clear the more-data bit in it. */
1340                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1341                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1342         }
1343         /* Now transfer the whole frame. */
1344         wmb();
1345         ops->poke_tx(ring, next_slot(ring, slot));
1346         return 0;
1347
1348 out_unmap_hdr:
1349         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1350                          hdrsize, 1);
1351         return err;
1352 }
1353
1354 static inline int should_inject_overflow(struct b43_dmaring *ring)
1355 {
1356 #ifdef CONFIG_B43_DEBUG
1357         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1358                 /* Check if we should inject another ringbuffer overflow
1359                  * to test handling of this situation in the stack. */
1360                 unsigned long next_overflow;
1361
1362                 next_overflow = ring->last_injected_overflow + HZ;
1363                 if (time_after(jiffies, next_overflow)) {
1364                         ring->last_injected_overflow = jiffies;
1365                         b43dbg(ring->dev->wl,
1366                                "Injecting TX ring overflow on "
1367                                "DMA controller %d\n", ring->index);
1368                         return 1;
1369                 }
1370         }
1371 #endif /* CONFIG_B43_DEBUG */
1372         return 0;
1373 }
1374
1375 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1376 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1377                                                    u8 queue_prio)
1378 {
1379         struct b43_dmaring *ring;
1380
1381         if (dev->qos_enabled) {
1382                 /* 0 = highest priority */
1383                 switch (queue_prio) {
1384                 default:
1385                         B43_WARN_ON(1);
1386                         /* fallthrough */
1387                 case 0:
1388                         ring = dev->dma.tx_ring_AC_VO;
1389                         break;
1390                 case 1:
1391                         ring = dev->dma.tx_ring_AC_VI;
1392                         break;
1393                 case 2:
1394                         ring = dev->dma.tx_ring_AC_BE;
1395                         break;
1396                 case 3:
1397                         ring = dev->dma.tx_ring_AC_BK;
1398                         break;
1399                 }
1400         } else
1401                 ring = dev->dma.tx_ring_AC_BE;
1402
1403         return ring;
1404 }
1405
1406 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1407 {
1408         struct b43_dmaring *ring;
1409         struct ieee80211_hdr *hdr;
1410         int err = 0;
1411         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1412
1413         hdr = (struct ieee80211_hdr *)skb->data;
1414         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1415                 /* The multicast ring will be sent after the DTIM */
1416                 ring = dev->dma.tx_ring_mcast;
1417                 /* Set the more-data bit. Ucode will clear it on
1418                  * the last frame for us. */
1419                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1420         } else {
1421                 /* Decide by priority where to put this frame. */
1422                 ring = select_ring_by_priority(
1423                         dev, skb_get_queue_mapping(skb));
1424         }
1425
1426         B43_WARN_ON(!ring->tx);
1427
1428         if (unlikely(ring->stopped)) {
1429                 /* We get here only because of a bug in mac80211.
1430                  * Because of a race, one packet may be queued after
1431                  * the queue is stopped, thus we got called when we shouldn't.
1432                  * For now, just refuse the transmit. */
1433                 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1434                         b43err(dev->wl, "Packet after queue stopped\n");
1435                 err = -ENOSPC;
1436                 goto out;
1437         }
1438
1439         if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1440                 /* If we get here, we have a real error with the queue
1441                  * full, but queues not stopped. */
1442                 b43err(dev->wl, "DMA queue overflow\n");
1443                 err = -ENOSPC;
1444                 goto out;
1445         }
1446
1447         /* Assign the queue number to the ring (if not already done before)
1448          * so TX status handling can use it. The queue to ring mapping is
1449          * static, so we don't need to store it per frame. */
1450         ring->queue_prio = skb_get_queue_mapping(skb);
1451
1452         err = dma_tx_fragment(ring, skb);
1453         if (unlikely(err == -ENOKEY)) {
1454                 /* Drop this packet, as we don't have the encryption key
1455                  * anymore and must not transmit it unencrypted. */
1456                 dev_kfree_skb_any(skb);
1457                 err = 0;
1458                 goto out;
1459         }
1460         if (unlikely(err)) {
1461                 b43err(dev->wl, "DMA tx mapping failure\n");
1462                 goto out;
1463         }
1464         if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1465             should_inject_overflow(ring)) {
1466                 /* This TX ring is full. */
1467                 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1468                 ring->stopped = 1;
1469                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1470                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1471                 }
1472         }
1473 out:
1474
1475         return err;
1476 }
1477
1478 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1479                              const struct b43_txstatus *status)
1480 {
1481         const struct b43_dma_ops *ops;
1482         struct b43_dmaring *ring;
1483         struct b43_dmadesc_meta *meta;
1484         int slot, firstused;
1485         bool frame_succeed;
1486
1487         ring = parse_cookie(dev, status->cookie, &slot);
1488         if (unlikely(!ring))
1489                 return;
1490         B43_WARN_ON(!ring->tx);
1491
1492         /* Sanity check: TX packets are processed in-order on one ring.
1493          * Check if the slot deduced from the cookie really is the first
1494          * used slot. */
1495         firstused = ring->current_slot - ring->used_slots + 1;
1496         if (firstused < 0)
1497                 firstused = ring->nr_slots + firstused;
1498         if (unlikely(slot != firstused)) {
1499                 /* This possibly is a firmware bug and will result in
1500                  * malfunction, memory leaks and/or stall of DMA functionality. */
1501                 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1502                        "Expected %d, but got %d\n",
1503                        ring->index, firstused, slot);
1504                 return;
1505         }
1506
1507         ops = ring->ops;
1508         while (1) {
1509                 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1510                 /* get meta - ignore returned value */
1511                 ops->idx2desc(ring, slot, &meta);
1512
1513                 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1514                         b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1515                                "on ring %d\n",
1516                                slot, firstused, ring->index);
1517                         break;
1518                 }
1519                 if (meta->skb) {
1520                         struct b43_private_tx_info *priv_info =
1521                                 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1522
1523                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1524                         kfree(priv_info->bouncebuffer);
1525                         priv_info->bouncebuffer = NULL;
1526                 } else {
1527                         unmap_descbuffer(ring, meta->dmaaddr,
1528                                          b43_txhdr_size(dev), 1);
1529                 }
1530
1531                 if (meta->is_last_fragment) {
1532                         struct ieee80211_tx_info *info;
1533
1534                         if (unlikely(!meta->skb)) {
1535                                 /* This is a scatter-gather fragment of a frame, so
1536                                  * the skb pointer must not be NULL. */
1537                                 b43dbg(dev->wl, "TX status unexpected NULL skb "
1538                                        "at slot %d (first=%d) on ring %d\n",
1539                                        slot, firstused, ring->index);
1540                                 break;
1541                         }
1542
1543                         info = IEEE80211_SKB_CB(meta->skb);
1544
1545                         /*
1546                          * Call back to inform the ieee80211 subsystem about
1547                          * the status of the transmission.
1548                          */
1549                         frame_succeed = b43_fill_txstatus_report(dev, info, status);
1550 #ifdef CONFIG_B43_DEBUG
1551                         if (frame_succeed)
1552                                 ring->nr_succeed_tx_packets++;
1553                         else
1554                                 ring->nr_failed_tx_packets++;
1555                         ring->nr_total_packet_tries += status->frame_count;
1556 #endif /* DEBUG */
1557                         ieee80211_tx_status(dev->wl->hw, meta->skb);
1558
1559                         /* skb will be freed by ieee80211_tx_status().
1560                          * Poison our pointer. */
1561                         meta->skb = B43_DMA_PTR_POISON;
1562                 } else {
1563                         /* No need to call free_descriptor_buffer here, as
1564                          * this is only the txhdr, which is not allocated.
1565                          */
1566                         if (unlikely(meta->skb)) {
1567                                 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1568                                        "at slot %d (first=%d) on ring %d\n",
1569                                        slot, firstused, ring->index);
1570                                 break;
1571                         }
1572                 }
1573
1574                 /* Everything unmapped and free'd. So it's not used anymore. */
1575                 ring->used_slots--;
1576
1577                 if (meta->is_last_fragment) {
1578                         /* This is the last scatter-gather
1579                          * fragment of the frame. We are done. */
1580                         break;
1581                 }
1582                 slot = next_slot(ring, slot);
1583         }
1584         if (ring->stopped) {
1585                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1586                 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1587                 ring->stopped = 0;
1588                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1589                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1590                 }
1591         }
1592 }
1593
1594 static void dma_rx(struct b43_dmaring *ring, int *slot)
1595 {
1596         const struct b43_dma_ops *ops = ring->ops;
1597         struct b43_dmadesc_generic *desc;
1598         struct b43_dmadesc_meta *meta;
1599         struct b43_rxhdr_fw4 *rxhdr;
1600         struct sk_buff *skb;
1601         u16 len;
1602         int err;
1603         dma_addr_t dmaaddr;
1604
1605         desc = ops->idx2desc(ring, *slot, &meta);
1606
1607         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1608         skb = meta->skb;
1609
1610         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1611         len = le16_to_cpu(rxhdr->frame_len);
1612         if (len == 0) {
1613                 int i = 0;
1614
1615                 do {
1616                         udelay(2);
1617                         barrier();
1618                         len = le16_to_cpu(rxhdr->frame_len);
1619                 } while (len == 0 && i++ < 5);
1620                 if (unlikely(len == 0)) {
1621                         dmaaddr = meta->dmaaddr;
1622                         goto drop_recycle_buffer;
1623                 }
1624         }
1625         if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1626                 /* Something went wrong with the DMA.
1627                  * The device did not touch the buffer and did not overwrite the poison. */
1628                 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1629                 dmaaddr = meta->dmaaddr;
1630                 goto drop_recycle_buffer;
1631         }
1632         if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1633                 /* The data did not fit into one descriptor buffer
1634                  * and is split over multiple buffers.
1635                  * This should never happen, as we try to allocate buffers
1636                  * big enough. So simply ignore this packet.
1637                  */
1638                 int cnt = 0;
1639                 s32 tmp = len;
1640
1641                 while (1) {
1642                         desc = ops->idx2desc(ring, *slot, &meta);
1643                         /* recycle the descriptor buffer. */
1644                         b43_poison_rx_buffer(ring, meta->skb);
1645                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1646                                                    ring->rx_buffersize);
1647                         *slot = next_slot(ring, *slot);
1648                         cnt++;
1649                         tmp -= ring->rx_buffersize;
1650                         if (tmp <= 0)
1651                                 break;
1652                 }
1653                 b43err(ring->dev->wl, "DMA RX buffer too small "
1654                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1655                        len, ring->rx_buffersize, cnt);
1656                 goto drop;
1657         }
1658
1659         dmaaddr = meta->dmaaddr;
1660         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1661         if (unlikely(err)) {
1662                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1663                 goto drop_recycle_buffer;
1664         }
1665
1666         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1667         skb_put(skb, len + ring->frameoffset);
1668         skb_pull(skb, ring->frameoffset);
1669
1670         b43_rx(ring->dev, skb, rxhdr);
1671 drop:
1672         return;
1673
1674 drop_recycle_buffer:
1675         /* Poison and recycle the RX buffer. */
1676         b43_poison_rx_buffer(ring, skb);
1677         sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1678 }
1679
1680 void b43_dma_rx(struct b43_dmaring *ring)
1681 {
1682         const struct b43_dma_ops *ops = ring->ops;
1683         int slot, current_slot;
1684         int used_slots = 0;
1685
1686         B43_WARN_ON(ring->tx);
1687         current_slot = ops->get_current_rxslot(ring);
1688         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1689
1690         slot = ring->current_slot;
1691         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1692                 dma_rx(ring, &slot);
1693                 update_max_used_slots(ring, ++used_slots);
1694         }
1695         wmb();
1696         ops->set_current_rxslot(ring, slot);
1697         ring->current_slot = slot;
1698 }
1699
1700 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1701 {
1702         B43_WARN_ON(!ring->tx);
1703         ring->ops->tx_suspend(ring);
1704 }
1705
1706 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1707 {
1708         B43_WARN_ON(!ring->tx);
1709         ring->ops->tx_resume(ring);
1710 }
1711
1712 void b43_dma_tx_suspend(struct b43_wldev *dev)
1713 {
1714         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1715         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1716         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1717         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1718         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1719         b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1720 }
1721
1722 void b43_dma_tx_resume(struct b43_wldev *dev)
1723 {
1724         b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1725         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1726         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1727         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1728         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1729         b43_power_saving_ctl_bits(dev, 0);
1730 }
1731
1732 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1733                            u16 mmio_base, bool enable)
1734 {
1735         u32 ctl;
1736
1737         if (type == B43_DMA_64BIT) {
1738                 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1739                 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1740                 if (enable)
1741                         ctl |= B43_DMA64_RXDIRECTFIFO;
1742                 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1743         } else {
1744                 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1745                 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1746                 if (enable)
1747                         ctl |= B43_DMA32_RXDIRECTFIFO;
1748                 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1749         }
1750 }
1751
1752 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1753  * This is called from PIO code, so DMA structures are not available. */
1754 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1755                             unsigned int engine_index, bool enable)
1756 {
1757         enum b43_dmatype type;
1758         u16 mmio_base;
1759
1760         type = dma_mask_to_engine_type(supported_dma_mask(dev));
1761
1762         mmio_base = b43_dmacontroller_base(type, engine_index);
1763         direct_fifo_rx(dev, type, mmio_base, enable);
1764 }