drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  50         *csz = (int)u8tmp;
  51
  52         /*
  53          * This check was put in to avoid "unplesant" consequences if
  54          * the bootrom has not fully initialized all PCI devices.
  55          * Sometimes the cache line size register is not set
  56          */
  57
  58         if (*csz == 0)
  59                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  60 }
  61
  62 static void ath_cache_conf_rate(struct ath_softc *sc,
  63                                 struct ieee80211_conf *conf)
  64 {
  65         switch (conf->channel->band) {
  66         case IEEE80211_BAND_2GHZ:
  67                 if (conf_is_ht20(conf))
  68                         sc->cur_rate_table =
  69                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  70                 else if (conf_is_ht40_minus(conf))
  71                         sc->cur_rate_table =
  72                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  73                 else if (conf_is_ht40_plus(conf))
  74                         sc->cur_rate_table =
  75                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  76                 else
  77                         sc->cur_rate_table =
  78                           sc->hw_rate_table[ATH9K_MODE_11G];
  79                 break;
  80         case IEEE80211_BAND_5GHZ:
  81                 if (conf_is_ht20(conf))
  82                         sc->cur_rate_table =
  83                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  84                 else if (conf_is_ht40_minus(conf))
  85                         sc->cur_rate_table =
  86                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  87                 else if (conf_is_ht40_plus(conf))
  88                         sc->cur_rate_table =
  89                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  90                 else
  91                         sc->cur_rate_table =
  92                           sc->hw_rate_table[ATH9K_MODE_11A];
  93                 break;
  94         default:
  95                 BUG_ON(1);
  96                 break;
  97         }
  98 }
  99
 100 static void ath_update_txpow(struct ath_softc *sc)
 101 {
 102         struct ath_hal *ah = sc->sc_ah;
 103         u32 txpow;
 104
 105         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 106                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 107                 /* read back in case value is clamped */
 108                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 109                 sc->sc_curtxpow = txpow;
 110         }
 111 }
 112
 113 static u8 parse_mpdudensity(u8 mpdudensity)
 114 {
 115         /*
 116          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 117          *   0 for no restriction
 118          *   1 for 1/4 us
 119          *   2 for 1/2 us
 120          *   3 for 1 us
 121          *   4 for 2 us
 122          *   5 for 4 us
 123          *   6 for 8 us
 124          *   7 for 16 us
 125          */
 126         switch (mpdudensity) {
 127         case 0:
 128                 return 0;
 129         case 1:
 130         case 2:
 131         case 3:
 132                 /* Our lower layer calculations limit our precision to
 133                    1 microsecond */
 134                 return 1;
 135         case 4:
 136                 return 2;
 137         case 5:
 138                 return 4;
 139         case 6:
 140                 return 8;
 141         case 7:
 142                 return 16;
 143         default:
 144                 return 0;
 145         }
 146 }
 147
 148 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 149 {
 150         struct ath_rate_table *rate_table = NULL;
 151         struct ieee80211_supported_band *sband;
 152         struct ieee80211_rate *rate;
 153         int i, maxrates;
 154
 155         switch (band) {
 156         case IEEE80211_BAND_2GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 158                 break;
 159         case IEEE80211_BAND_5GHZ:
 160                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 161                 break;
 162         default:
 163                 break;
 164         }
 165
 166         if (rate_table == NULL)
 167                 return;
 168
 169         sband = &sc->sbands[band];
 170         rate = sc->rates[band];
 171
 172         if (rate_table->rate_cnt > ATH_RATE_MAX)
 173                 maxrates = ATH_RATE_MAX;
 174         else
 175                 maxrates = rate_table->rate_cnt;
 176
 177         for (i = 0; i < maxrates; i++) {
 178                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 179                 rate[i].hw_value = rate_table->info[i].ratecode;
 180                 sband->n_bitrates++;
 181                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 182                         rate[i].bitrate / 10, rate[i].hw_value);
 183         }
 184 }
 185
 186 static int ath_setup_channels(struct ath_softc *sc)
 187 {
 188         struct ath_hal *ah = sc->sc_ah;
 189         int nchan, i, a = 0, b = 0;
 190         u8 regclassids[ATH_REGCLASSIDS_MAX];
 191         u32 nregclass = 0;
 192         struct ieee80211_supported_band *band_2ghz;
 193         struct ieee80211_supported_band *band_5ghz;
 194         struct ieee80211_channel *chan_2ghz;
 195         struct ieee80211_channel *chan_5ghz;
 196         struct ath9k_channel *c;
 197
 198         /* Fill in ah->ah_channels */
 199         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 200                                       regclassids, ATH_REGCLASSIDS_MAX,
 201                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 202                 u32 rd = ah->ah_currentRD;
 203                 DPRINTF(sc, ATH_DBG_FATAL,
 204                         "Unable to collect channel list; "
 205                         "regdomain likely %u country code %u\n",
 206                         rd, CTRY_DEFAULT);
 207                 return -EINVAL;
 208         }
 209
 210         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 211         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 212         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 213         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 214
 215         for (i = 0; i < nchan; i++) {
 216                 c = &ah->ah_channels[i];
 217                 if (IS_CHAN_2GHZ(c)) {
 218                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 219                         chan_2ghz[a].center_freq = c->channel;
 220                         chan_2ghz[a].max_power = c->maxTxPower;
 221
 222                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 223                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 224                         if (c->channelFlags & CHANNEL_PASSIVE)
 225                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 226
 227                         band_2ghz->n_channels = ++a;
 228
 229                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 230                                 "channelFlags: 0x%x\n",
 231                                 c->channel, c->channelFlags);
 232                 } else if (IS_CHAN_5GHZ(c)) {
 233                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 234                         chan_5ghz[b].center_freq = c->channel;
 235                         chan_5ghz[b].max_power = c->maxTxPower;
 236
 237                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 238                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 239                         if (c->channelFlags & CHANNEL_PASSIVE)
 240                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 241
 242                         band_5ghz->n_channels = ++b;
 243
 244                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 245                                 "channelFlags: 0x%x\n",
 246                                 c->channel, c->channelFlags);
 247                 }
 248         }
 249
 250         return 0;
 251 }
 252
 253 /*
 254  * Set/change channels.  If the channel is really being changed, it's done
 255  * by reseting the chip.  To accomplish this we must first cleanup any pending
 256  * DMA, then restart stuff.
 257 */
 258 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 259 {
 260         struct ath_hal *ah = sc->sc_ah;
 261         bool fastcc = true, stopped;
 262         struct ieee80211_hw *hw = sc->hw;
 263
 264         if (sc->sc_flags & SC_OP_INVALID)
 265                 return -EIO;
 266
 267         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 268             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 269             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 270             (sc->sc_flags & SC_OP_FULL_RESET)) {
 271                 int status;
 272                 /*
 273                  * This is only performed if the channel settings have
 274                  * actually changed.
 275                  *
 276                  * To switch channels clear any pending DMA operations;
 277                  * wait long enough for the RX fifo to drain, reset the
 278                  * hardware at the new frequency, and then re-enable
 279                  * the relevant bits of the h/w.
 280                  */
 281                 ath9k_hw_set_interrupts(ah, 0);
 282                 ath_draintxq(sc, false);
 283                 stopped = ath_stoprecv(sc);
 284
 285                 /* XXX: do not flush receive queue here. We don't want
 286                  * to flush data frames already in queue because of
 287                  * changing channel. */
 288
 289                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 290                         fastcc = false;
 291
 292                 DPRINTF(sc, ATH_DBG_CONFIG,
 293                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 294                         sc->sc_ah->ah_curchan->channel,
 295                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 296
 297                 spin_lock_bh(&sc->sc_resetlock);
 298                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 299                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 300                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 301                         DPRINTF(sc, ATH_DBG_FATAL,
 302                                 "Unable to reset channel %u (%uMhz) "
 303                                 "flags 0x%x hal status %u\n",
 304                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 305                                                   hchan->channelFlags),
 306                                 hchan->channel, hchan->channelFlags, status);
 307                         spin_unlock_bh(&sc->sc_resetlock);
 308                         return -EIO;
 309                 }
 310                 spin_unlock_bh(&sc->sc_resetlock);
 311
 312                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 313                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 314
 315                 if (ath_startrecv(sc) != 0) {
 316                         DPRINTF(sc, ATH_DBG_FATAL,
 317                                 "Unable to restart recv logic\n");
 318                         return -EIO;
 319                 }
 320
 321                 ath_cache_conf_rate(sc, &hw->conf);
 322                 ath_update_txpow(sc);
 323                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 324         }
 325         return 0;
 326 }
 327
 328 /*
 329  *  This routine performs the periodic noise floor calibration function
 330  *  that is used to adjust and optimize the chip performance.  This
 331  *  takes environmental changes (location, temperature) into account.
 332  *  When the task is complete, it reschedules itself depending on the
 333  *  appropriate interval that was calculated.
 334  */
 335 static void ath_ani_calibrate(unsigned long data)
 336 {
 337         struct ath_softc *sc;
 338         struct ath_hal *ah;
 339         bool longcal = false;
 340         bool shortcal = false;
 341         bool aniflag = false;
 342         unsigned int timestamp = jiffies_to_msecs(jiffies);
 343         u32 cal_interval;
 344
 345         sc = (struct ath_softc *)data;
 346         ah = sc->sc_ah;
 347
 348         /*
 349         * don't calibrate when we're scanning.
 350         * we are most likely not on our home channel.
 351         */
 352         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 353                 return;
 354
 355         /* Long calibration runs independently of short calibration. */
 356         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 357                 longcal = true;
 358                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 359                 sc->sc_ani.sc_longcal_timer = timestamp;
 360         }
 361
 362         /* Short calibration applies only while sc_caldone is false */
 363         if (!sc->sc_ani.sc_caldone) {
 364                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 365                     ATH_SHORT_CALINTERVAL) {
 366                         shortcal = true;
 367                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 368                         sc->sc_ani.sc_shortcal_timer = timestamp;
 369                         sc->sc_ani.sc_resetcal_timer = timestamp;
 370                 }
 371         } else {
 372                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 373                     ATH_RESTART_CALINTERVAL) {
 374                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 375                                                 &sc->sc_ani.sc_caldone);
 376                         if (sc->sc_ani.sc_caldone)
 377                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 378                 }
 379         }
 380
 381         /* Verify whether we must check ANI */
 382         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 383            ATH_ANI_POLLINTERVAL) {
 384                 aniflag = true;
 385                 sc->sc_ani.sc_checkani_timer = timestamp;
 386         }
 387
 388         /* Skip all processing if there's nothing to do. */
 389         if (longcal || shortcal || aniflag) {
 390                 /* Call ANI routine if necessary */
 391                 if (aniflag)
 392                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 393                                              ah->ah_curchan);
 394
 395                 /* Perform calibration if necessary */
 396                 if (longcal || shortcal) {
 397                         bool iscaldone = false;
 398
 399                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 400                                                sc->sc_rx_chainmask, longcal,
 401                                                &iscaldone)) {
 402                                 if (longcal)
 403                                         sc->sc_ani.sc_noise_floor =
 404                                                 ath9k_hw_getchan_noise(ah,
 405                                                                ah->ah_curchan);
 406
 407                                 DPRINTF(sc, ATH_DBG_ANI,
 408                                         "calibrate chan %u/%x nf: %d\n",
 409                                         ah->ah_curchan->channel,
 410                                         ah->ah_curchan->channelFlags,
 411                                         sc->sc_ani.sc_noise_floor);
 412                         } else {
 413                                 DPRINTF(sc, ATH_DBG_ANY,
 414                                         "calibrate chan %u/%x failed\n",
 415                                         ah->ah_curchan->channel,
 416                                         ah->ah_curchan->channelFlags);
 417                         }
 418                         sc->sc_ani.sc_caldone = iscaldone;
 419                 }
 420         }
 421
 422         /*
 423         * Set timer interval based on previous results.
 424         * The interval must be the shortest necessary to satisfy ANI,
 425         * short calibration and long calibration.
 426         */
 427         cal_interval = ATH_LONG_CALINTERVAL;
 428         if (sc->sc_ah->ah_config.enable_ani)
 429                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 430         if (!sc->sc_ani.sc_caldone)
 431                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 432
 433         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 434 }
 435
 436 /*
 437  * Update tx/rx chainmask. For legacy association,
 438  * hard code chainmask to 1x1, for 11n association, use
 439  * the chainmask configuration.
 440  */
 441 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 442 {
 443         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 444         if (is_ht) {
 445                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 446                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 447         } else {
 448                 sc->sc_tx_chainmask = 1;
 449                 sc->sc_rx_chainmask = 1;
 450         }
 451
 452         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 453                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 454 }
 455
 456 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 457 {
 458         struct ath_node *an;
 459
 460         an = (struct ath_node *)sta->drv_priv;
 461
 462         if (sc->sc_flags & SC_OP_TXAGGR)
 463                 ath_tx_node_init(sc, an);
 464
 465         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 466                              sta->ht_cap.ampdu_factor);
 467         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 468 }
 469
 470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 471 {
 472         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 473
 474         if (sc->sc_flags & SC_OP_TXAGGR)
 475                 ath_tx_node_cleanup(sc, an);
 476 }
 477
 478 static void ath9k_tasklet(unsigned long data)
 479 {
 480         struct ath_softc *sc = (struct ath_softc *)data;
 481         u32 status = sc->sc_intrstatus;
 482
 483         if (status & ATH9K_INT_FATAL) {
 484                 /* need a chip reset */
 485                 ath_reset(sc, false);
 486                 return;
 487         } else {
 488
 489                 if (status &
 490                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 491                         spin_lock_bh(&sc->rx.rxflushlock);
 492                         ath_rx_tasklet(sc, 0);
 493                         spin_unlock_bh(&sc->rx.rxflushlock);
 494                 }
 495                 /* XXX: optimize this */
 496                 if (status & ATH9K_INT_TX)
 497                         ath_tx_tasklet(sc);
 498         }
 499
 500         /* re-enable hardware interrupt */
 501         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 502 }
 503
 504 static irqreturn_t ath_isr(int irq, void *dev)
 505 {
 506         struct ath_softc *sc = dev;
 507         struct ath_hal *ah = sc->sc_ah;
 508         enum ath9k_int status;
 509         bool sched = false;
 510
 511         do {
 512                 if (sc->sc_flags & SC_OP_INVALID) {
 513                         /*
 514                          * The hardware is not ready/present, don't
 515                          * touch anything. Note this can happen early
 516                          * on if the IRQ is shared.
 517                          */
 518                         return IRQ_NONE;
 519                 }
 520                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 521                         return IRQ_NONE;
 522                 }
 523
 524                 /*
 525                  * Figure out the reason(s) for the interrupt.  Note
 526                  * that the hal returns a pseudo-ISR that may include
 527                  * bits we haven't explicitly enabled so we mask the
 528                  * value to insure we only process bits we requested.
 529                  */
 530                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 531
 532                 status &= sc->sc_imask; /* discard unasked-for bits */
 533
 534                 /*
 535                  * If there are no status bits set, then this interrupt was not
 536                  * for me (should have been caught above).
 537                  */
 538                 if (!status)
 539                         return IRQ_NONE;
 540
 541                 sc->sc_intrstatus = status;
 542
 543                 if (status & ATH9K_INT_FATAL) {
 544                         /* need a chip reset */
 545                         sched = true;
 546                 } else if (status & ATH9K_INT_RXORN) {
 547                         /* need a chip reset */
 548                         sched = true;
 549                 } else {
 550                         if (status & ATH9K_INT_SWBA) {
 551                                 /* schedule a tasklet for beacon handling */
 552                                 tasklet_schedule(&sc->bcon_tasklet);
 553                         }
 554                         if (status & ATH9K_INT_RXEOL) {
 555                                 /*
 556                                  * NB: the hardware should re-read the link when
 557                                  *     RXE bit is written, but it doesn't work
 558                                  *     at least on older hardware revs.
 559                                  */
 560                                 sched = true;
 561                         }
 562
 563                         if (status & ATH9K_INT_TXURN)
 564                                 /* bump tx trigger level */
 565                                 ath9k_hw_updatetxtriglevel(ah, true);
 566                         /* XXX: optimize this */
 567                         if (status & ATH9K_INT_RX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_TX)
 570                                 sched = true;
 571                         if (status & ATH9K_INT_BMISS)
 572                                 sched = true;
 573                         /* carrier sense timeout */
 574                         if (status & ATH9K_INT_CST)
 575                                 sched = true;
 576                         if (status & ATH9K_INT_MIB) {
 577                                 /*
 578                                  * Disable interrupts until we service the MIB
 579                                  * interrupt; otherwise it will continue to
 580                                  * fire.
 581                                  */
 582                                 ath9k_hw_set_interrupts(ah, 0);
 583                                 /*
 584                                  * Let the hal handle the event. We assume
 585                                  * it will clear whatever condition caused
 586                                  * the interrupt.
 587                                  */
 588                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 589                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 590                         }
 591                         if (status & ATH9K_INT_TIM_TIMER) {
 592                                 if (!(ah->ah_caps.hw_caps &
 593                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 594                                         /* Clear RxAbort bit so that we can
 595                                          * receive frames */
 596                                         ath9k_hw_setrxabort(ah, 0);
 597                                         sched = true;
 598                                 }
 599                         }
 600                 }
 601         } while (0);
 602
 603         ath_debug_stat_interrupt(sc, status);
 604
 605         if (sched) {
 606                 /* turn off every interrupt except SWBA */
 607                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 608                 tasklet_schedule(&sc->intr_tq);
 609         }
 610
 611         return IRQ_HANDLED;
 612 }
 613
 614 static int ath_get_channel(struct ath_softc *sc,
 615                            struct ieee80211_channel *chan)
 616 {
 617         int i;
 618
 619         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 620                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 621                         return i;
 622         }
 623
 624         return -1;
 625 }
 626
 627 static u32 ath_get_extchanmode(struct ath_softc *sc,
 628                                struct ieee80211_channel *chan,
 629                                enum nl80211_channel_type channel_type)
 630 {
 631         u32 chanmode = 0;
 632
 633         switch (chan->band) {
 634         case IEEE80211_BAND_2GHZ:
 635                 switch(channel_type) {
 636                 case NL80211_CHAN_NO_HT:
 637                 case NL80211_CHAN_HT20:
 638                         chanmode = CHANNEL_G_HT20;
 639                         break;
 640                 case NL80211_CHAN_HT40PLUS:
 641                         chanmode = CHANNEL_G_HT40PLUS;
 642                         break;
 643                 case NL80211_CHAN_HT40MINUS:
 644                         chanmode = CHANNEL_G_HT40MINUS;
 645                         break;
 646                 }
 647                 break;
 648         case IEEE80211_BAND_5GHZ:
 649                 switch(channel_type) {
 650                 case NL80211_CHAN_NO_HT:
 651                 case NL80211_CHAN_HT20:
 652                         chanmode = CHANNEL_A_HT20;
 653                         break;
 654                 case NL80211_CHAN_HT40PLUS:
 655                         chanmode = CHANNEL_A_HT40PLUS;
 656                         break;
 657                 case NL80211_CHAN_HT40MINUS:
 658                         chanmode = CHANNEL_A_HT40MINUS;
 659                         break;
 660                 }
 661                 break;
 662         default:
 663                 break;
 664         }
 665
 666         return chanmode;
 667 }
 668
 669 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 670                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 671 {
 672         bool status;
 673
 674         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 675                 keyix, hk, mac, false);
 676
 677         return status != false;
 678 }
 679
 680 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 681                            struct ath9k_keyval *hk,
 682                            const u8 *addr)
 683 {
 684         const u8 *key_rxmic;
 685         const u8 *key_txmic;
 686
 687         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 688         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 689
 690         if (addr == NULL) {
 691                 /* Group key installation */
 692                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 693                 return ath_keyset(sc, keyix, hk, addr);
 694         }
 695         if (!sc->sc_splitmic) {
 696                 /*
 697                  * data key goes at first index,
 698                  * the hal handles the MIC keys at index+64.
 699                  */
 700                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 701                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 702                 return ath_keyset(sc, keyix, hk, addr);
 703         }
 704         /*
 705          * TX key goes at first index, RX key at +32.
 706          * The hal handles the MIC keys at index+64.
 707          */
 708         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 709         if (!ath_keyset(sc, keyix, hk, NULL)) {
 710                 /* Txmic entry failed. No need to proceed further */
 711                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 712                         "Setting TX MIC Key Failed\n");
 713                 return 0;
 714         }
 715
 716         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 717         /* XXX delete tx key on failure? */
 718         return ath_keyset(sc, keyix + 32, hk, addr);
 719 }
 720
 721 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 722 {
 723         int i;
 724
 725         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 726                 if (test_bit(i, sc->sc_keymap) ||
 727                     test_bit(i + 64, sc->sc_keymap))
 728                         continue; /* At least one part of TKIP key allocated */
 729                 if (sc->sc_splitmic &&
 730                     (test_bit(i + 32, sc->sc_keymap) ||
 731                      test_bit(i + 64 + 32, sc->sc_keymap)))
 732                         continue; /* At least one part of TKIP key allocated */
 733
 734                 /* Found a free slot for a TKIP key */
 735                 return i;
 736         }
 737         return -1;
 738 }
 739
 740 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 741 {
 742         int i;
 743
 744         /* First, try to find slots that would not be available for TKIP. */
 745         if (sc->sc_splitmic) {
 746                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 747                         if (!test_bit(i, sc->sc_keymap) &&
 748                             (test_bit(i + 32, sc->sc_keymap) ||
 749                              test_bit(i + 64, sc->sc_keymap) ||
 750                              test_bit(i + 64 + 32, sc->sc_keymap)))
 751                                 return i;
 752                         if (!test_bit(i + 32, sc->sc_keymap) &&
 753                             (test_bit(i, sc->sc_keymap) ||
 754                              test_bit(i + 64, sc->sc_keymap) ||
 755                              test_bit(i + 64 + 32, sc->sc_keymap)))
 756                                 return i + 32;
 757                         if (!test_bit(i + 64, sc->sc_keymap) &&
 758                             (test_bit(i , sc->sc_keymap) ||
 759                              test_bit(i + 32, sc->sc_keymap) ||
 760                              test_bit(i + 64 + 32, sc->sc_keymap)))
 761                                 return i + 64;
 762                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 763                             (test_bit(i, sc->sc_keymap) ||
 764                              test_bit(i + 32, sc->sc_keymap) ||
 765                              test_bit(i + 64, sc->sc_keymap)))
 766                                 return i + 64 + 32;
 767                 }
 768         } else {
 769                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 770                         if (!test_bit(i, sc->sc_keymap) &&
 771                             test_bit(i + 64, sc->sc_keymap))
 772                                 return i;
 773                         if (test_bit(i, sc->sc_keymap) &&
 774                             !test_bit(i + 64, sc->sc_keymap))
 775                                 return i + 64;
 776                 }
 777         }
 778
 779         /* No partially used TKIP slots, pick any available slot */
 780         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 781                 /* Do not allow slots that could be needed for TKIP group keys
 782                  * to be used. This limitation could be removed if we know that
 783                  * TKIP will not be used. */
 784                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 785                         continue;
 786                 if (sc->sc_splitmic) {
 787                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 788                                 continue;
 789                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 790                                 continue;
 791                 }
 792
 793                 if (!test_bit(i, sc->sc_keymap))
 794                         return i; /* Found a free slot for a key */
 795         }
 796
 797         /* No free slot found */
 798         return -1;
 799 }
 800
 801 static int ath_key_config(struct ath_softc *sc,
 802                           const u8 *addr,
 803                           struct ieee80211_key_conf *key)
 804 {
 805         struct ath9k_keyval hk;
 806         const u8 *mac = NULL;
 807         int ret = 0;
 808         int idx;
 809
 810         memset(&hk, 0, sizeof(hk));
 811
 812         switch (key->alg) {
 813         case ALG_WEP:
 814                 hk.kv_type = ATH9K_CIPHER_WEP;
 815                 break;
 816         case ALG_TKIP:
 817                 hk.kv_type = ATH9K_CIPHER_TKIP;
 818                 break;
 819         case ALG_CCMP:
 820                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 821                 break;
 822         default:
 823                 return -EINVAL;
 824         }
 825
 826         hk.kv_len = key->keylen;
 827         memcpy(hk.kv_val, key->key, key->keylen);
 828
 829         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 830                 /* For now, use the default keys for broadcast keys. This may
 831                  * need to change with virtual interfaces. */
 832                 idx = key->keyidx;
 833         } else if (key->keyidx) {
 834                 struct ieee80211_vif *vif;
 835
 836                 mac = addr;
 837                 vif = sc->sc_vaps[0];
 838                 if (vif->type != NL80211_IFTYPE_AP) {
 839                         /* Only keyidx 0 should be used with unicast key, but
 840                          * allow this for client mode for now. */
 841                         idx = key->keyidx;
 842                 } else
 843                         return -EIO;
 844         } else {
 845                 mac = addr;
 846                 if (key->alg == ALG_TKIP)
 847                         idx = ath_reserve_key_cache_slot_tkip(sc);
 848                 else
 849                         idx = ath_reserve_key_cache_slot(sc);
 850                 if (idx < 0)
 851                         return -EIO; /* no free key cache entries */
 852         }
 853
 854         if (key->alg == ALG_TKIP)
 855                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 856         else
 857                 ret = ath_keyset(sc, idx, &hk, mac);
 858
 859         if (!ret)
 860                 return -EIO;
 861
 862         set_bit(idx, sc->sc_keymap);
 863         if (key->alg == ALG_TKIP) {
 864                 set_bit(idx + 64, sc->sc_keymap);
 865                 if (sc->sc_splitmic) {
 866                         set_bit(idx + 32, sc->sc_keymap);
 867                         set_bit(idx + 64 + 32, sc->sc_keymap);
 868                 }
 869         }
 870
 871         return idx;
 872 }
 873
 874 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 875 {
 876         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 877         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 878                 return;
 879
 880         clear_bit(key->hw_key_idx, sc->sc_keymap);
 881         if (key->alg != ALG_TKIP)
 882                 return;
 883
 884         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 885         if (sc->sc_splitmic) {
 886                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 887                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 888         }
 889 }
 890
 891 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 892 {
 893 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 894 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 895
 896         ht_info->ht_supported = true;
 897         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 898                        IEEE80211_HT_CAP_SM_PS |
 899                        IEEE80211_HT_CAP_SGI_40 |
 900                        IEEE80211_HT_CAP_DSSSCCK40;
 901
 902         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 903         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 904         /* set up supported mcs set */
 905         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 906         ht_info->mcs.rx_mask[0] = 0xff;
 907         ht_info->mcs.rx_mask[1] = 0xff;
 908         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 909 }
 910
 911 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 912                                  struct ieee80211_vif *vif,
 913                                  struct ieee80211_bss_conf *bss_conf)
 914 {
 915         struct ath_vap *avp = (void *)vif->drv_priv;
 916
 917         if (bss_conf->assoc) {
 918                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 919                         bss_conf->aid, sc->sc_curbssid);
 920
 921                 /* New association, store aid */
 922                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 923                         sc->sc_curaid = bss_conf->aid;
 924                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 925                                                sc->sc_curaid);
 926                 }
 927
 928                 /* Configure the beacon */
 929                 ath_beacon_config(sc, 0);
 930                 sc->sc_flags |= SC_OP_BEACONS;
 931
 932                 /* Reset rssi stats */
 933                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 934                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 935                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 936                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 937
 938                 /* Start ANI */
 939                 mod_timer(&sc->sc_ani.timer,
 940                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 941
 942         } else {
 943                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 944                 sc->sc_curaid = 0;
 945         }
 946 }
 947
 948 /********************************/
 949 /*       LED functions          */
 950 /********************************/
 951
 952 static void ath_led_brightness(struct led_classdev *led_cdev,
 953                                enum led_brightness brightness)
 954 {
 955         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 956         struct ath_softc *sc = led->sc;
 957
 958         switch (brightness) {
 959         case LED_OFF:
 960                 if (led->led_type == ATH_LED_ASSOC ||
 961                     led->led_type == ATH_LED_RADIO)
 962                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 963                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 964                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 965                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 966                 break;
 967         case LED_FULL:
 968                 if (led->led_type == ATH_LED_ASSOC)
 969                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 970                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 971                 break;
 972         default:
 973                 break;
 974         }
 975 }
 976
 977 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 978                             char *trigger)
 979 {
 980         int ret;
 981
 982         led->sc = sc;
 983         led->led_cdev.name = led->name;
 984         led->led_cdev.default_trigger = trigger;
 985         led->led_cdev.brightness_set = ath_led_brightness;
 986
 987         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 988         if (ret)
 989                 DPRINTF(sc, ATH_DBG_FATAL,
 990                         "Failed to register led:%s", led->name);
 991         else
 992                 led->registered = 1;
 993         return ret;
 994 }
 995
 996 static void ath_unregister_led(struct ath_led *led)
 997 {
 998         if (led->registered) {
 999                 led_classdev_unregister(&led->led_cdev);
1000                 led->registered = 0;
1001         }
1002 }
1003
1004 static void ath_deinit_leds(struct ath_softc *sc)
1005 {
1006         ath_unregister_led(&sc->assoc_led);
1007         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1008         ath_unregister_led(&sc->tx_led);
1009         ath_unregister_led(&sc->rx_led);
1010         ath_unregister_led(&sc->radio_led);
1011         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1012 }
1013
1014 static void ath_init_leds(struct ath_softc *sc)
1015 {
1016         char *trigger;
1017         int ret;
1018
1019         /* Configure gpio 1 for output */
1020         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1021                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1022         /* LED off, active low */
1023         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1024
1025         trigger = ieee80211_get_radio_led_name(sc->hw);
1026         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1027                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1028         ret = ath_register_led(sc, &sc->radio_led, trigger);
1029         sc->radio_led.led_type = ATH_LED_RADIO;
1030         if (ret)
1031                 goto fail;
1032
1033         trigger = ieee80211_get_assoc_led_name(sc->hw);
1034         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1035                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1036         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1037         sc->assoc_led.led_type = ATH_LED_ASSOC;
1038         if (ret)
1039                 goto fail;
1040
1041         trigger = ieee80211_get_tx_led_name(sc->hw);
1042         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1043                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1044         ret = ath_register_led(sc, &sc->tx_led, trigger);
1045         sc->tx_led.led_type = ATH_LED_TX;
1046         if (ret)
1047                 goto fail;
1048
1049         trigger = ieee80211_get_rx_led_name(sc->hw);
1050         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1051                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1052         ret = ath_register_led(sc, &sc->rx_led, trigger);
1053         sc->rx_led.led_type = ATH_LED_RX;
1054         if (ret)
1055                 goto fail;
1056
1057         return;
1058
1059 fail:
1060         ath_deinit_leds(sc);
1061 }
1062
1063 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1064
1065 /*******************/
1066 /*      Rfkill     */
1067 /*******************/
1068
1069 static void ath_radio_enable(struct ath_softc *sc)
1070 {
1071         struct ath_hal *ah = sc->sc_ah;
1072         int status;
1073
1074         spin_lock_bh(&sc->sc_resetlock);
1075         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1076                             sc->tx_chan_width,
1077                             sc->sc_tx_chainmask,
1078                             sc->sc_rx_chainmask,
1079                             sc->sc_ht_extprotspacing,
1080                             false, &status)) {
1081                 DPRINTF(sc, ATH_DBG_FATAL,
1082                         "Unable to reset channel %u (%uMhz) "
1083                         "flags 0x%x hal status %u\n",
1084                         ath9k_hw_mhz2ieee(ah,
1085                                           ah->ah_curchan->channel,
1086                                           ah->ah_curchan->channelFlags),
1087                         ah->ah_curchan->channel,
1088                         ah->ah_curchan->channelFlags, status);
1089         }
1090         spin_unlock_bh(&sc->sc_resetlock);
1091
1092         ath_update_txpow(sc);
1093         if (ath_startrecv(sc) != 0) {
1094                 DPRINTF(sc, ATH_DBG_FATAL,
1095                         "Unable to restart recv logic\n");
1096                 return;
1097         }
1098
1099         if (sc->sc_flags & SC_OP_BEACONS)
1100                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1101
1102         /* Re-Enable  interrupts */
1103         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1104
1105         /* Enable LED */
1106         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1107                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1108         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1109
1110         ieee80211_wake_queues(sc->hw);
1111 }
1112
1113 static void ath_radio_disable(struct ath_softc *sc)
1114 {
1115         struct ath_hal *ah = sc->sc_ah;
1116         int status;
1117
1118
1119         ieee80211_stop_queues(sc->hw);
1120
1121         /* Disable LED */
1122         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1123         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1124
1125         /* Disable interrupts */
1126         ath9k_hw_set_interrupts(ah, 0);
1127
1128         ath_draintxq(sc, false);        /* clear pending tx frames */
1129         ath_stoprecv(sc);               /* turn off frame recv */
1130         ath_flushrecv(sc);              /* flush recv queue */
1131
1132         spin_lock_bh(&sc->sc_resetlock);
1133         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1134                             sc->tx_chan_width,
1135                             sc->sc_tx_chainmask,
1136                             sc->sc_rx_chainmask,
1137                             sc->sc_ht_extprotspacing,
1138                             false, &status)) {
1139                 DPRINTF(sc, ATH_DBG_FATAL,
1140                         "Unable to reset channel %u (%uMhz) "
1141                         "flags 0x%x hal status %u\n",
1142                         ath9k_hw_mhz2ieee(ah,
1143                                 ah->ah_curchan->channel,
1144                                 ah->ah_curchan->channelFlags),
1145                         ah->ah_curchan->channel,
1146                         ah->ah_curchan->channelFlags, status);
1147         }
1148         spin_unlock_bh(&sc->sc_resetlock);
1149
1150         ath9k_hw_phy_disable(ah);
1151         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1152 }
1153
1154 static bool ath_is_rfkill_set(struct ath_softc *sc)
1155 {
1156         struct ath_hal *ah = sc->sc_ah;
1157
1158         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1159                                   ah->ah_rfkill_polarity;
1160 }
1161
1162 /* h/w rfkill poll function */
1163 static void ath_rfkill_poll(struct work_struct *work)
1164 {
1165         struct ath_softc *sc = container_of(work, struct ath_softc,
1166                                             rf_kill.rfkill_poll.work);
1167         bool radio_on;
1168
1169         if (sc->sc_flags & SC_OP_INVALID)
1170                 return;
1171
1172         radio_on = !ath_is_rfkill_set(sc);
1173
1174         /*
1175          * enable/disable radio only when there is a
1176          * state change in RF switch
1177          */
1178         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1179                 enum rfkill_state state;
1180
1181                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1182                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1183                                 : RFKILL_STATE_HARD_BLOCKED;
1184                 } else if (radio_on) {
1185                         ath_radio_enable(sc);
1186                         state = RFKILL_STATE_UNBLOCKED;
1187                 } else {
1188                         ath_radio_disable(sc);
1189                         state = RFKILL_STATE_HARD_BLOCKED;
1190                 }
1191
1192                 if (state == RFKILL_STATE_HARD_BLOCKED)
1193                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1194                 else
1195                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1196
1197                 rfkill_force_state(sc->rf_kill.rfkill, state);
1198         }
1199
1200         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1201                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1202 }
1203
1204 /* s/w rfkill handler */
1205 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1206 {
1207         struct ath_softc *sc = data;
1208
1209         switch (state) {
1210         case RFKILL_STATE_SOFT_BLOCKED:
1211                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1212                     SC_OP_RFKILL_SW_BLOCKED)))
1213                         ath_radio_disable(sc);
1214                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1215                 return 0;
1216         case RFKILL_STATE_UNBLOCKED:
1217                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1218                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1219                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1220                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1221                                         "radio as it is disabled by h/w\n");
1222                                 return -EPERM;
1223                         }
1224                         ath_radio_enable(sc);
1225                 }
1226                 return 0;
1227         default:
1228                 return -EINVAL;
1229         }
1230 }
1231
1232 /* Init s/w rfkill */
1233 static int ath_init_sw_rfkill(struct ath_softc *sc)
1234 {
1235         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1236                                              RFKILL_TYPE_WLAN);
1237         if (!sc->rf_kill.rfkill) {
1238                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1239                 return -ENOMEM;
1240         }
1241
1242         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1243                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1244         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1245         sc->rf_kill.rfkill->data = sc;
1246         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1247         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1248         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1249
1250         return 0;
1251 }
1252
1253 /* Deinitialize rfkill */
1254 static void ath_deinit_rfkill(struct ath_softc *sc)
1255 {
1256         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1257                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1258
1259         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1260                 rfkill_unregister(sc->rf_kill.rfkill);
1261                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1262                 sc->rf_kill.rfkill = NULL;
1263         }
1264 }
1265
1266 static int ath_start_rfkill_poll(struct ath_softc *sc)
1267 {
1268         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1269                 queue_delayed_work(sc->hw->workqueue,
1270                                    &sc->rf_kill.rfkill_poll, 0);
1271
1272         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1273                 if (rfkill_register(sc->rf_kill.rfkill)) {
1274                         DPRINTF(sc, ATH_DBG_FATAL,
1275                                 "Unable to register rfkill\n");
1276                         rfkill_free(sc->rf_kill.rfkill);
1277
1278                         /* Deinitialize the device */
1279                         ath_detach(sc);
1280                         if (sc->pdev->irq)
1281                                 free_irq(sc->pdev->irq, sc);
1282                         pci_iounmap(sc->pdev, sc->mem);
1283                         pci_release_region(sc->pdev, 0);
1284                         pci_disable_device(sc->pdev);
1285                         ieee80211_free_hw(sc->hw);
1286                         return -EIO;
1287                 } else {
1288                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1289                 }
1290         }
1291
1292         return 0;
1293 }
1294 #endif /* CONFIG_RFKILL */
1295
1296 static void ath_detach(struct ath_softc *sc)
1297 {
1298         struct ieee80211_hw *hw = sc->hw;
1299         int i = 0;
1300
1301         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1302
1303 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1304         ath_deinit_rfkill(sc);
1305 #endif
1306         ath_deinit_leds(sc);
1307
1308         ieee80211_unregister_hw(hw);
1309         ath_rx_cleanup(sc);
1310         ath_tx_cleanup(sc);
1311
1312         tasklet_kill(&sc->intr_tq);
1313         tasklet_kill(&sc->bcon_tasklet);
1314
1315         if (!(sc->sc_flags & SC_OP_INVALID))
1316                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1317
1318         /* cleanup tx queues */
1319         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1320                 if (ATH_TXQ_SETUP(sc, i))
1321                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1322
1323         ath9k_hw_detach(sc->sc_ah);
1324         ath9k_exit_debug(sc);
1325 }
1326
1327 static int ath_init(u16 devid, struct ath_softc *sc)
1328 {
1329         struct ath_hal *ah = NULL;
1330         int status;
1331         int error = 0, i;
1332         int csz = 0;
1333
1334         /* XXX: hardware will not be ready until ath_open() being called */
1335         sc->sc_flags |= SC_OP_INVALID;
1336
1337         if (ath9k_init_debug(sc) < 0)
1338                 printk(KERN_ERR "Unable to create debugfs files\n");
1339
1340         spin_lock_init(&sc->sc_resetlock);
1341         mutex_init(&sc->mutex);
1342         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1343         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1344                      (unsigned long)sc);
1345
1346         /*
1347          * Cache line size is used to size and align various
1348          * structures used to communicate with the hardware.
1349          */
1350         bus_read_cachesize(sc, &csz);
1351         /* XXX assert csz is non-zero */
1352         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1353
1354         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1355         if (ah == NULL) {
1356                 DPRINTF(sc, ATH_DBG_FATAL,
1357                         "Unable to attach hardware; HAL status %u\n", status);
1358                 error = -ENXIO;
1359                 goto bad;
1360         }
1361         sc->sc_ah = ah;
1362
1363         /* Get the hardware key cache size. */
1364         sc->sc_keymax = ah->ah_caps.keycache_size;
1365         if (sc->sc_keymax > ATH_KEYMAX) {
1366                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1367                         "Warning, using only %u entries in %u key cache\n",
1368                         ATH_KEYMAX, sc->sc_keymax);
1369                 sc->sc_keymax = ATH_KEYMAX;
1370         }
1371
1372         /*
1373          * Reset the key cache since some parts do not
1374          * reset the contents on initial power up.
1375          */
1376         for (i = 0; i < sc->sc_keymax; i++)
1377                 ath9k_hw_keyreset(ah, (u16) i);
1378
1379         /* Collect the channel list using the default country code */
1380
1381         error = ath_setup_channels(sc);
1382         if (error)
1383                 goto bad;
1384
1385         /* default to MONITOR mode */
1386         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1387
1388
1389         /* Setup rate tables */
1390
1391         ath_rate_attach(sc);
1392         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1393         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1394
1395         /*
1396          * Allocate hardware transmit queues: one queue for
1397          * beacon frames and one data queue for each QoS
1398          * priority.  Note that the hal handles reseting
1399          * these queues at the needed time.
1400          */
1401         sc->beacon.beaconq = ath_beaconq_setup(ah);
1402         if (sc->beacon.beaconq == -1) {
1403                 DPRINTF(sc, ATH_DBG_FATAL,
1404                         "Unable to setup a beacon xmit queue\n");
1405                 error = -EIO;
1406                 goto bad2;
1407         }
1408         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1409         if (sc->beacon.cabq == NULL) {
1410                 DPRINTF(sc, ATH_DBG_FATAL,
1411                         "Unable to setup CAB xmit queue\n");
1412                 error = -EIO;
1413                 goto bad2;
1414         }
1415
1416         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1417         ath_cabq_update(sc);
1418
1419         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1420                 sc->tx.hwq_map[i] = -1;
1421
1422         /* Setup data queues */
1423         /* NB: ensure BK queue is the lowest priority h/w queue */
1424         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1425                 DPRINTF(sc, ATH_DBG_FATAL,
1426                         "Unable to setup xmit queue for BK traffic\n");
1427                 error = -EIO;
1428                 goto bad2;
1429         }
1430
1431         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1432                 DPRINTF(sc, ATH_DBG_FATAL,
1433                         "Unable to setup xmit queue for BE traffic\n");
1434                 error = -EIO;
1435                 goto bad2;
1436         }
1437         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1438                 DPRINTF(sc, ATH_DBG_FATAL,
1439                         "Unable to setup xmit queue for VI traffic\n");
1440                 error = -EIO;
1441                 goto bad2;
1442         }
1443         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1444                 DPRINTF(sc, ATH_DBG_FATAL,
1445                         "Unable to setup xmit queue for VO traffic\n");
1446                 error = -EIO;
1447                 goto bad2;
1448         }
1449
1450         /* Initializes the noise floor to a reasonable default value.
1451          * Later on this will be updated during ANI processing. */
1452
1453         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1454         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1455
1456         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1457                                    ATH9K_CIPHER_TKIP, NULL)) {
1458                 /*
1459                  * Whether we should enable h/w TKIP MIC.
1460                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1461                  * report WMM capable, so it's always safe to turn on
1462                  * TKIP MIC in this case.
1463                  */
1464                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1465                                        0, 1, NULL);
1466         }
1467
1468         /*
1469          * Check whether the separate key cache entries
1470          * are required to handle both tx+rx MIC keys.
1471          * With split mic keys the number of stations is limited
1472          * to 27 otherwise 59.
1473          */
1474         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1475                                    ATH9K_CIPHER_TKIP, NULL)
1476             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1477                                       ATH9K_CIPHER_MIC, NULL)
1478             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1479                                       0, NULL))
1480                 sc->sc_splitmic = 1;
1481
1482         /* turn on mcast key search if possible */
1483         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1484                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1485                                              1, NULL);
1486
1487         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1488         sc->sc_config.txpowlimit_override = 0;
1489
1490         /* 11n Capabilities */
1491         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1492                 sc->sc_flags |= SC_OP_TXAGGR;
1493                 sc->sc_flags |= SC_OP_RXAGGR;
1494         }
1495
1496         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1497         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1498
1499         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1500         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1501
1502         ath9k_hw_getmac(ah, sc->sc_myaddr);
1503         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1504                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1505                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1506                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1507         }
1508
1509         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1510
1511         /* initialize beacon slots */
1512         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1513                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1514
1515         /* save MISC configurations */
1516         sc->sc_config.swBeaconProcess = 1;
1517
1518         /* setup channels and rates */
1519
1520         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1521                 sc->channels[IEEE80211_BAND_2GHZ];
1522         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1523                 sc->rates[IEEE80211_BAND_2GHZ];
1524         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1525
1526         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1527                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1528                         sc->channels[IEEE80211_BAND_5GHZ];
1529                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1530                         sc->rates[IEEE80211_BAND_5GHZ];
1531                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1532         }
1533
1534         return 0;
1535 bad2:
1536         /* cleanup tx queues */
1537         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1538                 if (ATH_TXQ_SETUP(sc, i))
1539                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1540 bad:
1541         if (ah)
1542                 ath9k_hw_detach(ah);
1543
1544         return error;
1545 }
1546
1547 static int ath_attach(u16 devid, struct ath_softc *sc)
1548 {
1549         struct ieee80211_hw *hw = sc->hw;
1550         int error = 0;
1551
1552         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1553
1554         error = ath_init(devid, sc);
1555         if (error != 0)
1556                 return error;
1557
1558         /* get mac address from hardware and set in mac80211 */
1559
1560         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1561
1562         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1563                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1564                 IEEE80211_HW_SIGNAL_DBM |
1565                 IEEE80211_HW_AMPDU_AGGREGATION;
1566
1567         hw->wiphy->interface_modes =
1568                 BIT(NL80211_IFTYPE_AP) |
1569                 BIT(NL80211_IFTYPE_STATION) |
1570                 BIT(NL80211_IFTYPE_ADHOC);
1571
1572         hw->queues = 4;
1573         hw->max_rates = 4;
1574         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1575         hw->sta_data_size = sizeof(struct ath_node);
1576         hw->vif_data_size = sizeof(struct ath_vap);
1577
1578         hw->rate_control_algorithm = "ath9k_rate_control";
1579
1580         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1581                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1582                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1583                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1584         }
1585
1586         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1587         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1588                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1589                         &sc->sbands[IEEE80211_BAND_5GHZ];
1590
1591         /* initialize tx/rx engine */
1592         error = ath_tx_init(sc, ATH_TXBUF);
1593         if (error != 0)
1594                 goto detach;
1595
1596         error = ath_rx_init(sc, ATH_RXBUF);
1597         if (error != 0)
1598                 goto detach;
1599
1600 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1601         /* Initialze h/w Rfkill */
1602         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1603                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1604
1605         /* Initialize s/w rfkill */
1606         if (ath_init_sw_rfkill(sc))
1607                 goto detach;
1608 #endif
1609
1610         error = ieee80211_register_hw(hw);
1611
1612         /* Initialize LED control */
1613         ath_init_leds(sc);
1614
1615         return 0;
1616 detach:
1617         ath_detach(sc);
1618         return error;
1619 }
1620
1621 int ath_reset(struct ath_softc *sc, bool retry_tx)
1622 {
1623         struct ath_hal *ah = sc->sc_ah;
1624         struct ieee80211_hw *hw = sc->hw;
1625         int status;
1626         int error = 0;
1627
1628         ath9k_hw_set_interrupts(ah, 0);
1629         ath_draintxq(sc, retry_tx);
1630         ath_stoprecv(sc);
1631         ath_flushrecv(sc);
1632
1633         spin_lock_bh(&sc->sc_resetlock);
1634         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1635                             sc->tx_chan_width,
1636                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1637                             sc->sc_ht_extprotspacing, false, &status)) {
1638                 DPRINTF(sc, ATH_DBG_FATAL,
1639                         "Unable to reset hardware; hal status %u\n", status);
1640                 error = -EIO;
1641         }
1642         spin_unlock_bh(&sc->sc_resetlock);
1643
1644         if (ath_startrecv(sc) != 0)
1645                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1646
1647         /*
1648          * We may be doing a reset in response to a request
1649          * that changes the channel so update any state that
1650          * might change as a result.
1651          */
1652         ath_cache_conf_rate(sc, &hw->conf);
1653
1654         ath_update_txpow(sc);
1655
1656         if (sc->sc_flags & SC_OP_BEACONS)
1657                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1658
1659         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1660
1661         if (retry_tx) {
1662                 int i;
1663                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1664                         if (ATH_TXQ_SETUP(sc, i)) {
1665                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1666                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1667                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1668                         }
1669                 }
1670         }
1671
1672         return error;
1673 }
1674
1675 /*
1676  *  This function will allocate both the DMA descriptor structure, and the
1677  *  buffers it contains.  These are used to contain the descriptors used
1678  *  by the system.
1679 */
1680 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1681                       struct list_head *head, const char *name,
1682                       int nbuf, int ndesc)
1683 {
1684 #define DS2PHYS(_dd, _ds)                                               \
1685         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1686 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1687 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1688
1689         struct ath_desc *ds;
1690         struct ath_buf *bf;
1691         int i, bsize, error;
1692
1693         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1694                 name, nbuf, ndesc);
1695
1696         /* ath_desc must be a multiple of DWORDs */
1697         if ((sizeof(struct ath_desc) % 4) != 0) {
1698                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1699                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1700                 error = -ENOMEM;
1701                 goto fail;
1702         }
1703
1704         dd->dd_name = name;
1705         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1706
1707         /*
1708          * Need additional DMA memory because we can't use
1709          * descriptors that cross the 4K page boundary. Assume
1710          * one skipped descriptor per 4K page.
1711          */
1712         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1713                 u32 ndesc_skipped =
1714                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1715                 u32 dma_len;
1716
1717                 while (ndesc_skipped) {
1718                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1719                         dd->dd_desc_len += dma_len;
1720
1721                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1722                 };
1723         }
1724
1725         /* allocate descriptors */
1726         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1727                               dd->dd_desc_len,
1728                               &dd->dd_desc_paddr);
1729         if (dd->dd_desc == NULL) {
1730                 error = -ENOMEM;
1731                 goto fail;
1732         }
1733         ds = dd->dd_desc;
1734         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1735                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1736                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1737
1738         /* allocate buffers */
1739         bsize = sizeof(struct ath_buf) * nbuf;
1740         bf = kmalloc(bsize, GFP_KERNEL);
1741         if (bf == NULL) {
1742                 error = -ENOMEM;
1743                 goto fail2;
1744         }
1745         memset(bf, 0, bsize);
1746         dd->dd_bufptr = bf;
1747
1748         INIT_LIST_HEAD(head);
1749         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1750                 bf->bf_desc = ds;
1751                 bf->bf_daddr = DS2PHYS(dd, ds);
1752
1753                 if (!(sc->sc_ah->ah_caps.hw_caps &
1754                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1755                         /*
1756                          * Skip descriptor addresses which can cause 4KB
1757                          * boundary crossing (addr + length) with a 32 dword
1758                          * descriptor fetch.
1759                          */
1760                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1761                                 ASSERT((caddr_t) bf->bf_desc <
1762                                        ((caddr_t) dd->dd_desc +
1763                                         dd->dd_desc_len));
1764
1765                                 ds += ndesc;
1766                                 bf->bf_desc = ds;
1767                                 bf->bf_daddr = DS2PHYS(dd, ds);
1768                         }
1769                 }
1770                 list_add_tail(&bf->list, head);
1771         }
1772         return 0;
1773 fail2:
1774         pci_free_consistent(sc->pdev,
1775                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1776 fail:
1777         memset(dd, 0, sizeof(*dd));
1778         return error;
1779 #undef ATH_DESC_4KB_BOUND_CHECK
1780 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1781 #undef DS2PHYS
1782 }
1783
1784 void ath_descdma_cleanup(struct ath_softc *sc,
1785                          struct ath_descdma *dd,
1786                          struct list_head *head)
1787 {
1788         pci_free_consistent(sc->pdev,
1789                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1790
1791         INIT_LIST_HEAD(head);
1792         kfree(dd->dd_bufptr);
1793         memset(dd, 0, sizeof(*dd));
1794 }
1795
1796 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1797 {
1798         int qnum;
1799
1800         switch (queue) {
1801         case 0:
1802                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1803                 break;
1804         case 1:
1805                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1806                 break;
1807         case 2:
1808                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1809                 break;
1810         case 3:
1811                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1812                 break;
1813         default:
1814                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1815                 break;
1816         }
1817
1818         return qnum;
1819 }
1820
1821 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1822 {
1823         int qnum;
1824
1825         switch (queue) {
1826         case ATH9K_WME_AC_VO:
1827                 qnum = 0;
1828                 break;
1829         case ATH9K_WME_AC_VI:
1830                 qnum = 1;
1831                 break;
1832         case ATH9K_WME_AC_BE:
1833                 qnum = 2;
1834                 break;
1835         case ATH9K_WME_AC_BK:
1836                 qnum = 3;
1837                 break;
1838         default:
1839                 qnum = -1;
1840                 break;
1841         }
1842
1843         return qnum;
1844 }
1845
1846 /**********************/
1847 /* mac80211 callbacks */
1848 /**********************/
1849
1850 static int ath9k_start(struct ieee80211_hw *hw)
1851 {
1852         struct ath_softc *sc = hw->priv;
1853         struct ieee80211_channel *curchan = hw->conf.channel;
1854         struct ath9k_channel *init_channel;
1855         int error = 0, pos, status;
1856
1857         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1858                 "initial channel: %d MHz\n", curchan->center_freq);
1859
1860         /* setup initial channel */
1861
1862         pos = ath_get_channel(sc, curchan);
1863         if (pos == -1) {
1864                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1865                 error = -EINVAL;
1866                 goto error;
1867         }
1868
1869         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1870         sc->sc_ah->ah_channels[pos].chanmode =
1871                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1872         init_channel = &sc->sc_ah->ah_channels[pos];
1873
1874         /* Reset SERDES registers */
1875         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1876
1877         /*
1878          * The basic interface to setting the hardware in a good
1879          * state is ``reset''.  On return the hardware is known to
1880          * be powered up and with interrupts disabled.  This must
1881          * be followed by initialization of the appropriate bits
1882          * and then setup of the interrupt mask.
1883          */
1884         spin_lock_bh(&sc->sc_resetlock);
1885         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1886                             sc->tx_chan_width,
1887                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1888                             sc->sc_ht_extprotspacing, false, &status)) {
1889                 DPRINTF(sc, ATH_DBG_FATAL,
1890                         "Unable to reset hardware; hal status %u "
1891                         "(freq %u flags 0x%x)\n", status,
1892                         init_channel->channel, init_channel->channelFlags);
1893                 error = -EIO;
1894                 spin_unlock_bh(&sc->sc_resetlock);
1895                 goto error;
1896         }
1897         spin_unlock_bh(&sc->sc_resetlock);
1898
1899         /*
1900          * This is needed only to setup initial state
1901          * but it's best done after a reset.
1902          */
1903         ath_update_txpow(sc);
1904
1905         /*
1906          * Setup the hardware after reset:
1907          * The receive engine is set going.
1908          * Frame transmit is handled entirely
1909          * in the frame output path; there's nothing to do
1910          * here except setup the interrupt mask.
1911          */
1912         if (ath_startrecv(sc) != 0) {
1913                 DPRINTF(sc, ATH_DBG_FATAL,
1914                         "Unable to start recv logic\n");
1915                 error = -EIO;
1916                 goto error;
1917         }
1918
1919         /* Setup our intr mask. */
1920         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1921                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1922                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1923
1924         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1925                 sc->sc_imask |= ATH9K_INT_GTT;
1926
1927         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1928                 sc->sc_imask |= ATH9K_INT_CST;
1929
1930         /*
1931          * Enable MIB interrupts when there are hardware phy counters.
1932          * Note we only do this (at the moment) for station mode.
1933          */
1934         if (ath9k_hw_phycounters(sc->sc_ah) &&
1935             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1936              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1937                 sc->sc_imask |= ATH9K_INT_MIB;
1938         /*
1939          * Some hardware processes the TIM IE and fires an
1940          * interrupt when the TIM bit is set.  For hardware
1941          * that does, if not overridden by configuration,
1942          * enable the TIM interrupt when operating as station.
1943          */
1944         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1945             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1946             !sc->sc_config.swBeaconProcess)
1947                 sc->sc_imask |= ATH9K_INT_TIM;
1948
1949         ath_cache_conf_rate(sc, &hw->conf);
1950
1951         sc->sc_flags &= ~SC_OP_INVALID;
1952
1953         /* Disable BMISS interrupt when we're not associated */
1954         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1955         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1956
1957         ieee80211_wake_queues(sc->hw);
1958
1959 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1960         error = ath_start_rfkill_poll(sc);
1961 #endif
1962
1963 error:
1964         return error;
1965 }
1966
1967 static int ath9k_tx(struct ieee80211_hw *hw,
1968                     struct sk_buff *skb)
1969 {
1970         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1971         struct ath_softc *sc = hw->priv;
1972         struct ath_tx_control txctl;
1973         int hdrlen, padsize;
1974
1975         memset(&txctl, 0, sizeof(struct ath_tx_control));
1976
1977         /*
1978          * As a temporary workaround, assign seq# here; this will likely need
1979          * to be cleaned up to work better with Beacon transmission and virtual
1980          * BSSes.
1981          */
1982         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1983                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1984                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1985                         sc->tx.seq_no += 0x10;
1986                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1987                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1988         }
1989
1990         /* Add the padding after the header if this is not already done */
1991         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1992         if (hdrlen & 3) {
1993                 padsize = hdrlen % 4;
1994                 if (skb_headroom(skb) < padsize)
1995                         return -1;
1996                 skb_push(skb, padsize);
1997                 memmove(skb->data, skb->data + padsize, hdrlen);
1998         }
1999
2000         /* Check if a tx queue is available */
2001
2002         txctl.txq = ath_test_get_txq(sc, skb);
2003         if (!txctl.txq)
2004                 goto exit;
2005
2006         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2007
2008         if (ath_tx_start(sc, skb, &txctl) != 0) {
2009                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2010                 goto exit;
2011         }
2012
2013         return 0;
2014 exit:
2015         dev_kfree_skb_any(skb);
2016         return 0;
2017 }
2018
2019 static void ath9k_stop(struct ieee80211_hw *hw)
2020 {
2021         struct ath_softc *sc = hw->priv;
2022
2023         if (sc->sc_flags & SC_OP_INVALID) {
2024                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2025                 return;
2026         }
2027
2028         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2029
2030         ieee80211_stop_queues(sc->hw);
2031
2032         /* make sure h/w will not generate any interrupt
2033          * before setting the invalid flag. */
2034         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2035
2036         if (!(sc->sc_flags & SC_OP_INVALID)) {
2037                 ath_draintxq(sc, false);
2038                 ath_stoprecv(sc);
2039                 ath9k_hw_phy_disable(sc->sc_ah);
2040         } else
2041                 sc->rx.rxlink = NULL;
2042
2043 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2044         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2045                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2046 #endif
2047         /* disable HAL and put h/w to sleep */
2048         ath9k_hw_disable(sc->sc_ah);
2049         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2050
2051         sc->sc_flags |= SC_OP_INVALID;
2052
2053         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2054 }
2055
2056 static int ath9k_add_interface(struct ieee80211_hw *hw,
2057                                struct ieee80211_if_init_conf *conf)
2058 {
2059         struct ath_softc *sc = hw->priv;
2060         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2061         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2062
2063         /* Support only vap for now */
2064
2065         if (sc->sc_nvaps)
2066                 return -ENOBUFS;
2067
2068         switch (conf->type) {
2069         case NL80211_IFTYPE_STATION:
2070                 ic_opmode = NL80211_IFTYPE_STATION;
2071                 break;
2072         case NL80211_IFTYPE_ADHOC:
2073                 ic_opmode = NL80211_IFTYPE_ADHOC;
2074                 break;
2075         case NL80211_IFTYPE_AP:
2076                 ic_opmode = NL80211_IFTYPE_AP;
2077                 break;
2078         default:
2079                 DPRINTF(sc, ATH_DBG_FATAL,
2080                         "Interface type %d not yet supported\n", conf->type);
2081                 return -EOPNOTSUPP;
2082         }
2083
2084         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2085
2086         /* Set the VAP opmode */
2087         avp->av_opmode = ic_opmode;
2088         avp->av_bslot = -1;
2089
2090         if (ic_opmode == NL80211_IFTYPE_AP)
2091                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2092
2093         sc->sc_vaps[0] = conf->vif;
2094         sc->sc_nvaps++;
2095
2096         /* Set the device opmode */
2097         sc->sc_ah->ah_opmode = ic_opmode;
2098
2099         if (conf->type == NL80211_IFTYPE_AP) {
2100                 /* TODO: is this a suitable place to start ANI for AP mode? */
2101                 /* Start ANI */
2102                 mod_timer(&sc->sc_ani.timer,
2103                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2104         }
2105
2106         return 0;
2107 }
2108
2109 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2110                                    struct ieee80211_if_init_conf *conf)
2111 {
2112         struct ath_softc *sc = hw->priv;
2113         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2114
2115         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2116
2117         /* Stop ANI */
2118         del_timer_sync(&sc->sc_ani.timer);
2119
2120         /* Reclaim beacon resources */
2121         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2122             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2123                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2124                 ath_beacon_return(sc, avp);
2125         }
2126
2127         sc->sc_flags &= ~SC_OP_BEACONS;
2128
2129         sc->sc_vaps[0] = NULL;
2130         sc->sc_nvaps--;
2131 }
2132
2133 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2134 {
2135         struct ath_softc *sc = hw->priv;
2136         struct ieee80211_conf *conf = &hw->conf;
2137
2138         mutex_lock(&sc->mutex);
2139         if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2140                        IEEE80211_CONF_CHANGE_HT)) {
2141                 struct ieee80211_channel *curchan = hw->conf.channel;
2142                 int pos;
2143
2144                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2145                         curchan->center_freq);
2146
2147                 pos = ath_get_channel(sc, curchan);
2148                 if (pos == -1) {
2149                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2150                                 curchan->center_freq);
2151                         mutex_unlock(&sc->mutex);
2152                         return -EINVAL;
2153                 }
2154
2155                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2156                 sc->sc_ah->ah_channels[pos].chanmode =
2157                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2158                         CHANNEL_G : CHANNEL_A;
2159
2160                 if (conf->ht.enabled) {
2161                         if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2162                             conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2163                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2164
2165                         sc->sc_ah->ah_channels[pos].chanmode =
2166                                 ath_get_extchanmode(sc, curchan,
2167                                                     conf->ht.channel_type);
2168                 }
2169
2170                 ath_update_chainmask(sc, conf->ht.enabled);
2171
2172                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2173                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2174                         mutex_unlock(&sc->mutex);
2175                         return -EINVAL;
2176                 }
2177         }
2178
2179         if (changed & IEEE80211_CONF_CHANGE_POWER)
2180                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2181
2182         mutex_unlock(&sc->mutex);
2183         return 0;
2184 }
2185
2186 static int ath9k_config_interface(struct ieee80211_hw *hw,
2187                                   struct ieee80211_vif *vif,
2188                                   struct ieee80211_if_conf *conf)
2189 {
2190         struct ath_softc *sc = hw->priv;
2191         struct ath_hal *ah = sc->sc_ah;
2192         struct ath_vap *avp = (void *)vif->drv_priv;
2193         u32 rfilt = 0;
2194         int error, i;
2195
2196         /* TODO: Need to decide which hw opmode to use for multi-interface
2197          * cases */
2198         if (vif->type == NL80211_IFTYPE_AP &&
2199             ah->ah_opmode != NL80211_IFTYPE_AP) {
2200                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2201                 ath9k_hw_setopmode(ah);
2202                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2203                 /* Request full reset to get hw opmode changed properly */
2204                 sc->sc_flags |= SC_OP_FULL_RESET;
2205         }
2206
2207         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2208             !is_zero_ether_addr(conf->bssid)) {
2209                 switch (vif->type) {
2210                 case NL80211_IFTYPE_STATION:
2211                 case NL80211_IFTYPE_ADHOC:
2212                         /* Set BSSID */
2213                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2214                         sc->sc_curaid = 0;
2215                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2216                                                sc->sc_curaid);
2217
2218                         /* Set aggregation protection mode parameters */
2219                         sc->sc_config.ath_aggr_prot = 0;
2220
2221                         DPRINTF(sc, ATH_DBG_CONFIG,
2222                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2223                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2224
2225                         /* need to reconfigure the beacon */
2226                         sc->sc_flags &= ~SC_OP_BEACONS ;
2227
2228                         break;
2229                 default:
2230                         break;
2231                 }
2232         }
2233
2234         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2235             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2236              (vif->type == NL80211_IFTYPE_AP))) {
2237                 /*
2238                  * Allocate and setup the beacon frame.
2239                  *
2240                  * Stop any previous beacon DMA.  This may be
2241                  * necessary, for example, when an ibss merge
2242                  * causes reconfiguration; we may be called
2243                  * with beacon transmission active.
2244                  */
2245                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2246
2247                 error = ath_beacon_alloc(sc, 0);
2248                 if (error != 0)
2249                         return error;
2250
2251                 ath_beacon_sync(sc, 0);
2252         }
2253
2254         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2255         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2256                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2257                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2258                                 ath9k_hw_keysetmac(sc->sc_ah,
2259                                                    (u16)i,
2260                                                    sc->sc_curbssid);
2261         }
2262
2263         /* Only legacy IBSS for now */
2264         if (vif->type == NL80211_IFTYPE_ADHOC)
2265                 ath_update_chainmask(sc, 0);
2266
2267         return 0;
2268 }
2269
2270 #define SUPPORTED_FILTERS                       \
2271         (FIF_PROMISC_IN_BSS |                   \
2272         FIF_ALLMULTI |                          \
2273         FIF_CONTROL |                           \
2274         FIF_OTHER_BSS |                         \
2275         FIF_BCN_PRBRESP_PROMISC |               \
2276         FIF_FCSFAIL)
2277
2278 /* FIXME: sc->sc_full_reset ? */
2279 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2280                                    unsigned int changed_flags,
2281                                    unsigned int *total_flags,
2282                                    int mc_count,
2283                                    struct dev_mc_list *mclist)
2284 {
2285         struct ath_softc *sc = hw->priv;
2286         u32 rfilt;
2287
2288         changed_flags &= SUPPORTED_FILTERS;
2289         *total_flags &= SUPPORTED_FILTERS;
2290
2291         sc->rx.rxfilter = *total_flags;
2292         rfilt = ath_calcrxfilter(sc);
2293         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2294
2295         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2296                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2297                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2298         }
2299
2300         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2301 }
2302
2303 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2304                              struct ieee80211_vif *vif,
2305                              enum sta_notify_cmd cmd,
2306                              struct ieee80211_sta *sta)
2307 {
2308         struct ath_softc *sc = hw->priv;
2309
2310         switch (cmd) {
2311         case STA_NOTIFY_ADD:
2312                 ath_node_attach(sc, sta);
2313                 break;
2314         case STA_NOTIFY_REMOVE:
2315                 ath_node_detach(sc, sta);
2316                 break;
2317         default:
2318                 break;
2319         }
2320 }
2321
2322 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2323                          u16 queue,
2324                          const struct ieee80211_tx_queue_params *params)
2325 {
2326         struct ath_softc *sc = hw->priv;
2327         struct ath9k_tx_queue_info qi;
2328         int ret = 0, qnum;
2329
2330         if (queue >= WME_NUM_AC)
2331                 return 0;
2332
2333         qi.tqi_aifs = params->aifs;
2334         qi.tqi_cwmin = params->cw_min;
2335         qi.tqi_cwmax = params->cw_max;
2336         qi.tqi_burstTime = params->txop;
2337         qnum = ath_get_hal_qnum(queue, sc);
2338
2339         DPRINTF(sc, ATH_DBG_CONFIG,
2340                 "Configure tx [queue/halq] [%d/%d],  "
2341                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2342                 queue, qnum, params->aifs, params->cw_min,
2343                 params->cw_max, params->txop);
2344
2345         ret = ath_txq_update(sc, qnum, &qi);
2346         if (ret)
2347                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2348
2349         return ret;
2350 }
2351
2352 static int ath9k_set_key(struct ieee80211_hw *hw,
2353                          enum set_key_cmd cmd,
2354                          const u8 *local_addr,
2355                          const u8 *addr,
2356                          struct ieee80211_key_conf *key)
2357 {
2358         struct ath_softc *sc = hw->priv;
2359         int ret = 0;
2360
2361         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2362
2363         switch (cmd) {
2364         case SET_KEY:
2365                 ret = ath_key_config(sc, addr, key);
2366                 if (ret >= 0) {
2367                         key->hw_key_idx = ret;
2368                         /* push IV and Michael MIC generation to stack */
2369                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2370                         if (key->alg == ALG_TKIP)
2371                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2372                         ret = 0;
2373                 }
2374                 break;
2375         case DISABLE_KEY:
2376                 ath_key_delete(sc, key);
2377                 break;
2378         default:
2379                 ret = -EINVAL;
2380         }
2381
2382         return ret;
2383 }
2384
2385 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2386                                    struct ieee80211_vif *vif,
2387                                    struct ieee80211_bss_conf *bss_conf,
2388                                    u32 changed)
2389 {
2390         struct ath_softc *sc = hw->priv;
2391
2392         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2393                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2394                         bss_conf->use_short_preamble);
2395                 if (bss_conf->use_short_preamble)
2396                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2397                 else
2398                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2399         }
2400
2401         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2402                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2403                         bss_conf->use_cts_prot);
2404                 if (bss_conf->use_cts_prot &&
2405                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2406                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2407                 else
2408                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2409         }
2410
2411         if (changed & BSS_CHANGED_ASSOC) {
2412                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2413                         bss_conf->assoc);
2414                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2415         }
2416 }
2417
2418 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2419 {
2420         u64 tsf;
2421         struct ath_softc *sc = hw->priv;
2422         struct ath_hal *ah = sc->sc_ah;
2423
2424         tsf = ath9k_hw_gettsf64(ah);
2425
2426         return tsf;
2427 }
2428
2429 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2430 {
2431         struct ath_softc *sc = hw->priv;
2432         struct ath_hal *ah = sc->sc_ah;
2433
2434         ath9k_hw_reset_tsf(ah);
2435 }
2436
2437 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2438                        enum ieee80211_ampdu_mlme_action action,
2439                        struct ieee80211_sta *sta,
2440                        u16 tid, u16 *ssn)
2441 {
2442         struct ath_softc *sc = hw->priv;
2443         int ret = 0;
2444
2445         switch (action) {
2446         case IEEE80211_AMPDU_RX_START:
2447                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2448                         ret = -ENOTSUPP;
2449                 break;
2450         case IEEE80211_AMPDU_RX_STOP:
2451                 break;
2452         case IEEE80211_AMPDU_TX_START:
2453                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2454                 if (ret < 0)
2455                         DPRINTF(sc, ATH_DBG_FATAL,
2456                                 "Unable to start TX aggregation\n");
2457                 else
2458                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2459                 break;
2460         case IEEE80211_AMPDU_TX_STOP:
2461                 ret = ath_tx_aggr_stop(sc, sta, tid);
2462                 if (ret < 0)
2463                         DPRINTF(sc, ATH_DBG_FATAL,
2464                                 "Unable to stop TX aggregation\n");
2465
2466                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2467                 break;
2468         case IEEE80211_AMPDU_TX_RESUME:
2469                 ath_tx_aggr_resume(sc, sta, tid);
2470                 break;
2471         default:
2472                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2473         }
2474
2475         return ret;
2476 }
2477
2478 static struct ieee80211_ops ath9k_ops = {
2479         .tx                 = ath9k_tx,
2480         .start              = ath9k_start,
2481         .stop               = ath9k_stop,
2482         .add_interface      = ath9k_add_interface,
2483         .remove_interface   = ath9k_remove_interface,
2484         .config             = ath9k_config,
2485         .config_interface   = ath9k_config_interface,
2486         .configure_filter   = ath9k_configure_filter,
2487         .sta_notify         = ath9k_sta_notify,
2488         .conf_tx            = ath9k_conf_tx,
2489         .bss_info_changed   = ath9k_bss_info_changed,
2490         .set_key            = ath9k_set_key,
2491         .get_tsf            = ath9k_get_tsf,
2492         .reset_tsf          = ath9k_reset_tsf,
2493         .ampdu_action       = ath9k_ampdu_action,
2494 };
2495
2496 static struct {
2497         u32 version;
2498         const char * name;
2499 } ath_mac_bb_names[] = {
2500         { AR_SREV_VERSION_5416_PCI,     "5416" },
2501         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2502         { AR_SREV_VERSION_9100,         "9100" },
2503         { AR_SREV_VERSION_9160,         "9160" },
2504         { AR_SREV_VERSION_9280,         "9280" },
2505         { AR_SREV_VERSION_9285,         "9285" }
2506 };
2507
2508 static struct {
2509         u16 version;
2510         const char * name;
2511 } ath_rf_names[] = {
2512         { 0,                            "5133" },
2513         { AR_RAD5133_SREV_MAJOR,        "5133" },
2514         { AR_RAD5122_SREV_MAJOR,        "5122" },
2515         { AR_RAD2133_SREV_MAJOR,        "2133" },
2516         { AR_RAD2122_SREV_MAJOR,        "2122" }
2517 };
2518
2519 /*
2520  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2521  */
2522 static const char *
2523 ath_mac_bb_name(u32 mac_bb_version)
2524 {
2525         int i;
2526
2527         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2528                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2529                         return ath_mac_bb_names[i].name;
2530                 }
2531         }
2532
2533         return "????";
2534 }
2535
2536 /*
2537  * Return the RF name. "????" is returned if the RF is unknown.
2538  */
2539 static const char *
2540 ath_rf_name(u16 rf_version)
2541 {
2542         int i;
2543
2544         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2545                 if (ath_rf_names[i].version == rf_version) {
2546                         return ath_rf_names[i].name;
2547                 }
2548         }
2549
2550         return "????";
2551 }
2552
2553 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2554 {
2555         void __iomem *mem;
2556         struct ath_softc *sc;
2557         struct ieee80211_hw *hw;
2558         u8 csz;
2559         u32 val;
2560         int ret = 0;
2561         struct ath_hal *ah;
2562
2563         if (pci_enable_device(pdev))
2564                 return -EIO;
2565
2566         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2567
2568         if (ret) {
2569                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2570                 goto bad;
2571         }
2572
2573         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2574
2575         if (ret) {
2576                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2577                         "DMA enable failed\n");
2578                 goto bad;
2579         }
2580
2581         /*
2582          * Cache line size is used to size and align various
2583          * structures used to communicate with the hardware.
2584          */
2585         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2586         if (csz == 0) {
2587                 /*
2588                  * Linux 2.4.18 (at least) writes the cache line size
2589                  * register as a 16-bit wide register which is wrong.
2590                  * We must have this setup properly for rx buffer
2591                  * DMA to work so force a reasonable value here if it
2592                  * comes up zero.
2593                  */
2594                 csz = L1_CACHE_BYTES / sizeof(u32);
2595                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2596         }
2597         /*
2598          * The default setting of latency timer yields poor results,
2599          * set it to the value used by other systems. It may be worth
2600          * tweaking this setting more.
2601          */
2602         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2603
2604         pci_set_master(pdev);
2605
2606         /*
2607          * Disable the RETRY_TIMEOUT register (0x41) to keep
2608          * PCI Tx retries from interfering with C3 CPU state.
2609          */
2610         pci_read_config_dword(pdev, 0x40, &val);
2611         if ((val & 0x0000ff00) != 0)
2612                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2613
2614         ret = pci_request_region(pdev, 0, "ath9k");
2615         if (ret) {
2616                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2617                 ret = -ENODEV;
2618                 goto bad;
2619         }
2620
2621         mem = pci_iomap(pdev, 0, 0);
2622         if (!mem) {
2623                 printk(KERN_ERR "PCI memory map error\n") ;
2624                 ret = -EIO;
2625                 goto bad1;
2626         }
2627
2628         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2629         if (hw == NULL) {
2630                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2631                 goto bad2;
2632         }
2633
2634         SET_IEEE80211_DEV(hw, &pdev->dev);
2635         pci_set_drvdata(pdev, hw);
2636
2637         sc = hw->priv;
2638         sc->hw = hw;
2639         sc->pdev = pdev;
2640         sc->mem = mem;
2641
2642         if (ath_attach(id->device, sc) != 0) {
2643                 ret = -ENODEV;
2644                 goto bad3;
2645         }
2646
2647         /* setup interrupt service routine */
2648
2649         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2650                 printk(KERN_ERR "%s: request_irq failed\n",
2651                         wiphy_name(hw->wiphy));
2652                 ret = -EIO;
2653                 goto bad4;
2654         }
2655
2656         ah = sc->sc_ah;
2657         printk(KERN_INFO
2658                "%s: Atheros AR%s MAC/BB Rev:%x "
2659                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2660                wiphy_name(hw->wiphy),
2661                ath_mac_bb_name(ah->ah_macVersion),
2662                ah->ah_macRev,
2663                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2664                ah->ah_phyRev,
2665                (unsigned long)mem, pdev->irq);
2666
2667         return 0;
2668 bad4:
2669         ath_detach(sc);
2670 bad3:
2671         ieee80211_free_hw(hw);
2672 bad2:
2673         pci_iounmap(pdev, mem);
2674 bad1:
2675         pci_release_region(pdev, 0);
2676 bad:
2677         pci_disable_device(pdev);
2678         return ret;
2679 }
2680
2681 static void ath_pci_remove(struct pci_dev *pdev)
2682 {
2683         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2684         struct ath_softc *sc = hw->priv;
2685
2686         ath_detach(sc);
2687         if (pdev->irq)
2688                 free_irq(pdev->irq, sc);
2689         pci_iounmap(pdev, sc->mem);
2690         pci_release_region(pdev, 0);
2691         pci_disable_device(pdev);
2692         ieee80211_free_hw(hw);
2693 }
2694
2695 #ifdef CONFIG_PM
2696
2697 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2698 {
2699         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2700         struct ath_softc *sc = hw->priv;
2701
2702         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2703
2704 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2705         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2706                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2707 #endif
2708
2709         pci_save_state(pdev);
2710         pci_disable_device(pdev);
2711         pci_set_power_state(pdev, 3);
2712
2713         return 0;
2714 }
2715
2716 static int ath_pci_resume(struct pci_dev *pdev)
2717 {
2718         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2719         struct ath_softc *sc = hw->priv;
2720         u32 val;
2721         int err;
2722
2723         err = pci_enable_device(pdev);
2724         if (err)
2725                 return err;
2726         pci_restore_state(pdev);
2727         /*
2728          * Suspend/Resume resets the PCI configuration space, so we have to
2729          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2730          * PCI Tx retries from interfering with C3 CPU state
2731          */
2732         pci_read_config_dword(pdev, 0x40, &val);
2733         if ((val & 0x0000ff00) != 0)
2734                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2735
2736         /* Enable LED */
2737         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2738                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2739         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2740
2741 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2742         /*
2743          * check the h/w rfkill state on resume
2744          * and start the rfkill poll timer
2745          */
2746         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2747                 queue_delayed_work(sc->hw->workqueue,
2748                                    &sc->rf_kill.rfkill_poll, 0);
2749 #endif
2750
2751         return 0;
2752 }
2753
2754 #endif /* CONFIG_PM */
2755
2756 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2757
2758 static struct pci_driver ath_pci_driver = {
2759         .name       = "ath9k",
2760         .id_table   = ath_pci_id_table,
2761         .probe      = ath_pci_probe,
2762         .remove     = ath_pci_remove,
2763 #ifdef CONFIG_PM
2764         .suspend    = ath_pci_suspend,
2765         .resume     = ath_pci_resume,
2766 #endif /* CONFIG_PM */
2767 };
2768
2769 static int __init init_ath_pci(void)
2770 {
2771         int error;
2772
2773         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2774
2775         /* Register rate control algorithm */
2776         error = ath_rate_control_register();
2777         if (error != 0) {
2778                 printk(KERN_ERR
2779                         "Unable to register rate control algorithm: %d\n",
2780                         error);
2781                 ath_rate_control_unregister();
2782                 return error;
2783         }
2784
2785         if (pci_register_driver(&ath_pci_driver) < 0) {
2786                 printk(KERN_ERR
2787                         "ath_pci: No devices found, driver not installed.\n");
2788                 ath_rate_control_unregister();
2789                 pci_unregister_driver(&ath_pci_driver);
2790                 return -ENODEV;
2791         }
2792
2793         return 0;
2794 }
2795 module_init(init_ath_pci);
2796
2797 static void __exit exit_ath_pci(void)
2798 {
2799         ath_rate_control_unregister();
2800         pci_unregister_driver(&ath_pci_driver);
2801         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2802 }
2803 module_exit(exit_ath_pci);