drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  50         *csz = (int)u8tmp;
  51
  52         /*
  53          * This check was put in to avoid "unplesant" consequences if
  54          * the bootrom has not fully initialized all PCI devices.
  55          * Sometimes the cache line size register is not set
  56          */
  57
  58         if (*csz == 0)
  59                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  60 }
  61
  62 static void ath_setcurmode(struct ath_softc *sc, struct ieee80211_conf *conf)
  63 {
  64         switch (conf->channel->band) {
  65         case IEEE80211_BAND_2GHZ:
  66                 if (conf_is_ht20(conf))
  67                         sc->cur_rate_table =
  68                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  69                 else if (conf_is_ht40_minus(conf))
  70                         sc->cur_rate_table =
  71                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  72                 else if (conf_is_ht40_plus(conf))
  73                         sc->cur_rate_table =
  74                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  75                 else
  76                         sc->cur_rate_table =
  77                           sc->hw_rate_table[ATH9K_MODE_11G];
  78                 break;
  79         case IEEE80211_BAND_5GHZ:
  80                 if (conf_is_ht20(conf))
  81                         sc->cur_rate_table =
  82                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  83                 else if (conf_is_ht40_minus(conf))
  84                         sc->cur_rate_table =
  85                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  86                 else if (conf_is_ht40_plus(conf))
  87                         sc->cur_rate_table =
  88                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  89                 else
  90                         sc->cur_rate_table =
  91                           sc->hw_rate_table[ATH9K_MODE_11A];
  92                 break;
  93         default:
  94                 break;
  95         }
  96 }
  97
  98 static void ath_update_txpow(struct ath_softc *sc)
  99 {
 100         struct ath_hal *ah = sc->sc_ah;
 101         u32 txpow;
 102
 103         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 104                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 105                 /* read back in case value is clamped */
 106                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 107                 sc->sc_curtxpow = txpow;
 108         }
 109 }
 110
 111 static u8 parse_mpdudensity(u8 mpdudensity)
 112 {
 113         /*
 114          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 115          *   0 for no restriction
 116          *   1 for 1/4 us
 117          *   2 for 1/2 us
 118          *   3 for 1 us
 119          *   4 for 2 us
 120          *   5 for 4 us
 121          *   6 for 8 us
 122          *   7 for 16 us
 123          */
 124         switch (mpdudensity) {
 125         case 0:
 126                 return 0;
 127         case 1:
 128         case 2:
 129         case 3:
 130                 /* Our lower layer calculations limit our precision to
 131                    1 microsecond */
 132                 return 1;
 133         case 4:
 134                 return 2;
 135         case 5:
 136                 return 4;
 137         case 6:
 138                 return 8;
 139         case 7:
 140                 return 16;
 141         default:
 142                 return 0;
 143         }
 144 }
 145
 146 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 147 {
 148         struct ath_rate_table *rate_table = NULL;
 149         struct ieee80211_supported_band *sband;
 150         struct ieee80211_rate *rate;
 151         int i, maxrates;
 152
 153         switch (band) {
 154         case IEEE80211_BAND_2GHZ:
 155                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 156                 break;
 157         case IEEE80211_BAND_5GHZ:
 158                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         if (rate_table == NULL)
 165                 return;
 166
 167         sband = &sc->sbands[band];
 168         rate = sc->rates[band];
 169
 170         if (rate_table->rate_cnt > ATH_RATE_MAX)
 171                 maxrates = ATH_RATE_MAX;
 172         else
 173                 maxrates = rate_table->rate_cnt;
 174
 175         for (i = 0; i < maxrates; i++) {
 176                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 177                 rate[i].hw_value = rate_table->info[i].ratecode;
 178                 sband->n_bitrates++;
 179                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 180                         rate[i].bitrate / 10, rate[i].hw_value);
 181         }
 182 }
 183
 184 static int ath_setup_channels(struct ath_softc *sc)
 185 {
 186         struct ath_hal *ah = sc->sc_ah;
 187         int nchan, i, a = 0, b = 0;
 188         u8 regclassids[ATH_REGCLASSIDS_MAX];
 189         u32 nregclass = 0;
 190         struct ieee80211_supported_band *band_2ghz;
 191         struct ieee80211_supported_band *band_5ghz;
 192         struct ieee80211_channel *chan_2ghz;
 193         struct ieee80211_channel *chan_5ghz;
 194         struct ath9k_channel *c;
 195
 196         /* Fill in ah->ah_channels */
 197         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 198                                       regclassids, ATH_REGCLASSIDS_MAX,
 199                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 200                 u32 rd = ah->ah_currentRD;
 201                 DPRINTF(sc, ATH_DBG_FATAL,
 202                         "Unable to collect channel list; "
 203                         "regdomain likely %u country code %u\n",
 204                         rd, CTRY_DEFAULT);
 205                 return -EINVAL;
 206         }
 207
 208         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 209         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 210         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 211         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 212
 213         for (i = 0; i < nchan; i++) {
 214                 c = &ah->ah_channels[i];
 215                 if (IS_CHAN_2GHZ(c)) {
 216                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 217                         chan_2ghz[a].center_freq = c->channel;
 218                         chan_2ghz[a].max_power = c->maxTxPower;
 219
 220                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 221                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 222                         if (c->channelFlags & CHANNEL_PASSIVE)
 223                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 224
 225                         band_2ghz->n_channels = ++a;
 226
 227                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 228                                 "channelFlags: 0x%x\n",
 229                                 c->channel, c->channelFlags);
 230                 } else if (IS_CHAN_5GHZ(c)) {
 231                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 232                         chan_5ghz[b].center_freq = c->channel;
 233                         chan_5ghz[b].max_power = c->maxTxPower;
 234
 235                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 236                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 237                         if (c->channelFlags & CHANNEL_PASSIVE)
 238                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 239
 240                         band_5ghz->n_channels = ++b;
 241
 242                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 243                                 "channelFlags: 0x%x\n",
 244                                 c->channel, c->channelFlags);
 245                 }
 246         }
 247
 248         return 0;
 249 }
 250
 251 /*
 252  * Set/change channels.  If the channel is really being changed, it's done
 253  * by reseting the chip.  To accomplish this we must first cleanup any pending
 254  * DMA, then restart stuff.
 255 */
 256 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 257 {
 258         struct ath_hal *ah = sc->sc_ah;
 259         bool fastcc = true, stopped;
 260         struct ieee80211_hw *hw = sc->hw;
 261
 262         if (sc->sc_flags & SC_OP_INVALID)
 263                 return -EIO;
 264
 265         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 266             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 267             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 268             (sc->sc_flags & SC_OP_FULL_RESET)) {
 269                 int status;
 270                 /*
 271                  * This is only performed if the channel settings have
 272                  * actually changed.
 273                  *
 274                  * To switch channels clear any pending DMA operations;
 275                  * wait long enough for the RX fifo to drain, reset the
 276                  * hardware at the new frequency, and then re-enable
 277                  * the relevant bits of the h/w.
 278                  */
 279                 ath9k_hw_set_interrupts(ah, 0);
 280                 ath_draintxq(sc, false);
 281                 stopped = ath_stoprecv(sc);
 282
 283                 /* XXX: do not flush receive queue here. We don't want
 284                  * to flush data frames already in queue because of
 285                  * changing channel. */
 286
 287                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 288                         fastcc = false;
 289
 290                 DPRINTF(sc, ATH_DBG_CONFIG,
 291                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 292                         sc->sc_ah->ah_curchan->channel,
 293                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 294
 295                 spin_lock_bh(&sc->sc_resetlock);
 296                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 297                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 298                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 299                         DPRINTF(sc, ATH_DBG_FATAL,
 300                                 "Unable to reset channel %u (%uMhz) "
 301                                 "flags 0x%x hal status %u\n",
 302                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 303                                                   hchan->channelFlags),
 304                                 hchan->channel, hchan->channelFlags, status);
 305                         spin_unlock_bh(&sc->sc_resetlock);
 306                         return -EIO;
 307                 }
 308                 spin_unlock_bh(&sc->sc_resetlock);
 309
 310                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 311                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 312
 313                 if (ath_startrecv(sc) != 0) {
 314                         DPRINTF(sc, ATH_DBG_FATAL,
 315                                 "Unable to restart recv logic\n");
 316                         return -EIO;
 317                 }
 318
 319                 ath_setcurmode(sc, &hw->conf);
 320                 ath_update_txpow(sc);
 321                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 322         }
 323         return 0;
 324 }
 325
 326 /*
 327  *  This routine performs the periodic noise floor calibration function
 328  *  that is used to adjust and optimize the chip performance.  This
 329  *  takes environmental changes (location, temperature) into account.
 330  *  When the task is complete, it reschedules itself depending on the
 331  *  appropriate interval that was calculated.
 332  */
 333 static void ath_ani_calibrate(unsigned long data)
 334 {
 335         struct ath_softc *sc;
 336         struct ath_hal *ah;
 337         bool longcal = false;
 338         bool shortcal = false;
 339         bool aniflag = false;
 340         unsigned int timestamp = jiffies_to_msecs(jiffies);
 341         u32 cal_interval;
 342
 343         sc = (struct ath_softc *)data;
 344         ah = sc->sc_ah;
 345
 346         /*
 347         * don't calibrate when we're scanning.
 348         * we are most likely not on our home channel.
 349         */
 350         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 351                 return;
 352
 353         /* Long calibration runs independently of short calibration. */
 354         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 355                 longcal = true;
 356                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 357                 sc->sc_ani.sc_longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while sc_caldone is false */
 361         if (!sc->sc_ani.sc_caldone) {
 362                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 363                     ATH_SHORT_CALINTERVAL) {
 364                         shortcal = true;
 365                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 366                         sc->sc_ani.sc_shortcal_timer = timestamp;
 367                         sc->sc_ani.sc_resetcal_timer = timestamp;
 368                 }
 369         } else {
 370                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 371                     ATH_RESTART_CALINTERVAL) {
 372                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 373                                                 &sc->sc_ani.sc_caldone);
 374                         if (sc->sc_ani.sc_caldone)
 375                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 376                 }
 377         }
 378
 379         /* Verify whether we must check ANI */
 380         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 381            ATH_ANI_POLLINTERVAL) {
 382                 aniflag = true;
 383                 sc->sc_ani.sc_checkani_timer = timestamp;
 384         }
 385
 386         /* Skip all processing if there's nothing to do. */
 387         if (longcal || shortcal || aniflag) {
 388                 /* Call ANI routine if necessary */
 389                 if (aniflag)
 390                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 391                                              ah->ah_curchan);
 392
 393                 /* Perform calibration if necessary */
 394                 if (longcal || shortcal) {
 395                         bool iscaldone = false;
 396
 397                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 398                                                sc->sc_rx_chainmask, longcal,
 399                                                &iscaldone)) {
 400                                 if (longcal)
 401                                         sc->sc_ani.sc_noise_floor =
 402                                                 ath9k_hw_getchan_noise(ah,
 403                                                                ah->ah_curchan);
 404
 405                                 DPRINTF(sc, ATH_DBG_ANI,
 406                                         "calibrate chan %u/%x nf: %d\n",
 407                                         ah->ah_curchan->channel,
 408                                         ah->ah_curchan->channelFlags,
 409                                         sc->sc_ani.sc_noise_floor);
 410                         } else {
 411                                 DPRINTF(sc, ATH_DBG_ANY,
 412                                         "calibrate chan %u/%x failed\n",
 413                                         ah->ah_curchan->channel,
 414                                         ah->ah_curchan->channelFlags);
 415                         }
 416                         sc->sc_ani.sc_caldone = iscaldone;
 417                 }
 418         }
 419
 420         /*
 421         * Set timer interval based on previous results.
 422         * The interval must be the shortest necessary to satisfy ANI,
 423         * short calibration and long calibration.
 424         */
 425         cal_interval = ATH_LONG_CALINTERVAL;
 426         if (sc->sc_ah->ah_config.enable_ani)
 427                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 428         if (!sc->sc_ani.sc_caldone)
 429                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 430
 431         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 432 }
 433
 434 /*
 435  * Update tx/rx chainmask. For legacy association,
 436  * hard code chainmask to 1x1, for 11n association, use
 437  * the chainmask configuration.
 438  */
 439 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 440 {
 441         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 442         if (is_ht) {
 443                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 444                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 445         } else {
 446                 sc->sc_tx_chainmask = 1;
 447                 sc->sc_rx_chainmask = 1;
 448         }
 449
 450         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 451                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 452 }
 453
 454 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 455 {
 456         struct ath_node *an;
 457
 458         an = (struct ath_node *)sta->drv_priv;
 459
 460         if (sc->sc_flags & SC_OP_TXAGGR)
 461                 ath_tx_node_init(sc, an);
 462
 463         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 464                              sta->ht_cap.ampdu_factor);
 465         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 466 }
 467
 468 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 469 {
 470         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 471
 472         if (sc->sc_flags & SC_OP_TXAGGR)
 473                 ath_tx_node_cleanup(sc, an);
 474 }
 475
 476 static void ath9k_tasklet(unsigned long data)
 477 {
 478         struct ath_softc *sc = (struct ath_softc *)data;
 479         u32 status = sc->sc_intrstatus;
 480
 481         if (status & ATH9K_INT_FATAL) {
 482                 /* need a chip reset */
 483                 ath_reset(sc, false);
 484                 return;
 485         } else {
 486
 487                 if (status &
 488                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 489                         spin_lock_bh(&sc->rx.rxflushlock);
 490                         ath_rx_tasklet(sc, 0);
 491                         spin_unlock_bh(&sc->rx.rxflushlock);
 492                 }
 493                 /* XXX: optimize this */
 494                 if (status & ATH9K_INT_TX)
 495                         ath_tx_tasklet(sc);
 496         }
 497
 498         /* re-enable hardware interrupt */
 499         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 500 }
 501
 502 static irqreturn_t ath_isr(int irq, void *dev)
 503 {
 504         struct ath_softc *sc = dev;
 505         struct ath_hal *ah = sc->sc_ah;
 506         enum ath9k_int status;
 507         bool sched = false;
 508
 509         do {
 510                 if (sc->sc_flags & SC_OP_INVALID) {
 511                         /*
 512                          * The hardware is not ready/present, don't
 513                          * touch anything. Note this can happen early
 514                          * on if the IRQ is shared.
 515                          */
 516                         return IRQ_NONE;
 517                 }
 518                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 519                         return IRQ_NONE;
 520                 }
 521
 522                 /*
 523                  * Figure out the reason(s) for the interrupt.  Note
 524                  * that the hal returns a pseudo-ISR that may include
 525                  * bits we haven't explicitly enabled so we mask the
 526                  * value to insure we only process bits we requested.
 527                  */
 528                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 529
 530                 status &= sc->sc_imask; /* discard unasked-for bits */
 531
 532                 /*
 533                  * If there are no status bits set, then this interrupt was not
 534                  * for me (should have been caught above).
 535                  */
 536                 if (!status)
 537                         return IRQ_NONE;
 538
 539                 sc->sc_intrstatus = status;
 540
 541                 if (status & ATH9K_INT_FATAL) {
 542                         /* need a chip reset */
 543                         sched = true;
 544                 } else if (status & ATH9K_INT_RXORN) {
 545                         /* need a chip reset */
 546                         sched = true;
 547                 } else {
 548                         if (status & ATH9K_INT_SWBA) {
 549                                 /* schedule a tasklet for beacon handling */
 550                                 tasklet_schedule(&sc->bcon_tasklet);
 551                         }
 552                         if (status & ATH9K_INT_RXEOL) {
 553                                 /*
 554                                  * NB: the hardware should re-read the link when
 555                                  *     RXE bit is written, but it doesn't work
 556                                  *     at least on older hardware revs.
 557                                  */
 558                                 sched = true;
 559                         }
 560
 561                         if (status & ATH9K_INT_TXURN)
 562                                 /* bump tx trigger level */
 563                                 ath9k_hw_updatetxtriglevel(ah, true);
 564                         /* XXX: optimize this */
 565                         if (status & ATH9K_INT_RX)
 566                                 sched = true;
 567                         if (status & ATH9K_INT_TX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_BMISS)
 570                                 sched = true;
 571                         /* carrier sense timeout */
 572                         if (status & ATH9K_INT_CST)
 573                                 sched = true;
 574                         if (status & ATH9K_INT_MIB) {
 575                                 /*
 576                                  * Disable interrupts until we service the MIB
 577                                  * interrupt; otherwise it will continue to
 578                                  * fire.
 579                                  */
 580                                 ath9k_hw_set_interrupts(ah, 0);
 581                                 /*
 582                                  * Let the hal handle the event. We assume
 583                                  * it will clear whatever condition caused
 584                                  * the interrupt.
 585                                  */
 586                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 587                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 588                         }
 589                         if (status & ATH9K_INT_TIM_TIMER) {
 590                                 if (!(ah->ah_caps.hw_caps &
 591                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 592                                         /* Clear RxAbort bit so that we can
 593                                          * receive frames */
 594                                         ath9k_hw_setrxabort(ah, 0);
 595                                         sched = true;
 596                                 }
 597                         }
 598                 }
 599         } while (0);
 600
 601         ath_debug_stat_interrupt(sc, status);
 602
 603         if (sched) {
 604                 /* turn off every interrupt except SWBA */
 605                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 606                 tasklet_schedule(&sc->intr_tq);
 607         }
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static int ath_get_channel(struct ath_softc *sc,
 613                            struct ieee80211_channel *chan)
 614 {
 615         int i;
 616
 617         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 618                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 619                         return i;
 620         }
 621
 622         return -1;
 623 }
 624
 625 static u32 ath_get_extchanmode(struct ath_softc *sc,
 626                                struct ieee80211_channel *chan,
 627                                enum nl80211_channel_type channel_type)
 628 {
 629         u32 chanmode = 0;
 630
 631         switch (chan->band) {
 632         case IEEE80211_BAND_2GHZ:
 633                 switch(channel_type) {
 634                 case NL80211_CHAN_NO_HT:
 635                 case NL80211_CHAN_HT20:
 636                         chanmode = CHANNEL_G_HT20;
 637                         break;
 638                 case NL80211_CHAN_HT40PLUS:
 639                         chanmode = CHANNEL_G_HT40PLUS;
 640                         break;
 641                 case NL80211_CHAN_HT40MINUS:
 642                         chanmode = CHANNEL_G_HT40MINUS;
 643                         break;
 644                 }
 645                 break;
 646         case IEEE80211_BAND_5GHZ:
 647                 switch(channel_type) {
 648                 case NL80211_CHAN_NO_HT:
 649                 case NL80211_CHAN_HT20:
 650                         chanmode = CHANNEL_A_HT20;
 651                         break;
 652                 case NL80211_CHAN_HT40PLUS:
 653                         chanmode = CHANNEL_A_HT40PLUS;
 654                         break;
 655                 case NL80211_CHAN_HT40MINUS:
 656                         chanmode = CHANNEL_A_HT40MINUS;
 657                         break;
 658                 }
 659                 break;
 660         default:
 661                 break;
 662         }
 663
 664         return chanmode;
 665 }
 666
 667 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 668                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 669 {
 670         bool status;
 671
 672         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 673                 keyix, hk, mac, false);
 674
 675         return status != false;
 676 }
 677
 678 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 679                            struct ath9k_keyval *hk,
 680                            const u8 *addr)
 681 {
 682         const u8 *key_rxmic;
 683         const u8 *key_txmic;
 684
 685         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 686         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 687
 688         if (addr == NULL) {
 689                 /* Group key installation */
 690                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 691                 return ath_keyset(sc, keyix, hk, addr);
 692         }
 693         if (!sc->sc_splitmic) {
 694                 /*
 695                  * data key goes at first index,
 696                  * the hal handles the MIC keys at index+64.
 697                  */
 698                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 699                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 700                 return ath_keyset(sc, keyix, hk, addr);
 701         }
 702         /*
 703          * TX key goes at first index, RX key at +32.
 704          * The hal handles the MIC keys at index+64.
 705          */
 706         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 707         if (!ath_keyset(sc, keyix, hk, NULL)) {
 708                 /* Txmic entry failed. No need to proceed further */
 709                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 710                         "Setting TX MIC Key Failed\n");
 711                 return 0;
 712         }
 713
 714         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 715         /* XXX delete tx key on failure? */
 716         return ath_keyset(sc, keyix + 32, hk, addr);
 717 }
 718
 719 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 720 {
 721         int i;
 722
 723         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 724                 if (test_bit(i, sc->sc_keymap) ||
 725                     test_bit(i + 64, sc->sc_keymap))
 726                         continue; /* At least one part of TKIP key allocated */
 727                 if (sc->sc_splitmic &&
 728                     (test_bit(i + 32, sc->sc_keymap) ||
 729                      test_bit(i + 64 + 32, sc->sc_keymap)))
 730                         continue; /* At least one part of TKIP key allocated */
 731
 732                 /* Found a free slot for a TKIP key */
 733                 return i;
 734         }
 735         return -1;
 736 }
 737
 738 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 739 {
 740         int i;
 741
 742         /* First, try to find slots that would not be available for TKIP. */
 743         if (sc->sc_splitmic) {
 744                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 745                         if (!test_bit(i, sc->sc_keymap) &&
 746                             (test_bit(i + 32, sc->sc_keymap) ||
 747                              test_bit(i + 64, sc->sc_keymap) ||
 748                              test_bit(i + 64 + 32, sc->sc_keymap)))
 749                                 return i;
 750                         if (!test_bit(i + 32, sc->sc_keymap) &&
 751                             (test_bit(i, sc->sc_keymap) ||
 752                              test_bit(i + 64, sc->sc_keymap) ||
 753                              test_bit(i + 64 + 32, sc->sc_keymap)))
 754                                 return i + 32;
 755                         if (!test_bit(i + 64, sc->sc_keymap) &&
 756                             (test_bit(i , sc->sc_keymap) ||
 757                              test_bit(i + 32, sc->sc_keymap) ||
 758                              test_bit(i + 64 + 32, sc->sc_keymap)))
 759                                 return i + 64;
 760                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 761                             (test_bit(i, sc->sc_keymap) ||
 762                              test_bit(i + 32, sc->sc_keymap) ||
 763                              test_bit(i + 64, sc->sc_keymap)))
 764                                 return i + 64 + 32;
 765                 }
 766         } else {
 767                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 768                         if (!test_bit(i, sc->sc_keymap) &&
 769                             test_bit(i + 64, sc->sc_keymap))
 770                                 return i;
 771                         if (test_bit(i, sc->sc_keymap) &&
 772                             !test_bit(i + 64, sc->sc_keymap))
 773                                 return i + 64;
 774                 }
 775         }
 776
 777         /* No partially used TKIP slots, pick any available slot */
 778         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 779                 /* Do not allow slots that could be needed for TKIP group keys
 780                  * to be used. This limitation could be removed if we know that
 781                  * TKIP will not be used. */
 782                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 783                         continue;
 784                 if (sc->sc_splitmic) {
 785                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 786                                 continue;
 787                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 788                                 continue;
 789                 }
 790
 791                 if (!test_bit(i, sc->sc_keymap))
 792                         return i; /* Found a free slot for a key */
 793         }
 794
 795         /* No free slot found */
 796         return -1;
 797 }
 798
 799 static int ath_key_config(struct ath_softc *sc,
 800                           const u8 *addr,
 801                           struct ieee80211_key_conf *key)
 802 {
 803         struct ath9k_keyval hk;
 804         const u8 *mac = NULL;
 805         int ret = 0;
 806         int idx;
 807
 808         memset(&hk, 0, sizeof(hk));
 809
 810         switch (key->alg) {
 811         case ALG_WEP:
 812                 hk.kv_type = ATH9K_CIPHER_WEP;
 813                 break;
 814         case ALG_TKIP:
 815                 hk.kv_type = ATH9K_CIPHER_TKIP;
 816                 break;
 817         case ALG_CCMP:
 818                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 819                 break;
 820         default:
 821                 return -EINVAL;
 822         }
 823
 824         hk.kv_len = key->keylen;
 825         memcpy(hk.kv_val, key->key, key->keylen);
 826
 827         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 828                 /* For now, use the default keys for broadcast keys. This may
 829                  * need to change with virtual interfaces. */
 830                 idx = key->keyidx;
 831         } else if (key->keyidx) {
 832                 struct ieee80211_vif *vif;
 833
 834                 mac = addr;
 835                 vif = sc->sc_vaps[0];
 836                 if (vif->type != NL80211_IFTYPE_AP) {
 837                         /* Only keyidx 0 should be used with unicast key, but
 838                          * allow this for client mode for now. */
 839                         idx = key->keyidx;
 840                 } else
 841                         return -EIO;
 842         } else {
 843                 mac = addr;
 844                 if (key->alg == ALG_TKIP)
 845                         idx = ath_reserve_key_cache_slot_tkip(sc);
 846                 else
 847                         idx = ath_reserve_key_cache_slot(sc);
 848                 if (idx < 0)
 849                         return -EIO; /* no free key cache entries */
 850         }
 851
 852         if (key->alg == ALG_TKIP)
 853                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 854         else
 855                 ret = ath_keyset(sc, idx, &hk, mac);
 856
 857         if (!ret)
 858                 return -EIO;
 859
 860         set_bit(idx, sc->sc_keymap);
 861         if (key->alg == ALG_TKIP) {
 862                 set_bit(idx + 64, sc->sc_keymap);
 863                 if (sc->sc_splitmic) {
 864                         set_bit(idx + 32, sc->sc_keymap);
 865                         set_bit(idx + 64 + 32, sc->sc_keymap);
 866                 }
 867         }
 868
 869         return idx;
 870 }
 871
 872 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 873 {
 874         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 875         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 876                 return;
 877
 878         clear_bit(key->hw_key_idx, sc->sc_keymap);
 879         if (key->alg != ALG_TKIP)
 880                 return;
 881
 882         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 883         if (sc->sc_splitmic) {
 884                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 885                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 886         }
 887 }
 888
 889 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 890 {
 891 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 892 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 893
 894         ht_info->ht_supported = true;
 895         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 896                        IEEE80211_HT_CAP_SM_PS |
 897                        IEEE80211_HT_CAP_SGI_40 |
 898                        IEEE80211_HT_CAP_DSSSCCK40;
 899
 900         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 901         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 902         /* set up supported mcs set */
 903         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 904         ht_info->mcs.rx_mask[0] = 0xff;
 905         ht_info->mcs.rx_mask[1] = 0xff;
 906         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 907 }
 908
 909 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 910                                  struct ieee80211_vif *vif,
 911                                  struct ieee80211_bss_conf *bss_conf)
 912 {
 913         struct ath_vap *avp = (void *)vif->drv_priv;
 914
 915         if (bss_conf->assoc) {
 916                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 917                         bss_conf->aid, sc->sc_curbssid);
 918
 919                 /* New association, store aid */
 920                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 921                         sc->sc_curaid = bss_conf->aid;
 922                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 923                                                sc->sc_curaid);
 924                 }
 925
 926                 /* Configure the beacon */
 927                 ath_beacon_config(sc, 0);
 928                 sc->sc_flags |= SC_OP_BEACONS;
 929
 930                 /* Reset rssi stats */
 931                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 932                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 933                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 934                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 935
 936                 /* Start ANI */
 937                 mod_timer(&sc->sc_ani.timer,
 938                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 939
 940         } else {
 941                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 942                 sc->sc_curaid = 0;
 943         }
 944 }
 945
 946 /********************************/
 947 /*       LED functions          */
 948 /********************************/
 949
 950 static void ath_led_brightness(struct led_classdev *led_cdev,
 951                                enum led_brightness brightness)
 952 {
 953         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 954         struct ath_softc *sc = led->sc;
 955
 956         switch (brightness) {
 957         case LED_OFF:
 958                 if (led->led_type == ATH_LED_ASSOC ||
 959                     led->led_type == ATH_LED_RADIO)
 960                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 961                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 962                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 963                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 964                 break;
 965         case LED_FULL:
 966                 if (led->led_type == ATH_LED_ASSOC)
 967                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 968                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 969                 break;
 970         default:
 971                 break;
 972         }
 973 }
 974
 975 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 976                             char *trigger)
 977 {
 978         int ret;
 979
 980         led->sc = sc;
 981         led->led_cdev.name = led->name;
 982         led->led_cdev.default_trigger = trigger;
 983         led->led_cdev.brightness_set = ath_led_brightness;
 984
 985         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 986         if (ret)
 987                 DPRINTF(sc, ATH_DBG_FATAL,
 988                         "Failed to register led:%s", led->name);
 989         else
 990                 led->registered = 1;
 991         return ret;
 992 }
 993
 994 static void ath_unregister_led(struct ath_led *led)
 995 {
 996         if (led->registered) {
 997                 led_classdev_unregister(&led->led_cdev);
 998                 led->registered = 0;
 999         }
1000 }
1001
1002 static void ath_deinit_leds(struct ath_softc *sc)
1003 {
1004         ath_unregister_led(&sc->assoc_led);
1005         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1006         ath_unregister_led(&sc->tx_led);
1007         ath_unregister_led(&sc->rx_led);
1008         ath_unregister_led(&sc->radio_led);
1009         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1010 }
1011
1012 static void ath_init_leds(struct ath_softc *sc)
1013 {
1014         char *trigger;
1015         int ret;
1016
1017         /* Configure gpio 1 for output */
1018         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1019                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1020         /* LED off, active low */
1021         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1022
1023         trigger = ieee80211_get_radio_led_name(sc->hw);
1024         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1025                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1026         ret = ath_register_led(sc, &sc->radio_led, trigger);
1027         sc->radio_led.led_type = ATH_LED_RADIO;
1028         if (ret)
1029                 goto fail;
1030
1031         trigger = ieee80211_get_assoc_led_name(sc->hw);
1032         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1033                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1034         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1035         sc->assoc_led.led_type = ATH_LED_ASSOC;
1036         if (ret)
1037                 goto fail;
1038
1039         trigger = ieee80211_get_tx_led_name(sc->hw);
1040         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1041                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1042         ret = ath_register_led(sc, &sc->tx_led, trigger);
1043         sc->tx_led.led_type = ATH_LED_TX;
1044         if (ret)
1045                 goto fail;
1046
1047         trigger = ieee80211_get_rx_led_name(sc->hw);
1048         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1049                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1050         ret = ath_register_led(sc, &sc->rx_led, trigger);
1051         sc->rx_led.led_type = ATH_LED_RX;
1052         if (ret)
1053                 goto fail;
1054
1055         return;
1056
1057 fail:
1058         ath_deinit_leds(sc);
1059 }
1060
1061 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1062
1063 /*******************/
1064 /*      Rfkill     */
1065 /*******************/
1066
1067 static void ath_radio_enable(struct ath_softc *sc)
1068 {
1069         struct ath_hal *ah = sc->sc_ah;
1070         int status;
1071
1072         spin_lock_bh(&sc->sc_resetlock);
1073         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1074                             sc->tx_chan_width,
1075                             sc->sc_tx_chainmask,
1076                             sc->sc_rx_chainmask,
1077                             sc->sc_ht_extprotspacing,
1078                             false, &status)) {
1079                 DPRINTF(sc, ATH_DBG_FATAL,
1080                         "Unable to reset channel %u (%uMhz) "
1081                         "flags 0x%x hal status %u\n",
1082                         ath9k_hw_mhz2ieee(ah,
1083                                           ah->ah_curchan->channel,
1084                                           ah->ah_curchan->channelFlags),
1085                         ah->ah_curchan->channel,
1086                         ah->ah_curchan->channelFlags, status);
1087         }
1088         spin_unlock_bh(&sc->sc_resetlock);
1089
1090         ath_update_txpow(sc);
1091         if (ath_startrecv(sc) != 0) {
1092                 DPRINTF(sc, ATH_DBG_FATAL,
1093                         "Unable to restart recv logic\n");
1094                 return;
1095         }
1096
1097         if (sc->sc_flags & SC_OP_BEACONS)
1098                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1099
1100         /* Re-Enable  interrupts */
1101         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1102
1103         /* Enable LED */
1104         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1105                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1106         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1107
1108         ieee80211_wake_queues(sc->hw);
1109 }
1110
1111 static void ath_radio_disable(struct ath_softc *sc)
1112 {
1113         struct ath_hal *ah = sc->sc_ah;
1114         int status;
1115
1116
1117         ieee80211_stop_queues(sc->hw);
1118
1119         /* Disable LED */
1120         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1121         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1122
1123         /* Disable interrupts */
1124         ath9k_hw_set_interrupts(ah, 0);
1125
1126         ath_draintxq(sc, false);        /* clear pending tx frames */
1127         ath_stoprecv(sc);               /* turn off frame recv */
1128         ath_flushrecv(sc);              /* flush recv queue */
1129
1130         spin_lock_bh(&sc->sc_resetlock);
1131         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1132                             sc->tx_chan_width,
1133                             sc->sc_tx_chainmask,
1134                             sc->sc_rx_chainmask,
1135                             sc->sc_ht_extprotspacing,
1136                             false, &status)) {
1137                 DPRINTF(sc, ATH_DBG_FATAL,
1138                         "Unable to reset channel %u (%uMhz) "
1139                         "flags 0x%x hal status %u\n",
1140                         ath9k_hw_mhz2ieee(ah,
1141                                 ah->ah_curchan->channel,
1142                                 ah->ah_curchan->channelFlags),
1143                         ah->ah_curchan->channel,
1144                         ah->ah_curchan->channelFlags, status);
1145         }
1146         spin_unlock_bh(&sc->sc_resetlock);
1147
1148         ath9k_hw_phy_disable(ah);
1149         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1150 }
1151
1152 static bool ath_is_rfkill_set(struct ath_softc *sc)
1153 {
1154         struct ath_hal *ah = sc->sc_ah;
1155
1156         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1157                                   ah->ah_rfkill_polarity;
1158 }
1159
1160 /* h/w rfkill poll function */
1161 static void ath_rfkill_poll(struct work_struct *work)
1162 {
1163         struct ath_softc *sc = container_of(work, struct ath_softc,
1164                                             rf_kill.rfkill_poll.work);
1165         bool radio_on;
1166
1167         if (sc->sc_flags & SC_OP_INVALID)
1168                 return;
1169
1170         radio_on = !ath_is_rfkill_set(sc);
1171
1172         /*
1173          * enable/disable radio only when there is a
1174          * state change in RF switch
1175          */
1176         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1177                 enum rfkill_state state;
1178
1179                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1180                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1181                                 : RFKILL_STATE_HARD_BLOCKED;
1182                 } else if (radio_on) {
1183                         ath_radio_enable(sc);
1184                         state = RFKILL_STATE_UNBLOCKED;
1185                 } else {
1186                         ath_radio_disable(sc);
1187                         state = RFKILL_STATE_HARD_BLOCKED;
1188                 }
1189
1190                 if (state == RFKILL_STATE_HARD_BLOCKED)
1191                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1192                 else
1193                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1194
1195                 rfkill_force_state(sc->rf_kill.rfkill, state);
1196         }
1197
1198         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1199                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1200 }
1201
1202 /* s/w rfkill handler */
1203 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1204 {
1205         struct ath_softc *sc = data;
1206
1207         switch (state) {
1208         case RFKILL_STATE_SOFT_BLOCKED:
1209                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1210                     SC_OP_RFKILL_SW_BLOCKED)))
1211                         ath_radio_disable(sc);
1212                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1213                 return 0;
1214         case RFKILL_STATE_UNBLOCKED:
1215                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1216                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1217                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1218                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1219                                         "radio as it is disabled by h/w\n");
1220                                 return -EPERM;
1221                         }
1222                         ath_radio_enable(sc);
1223                 }
1224                 return 0;
1225         default:
1226                 return -EINVAL;
1227         }
1228 }
1229
1230 /* Init s/w rfkill */
1231 static int ath_init_sw_rfkill(struct ath_softc *sc)
1232 {
1233         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1234                                              RFKILL_TYPE_WLAN);
1235         if (!sc->rf_kill.rfkill) {
1236                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1237                 return -ENOMEM;
1238         }
1239
1240         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1241                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1242         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1243         sc->rf_kill.rfkill->data = sc;
1244         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1245         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1246         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1247
1248         return 0;
1249 }
1250
1251 /* Deinitialize rfkill */
1252 static void ath_deinit_rfkill(struct ath_softc *sc)
1253 {
1254         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1255                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1256
1257         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1258                 rfkill_unregister(sc->rf_kill.rfkill);
1259                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1260                 sc->rf_kill.rfkill = NULL;
1261         }
1262 }
1263
1264 static int ath_start_rfkill_poll(struct ath_softc *sc)
1265 {
1266         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1267                 queue_delayed_work(sc->hw->workqueue,
1268                                    &sc->rf_kill.rfkill_poll, 0);
1269
1270         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1271                 if (rfkill_register(sc->rf_kill.rfkill)) {
1272                         DPRINTF(sc, ATH_DBG_FATAL,
1273                                 "Unable to register rfkill\n");
1274                         rfkill_free(sc->rf_kill.rfkill);
1275
1276                         /* Deinitialize the device */
1277                         ath_detach(sc);
1278                         if (sc->pdev->irq)
1279                                 free_irq(sc->pdev->irq, sc);
1280                         pci_iounmap(sc->pdev, sc->mem);
1281                         pci_release_region(sc->pdev, 0);
1282                         pci_disable_device(sc->pdev);
1283                         ieee80211_free_hw(sc->hw);
1284                         return -EIO;
1285                 } else {
1286                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1287                 }
1288         }
1289
1290         return 0;
1291 }
1292 #endif /* CONFIG_RFKILL */
1293
1294 static void ath_detach(struct ath_softc *sc)
1295 {
1296         struct ieee80211_hw *hw = sc->hw;
1297         int i = 0;
1298
1299         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1300
1301 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1302         ath_deinit_rfkill(sc);
1303 #endif
1304         ath_deinit_leds(sc);
1305
1306         ieee80211_unregister_hw(hw);
1307         ath_rx_cleanup(sc);
1308         ath_tx_cleanup(sc);
1309
1310         tasklet_kill(&sc->intr_tq);
1311         tasklet_kill(&sc->bcon_tasklet);
1312
1313         if (!(sc->sc_flags & SC_OP_INVALID))
1314                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1315
1316         /* cleanup tx queues */
1317         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1318                 if (ATH_TXQ_SETUP(sc, i))
1319                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1320
1321         ath9k_hw_detach(sc->sc_ah);
1322         ath9k_exit_debug(sc);
1323 }
1324
1325 static int ath_init(u16 devid, struct ath_softc *sc)
1326 {
1327         struct ath_hal *ah = NULL;
1328         int status;
1329         int error = 0, i;
1330         int csz = 0;
1331
1332         /* XXX: hardware will not be ready until ath_open() being called */
1333         sc->sc_flags |= SC_OP_INVALID;
1334
1335         if (ath9k_init_debug(sc) < 0)
1336                 printk(KERN_ERR "Unable to create debugfs files\n");
1337
1338         spin_lock_init(&sc->sc_resetlock);
1339         mutex_init(&sc->mutex);
1340         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1341         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1342                      (unsigned long)sc);
1343
1344         /*
1345          * Cache line size is used to size and align various
1346          * structures used to communicate with the hardware.
1347          */
1348         bus_read_cachesize(sc, &csz);
1349         /* XXX assert csz is non-zero */
1350         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1351
1352         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1353         if (ah == NULL) {
1354                 DPRINTF(sc, ATH_DBG_FATAL,
1355                         "Unable to attach hardware; HAL status %u\n", status);
1356                 error = -ENXIO;
1357                 goto bad;
1358         }
1359         sc->sc_ah = ah;
1360
1361         /* Get the hardware key cache size. */
1362         sc->sc_keymax = ah->ah_caps.keycache_size;
1363         if (sc->sc_keymax > ATH_KEYMAX) {
1364                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1365                         "Warning, using only %u entries in %u key cache\n",
1366                         ATH_KEYMAX, sc->sc_keymax);
1367                 sc->sc_keymax = ATH_KEYMAX;
1368         }
1369
1370         /*
1371          * Reset the key cache since some parts do not
1372          * reset the contents on initial power up.
1373          */
1374         for (i = 0; i < sc->sc_keymax; i++)
1375                 ath9k_hw_keyreset(ah, (u16) i);
1376
1377         /* Collect the channel list using the default country code */
1378
1379         error = ath_setup_channels(sc);
1380         if (error)
1381                 goto bad;
1382
1383         /* default to MONITOR mode */
1384         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1385
1386
1387         /* Setup rate tables */
1388
1389         ath_rate_attach(sc);
1390         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1391         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1392
1393         /*
1394          * Allocate hardware transmit queues: one queue for
1395          * beacon frames and one data queue for each QoS
1396          * priority.  Note that the hal handles reseting
1397          * these queues at the needed time.
1398          */
1399         sc->beacon.beaconq = ath_beaconq_setup(ah);
1400         if (sc->beacon.beaconq == -1) {
1401                 DPRINTF(sc, ATH_DBG_FATAL,
1402                         "Unable to setup a beacon xmit queue\n");
1403                 error = -EIO;
1404                 goto bad2;
1405         }
1406         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1407         if (sc->beacon.cabq == NULL) {
1408                 DPRINTF(sc, ATH_DBG_FATAL,
1409                         "Unable to setup CAB xmit queue\n");
1410                 error = -EIO;
1411                 goto bad2;
1412         }
1413
1414         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1415         ath_cabq_update(sc);
1416
1417         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1418                 sc->tx.hwq_map[i] = -1;
1419
1420         /* Setup data queues */
1421         /* NB: ensure BK queue is the lowest priority h/w queue */
1422         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1423                 DPRINTF(sc, ATH_DBG_FATAL,
1424                         "Unable to setup xmit queue for BK traffic\n");
1425                 error = -EIO;
1426                 goto bad2;
1427         }
1428
1429         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1430                 DPRINTF(sc, ATH_DBG_FATAL,
1431                         "Unable to setup xmit queue for BE traffic\n");
1432                 error = -EIO;
1433                 goto bad2;
1434         }
1435         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1436                 DPRINTF(sc, ATH_DBG_FATAL,
1437                         "Unable to setup xmit queue for VI traffic\n");
1438                 error = -EIO;
1439                 goto bad2;
1440         }
1441         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1442                 DPRINTF(sc, ATH_DBG_FATAL,
1443                         "Unable to setup xmit queue for VO traffic\n");
1444                 error = -EIO;
1445                 goto bad2;
1446         }
1447
1448         /* Initializes the noise floor to a reasonable default value.
1449          * Later on this will be updated during ANI processing. */
1450
1451         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1452         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1453
1454         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1455                                    ATH9K_CIPHER_TKIP, NULL)) {
1456                 /*
1457                  * Whether we should enable h/w TKIP MIC.
1458                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1459                  * report WMM capable, so it's always safe to turn on
1460                  * TKIP MIC in this case.
1461                  */
1462                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1463                                        0, 1, NULL);
1464         }
1465
1466         /*
1467          * Check whether the separate key cache entries
1468          * are required to handle both tx+rx MIC keys.
1469          * With split mic keys the number of stations is limited
1470          * to 27 otherwise 59.
1471          */
1472         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473                                    ATH9K_CIPHER_TKIP, NULL)
1474             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1475                                       ATH9K_CIPHER_MIC, NULL)
1476             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1477                                       0, NULL))
1478                 sc->sc_splitmic = 1;
1479
1480         /* turn on mcast key search if possible */
1481         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1482                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1483                                              1, NULL);
1484
1485         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1486         sc->sc_config.txpowlimit_override = 0;
1487
1488         /* 11n Capabilities */
1489         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1490                 sc->sc_flags |= SC_OP_TXAGGR;
1491                 sc->sc_flags |= SC_OP_RXAGGR;
1492         }
1493
1494         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1495         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1496
1497         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1498         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1499
1500         ath9k_hw_getmac(ah, sc->sc_myaddr);
1501         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1502                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1503                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1504                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1505         }
1506
1507         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1508
1509         /* initialize beacon slots */
1510         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1511                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1512
1513         /* save MISC configurations */
1514         sc->sc_config.swBeaconProcess = 1;
1515
1516         /* setup channels and rates */
1517
1518         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1519                 sc->channels[IEEE80211_BAND_2GHZ];
1520         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1521                 sc->rates[IEEE80211_BAND_2GHZ];
1522         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1523
1524         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1525                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1526                         sc->channels[IEEE80211_BAND_5GHZ];
1527                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1528                         sc->rates[IEEE80211_BAND_5GHZ];
1529                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1530         }
1531
1532         return 0;
1533 bad2:
1534         /* cleanup tx queues */
1535         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1536                 if (ATH_TXQ_SETUP(sc, i))
1537                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1538 bad:
1539         if (ah)
1540                 ath9k_hw_detach(ah);
1541
1542         return error;
1543 }
1544
1545 static int ath_attach(u16 devid, struct ath_softc *sc)
1546 {
1547         struct ieee80211_hw *hw = sc->hw;
1548         int error = 0;
1549
1550         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1551
1552         error = ath_init(devid, sc);
1553         if (error != 0)
1554                 return error;
1555
1556         /* get mac address from hardware and set in mac80211 */
1557
1558         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1559
1560         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1561                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1562                 IEEE80211_HW_SIGNAL_DBM |
1563                 IEEE80211_HW_AMPDU_AGGREGATION;
1564
1565         hw->wiphy->interface_modes =
1566                 BIT(NL80211_IFTYPE_AP) |
1567                 BIT(NL80211_IFTYPE_STATION) |
1568                 BIT(NL80211_IFTYPE_ADHOC);
1569
1570         hw->queues = 4;
1571         hw->max_rates = 4;
1572         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1573         hw->sta_data_size = sizeof(struct ath_node);
1574         hw->vif_data_size = sizeof(struct ath_vap);
1575
1576         hw->rate_control_algorithm = "ath9k_rate_control";
1577
1578         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1579                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1580                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1581                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1582         }
1583
1584         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1585         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1586                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1587                         &sc->sbands[IEEE80211_BAND_5GHZ];
1588
1589         /* initialize tx/rx engine */
1590         error = ath_tx_init(sc, ATH_TXBUF);
1591         if (error != 0)
1592                 goto detach;
1593
1594         error = ath_rx_init(sc, ATH_RXBUF);
1595         if (error != 0)
1596                 goto detach;
1597
1598 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1599         /* Initialze h/w Rfkill */
1600         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1601                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1602
1603         /* Initialize s/w rfkill */
1604         if (ath_init_sw_rfkill(sc))
1605                 goto detach;
1606 #endif
1607
1608         error = ieee80211_register_hw(hw);
1609
1610         /* Initialize LED control */
1611         ath_init_leds(sc);
1612
1613         return 0;
1614 detach:
1615         ath_detach(sc);
1616         return error;
1617 }
1618
1619 int ath_reset(struct ath_softc *sc, bool retry_tx)
1620 {
1621         struct ath_hal *ah = sc->sc_ah;
1622         struct ieee80211_hw *hw = sc->hw;
1623         int status;
1624         int error = 0;
1625
1626         ath9k_hw_set_interrupts(ah, 0);
1627         ath_draintxq(sc, retry_tx);
1628         ath_stoprecv(sc);
1629         ath_flushrecv(sc);
1630
1631         spin_lock_bh(&sc->sc_resetlock);
1632         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1633                             sc->tx_chan_width,
1634                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1635                             sc->sc_ht_extprotspacing, false, &status)) {
1636                 DPRINTF(sc, ATH_DBG_FATAL,
1637                         "Unable to reset hardware; hal status %u\n", status);
1638                 error = -EIO;
1639         }
1640         spin_unlock_bh(&sc->sc_resetlock);
1641
1642         if (ath_startrecv(sc) != 0)
1643                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1644
1645         /*
1646          * We may be doing a reset in response to a request
1647          * that changes the channel so update any state that
1648          * might change as a result.
1649          */
1650         ath_setcurmode(sc, &hw->conf);
1651
1652         ath_update_txpow(sc);
1653
1654         if (sc->sc_flags & SC_OP_BEACONS)
1655                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1656
1657         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1658
1659         if (retry_tx) {
1660                 int i;
1661                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1662                         if (ATH_TXQ_SETUP(sc, i)) {
1663                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1664                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1665                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1666                         }
1667                 }
1668         }
1669
1670         return error;
1671 }
1672
1673 /*
1674  *  This function will allocate both the DMA descriptor structure, and the
1675  *  buffers it contains.  These are used to contain the descriptors used
1676  *  by the system.
1677 */
1678 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1679                       struct list_head *head, const char *name,
1680                       int nbuf, int ndesc)
1681 {
1682 #define DS2PHYS(_dd, _ds)                                               \
1683         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1684 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1685 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1686
1687         struct ath_desc *ds;
1688         struct ath_buf *bf;
1689         int i, bsize, error;
1690
1691         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1692                 name, nbuf, ndesc);
1693
1694         /* ath_desc must be a multiple of DWORDs */
1695         if ((sizeof(struct ath_desc) % 4) != 0) {
1696                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1697                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1698                 error = -ENOMEM;
1699                 goto fail;
1700         }
1701
1702         dd->dd_name = name;
1703         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1704
1705         /*
1706          * Need additional DMA memory because we can't use
1707          * descriptors that cross the 4K page boundary. Assume
1708          * one skipped descriptor per 4K page.
1709          */
1710         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1711                 u32 ndesc_skipped =
1712                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1713                 u32 dma_len;
1714
1715                 while (ndesc_skipped) {
1716                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1717                         dd->dd_desc_len += dma_len;
1718
1719                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1720                 };
1721         }
1722
1723         /* allocate descriptors */
1724         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1725                               dd->dd_desc_len,
1726                               &dd->dd_desc_paddr);
1727         if (dd->dd_desc == NULL) {
1728                 error = -ENOMEM;
1729                 goto fail;
1730         }
1731         ds = dd->dd_desc;
1732         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1733                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1734                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1735
1736         /* allocate buffers */
1737         bsize = sizeof(struct ath_buf) * nbuf;
1738         bf = kmalloc(bsize, GFP_KERNEL);
1739         if (bf == NULL) {
1740                 error = -ENOMEM;
1741                 goto fail2;
1742         }
1743         memset(bf, 0, bsize);
1744         dd->dd_bufptr = bf;
1745
1746         INIT_LIST_HEAD(head);
1747         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1748                 bf->bf_desc = ds;
1749                 bf->bf_daddr = DS2PHYS(dd, ds);
1750
1751                 if (!(sc->sc_ah->ah_caps.hw_caps &
1752                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1753                         /*
1754                          * Skip descriptor addresses which can cause 4KB
1755                          * boundary crossing (addr + length) with a 32 dword
1756                          * descriptor fetch.
1757                          */
1758                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1759                                 ASSERT((caddr_t) bf->bf_desc <
1760                                        ((caddr_t) dd->dd_desc +
1761                                         dd->dd_desc_len));
1762
1763                                 ds += ndesc;
1764                                 bf->bf_desc = ds;
1765                                 bf->bf_daddr = DS2PHYS(dd, ds);
1766                         }
1767                 }
1768                 list_add_tail(&bf->list, head);
1769         }
1770         return 0;
1771 fail2:
1772         pci_free_consistent(sc->pdev,
1773                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1774 fail:
1775         memset(dd, 0, sizeof(*dd));
1776         return error;
1777 #undef ATH_DESC_4KB_BOUND_CHECK
1778 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1779 #undef DS2PHYS
1780 }
1781
1782 void ath_descdma_cleanup(struct ath_softc *sc,
1783                          struct ath_descdma *dd,
1784                          struct list_head *head)
1785 {
1786         pci_free_consistent(sc->pdev,
1787                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1788
1789         INIT_LIST_HEAD(head);
1790         kfree(dd->dd_bufptr);
1791         memset(dd, 0, sizeof(*dd));
1792 }
1793
1794 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1795 {
1796         int qnum;
1797
1798         switch (queue) {
1799         case 0:
1800                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1801                 break;
1802         case 1:
1803                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1804                 break;
1805         case 2:
1806                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1807                 break;
1808         case 3:
1809                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1810                 break;
1811         default:
1812                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1813                 break;
1814         }
1815
1816         return qnum;
1817 }
1818
1819 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1820 {
1821         int qnum;
1822
1823         switch (queue) {
1824         case ATH9K_WME_AC_VO:
1825                 qnum = 0;
1826                 break;
1827         case ATH9K_WME_AC_VI:
1828                 qnum = 1;
1829                 break;
1830         case ATH9K_WME_AC_BE:
1831                 qnum = 2;
1832                 break;
1833         case ATH9K_WME_AC_BK:
1834                 qnum = 3;
1835                 break;
1836         default:
1837                 qnum = -1;
1838                 break;
1839         }
1840
1841         return qnum;
1842 }
1843
1844 /**********************/
1845 /* mac80211 callbacks */
1846 /**********************/
1847
1848 static int ath9k_start(struct ieee80211_hw *hw)
1849 {
1850         struct ath_softc *sc = hw->priv;
1851         struct ieee80211_channel *curchan = hw->conf.channel;
1852         struct ath9k_channel *init_channel;
1853         int error = 0, pos, status;
1854
1855         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1856                 "initial channel: %d MHz\n", curchan->center_freq);
1857
1858         /* setup initial channel */
1859
1860         pos = ath_get_channel(sc, curchan);
1861         if (pos == -1) {
1862                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1863                 error = -EINVAL;
1864                 goto error;
1865         }
1866
1867         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1868         sc->sc_ah->ah_channels[pos].chanmode =
1869                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1870         init_channel = &sc->sc_ah->ah_channels[pos];
1871
1872         /* Reset SERDES registers */
1873         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1874
1875         /*
1876          * The basic interface to setting the hardware in a good
1877          * state is ``reset''.  On return the hardware is known to
1878          * be powered up and with interrupts disabled.  This must
1879          * be followed by initialization of the appropriate bits
1880          * and then setup of the interrupt mask.
1881          */
1882         spin_lock_bh(&sc->sc_resetlock);
1883         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1884                             sc->tx_chan_width,
1885                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1886                             sc->sc_ht_extprotspacing, false, &status)) {
1887                 DPRINTF(sc, ATH_DBG_FATAL,
1888                         "Unable to reset hardware; hal status %u "
1889                         "(freq %u flags 0x%x)\n", status,
1890                         init_channel->channel, init_channel->channelFlags);
1891                 error = -EIO;
1892                 spin_unlock_bh(&sc->sc_resetlock);
1893                 goto error;
1894         }
1895         spin_unlock_bh(&sc->sc_resetlock);
1896
1897         /*
1898          * This is needed only to setup initial state
1899          * but it's best done after a reset.
1900          */
1901         ath_update_txpow(sc);
1902
1903         /*
1904          * Setup the hardware after reset:
1905          * The receive engine is set going.
1906          * Frame transmit is handled entirely
1907          * in the frame output path; there's nothing to do
1908          * here except setup the interrupt mask.
1909          */
1910         if (ath_startrecv(sc) != 0) {
1911                 DPRINTF(sc, ATH_DBG_FATAL,
1912                         "Unable to start recv logic\n");
1913                 error = -EIO;
1914                 goto error;
1915         }
1916
1917         /* Setup our intr mask. */
1918         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1919                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1920                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1921
1922         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1923                 sc->sc_imask |= ATH9K_INT_GTT;
1924
1925         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1926                 sc->sc_imask |= ATH9K_INT_CST;
1927
1928         /*
1929          * Enable MIB interrupts when there are hardware phy counters.
1930          * Note we only do this (at the moment) for station mode.
1931          */
1932         if (ath9k_hw_phycounters(sc->sc_ah) &&
1933             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1934              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1935                 sc->sc_imask |= ATH9K_INT_MIB;
1936         /*
1937          * Some hardware processes the TIM IE and fires an
1938          * interrupt when the TIM bit is set.  For hardware
1939          * that does, if not overridden by configuration,
1940          * enable the TIM interrupt when operating as station.
1941          */
1942         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1943             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1944             !sc->sc_config.swBeaconProcess)
1945                 sc->sc_imask |= ATH9K_INT_TIM;
1946
1947         ath_setcurmode(sc, &hw->conf);
1948
1949         sc->sc_flags &= ~SC_OP_INVALID;
1950
1951         /* Disable BMISS interrupt when we're not associated */
1952         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1953         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1954
1955         ieee80211_wake_queues(sc->hw);
1956
1957 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1958         error = ath_start_rfkill_poll(sc);
1959 #endif
1960
1961 error:
1962         return error;
1963 }
1964
1965 static int ath9k_tx(struct ieee80211_hw *hw,
1966                     struct sk_buff *skb)
1967 {
1968         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1969         struct ath_softc *sc = hw->priv;
1970         struct ath_tx_control txctl;
1971         int hdrlen, padsize;
1972
1973         memset(&txctl, 0, sizeof(struct ath_tx_control));
1974
1975         /*
1976          * As a temporary workaround, assign seq# here; this will likely need
1977          * to be cleaned up to work better with Beacon transmission and virtual
1978          * BSSes.
1979          */
1980         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1981                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1982                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1983                         sc->tx.seq_no += 0x10;
1984                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1985                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1986         }
1987
1988         /* Add the padding after the header if this is not already done */
1989         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1990         if (hdrlen & 3) {
1991                 padsize = hdrlen % 4;
1992                 if (skb_headroom(skb) < padsize)
1993                         return -1;
1994                 skb_push(skb, padsize);
1995                 memmove(skb->data, skb->data + padsize, hdrlen);
1996         }
1997
1998         /* Check if a tx queue is available */
1999
2000         txctl.txq = ath_test_get_txq(sc, skb);
2001         if (!txctl.txq)
2002                 goto exit;
2003
2004         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2005
2006         if (ath_tx_start(sc, skb, &txctl) != 0) {
2007                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2008                 goto exit;
2009         }
2010
2011         return 0;
2012 exit:
2013         dev_kfree_skb_any(skb);
2014         return 0;
2015 }
2016
2017 static void ath9k_stop(struct ieee80211_hw *hw)
2018 {
2019         struct ath_softc *sc = hw->priv;
2020
2021         if (sc->sc_flags & SC_OP_INVALID) {
2022                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2023                 return;
2024         }
2025
2026         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2027
2028         ieee80211_stop_queues(sc->hw);
2029
2030         /* make sure h/w will not generate any interrupt
2031          * before setting the invalid flag. */
2032         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2033
2034         if (!(sc->sc_flags & SC_OP_INVALID)) {
2035                 ath_draintxq(sc, false);
2036                 ath_stoprecv(sc);
2037                 ath9k_hw_phy_disable(sc->sc_ah);
2038         } else
2039                 sc->rx.rxlink = NULL;
2040
2041 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2042         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2043                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2044 #endif
2045         /* disable HAL and put h/w to sleep */
2046         ath9k_hw_disable(sc->sc_ah);
2047         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2048
2049         sc->sc_flags |= SC_OP_INVALID;
2050
2051         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2052 }
2053
2054 static int ath9k_add_interface(struct ieee80211_hw *hw,
2055                                struct ieee80211_if_init_conf *conf)
2056 {
2057         struct ath_softc *sc = hw->priv;
2058         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2059         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2060
2061         /* Support only vap for now */
2062
2063         if (sc->sc_nvaps)
2064                 return -ENOBUFS;
2065
2066         switch (conf->type) {
2067         case NL80211_IFTYPE_STATION:
2068                 ic_opmode = NL80211_IFTYPE_STATION;
2069                 break;
2070         case NL80211_IFTYPE_ADHOC:
2071                 ic_opmode = NL80211_IFTYPE_ADHOC;
2072                 break;
2073         case NL80211_IFTYPE_AP:
2074                 ic_opmode = NL80211_IFTYPE_AP;
2075                 break;
2076         default:
2077                 DPRINTF(sc, ATH_DBG_FATAL,
2078                         "Interface type %d not yet supported\n", conf->type);
2079                 return -EOPNOTSUPP;
2080         }
2081
2082         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2083
2084         /* Set the VAP opmode */
2085         avp->av_opmode = ic_opmode;
2086         avp->av_bslot = -1;
2087
2088         if (ic_opmode == NL80211_IFTYPE_AP)
2089                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2090
2091         sc->sc_vaps[0] = conf->vif;
2092         sc->sc_nvaps++;
2093
2094         /* Set the device opmode */
2095         sc->sc_ah->ah_opmode = ic_opmode;
2096
2097         if (conf->type == NL80211_IFTYPE_AP) {
2098                 /* TODO: is this a suitable place to start ANI for AP mode? */
2099                 /* Start ANI */
2100                 mod_timer(&sc->sc_ani.timer,
2101                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2102         }
2103
2104         return 0;
2105 }
2106
2107 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2108                                    struct ieee80211_if_init_conf *conf)
2109 {
2110         struct ath_softc *sc = hw->priv;
2111         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2112
2113         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2114
2115         /* Stop ANI */
2116         del_timer_sync(&sc->sc_ani.timer);
2117
2118         /* Reclaim beacon resources */
2119         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2120             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2121                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2122                 ath_beacon_return(sc, avp);
2123         }
2124
2125         sc->sc_flags &= ~SC_OP_BEACONS;
2126
2127         sc->sc_vaps[0] = NULL;
2128         sc->sc_nvaps--;
2129 }
2130
2131 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2132 {
2133         struct ath_softc *sc = hw->priv;
2134         struct ieee80211_conf *conf = &hw->conf;
2135
2136         mutex_lock(&sc->mutex);
2137         if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2138                        IEEE80211_CONF_CHANGE_HT)) {
2139                 struct ieee80211_channel *curchan = hw->conf.channel;
2140                 int pos;
2141
2142                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2143                         curchan->center_freq);
2144
2145                 pos = ath_get_channel(sc, curchan);
2146                 if (pos == -1) {
2147                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2148                                 curchan->center_freq);
2149                         mutex_unlock(&sc->mutex);
2150                         return -EINVAL;
2151                 }
2152
2153                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2154                 sc->sc_ah->ah_channels[pos].chanmode =
2155                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2156                         CHANNEL_G : CHANNEL_A;
2157
2158                 if (conf->ht.enabled) {
2159                         if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2160                             conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2161                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2162
2163                         sc->sc_ah->ah_channels[pos].chanmode =
2164                                 ath_get_extchanmode(sc, curchan,
2165                                                     conf->ht.channel_type);
2166                 }
2167
2168                 ath_update_chainmask(sc, conf->ht.enabled);
2169
2170                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2171                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2172                         mutex_unlock(&sc->mutex);
2173                         return -EINVAL;
2174                 }
2175         }
2176
2177         if (changed & IEEE80211_CONF_CHANGE_POWER)
2178                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2179
2180         mutex_unlock(&sc->mutex);
2181         return 0;
2182 }
2183
2184 static int ath9k_config_interface(struct ieee80211_hw *hw,
2185                                   struct ieee80211_vif *vif,
2186                                   struct ieee80211_if_conf *conf)
2187 {
2188         struct ath_softc *sc = hw->priv;
2189         struct ath_hal *ah = sc->sc_ah;
2190         struct ath_vap *avp = (void *)vif->drv_priv;
2191         u32 rfilt = 0;
2192         int error, i;
2193
2194         /* TODO: Need to decide which hw opmode to use for multi-interface
2195          * cases */
2196         if (vif->type == NL80211_IFTYPE_AP &&
2197             ah->ah_opmode != NL80211_IFTYPE_AP) {
2198                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2199                 ath9k_hw_setopmode(ah);
2200                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2201                 /* Request full reset to get hw opmode changed properly */
2202                 sc->sc_flags |= SC_OP_FULL_RESET;
2203         }
2204
2205         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2206             !is_zero_ether_addr(conf->bssid)) {
2207                 switch (vif->type) {
2208                 case NL80211_IFTYPE_STATION:
2209                 case NL80211_IFTYPE_ADHOC:
2210                         /* Set BSSID */
2211                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2212                         sc->sc_curaid = 0;
2213                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2214                                                sc->sc_curaid);
2215
2216                         /* Set aggregation protection mode parameters */
2217                         sc->sc_config.ath_aggr_prot = 0;
2218
2219                         DPRINTF(sc, ATH_DBG_CONFIG,
2220                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2221                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2222
2223                         /* need to reconfigure the beacon */
2224                         sc->sc_flags &= ~SC_OP_BEACONS ;
2225
2226                         break;
2227                 default:
2228                         break;
2229                 }
2230         }
2231
2232         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2233             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2234              (vif->type == NL80211_IFTYPE_AP))) {
2235                 /*
2236                  * Allocate and setup the beacon frame.
2237                  *
2238                  * Stop any previous beacon DMA.  This may be
2239                  * necessary, for example, when an ibss merge
2240                  * causes reconfiguration; we may be called
2241                  * with beacon transmission active.
2242                  */
2243                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2244
2245                 error = ath_beacon_alloc(sc, 0);
2246                 if (error != 0)
2247                         return error;
2248
2249                 ath_beacon_sync(sc, 0);
2250         }
2251
2252         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2253         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2254                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2255                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2256                                 ath9k_hw_keysetmac(sc->sc_ah,
2257                                                    (u16)i,
2258                                                    sc->sc_curbssid);
2259         }
2260
2261         /* Only legacy IBSS for now */
2262         if (vif->type == NL80211_IFTYPE_ADHOC)
2263                 ath_update_chainmask(sc, 0);
2264
2265         return 0;
2266 }
2267
2268 #define SUPPORTED_FILTERS                       \
2269         (FIF_PROMISC_IN_BSS |                   \
2270         FIF_ALLMULTI |                          \
2271         FIF_CONTROL |                           \
2272         FIF_OTHER_BSS |                         \
2273         FIF_BCN_PRBRESP_PROMISC |               \
2274         FIF_FCSFAIL)
2275
2276 /* FIXME: sc->sc_full_reset ? */
2277 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2278                                    unsigned int changed_flags,
2279                                    unsigned int *total_flags,
2280                                    int mc_count,
2281                                    struct dev_mc_list *mclist)
2282 {
2283         struct ath_softc *sc = hw->priv;
2284         u32 rfilt;
2285
2286         changed_flags &= SUPPORTED_FILTERS;
2287         *total_flags &= SUPPORTED_FILTERS;
2288
2289         sc->rx.rxfilter = *total_flags;
2290         rfilt = ath_calcrxfilter(sc);
2291         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2292
2293         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2294                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2295                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2296         }
2297
2298         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2299 }
2300
2301 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2302                              struct ieee80211_vif *vif,
2303                              enum sta_notify_cmd cmd,
2304                              struct ieee80211_sta *sta)
2305 {
2306         struct ath_softc *sc = hw->priv;
2307
2308         switch (cmd) {
2309         case STA_NOTIFY_ADD:
2310                 ath_node_attach(sc, sta);
2311                 break;
2312         case STA_NOTIFY_REMOVE:
2313                 ath_node_detach(sc, sta);
2314                 break;
2315         default:
2316                 break;
2317         }
2318 }
2319
2320 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2321                          u16 queue,
2322                          const struct ieee80211_tx_queue_params *params)
2323 {
2324         struct ath_softc *sc = hw->priv;
2325         struct ath9k_tx_queue_info qi;
2326         int ret = 0, qnum;
2327
2328         if (queue >= WME_NUM_AC)
2329                 return 0;
2330
2331         qi.tqi_aifs = params->aifs;
2332         qi.tqi_cwmin = params->cw_min;
2333         qi.tqi_cwmax = params->cw_max;
2334         qi.tqi_burstTime = params->txop;
2335         qnum = ath_get_hal_qnum(queue, sc);
2336
2337         DPRINTF(sc, ATH_DBG_CONFIG,
2338                 "Configure tx [queue/halq] [%d/%d],  "
2339                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2340                 queue, qnum, params->aifs, params->cw_min,
2341                 params->cw_max, params->txop);
2342
2343         ret = ath_txq_update(sc, qnum, &qi);
2344         if (ret)
2345                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2346
2347         return ret;
2348 }
2349
2350 static int ath9k_set_key(struct ieee80211_hw *hw,
2351                          enum set_key_cmd cmd,
2352                          const u8 *local_addr,
2353                          const u8 *addr,
2354                          struct ieee80211_key_conf *key)
2355 {
2356         struct ath_softc *sc = hw->priv;
2357         int ret = 0;
2358
2359         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2360
2361         switch (cmd) {
2362         case SET_KEY:
2363                 ret = ath_key_config(sc, addr, key);
2364                 if (ret >= 0) {
2365                         key->hw_key_idx = ret;
2366                         /* push IV and Michael MIC generation to stack */
2367                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2368                         if (key->alg == ALG_TKIP)
2369                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2370                         ret = 0;
2371                 }
2372                 break;
2373         case DISABLE_KEY:
2374                 ath_key_delete(sc, key);
2375                 break;
2376         default:
2377                 ret = -EINVAL;
2378         }
2379
2380         return ret;
2381 }
2382
2383 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2384                                    struct ieee80211_vif *vif,
2385                                    struct ieee80211_bss_conf *bss_conf,
2386                                    u32 changed)
2387 {
2388         struct ath_softc *sc = hw->priv;
2389
2390         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2391                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2392                         bss_conf->use_short_preamble);
2393                 if (bss_conf->use_short_preamble)
2394                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2395                 else
2396                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2397         }
2398
2399         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2400                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2401                         bss_conf->use_cts_prot);
2402                 if (bss_conf->use_cts_prot &&
2403                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2404                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2405                 else
2406                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2407         }
2408
2409         if (changed & BSS_CHANGED_ASSOC) {
2410                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2411                         bss_conf->assoc);
2412                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2413         }
2414 }
2415
2416 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2417 {
2418         u64 tsf;
2419         struct ath_softc *sc = hw->priv;
2420         struct ath_hal *ah = sc->sc_ah;
2421
2422         tsf = ath9k_hw_gettsf64(ah);
2423
2424         return tsf;
2425 }
2426
2427 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2428 {
2429         struct ath_softc *sc = hw->priv;
2430         struct ath_hal *ah = sc->sc_ah;
2431
2432         ath9k_hw_reset_tsf(ah);
2433 }
2434
2435 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2436                        enum ieee80211_ampdu_mlme_action action,
2437                        struct ieee80211_sta *sta,
2438                        u16 tid, u16 *ssn)
2439 {
2440         struct ath_softc *sc = hw->priv;
2441         int ret = 0;
2442
2443         switch (action) {
2444         case IEEE80211_AMPDU_RX_START:
2445                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2446                         ret = -ENOTSUPP;
2447                 break;
2448         case IEEE80211_AMPDU_RX_STOP:
2449                 break;
2450         case IEEE80211_AMPDU_TX_START:
2451                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2452                 if (ret < 0)
2453                         DPRINTF(sc, ATH_DBG_FATAL,
2454                                 "Unable to start TX aggregation\n");
2455                 else
2456                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2457                 break;
2458         case IEEE80211_AMPDU_TX_STOP:
2459                 ret = ath_tx_aggr_stop(sc, sta, tid);
2460                 if (ret < 0)
2461                         DPRINTF(sc, ATH_DBG_FATAL,
2462                                 "Unable to stop TX aggregation\n");
2463
2464                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2465                 break;
2466         case IEEE80211_AMPDU_TX_RESUME:
2467                 ath_tx_aggr_resume(sc, sta, tid);
2468                 break;
2469         default:
2470                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2471         }
2472
2473         return ret;
2474 }
2475
2476 static struct ieee80211_ops ath9k_ops = {
2477         .tx                 = ath9k_tx,
2478         .start              = ath9k_start,
2479         .stop               = ath9k_stop,
2480         .add_interface      = ath9k_add_interface,
2481         .remove_interface   = ath9k_remove_interface,
2482         .config             = ath9k_config,
2483         .config_interface   = ath9k_config_interface,
2484         .configure_filter   = ath9k_configure_filter,
2485         .sta_notify         = ath9k_sta_notify,
2486         .conf_tx            = ath9k_conf_tx,
2487         .bss_info_changed   = ath9k_bss_info_changed,
2488         .set_key            = ath9k_set_key,
2489         .get_tsf            = ath9k_get_tsf,
2490         .reset_tsf          = ath9k_reset_tsf,
2491         .ampdu_action       = ath9k_ampdu_action,
2492 };
2493
2494 static struct {
2495         u32 version;
2496         const char * name;
2497 } ath_mac_bb_names[] = {
2498         { AR_SREV_VERSION_5416_PCI,     "5416" },
2499         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2500         { AR_SREV_VERSION_9100,         "9100" },
2501         { AR_SREV_VERSION_9160,         "9160" },
2502         { AR_SREV_VERSION_9280,         "9280" },
2503         { AR_SREV_VERSION_9285,         "9285" }
2504 };
2505
2506 static struct {
2507         u16 version;
2508         const char * name;
2509 } ath_rf_names[] = {
2510         { 0,                            "5133" },
2511         { AR_RAD5133_SREV_MAJOR,        "5133" },
2512         { AR_RAD5122_SREV_MAJOR,        "5122" },
2513         { AR_RAD2133_SREV_MAJOR,        "2133" },
2514         { AR_RAD2122_SREV_MAJOR,        "2122" }
2515 };
2516
2517 /*
2518  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2519  */
2520 static const char *
2521 ath_mac_bb_name(u32 mac_bb_version)
2522 {
2523         int i;
2524
2525         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2526                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2527                         return ath_mac_bb_names[i].name;
2528                 }
2529         }
2530
2531         return "????";
2532 }
2533
2534 /*
2535  * Return the RF name. "????" is returned if the RF is unknown.
2536  */
2537 static const char *
2538 ath_rf_name(u16 rf_version)
2539 {
2540         int i;
2541
2542         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2543                 if (ath_rf_names[i].version == rf_version) {
2544                         return ath_rf_names[i].name;
2545                 }
2546         }
2547
2548         return "????";
2549 }
2550
2551 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2552 {
2553         void __iomem *mem;
2554         struct ath_softc *sc;
2555         struct ieee80211_hw *hw;
2556         u8 csz;
2557         u32 val;
2558         int ret = 0;
2559         struct ath_hal *ah;
2560
2561         if (pci_enable_device(pdev))
2562                 return -EIO;
2563
2564         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2565
2566         if (ret) {
2567                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2568                 goto bad;
2569         }
2570
2571         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2572
2573         if (ret) {
2574                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2575                         "DMA enable failed\n");
2576                 goto bad;
2577         }
2578
2579         /*
2580          * Cache line size is used to size and align various
2581          * structures used to communicate with the hardware.
2582          */
2583         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2584         if (csz == 0) {
2585                 /*
2586                  * Linux 2.4.18 (at least) writes the cache line size
2587                  * register as a 16-bit wide register which is wrong.
2588                  * We must have this setup properly for rx buffer
2589                  * DMA to work so force a reasonable value here if it
2590                  * comes up zero.
2591                  */
2592                 csz = L1_CACHE_BYTES / sizeof(u32);
2593                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2594         }
2595         /*
2596          * The default setting of latency timer yields poor results,
2597          * set it to the value used by other systems. It may be worth
2598          * tweaking this setting more.
2599          */
2600         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2601
2602         pci_set_master(pdev);
2603
2604         /*
2605          * Disable the RETRY_TIMEOUT register (0x41) to keep
2606          * PCI Tx retries from interfering with C3 CPU state.
2607          */
2608         pci_read_config_dword(pdev, 0x40, &val);
2609         if ((val & 0x0000ff00) != 0)
2610                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2611
2612         ret = pci_request_region(pdev, 0, "ath9k");
2613         if (ret) {
2614                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2615                 ret = -ENODEV;
2616                 goto bad;
2617         }
2618
2619         mem = pci_iomap(pdev, 0, 0);
2620         if (!mem) {
2621                 printk(KERN_ERR "PCI memory map error\n") ;
2622                 ret = -EIO;
2623                 goto bad1;
2624         }
2625
2626         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2627         if (hw == NULL) {
2628                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2629                 goto bad2;
2630         }
2631
2632         SET_IEEE80211_DEV(hw, &pdev->dev);
2633         pci_set_drvdata(pdev, hw);
2634
2635         sc = hw->priv;
2636         sc->hw = hw;
2637         sc->pdev = pdev;
2638         sc->mem = mem;
2639
2640         if (ath_attach(id->device, sc) != 0) {
2641                 ret = -ENODEV;
2642                 goto bad3;
2643         }
2644
2645         /* setup interrupt service routine */
2646
2647         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2648                 printk(KERN_ERR "%s: request_irq failed\n",
2649                         wiphy_name(hw->wiphy));
2650                 ret = -EIO;
2651                 goto bad4;
2652         }
2653
2654         ah = sc->sc_ah;
2655         printk(KERN_INFO
2656                "%s: Atheros AR%s MAC/BB Rev:%x "
2657                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2658                wiphy_name(hw->wiphy),
2659                ath_mac_bb_name(ah->ah_macVersion),
2660                ah->ah_macRev,
2661                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2662                ah->ah_phyRev,
2663                (unsigned long)mem, pdev->irq);
2664
2665         return 0;
2666 bad4:
2667         ath_detach(sc);
2668 bad3:
2669         ieee80211_free_hw(hw);
2670 bad2:
2671         pci_iounmap(pdev, mem);
2672 bad1:
2673         pci_release_region(pdev, 0);
2674 bad:
2675         pci_disable_device(pdev);
2676         return ret;
2677 }
2678
2679 static void ath_pci_remove(struct pci_dev *pdev)
2680 {
2681         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2682         struct ath_softc *sc = hw->priv;
2683
2684         ath_detach(sc);
2685         if (pdev->irq)
2686                 free_irq(pdev->irq, sc);
2687         pci_iounmap(pdev, sc->mem);
2688         pci_release_region(pdev, 0);
2689         pci_disable_device(pdev);
2690         ieee80211_free_hw(hw);
2691 }
2692
2693 #ifdef CONFIG_PM
2694
2695 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2696 {
2697         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2698         struct ath_softc *sc = hw->priv;
2699
2700         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2701
2702 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2703         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2704                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2705 #endif
2706
2707         pci_save_state(pdev);
2708         pci_disable_device(pdev);
2709         pci_set_power_state(pdev, 3);
2710
2711         return 0;
2712 }
2713
2714 static int ath_pci_resume(struct pci_dev *pdev)
2715 {
2716         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2717         struct ath_softc *sc = hw->priv;
2718         u32 val;
2719         int err;
2720
2721         err = pci_enable_device(pdev);
2722         if (err)
2723                 return err;
2724         pci_restore_state(pdev);
2725         /*
2726          * Suspend/Resume resets the PCI configuration space, so we have to
2727          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2728          * PCI Tx retries from interfering with C3 CPU state
2729          */
2730         pci_read_config_dword(pdev, 0x40, &val);
2731         if ((val & 0x0000ff00) != 0)
2732                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2733
2734         /* Enable LED */
2735         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2736                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2737         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2738
2739 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2740         /*
2741          * check the h/w rfkill state on resume
2742          * and start the rfkill poll timer
2743          */
2744         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2745                 queue_delayed_work(sc->hw->workqueue,
2746                                    &sc->rf_kill.rfkill_poll, 0);
2747 #endif
2748
2749         return 0;
2750 }
2751
2752 #endif /* CONFIG_PM */
2753
2754 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2755
2756 static struct pci_driver ath_pci_driver = {
2757         .name       = "ath9k",
2758         .id_table   = ath_pci_id_table,
2759         .probe      = ath_pci_probe,
2760         .remove     = ath_pci_remove,
2761 #ifdef CONFIG_PM
2762         .suspend    = ath_pci_suspend,
2763         .resume     = ath_pci_resume,
2764 #endif /* CONFIG_PM */
2765 };
2766
2767 static int __init init_ath_pci(void)
2768 {
2769         int error;
2770
2771         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2772
2773         /* Register rate control algorithm */
2774         error = ath_rate_control_register();
2775         if (error != 0) {
2776                 printk(KERN_ERR
2777                         "Unable to register rate control algorithm: %d\n",
2778                         error);
2779                 ath_rate_control_unregister();
2780                 return error;
2781         }
2782
2783         if (pci_register_driver(&ath_pci_driver) < 0) {
2784                 printk(KERN_ERR
2785                         "ath_pci: No devices found, driver not installed.\n");
2786                 ath_rate_control_unregister();
2787                 pci_unregister_driver(&ath_pci_driver);
2788                 return -ENODEV;
2789         }
2790
2791         return 0;
2792 }
2793 module_init(init_ath_pci);
2794
2795 static void __exit exit_ath_pci(void)
2796 {
2797         ath_rate_control_unregister();
2798         pci_unregister_driver(&ath_pci_driver);
2799         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2800 }
2801 module_exit(exit_ath_pci);