drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42 static void ath_cleanup(struct ath_softc *sc);
  43
  44 /* return bus cachesize in 4B word units */
  45
  46 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
  47 {
  48         u8 u8tmp;
  49
  50         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
  51                              (u8 *)&u8tmp);
  52         *csz = (int)u8tmp;
  53
  54         /*
  55          * This check was put in to avoid "unplesant" consequences if
  56          * the bootrom has not fully initialized all PCI devices.
  57          * Sometimes the cache line size register is not set
  58          */
  59
  60         if (*csz == 0)
  61                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  62 }
  63
  64 static void ath_cache_conf_rate(struct ath_softc *sc,
  65                                 struct ieee80211_conf *conf)
  66 {
  67         switch (conf->channel->band) {
  68         case IEEE80211_BAND_2GHZ:
  69                 if (conf_is_ht20(conf))
  70                         sc->cur_rate_table =
  71                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  72                 else if (conf_is_ht40_minus(conf))
  73                         sc->cur_rate_table =
  74                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  75                 else if (conf_is_ht40_plus(conf))
  76                         sc->cur_rate_table =
  77                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  78                 else
  79                         sc->cur_rate_table =
  80                           sc->hw_rate_table[ATH9K_MODE_11G];
  81                 break;
  82         case IEEE80211_BAND_5GHZ:
  83                 if (conf_is_ht20(conf))
  84                         sc->cur_rate_table =
  85                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  86                 else if (conf_is_ht40_minus(conf))
  87                         sc->cur_rate_table =
  88                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  89                 else if (conf_is_ht40_plus(conf))
  90                         sc->cur_rate_table =
  91                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  92                 else
  93                         sc->cur_rate_table =
  94                           sc->hw_rate_table[ATH9K_MODE_11A];
  95                 break;
  96         default:
  97                 BUG_ON(1);
  98                 break;
  99         }
 100 }
 101
 102 static void ath_update_txpow(struct ath_softc *sc)
 103 {
 104         struct ath_hal *ah = sc->sc_ah;
 105         u32 txpow;
 106
 107         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 108                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 109                 /* read back in case value is clamped */
 110                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 111                 sc->sc_curtxpow = txpow;
 112         }
 113 }
 114
 115 static u8 parse_mpdudensity(u8 mpdudensity)
 116 {
 117         /*
 118          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 119          *   0 for no restriction
 120          *   1 for 1/4 us
 121          *   2 for 1/2 us
 122          *   3 for 1 us
 123          *   4 for 2 us
 124          *   5 for 4 us
 125          *   6 for 8 us
 126          *   7 for 16 us
 127          */
 128         switch (mpdudensity) {
 129         case 0:
 130                 return 0;
 131         case 1:
 132         case 2:
 133         case 3:
 134                 /* Our lower layer calculations limit our precision to
 135                    1 microsecond */
 136                 return 1;
 137         case 4:
 138                 return 2;
 139         case 5:
 140                 return 4;
 141         case 6:
 142                 return 8;
 143         case 7:
 144                 return 16;
 145         default:
 146                 return 0;
 147         }
 148 }
 149
 150 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 151 {
 152         struct ath_rate_table *rate_table = NULL;
 153         struct ieee80211_supported_band *sband;
 154         struct ieee80211_rate *rate;
 155         int i, maxrates;
 156
 157         switch (band) {
 158         case IEEE80211_BAND_2GHZ:
 159                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 160                 break;
 161         case IEEE80211_BAND_5GHZ:
 162                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 163                 break;
 164         default:
 165                 break;
 166         }
 167
 168         if (rate_table == NULL)
 169                 return;
 170
 171         sband = &sc->sbands[band];
 172         rate = sc->rates[band];
 173
 174         if (rate_table->rate_cnt > ATH_RATE_MAX)
 175                 maxrates = ATH_RATE_MAX;
 176         else
 177                 maxrates = rate_table->rate_cnt;
 178
 179         for (i = 0; i < maxrates; i++) {
 180                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 181                 rate[i].hw_value = rate_table->info[i].ratecode;
 182                 sband->n_bitrates++;
 183                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 184                         rate[i].bitrate / 10, rate[i].hw_value);
 185         }
 186 }
 187
 188 static int ath_setup_channels(struct ath_softc *sc)
 189 {
 190         struct ath_hal *ah = sc->sc_ah;
 191         int nchan, i, a = 0, b = 0;
 192         u8 regclassids[ATH_REGCLASSIDS_MAX];
 193         u32 nregclass = 0;
 194         struct ieee80211_supported_band *band_2ghz;
 195         struct ieee80211_supported_band *band_5ghz;
 196         struct ieee80211_channel *chan_2ghz;
 197         struct ieee80211_channel *chan_5ghz;
 198         struct ath9k_channel *c;
 199
 200         /* Fill in ah->ah_channels */
 201         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 202                                       regclassids, ATH_REGCLASSIDS_MAX,
 203                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 204                 u32 rd = ah->ah_currentRD;
 205                 DPRINTF(sc, ATH_DBG_FATAL,
 206                         "Unable to collect channel list; "
 207                         "regdomain likely %u country code %u\n",
 208                         rd, CTRY_DEFAULT);
 209                 return -EINVAL;
 210         }
 211
 212         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 213         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 214         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 215         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 216
 217         for (i = 0; i < nchan; i++) {
 218                 c = &ah->ah_channels[i];
 219                 if (IS_CHAN_2GHZ(c)) {
 220                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 221                         chan_2ghz[a].center_freq = c->channel;
 222                         chan_2ghz[a].max_power = c->maxTxPower;
 223                         c->chan = &chan_2ghz[a];
 224
 225                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 226                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 227                         if (c->channelFlags & CHANNEL_PASSIVE)
 228                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 229
 230                         band_2ghz->n_channels = ++a;
 231
 232                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 233                                 "channelFlags: 0x%x\n",
 234                                 c->channel, c->channelFlags);
 235                 } else if (IS_CHAN_5GHZ(c)) {
 236                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 237                         chan_5ghz[b].center_freq = c->channel;
 238                         chan_5ghz[b].max_power = c->maxTxPower;
 239                         c->chan = &chan_5ghz[a];
 240
 241                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 242                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 243                         if (c->channelFlags & CHANNEL_PASSIVE)
 244                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 245
 246                         band_5ghz->n_channels = ++b;
 247
 248                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 249                                 "channelFlags: 0x%x\n",
 250                                 c->channel, c->channelFlags);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * Set/change channels.  If the channel is really being changed, it's done
 259  * by reseting the chip.  To accomplish this we must first cleanup any pending
 260  * DMA, then restart stuff.
 261 */
 262 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 263 {
 264         struct ath_hal *ah = sc->sc_ah;
 265         bool fastcc = true, stopped;
 266         struct ieee80211_hw *hw = sc->hw;
 267         struct ieee80211_channel *channel = hw->conf.channel;
 268         int r;
 269
 270         if (sc->sc_flags & SC_OP_INVALID)
 271                 return -EIO;
 272
 273         /*
 274          * This is only performed if the channel settings have
 275          * actually changed.
 276          *
 277          * To switch channels clear any pending DMA operations;
 278          * wait long enough for the RX fifo to drain, reset the
 279          * hardware at the new frequency, and then re-enable
 280          * the relevant bits of the h/w.
 281          */
 282         ath9k_hw_set_interrupts(ah, 0);
 283         ath_draintxq(sc, false);
 284         stopped = ath_stoprecv(sc);
 285
 286         /* XXX: do not flush receive queue here. We don't want
 287          * to flush data frames already in queue because of
 288          * changing channel. */
 289
 290         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 291                 fastcc = false;
 292
 293         DPRINTF(sc, ATH_DBG_CONFIG,
 294                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 295                 sc->sc_ah->ah_curchan->channel,
 296                 channel->center_freq, sc->tx_chan_width);
 297
 298         spin_lock_bh(&sc->sc_resetlock);
 299
 300         r = ath9k_hw_reset(ah, hchan, fastcc);
 301         if (r) {
 302                 DPRINTF(sc, ATH_DBG_FATAL,
 303                         "Unable to reset channel (%u Mhz) "
 304                         "reset status %u\n",
 305                         channel->center_freq, r);
 306                 spin_unlock_bh(&sc->sc_resetlock);
 307                 return r;
 308         }
 309         spin_unlock_bh(&sc->sc_resetlock);
 310
 311         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 312         sc->sc_flags &= ~SC_OP_FULL_RESET;
 313
 314         if (ath_startrecv(sc) != 0) {
 315                 DPRINTF(sc, ATH_DBG_FATAL,
 316                         "Unable to restart recv logic\n");
 317                 return -EIO;
 318         }
 319
 320         ath_cache_conf_rate(sc, &hw->conf);
 321         ath_update_txpow(sc);
 322         ath9k_hw_set_interrupts(ah, sc->sc_imask);
 323         return 0;
 324 }
 325
 326 /*
 327  *  This routine performs the periodic noise floor calibration function
 328  *  that is used to adjust and optimize the chip performance.  This
 329  *  takes environmental changes (location, temperature) into account.
 330  *  When the task is complete, it reschedules itself depending on the
 331  *  appropriate interval that was calculated.
 332  */
 333 static void ath_ani_calibrate(unsigned long data)
 334 {
 335         struct ath_softc *sc;
 336         struct ath_hal *ah;
 337         bool longcal = false;
 338         bool shortcal = false;
 339         bool aniflag = false;
 340         unsigned int timestamp = jiffies_to_msecs(jiffies);
 341         u32 cal_interval;
 342
 343         sc = (struct ath_softc *)data;
 344         ah = sc->sc_ah;
 345
 346         /*
 347         * don't calibrate when we're scanning.
 348         * we are most likely not on our home channel.
 349         */
 350         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 351                 return;
 352
 353         /* Long calibration runs independently of short calibration. */
 354         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 355                 longcal = true;
 356                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 357                 sc->sc_ani.sc_longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while sc_caldone is false */
 361         if (!sc->sc_ani.sc_caldone) {
 362                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 363                     ATH_SHORT_CALINTERVAL) {
 364                         shortcal = true;
 365                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 366                         sc->sc_ani.sc_shortcal_timer = timestamp;
 367                         sc->sc_ani.sc_resetcal_timer = timestamp;
 368                 }
 369         } else {
 370                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 371                     ATH_RESTART_CALINTERVAL) {
 372                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
 373                         if (sc->sc_ani.sc_caldone)
 374                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 375                 }
 376         }
 377
 378         /* Verify whether we must check ANI */
 379         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 380            ATH_ANI_POLLINTERVAL) {
 381                 aniflag = true;
 382                 sc->sc_ani.sc_checkani_timer = timestamp;
 383         }
 384
 385         /* Skip all processing if there's nothing to do. */
 386         if (longcal || shortcal || aniflag) {
 387                 /* Call ANI routine if necessary */
 388                 if (aniflag)
 389                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 390                                              ah->ah_curchan);
 391
 392                 /* Perform calibration if necessary */
 393                 if (longcal || shortcal) {
 394                         bool iscaldone = false;
 395
 396                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 397                                                sc->sc_rx_chainmask, longcal,
 398                                                &iscaldone)) {
 399                                 if (longcal)
 400                                         sc->sc_ani.sc_noise_floor =
 401                                                 ath9k_hw_getchan_noise(ah,
 402                                                                ah->ah_curchan);
 403
 404                                 DPRINTF(sc, ATH_DBG_ANI,
 405                                         "calibrate chan %u/%x nf: %d\n",
 406                                         ah->ah_curchan->channel,
 407                                         ah->ah_curchan->channelFlags,
 408                                         sc->sc_ani.sc_noise_floor);
 409                         } else {
 410                                 DPRINTF(sc, ATH_DBG_ANY,
 411                                         "calibrate chan %u/%x failed\n",
 412                                         ah->ah_curchan->channel,
 413                                         ah->ah_curchan->channelFlags);
 414                         }
 415                         sc->sc_ani.sc_caldone = iscaldone;
 416                 }
 417         }
 418
 419         /*
 420         * Set timer interval based on previous results.
 421         * The interval must be the shortest necessary to satisfy ANI,
 422         * short calibration and long calibration.
 423         */
 424         cal_interval = ATH_LONG_CALINTERVAL;
 425         if (sc->sc_ah->ah_config.enable_ani)
 426                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 427         if (!sc->sc_ani.sc_caldone)
 428                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 429
 430         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 431 }
 432
 433 /*
 434  * Update tx/rx chainmask. For legacy association,
 435  * hard code chainmask to 1x1, for 11n association, use
 436  * the chainmask configuration, for bt coexistence, use
 437  * the chainmask configuration even in legacy mode.
 438  */
 439 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 440 {
 441         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 442         if (is_ht ||
 443             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 444                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 445                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 446         } else {
 447                 sc->sc_tx_chainmask = 1;
 448                 sc->sc_rx_chainmask = 1;
 449         }
 450
 451         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 452                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 453 }
 454
 455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 456 {
 457         struct ath_node *an;
 458
 459         an = (struct ath_node *)sta->drv_priv;
 460
 461         if (sc->sc_flags & SC_OP_TXAGGR)
 462                 ath_tx_node_init(sc, an);
 463
 464         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 465                              sta->ht_cap.ampdu_factor);
 466         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 467 }
 468
 469 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 470 {
 471         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 472
 473         if (sc->sc_flags & SC_OP_TXAGGR)
 474                 ath_tx_node_cleanup(sc, an);
 475 }
 476
 477 static void ath9k_tasklet(unsigned long data)
 478 {
 479         struct ath_softc *sc = (struct ath_softc *)data;
 480         u32 status = sc->sc_intrstatus;
 481
 482         if (status & ATH9K_INT_FATAL) {
 483                 /* need a chip reset */
 484                 ath_reset(sc, false);
 485                 return;
 486         } else {
 487
 488                 if (status &
 489                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 490                         spin_lock_bh(&sc->rx.rxflushlock);
 491                         ath_rx_tasklet(sc, 0);
 492                         spin_unlock_bh(&sc->rx.rxflushlock);
 493                 }
 494                 /* XXX: optimize this */
 495                 if (status & ATH9K_INT_TX)
 496                         ath_tx_tasklet(sc);
 497         }
 498
 499         /* re-enable hardware interrupt */
 500         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 501 }
 502
 503 static irqreturn_t ath_isr(int irq, void *dev)
 504 {
 505         struct ath_softc *sc = dev;
 506         struct ath_hal *ah = sc->sc_ah;
 507         enum ath9k_int status;
 508         bool sched = false;
 509
 510         do {
 511                 if (sc->sc_flags & SC_OP_INVALID) {
 512                         /*
 513                          * The hardware is not ready/present, don't
 514                          * touch anything. Note this can happen early
 515                          * on if the IRQ is shared.
 516                          */
 517                         return IRQ_NONE;
 518                 }
 519                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 520                         return IRQ_NONE;
 521                 }
 522
 523                 /*
 524                  * Figure out the reason(s) for the interrupt.  Note
 525                  * that the hal returns a pseudo-ISR that may include
 526                  * bits we haven't explicitly enabled so we mask the
 527                  * value to insure we only process bits we requested.
 528                  */
 529                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 530
 531                 status &= sc->sc_imask; /* discard unasked-for bits */
 532
 533                 /*
 534                  * If there are no status bits set, then this interrupt was not
 535                  * for me (should have been caught above).
 536                  */
 537                 if (!status)
 538                         return IRQ_NONE;
 539
 540                 sc->sc_intrstatus = status;
 541
 542                 if (status & ATH9K_INT_FATAL) {
 543                         /* need a chip reset */
 544                         sched = true;
 545                 } else if (status & ATH9K_INT_RXORN) {
 546                         /* need a chip reset */
 547                         sched = true;
 548                 } else {
 549                         if (status & ATH9K_INT_SWBA) {
 550                                 /* schedule a tasklet for beacon handling */
 551                                 tasklet_schedule(&sc->bcon_tasklet);
 552                         }
 553                         if (status & ATH9K_INT_RXEOL) {
 554                                 /*
 555                                  * NB: the hardware should re-read the link when
 556                                  *     RXE bit is written, but it doesn't work
 557                                  *     at least on older hardware revs.
 558                                  */
 559                                 sched = true;
 560                         }
 561
 562                         if (status & ATH9K_INT_TXURN)
 563                                 /* bump tx trigger level */
 564                                 ath9k_hw_updatetxtriglevel(ah, true);
 565                         /* XXX: optimize this */
 566                         if (status & ATH9K_INT_RX)
 567                                 sched = true;
 568                         if (status & ATH9K_INT_TX)
 569                                 sched = true;
 570                         if (status & ATH9K_INT_BMISS)
 571                                 sched = true;
 572                         /* carrier sense timeout */
 573                         if (status & ATH9K_INT_CST)
 574                                 sched = true;
 575                         if (status & ATH9K_INT_MIB) {
 576                                 /*
 577                                  * Disable interrupts until we service the MIB
 578                                  * interrupt; otherwise it will continue to
 579                                  * fire.
 580                                  */
 581                                 ath9k_hw_set_interrupts(ah, 0);
 582                                 /*
 583                                  * Let the hal handle the event. We assume
 584                                  * it will clear whatever condition caused
 585                                  * the interrupt.
 586                                  */
 587                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 588                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 589                         }
 590                         if (status & ATH9K_INT_TIM_TIMER) {
 591                                 if (!(ah->ah_caps.hw_caps &
 592                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 593                                         /* Clear RxAbort bit so that we can
 594                                          * receive frames */
 595                                         ath9k_hw_setrxabort(ah, 0);
 596                                         sched = true;
 597                                 }
 598                         }
 599                 }
 600         } while (0);
 601
 602         ath_debug_stat_interrupt(sc, status);
 603
 604         if (sched) {
 605                 /* turn off every interrupt except SWBA */
 606                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 607                 tasklet_schedule(&sc->intr_tq);
 608         }
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 static int ath_get_channel(struct ath_softc *sc,
 614                            struct ieee80211_channel *chan)
 615 {
 616         int i;
 617
 618         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 619                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 620                         return i;
 621         }
 622
 623         return -1;
 624 }
 625
 626 static u32 ath_get_extchanmode(struct ath_softc *sc,
 627                                struct ieee80211_channel *chan,
 628                                enum nl80211_channel_type channel_type)
 629 {
 630         u32 chanmode = 0;
 631
 632         switch (chan->band) {
 633         case IEEE80211_BAND_2GHZ:
 634                 switch(channel_type) {
 635                 case NL80211_CHAN_NO_HT:
 636                 case NL80211_CHAN_HT20:
 637                         chanmode = CHANNEL_G_HT20;
 638                         break;
 639                 case NL80211_CHAN_HT40PLUS:
 640                         chanmode = CHANNEL_G_HT40PLUS;
 641                         break;
 642                 case NL80211_CHAN_HT40MINUS:
 643                         chanmode = CHANNEL_G_HT40MINUS;
 644                         break;
 645                 }
 646                 break;
 647         case IEEE80211_BAND_5GHZ:
 648                 switch(channel_type) {
 649                 case NL80211_CHAN_NO_HT:
 650                 case NL80211_CHAN_HT20:
 651                         chanmode = CHANNEL_A_HT20;
 652                         break;
 653                 case NL80211_CHAN_HT40PLUS:
 654                         chanmode = CHANNEL_A_HT40PLUS;
 655                         break;
 656                 case NL80211_CHAN_HT40MINUS:
 657                         chanmode = CHANNEL_A_HT40MINUS;
 658                         break;
 659                 }
 660                 break;
 661         default:
 662                 break;
 663         }
 664
 665         return chanmode;
 666 }
 667
 668 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 669                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 670 {
 671         bool status;
 672
 673         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 674                 keyix, hk, mac, false);
 675
 676         return status != false;
 677 }
 678
 679 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 680                            struct ath9k_keyval *hk,
 681                            const u8 *addr)
 682 {
 683         const u8 *key_rxmic;
 684         const u8 *key_txmic;
 685
 686         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 687         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 688
 689         if (addr == NULL) {
 690                 /* Group key installation */
 691                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 692                 return ath_keyset(sc, keyix, hk, addr);
 693         }
 694         if (!sc->sc_splitmic) {
 695                 /*
 696                  * data key goes at first index,
 697                  * the hal handles the MIC keys at index+64.
 698                  */
 699                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 700                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 701                 return ath_keyset(sc, keyix, hk, addr);
 702         }
 703         /*
 704          * TX key goes at first index, RX key at +32.
 705          * The hal handles the MIC keys at index+64.
 706          */
 707         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 708         if (!ath_keyset(sc, keyix, hk, NULL)) {
 709                 /* Txmic entry failed. No need to proceed further */
 710                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 711                         "Setting TX MIC Key Failed\n");
 712                 return 0;
 713         }
 714
 715         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 716         /* XXX delete tx key on failure? */
 717         return ath_keyset(sc, keyix + 32, hk, addr);
 718 }
 719
 720 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 721 {
 722         int i;
 723
 724         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 725                 if (test_bit(i, sc->sc_keymap) ||
 726                     test_bit(i + 64, sc->sc_keymap))
 727                         continue; /* At least one part of TKIP key allocated */
 728                 if (sc->sc_splitmic &&
 729                     (test_bit(i + 32, sc->sc_keymap) ||
 730                      test_bit(i + 64 + 32, sc->sc_keymap)))
 731                         continue; /* At least one part of TKIP key allocated */
 732
 733                 /* Found a free slot for a TKIP key */
 734                 return i;
 735         }
 736         return -1;
 737 }
 738
 739 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 740 {
 741         int i;
 742
 743         /* First, try to find slots that would not be available for TKIP. */
 744         if (sc->sc_splitmic) {
 745                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 746                         if (!test_bit(i, sc->sc_keymap) &&
 747                             (test_bit(i + 32, sc->sc_keymap) ||
 748                              test_bit(i + 64, sc->sc_keymap) ||
 749                              test_bit(i + 64 + 32, sc->sc_keymap)))
 750                                 return i;
 751                         if (!test_bit(i + 32, sc->sc_keymap) &&
 752                             (test_bit(i, sc->sc_keymap) ||
 753                              test_bit(i + 64, sc->sc_keymap) ||
 754                              test_bit(i + 64 + 32, sc->sc_keymap)))
 755                                 return i + 32;
 756                         if (!test_bit(i + 64, sc->sc_keymap) &&
 757                             (test_bit(i , sc->sc_keymap) ||
 758                              test_bit(i + 32, sc->sc_keymap) ||
 759                              test_bit(i + 64 + 32, sc->sc_keymap)))
 760                                 return i + 64;
 761                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 762                             (test_bit(i, sc->sc_keymap) ||
 763                              test_bit(i + 32, sc->sc_keymap) ||
 764                              test_bit(i + 64, sc->sc_keymap)))
 765                                 return i + 64 + 32;
 766                 }
 767         } else {
 768                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 769                         if (!test_bit(i, sc->sc_keymap) &&
 770                             test_bit(i + 64, sc->sc_keymap))
 771                                 return i;
 772                         if (test_bit(i, sc->sc_keymap) &&
 773                             !test_bit(i + 64, sc->sc_keymap))
 774                                 return i + 64;
 775                 }
 776         }
 777
 778         /* No partially used TKIP slots, pick any available slot */
 779         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 780                 /* Do not allow slots that could be needed for TKIP group keys
 781                  * to be used. This limitation could be removed if we know that
 782                  * TKIP will not be used. */
 783                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 784                         continue;
 785                 if (sc->sc_splitmic) {
 786                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 787                                 continue;
 788                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 789                                 continue;
 790                 }
 791
 792                 if (!test_bit(i, sc->sc_keymap))
 793                         return i; /* Found a free slot for a key */
 794         }
 795
 796         /* No free slot found */
 797         return -1;
 798 }
 799
 800 static int ath_key_config(struct ath_softc *sc,
 801                           struct ieee80211_sta *sta,
 802                           struct ieee80211_key_conf *key)
 803 {
 804         struct ath9k_keyval hk;
 805         const u8 *mac = NULL;
 806         int ret = 0;
 807         int idx;
 808
 809         memset(&hk, 0, sizeof(hk));
 810
 811         switch (key->alg) {
 812         case ALG_WEP:
 813                 hk.kv_type = ATH9K_CIPHER_WEP;
 814                 break;
 815         case ALG_TKIP:
 816                 hk.kv_type = ATH9K_CIPHER_TKIP;
 817                 break;
 818         case ALG_CCMP:
 819                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 820                 break;
 821         default:
 822                 return -EOPNOTSUPP;
 823         }
 824
 825         hk.kv_len = key->keylen;
 826         memcpy(hk.kv_val, key->key, key->keylen);
 827
 828         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 829                 /* For now, use the default keys for broadcast keys. This may
 830                  * need to change with virtual interfaces. */
 831                 idx = key->keyidx;
 832         } else if (key->keyidx) {
 833                 struct ieee80211_vif *vif;
 834
 835                 if (WARN_ON(!sta))
 836                         return -EOPNOTSUPP;
 837                 mac = sta->addr;
 838
 839                 vif = sc->sc_vaps[0];
 840                 if (vif->type != NL80211_IFTYPE_AP) {
 841                         /* Only keyidx 0 should be used with unicast key, but
 842                          * allow this for client mode for now. */
 843                         idx = key->keyidx;
 844                 } else
 845                         return -EIO;
 846         } else {
 847                 if (WARN_ON(!sta))
 848                         return -EOPNOTSUPP;
 849                 mac = sta->addr;
 850
 851                 if (key->alg == ALG_TKIP)
 852                         idx = ath_reserve_key_cache_slot_tkip(sc);
 853                 else
 854                         idx = ath_reserve_key_cache_slot(sc);
 855                 if (idx < 0)
 856                         return -ENOSPC; /* no free key cache entries */
 857         }
 858
 859         if (key->alg == ALG_TKIP)
 860                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 861         else
 862                 ret = ath_keyset(sc, idx, &hk, mac);
 863
 864         if (!ret)
 865                 return -EIO;
 866
 867         set_bit(idx, sc->sc_keymap);
 868         if (key->alg == ALG_TKIP) {
 869                 set_bit(idx + 64, sc->sc_keymap);
 870                 if (sc->sc_splitmic) {
 871                         set_bit(idx + 32, sc->sc_keymap);
 872                         set_bit(idx + 64 + 32, sc->sc_keymap);
 873                 }
 874         }
 875
 876         return idx;
 877 }
 878
 879 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 880 {
 881         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 882         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 883                 return;
 884
 885         clear_bit(key->hw_key_idx, sc->sc_keymap);
 886         if (key->alg != ALG_TKIP)
 887                 return;
 888
 889         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 890         if (sc->sc_splitmic) {
 891                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 892                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 893         }
 894 }
 895
 896 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 897 {
 898 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 899 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 900
 901         ht_info->ht_supported = true;
 902         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 903                        IEEE80211_HT_CAP_SM_PS |
 904                        IEEE80211_HT_CAP_SGI_40 |
 905                        IEEE80211_HT_CAP_DSSSCCK40;
 906
 907         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 908         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 909         /* set up supported mcs set */
 910         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 911         ht_info->mcs.rx_mask[0] = 0xff;
 912         ht_info->mcs.rx_mask[1] = 0xff;
 913         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 914 }
 915
 916 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 917                                  struct ieee80211_vif *vif,
 918                                  struct ieee80211_bss_conf *bss_conf)
 919 {
 920         struct ath_vap *avp = (void *)vif->drv_priv;
 921
 922         if (bss_conf->assoc) {
 923                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 924                         bss_conf->aid, sc->sc_curbssid);
 925
 926                 /* New association, store aid */
 927                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 928                         sc->sc_curaid = bss_conf->aid;
 929                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 930                                                sc->sc_curaid);
 931                 }
 932
 933                 /* Configure the beacon */
 934                 ath_beacon_config(sc, 0);
 935                 sc->sc_flags |= SC_OP_BEACONS;
 936
 937                 /* Reset rssi stats */
 938                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 939                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 940                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 941                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 942
 943                 /* Start ANI */
 944                 mod_timer(&sc->sc_ani.timer,
 945                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 946
 947         } else {
 948                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 949                 sc->sc_curaid = 0;
 950         }
 951 }
 952
 953 /********************************/
 954 /*       LED functions          */
 955 /********************************/
 956
 957 static void ath_led_brightness(struct led_classdev *led_cdev,
 958                                enum led_brightness brightness)
 959 {
 960         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 961         struct ath_softc *sc = led->sc;
 962
 963         switch (brightness) {
 964         case LED_OFF:
 965                 if (led->led_type == ATH_LED_ASSOC ||
 966                     led->led_type == ATH_LED_RADIO)
 967                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 968                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 969                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 970                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 971                 break;
 972         case LED_FULL:
 973                 if (led->led_type == ATH_LED_ASSOC)
 974                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 975                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 976                 break;
 977         default:
 978                 break;
 979         }
 980 }
 981
 982 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 983                             char *trigger)
 984 {
 985         int ret;
 986
 987         led->sc = sc;
 988         led->led_cdev.name = led->name;
 989         led->led_cdev.default_trigger = trigger;
 990         led->led_cdev.brightness_set = ath_led_brightness;
 991
 992         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 993         if (ret)
 994                 DPRINTF(sc, ATH_DBG_FATAL,
 995                         "Failed to register led:%s", led->name);
 996         else
 997                 led->registered = 1;
 998         return ret;
 999 }
1000
1001 static void ath_unregister_led(struct ath_led *led)
1002 {
1003         if (led->registered) {
1004                 led_classdev_unregister(&led->led_cdev);
1005                 led->registered = 0;
1006         }
1007 }
1008
1009 static void ath_deinit_leds(struct ath_softc *sc)
1010 {
1011         ath_unregister_led(&sc->assoc_led);
1012         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1013         ath_unregister_led(&sc->tx_led);
1014         ath_unregister_led(&sc->rx_led);
1015         ath_unregister_led(&sc->radio_led);
1016         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1017 }
1018
1019 static void ath_init_leds(struct ath_softc *sc)
1020 {
1021         char *trigger;
1022         int ret;
1023
1024         /* Configure gpio 1 for output */
1025         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1026                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1027         /* LED off, active low */
1028         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1029
1030         trigger = ieee80211_get_radio_led_name(sc->hw);
1031         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1032                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1033         ret = ath_register_led(sc, &sc->radio_led, trigger);
1034         sc->radio_led.led_type = ATH_LED_RADIO;
1035         if (ret)
1036                 goto fail;
1037
1038         trigger = ieee80211_get_assoc_led_name(sc->hw);
1039         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1040                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1041         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1042         sc->assoc_led.led_type = ATH_LED_ASSOC;
1043         if (ret)
1044                 goto fail;
1045
1046         trigger = ieee80211_get_tx_led_name(sc->hw);
1047         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1048                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1049         ret = ath_register_led(sc, &sc->tx_led, trigger);
1050         sc->tx_led.led_type = ATH_LED_TX;
1051         if (ret)
1052                 goto fail;
1053
1054         trigger = ieee80211_get_rx_led_name(sc->hw);
1055         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1056                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1057         ret = ath_register_led(sc, &sc->rx_led, trigger);
1058         sc->rx_led.led_type = ATH_LED_RX;
1059         if (ret)
1060                 goto fail;
1061
1062         return;
1063
1064 fail:
1065         ath_deinit_leds(sc);
1066 }
1067
1068 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1069
1070 /*******************/
1071 /*      Rfkill     */
1072 /*******************/
1073
1074 static void ath_radio_enable(struct ath_softc *sc)
1075 {
1076         struct ath_hal *ah = sc->sc_ah;
1077         struct ieee80211_channel *channel = sc->hw->conf.channel;
1078         int r;
1079
1080         spin_lock_bh(&sc->sc_resetlock);
1081
1082         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1083
1084         if (r) {
1085                 DPRINTF(sc, ATH_DBG_FATAL,
1086                         "Unable to reset channel %u (%uMhz) ",
1087                         "reset status %u\n",
1088                         channel->center_freq, r);
1089         }
1090         spin_unlock_bh(&sc->sc_resetlock);
1091
1092         ath_update_txpow(sc);
1093         if (ath_startrecv(sc) != 0) {
1094                 DPRINTF(sc, ATH_DBG_FATAL,
1095                         "Unable to restart recv logic\n");
1096                 return;
1097         }
1098
1099         if (sc->sc_flags & SC_OP_BEACONS)
1100                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1101
1102         /* Re-Enable  interrupts */
1103         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1104
1105         /* Enable LED */
1106         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1107                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1108         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1109
1110         ieee80211_wake_queues(sc->hw);
1111 }
1112
1113 static void ath_radio_disable(struct ath_softc *sc)
1114 {
1115         struct ath_hal *ah = sc->sc_ah;
1116         struct ieee80211_channel *channel = sc->hw->conf.channel;
1117         int r;
1118
1119         ieee80211_stop_queues(sc->hw);
1120
1121         /* Disable LED */
1122         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1123         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1124
1125         /* Disable interrupts */
1126         ath9k_hw_set_interrupts(ah, 0);
1127
1128         ath_draintxq(sc, false);        /* clear pending tx frames */
1129         ath_stoprecv(sc);               /* turn off frame recv */
1130         ath_flushrecv(sc);              /* flush recv queue */
1131
1132         spin_lock_bh(&sc->sc_resetlock);
1133         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1134         if (r) {
1135                 DPRINTF(sc, ATH_DBG_FATAL,
1136                         "Unable to reset channel %u (%uMhz) "
1137                         "reset status %u\n",
1138                         channel->center_freq, r);
1139         }
1140         spin_unlock_bh(&sc->sc_resetlock);
1141
1142         ath9k_hw_phy_disable(ah);
1143         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1144 }
1145
1146 static bool ath_is_rfkill_set(struct ath_softc *sc)
1147 {
1148         struct ath_hal *ah = sc->sc_ah;
1149
1150         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1151                                   ah->ah_rfkill_polarity;
1152 }
1153
1154 /* h/w rfkill poll function */
1155 static void ath_rfkill_poll(struct work_struct *work)
1156 {
1157         struct ath_softc *sc = container_of(work, struct ath_softc,
1158                                             rf_kill.rfkill_poll.work);
1159         bool radio_on;
1160
1161         if (sc->sc_flags & SC_OP_INVALID)
1162                 return;
1163
1164         radio_on = !ath_is_rfkill_set(sc);
1165
1166         /*
1167          * enable/disable radio only when there is a
1168          * state change in RF switch
1169          */
1170         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1171                 enum rfkill_state state;
1172
1173                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1174                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1175                                 : RFKILL_STATE_HARD_BLOCKED;
1176                 } else if (radio_on) {
1177                         ath_radio_enable(sc);
1178                         state = RFKILL_STATE_UNBLOCKED;
1179                 } else {
1180                         ath_radio_disable(sc);
1181                         state = RFKILL_STATE_HARD_BLOCKED;
1182                 }
1183
1184                 if (state == RFKILL_STATE_HARD_BLOCKED)
1185                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1186                 else
1187                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1188
1189                 rfkill_force_state(sc->rf_kill.rfkill, state);
1190         }
1191
1192         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1193                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1194 }
1195
1196 /* s/w rfkill handler */
1197 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1198 {
1199         struct ath_softc *sc = data;
1200
1201         switch (state) {
1202         case RFKILL_STATE_SOFT_BLOCKED:
1203                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1204                     SC_OP_RFKILL_SW_BLOCKED)))
1205                         ath_radio_disable(sc);
1206                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1207                 return 0;
1208         case RFKILL_STATE_UNBLOCKED:
1209                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1210                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1211                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1212                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1213                                         "radio as it is disabled by h/w\n");
1214                                 return -EPERM;
1215                         }
1216                         ath_radio_enable(sc);
1217                 }
1218                 return 0;
1219         default:
1220                 return -EINVAL;
1221         }
1222 }
1223
1224 /* Init s/w rfkill */
1225 static int ath_init_sw_rfkill(struct ath_softc *sc)
1226 {
1227         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1228                                              RFKILL_TYPE_WLAN);
1229         if (!sc->rf_kill.rfkill) {
1230                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1231                 return -ENOMEM;
1232         }
1233
1234         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1235                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1236         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1237         sc->rf_kill.rfkill->data = sc;
1238         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1239         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1240         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1241
1242         return 0;
1243 }
1244
1245 /* Deinitialize rfkill */
1246 static void ath_deinit_rfkill(struct ath_softc *sc)
1247 {
1248         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1249                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1250
1251         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1252                 rfkill_unregister(sc->rf_kill.rfkill);
1253                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1254                 sc->rf_kill.rfkill = NULL;
1255         }
1256 }
1257
1258 static int ath_start_rfkill_poll(struct ath_softc *sc)
1259 {
1260         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1261                 queue_delayed_work(sc->hw->workqueue,
1262                                    &sc->rf_kill.rfkill_poll, 0);
1263
1264         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1265                 if (rfkill_register(sc->rf_kill.rfkill)) {
1266                         DPRINTF(sc, ATH_DBG_FATAL,
1267                                 "Unable to register rfkill\n");
1268                         rfkill_free(sc->rf_kill.rfkill);
1269
1270                         /* Deinitialize the device */
1271                         ath_cleanup(sc);
1272                         return -EIO;
1273                 } else {
1274                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1275                 }
1276         }
1277
1278         return 0;
1279 }
1280 #endif /* CONFIG_RFKILL */
1281
1282 static void ath_cleanup(struct ath_softc *sc)
1283 {
1284         ath_detach(sc);
1285         free_irq(sc->irq, sc);
1286         ath_bus_cleanup(sc);
1287         ieee80211_free_hw(sc->hw);
1288 }
1289
1290 static void ath_detach(struct ath_softc *sc)
1291 {
1292         struct ieee80211_hw *hw = sc->hw;
1293         int i = 0;
1294
1295         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1296
1297 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1298         ath_deinit_rfkill(sc);
1299 #endif
1300         ath_deinit_leds(sc);
1301
1302         ieee80211_unregister_hw(hw);
1303         ath_rx_cleanup(sc);
1304         ath_tx_cleanup(sc);
1305
1306         tasklet_kill(&sc->intr_tq);
1307         tasklet_kill(&sc->bcon_tasklet);
1308
1309         if (!(sc->sc_flags & SC_OP_INVALID))
1310                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1311
1312         /* cleanup tx queues */
1313         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1314                 if (ATH_TXQ_SETUP(sc, i))
1315                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1316
1317         ath9k_hw_detach(sc->sc_ah);
1318         ath9k_exit_debug(sc);
1319 }
1320
1321 static int ath_init(u16 devid, struct ath_softc *sc)
1322 {
1323         struct ath_hal *ah = NULL;
1324         int status;
1325         int error = 0, i;
1326         int csz = 0;
1327
1328         /* XXX: hardware will not be ready until ath_open() being called */
1329         sc->sc_flags |= SC_OP_INVALID;
1330
1331         if (ath9k_init_debug(sc) < 0)
1332                 printk(KERN_ERR "Unable to create debugfs files\n");
1333
1334         spin_lock_init(&sc->sc_resetlock);
1335         mutex_init(&sc->mutex);
1336         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1337         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1338                      (unsigned long)sc);
1339
1340         /*
1341          * Cache line size is used to size and align various
1342          * structures used to communicate with the hardware.
1343          */
1344         ath_read_cachesize(sc, &csz);
1345         /* XXX assert csz is non-zero */
1346         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1347
1348         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1349         if (ah == NULL) {
1350                 DPRINTF(sc, ATH_DBG_FATAL,
1351                         "Unable to attach hardware; HAL status %d\n", status);
1352                 error = -ENXIO;
1353                 goto bad;
1354         }
1355         sc->sc_ah = ah;
1356
1357         /* Get the hardware key cache size. */
1358         sc->sc_keymax = ah->ah_caps.keycache_size;
1359         if (sc->sc_keymax > ATH_KEYMAX) {
1360                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1361                         "Warning, using only %u entries in %u key cache\n",
1362                         ATH_KEYMAX, sc->sc_keymax);
1363                 sc->sc_keymax = ATH_KEYMAX;
1364         }
1365
1366         /*
1367          * Reset the key cache since some parts do not
1368          * reset the contents on initial power up.
1369          */
1370         for (i = 0; i < sc->sc_keymax; i++)
1371                 ath9k_hw_keyreset(ah, (u16) i);
1372
1373         /* Collect the channel list using the default country code */
1374
1375         error = ath_setup_channels(sc);
1376         if (error)
1377                 goto bad;
1378
1379         /* default to MONITOR mode */
1380         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1381
1382
1383         /* Setup rate tables */
1384
1385         ath_rate_attach(sc);
1386         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1387         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1388
1389         /*
1390          * Allocate hardware transmit queues: one queue for
1391          * beacon frames and one data queue for each QoS
1392          * priority.  Note that the hal handles reseting
1393          * these queues at the needed time.
1394          */
1395         sc->beacon.beaconq = ath_beaconq_setup(ah);
1396         if (sc->beacon.beaconq == -1) {
1397                 DPRINTF(sc, ATH_DBG_FATAL,
1398                         "Unable to setup a beacon xmit queue\n");
1399                 error = -EIO;
1400                 goto bad2;
1401         }
1402         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1403         if (sc->beacon.cabq == NULL) {
1404                 DPRINTF(sc, ATH_DBG_FATAL,
1405                         "Unable to setup CAB xmit queue\n");
1406                 error = -EIO;
1407                 goto bad2;
1408         }
1409
1410         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1411         ath_cabq_update(sc);
1412
1413         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1414                 sc->tx.hwq_map[i] = -1;
1415
1416         /* Setup data queues */
1417         /* NB: ensure BK queue is the lowest priority h/w queue */
1418         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1419                 DPRINTF(sc, ATH_DBG_FATAL,
1420                         "Unable to setup xmit queue for BK traffic\n");
1421                 error = -EIO;
1422                 goto bad2;
1423         }
1424
1425         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1426                 DPRINTF(sc, ATH_DBG_FATAL,
1427                         "Unable to setup xmit queue for BE traffic\n");
1428                 error = -EIO;
1429                 goto bad2;
1430         }
1431         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1432                 DPRINTF(sc, ATH_DBG_FATAL,
1433                         "Unable to setup xmit queue for VI traffic\n");
1434                 error = -EIO;
1435                 goto bad2;
1436         }
1437         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1438                 DPRINTF(sc, ATH_DBG_FATAL,
1439                         "Unable to setup xmit queue for VO traffic\n");
1440                 error = -EIO;
1441                 goto bad2;
1442         }
1443
1444         /* Initializes the noise floor to a reasonable default value.
1445          * Later on this will be updated during ANI processing. */
1446
1447         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1448         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1449
1450         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1451                                    ATH9K_CIPHER_TKIP, NULL)) {
1452                 /*
1453                  * Whether we should enable h/w TKIP MIC.
1454                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1455                  * report WMM capable, so it's always safe to turn on
1456                  * TKIP MIC in this case.
1457                  */
1458                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1459                                        0, 1, NULL);
1460         }
1461
1462         /*
1463          * Check whether the separate key cache entries
1464          * are required to handle both tx+rx MIC keys.
1465          * With split mic keys the number of stations is limited
1466          * to 27 otherwise 59.
1467          */
1468         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1469                                    ATH9K_CIPHER_TKIP, NULL)
1470             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1471                                       ATH9K_CIPHER_MIC, NULL)
1472             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1473                                       0, NULL))
1474                 sc->sc_splitmic = 1;
1475
1476         /* turn on mcast key search if possible */
1477         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1478                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1479                                              1, NULL);
1480
1481         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1482         sc->sc_config.txpowlimit_override = 0;
1483
1484         /* 11n Capabilities */
1485         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1486                 sc->sc_flags |= SC_OP_TXAGGR;
1487                 sc->sc_flags |= SC_OP_RXAGGR;
1488         }
1489
1490         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1491         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1492
1493         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1494         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1495
1496         ath9k_hw_getmac(ah, sc->sc_myaddr);
1497         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1498                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1499                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1500                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1501         }
1502
1503         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1504
1505         /* initialize beacon slots */
1506         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1507                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1508
1509         /* save MISC configurations */
1510         sc->sc_config.swBeaconProcess = 1;
1511
1512         /* setup channels and rates */
1513
1514         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1515                 sc->channels[IEEE80211_BAND_2GHZ];
1516         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1517                 sc->rates[IEEE80211_BAND_2GHZ];
1518         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1519
1520         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1521                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1522                         sc->channels[IEEE80211_BAND_5GHZ];
1523                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1524                         sc->rates[IEEE80211_BAND_5GHZ];
1525                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1526         }
1527
1528         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1529                 ath9k_hw_btcoex_enable(sc->sc_ah);
1530
1531         return 0;
1532 bad2:
1533         /* cleanup tx queues */
1534         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1535                 if (ATH_TXQ_SETUP(sc, i))
1536                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1537 bad:
1538         if (ah)
1539                 ath9k_hw_detach(ah);
1540
1541         return error;
1542 }
1543
1544 static int ath_attach(u16 devid, struct ath_softc *sc)
1545 {
1546         struct ieee80211_hw *hw = sc->hw;
1547         int error = 0;
1548
1549         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1550
1551         error = ath_init(devid, sc);
1552         if (error != 0)
1553                 return error;
1554
1555         /* get mac address from hardware and set in mac80211 */
1556
1557         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1558
1559         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1560                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1561                 IEEE80211_HW_SIGNAL_DBM |
1562                 IEEE80211_HW_AMPDU_AGGREGATION;
1563
1564         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1565                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1566
1567         hw->wiphy->interface_modes =
1568                 BIT(NL80211_IFTYPE_AP) |
1569                 BIT(NL80211_IFTYPE_STATION) |
1570                 BIT(NL80211_IFTYPE_ADHOC);
1571
1572         hw->queues = 4;
1573         hw->max_rates = 4;
1574         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1575         hw->sta_data_size = sizeof(struct ath_node);
1576         hw->vif_data_size = sizeof(struct ath_vap);
1577
1578         hw->rate_control_algorithm = "ath9k_rate_control";
1579
1580         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1581                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1582                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1583                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1584         }
1585
1586         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1587         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1588                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1589                         &sc->sbands[IEEE80211_BAND_5GHZ];
1590
1591         /* initialize tx/rx engine */
1592         error = ath_tx_init(sc, ATH_TXBUF);
1593         if (error != 0)
1594                 goto detach;
1595
1596         error = ath_rx_init(sc, ATH_RXBUF);
1597         if (error != 0)
1598                 goto detach;
1599
1600 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1601         /* Initialze h/w Rfkill */
1602         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1603                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1604
1605         /* Initialize s/w rfkill */
1606         if (ath_init_sw_rfkill(sc))
1607                 goto detach;
1608 #endif
1609
1610         error = ieee80211_register_hw(hw);
1611
1612         /* Initialize LED control */
1613         ath_init_leds(sc);
1614
1615         return 0;
1616 detach:
1617         ath_detach(sc);
1618         return error;
1619 }
1620
1621 int ath_reset(struct ath_softc *sc, bool retry_tx)
1622 {
1623         struct ath_hal *ah = sc->sc_ah;
1624         struct ieee80211_hw *hw = sc->hw;
1625         int r;
1626
1627         ath9k_hw_set_interrupts(ah, 0);
1628         ath_draintxq(sc, retry_tx);
1629         ath_stoprecv(sc);
1630         ath_flushrecv(sc);
1631
1632         spin_lock_bh(&sc->sc_resetlock);
1633         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1634         if (r)
1635                 DPRINTF(sc, ATH_DBG_FATAL,
1636                         "Unable to reset hardware; reset status %u\n", r);
1637         spin_unlock_bh(&sc->sc_resetlock);
1638
1639         if (ath_startrecv(sc) != 0)
1640                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1641
1642         /*
1643          * We may be doing a reset in response to a request
1644          * that changes the channel so update any state that
1645          * might change as a result.
1646          */
1647         ath_cache_conf_rate(sc, &hw->conf);
1648
1649         ath_update_txpow(sc);
1650
1651         if (sc->sc_flags & SC_OP_BEACONS)
1652                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1653
1654         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1655
1656         if (retry_tx) {
1657                 int i;
1658                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1659                         if (ATH_TXQ_SETUP(sc, i)) {
1660                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1661                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1662                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1663                         }
1664                 }
1665         }
1666
1667         return r;
1668 }
1669
1670 /*
1671  *  This function will allocate both the DMA descriptor structure, and the
1672  *  buffers it contains.  These are used to contain the descriptors used
1673  *  by the system.
1674 */
1675 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1676                       struct list_head *head, const char *name,
1677                       int nbuf, int ndesc)
1678 {
1679 #define DS2PHYS(_dd, _ds)                                               \
1680         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1681 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1682 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1683
1684         struct ath_desc *ds;
1685         struct ath_buf *bf;
1686         int i, bsize, error;
1687
1688         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1689                 name, nbuf, ndesc);
1690
1691         /* ath_desc must be a multiple of DWORDs */
1692         if ((sizeof(struct ath_desc) % 4) != 0) {
1693                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1694                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1695                 error = -ENOMEM;
1696                 goto fail;
1697         }
1698
1699         dd->dd_name = name;
1700         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1701
1702         /*
1703          * Need additional DMA memory because we can't use
1704          * descriptors that cross the 4K page boundary. Assume
1705          * one skipped descriptor per 4K page.
1706          */
1707         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1708                 u32 ndesc_skipped =
1709                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1710                 u32 dma_len;
1711
1712                 while (ndesc_skipped) {
1713                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1714                         dd->dd_desc_len += dma_len;
1715
1716                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1717                 };
1718         }
1719
1720         /* allocate descriptors */
1721         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1722                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1723         if (dd->dd_desc == NULL) {
1724                 error = -ENOMEM;
1725                 goto fail;
1726         }
1727         ds = dd->dd_desc;
1728         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1729                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1730                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1731
1732         /* allocate buffers */
1733         bsize = sizeof(struct ath_buf) * nbuf;
1734         bf = kmalloc(bsize, GFP_KERNEL);
1735         if (bf == NULL) {
1736                 error = -ENOMEM;
1737                 goto fail2;
1738         }
1739         memset(bf, 0, bsize);
1740         dd->dd_bufptr = bf;
1741
1742         INIT_LIST_HEAD(head);
1743         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1744                 bf->bf_desc = ds;
1745                 bf->bf_daddr = DS2PHYS(dd, ds);
1746
1747                 if (!(sc->sc_ah->ah_caps.hw_caps &
1748                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1749                         /*
1750                          * Skip descriptor addresses which can cause 4KB
1751                          * boundary crossing (addr + length) with a 32 dword
1752                          * descriptor fetch.
1753                          */
1754                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1755                                 ASSERT((caddr_t) bf->bf_desc <
1756                                        ((caddr_t) dd->dd_desc +
1757                                         dd->dd_desc_len));
1758
1759                                 ds += ndesc;
1760                                 bf->bf_desc = ds;
1761                                 bf->bf_daddr = DS2PHYS(dd, ds);
1762                         }
1763                 }
1764                 list_add_tail(&bf->list, head);
1765         }
1766         return 0;
1767 fail2:
1768         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1769                           dd->dd_desc_paddr);
1770 fail:
1771         memset(dd, 0, sizeof(*dd));
1772         return error;
1773 #undef ATH_DESC_4KB_BOUND_CHECK
1774 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1775 #undef DS2PHYS
1776 }
1777
1778 void ath_descdma_cleanup(struct ath_softc *sc,
1779                          struct ath_descdma *dd,
1780                          struct list_head *head)
1781 {
1782         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1783                           dd->dd_desc_paddr);
1784
1785         INIT_LIST_HEAD(head);
1786         kfree(dd->dd_bufptr);
1787         memset(dd, 0, sizeof(*dd));
1788 }
1789
1790 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1791 {
1792         int qnum;
1793
1794         switch (queue) {
1795         case 0:
1796                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1797                 break;
1798         case 1:
1799                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1800                 break;
1801         case 2:
1802                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1803                 break;
1804         case 3:
1805                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1806                 break;
1807         default:
1808                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1809                 break;
1810         }
1811
1812         return qnum;
1813 }
1814
1815 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1816 {
1817         int qnum;
1818
1819         switch (queue) {
1820         case ATH9K_WME_AC_VO:
1821                 qnum = 0;
1822                 break;
1823         case ATH9K_WME_AC_VI:
1824                 qnum = 1;
1825                 break;
1826         case ATH9K_WME_AC_BE:
1827                 qnum = 2;
1828                 break;
1829         case ATH9K_WME_AC_BK:
1830                 qnum = 3;
1831                 break;
1832         default:
1833                 qnum = -1;
1834                 break;
1835         }
1836
1837         return qnum;
1838 }
1839
1840 /**********************/
1841 /* mac80211 callbacks */
1842 /**********************/
1843
1844 static int ath9k_start(struct ieee80211_hw *hw)
1845 {
1846         struct ath_softc *sc = hw->priv;
1847         struct ieee80211_channel *curchan = hw->conf.channel;
1848         struct ath9k_channel *init_channel;
1849         int r, pos;
1850
1851         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1852                 "initial channel: %d MHz\n", curchan->center_freq);
1853
1854         /* setup initial channel */
1855
1856         pos = ath_get_channel(sc, curchan);
1857         if (pos == -1) {
1858                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1859                 return -EINVAL;
1860         }
1861
1862         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1863         sc->sc_ah->ah_channels[pos].chanmode =
1864                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1865         init_channel = &sc->sc_ah->ah_channels[pos];
1866
1867         /* Reset SERDES registers */
1868         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1869
1870         /*
1871          * The basic interface to setting the hardware in a good
1872          * state is ``reset''.  On return the hardware is known to
1873          * be powered up and with interrupts disabled.  This must
1874          * be followed by initialization of the appropriate bits
1875          * and then setup of the interrupt mask.
1876          */
1877         spin_lock_bh(&sc->sc_resetlock);
1878         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1879         if (r) {
1880                 DPRINTF(sc, ATH_DBG_FATAL,
1881                         "Unable to reset hardware; reset status %u "
1882                         "(freq %u MHz)\n", r,
1883                         curchan->center_freq);
1884                 spin_unlock_bh(&sc->sc_resetlock);
1885                 return r;
1886         }
1887         spin_unlock_bh(&sc->sc_resetlock);
1888
1889         /*
1890          * This is needed only to setup initial state
1891          * but it's best done after a reset.
1892          */
1893         ath_update_txpow(sc);
1894
1895         /*
1896          * Setup the hardware after reset:
1897          * The receive engine is set going.
1898          * Frame transmit is handled entirely
1899          * in the frame output path; there's nothing to do
1900          * here except setup the interrupt mask.
1901          */
1902         if (ath_startrecv(sc) != 0) {
1903                 DPRINTF(sc, ATH_DBG_FATAL,
1904                         "Unable to start recv logic\n");
1905                 return -EIO;
1906         }
1907
1908         /* Setup our intr mask. */
1909         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1910                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1911                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1912
1913         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1914                 sc->sc_imask |= ATH9K_INT_GTT;
1915
1916         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1917                 sc->sc_imask |= ATH9K_INT_CST;
1918
1919         /*
1920          * Enable MIB interrupts when there are hardware phy counters.
1921          * Note we only do this (at the moment) for station mode.
1922          */
1923         if (ath9k_hw_phycounters(sc->sc_ah) &&
1924             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1925              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1926                 sc->sc_imask |= ATH9K_INT_MIB;
1927         /*
1928          * Some hardware processes the TIM IE and fires an
1929          * interrupt when the TIM bit is set.  For hardware
1930          * that does, if not overridden by configuration,
1931          * enable the TIM interrupt when operating as station.
1932          */
1933         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1934             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1935             !sc->sc_config.swBeaconProcess)
1936                 sc->sc_imask |= ATH9K_INT_TIM;
1937
1938         ath_cache_conf_rate(sc, &hw->conf);
1939
1940         sc->sc_flags &= ~SC_OP_INVALID;
1941
1942         /* Disable BMISS interrupt when we're not associated */
1943         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1944         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1945
1946         ieee80211_wake_queues(sc->hw);
1947
1948 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1949         r = ath_start_rfkill_poll(sc);
1950 #endif
1951         return r;
1952 }
1953
1954 static int ath9k_tx(struct ieee80211_hw *hw,
1955                     struct sk_buff *skb)
1956 {
1957         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1958         struct ath_softc *sc = hw->priv;
1959         struct ath_tx_control txctl;
1960         int hdrlen, padsize;
1961
1962         memset(&txctl, 0, sizeof(struct ath_tx_control));
1963
1964         /*
1965          * As a temporary workaround, assign seq# here; this will likely need
1966          * to be cleaned up to work better with Beacon transmission and virtual
1967          * BSSes.
1968          */
1969         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1970                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1971                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1972                         sc->tx.seq_no += 0x10;
1973                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1974                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1975         }
1976
1977         /* Add the padding after the header if this is not already done */
1978         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1979         if (hdrlen & 3) {
1980                 padsize = hdrlen % 4;
1981                 if (skb_headroom(skb) < padsize)
1982                         return -1;
1983                 skb_push(skb, padsize);
1984                 memmove(skb->data, skb->data + padsize, hdrlen);
1985         }
1986
1987         /* Check if a tx queue is available */
1988
1989         txctl.txq = ath_test_get_txq(sc, skb);
1990         if (!txctl.txq)
1991                 goto exit;
1992
1993         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1994
1995         if (ath_tx_start(sc, skb, &txctl) != 0) {
1996                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
1997                 goto exit;
1998         }
1999
2000         return 0;
2001 exit:
2002         dev_kfree_skb_any(skb);
2003         return 0;
2004 }
2005
2006 static void ath9k_stop(struct ieee80211_hw *hw)
2007 {
2008         struct ath_softc *sc = hw->priv;
2009
2010         if (sc->sc_flags & SC_OP_INVALID) {
2011                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2012                 return;
2013         }
2014
2015         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2016
2017         ieee80211_stop_queues(sc->hw);
2018
2019         /* make sure h/w will not generate any interrupt
2020          * before setting the invalid flag. */
2021         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2022
2023         if (!(sc->sc_flags & SC_OP_INVALID)) {
2024                 ath_draintxq(sc, false);
2025                 ath_stoprecv(sc);
2026                 ath9k_hw_phy_disable(sc->sc_ah);
2027         } else
2028                 sc->rx.rxlink = NULL;
2029
2030 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2031         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2032                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2033 #endif
2034         /* disable HAL and put h/w to sleep */
2035         ath9k_hw_disable(sc->sc_ah);
2036         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2037
2038         sc->sc_flags |= SC_OP_INVALID;
2039
2040         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2041 }
2042
2043 static int ath9k_add_interface(struct ieee80211_hw *hw,
2044                                struct ieee80211_if_init_conf *conf)
2045 {
2046         struct ath_softc *sc = hw->priv;
2047         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2048         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2049
2050         /* Support only vap for now */
2051
2052         if (sc->sc_nvaps)
2053                 return -ENOBUFS;
2054
2055         switch (conf->type) {
2056         case NL80211_IFTYPE_STATION:
2057                 ic_opmode = NL80211_IFTYPE_STATION;
2058                 break;
2059         case NL80211_IFTYPE_ADHOC:
2060                 ic_opmode = NL80211_IFTYPE_ADHOC;
2061                 break;
2062         case NL80211_IFTYPE_AP:
2063                 ic_opmode = NL80211_IFTYPE_AP;
2064                 break;
2065         default:
2066                 DPRINTF(sc, ATH_DBG_FATAL,
2067                         "Interface type %d not yet supported\n", conf->type);
2068                 return -EOPNOTSUPP;
2069         }
2070
2071         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2072
2073         /* Set the VAP opmode */
2074         avp->av_opmode = ic_opmode;
2075         avp->av_bslot = -1;
2076
2077         if (ic_opmode == NL80211_IFTYPE_AP)
2078                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2079
2080         sc->sc_vaps[0] = conf->vif;
2081         sc->sc_nvaps++;
2082
2083         /* Set the device opmode */
2084         sc->sc_ah->ah_opmode = ic_opmode;
2085
2086         if (conf->type == NL80211_IFTYPE_AP) {
2087                 /* TODO: is this a suitable place to start ANI for AP mode? */
2088                 /* Start ANI */
2089                 mod_timer(&sc->sc_ani.timer,
2090                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2091         }
2092
2093         return 0;
2094 }
2095
2096 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2097                                    struct ieee80211_if_init_conf *conf)
2098 {
2099         struct ath_softc *sc = hw->priv;
2100         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2101
2102         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2103
2104         /* Stop ANI */
2105         del_timer_sync(&sc->sc_ani.timer);
2106
2107         /* Reclaim beacon resources */
2108         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2109             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2110                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2111                 ath_beacon_return(sc, avp);
2112         }
2113
2114         sc->sc_flags &= ~SC_OP_BEACONS;
2115
2116         sc->sc_vaps[0] = NULL;
2117         sc->sc_nvaps--;
2118 }
2119
2120 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2121 {
2122         struct ath_softc *sc = hw->priv;
2123         struct ieee80211_conf *conf = &hw->conf;
2124
2125         mutex_lock(&sc->mutex);
2126         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2127                 struct ieee80211_channel *curchan = hw->conf.channel;
2128                 int pos;
2129
2130                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2131                         curchan->center_freq);
2132
2133                 pos = ath_get_channel(sc, curchan);
2134                 if (pos == -1) {
2135                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2136                                 curchan->center_freq);
2137                         mutex_unlock(&sc->mutex);
2138                         return -EINVAL;
2139                 }
2140
2141                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2142                 sc->sc_ah->ah_channels[pos].chanmode =
2143                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2144                         CHANNEL_G : CHANNEL_A;
2145
2146                 if (conf_is_ht(conf)) {
2147                         if (conf_is_ht40(conf))
2148                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2149
2150                         sc->sc_ah->ah_channels[pos].chanmode =
2151                                 ath_get_extchanmode(sc, curchan,
2152                                                     conf->channel_type);
2153                 }
2154
2155                 ath_update_chainmask(sc, conf_is_ht(conf));
2156
2157                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2158                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2159                         mutex_unlock(&sc->mutex);
2160                         return -EINVAL;
2161                 }
2162         }
2163
2164         if (changed & IEEE80211_CONF_CHANGE_POWER)
2165                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2166
2167         mutex_unlock(&sc->mutex);
2168         return 0;
2169 }
2170
2171 static int ath9k_config_interface(struct ieee80211_hw *hw,
2172                                   struct ieee80211_vif *vif,
2173                                   struct ieee80211_if_conf *conf)
2174 {
2175         struct ath_softc *sc = hw->priv;
2176         struct ath_hal *ah = sc->sc_ah;
2177         struct ath_vap *avp = (void *)vif->drv_priv;
2178         u32 rfilt = 0;
2179         int error, i;
2180
2181         /* TODO: Need to decide which hw opmode to use for multi-interface
2182          * cases */
2183         if (vif->type == NL80211_IFTYPE_AP &&
2184             ah->ah_opmode != NL80211_IFTYPE_AP) {
2185                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2186                 ath9k_hw_setopmode(ah);
2187                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2188                 /* Request full reset to get hw opmode changed properly */
2189                 sc->sc_flags |= SC_OP_FULL_RESET;
2190         }
2191
2192         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2193             !is_zero_ether_addr(conf->bssid)) {
2194                 switch (vif->type) {
2195                 case NL80211_IFTYPE_STATION:
2196                 case NL80211_IFTYPE_ADHOC:
2197                         /* Set BSSID */
2198                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2199                         sc->sc_curaid = 0;
2200                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2201                                                sc->sc_curaid);
2202
2203                         /* Set aggregation protection mode parameters */
2204                         sc->sc_config.ath_aggr_prot = 0;
2205
2206                         DPRINTF(sc, ATH_DBG_CONFIG,
2207                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2208                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2209
2210                         /* need to reconfigure the beacon */
2211                         sc->sc_flags &= ~SC_OP_BEACONS ;
2212
2213                         break;
2214                 default:
2215                         break;
2216                 }
2217         }
2218
2219         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2220             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2221              (vif->type == NL80211_IFTYPE_AP))) {
2222                 /*
2223                  * Allocate and setup the beacon frame.
2224                  *
2225                  * Stop any previous beacon DMA.  This may be
2226                  * necessary, for example, when an ibss merge
2227                  * causes reconfiguration; we may be called
2228                  * with beacon transmission active.
2229                  */
2230                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2231
2232                 error = ath_beacon_alloc(sc, 0);
2233                 if (error != 0)
2234                         return error;
2235
2236                 ath_beacon_sync(sc, 0);
2237         }
2238
2239         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2240         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2241                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2242                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2243                                 ath9k_hw_keysetmac(sc->sc_ah,
2244                                                    (u16)i,
2245                                                    sc->sc_curbssid);
2246         }
2247
2248         /* Only legacy IBSS for now */
2249         if (vif->type == NL80211_IFTYPE_ADHOC)
2250                 ath_update_chainmask(sc, 0);
2251
2252         return 0;
2253 }
2254
2255 #define SUPPORTED_FILTERS                       \
2256         (FIF_PROMISC_IN_BSS |                   \
2257         FIF_ALLMULTI |                          \
2258         FIF_CONTROL |                           \
2259         FIF_OTHER_BSS |                         \
2260         FIF_BCN_PRBRESP_PROMISC |               \
2261         FIF_FCSFAIL)
2262
2263 /* FIXME: sc->sc_full_reset ? */
2264 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2265                                    unsigned int changed_flags,
2266                                    unsigned int *total_flags,
2267                                    int mc_count,
2268                                    struct dev_mc_list *mclist)
2269 {
2270         struct ath_softc *sc = hw->priv;
2271         u32 rfilt;
2272
2273         changed_flags &= SUPPORTED_FILTERS;
2274         *total_flags &= SUPPORTED_FILTERS;
2275
2276         sc->rx.rxfilter = *total_flags;
2277         rfilt = ath_calcrxfilter(sc);
2278         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2279
2280         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2281                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2282                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2283         }
2284
2285         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2286 }
2287
2288 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2289                              struct ieee80211_vif *vif,
2290                              enum sta_notify_cmd cmd,
2291                              struct ieee80211_sta *sta)
2292 {
2293         struct ath_softc *sc = hw->priv;
2294
2295         switch (cmd) {
2296         case STA_NOTIFY_ADD:
2297                 ath_node_attach(sc, sta);
2298                 break;
2299         case STA_NOTIFY_REMOVE:
2300                 ath_node_detach(sc, sta);
2301                 break;
2302         default:
2303                 break;
2304         }
2305 }
2306
2307 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2308                          u16 queue,
2309                          const struct ieee80211_tx_queue_params *params)
2310 {
2311         struct ath_softc *sc = hw->priv;
2312         struct ath9k_tx_queue_info qi;
2313         int ret = 0, qnum;
2314
2315         if (queue >= WME_NUM_AC)
2316                 return 0;
2317
2318         qi.tqi_aifs = params->aifs;
2319         qi.tqi_cwmin = params->cw_min;
2320         qi.tqi_cwmax = params->cw_max;
2321         qi.tqi_burstTime = params->txop;
2322         qnum = ath_get_hal_qnum(queue, sc);
2323
2324         DPRINTF(sc, ATH_DBG_CONFIG,
2325                 "Configure tx [queue/halq] [%d/%d],  "
2326                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2327                 queue, qnum, params->aifs, params->cw_min,
2328                 params->cw_max, params->txop);
2329
2330         ret = ath_txq_update(sc, qnum, &qi);
2331         if (ret)
2332                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2333
2334         return ret;
2335 }
2336
2337 static int ath9k_set_key(struct ieee80211_hw *hw,
2338                          enum set_key_cmd cmd,
2339                          struct ieee80211_vif *vif,
2340                          struct ieee80211_sta *sta,
2341                          struct ieee80211_key_conf *key)
2342 {
2343         struct ath_softc *sc = hw->priv;
2344         int ret = 0;
2345
2346         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2347
2348         switch (cmd) {
2349         case SET_KEY:
2350                 ret = ath_key_config(sc, sta, key);
2351                 if (ret >= 0) {
2352                         key->hw_key_idx = ret;
2353                         /* push IV and Michael MIC generation to stack */
2354                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2355                         if (key->alg == ALG_TKIP)
2356                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2357                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2358                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2359                         ret = 0;
2360                 }
2361                 break;
2362         case DISABLE_KEY:
2363                 ath_key_delete(sc, key);
2364                 break;
2365         default:
2366                 ret = -EINVAL;
2367         }
2368
2369         return ret;
2370 }
2371
2372 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2373                                    struct ieee80211_vif *vif,
2374                                    struct ieee80211_bss_conf *bss_conf,
2375                                    u32 changed)
2376 {
2377         struct ath_softc *sc = hw->priv;
2378
2379         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2380                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2381                         bss_conf->use_short_preamble);
2382                 if (bss_conf->use_short_preamble)
2383                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2384                 else
2385                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2386         }
2387
2388         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2389                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2390                         bss_conf->use_cts_prot);
2391                 if (bss_conf->use_cts_prot &&
2392                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2393                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2394                 else
2395                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2396         }
2397
2398         if (changed & BSS_CHANGED_ASSOC) {
2399                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2400                         bss_conf->assoc);
2401                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2402         }
2403 }
2404
2405 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2406 {
2407         u64 tsf;
2408         struct ath_softc *sc = hw->priv;
2409         struct ath_hal *ah = sc->sc_ah;
2410
2411         tsf = ath9k_hw_gettsf64(ah);
2412
2413         return tsf;
2414 }
2415
2416 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2417 {
2418         struct ath_softc *sc = hw->priv;
2419         struct ath_hal *ah = sc->sc_ah;
2420
2421         ath9k_hw_reset_tsf(ah);
2422 }
2423
2424 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2425                        enum ieee80211_ampdu_mlme_action action,
2426                        struct ieee80211_sta *sta,
2427                        u16 tid, u16 *ssn)
2428 {
2429         struct ath_softc *sc = hw->priv;
2430         int ret = 0;
2431
2432         switch (action) {
2433         case IEEE80211_AMPDU_RX_START:
2434                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2435                         ret = -ENOTSUPP;
2436                 break;
2437         case IEEE80211_AMPDU_RX_STOP:
2438                 break;
2439         case IEEE80211_AMPDU_TX_START:
2440                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2441                 if (ret < 0)
2442                         DPRINTF(sc, ATH_DBG_FATAL,
2443                                 "Unable to start TX aggregation\n");
2444                 else
2445                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2446                 break;
2447         case IEEE80211_AMPDU_TX_STOP:
2448                 ret = ath_tx_aggr_stop(sc, sta, tid);
2449                 if (ret < 0)
2450                         DPRINTF(sc, ATH_DBG_FATAL,
2451                                 "Unable to stop TX aggregation\n");
2452
2453                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2454                 break;
2455         case IEEE80211_AMPDU_TX_RESUME:
2456                 ath_tx_aggr_resume(sc, sta, tid);
2457                 break;
2458         default:
2459                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2460         }
2461
2462         return ret;
2463 }
2464
2465 static struct ieee80211_ops ath9k_ops = {
2466         .tx                 = ath9k_tx,
2467         .start              = ath9k_start,
2468         .stop               = ath9k_stop,
2469         .add_interface      = ath9k_add_interface,
2470         .remove_interface   = ath9k_remove_interface,
2471         .config             = ath9k_config,
2472         .config_interface   = ath9k_config_interface,
2473         .configure_filter   = ath9k_configure_filter,
2474         .sta_notify         = ath9k_sta_notify,
2475         .conf_tx            = ath9k_conf_tx,
2476         .bss_info_changed   = ath9k_bss_info_changed,
2477         .set_key            = ath9k_set_key,
2478         .get_tsf            = ath9k_get_tsf,
2479         .reset_tsf          = ath9k_reset_tsf,
2480         .ampdu_action       = ath9k_ampdu_action,
2481 };
2482
2483 static struct {
2484         u32 version;
2485         const char * name;
2486 } ath_mac_bb_names[] = {
2487         { AR_SREV_VERSION_5416_PCI,     "5416" },
2488         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2489         { AR_SREV_VERSION_9100,         "9100" },
2490         { AR_SREV_VERSION_9160,         "9160" },
2491         { AR_SREV_VERSION_9280,         "9280" },
2492         { AR_SREV_VERSION_9285,         "9285" }
2493 };
2494
2495 static struct {
2496         u16 version;
2497         const char * name;
2498 } ath_rf_names[] = {
2499         { 0,                            "5133" },
2500         { AR_RAD5133_SREV_MAJOR,        "5133" },
2501         { AR_RAD5122_SREV_MAJOR,        "5122" },
2502         { AR_RAD2133_SREV_MAJOR,        "2133" },
2503         { AR_RAD2122_SREV_MAJOR,        "2122" }
2504 };
2505
2506 /*
2507  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2508  */
2509 static const char *
2510 ath_mac_bb_name(u32 mac_bb_version)
2511 {
2512         int i;
2513
2514         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2515                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2516                         return ath_mac_bb_names[i].name;
2517                 }
2518         }
2519
2520         return "????";
2521 }
2522
2523 /*
2524  * Return the RF name. "????" is returned if the RF is unknown.
2525  */
2526 static const char *
2527 ath_rf_name(u16 rf_version)
2528 {
2529         int i;
2530
2531         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2532                 if (ath_rf_names[i].version == rf_version) {
2533                         return ath_rf_names[i].name;
2534                 }
2535         }
2536
2537         return "????";
2538 }
2539
2540 static void ath_pci_cleanup(struct ath_softc *sc)
2541 {
2542         struct pci_dev *pdev = to_pci_dev(sc->dev);
2543
2544         pci_iounmap(pdev, sc->mem);
2545         pci_release_region(pdev, 0);
2546         pci_disable_device(pdev);
2547 }
2548
2549 static struct ath_bus_ops ath_pci_bus_ops = {
2550         .read_cachesize = ath_pci_read_cachesize,
2551         .cleanup = ath_pci_cleanup,
2552 };
2553
2554 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2555 {
2556         void __iomem *mem;
2557         struct ath_softc *sc;
2558         struct ieee80211_hw *hw;
2559         u8 csz;
2560         u32 val;
2561         int ret = 0;
2562         struct ath_hal *ah;
2563
2564         if (pci_enable_device(pdev))
2565                 return -EIO;
2566
2567         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2568
2569         if (ret) {
2570                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2571                 goto bad;
2572         }
2573
2574         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2575
2576         if (ret) {
2577                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2578                         "DMA enable failed\n");
2579                 goto bad;
2580         }
2581
2582         /*
2583          * Cache line size is used to size and align various
2584          * structures used to communicate with the hardware.
2585          */
2586         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2587         if (csz == 0) {
2588                 /*
2589                  * Linux 2.4.18 (at least) writes the cache line size
2590                  * register as a 16-bit wide register which is wrong.
2591                  * We must have this setup properly for rx buffer
2592                  * DMA to work so force a reasonable value here if it
2593                  * comes up zero.
2594                  */
2595                 csz = L1_CACHE_BYTES / sizeof(u32);
2596                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2597         }
2598         /*
2599          * The default setting of latency timer yields poor results,
2600          * set it to the value used by other systems. It may be worth
2601          * tweaking this setting more.
2602          */
2603         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2604
2605         pci_set_master(pdev);
2606
2607         /*
2608          * Disable the RETRY_TIMEOUT register (0x41) to keep
2609          * PCI Tx retries from interfering with C3 CPU state.
2610          */
2611         pci_read_config_dword(pdev, 0x40, &val);
2612         if ((val & 0x0000ff00) != 0)
2613                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2614
2615         ret = pci_request_region(pdev, 0, "ath9k");
2616         if (ret) {
2617                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2618                 ret = -ENODEV;
2619                 goto bad;
2620         }
2621
2622         mem = pci_iomap(pdev, 0, 0);
2623         if (!mem) {
2624                 printk(KERN_ERR "PCI memory map error\n") ;
2625                 ret = -EIO;
2626                 goto bad1;
2627         }
2628
2629         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2630         if (hw == NULL) {
2631                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2632                 goto bad2;
2633         }
2634
2635         SET_IEEE80211_DEV(hw, &pdev->dev);
2636         pci_set_drvdata(pdev, hw);
2637
2638         sc = hw->priv;
2639         sc->hw = hw;
2640         sc->dev = &pdev->dev;
2641         sc->mem = mem;
2642         sc->bus_ops = &ath_pci_bus_ops;
2643
2644         if (ath_attach(id->device, sc) != 0) {
2645                 ret = -ENODEV;
2646                 goto bad3;
2647         }
2648
2649         /* setup interrupt service routine */
2650
2651         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2652                 printk(KERN_ERR "%s: request_irq failed\n",
2653                         wiphy_name(hw->wiphy));
2654                 ret = -EIO;
2655                 goto bad4;
2656         }
2657
2658         sc->irq = pdev->irq;
2659
2660         ah = sc->sc_ah;
2661         printk(KERN_INFO
2662                "%s: Atheros AR%s MAC/BB Rev:%x "
2663                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2664                wiphy_name(hw->wiphy),
2665                ath_mac_bb_name(ah->ah_macVersion),
2666                ah->ah_macRev,
2667                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2668                ah->ah_phyRev,
2669                (unsigned long)mem, pdev->irq);
2670
2671         return 0;
2672 bad4:
2673         ath_detach(sc);
2674 bad3:
2675         ieee80211_free_hw(hw);
2676 bad2:
2677         pci_iounmap(pdev, mem);
2678 bad1:
2679         pci_release_region(pdev, 0);
2680 bad:
2681         pci_disable_device(pdev);
2682         return ret;
2683 }
2684
2685 static void ath_pci_remove(struct pci_dev *pdev)
2686 {
2687         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2688         struct ath_softc *sc = hw->priv;
2689
2690         ath_cleanup(sc);
2691 }
2692
2693 #ifdef CONFIG_PM
2694
2695 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2696 {
2697         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2698         struct ath_softc *sc = hw->priv;
2699
2700         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2701
2702 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2703         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2704                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2705 #endif
2706
2707         pci_save_state(pdev);
2708         pci_disable_device(pdev);
2709         pci_set_power_state(pdev, PCI_D3hot);
2710
2711         return 0;
2712 }
2713
2714 static int ath_pci_resume(struct pci_dev *pdev)
2715 {
2716         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2717         struct ath_softc *sc = hw->priv;
2718         u32 val;
2719         int err;
2720
2721         err = pci_enable_device(pdev);
2722         if (err)
2723                 return err;
2724         pci_restore_state(pdev);
2725         /*
2726          * Suspend/Resume resets the PCI configuration space, so we have to
2727          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2728          * PCI Tx retries from interfering with C3 CPU state
2729          */
2730         pci_read_config_dword(pdev, 0x40, &val);
2731         if ((val & 0x0000ff00) != 0)
2732                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2733
2734         /* Enable LED */
2735         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2736                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2737         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2738
2739 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2740         /*
2741          * check the h/w rfkill state on resume
2742          * and start the rfkill poll timer
2743          */
2744         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2745                 queue_delayed_work(sc->hw->workqueue,
2746                                    &sc->rf_kill.rfkill_poll, 0);
2747 #endif
2748
2749         return 0;
2750 }
2751
2752 #endif /* CONFIG_PM */
2753
2754 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2755
2756 static struct pci_driver ath_pci_driver = {
2757         .name       = "ath9k",
2758         .id_table   = ath_pci_id_table,
2759         .probe      = ath_pci_probe,
2760         .remove     = ath_pci_remove,
2761 #ifdef CONFIG_PM
2762         .suspend    = ath_pci_suspend,
2763         .resume     = ath_pci_resume,
2764 #endif /* CONFIG_PM */
2765 };
2766
2767 static int __init init_ath_pci(void)
2768 {
2769         int error;
2770
2771         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2772
2773         /* Register rate control algorithm */
2774         error = ath_rate_control_register();
2775         if (error != 0) {
2776                 printk(KERN_ERR
2777                         "Unable to register rate control algorithm: %d\n",
2778                         error);
2779                 ath_rate_control_unregister();
2780                 return error;
2781         }
2782
2783         if (pci_register_driver(&ath_pci_driver) < 0) {
2784                 printk(KERN_ERR
2785                         "ath_pci: No devices found, driver not installed.\n");
2786                 ath_rate_control_unregister();
2787                 pci_unregister_driver(&ath_pci_driver);
2788                 return -ENODEV;
2789         }
2790
2791         return 0;
2792 }
2793 module_init(init_ath_pci);
2794
2795 static void __exit exit_ath_pci(void)
2796 {
2797         ath_rate_control_unregister();
2798         pci_unregister_driver(&ath_pci_driver);
2799         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2800 }
2801 module_exit(exit_ath_pci);