drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  27
  28 extern struct hal_percal_data iq_cal_multi_sample;
  29 extern struct hal_percal_data iq_cal_single_sample;
  30 extern struct hal_percal_data adc_gain_cal_multi_sample;
  31 extern struct hal_percal_data adc_gain_cal_single_sample;
  32 extern struct hal_percal_data adc_dc_cal_multi_sample;
  33 extern struct hal_percal_data adc_dc_cal_single_sample;
  34 extern struct hal_percal_data adc_init_dc_cal;
  35
  36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  38                               enum ath9k_ht_macmode macmode);
  39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  40                               struct ar5416_eeprom_def *pEepData,
  41                               u32 reg, u32 value);
  42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  44
  45 /********************/
  46 /* Helper Functions */
  47 /********************/
  48
  49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  50 {
  51         if (ah->ah_curchan != NULL)
  52                 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
  53         else
  54                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
  55 }
  56
  57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  58 {
  59         struct ath9k_channel *chan = ah->ah_curchan;
  60
  61         if (chan && IS_CHAN_HT40(chan))
  62                 return ath9k_hw_mac_usec(ah, clks) / 2;
  63         else
  64                 return ath9k_hw_mac_usec(ah, clks);
  65 }
  66
  67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  68 {
  69         if (ah->ah_curchan != NULL)
  70                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
  71                         ah->ah_curchan)];
  72         else
  73                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
  74 }
  75
  76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  77 {
  78         struct ath9k_channel *chan = ah->ah_curchan;
  79
  80         if (chan && IS_CHAN_HT40(chan))
  81                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  82         else
  83                 return ath9k_hw_mac_clks(ah, usecs);
  84 }
  85
  86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
  87                                const struct ath9k_channel *chan)
  88 {
  89         if (IS_CHAN_B(chan))
  90                 return ATH9K_MODE_11B;
  91         if (IS_CHAN_G(chan))
  92                 return ATH9K_MODE_11G;
  93
  94         return ATH9K_MODE_11A;
  95 }
  96
  97 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  98 {
  99         int i;
 100
 101         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 102                 if ((REG_READ(ah, reg) & mask) == val)
 103                         return true;
 104
 105                 udelay(AH_TIME_QUANTUM);
 106         }
 107
 108         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 109                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 110                 reg, REG_READ(ah, reg), mask, val);
 111
 112         return false;
 113 }
 114
 115 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 116 {
 117         u32 retval;
 118         int i;
 119
 120         for (i = 0, retval = 0; i < n; i++) {
 121                 retval = (retval << 1) | (val & 1);
 122                 val >>= 1;
 123         }
 124         return retval;
 125 }
 126
 127 bool ath9k_get_channel_edges(struct ath_hal *ah,
 128                              u16 flags, u16 *low,
 129                              u16 *high)
 130 {
 131         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 132
 133         if (flags & CHANNEL_5GHZ) {
 134                 *low = pCap->low_5ghz_chan;
 135                 *high = pCap->high_5ghz_chan;
 136                 return true;
 137         }
 138         if ((flags & CHANNEL_2GHZ)) {
 139                 *low = pCap->low_2ghz_chan;
 140                 *high = pCap->high_2ghz_chan;
 141                 return true;
 142         }
 143         return false;
 144 }
 145
 146 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 147                            struct ath_rate_table *rates,
 148                            u32 frameLen, u16 rateix,
 149                            bool shortPreamble)
 150 {
 151         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 152         u32 kbps;
 153
 154         kbps = rates->info[rateix].ratekbps;
 155
 156         if (kbps == 0)
 157                 return 0;
 158
 159         switch (rates->info[rateix].phy) {
 160         case WLAN_RC_PHY_CCK:
 161                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 162                 if (shortPreamble && rates->info[rateix].short_preamble)
 163                         phyTime >>= 1;
 164                 numBits = frameLen << 3;
 165                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 166                 break;
 167         case WLAN_RC_PHY_OFDM:
 168                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_QUARTER
 173                                 + OFDM_PREAMBLE_TIME_QUARTER
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 175                 } else if (ah->ah_curchan &&
 176                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 177                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 178                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 179                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 180                         txTime = OFDM_SIFS_TIME_HALF +
 181                                 OFDM_PREAMBLE_TIME_HALF
 182                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 183                 } else {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 188                                 + (numSymbols * OFDM_SYMBOL_TIME);
 189                 }
 190                 break;
 191         default:
 192                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 193                         "Unknown phy %u (rate ix %u)\n",
 194                         rates->info[rateix].phy, rateix);
 195                 txTime = 0;
 196                 break;
 197         }
 198
 199         return txTime;
 200 }
 201
 202 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 203 {
 204         if (flags & CHANNEL_2GHZ) {
 205                 if (freq == 2484)
 206                         return 14;
 207                 if (freq < 2484)
 208                         return (freq - 2407) / 5;
 209                 else
 210                         return 15 + ((freq - 2512) / 20);
 211         } else if (flags & CHANNEL_5GHZ) {
 212                 if (ath9k_regd_is_public_safety_sku(ah) &&
 213                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 214                         return ((freq * 10) +
 215                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
 216                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
 217                         return (freq - 4000) / 5;
 218                 } else {
 219                         return (freq - 5000) / 5;
 220                 }
 221         } else {
 222                 if (freq == 2484)
 223                         return 14;
 224                 if (freq < 2484)
 225                         return (freq - 2407) / 5;
 226                 if (freq < 5000) {
 227                         if (ath9k_regd_is_public_safety_sku(ah)
 228                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 229                                 return ((freq * 10) +
 230                                         (((freq % 5) ==
 231                                           2) ? 5 : 0) - 49400) / 5;
 232                         } else if (freq > 4900) {
 233                                 return (freq - 4000) / 5;
 234                         } else {
 235                                 return 15 + ((freq - 2512) / 20);
 236                         }
 237                 }
 238                 return (freq - 5000) / 5;
 239         }
 240 }
 241
 242 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 243                                   struct ath9k_channel *chan,
 244                                   struct chan_centers *centers)
 245 {
 246         int8_t extoff;
 247         struct ath_hal_5416 *ahp = AH5416(ah);
 248
 249         if (!IS_CHAN_HT40(chan)) {
 250                 centers->ctl_center = centers->ext_center =
 251                         centers->synth_center = chan->channel;
 252                 return;
 253         }
 254
 255         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 256             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 257                 centers->synth_center =
 258                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 259                 extoff = 1;
 260         } else {
 261                 centers->synth_center =
 262                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 263                 extoff = -1;
 264         }
 265
 266         centers->ctl_center =
 267                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 268         centers->ext_center =
 269                 centers->synth_center + (extoff *
 270                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 271                           HT40_CHANNEL_CENTER_SHIFT : 15));
 272
 273 }
 274
 275 /******************/
 276 /* Chip Revisions */
 277 /******************/
 278
 279 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 280 {
 281         u32 val;
 282
 283         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 284
 285         if (val == 0xFF) {
 286                 val = REG_READ(ah, AR_SREV);
 287                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 288                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 289                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 290         } else {
 291                 if (!AR_SREV_9100(ah))
 292                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 293
 294                 ah->ah_macRev = val & AR_SREV_REVISION;
 295
 296                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 297                         ah->ah_isPciExpress = true;
 298         }
 299 }
 300
 301 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 302 {
 303         u32 val;
 304         int i;
 305
 306         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 307
 308         for (i = 0; i < 8; i++)
 309                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 310         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 311         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 312
 313         return ath9k_hw_reverse_bits(val, 8);
 314 }
 315
 316 /************************************/
 317 /* HW Attach, Detach, Init Routines */
 318 /************************************/
 319
 320 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 321 {
 322         if (!AR_SREV_9100(ah))
 323                 return;
 324
 325         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 326         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 327         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 328         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 329         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 330         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 331         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 332         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 333         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 334
 335         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 336 }
 337
 338 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 339 {
 340         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 341         u32 regHold[2];
 342         u32 patternData[4] = { 0x55555555,
 343                                0xaaaaaaaa,
 344                                0x66666666,
 345                                0x99999999 };
 346         int i, j;
 347
 348         for (i = 0; i < 2; i++) {
 349                 u32 addr = regAddr[i];
 350                 u32 wrData, rdData;
 351
 352                 regHold[i] = REG_READ(ah, addr);
 353                 for (j = 0; j < 0x100; j++) {
 354                         wrData = (j << 16) | j;
 355                         REG_WRITE(ah, addr, wrData);
 356                         rdData = REG_READ(ah, addr);
 357                         if (rdData != wrData) {
 358                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 359                                         "address test failed "
 360                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 361                                         addr, wrData, rdData);
 362                                 return false;
 363                         }
 364                 }
 365                 for (j = 0; j < 4; j++) {
 366                         wrData = patternData[j];
 367                         REG_WRITE(ah, addr, wrData);
 368                         rdData = REG_READ(ah, addr);
 369                         if (wrData != rdData) {
 370                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 371                                         "address test failed "
 372                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 373                                         addr, wrData, rdData);
 374                                 return false;
 375                         }
 376                 }
 377                 REG_WRITE(ah, regAddr[i], regHold[i]);
 378         }
 379         udelay(100);
 380         return true;
 381 }
 382
 383 static const char *ath9k_hw_devname(u16 devid)
 384 {
 385         switch (devid) {
 386         case AR5416_DEVID_PCI:
 387                 return "Atheros 5416";
 388         case AR5416_DEVID_PCIE:
 389                 return "Atheros 5418";
 390         case AR9160_DEVID_PCI:
 391                 return "Atheros 9160";
 392         case AR9280_DEVID_PCI:
 393         case AR9280_DEVID_PCIE:
 394                 return "Atheros 9280";
 395         case AR9285_DEVID_PCIE:
 396                 return "Atheros 9285";
 397         }
 398
 399         return NULL;
 400 }
 401
 402 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 403 {
 404         int i;
 405
 406         ah->ah_config.dma_beacon_response_time = 2;
 407         ah->ah_config.sw_beacon_response_time = 10;
 408         ah->ah_config.additional_swba_backoff = 0;
 409         ah->ah_config.ack_6mb = 0x0;
 410         ah->ah_config.cwm_ignore_extcca = 0;
 411         ah->ah_config.pcie_powersave_enable = 0;
 412         ah->ah_config.pcie_l1skp_enable = 0;
 413         ah->ah_config.pcie_clock_req = 0;
 414         ah->ah_config.pcie_power_reset = 0x100;
 415         ah->ah_config.pcie_restore = 0;
 416         ah->ah_config.pcie_waen = 0;
 417         ah->ah_config.analog_shiftreg = 1;
 418         ah->ah_config.ht_enable = 1;
 419         ah->ah_config.ofdm_trig_low = 200;
 420         ah->ah_config.ofdm_trig_high = 500;
 421         ah->ah_config.cck_trig_high = 200;
 422         ah->ah_config.cck_trig_low = 100;
 423         ah->ah_config.enable_ani = 1;
 424         ah->ah_config.noise_immunity_level = 4;
 425         ah->ah_config.ofdm_weaksignal_det = 1;
 426         ah->ah_config.cck_weaksignal_thr = 0;
 427         ah->ah_config.spur_immunity_level = 2;
 428         ah->ah_config.firstep_level = 0;
 429         ah->ah_config.rssi_thr_high = 40;
 430         ah->ah_config.rssi_thr_low = 7;
 431         ah->ah_config.diversity_control = 0;
 432         ah->ah_config.antenna_switch_swap = 0;
 433
 434         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 435                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 436                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 437         }
 438
 439         ah->ah_config.intr_mitigation = 1;
 440 }
 441
 442 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 443                                               struct ath_softc *sc,
 444                                               void __iomem *mem,
 445                                               int *status)
 446 {
 447         static const u8 defbssidmask[ETH_ALEN] =
 448                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 449         struct ath_hal_5416 *ahp;
 450         struct ath_hal *ah;
 451
 452         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 453         if (ahp == NULL) {
 454                 DPRINTF(sc, ATH_DBG_FATAL,
 455                         "Cannot allocate memory for state block\n");
 456                 *status = -ENOMEM;
 457                 return NULL;
 458         }
 459
 460         ah = &ahp->ah;
 461         ah->ah_sc = sc;
 462         ah->ah_sh = mem;
 463         ah->ah_magic = AR5416_MAGIC;
 464         ah->ah_countryCode = CTRY_DEFAULT;
 465         ah->ah_devid = devid;
 466         ah->ah_subvendorid = 0;
 467
 468         ah->ah_flags = 0;
 469         if ((devid == AR5416_AR9100_DEVID))
 470                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 471         if (!AR_SREV_9100(ah))
 472                 ah->ah_flags = AH_USE_EEPROM;
 473
 474         ah->ah_powerLimit = MAX_RATE_POWER;
 475         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 476         ahp->ah_atimWindow = 0;
 477         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 478         ahp->ah_antennaSwitchSwap =
 479                 ah->ah_config.antenna_switch_swap;
 480         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 481         ahp->ah_beaconInterval = 100;
 482         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 483         ahp->ah_slottime = (u32) -1;
 484         ahp->ah_acktimeout = (u32) -1;
 485         ahp->ah_ctstimeout = (u32) -1;
 486         ahp->ah_globaltxtimeout = (u32) -1;
 487         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 488
 489         ahp->ah_gBeaconRate = 0;
 490
 491         return ahp;
 492 }
 493
 494 static int ath9k_hw_rfattach(struct ath_hal *ah)
 495 {
 496         bool rfStatus = false;
 497         int ecode = 0;
 498
 499         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 500         if (!rfStatus) {
 501                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 502                         "RF setup failed, status %u\n", ecode);
 503                 return ecode;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 510 {
 511         u32 val;
 512
 513         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 514
 515         val = ath9k_hw_get_radiorev(ah);
 516         switch (val & AR_RADIO_SREV_MAJOR) {
 517         case 0:
 518                 val = AR_RAD5133_SREV_MAJOR;
 519                 break;
 520         case AR_RAD5133_SREV_MAJOR:
 521         case AR_RAD5122_SREV_MAJOR:
 522         case AR_RAD2133_SREV_MAJOR:
 523         case AR_RAD2122_SREV_MAJOR:
 524                 break;
 525         default:
 526                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 527                         "5G Radio Chip Rev 0x%02X is not "
 528                         "supported by this driver\n",
 529                         ah->ah_analog5GhzRev);
 530                 return -EOPNOTSUPP;
 531         }
 532
 533         ah->ah_analog5GhzRev = val;
 534
 535         return 0;
 536 }
 537
 538 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 539 {
 540         u32 sum;
 541         int i;
 542         u16 eeval;
 543         struct ath_hal_5416 *ahp = AH5416(ah);
 544
 545         sum = 0;
 546         for (i = 0; i < 3; i++) {
 547                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 548                 sum += eeval;
 549                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 550                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 551         }
 552         if (sum == 0 || sum == 0xffff * 3) {
 553                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 554                         "mac address read failed: %pM\n",
 555                         ahp->ah_macaddr);
 556                 return -EADDRNOTAVAIL;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 563 {
 564         u32 rxgain_type;
 565         struct ath_hal_5416 *ahp = AH5416(ah);
 566
 567         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 568                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 569
 570                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 571                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 572                         ar9280Modes_backoff_13db_rxgain_9280_2,
 573                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 574                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 575                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 576                         ar9280Modes_backoff_23db_rxgain_9280_2,
 577                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 578                 else
 579                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 580                         ar9280Modes_original_rxgain_9280_2,
 581                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 582         } else
 583                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 584                         ar9280Modes_original_rxgain_9280_2,
 585                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 586 }
 587
 588 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 589 {
 590         u32 txgain_type;
 591         struct ath_hal_5416 *ahp = AH5416(ah);
 592
 593         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 594                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 595
 596                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 597                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 598                         ar9280Modes_high_power_tx_gain_9280_2,
 599                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 600                 else
 601                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 602                         ar9280Modes_original_tx_gain_9280_2,
 603                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 604         } else
 605                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 606                 ar9280Modes_original_tx_gain_9280_2,
 607                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 608 }
 609
 610 static int ath9k_hw_post_attach(struct ath_hal *ah)
 611 {
 612         int ecode;
 613
 614         if (!ath9k_hw_chip_test(ah)) {
 615                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 616                         "hardware self-test failed\n");
 617                 return -ENODEV;
 618         }
 619
 620         ecode = ath9k_hw_rf_claim(ah);
 621         if (ecode != 0)
 622                 return ecode;
 623
 624         ecode = ath9k_hw_eeprom_attach(ah);
 625         if (ecode != 0)
 626                 return ecode;
 627         ecode = ath9k_hw_rfattach(ah);
 628         if (ecode != 0)
 629                 return ecode;
 630
 631         if (!AR_SREV_9100(ah)) {
 632                 ath9k_hw_ani_setup(ah);
 633                 ath9k_hw_ani_attach(ah);
 634         }
 635
 636         return 0;
 637 }
 638
 639 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 640                                           void __iomem *mem, int *status)
 641 {
 642         struct ath_hal_5416 *ahp;
 643         struct ath_hal *ah;
 644         int ecode;
 645         u32 i, j;
 646
 647         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 648         if (ahp == NULL)
 649                 return NULL;
 650
 651         ah = &ahp->ah;
 652
 653         ath9k_hw_set_defaults(ah);
 654
 655         if (ah->ah_config.intr_mitigation != 0)
 656                 ahp->ah_intrMitigation = true;
 657
 658         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 659                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 660                 ecode = -EIO;
 661                 goto bad;
 662         }
 663
 664         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 665                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 666                 ecode = -EIO;
 667                 goto bad;
 668         }
 669
 670         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 671                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 672                         ah->ah_config.serialize_regmode =
 673                                 SER_REG_MODE_ON;
 674                 } else {
 675                         ah->ah_config.serialize_regmode =
 676                                 SER_REG_MODE_OFF;
 677                 }
 678         }
 679
 680         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 681                 "serialize_regmode is %d\n",
 682                 ah->ah_config.serialize_regmode);
 683
 684         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 685             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 686             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 687             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 688                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 689                         "Mac Chip Rev 0x%02x.%x is not supported by "
 690                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
 691                 ecode = -EOPNOTSUPP;
 692                 goto bad;
 693         }
 694
 695         if (AR_SREV_9100(ah)) {
 696                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 697                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 698                 ah->ah_isPciExpress = false;
 699         }
 700         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 701
 702         if (AR_SREV_9160_10_OR_LATER(ah)) {
 703                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 704                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 705                         ahp->ah_adcGainCalData.calData =
 706                                 &adc_gain_cal_single_sample;
 707                         ahp->ah_adcDcCalData.calData =
 708                                 &adc_dc_cal_single_sample;
 709                         ahp->ah_adcDcCalInitData.calData =
 710                                 &adc_init_dc_cal;
 711                 } else {
 712                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 713                         ahp->ah_adcGainCalData.calData =
 714                                 &adc_gain_cal_multi_sample;
 715                         ahp->ah_adcDcCalData.calData =
 716                                 &adc_dc_cal_multi_sample;
 717                         ahp->ah_adcDcCalInitData.calData =
 718                                 &adc_init_dc_cal;
 719                 }
 720                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 721         }
 722
 723         if (AR_SREV_9160(ah)) {
 724                 ah->ah_config.enable_ani = 1;
 725                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 726                                         ATH9K_ANI_FIRSTEP_LEVEL);
 727         } else {
 728                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 729                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 730                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 731                 }
 732         }
 733
 734         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 735                 "This Mac Chip Rev 0x%02x.%x is \n",
 736                 ah->ah_macVersion, ah->ah_macRev);
 737
 738         if (AR_SREV_9285_12_OR_LATER(ah)) {
 739                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
 740                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 741                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
 742                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 743
 744                 if (ah->ah_config.pcie_clock_req) {
 745                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 746                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 747                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 748                 } else {
 749                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 750                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 751                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 752                                   2);
 753                 }
 754         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 755                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
 756                                ARRAY_SIZE(ar9285Modes_9285), 6);
 757                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
 758                                ARRAY_SIZE(ar9285Common_9285), 2);
 759
 760                 if (ah->ah_config.pcie_clock_req) {
 761                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 762                         ar9285PciePhy_clkreq_off_L1_9285,
 763                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 764                 } else {
 765                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 766                         ar9285PciePhy_clkreq_always_on_L1_9285,
 767                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 768                 }
 769         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 770                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 771                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 772                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 773                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 774
 775                 if (ah->ah_config.pcie_clock_req) {
 776                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 777                                ar9280PciePhy_clkreq_off_L1_9280,
 778                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 779                 } else {
 780                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 781                                ar9280PciePhy_clkreq_always_on_L1_9280,
 782                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 783                 }
 784                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 785                                ar9280Modes_fast_clock_9280_2,
 786                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 787         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 788                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 789                                ARRAY_SIZE(ar9280Modes_9280), 6);
 790                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 791                                ARRAY_SIZE(ar9280Common_9280), 2);
 792         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 793                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 794                                ARRAY_SIZE(ar5416Modes_9160), 6);
 795                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 796                                ARRAY_SIZE(ar5416Common_9160), 2);
 797                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 798                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 799                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 800                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 801                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 802                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 803                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 804                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 805                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 806                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 807                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 808                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 809                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 810                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 811                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 812                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 813                 if (AR_SREV_9160_11(ah)) {
 814                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 815                                        ar5416Addac_91601_1,
 816                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 817                 } else {
 818                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 819                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 820                 }
 821         } else if (AR_SREV_9100_OR_LATER(ah)) {
 822                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 823                                ARRAY_SIZE(ar5416Modes_9100), 6);
 824                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 825                                ARRAY_SIZE(ar5416Common_9100), 2);
 826                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 827                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 828                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 829                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 830                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 831                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 832                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 833                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 834                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 835                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 836                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 837                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 838                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 839                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 840                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 841                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 842                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 843                                ARRAY_SIZE(ar5416Addac_9100), 2);
 844         } else {
 845                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 846                                ARRAY_SIZE(ar5416Modes), 6);
 847                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 848                                ARRAY_SIZE(ar5416Common), 2);
 849                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 850                                ARRAY_SIZE(ar5416Bank0), 2);
 851                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 852                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 853                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 854                                ARRAY_SIZE(ar5416Bank1), 2);
 855                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 856                                ARRAY_SIZE(ar5416Bank2), 2);
 857                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 858                                ARRAY_SIZE(ar5416Bank3), 3);
 859                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 860                                ARRAY_SIZE(ar5416Bank6), 3);
 861                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 862                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 863                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 864                                ARRAY_SIZE(ar5416Bank7), 2);
 865                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 866                                ARRAY_SIZE(ar5416Addac), 2);
 867         }
 868
 869         if (ah->ah_isPciExpress)
 870                 ath9k_hw_configpcipowersave(ah, 0);
 871         else
 872                 ath9k_hw_disablepcie(ah);
 873
 874         ecode = ath9k_hw_post_attach(ah);
 875         if (ecode != 0)
 876                 goto bad;
 877
 878         /* rxgain table */
 879         if (AR_SREV_9280_20(ah))
 880                 ath9k_hw_init_rxgain_ini(ah);
 881
 882         /* txgain table */
 883         if (AR_SREV_9280_20(ah))
 884                 ath9k_hw_init_txgain_ini(ah);
 885
 886         if (ah->ah_devid == AR9280_DEVID_PCI) {
 887                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 888                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 889
 890                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 891                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 892
 893                                 INI_RA(&ahp->ah_iniModes, i, j) =
 894                                         ath9k_hw_ini_fixup(ah,
 895                                                            &ahp->ah_eeprom.def,
 896                                                            reg, val);
 897                         }
 898                 }
 899         }
 900
 901         if (!ath9k_hw_fill_cap_info(ah)) {
 902                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 903                         "failed ath9k_hw_fill_cap_info\n");
 904                 ecode = -EINVAL;
 905                 goto bad;
 906         }
 907
 908         ecode = ath9k_hw_init_macaddr(ah);
 909         if (ecode != 0) {
 910                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 911                         "failed initializing mac address\n");
 912                 goto bad;
 913         }
 914
 915         if (AR_SREV_9285(ah))
 916                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 917         else
 918                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 919
 920         ath9k_init_nfcal_hist_buffer(ah);
 921
 922         return ah;
 923 bad:
 924         if (ahp)
 925                 ath9k_hw_detach((struct ath_hal *) ahp);
 926         if (status)
 927                 *status = ecode;
 928
 929         return NULL;
 930 }
 931
 932 static void ath9k_hw_init_bb(struct ath_hal *ah,
 933                              struct ath9k_channel *chan)
 934 {
 935         u32 synthDelay;
 936
 937         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 938         if (IS_CHAN_B(chan))
 939                 synthDelay = (4 * synthDelay) / 22;
 940         else
 941                 synthDelay /= 10;
 942
 943         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 944
 945         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 946 }
 947
 948 static void ath9k_hw_init_qos(struct ath_hal *ah)
 949 {
 950         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 951         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 952
 953         REG_WRITE(ah, AR_QOS_NO_ACK,
 954                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 955                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 956                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 957
 958         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 959         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 960         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 961         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 962         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 963 }
 964
 965 static void ath9k_hw_init_pll(struct ath_hal *ah,
 966                               struct ath9k_channel *chan)
 967 {
 968         u32 pll;
 969
 970         if (AR_SREV_9100(ah)) {
 971                 if (chan && IS_CHAN_5GHZ(chan))
 972                         pll = 0x1450;
 973                 else
 974                         pll = 0x1458;
 975         } else {
 976                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 977                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 978
 979                         if (chan && IS_CHAN_HALF_RATE(chan))
 980                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 981                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 982                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 983
 984                         if (chan && IS_CHAN_5GHZ(chan)) {
 985                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 986
 987
 988                                 if (AR_SREV_9280_20(ah)) {
 989                                         if (((chan->channel % 20) == 0)
 990                                             || ((chan->channel % 10) == 0))
 991                                                 pll = 0x2850;
 992                                         else
 993                                                 pll = 0x142c;
 994                                 }
 995                         } else {
 996                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 997                         }
 998
 999                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1000
1001                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1002
1003                         if (chan && IS_CHAN_HALF_RATE(chan))
1004                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1005                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1006                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1007
1008                         if (chan && IS_CHAN_5GHZ(chan))
1009                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1010                         else
1011                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1012                 } else {
1013                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1014
1015                         if (chan && IS_CHAN_HALF_RATE(chan))
1016                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1017                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1018                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1019
1020                         if (chan && IS_CHAN_5GHZ(chan))
1021                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1022                         else
1023                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1024                 }
1025         }
1026         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1027
1028         udelay(RTC_PLL_SETTLE_DELAY);
1029
1030         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1031 }
1032
1033 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1034 {
1035         struct ath_hal_5416 *ahp = AH5416(ah);
1036         int rx_chainmask, tx_chainmask;
1037
1038         rx_chainmask = ahp->ah_rxchainmask;
1039         tx_chainmask = ahp->ah_txchainmask;
1040
1041         switch (rx_chainmask) {
1042         case 0x5:
1043                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044                             AR_PHY_SWAP_ALT_CHAIN);
1045         case 0x3:
1046                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1047                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1048                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1049                         break;
1050                 }
1051         case 0x1:
1052         case 0x2:
1053         case 0x7:
1054                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1055                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1056                 break;
1057         default:
1058                 break;
1059         }
1060
1061         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1062         if (tx_chainmask == 0x5) {
1063                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1064                             AR_PHY_SWAP_ALT_CHAIN);
1065         }
1066         if (AR_SREV_9100(ah))
1067                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1068                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1069 }
1070
1071 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1072                                           enum nl80211_iftype opmode)
1073 {
1074         struct ath_hal_5416 *ahp = AH5416(ah);
1075
1076         ahp->ah_maskReg = AR_IMR_TXERR |
1077                 AR_IMR_TXURN |
1078                 AR_IMR_RXERR |
1079                 AR_IMR_RXORN |
1080                 AR_IMR_BCNMISC;
1081
1082         if (ahp->ah_intrMitigation)
1083                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1084         else
1085                 ahp->ah_maskReg |= AR_IMR_RXOK;
1086
1087         ahp->ah_maskReg |= AR_IMR_TXOK;
1088
1089         if (opmode == NL80211_IFTYPE_AP)
1090                 ahp->ah_maskReg |= AR_IMR_MIB;
1091
1092         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1093         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1094
1095         if (!AR_SREV_9100(ah)) {
1096                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1097                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1098                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1099         }
1100 }
1101
1102 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1103 {
1104         struct ath_hal_5416 *ahp = AH5416(ah);
1105
1106         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1107                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1108                 ahp->ah_acktimeout = (u32) -1;
1109                 return false;
1110         } else {
1111                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1112                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1113                 ahp->ah_acktimeout = us;
1114                 return true;
1115         }
1116 }
1117
1118 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1119 {
1120         struct ath_hal_5416 *ahp = AH5416(ah);
1121
1122         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1123                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1124                 ahp->ah_ctstimeout = (u32) -1;
1125                 return false;
1126         } else {
1127                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1128                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1129                 ahp->ah_ctstimeout = us;
1130                 return true;
1131         }
1132 }
1133
1134 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1135 {
1136         struct ath_hal_5416 *ahp = AH5416(ah);
1137
1138         if (tu > 0xFFFF) {
1139                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1140                         "bad global tx timeout %u\n", tu);
1141                 ahp->ah_globaltxtimeout = (u32) -1;
1142                 return false;
1143         } else {
1144                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1145                 ahp->ah_globaltxtimeout = tu;
1146                 return true;
1147         }
1148 }
1149
1150 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1151 {
1152         struct ath_hal_5416 *ahp = AH5416(ah);
1153
1154         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1155                 ahp->ah_miscMode);
1156
1157         if (ahp->ah_miscMode != 0)
1158                 REG_WRITE(ah, AR_PCU_MISC,
1159                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1160         if (ahp->ah_slottime != (u32) -1)
1161                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1162         if (ahp->ah_acktimeout != (u32) -1)
1163                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1164         if (ahp->ah_ctstimeout != (u32) -1)
1165                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1166         if (ahp->ah_globaltxtimeout != (u32) -1)
1167                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1168 }
1169
1170 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1171 {
1172         return vendorid == ATHEROS_VENDOR_ID ?
1173                 ath9k_hw_devname(devid) : NULL;
1174 }
1175
1176 void ath9k_hw_detach(struct ath_hal *ah)
1177 {
1178         if (!AR_SREV_9100(ah))
1179                 ath9k_hw_ani_detach(ah);
1180
1181         ath9k_hw_rfdetach(ah);
1182         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1183         kfree(ah);
1184 }
1185
1186 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1187                                 void __iomem *mem, int *error)
1188 {
1189         struct ath_hal *ah = NULL;
1190
1191         switch (devid) {
1192         case AR5416_DEVID_PCI:
1193         case AR5416_DEVID_PCIE:
1194         case AR9160_DEVID_PCI:
1195         case AR9280_DEVID_PCI:
1196         case AR9280_DEVID_PCIE:
1197         case AR9285_DEVID_PCIE:
1198                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1199                 break;
1200         default:
1201                 *error = -ENXIO;
1202                 break;
1203         }
1204
1205         return ah;
1206 }
1207
1208 /*******/
1209 /* INI */
1210 /*******/
1211
1212 static void ath9k_hw_override_ini(struct ath_hal *ah,
1213                                   struct ath9k_channel *chan)
1214 {
1215         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1216             AR_SREV_9280_10_OR_LATER(ah))
1217                 return;
1218
1219         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1220 }
1221
1222 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1223                               struct ar5416_eeprom_def *pEepData,
1224                               u32 reg, u32 value)
1225 {
1226         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1227
1228         switch (ah->ah_devid) {
1229         case AR9280_DEVID_PCI:
1230                 if (reg == 0x7894) {
1231                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1232                                 "ini VAL: %x  EEPROM: %x\n", value,
1233                                 (pBase->version & 0xff));
1234
1235                         if ((pBase->version & 0xff) > 0x0a) {
1236                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1237                                         "PWDCLKIND: %d\n",
1238                                         pBase->pwdclkind);
1239                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1240                                 value |= AR_AN_TOP2_PWDCLKIND &
1241                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1242                         } else {
1243                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1244                                         "PWDCLKIND Earlier Rev\n");
1245                         }
1246
1247                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1248                                 "final ini VAL: %x\n", value);
1249                 }
1250                 break;
1251         }
1252
1253         return value;
1254 }
1255
1256 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1257                               struct ar5416_eeprom_def *pEepData,
1258                               u32 reg, u32 value)
1259 {
1260         struct ath_hal_5416 *ahp = AH5416(ah);
1261
1262         if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1263                 return value;
1264         else
1265                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1266 }
1267
1268 static int ath9k_hw_process_ini(struct ath_hal *ah,
1269                                 struct ath9k_channel *chan,
1270                                 enum ath9k_ht_macmode macmode)
1271 {
1272         int i, regWrites = 0;
1273         struct ath_hal_5416 *ahp = AH5416(ah);
1274         u32 modesIndex, freqIndex;
1275         int status;
1276
1277         switch (chan->chanmode) {
1278         case CHANNEL_A:
1279         case CHANNEL_A_HT20:
1280                 modesIndex = 1;
1281                 freqIndex = 1;
1282                 break;
1283         case CHANNEL_A_HT40PLUS:
1284         case CHANNEL_A_HT40MINUS:
1285                 modesIndex = 2;
1286                 freqIndex = 1;
1287                 break;
1288         case CHANNEL_G:
1289         case CHANNEL_G_HT20:
1290         case CHANNEL_B:
1291                 modesIndex = 4;
1292                 freqIndex = 2;
1293                 break;
1294         case CHANNEL_G_HT40PLUS:
1295         case CHANNEL_G_HT40MINUS:
1296                 modesIndex = 3;
1297                 freqIndex = 2;
1298                 break;
1299
1300         default:
1301                 return -EINVAL;
1302         }
1303
1304         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1305
1306         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1307
1308         ath9k_hw_set_addac(ah, chan);
1309
1310         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1311                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1312         } else {
1313                 struct ar5416IniArray temp;
1314                 u32 addacSize =
1315                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1316                         ahp->ah_iniAddac.ia_columns;
1317
1318                 memcpy(ahp->ah_addac5416_21,
1319                        ahp->ah_iniAddac.ia_array, addacSize);
1320
1321                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1322
1323                 temp.ia_array = ahp->ah_addac5416_21;
1324                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1325                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1326                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1327         }
1328
1329         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1330
1331         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1332                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1333                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1334
1335                 REG_WRITE(ah, reg, val);
1336
1337                 if (reg >= 0x7800 && reg < 0x78a0
1338                     && ah->ah_config.analog_shiftreg) {
1339                         udelay(100);
1340                 }
1341
1342                 DO_DELAY(regWrites);
1343         }
1344
1345         if (AR_SREV_9280(ah))
1346                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1347
1348         if (AR_SREV_9280(ah))
1349                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1350
1351         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1352                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1353                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1354
1355                 REG_WRITE(ah, reg, val);
1356
1357                 if (reg >= 0x7800 && reg < 0x78a0
1358                     && ah->ah_config.analog_shiftreg) {
1359                         udelay(100);
1360                 }
1361
1362                 DO_DELAY(regWrites);
1363         }
1364
1365         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1366
1367         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1368                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1369                                 regWrites);
1370         }
1371
1372         ath9k_hw_override_ini(ah, chan);
1373         ath9k_hw_set_regs(ah, chan, macmode);
1374         ath9k_hw_init_chain_masks(ah);
1375
1376         status = ath9k_hw_set_txpower(ah, chan,
1377                                       ath9k_regd_get_ctl(ah, chan),
1378                                       ath9k_regd_get_antenna_allowed(ah,
1379                                                                      chan),
1380                                       chan->maxRegTxPower * 2,
1381                                       min((u32) MAX_RATE_POWER,
1382                                           (u32) ah->ah_powerLimit));
1383         if (status != 0) {
1384                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1385                         "error init'ing transmit power\n");
1386                 return -EIO;
1387         }
1388
1389         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1390                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1391                         "ar5416SetRfRegs failed\n");
1392                 return -EIO;
1393         }
1394
1395         return 0;
1396 }
1397
1398 /****************************************/
1399 /* Reset and Channel Switching Routines */
1400 /****************************************/
1401
1402 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1403 {
1404         u32 rfMode = 0;
1405
1406         if (chan == NULL)
1407                 return;
1408
1409         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1410                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1411
1412         if (!AR_SREV_9280_10_OR_LATER(ah))
1413                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1414                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1415
1416         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1417                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1418
1419         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1420 }
1421
1422 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1423 {
1424         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1425 }
1426
1427 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1428 {
1429         u32 regval;
1430
1431         regval = REG_READ(ah, AR_AHB_MODE);
1432         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1433
1434         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1435         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1436
1437         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1438
1439         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1440         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1441
1442         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1443
1444         if (AR_SREV_9285(ah)) {
1445                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1446                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1447         } else {
1448                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1449                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1450         }
1451 }
1452
1453 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1454 {
1455         u32 val;
1456
1457         val = REG_READ(ah, AR_STA_ID1);
1458         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1459         switch (opmode) {
1460         case NL80211_IFTYPE_AP:
1461                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1462                           | AR_STA_ID1_KSRCH_MODE);
1463                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1464                 break;
1465         case NL80211_IFTYPE_ADHOC:
1466                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1467                           | AR_STA_ID1_KSRCH_MODE);
1468                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1469                 break;
1470         case NL80211_IFTYPE_STATION:
1471         case NL80211_IFTYPE_MONITOR:
1472                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1473                 break;
1474         }
1475 }
1476
1477 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1478                                                  u32 coef_scaled,
1479                                                  u32 *coef_mantissa,
1480                                                  u32 *coef_exponent)
1481 {
1482         u32 coef_exp, coef_man;
1483
1484         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1485                 if ((coef_scaled >> coef_exp) & 0x1)
1486                         break;
1487
1488         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1489
1490         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1491
1492         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1493         *coef_exponent = coef_exp - 16;
1494 }
1495
1496 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1497                                      struct ath9k_channel *chan)
1498 {
1499         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1500         u32 clockMhzScaled = 0x64000000;
1501         struct chan_centers centers;
1502
1503         if (IS_CHAN_HALF_RATE(chan))
1504                 clockMhzScaled = clockMhzScaled >> 1;
1505         else if (IS_CHAN_QUARTER_RATE(chan))
1506                 clockMhzScaled = clockMhzScaled >> 2;
1507
1508         ath9k_hw_get_channel_centers(ah, chan, &centers);
1509         coef_scaled = clockMhzScaled / centers.synth_center;
1510
1511         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1512                                       &ds_coef_exp);
1513
1514         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1515                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1516         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1517                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1518
1519         coef_scaled = (9 * coef_scaled) / 10;
1520
1521         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1522                                       &ds_coef_exp);
1523
1524         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1525                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1526         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1527                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1528 }
1529
1530 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1531 {
1532         u32 rst_flags;
1533         u32 tmpReg;
1534
1535         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1536                   AR_RTC_FORCE_WAKE_ON_INT);
1537
1538         if (AR_SREV_9100(ah)) {
1539                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1540                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1541         } else {
1542                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1543                 if (tmpReg &
1544                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1545                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1546                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1547                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1548                 } else {
1549                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1550                 }
1551
1552                 rst_flags = AR_RTC_RC_MAC_WARM;
1553                 if (type == ATH9K_RESET_COLD)
1554                         rst_flags |= AR_RTC_RC_MAC_COLD;
1555         }
1556
1557         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1558         udelay(50);
1559
1560         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1561         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1562                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1563                         "RTC stuck in MAC reset\n");
1564                 return false;
1565         }
1566
1567         if (!AR_SREV_9100(ah))
1568                 REG_WRITE(ah, AR_RC, 0);
1569
1570         ath9k_hw_init_pll(ah, NULL);
1571
1572         if (AR_SREV_9100(ah))
1573                 udelay(50);
1574
1575         return true;
1576 }
1577
1578 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1579 {
1580         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1581                   AR_RTC_FORCE_WAKE_ON_INT);
1582
1583         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1584         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1585
1586         if (!ath9k_hw_wait(ah,
1587                            AR_RTC_STATUS,
1588                            AR_RTC_STATUS_M,
1589                            AR_RTC_STATUS_ON)) {
1590                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1591                 return false;
1592         }
1593
1594         ath9k_hw_read_revisions(ah);
1595
1596         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1597 }
1598
1599 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1600 {
1601         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1602                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1603
1604         switch (type) {
1605         case ATH9K_RESET_POWER_ON:
1606                 return ath9k_hw_set_reset_power_on(ah);
1607                 break;
1608         case ATH9K_RESET_WARM:
1609         case ATH9K_RESET_COLD:
1610                 return ath9k_hw_set_reset(ah, type);
1611                 break;
1612         default:
1613                 return false;
1614         }
1615 }
1616
1617 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1618                               enum ath9k_ht_macmode macmode)
1619 {
1620         u32 phymode;
1621         u32 enableDacFifo = 0;
1622         struct ath_hal_5416 *ahp = AH5416(ah);
1623
1624         if (AR_SREV_9285_10_OR_LATER(ah))
1625                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1626                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1627
1628         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1629                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1630
1631         if (IS_CHAN_HT40(chan)) {
1632                 phymode |= AR_PHY_FC_DYN2040_EN;
1633
1634                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1635                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1636                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1637
1638                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1639                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1640         }
1641         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1642
1643         ath9k_hw_set11nmac2040(ah, macmode);
1644
1645         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1646         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1647 }
1648
1649 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1650                                 struct ath9k_channel *chan)
1651 {
1652         struct ath_hal_5416 *ahp = AH5416(ah);
1653
1654         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1655                 return false;
1656
1657         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1658                 return false;
1659
1660         ahp->ah_chipFullSleep = false;
1661
1662         ath9k_hw_init_pll(ah, chan);
1663
1664         ath9k_hw_set_rfmode(ah, chan);
1665
1666         return true;
1667 }
1668
1669 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1670                                                  struct ath9k_channel *chan)
1671 {
1672         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1673                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1674                         "invalid channel %u/0x%x; not marked as "
1675                         "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1676                 return NULL;
1677         }
1678
1679         if (!IS_CHAN_OFDM(chan) &&
1680             !IS_CHAN_B(chan) &&
1681             !IS_CHAN_HT20(chan) &&
1682             !IS_CHAN_HT40(chan)) {
1683                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1684                         "invalid channel %u/0x%x; not marked as "
1685                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1686                         chan->channel, chan->channelFlags);
1687                 return NULL;
1688         }
1689
1690         return ath9k_regd_check_channel(ah, chan);
1691 }
1692
1693 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1694                                     struct ath9k_channel *chan,
1695                                     enum ath9k_ht_macmode macmode)
1696 {
1697         u32 synthDelay, qnum;
1698
1699         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1700                 if (ath9k_hw_numtxpending(ah, qnum)) {
1701                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1702                                 "Transmit frames pending on queue %d\n", qnum);
1703                         return false;
1704                 }
1705         }
1706
1707         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1708         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1709                            AR_PHY_RFBUS_GRANT_EN)) {
1710                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1711                         "Could not kill baseband RX\n");
1712                 return false;
1713         }
1714
1715         ath9k_hw_set_regs(ah, chan, macmode);
1716
1717         if (AR_SREV_9280_10_OR_LATER(ah)) {
1718                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1719                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1720                                 "failed to set channel\n");
1721                         return false;
1722                 }
1723         } else {
1724                 if (!(ath9k_hw_set_channel(ah, chan))) {
1725                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1726                                 "failed to set channel\n");
1727                         return false;
1728                 }
1729         }
1730
1731         if (ath9k_hw_set_txpower(ah, chan,
1732                                  ath9k_regd_get_ctl(ah, chan),
1733                                  ath9k_regd_get_antenna_allowed(ah, chan),
1734                                  chan->maxRegTxPower * 2,
1735                                  min((u32) MAX_RATE_POWER,
1736                                      (u32) ah->ah_powerLimit)) != 0) {
1737                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1738                         "error init'ing transmit power\n");
1739                 return false;
1740         }
1741
1742         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1743         if (IS_CHAN_B(chan))
1744                 synthDelay = (4 * synthDelay) / 22;
1745         else
1746                 synthDelay /= 10;
1747
1748         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1749
1750         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1751
1752         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1753                 ath9k_hw_set_delta_slope(ah, chan);
1754
1755         if (AR_SREV_9280_10_OR_LATER(ah))
1756                 ath9k_hw_9280_spur_mitigate(ah, chan);
1757         else
1758                 ath9k_hw_spur_mitigate(ah, chan);
1759
1760         if (!chan->oneTimeCalsDone)
1761                 chan->oneTimeCalsDone = true;
1762
1763         return true;
1764 }
1765
1766 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1767 {
1768         int bb_spur = AR_NO_SPUR;
1769         int freq;
1770         int bin, cur_bin;
1771         int bb_spur_off, spur_subchannel_sd;
1772         int spur_freq_sd;
1773         int spur_delta_phase;
1774         int denominator;
1775         int upper, lower, cur_vit_mask;
1776         int tmp, newVal;
1777         int i;
1778         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1779                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1780         };
1781         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1782                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1783         };
1784         int inc[4] = { 0, 100, 0, 0 };
1785         struct chan_centers centers;
1786
1787         int8_t mask_m[123];
1788         int8_t mask_p[123];
1789         int8_t mask_amt;
1790         int tmp_mask;
1791         int cur_bb_spur;
1792         bool is2GHz = IS_CHAN_2GHZ(chan);
1793
1794         memset(&mask_m, 0, sizeof(int8_t) * 123);
1795         memset(&mask_p, 0, sizeof(int8_t) * 123);
1796
1797         ath9k_hw_get_channel_centers(ah, chan, &centers);
1798         freq = centers.synth_center;
1799
1800         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1801         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1802                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1803
1804                 if (is2GHz)
1805                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1806                 else
1807                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1808
1809                 if (AR_NO_SPUR == cur_bb_spur)
1810                         break;
1811                 cur_bb_spur = cur_bb_spur - freq;
1812
1813                 if (IS_CHAN_HT40(chan)) {
1814                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1815                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1816                                 bb_spur = cur_bb_spur;
1817                                 break;
1818                         }
1819                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1820                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1821                         bb_spur = cur_bb_spur;
1822                         break;
1823                 }
1824         }
1825
1826         if (AR_NO_SPUR == bb_spur) {
1827                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1828                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1829                 return;
1830         } else {
1831                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1832                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1833         }
1834
1835         bin = bb_spur * 320;
1836
1837         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1838
1839         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1840                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1841                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1842                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1843         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1844
1845         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1846                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1847                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1848                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1849                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1850         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1851
1852         if (IS_CHAN_HT40(chan)) {
1853                 if (bb_spur < 0) {
1854                         spur_subchannel_sd = 1;
1855                         bb_spur_off = bb_spur + 10;
1856                 } else {
1857                         spur_subchannel_sd = 0;
1858                         bb_spur_off = bb_spur - 10;
1859                 }
1860         } else {
1861                 spur_subchannel_sd = 0;
1862                 bb_spur_off = bb_spur;
1863         }
1864
1865         if (IS_CHAN_HT40(chan))
1866                 spur_delta_phase =
1867                         ((bb_spur * 262144) /
1868                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1869         else
1870                 spur_delta_phase =
1871                         ((bb_spur * 524288) /
1872                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1873
1874         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1875         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1876
1877         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1878                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1879                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1880         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1881
1882         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1883         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1884
1885         cur_bin = -6000;
1886         upper = bin + 100;
1887         lower = bin - 100;
1888
1889         for (i = 0; i < 4; i++) {
1890                 int pilot_mask = 0;
1891                 int chan_mask = 0;
1892                 int bp = 0;
1893                 for (bp = 0; bp < 30; bp++) {
1894                         if ((cur_bin > lower) && (cur_bin < upper)) {
1895                                 pilot_mask = pilot_mask | 0x1 << bp;
1896                                 chan_mask = chan_mask | 0x1 << bp;
1897                         }
1898                         cur_bin += 100;
1899                 }
1900                 cur_bin += inc[i];
1901                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1902                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1903         }
1904
1905         cur_vit_mask = 6100;
1906         upper = bin + 120;
1907         lower = bin - 120;
1908
1909         for (i = 0; i < 123; i++) {
1910                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1911
1912                         /* workaround for gcc bug #37014 */
1913                         volatile int tmp = abs(cur_vit_mask - bin);
1914
1915                         if (tmp < 75)
1916                                 mask_amt = 1;
1917                         else
1918                                 mask_amt = 0;
1919                         if (cur_vit_mask < 0)
1920                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1921                         else
1922                                 mask_p[cur_vit_mask / 100] = mask_amt;
1923                 }
1924                 cur_vit_mask -= 100;
1925         }
1926
1927         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1928                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1929                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1930                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1931                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1932                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1933                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1934                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1935         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1936         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1937
1938         tmp_mask = (mask_m[31] << 28)
1939                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1940                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1941                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1942                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1943                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1944                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1945                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1946         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1947         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1948
1949         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1950                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1951                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1952                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1953                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1954                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1955                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1956                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1957         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1958         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1959
1960         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1961                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1962                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1963                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1964                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1965                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1966                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1967                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1968         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1969         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1970
1971         tmp_mask = (mask_p[15] << 28)
1972                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1973                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1974                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1975                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1976                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1977                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1978                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1979         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1980         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1981
1982         tmp_mask = (mask_p[30] << 28)
1983                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1984                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1985                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1986                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1987                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1988                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1989                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1990         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1991         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1992
1993         tmp_mask = (mask_p[45] << 28)
1994                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1995                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1996                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1997                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1998                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1999                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2000                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2001         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2002         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2003
2004         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2005                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2006                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2007                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2008                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2009                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2010                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2011                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2012         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2013         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2014 }
2015
2016 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
2017 {
2018         int bb_spur = AR_NO_SPUR;
2019         int bin, cur_bin;
2020         int spur_freq_sd;
2021         int spur_delta_phase;
2022         int denominator;
2023         int upper, lower, cur_vit_mask;
2024         int tmp, new;
2025         int i;
2026         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2027                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2028         };
2029         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2030                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2031         };
2032         int inc[4] = { 0, 100, 0, 0 };
2033
2034         int8_t mask_m[123];
2035         int8_t mask_p[123];
2036         int8_t mask_amt;
2037         int tmp_mask;
2038         int cur_bb_spur;
2039         bool is2GHz = IS_CHAN_2GHZ(chan);
2040
2041         memset(&mask_m, 0, sizeof(int8_t) * 123);
2042         memset(&mask_p, 0, sizeof(int8_t) * 123);
2043
2044         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2045                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2046                 if (AR_NO_SPUR == cur_bb_spur)
2047                         break;
2048                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2049                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2050                         bb_spur = cur_bb_spur;
2051                         break;
2052                 }
2053         }
2054
2055         if (AR_NO_SPUR == bb_spur)
2056                 return;
2057
2058         bin = bb_spur * 32;
2059
2060         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2061         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2062                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2063                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2064                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2065
2066         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2067
2068         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2069                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2070                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2071                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2072                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2073         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2074
2075         spur_delta_phase = ((bb_spur * 524288) / 100) &
2076                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2077
2078         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2079         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2080
2081         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2082                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2083                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2084         REG_WRITE(ah, AR_PHY_TIMING11, new);
2085
2086         cur_bin = -6000;
2087         upper = bin + 100;
2088         lower = bin - 100;
2089
2090         for (i = 0; i < 4; i++) {
2091                 int pilot_mask = 0;
2092                 int chan_mask = 0;
2093                 int bp = 0;
2094                 for (bp = 0; bp < 30; bp++) {
2095                         if ((cur_bin > lower) && (cur_bin < upper)) {
2096                                 pilot_mask = pilot_mask | 0x1 << bp;
2097                                 chan_mask = chan_mask | 0x1 << bp;
2098                         }
2099                         cur_bin += 100;
2100                 }
2101                 cur_bin += inc[i];
2102                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2103                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2104         }
2105
2106         cur_vit_mask = 6100;
2107         upper = bin + 120;
2108         lower = bin - 120;
2109
2110         for (i = 0; i < 123; i++) {
2111                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2112
2113                         /* workaround for gcc bug #37014 */
2114                         volatile int tmp = abs(cur_vit_mask - bin);
2115
2116                         if (tmp < 75)
2117                                 mask_amt = 1;
2118                         else
2119                                 mask_amt = 0;
2120                         if (cur_vit_mask < 0)
2121                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2122                         else
2123                                 mask_p[cur_vit_mask / 100] = mask_amt;
2124                 }
2125                 cur_vit_mask -= 100;
2126         }
2127
2128         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2129                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2130                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2131                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2132                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2133                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2134                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2135                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2136         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2137         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2138
2139         tmp_mask = (mask_m[31] << 28)
2140                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2141                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2142                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2143                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2144                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2145                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2146                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2147         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2148         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2149
2150         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2151                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2152                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2153                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2154                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2155                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2156                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2157                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2158         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2159         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2160
2161         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2162                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2163                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2164                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2165                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2166                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2167                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2168                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2169         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2170         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2171
2172         tmp_mask = (mask_p[15] << 28)
2173                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2174                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2175                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2176                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2177                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2178                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2179                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2180         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2181         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2182
2183         tmp_mask = (mask_p[30] << 28)
2184                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2185                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2186                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2187                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2188                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2189                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2190                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2191         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2192         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2193
2194         tmp_mask = (mask_p[45] << 28)
2195                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2196                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2197                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2198                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2199                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2200                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2201                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2202         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2203         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2204
2205         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2206                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2207                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2208                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2209                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2210                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2211                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2212                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2213         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2214         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2215 }
2216
2217 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2218                     enum ath9k_ht_macmode macmode,
2219                     u8 txchainmask, u8 rxchainmask,
2220                     enum ath9k_ht_extprotspacing extprotspacing,
2221                     bool bChannelChange, int *status)
2222 {
2223         u32 saveLedState;
2224         struct ath_hal_5416 *ahp = AH5416(ah);
2225         struct ath9k_channel *curchan = ah->ah_curchan;
2226         u32 saveDefAntenna;
2227         u32 macStaId1;
2228         int ecode;
2229         int i, rx_chainmask;
2230
2231         ahp->ah_extprotspacing = extprotspacing;
2232         ahp->ah_txchainmask = txchainmask;
2233         ahp->ah_rxchainmask = rxchainmask;
2234
2235         if (AR_SREV_9280(ah)) {
2236                 ahp->ah_txchainmask &= 0x3;
2237                 ahp->ah_rxchainmask &= 0x3;
2238         }
2239
2240         if (ath9k_hw_check_chan(ah, chan) == NULL) {
2241                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2242                         "invalid channel %u/0x%x; no mapping\n",
2243                         chan->channel, chan->channelFlags);
2244                 ecode = -EINVAL;
2245                 goto bad;
2246         }
2247
2248         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2249                 ecode = -EIO;
2250                 goto bad;
2251         }
2252
2253         if (curchan)
2254                 ath9k_hw_getnf(ah, curchan);
2255
2256         if (bChannelChange &&
2257             (ahp->ah_chipFullSleep != true) &&
2258             (ah->ah_curchan != NULL) &&
2259             (chan->channel != ah->ah_curchan->channel) &&
2260             ((chan->channelFlags & CHANNEL_ALL) ==
2261              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2262             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2263                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2264
2265                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2266                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2267                         ath9k_hw_start_nfcal(ah);
2268                         return true;
2269                 }
2270         }
2271
2272         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2273         if (saveDefAntenna == 0)
2274                 saveDefAntenna = 1;
2275
2276         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2277
2278         saveLedState = REG_READ(ah, AR_CFG_LED) &
2279                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2280                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2281
2282         ath9k_hw_mark_phy_inactive(ah);
2283
2284         if (!ath9k_hw_chip_reset(ah, chan)) {
2285                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2286                 ecode = -EINVAL;
2287                 goto bad;
2288         }
2289
2290         if (AR_SREV_9280(ah)) {
2291                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2292                             AR_GPIO_JTAG_DISABLE);
2293
2294                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2295                         if (IS_CHAN_5GHZ(chan))
2296                                 ath9k_hw_set_gpio(ah, 9, 0);
2297                         else
2298                                 ath9k_hw_set_gpio(ah, 9, 1);
2299                 }
2300                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2301         }
2302
2303         ecode = ath9k_hw_process_ini(ah, chan, macmode);
2304         if (ecode != 0) {
2305                 ecode = -EINVAL;
2306                 goto bad;
2307         }
2308
2309         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2310                 ath9k_hw_set_delta_slope(ah, chan);
2311
2312         if (AR_SREV_9280_10_OR_LATER(ah))
2313                 ath9k_hw_9280_spur_mitigate(ah, chan);
2314         else
2315                 ath9k_hw_spur_mitigate(ah, chan);
2316
2317         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2318                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2319                         "error setting board options\n");
2320                 ecode = -EIO;
2321                 goto bad;
2322         }
2323
2324         ath9k_hw_decrease_chain_power(ah, chan);
2325
2326         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2327         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2328                   | macStaId1
2329                   | AR_STA_ID1_RTS_USE_DEF
2330                   | (ah->ah_config.
2331                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2332                   | ahp->ah_staId1Defaults);
2333         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2334
2335         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2336         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2337
2338         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2339
2340         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2341         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2342                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2343
2344         REG_WRITE(ah, AR_ISR, ~0);
2345
2346         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2347
2348         if (AR_SREV_9280_10_OR_LATER(ah)) {
2349                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2350                         ecode = -EIO;
2351                         goto bad;
2352                 }
2353         } else {
2354                 if (!(ath9k_hw_set_channel(ah, chan))) {
2355                         ecode = -EIO;
2356                         goto bad;
2357                 }
2358         }
2359
2360         for (i = 0; i < AR_NUM_DCU; i++)
2361                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2362
2363         ahp->ah_intrTxqs = 0;
2364         for (i = 0; i < ah->ah_caps.total_queues; i++)
2365                 ath9k_hw_resettxqueue(ah, i);
2366
2367         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2368         ath9k_hw_init_qos(ah);
2369
2370 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2371         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2372                 ath9k_enable_rfkill(ah);
2373 #endif
2374         ath9k_hw_init_user_settings(ah);
2375
2376         REG_WRITE(ah, AR_STA_ID1,
2377                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2378
2379         ath9k_hw_set_dma(ah);
2380
2381         REG_WRITE(ah, AR_OBS, 8);
2382
2383         if (ahp->ah_intrMitigation) {
2384
2385                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2386                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2387         }
2388
2389         ath9k_hw_init_bb(ah, chan);
2390
2391         if (!ath9k_hw_init_cal(ah, chan)){
2392                 ecode = -EIO;;
2393                 goto bad;
2394         }
2395
2396         rx_chainmask = ahp->ah_rxchainmask;
2397         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2398                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2399                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2400         }
2401
2402         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2403
2404         if (AR_SREV_9100(ah)) {
2405                 u32 mask;
2406                 mask = REG_READ(ah, AR_CFG);
2407                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2408                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2409                                 "CFG Byte Swap Set 0x%x\n", mask);
2410                 } else {
2411                         mask =
2412                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2413                         REG_WRITE(ah, AR_CFG, mask);
2414                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2415                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2416                 }
2417         } else {
2418 #ifdef __BIG_ENDIAN
2419                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2420 #endif
2421         }
2422
2423         return true;
2424 bad:
2425         if (status)
2426                 *status = ecode;
2427         return false;
2428 }
2429
2430 /************************/
2431 /* Key Cache Management */
2432 /************************/
2433
2434 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2435 {
2436         u32 keyType;
2437
2438         if (entry >= ah->ah_caps.keycache_size) {
2439                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2440                         "entry %u out of range\n", entry);
2441                 return false;
2442         }
2443
2444         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2445
2446         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2447         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2448         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2449         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2450         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2451         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2452         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2453         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2454
2455         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2456                 u16 micentry = entry + 64;
2457
2458                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2459                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2460                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2461                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2462
2463         }
2464
2465         if (ah->ah_curchan == NULL)
2466                 return true;
2467
2468         return true;
2469 }
2470
2471 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2472 {
2473         u32 macHi, macLo;
2474
2475         if (entry >= ah->ah_caps.keycache_size) {
2476                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2477                         "entry %u out of range\n", entry);
2478                 return false;
2479         }
2480
2481         if (mac != NULL) {
2482                 macHi = (mac[5] << 8) | mac[4];
2483                 macLo = (mac[3] << 24) |
2484                         (mac[2] << 16) |
2485                         (mac[1] << 8) |
2486                         mac[0];
2487                 macLo >>= 1;
2488                 macLo |= (macHi & 1) << 31;
2489                 macHi >>= 1;
2490         } else {
2491                 macLo = macHi = 0;
2492         }
2493         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2494         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2495
2496         return true;
2497 }
2498
2499 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2500                                  const struct ath9k_keyval *k,
2501                                  const u8 *mac, int xorKey)
2502 {
2503         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2504         u32 key0, key1, key2, key3, key4;
2505         u32 keyType;
2506         u32 xorMask = xorKey ?
2507                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2508                  | ATH9K_KEY_XOR) : 0;
2509         struct ath_hal_5416 *ahp = AH5416(ah);
2510
2511         if (entry >= pCap->keycache_size) {
2512                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2513                         "entry %u out of range\n", entry);
2514                 return false;
2515         }
2516
2517         switch (k->kv_type) {
2518         case ATH9K_CIPHER_AES_OCB:
2519                 keyType = AR_KEYTABLE_TYPE_AES;
2520                 break;
2521         case ATH9K_CIPHER_AES_CCM:
2522                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2523                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2524                                 "AES-CCM not supported by mac rev 0x%x\n",
2525                                 ah->ah_macRev);
2526                         return false;
2527                 }
2528                 keyType = AR_KEYTABLE_TYPE_CCM;
2529                 break;
2530         case ATH9K_CIPHER_TKIP:
2531                 keyType = AR_KEYTABLE_TYPE_TKIP;
2532                 if (ATH9K_IS_MIC_ENABLED(ah)
2533                     && entry + 64 >= pCap->keycache_size) {
2534                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2535                                 "entry %u inappropriate for TKIP\n", entry);
2536                         return false;
2537                 }
2538                 break;
2539         case ATH9K_CIPHER_WEP:
2540                 if (k->kv_len < LEN_WEP40) {
2541                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2542                                 "WEP key length %u too small\n", k->kv_len);
2543                         return false;
2544                 }
2545                 if (k->kv_len <= LEN_WEP40)
2546                         keyType = AR_KEYTABLE_TYPE_40;
2547                 else if (k->kv_len <= LEN_WEP104)
2548                         keyType = AR_KEYTABLE_TYPE_104;
2549                 else
2550                         keyType = AR_KEYTABLE_TYPE_128;
2551                 break;
2552         case ATH9K_CIPHER_CLR:
2553                 keyType = AR_KEYTABLE_TYPE_CLR;
2554                 break;
2555         default:
2556                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2557                         "cipher %u not supported\n", k->kv_type);
2558                 return false;
2559         }
2560
2561         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2562         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2563         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2564         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2565         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2566         if (k->kv_len <= LEN_WEP104)
2567                 key4 &= 0xff;
2568
2569         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2570                 u16 micentry = entry + 64;
2571
2572                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2573                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2574                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2575                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2576                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2577                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2578                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2579
2580                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2581                         u32 mic0, mic1, mic2, mic3, mic4;
2582
2583                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2584                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2585                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2586                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2587                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2588                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2589                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2590                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2591                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2592                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2593                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2594                                   AR_KEYTABLE_TYPE_CLR);
2595
2596                 } else {
2597                         u32 mic0, mic2;
2598
2599                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2600                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2601                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2602                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2603                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2604                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2605                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2606                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2607                                   AR_KEYTABLE_TYPE_CLR);
2608                 }
2609                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2610                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2611                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2612                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2613         } else {
2614                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2615                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2616                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2617                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2618                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2619                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2620
2621                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2622         }
2623
2624         if (ah->ah_curchan == NULL)
2625                 return true;
2626
2627         return true;
2628 }
2629
2630 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2631 {
2632         if (entry < ah->ah_caps.keycache_size) {
2633                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2634                 if (val & AR_KEYTABLE_VALID)
2635                         return true;
2636         }
2637         return false;
2638 }
2639
2640 /******************************/
2641 /* Power Management (Chipset) */
2642 /******************************/
2643
2644 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2645 {
2646         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2647         if (setChip) {
2648                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2649                             AR_RTC_FORCE_WAKE_EN);
2650                 if (!AR_SREV_9100(ah))
2651                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2652
2653                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2654                             AR_RTC_RESET_EN);
2655         }
2656 }
2657
2658 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2659 {
2660         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2661         if (setChip) {
2662                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2663
2664                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2665                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2666                                   AR_RTC_FORCE_WAKE_ON_INT);
2667                 } else {
2668                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2669                                     AR_RTC_FORCE_WAKE_EN);
2670                 }
2671         }
2672 }
2673
2674 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2675                                      int setChip)
2676 {
2677         u32 val;
2678         int i;
2679
2680         if (setChip) {
2681                 if ((REG_READ(ah, AR_RTC_STATUS) &
2682                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2683                         if (ath9k_hw_set_reset_reg(ah,
2684                                            ATH9K_RESET_POWER_ON) != true) {
2685                                 return false;
2686                         }
2687                 }
2688                 if (AR_SREV_9100(ah))
2689                         REG_SET_BIT(ah, AR_RTC_RESET,
2690                                     AR_RTC_RESET_EN);
2691
2692                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2693                             AR_RTC_FORCE_WAKE_EN);
2694                 udelay(50);
2695
2696                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2697                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2698                         if (val == AR_RTC_STATUS_ON)
2699                                 break;
2700                         udelay(50);
2701                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2702                                     AR_RTC_FORCE_WAKE_EN);
2703                 }
2704                 if (i == 0) {
2705                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2706                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2707                         return false;
2708                 }
2709         }
2710
2711         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2712
2713         return true;
2714 }
2715
2716 bool ath9k_hw_setpower(struct ath_hal *ah,
2717                        enum ath9k_power_mode mode)
2718 {
2719         struct ath_hal_5416 *ahp = AH5416(ah);
2720         static const char *modes[] = {
2721                 "AWAKE",
2722                 "FULL-SLEEP",
2723                 "NETWORK SLEEP",
2724                 "UNDEFINED"
2725         };
2726         int status = true, setChip = true;
2727
2728         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2729                 modes[ahp->ah_powerMode], modes[mode],
2730                 setChip ? "set chip " : "");
2731
2732         switch (mode) {
2733         case ATH9K_PM_AWAKE:
2734                 status = ath9k_hw_set_power_awake(ah, setChip);
2735                 break;
2736         case ATH9K_PM_FULL_SLEEP:
2737                 ath9k_set_power_sleep(ah, setChip);
2738                 ahp->ah_chipFullSleep = true;
2739                 break;
2740         case ATH9K_PM_NETWORK_SLEEP:
2741                 ath9k_set_power_network_sleep(ah, setChip);
2742                 break;
2743         default:
2744                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2745                         "Unknown power mode %u\n", mode);
2746                 return false;
2747         }
2748         ahp->ah_powerMode = mode;
2749
2750         return status;
2751 }
2752
2753 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2754 {
2755         struct ath_hal_5416 *ahp = AH5416(ah);
2756         u8 i;
2757
2758         if (ah->ah_isPciExpress != true)
2759                 return;
2760
2761         if (ah->ah_config.pcie_powersave_enable == 2)
2762                 return;
2763
2764         if (restore)
2765                 return;
2766
2767         if (AR_SREV_9280_20_OR_LATER(ah)) {
2768                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2769                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2770                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2771                 }
2772                 udelay(1000);
2773         } else if (AR_SREV_9280(ah) &&
2774                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2775                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2776                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2777
2778                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2779                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2780                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2781
2782                 if (ah->ah_config.pcie_clock_req)
2783                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2784                 else
2785                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2786
2787                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2788                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2789                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2790
2791                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2792
2793                 udelay(1000);
2794         } else {
2795                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2796                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2797                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2798                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2799                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2800                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2801                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2802                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2803                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2804                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2805         }
2806
2807         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2808
2809         if (ah->ah_config.pcie_waen) {
2810                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2811         } else {
2812                 if (AR_SREV_9285(ah))
2813                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2814                 else if (AR_SREV_9280(ah))
2815                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2816                 else
2817                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2818         }
2819
2820 }
2821
2822 /**********************/
2823 /* Interrupt Handling */
2824 /**********************/
2825
2826 bool ath9k_hw_intrpend(struct ath_hal *ah)
2827 {
2828         u32 host_isr;
2829
2830         if (AR_SREV_9100(ah))
2831                 return true;
2832
2833         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2834         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2835                 return true;
2836
2837         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2838         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2839             && (host_isr != AR_INTR_SPURIOUS))
2840                 return true;
2841
2842         return false;
2843 }
2844
2845 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2846 {
2847         u32 isr = 0;
2848         u32 mask2 = 0;
2849         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2850         u32 sync_cause = 0;
2851         bool fatal_int = false;
2852         struct ath_hal_5416 *ahp = AH5416(ah);
2853
2854         if (!AR_SREV_9100(ah)) {
2855                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2856                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2857                             == AR_RTC_STATUS_ON) {
2858                                 isr = REG_READ(ah, AR_ISR);
2859                         }
2860                 }
2861
2862                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2863                         AR_INTR_SYNC_DEFAULT;
2864
2865                 *masked = 0;
2866
2867                 if (!isr && !sync_cause)
2868                         return false;
2869         } else {
2870                 *masked = 0;
2871                 isr = REG_READ(ah, AR_ISR);
2872         }
2873
2874         if (isr) {
2875                 if (isr & AR_ISR_BCNMISC) {
2876                         u32 isr2;
2877                         isr2 = REG_READ(ah, AR_ISR_S2);
2878                         if (isr2 & AR_ISR_S2_TIM)
2879                                 mask2 |= ATH9K_INT_TIM;
2880                         if (isr2 & AR_ISR_S2_DTIM)
2881                                 mask2 |= ATH9K_INT_DTIM;
2882                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2883                                 mask2 |= ATH9K_INT_DTIMSYNC;
2884                         if (isr2 & (AR_ISR_S2_CABEND))
2885                                 mask2 |= ATH9K_INT_CABEND;
2886                         if (isr2 & AR_ISR_S2_GTT)
2887                                 mask2 |= ATH9K_INT_GTT;
2888                         if (isr2 & AR_ISR_S2_CST)
2889                                 mask2 |= ATH9K_INT_CST;
2890                 }
2891
2892                 isr = REG_READ(ah, AR_ISR_RAC);
2893                 if (isr == 0xffffffff) {
2894                         *masked = 0;
2895                         return false;
2896                 }
2897
2898                 *masked = isr & ATH9K_INT_COMMON;
2899
2900                 if (ahp->ah_intrMitigation) {
2901                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2902                                 *masked |= ATH9K_INT_RX;
2903                 }
2904
2905                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2906                         *masked |= ATH9K_INT_RX;
2907                 if (isr &
2908                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2909                      AR_ISR_TXEOL)) {
2910                         u32 s0_s, s1_s;
2911
2912                         *masked |= ATH9K_INT_TX;
2913
2914                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2915                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2916                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2917
2918                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2919                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2920                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2921                 }
2922
2923                 if (isr & AR_ISR_RXORN) {
2924                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2925                                 "receive FIFO overrun interrupt\n");
2926                 }
2927
2928                 if (!AR_SREV_9100(ah)) {
2929                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2930                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2931                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2932                                         *masked |= ATH9K_INT_TIM_TIMER;
2933                         }
2934                 }
2935
2936                 *masked |= mask2;
2937         }
2938
2939         if (AR_SREV_9100(ah))
2940                 return true;
2941
2942         if (sync_cause) {
2943                 fatal_int =
2944                         (sync_cause &
2945                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2946                         ? true : false;
2947
2948                 if (fatal_int) {
2949                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2950                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2951                                         "received PCI FATAL interrupt\n");
2952                         }
2953                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2954                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2955                                         "received PCI PERR interrupt\n");
2956                         }
2957                 }
2958                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2959                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2960                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2961                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2962                         REG_WRITE(ah, AR_RC, 0);
2963                         *masked |= ATH9K_INT_FATAL;
2964                 }
2965                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2966                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2967                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2968                 }
2969
2970                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2971                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2972         }
2973
2974         return true;
2975 }
2976
2977 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2978 {
2979         return AH5416(ah)->ah_maskReg;
2980 }
2981
2982 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2983 {
2984         struct ath_hal_5416 *ahp = AH5416(ah);
2985         u32 omask = ahp->ah_maskReg;
2986         u32 mask, mask2;
2987         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2988
2989         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2990
2991         if (omask & ATH9K_INT_GLOBAL) {
2992                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2993                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2994                 (void) REG_READ(ah, AR_IER);
2995                 if (!AR_SREV_9100(ah)) {
2996                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2997                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2998
2999                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3000                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3001                 }
3002         }
3003
3004         mask = ints & ATH9K_INT_COMMON;
3005         mask2 = 0;
3006
3007         if (ints & ATH9K_INT_TX) {
3008                 if (ahp->ah_txOkInterruptMask)
3009                         mask |= AR_IMR_TXOK;
3010                 if (ahp->ah_txDescInterruptMask)
3011                         mask |= AR_IMR_TXDESC;
3012                 if (ahp->ah_txErrInterruptMask)
3013                         mask |= AR_IMR_TXERR;
3014                 if (ahp->ah_txEolInterruptMask)
3015                         mask |= AR_IMR_TXEOL;
3016         }
3017         if (ints & ATH9K_INT_RX) {
3018                 mask |= AR_IMR_RXERR;
3019                 if (ahp->ah_intrMitigation)
3020                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3021                 else
3022                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3023                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3024                         mask |= AR_IMR_GENTMR;
3025         }
3026
3027         if (ints & (ATH9K_INT_BMISC)) {
3028                 mask |= AR_IMR_BCNMISC;
3029                 if (ints & ATH9K_INT_TIM)
3030                         mask2 |= AR_IMR_S2_TIM;
3031                 if (ints & ATH9K_INT_DTIM)
3032                         mask2 |= AR_IMR_S2_DTIM;
3033                 if (ints & ATH9K_INT_DTIMSYNC)
3034                         mask2 |= AR_IMR_S2_DTIMSYNC;
3035                 if (ints & ATH9K_INT_CABEND)
3036                         mask2 |= (AR_IMR_S2_CABEND);
3037         }
3038
3039         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3040                 mask |= AR_IMR_BCNMISC;
3041                 if (ints & ATH9K_INT_GTT)
3042                         mask2 |= AR_IMR_S2_GTT;
3043                 if (ints & ATH9K_INT_CST)
3044                         mask2 |= AR_IMR_S2_CST;
3045         }
3046
3047         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3048         REG_WRITE(ah, AR_IMR, mask);
3049         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3050                                            AR_IMR_S2_DTIM |
3051                                            AR_IMR_S2_DTIMSYNC |
3052                                            AR_IMR_S2_CABEND |
3053                                            AR_IMR_S2_CABTO |
3054                                            AR_IMR_S2_TSFOOR |
3055                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3056         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3057         ahp->ah_maskReg = ints;
3058
3059         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3060                 if (ints & ATH9K_INT_TIM_TIMER)
3061                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3062                 else
3063                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3064         }
3065
3066         if (ints & ATH9K_INT_GLOBAL) {
3067                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3068                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3069                 if (!AR_SREV_9100(ah)) {
3070                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3071                                   AR_INTR_MAC_IRQ);
3072                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3073
3074
3075                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3076                                   AR_INTR_SYNC_DEFAULT);
3077                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3078                                   AR_INTR_SYNC_DEFAULT);
3079                 }
3080                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3081                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3082         }
3083
3084         return omask;
3085 }
3086
3087 /*******************/
3088 /* Beacon Handling */
3089 /*******************/
3090
3091 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3092 {
3093         struct ath_hal_5416 *ahp = AH5416(ah);
3094         int flags = 0;
3095
3096         ahp->ah_beaconInterval = beacon_period;
3097
3098         switch (ah->ah_opmode) {
3099         case NL80211_IFTYPE_STATION:
3100         case NL80211_IFTYPE_MONITOR:
3101                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3102                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3103                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3104                 flags |= AR_TBTT_TIMER_EN;
3105                 break;
3106         case NL80211_IFTYPE_ADHOC:
3107                 REG_SET_BIT(ah, AR_TXCFG,
3108                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3109                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3110                           TU_TO_USEC(next_beacon +
3111                                      (ahp->ah_atimWindow ? ahp->
3112                                       ah_atimWindow : 1)));
3113                 flags |= AR_NDP_TIMER_EN;
3114         case NL80211_IFTYPE_AP:
3115                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3116                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3117                           TU_TO_USEC(next_beacon -
3118                                      ah->ah_config.
3119                                      dma_beacon_response_time));
3120                 REG_WRITE(ah, AR_NEXT_SWBA,
3121                           TU_TO_USEC(next_beacon -
3122                                      ah->ah_config.
3123                                      sw_beacon_response_time));
3124                 flags |=
3125                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3126                 break;
3127         default:
3128                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3129                         "%s: unsupported opmode: %d\n",
3130                         __func__, ah->ah_opmode);
3131                 return;
3132                 break;
3133         }
3134
3135         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3136         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3137         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3138         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3139
3140         beacon_period &= ~ATH9K_BEACON_ENA;
3141         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3142                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3143                 ath9k_hw_reset_tsf(ah);
3144         }
3145
3146         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3147 }
3148
3149 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3150                                     const struct ath9k_beacon_state *bs)
3151 {
3152         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3153         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3154
3155         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3156
3157         REG_WRITE(ah, AR_BEACON_PERIOD,
3158                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3159         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3160                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3161
3162         REG_RMW_FIELD(ah, AR_RSSI_THR,
3163                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3164
3165         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3166
3167         if (bs->bs_sleepduration > beaconintval)
3168                 beaconintval = bs->bs_sleepduration;
3169
3170         dtimperiod = bs->bs_dtimperiod;
3171         if (bs->bs_sleepduration > dtimperiod)
3172                 dtimperiod = bs->bs_sleepduration;
3173
3174         if (beaconintval == dtimperiod)
3175                 nextTbtt = bs->bs_nextdtim;
3176         else
3177                 nextTbtt = bs->bs_nexttbtt;
3178
3179         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3180         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3181         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3182         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3183
3184         REG_WRITE(ah, AR_NEXT_DTIM,
3185                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3186         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3187
3188         REG_WRITE(ah, AR_SLEEP1,
3189                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3190                   | AR_SLEEP1_ASSUME_DTIM);
3191
3192         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3193                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3194         else
3195                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3196
3197         REG_WRITE(ah, AR_SLEEP2,
3198                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3199
3200         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3201         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3202
3203         REG_SET_BIT(ah, AR_TIMER_MODE,
3204                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3205                     AR_DTIM_TIMER_EN);
3206
3207 }
3208
3209 /*******************/
3210 /* HW Capabilities */
3211 /*******************/
3212
3213 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3214 {
3215         struct ath_hal_5416 *ahp = AH5416(ah);
3216         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3217         u16 capField = 0, eeval;
3218
3219         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3220
3221         ah->ah_currentRD = eeval;
3222
3223         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3224         ah->ah_currentRDExt = eeval;
3225
3226         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3227
3228         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3229             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3230                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3231                         ah->ah_currentRD += 5;
3232                 else if (ah->ah_currentRD == 0x41)
3233                         ah->ah_currentRD = 0x43;
3234                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3235                         "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3236         }
3237
3238         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3239         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3240
3241         if (eeval & AR5416_OPFLAGS_11A) {
3242                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3243                 if (ah->ah_config.ht_enable) {
3244                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3245                                 set_bit(ATH9K_MODE_11NA_HT20,
3246                                         pCap->wireless_modes);
3247                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3248                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3249                                         pCap->wireless_modes);
3250                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3251                                         pCap->wireless_modes);
3252                         }
3253                 }
3254         }
3255
3256         if (eeval & AR5416_OPFLAGS_11G) {
3257                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3258                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3259                 if (ah->ah_config.ht_enable) {
3260                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3261                                 set_bit(ATH9K_MODE_11NG_HT20,
3262                                         pCap->wireless_modes);
3263                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3264                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3265                                         pCap->wireless_modes);
3266                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3267                                         pCap->wireless_modes);
3268                         }
3269                 }
3270         }
3271
3272         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3273         if ((ah->ah_isPciExpress)
3274             || (eeval & AR5416_OPFLAGS_11A)) {
3275                 pCap->rx_chainmask =
3276                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3277         } else {
3278                 pCap->rx_chainmask =
3279                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3280         }
3281
3282         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3283                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3284
3285         pCap->low_2ghz_chan = 2312;
3286         pCap->high_2ghz_chan = 2732;
3287
3288         pCap->low_5ghz_chan = 4920;
3289         pCap->high_5ghz_chan = 6100;
3290
3291         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3292         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3293         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3294
3295         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3296         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3297         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3298
3299         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3300
3301         if (ah->ah_config.ht_enable)
3302                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3303         else
3304                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3305
3306         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3307         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3308         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3309         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3310
3311         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3312                 pCap->total_queues =
3313                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3314         else
3315                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3316
3317         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3318                 pCap->keycache_size =
3319                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3320         else
3321                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3322
3323         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3324         pCap->num_mr_retries = 4;
3325         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3326
3327         if (AR_SREV_9280_10_OR_LATER(ah))
3328                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3329         else
3330                 pCap->num_gpio_pins = AR_NUM_GPIO;
3331
3332         if (AR_SREV_9280_10_OR_LATER(ah)) {
3333                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3334                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3335         } else {
3336                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3337                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3338         }
3339
3340         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3341                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3342                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3343         } else {
3344                 pCap->rts_aggr_limit = (8 * 1024);
3345         }
3346
3347         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3348
3349 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3350         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3351         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3352                 ah->ah_rfkill_gpio =
3353                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3354                 ah->ah_rfkill_polarity =
3355                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3356
3357                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3358         }
3359 #endif
3360
3361         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3362             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3363             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3364             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3365             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3366                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3367         else
3368                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3369
3370         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3371                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3372         else
3373                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3374
3375         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3376                 pCap->reg_cap =
3377                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3378                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3379                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3380                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3381         } else {
3382                 pCap->reg_cap =
3383                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3384                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3385         }
3386
3387         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3388
3389         pCap->num_antcfg_5ghz =
3390                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3391         pCap->num_antcfg_2ghz =
3392                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3393
3394         return true;
3395 }
3396
3397 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3398                             u32 capability, u32 *result)
3399 {
3400         struct ath_hal_5416 *ahp = AH5416(ah);
3401         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3402
3403         switch (type) {
3404         case ATH9K_CAP_CIPHER:
3405                 switch (capability) {
3406                 case ATH9K_CIPHER_AES_CCM:
3407                 case ATH9K_CIPHER_AES_OCB:
3408                 case ATH9K_CIPHER_TKIP:
3409                 case ATH9K_CIPHER_WEP:
3410                 case ATH9K_CIPHER_MIC:
3411                 case ATH9K_CIPHER_CLR:
3412                         return true;
3413                 default:
3414                         return false;
3415                 }
3416         case ATH9K_CAP_TKIP_MIC:
3417                 switch (capability) {
3418                 case 0:
3419                         return true;
3420                 case 1:
3421                         return (ahp->ah_staId1Defaults &
3422                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3423                         false;
3424                 }
3425         case ATH9K_CAP_TKIP_SPLIT:
3426                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3427                         false : true;
3428         case ATH9K_CAP_WME_TKIPMIC:
3429                 return 0;
3430         case ATH9K_CAP_PHYCOUNTERS:
3431                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3432         case ATH9K_CAP_DIVERSITY:
3433                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3434                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3435                         true : false;
3436         case ATH9K_CAP_PHYDIAG:
3437                 return true;
3438         case ATH9K_CAP_MCAST_KEYSRCH:
3439                 switch (capability) {
3440                 case 0:
3441                         return true;
3442                 case 1:
3443                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3444                                 return false;
3445                         } else {
3446                                 return (ahp->ah_staId1Defaults &
3447                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3448                                         false;
3449                         }
3450                 }
3451                 return false;
3452         case ATH9K_CAP_TSF_ADJUST:
3453                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3454                         true : false;
3455         case ATH9K_CAP_RFSILENT:
3456                 if (capability == 3)
3457                         return false;
3458         case ATH9K_CAP_ANT_CFG_2GHZ:
3459                 *result = pCap->num_antcfg_2ghz;
3460                 return true;
3461         case ATH9K_CAP_ANT_CFG_5GHZ:
3462                 *result = pCap->num_antcfg_5ghz;
3463                 return true;
3464         case ATH9K_CAP_TXPOW:
3465                 switch (capability) {
3466                 case 0:
3467                         return 0;
3468                 case 1:
3469                         *result = ah->ah_powerLimit;
3470                         return 0;
3471                 case 2:
3472                         *result = ah->ah_maxPowerLevel;
3473                         return 0;
3474                 case 3:
3475                         *result = ah->ah_tpScale;
3476                         return 0;
3477                 }
3478                 return false;
3479         default:
3480                 return false;
3481         }
3482 }
3483
3484 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3485                             u32 capability, u32 setting, int *status)
3486 {
3487         struct ath_hal_5416 *ahp = AH5416(ah);
3488         u32 v;
3489
3490         switch (type) {
3491         case ATH9K_CAP_TKIP_MIC:
3492                 if (setting)
3493                         ahp->ah_staId1Defaults |=
3494                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3495                 else
3496                         ahp->ah_staId1Defaults &=
3497                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3498                 return true;
3499         case ATH9K_CAP_DIVERSITY:
3500                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3501                 if (setting)
3502                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3503                 else
3504                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3505                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3506                 return true;
3507         case ATH9K_CAP_MCAST_KEYSRCH:
3508                 if (setting)
3509                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3510                 else
3511                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3512                 return true;
3513         case ATH9K_CAP_TSF_ADJUST:
3514                 if (setting)
3515                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3516                 else
3517                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3518                 return true;
3519         default:
3520                 return false;
3521         }
3522 }
3523
3524 /****************************/
3525 /* GPIO / RFKILL / Antennae */
3526 /****************************/
3527
3528 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3529                                          u32 gpio, u32 type)
3530 {
3531         int addr;
3532         u32 gpio_shift, tmp;
3533
3534         if (gpio > 11)
3535                 addr = AR_GPIO_OUTPUT_MUX3;
3536         else if (gpio > 5)
3537                 addr = AR_GPIO_OUTPUT_MUX2;
3538         else
3539                 addr = AR_GPIO_OUTPUT_MUX1;
3540
3541         gpio_shift = (gpio % 6) * 5;
3542
3543         if (AR_SREV_9280_20_OR_LATER(ah)
3544             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3545                 REG_RMW(ah, addr, (type << gpio_shift),
3546                         (0x1f << gpio_shift));
3547         } else {
3548                 tmp = REG_READ(ah, addr);
3549                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3550                 tmp &= ~(0x1f << gpio_shift);
3551                 tmp |= (type << gpio_shift);
3552                 REG_WRITE(ah, addr, tmp);
3553         }
3554 }
3555
3556 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3557 {
3558         u32 gpio_shift;
3559
3560         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3561
3562         gpio_shift = gpio << 1;
3563
3564         REG_RMW(ah,
3565                 AR_GPIO_OE_OUT,
3566                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3567                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3568 }
3569
3570 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3571 {
3572         if (gpio >= ah->ah_caps.num_gpio_pins)
3573                 return 0xffffffff;
3574
3575         if (AR_SREV_9280_10_OR_LATER(ah)) {
3576                 return (MS
3577                         (REG_READ(ah, AR_GPIO_IN_OUT),
3578                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3579         } else {
3580                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3581                         AR_GPIO_BIT(gpio)) != 0;
3582         }
3583 }
3584
3585 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3586                          u32 ah_signal_type)
3587 {
3588         u32 gpio_shift;
3589
3590         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3591
3592         gpio_shift = 2 * gpio;
3593
3594         REG_RMW(ah,
3595                 AR_GPIO_OE_OUT,
3596                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3597                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3598 }
3599
3600 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3601 {
3602         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3603                 AR_GPIO_BIT(gpio));
3604 }
3605
3606 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3607 void ath9k_enable_rfkill(struct ath_hal *ah)
3608 {
3609         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3610                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3611
3612         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3613                     AR_GPIO_INPUT_MUX2_RFSILENT);
3614
3615         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3616         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3617 }
3618 #endif
3619
3620 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3621 {
3622         struct ath9k_channel *chan = ah->ah_curchan;
3623         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3624         u16 ant_config;
3625         u32 halNumAntConfig;
3626
3627         halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3628                 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3629
3630         if (cfg < halNumAntConfig) {
3631                 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3632                                                      cfg, &ant_config)) {
3633                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3634                         return 0;
3635                 }
3636         }
3637
3638         return -EINVAL;
3639 }
3640
3641 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3642 {
3643         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3644 }
3645
3646 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3647 {
3648         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3649 }
3650
3651 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3652                                enum ath9k_ant_setting settings,
3653                                struct ath9k_channel *chan,
3654                                u8 *tx_chainmask,
3655                                u8 *rx_chainmask,
3656                                u8 *antenna_cfgd)
3657 {
3658         struct ath_hal_5416 *ahp = AH5416(ah);
3659         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3660
3661         if (AR_SREV_9280(ah)) {
3662                 if (!tx_chainmask_cfg) {
3663
3664                         tx_chainmask_cfg = *tx_chainmask;
3665                         rx_chainmask_cfg = *rx_chainmask;
3666                 }
3667
3668                 switch (settings) {
3669                 case ATH9K_ANT_FIXED_A:
3670                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3671                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3672                         *antenna_cfgd = true;
3673                         break;
3674                 case ATH9K_ANT_FIXED_B:
3675                         if (ah->ah_caps.tx_chainmask >
3676                             ATH9K_ANTENNA1_CHAINMASK) {
3677                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3678                         }
3679                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3680                         *antenna_cfgd = true;
3681                         break;
3682                 case ATH9K_ANT_VARIABLE:
3683                         *tx_chainmask = tx_chainmask_cfg;
3684                         *rx_chainmask = rx_chainmask_cfg;
3685                         *antenna_cfgd = true;
3686                         break;
3687                 default:
3688                         break;
3689                 }
3690         } else {
3691                 ahp->ah_diversityControl = settings;
3692         }
3693
3694         return true;
3695 }
3696
3697 /*********************/
3698 /* General Operation */
3699 /*********************/
3700
3701 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3702 {
3703         u32 bits = REG_READ(ah, AR_RX_FILTER);
3704         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3705
3706         if (phybits & AR_PHY_ERR_RADAR)
3707                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3708         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3709                 bits |= ATH9K_RX_FILTER_PHYERR;
3710
3711         return bits;
3712 }
3713
3714 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3715 {
3716         u32 phybits;
3717
3718         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3719         phybits = 0;
3720         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3721                 phybits |= AR_PHY_ERR_RADAR;
3722         if (bits & ATH9K_RX_FILTER_PHYERR)
3723                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3724         REG_WRITE(ah, AR_PHY_ERR, phybits);
3725
3726         if (phybits)
3727                 REG_WRITE(ah, AR_RXCFG,
3728                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3729         else
3730                 REG_WRITE(ah, AR_RXCFG,
3731                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3732 }
3733
3734 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3735 {
3736         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3737 }
3738
3739 bool ath9k_hw_disable(struct ath_hal *ah)
3740 {
3741         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3742                 return false;
3743
3744         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3745 }
3746
3747 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3748 {
3749         struct ath9k_channel *chan = ah->ah_curchan;
3750
3751         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3752
3753         if (ath9k_hw_set_txpower(ah, chan,
3754                                  ath9k_regd_get_ctl(ah, chan),
3755                                  ath9k_regd_get_antenna_allowed(ah, chan),
3756                                  chan->maxRegTxPower * 2,
3757                                  min((u32) MAX_RATE_POWER,
3758                                      (u32) ah->ah_powerLimit)) != 0)
3759                 return false;
3760
3761         return true;
3762 }
3763
3764 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3765 {
3766         struct ath_hal_5416 *ahp = AH5416(ah);
3767
3768         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3769 }
3770
3771 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3772 {
3773         struct ath_hal_5416 *ahp = AH5416(ah);
3774
3775         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3776
3777         return true;
3778 }
3779
3780 void ath9k_hw_setopmode(struct ath_hal *ah)
3781 {
3782         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3783 }
3784
3785 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3786 {
3787         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3788         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3789 }
3790
3791 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3792 {
3793         struct ath_hal_5416 *ahp = AH5416(ah);
3794
3795         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3796 }
3797
3798 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3799 {
3800         struct ath_hal_5416 *ahp = AH5416(ah);
3801
3802         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3803
3804         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3805         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3806
3807         return true;
3808 }
3809
3810 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3811 {
3812         struct ath_hal_5416 *ahp = AH5416(ah);
3813
3814         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3815         ahp->ah_assocId = assocId;
3816
3817         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3818         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3819                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3820 }
3821
3822 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3823 {
3824         u64 tsf;
3825
3826         tsf = REG_READ(ah, AR_TSF_U32);
3827         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3828
3829         return tsf;
3830 }
3831
3832 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3833 {
3834         int count;
3835
3836         count = 0;
3837         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3838                 count++;
3839                 if (count > 10) {
3840                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3841                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3842                         break;
3843                 }
3844                 udelay(10);
3845         }
3846         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3847 }
3848
3849 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3850 {
3851         struct ath_hal_5416 *ahp = AH5416(ah);
3852
3853         if (setting)
3854                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3855         else
3856                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3857
3858         return true;
3859 }
3860
3861 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3862 {
3863         struct ath_hal_5416 *ahp = AH5416(ah);
3864
3865         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3866                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3867                 ahp->ah_slottime = (u32) -1;
3868                 return false;
3869         } else {
3870                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3871                 ahp->ah_slottime = us;
3872                 return true;
3873         }
3874 }
3875
3876 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3877 {
3878         u32 macmode;
3879
3880         if (mode == ATH9K_HT_MACMODE_2040 &&
3881             !ah->ah_config.cwm_ignore_extcca)
3882                 macmode = AR_2040_JOINED_RX_CLEAR;
3883         else
3884                 macmode = 0;
3885
3886         REG_WRITE(ah, AR_2040_MODE, macmode);
3887 }