drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 #define ATH9K_CLOCK_RATE_CCK            22
  27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  29
  30 extern struct hal_percal_data iq_cal_multi_sample;
  31 extern struct hal_percal_data iq_cal_single_sample;
  32 extern struct hal_percal_data adc_gain_cal_multi_sample;
  33 extern struct hal_percal_data adc_gain_cal_single_sample;
  34 extern struct hal_percal_data adc_dc_cal_multi_sample;
  35 extern struct hal_percal_data adc_dc_cal_single_sample;
  36 extern struct hal_percal_data adc_init_dc_cal;
  37
  38 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  39 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  40                               enum ath9k_ht_macmode macmode);
  41 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  42                               struct ar5416_eeprom_def *pEepData,
  43                               u32 reg, u32 value);
  44 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  45 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  46
  47 /********************/
  48 /* Helper Functions */
  49 /********************/
  50
  51 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  52 {
  53         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  54         if (!ah->ah_curchan) /* should really check for CCK instead */
  55                 return clks / ATH9K_CLOCK_RATE_CCK;
  56         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  57                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  58         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  59 }
  60
  61 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  62 {
  63         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  64         if (conf_is_ht40(conf))
  65                 return ath9k_hw_mac_usec(ah, clks) / 2;
  66         else
  67                 return ath9k_hw_mac_usec(ah, clks);
  68 }
  69
  70 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  71 {
  72         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  73         if (!ah->ah_curchan) /* should really check for CCK instead */
  74                 return usecs *ATH9K_CLOCK_RATE_CCK;
  75         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  76                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  77         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  78 }
  79
  80 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  81 {
  82         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  83         if (conf_is_ht40(conf))
  84                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  85         else
  86                 return ath9k_hw_mac_clks(ah, usecs);
  87 }
  88
  89 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  90 {
  91         int i;
  92
  93         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
  94                 if ((REG_READ(ah, reg) & mask) == val)
  95                         return true;
  96
  97                 udelay(AH_TIME_QUANTUM);
  98         }
  99
 100         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 101                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 102                 reg, REG_READ(ah, reg), mask, val);
 103
 104         return false;
 105 }
 106
 107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 108 {
 109         u32 retval;
 110         int i;
 111
 112         for (i = 0, retval = 0; i < n; i++) {
 113                 retval = (retval << 1) | (val & 1);
 114                 val >>= 1;
 115         }
 116         return retval;
 117 }
 118
 119 bool ath9k_get_channel_edges(struct ath_hal *ah,
 120                              u16 flags, u16 *low,
 121                              u16 *high)
 122 {
 123         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 124
 125         if (flags & CHANNEL_5GHZ) {
 126                 *low = pCap->low_5ghz_chan;
 127                 *high = pCap->high_5ghz_chan;
 128                 return true;
 129         }
 130         if ((flags & CHANNEL_2GHZ)) {
 131                 *low = pCap->low_2ghz_chan;
 132                 *high = pCap->high_2ghz_chan;
 133                 return true;
 134         }
 135         return false;
 136 }
 137
 138 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 139                            struct ath_rate_table *rates,
 140                            u32 frameLen, u16 rateix,
 141                            bool shortPreamble)
 142 {
 143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 144         u32 kbps;
 145
 146         kbps = rates->info[rateix].ratekbps;
 147
 148         if (kbps == 0)
 149                 return 0;
 150
 151         switch (rates->info[rateix].phy) {
 152         case WLAN_RC_PHY_CCK:
 153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 154                 if (shortPreamble && rates->info[rateix].short_preamble)
 155                         phyTime >>= 1;
 156                 numBits = frameLen << 3;
 157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 158                 break;
 159         case WLAN_RC_PHY_OFDM:
 160                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME_QUARTER
 165                                 + OFDM_PREAMBLE_TIME_QUARTER
 166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 167                 } else if (ah->ah_curchan &&
 168                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_HALF +
 173                                 OFDM_PREAMBLE_TIME_HALF
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 175                 } else {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 180                                 + (numSymbols * OFDM_SYMBOL_TIME);
 181                 }
 182                 break;
 183         default:
 184                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 185                         "Unknown phy %u (rate ix %u)\n",
 186                         rates->info[rateix].phy, rateix);
 187                 txTime = 0;
 188                 break;
 189         }
 190
 191         return txTime;
 192 }
 193
 194 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 195 {
 196         if (flags & CHANNEL_2GHZ) {
 197                 if (freq == 2484)
 198                         return 14;
 199                 if (freq < 2484)
 200                         return (freq - 2407) / 5;
 201                 else
 202                         return 15 + ((freq - 2512) / 20);
 203         } else if (flags & CHANNEL_5GHZ) {
 204                 if (ath9k_regd_is_public_safety_sku(ah) &&
 205                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 206                         return ((freq * 10) +
 207                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
 208                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
 209                         return (freq - 4000) / 5;
 210                 } else {
 211                         return (freq - 5000) / 5;
 212                 }
 213         } else {
 214                 if (freq == 2484)
 215                         return 14;
 216                 if (freq < 2484)
 217                         return (freq - 2407) / 5;
 218                 if (freq < 5000) {
 219                         if (ath9k_regd_is_public_safety_sku(ah)
 220                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 221                                 return ((freq * 10) +
 222                                         (((freq % 5) ==
 223                                           2) ? 5 : 0) - 49400) / 5;
 224                         } else if (freq > 4900) {
 225                                 return (freq - 4000) / 5;
 226                         } else {
 227                                 return 15 + ((freq - 2512) / 20);
 228                         }
 229                 }
 230                 return (freq - 5000) / 5;
 231         }
 232 }
 233
 234 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 235                                   struct ath9k_channel *chan,
 236                                   struct chan_centers *centers)
 237 {
 238         int8_t extoff;
 239         struct ath_hal_5416 *ahp = AH5416(ah);
 240
 241         if (!IS_CHAN_HT40(chan)) {
 242                 centers->ctl_center = centers->ext_center =
 243                         centers->synth_center = chan->channel;
 244                 return;
 245         }
 246
 247         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 248             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 249                 centers->synth_center =
 250                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 251                 extoff = 1;
 252         } else {
 253                 centers->synth_center =
 254                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 255                 extoff = -1;
 256         }
 257
 258         centers->ctl_center =
 259                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 260         centers->ext_center =
 261                 centers->synth_center + (extoff *
 262                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 263                           HT40_CHANNEL_CENTER_SHIFT : 15));
 264
 265 }
 266
 267 /******************/
 268 /* Chip Revisions */
 269 /******************/
 270
 271 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 272 {
 273         u32 val;
 274
 275         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 276
 277         if (val == 0xFF) {
 278                 val = REG_READ(ah, AR_SREV);
 279                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 280                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 281                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 282         } else {
 283                 if (!AR_SREV_9100(ah))
 284                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 285
 286                 ah->ah_macRev = val & AR_SREV_REVISION;
 287
 288                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 289                         ah->ah_isPciExpress = true;
 290         }
 291 }
 292
 293 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 294 {
 295         u32 val;
 296         int i;
 297
 298         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 299
 300         for (i = 0; i < 8; i++)
 301                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 302         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 303         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 304
 305         return ath9k_hw_reverse_bits(val, 8);
 306 }
 307
 308 /************************************/
 309 /* HW Attach, Detach, Init Routines */
 310 /************************************/
 311
 312 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 313 {
 314         if (!AR_SREV_9100(ah))
 315                 return;
 316
 317         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 318         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 319         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 320         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 321         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 322         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 323         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 324         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 325         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 326
 327         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 328 }
 329
 330 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 331 {
 332         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 333         u32 regHold[2];
 334         u32 patternData[4] = { 0x55555555,
 335                                0xaaaaaaaa,
 336                                0x66666666,
 337                                0x99999999 };
 338         int i, j;
 339
 340         for (i = 0; i < 2; i++) {
 341                 u32 addr = regAddr[i];
 342                 u32 wrData, rdData;
 343
 344                 regHold[i] = REG_READ(ah, addr);
 345                 for (j = 0; j < 0x100; j++) {
 346                         wrData = (j << 16) | j;
 347                         REG_WRITE(ah, addr, wrData);
 348                         rdData = REG_READ(ah, addr);
 349                         if (rdData != wrData) {
 350                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 351                                         "address test failed "
 352                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 353                                         addr, wrData, rdData);
 354                                 return false;
 355                         }
 356                 }
 357                 for (j = 0; j < 4; j++) {
 358                         wrData = patternData[j];
 359                         REG_WRITE(ah, addr, wrData);
 360                         rdData = REG_READ(ah, addr);
 361                         if (wrData != rdData) {
 362                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 363                                         "address test failed "
 364                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 365                                         addr, wrData, rdData);
 366                                 return false;
 367                         }
 368                 }
 369                 REG_WRITE(ah, regAddr[i], regHold[i]);
 370         }
 371         udelay(100);
 372         return true;
 373 }
 374
 375 static const char *ath9k_hw_devname(u16 devid)
 376 {
 377         switch (devid) {
 378         case AR5416_DEVID_PCI:
 379                 return "Atheros 5416";
 380         case AR5416_DEVID_PCIE:
 381                 return "Atheros 5418";
 382         case AR9160_DEVID_PCI:
 383                 return "Atheros 9160";
 384         case AR9280_DEVID_PCI:
 385         case AR9280_DEVID_PCIE:
 386                 return "Atheros 9280";
 387         case AR9285_DEVID_PCIE:
 388                 return "Atheros 9285";
 389         }
 390
 391         return NULL;
 392 }
 393
 394 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 395 {
 396         int i;
 397
 398         ah->ah_config.dma_beacon_response_time = 2;
 399         ah->ah_config.sw_beacon_response_time = 10;
 400         ah->ah_config.additional_swba_backoff = 0;
 401         ah->ah_config.ack_6mb = 0x0;
 402         ah->ah_config.cwm_ignore_extcca = 0;
 403         ah->ah_config.pcie_powersave_enable = 0;
 404         ah->ah_config.pcie_l1skp_enable = 0;
 405         ah->ah_config.pcie_clock_req = 0;
 406         ah->ah_config.pcie_power_reset = 0x100;
 407         ah->ah_config.pcie_restore = 0;
 408         ah->ah_config.pcie_waen = 0;
 409         ah->ah_config.analog_shiftreg = 1;
 410         ah->ah_config.ht_enable = 1;
 411         ah->ah_config.ofdm_trig_low = 200;
 412         ah->ah_config.ofdm_trig_high = 500;
 413         ah->ah_config.cck_trig_high = 200;
 414         ah->ah_config.cck_trig_low = 100;
 415         ah->ah_config.enable_ani = 1;
 416         ah->ah_config.noise_immunity_level = 4;
 417         ah->ah_config.ofdm_weaksignal_det = 1;
 418         ah->ah_config.cck_weaksignal_thr = 0;
 419         ah->ah_config.spur_immunity_level = 2;
 420         ah->ah_config.firstep_level = 0;
 421         ah->ah_config.rssi_thr_high = 40;
 422         ah->ah_config.rssi_thr_low = 7;
 423         ah->ah_config.diversity_control = 0;
 424         ah->ah_config.antenna_switch_swap = 0;
 425
 426         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 427                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 428                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 429         }
 430
 431         ah->ah_config.intr_mitigation = 1;
 432 }
 433
 434 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 435                                               struct ath_softc *sc,
 436                                               void __iomem *mem,
 437                                               int *status)
 438 {
 439         static const u8 defbssidmask[ETH_ALEN] =
 440                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 441         struct ath_hal_5416 *ahp;
 442         struct ath_hal *ah;
 443
 444         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 445         if (ahp == NULL) {
 446                 DPRINTF(sc, ATH_DBG_FATAL,
 447                         "Cannot allocate memory for state block\n");
 448                 *status = -ENOMEM;
 449                 return NULL;
 450         }
 451
 452         ah = &ahp->ah;
 453         ah->ah_sc = sc;
 454         ah->ah_sh = mem;
 455         ah->ah_magic = AR5416_MAGIC;
 456         ah->ah_countryCode = CTRY_DEFAULT;
 457         ah->ah_devid = devid;
 458         ah->ah_subvendorid = 0;
 459
 460         ah->ah_flags = 0;
 461         if ((devid == AR5416_AR9100_DEVID))
 462                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 463         if (!AR_SREV_9100(ah))
 464                 ah->ah_flags = AH_USE_EEPROM;
 465
 466         ah->ah_powerLimit = MAX_RATE_POWER;
 467         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 468         ahp->ah_atimWindow = 0;
 469         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 470         ahp->ah_antennaSwitchSwap =
 471                 ah->ah_config.antenna_switch_swap;
 472         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 473         ahp->ah_beaconInterval = 100;
 474         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 475         ahp->ah_slottime = (u32) -1;
 476         ahp->ah_acktimeout = (u32) -1;
 477         ahp->ah_ctstimeout = (u32) -1;
 478         ahp->ah_globaltxtimeout = (u32) -1;
 479         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 480
 481         ahp->ah_gBeaconRate = 0;
 482
 483         return ahp;
 484 }
 485
 486 static int ath9k_hw_rfattach(struct ath_hal *ah)
 487 {
 488         bool rfStatus = false;
 489         int ecode = 0;
 490
 491         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 492         if (!rfStatus) {
 493                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 494                         "RF setup failed, status %u\n", ecode);
 495                 return ecode;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 502 {
 503         u32 val;
 504
 505         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 506
 507         val = ath9k_hw_get_radiorev(ah);
 508         switch (val & AR_RADIO_SREV_MAJOR) {
 509         case 0:
 510                 val = AR_RAD5133_SREV_MAJOR;
 511                 break;
 512         case AR_RAD5133_SREV_MAJOR:
 513         case AR_RAD5122_SREV_MAJOR:
 514         case AR_RAD2133_SREV_MAJOR:
 515         case AR_RAD2122_SREV_MAJOR:
 516                 break;
 517         default:
 518                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 519                         "5G Radio Chip Rev 0x%02X is not "
 520                         "supported by this driver\n",
 521                         ah->ah_analog5GhzRev);
 522                 return -EOPNOTSUPP;
 523         }
 524
 525         ah->ah_analog5GhzRev = val;
 526
 527         return 0;
 528 }
 529
 530 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 531 {
 532         u32 sum;
 533         int i;
 534         u16 eeval;
 535         struct ath_hal_5416 *ahp = AH5416(ah);
 536
 537         sum = 0;
 538         for (i = 0; i < 3; i++) {
 539                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 540                 sum += eeval;
 541                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 542                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 543         }
 544         if (sum == 0 || sum == 0xffff * 3) {
 545                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 546                         "mac address read failed: %pM\n",
 547                         ahp->ah_macaddr);
 548                 return -EADDRNOTAVAIL;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 555 {
 556         u32 rxgain_type;
 557         struct ath_hal_5416 *ahp = AH5416(ah);
 558
 559         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 560                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 561
 562                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 563                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 564                         ar9280Modes_backoff_13db_rxgain_9280_2,
 565                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 566                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 567                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 568                         ar9280Modes_backoff_23db_rxgain_9280_2,
 569                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 570                 else
 571                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 572                         ar9280Modes_original_rxgain_9280_2,
 573                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 574         } else
 575                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 576                         ar9280Modes_original_rxgain_9280_2,
 577                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 578 }
 579
 580 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 581 {
 582         u32 txgain_type;
 583         struct ath_hal_5416 *ahp = AH5416(ah);
 584
 585         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 586                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 587
 588                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 589                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 590                         ar9280Modes_high_power_tx_gain_9280_2,
 591                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 592                 else
 593                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 594                         ar9280Modes_original_tx_gain_9280_2,
 595                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 596         } else
 597                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 598                 ar9280Modes_original_tx_gain_9280_2,
 599                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 600 }
 601
 602 static int ath9k_hw_post_attach(struct ath_hal *ah)
 603 {
 604         int ecode;
 605
 606         if (!ath9k_hw_chip_test(ah)) {
 607                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 608                         "hardware self-test failed\n");
 609                 return -ENODEV;
 610         }
 611
 612         ecode = ath9k_hw_rf_claim(ah);
 613         if (ecode != 0)
 614                 return ecode;
 615
 616         ecode = ath9k_hw_eeprom_attach(ah);
 617         if (ecode != 0)
 618                 return ecode;
 619         ecode = ath9k_hw_rfattach(ah);
 620         if (ecode != 0)
 621                 return ecode;
 622
 623         if (!AR_SREV_9100(ah)) {
 624                 ath9k_hw_ani_setup(ah);
 625                 ath9k_hw_ani_attach(ah);
 626         }
 627
 628         return 0;
 629 }
 630
 631 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 632                                           void __iomem *mem, int *status)
 633 {
 634         struct ath_hal_5416 *ahp;
 635         struct ath_hal *ah;
 636         int ecode;
 637         u32 i, j;
 638
 639         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 640         if (ahp == NULL)
 641                 return NULL;
 642
 643         ah = &ahp->ah;
 644
 645         ath9k_hw_set_defaults(ah);
 646
 647         if (ah->ah_config.intr_mitigation != 0)
 648                 ahp->ah_intrMitigation = true;
 649
 650         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 651                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 652                 ecode = -EIO;
 653                 goto bad;
 654         }
 655
 656         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 657                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 658                 ecode = -EIO;
 659                 goto bad;
 660         }
 661
 662         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 663                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 664                         ah->ah_config.serialize_regmode =
 665                                 SER_REG_MODE_ON;
 666                 } else {
 667                         ah->ah_config.serialize_regmode =
 668                                 SER_REG_MODE_OFF;
 669                 }
 670         }
 671
 672         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 673                 "serialize_regmode is %d\n",
 674                 ah->ah_config.serialize_regmode);
 675
 676         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 677             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 678             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 679             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 680                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 681                         "Mac Chip Rev 0x%02x.%x is not supported by "
 682                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
 683                 ecode = -EOPNOTSUPP;
 684                 goto bad;
 685         }
 686
 687         if (AR_SREV_9100(ah)) {
 688                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 689                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 690                 ah->ah_isPciExpress = false;
 691         }
 692         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 693
 694         if (AR_SREV_9160_10_OR_LATER(ah)) {
 695                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 696                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 697                         ahp->ah_adcGainCalData.calData =
 698                                 &adc_gain_cal_single_sample;
 699                         ahp->ah_adcDcCalData.calData =
 700                                 &adc_dc_cal_single_sample;
 701                         ahp->ah_adcDcCalInitData.calData =
 702                                 &adc_init_dc_cal;
 703                 } else {
 704                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 705                         ahp->ah_adcGainCalData.calData =
 706                                 &adc_gain_cal_multi_sample;
 707                         ahp->ah_adcDcCalData.calData =
 708                                 &adc_dc_cal_multi_sample;
 709                         ahp->ah_adcDcCalInitData.calData =
 710                                 &adc_init_dc_cal;
 711                 }
 712                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 713         }
 714
 715         if (AR_SREV_9160(ah)) {
 716                 ah->ah_config.enable_ani = 1;
 717                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 718                                         ATH9K_ANI_FIRSTEP_LEVEL);
 719         } else {
 720                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 721                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 722                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 723                 }
 724         }
 725
 726         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 727                 "This Mac Chip Rev 0x%02x.%x is \n",
 728                 ah->ah_macVersion, ah->ah_macRev);
 729
 730         if (AR_SREV_9285_12_OR_LATER(ah)) {
 731                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
 732                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 733                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
 734                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 735
 736                 if (ah->ah_config.pcie_clock_req) {
 737                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 738                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 739                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 740                 } else {
 741                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 742                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 743                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 744                                   2);
 745                 }
 746         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 747                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
 748                                ARRAY_SIZE(ar9285Modes_9285), 6);
 749                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
 750                                ARRAY_SIZE(ar9285Common_9285), 2);
 751
 752                 if (ah->ah_config.pcie_clock_req) {
 753                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 754                         ar9285PciePhy_clkreq_off_L1_9285,
 755                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 756                 } else {
 757                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 758                         ar9285PciePhy_clkreq_always_on_L1_9285,
 759                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 760                 }
 761         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 762                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 763                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 764                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 765                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 766
 767                 if (ah->ah_config.pcie_clock_req) {
 768                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 769                                ar9280PciePhy_clkreq_off_L1_9280,
 770                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 771                 } else {
 772                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 773                                ar9280PciePhy_clkreq_always_on_L1_9280,
 774                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 775                 }
 776                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 777                                ar9280Modes_fast_clock_9280_2,
 778                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 779         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 780                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 781                                ARRAY_SIZE(ar9280Modes_9280), 6);
 782                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 783                                ARRAY_SIZE(ar9280Common_9280), 2);
 784         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 785                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 786                                ARRAY_SIZE(ar5416Modes_9160), 6);
 787                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 788                                ARRAY_SIZE(ar5416Common_9160), 2);
 789                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 790                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 791                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 792                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 793                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 794                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 795                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 796                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 797                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 798                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 799                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 800                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 801                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 802                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 803                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 804                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 805                 if (AR_SREV_9160_11(ah)) {
 806                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 807                                        ar5416Addac_91601_1,
 808                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 809                 } else {
 810                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 811                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 812                 }
 813         } else if (AR_SREV_9100_OR_LATER(ah)) {
 814                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 815                                ARRAY_SIZE(ar5416Modes_9100), 6);
 816                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 817                                ARRAY_SIZE(ar5416Common_9100), 2);
 818                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 819                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 820                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 821                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 822                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 823                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 824                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 825                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 826                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 827                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 828                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 829                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 830                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 831                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 832                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 833                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 834                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 835                                ARRAY_SIZE(ar5416Addac_9100), 2);
 836         } else {
 837                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 838                                ARRAY_SIZE(ar5416Modes), 6);
 839                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 840                                ARRAY_SIZE(ar5416Common), 2);
 841                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 842                                ARRAY_SIZE(ar5416Bank0), 2);
 843                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 844                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 845                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 846                                ARRAY_SIZE(ar5416Bank1), 2);
 847                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 848                                ARRAY_SIZE(ar5416Bank2), 2);
 849                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 850                                ARRAY_SIZE(ar5416Bank3), 3);
 851                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 852                                ARRAY_SIZE(ar5416Bank6), 3);
 853                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 854                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 855                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 856                                ARRAY_SIZE(ar5416Bank7), 2);
 857                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 858                                ARRAY_SIZE(ar5416Addac), 2);
 859         }
 860
 861         if (ah->ah_isPciExpress)
 862                 ath9k_hw_configpcipowersave(ah, 0);
 863         else
 864                 ath9k_hw_disablepcie(ah);
 865
 866         ecode = ath9k_hw_post_attach(ah);
 867         if (ecode != 0)
 868                 goto bad;
 869
 870         /* rxgain table */
 871         if (AR_SREV_9280_20(ah))
 872                 ath9k_hw_init_rxgain_ini(ah);
 873
 874         /* txgain table */
 875         if (AR_SREV_9280_20(ah))
 876                 ath9k_hw_init_txgain_ini(ah);
 877
 878         if (ah->ah_devid == AR9280_DEVID_PCI) {
 879                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 880                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 881
 882                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 883                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 884
 885                                 INI_RA(&ahp->ah_iniModes, i, j) =
 886                                         ath9k_hw_ini_fixup(ah,
 887                                                            &ahp->ah_eeprom.def,
 888                                                            reg, val);
 889                         }
 890                 }
 891         }
 892
 893         if (!ath9k_hw_fill_cap_info(ah)) {
 894                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 895                         "failed ath9k_hw_fill_cap_info\n");
 896                 ecode = -EINVAL;
 897                 goto bad;
 898         }
 899
 900         ecode = ath9k_hw_init_macaddr(ah);
 901         if (ecode != 0) {
 902                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 903                         "failed initializing mac address\n");
 904                 goto bad;
 905         }
 906
 907         if (AR_SREV_9285(ah))
 908                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 909         else
 910                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 911
 912         ath9k_init_nfcal_hist_buffer(ah);
 913
 914         return ah;
 915 bad:
 916         if (ahp)
 917                 ath9k_hw_detach((struct ath_hal *) ahp);
 918         if (status)
 919                 *status = ecode;
 920
 921         return NULL;
 922 }
 923
 924 static void ath9k_hw_init_bb(struct ath_hal *ah,
 925                              struct ath9k_channel *chan)
 926 {
 927         u32 synthDelay;
 928
 929         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 930         if (IS_CHAN_B(chan))
 931                 synthDelay = (4 * synthDelay) / 22;
 932         else
 933                 synthDelay /= 10;
 934
 935         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 936
 937         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 938 }
 939
 940 static void ath9k_hw_init_qos(struct ath_hal *ah)
 941 {
 942         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 943         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 944
 945         REG_WRITE(ah, AR_QOS_NO_ACK,
 946                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 947                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 948                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 949
 950         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 951         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 952         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 953         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 954         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 955 }
 956
 957 static void ath9k_hw_init_pll(struct ath_hal *ah,
 958                               struct ath9k_channel *chan)
 959 {
 960         u32 pll;
 961
 962         if (AR_SREV_9100(ah)) {
 963                 if (chan && IS_CHAN_5GHZ(chan))
 964                         pll = 0x1450;
 965                 else
 966                         pll = 0x1458;
 967         } else {
 968                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 969                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 970
 971                         if (chan && IS_CHAN_HALF_RATE(chan))
 972                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 973                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 974                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 975
 976                         if (chan && IS_CHAN_5GHZ(chan)) {
 977                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 978
 979
 980                                 if (AR_SREV_9280_20(ah)) {
 981                                         if (((chan->channel % 20) == 0)
 982                                             || ((chan->channel % 10) == 0))
 983                                                 pll = 0x2850;
 984                                         else
 985                                                 pll = 0x142c;
 986                                 }
 987                         } else {
 988                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 989                         }
 990
 991                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 992
 993                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 994
 995                         if (chan && IS_CHAN_HALF_RATE(chan))
 996                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 997                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 998                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 999
1000                         if (chan && IS_CHAN_5GHZ(chan))
1001                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1002                         else
1003                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1004                 } else {
1005                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1006
1007                         if (chan && IS_CHAN_HALF_RATE(chan))
1008                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1009                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1010                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1011
1012                         if (chan && IS_CHAN_5GHZ(chan))
1013                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1014                         else
1015                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1016                 }
1017         }
1018         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1019
1020         udelay(RTC_PLL_SETTLE_DELAY);
1021
1022         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1023 }
1024
1025 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1026 {
1027         struct ath_hal_5416 *ahp = AH5416(ah);
1028         int rx_chainmask, tx_chainmask;
1029
1030         rx_chainmask = ahp->ah_rxchainmask;
1031         tx_chainmask = ahp->ah_txchainmask;
1032
1033         switch (rx_chainmask) {
1034         case 0x5:
1035                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1036                             AR_PHY_SWAP_ALT_CHAIN);
1037         case 0x3:
1038                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1039                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1040                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1041                         break;
1042                 }
1043         case 0x1:
1044         case 0x2:
1045         case 0x7:
1046                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1047                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1048                 break;
1049         default:
1050                 break;
1051         }
1052
1053         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1054         if (tx_chainmask == 0x5) {
1055                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1056                             AR_PHY_SWAP_ALT_CHAIN);
1057         }
1058         if (AR_SREV_9100(ah))
1059                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1060                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1061 }
1062
1063 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1064                                           enum nl80211_iftype opmode)
1065 {
1066         struct ath_hal_5416 *ahp = AH5416(ah);
1067
1068         ahp->ah_maskReg = AR_IMR_TXERR |
1069                 AR_IMR_TXURN |
1070                 AR_IMR_RXERR |
1071                 AR_IMR_RXORN |
1072                 AR_IMR_BCNMISC;
1073
1074         if (ahp->ah_intrMitigation)
1075                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1076         else
1077                 ahp->ah_maskReg |= AR_IMR_RXOK;
1078
1079         ahp->ah_maskReg |= AR_IMR_TXOK;
1080
1081         if (opmode == NL80211_IFTYPE_AP)
1082                 ahp->ah_maskReg |= AR_IMR_MIB;
1083
1084         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1085         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1086
1087         if (!AR_SREV_9100(ah)) {
1088                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1089                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1090                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1091         }
1092 }
1093
1094 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1095 {
1096         struct ath_hal_5416 *ahp = AH5416(ah);
1097
1098         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1099                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1100                 ahp->ah_acktimeout = (u32) -1;
1101                 return false;
1102         } else {
1103                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1104                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1105                 ahp->ah_acktimeout = us;
1106                 return true;
1107         }
1108 }
1109
1110 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1111 {
1112         struct ath_hal_5416 *ahp = AH5416(ah);
1113
1114         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1115                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1116                 ahp->ah_ctstimeout = (u32) -1;
1117                 return false;
1118         } else {
1119                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1120                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1121                 ahp->ah_ctstimeout = us;
1122                 return true;
1123         }
1124 }
1125
1126 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1127 {
1128         struct ath_hal_5416 *ahp = AH5416(ah);
1129
1130         if (tu > 0xFFFF) {
1131                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1132                         "bad global tx timeout %u\n", tu);
1133                 ahp->ah_globaltxtimeout = (u32) -1;
1134                 return false;
1135         } else {
1136                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1137                 ahp->ah_globaltxtimeout = tu;
1138                 return true;
1139         }
1140 }
1141
1142 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1143 {
1144         struct ath_hal_5416 *ahp = AH5416(ah);
1145
1146         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1147                 ahp->ah_miscMode);
1148
1149         if (ahp->ah_miscMode != 0)
1150                 REG_WRITE(ah, AR_PCU_MISC,
1151                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1152         if (ahp->ah_slottime != (u32) -1)
1153                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1154         if (ahp->ah_acktimeout != (u32) -1)
1155                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1156         if (ahp->ah_ctstimeout != (u32) -1)
1157                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1158         if (ahp->ah_globaltxtimeout != (u32) -1)
1159                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1160 }
1161
1162 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1163 {
1164         return vendorid == ATHEROS_VENDOR_ID ?
1165                 ath9k_hw_devname(devid) : NULL;
1166 }
1167
1168 void ath9k_hw_detach(struct ath_hal *ah)
1169 {
1170         if (!AR_SREV_9100(ah))
1171                 ath9k_hw_ani_detach(ah);
1172
1173         ath9k_hw_rfdetach(ah);
1174         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1175         kfree(ah);
1176 }
1177
1178 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1179                                 void __iomem *mem, int *error)
1180 {
1181         struct ath_hal *ah = NULL;
1182
1183         switch (devid) {
1184         case AR5416_DEVID_PCI:
1185         case AR5416_DEVID_PCIE:
1186         case AR9160_DEVID_PCI:
1187         case AR9280_DEVID_PCI:
1188         case AR9280_DEVID_PCIE:
1189         case AR9285_DEVID_PCIE:
1190                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1191                 break;
1192         default:
1193                 *error = -ENXIO;
1194                 break;
1195         }
1196
1197         return ah;
1198 }
1199
1200 /*******/
1201 /* INI */
1202 /*******/
1203
1204 static void ath9k_hw_override_ini(struct ath_hal *ah,
1205                                   struct ath9k_channel *chan)
1206 {
1207         /*
1208          * Set the RX_ABORT and RX_DIS and clear if off only after
1209          * RXE is set for MAC. This prevents frames with corrupted
1210          * descriptor status.
1211          */
1212         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1213
1214
1215         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1216             AR_SREV_9280_10_OR_LATER(ah))
1217                 return;
1218
1219         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1220 }
1221
1222 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1223                               struct ar5416_eeprom_def *pEepData,
1224                               u32 reg, u32 value)
1225 {
1226         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1227
1228         switch (ah->ah_devid) {
1229         case AR9280_DEVID_PCI:
1230                 if (reg == 0x7894) {
1231                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1232                                 "ini VAL: %x  EEPROM: %x\n", value,
1233                                 (pBase->version & 0xff));
1234
1235                         if ((pBase->version & 0xff) > 0x0a) {
1236                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1237                                         "PWDCLKIND: %d\n",
1238                                         pBase->pwdclkind);
1239                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1240                                 value |= AR_AN_TOP2_PWDCLKIND &
1241                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1242                         } else {
1243                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1244                                         "PWDCLKIND Earlier Rev\n");
1245                         }
1246
1247                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1248                                 "final ini VAL: %x\n", value);
1249                 }
1250                 break;
1251         }
1252
1253         return value;
1254 }
1255
1256 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1257                               struct ar5416_eeprom_def *pEepData,
1258                               u32 reg, u32 value)
1259 {
1260         struct ath_hal_5416 *ahp = AH5416(ah);
1261
1262         if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1263                 return value;
1264         else
1265                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1266 }
1267
1268 static int ath9k_hw_process_ini(struct ath_hal *ah,
1269                                 struct ath9k_channel *chan,
1270                                 enum ath9k_ht_macmode macmode)
1271 {
1272         int i, regWrites = 0;
1273         struct ath_hal_5416 *ahp = AH5416(ah);
1274         u32 modesIndex, freqIndex;
1275         int status;
1276
1277         switch (chan->chanmode) {
1278         case CHANNEL_A:
1279         case CHANNEL_A_HT20:
1280                 modesIndex = 1;
1281                 freqIndex = 1;
1282                 break;
1283         case CHANNEL_A_HT40PLUS:
1284         case CHANNEL_A_HT40MINUS:
1285                 modesIndex = 2;
1286                 freqIndex = 1;
1287                 break;
1288         case CHANNEL_G:
1289         case CHANNEL_G_HT20:
1290         case CHANNEL_B:
1291                 modesIndex = 4;
1292                 freqIndex = 2;
1293                 break;
1294         case CHANNEL_G_HT40PLUS:
1295         case CHANNEL_G_HT40MINUS:
1296                 modesIndex = 3;
1297                 freqIndex = 2;
1298                 break;
1299
1300         default:
1301                 return -EINVAL;
1302         }
1303
1304         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1305
1306         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1307
1308         ath9k_hw_set_addac(ah, chan);
1309
1310         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1311                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1312         } else {
1313                 struct ar5416IniArray temp;
1314                 u32 addacSize =
1315                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1316                         ahp->ah_iniAddac.ia_columns;
1317
1318                 memcpy(ahp->ah_addac5416_21,
1319                        ahp->ah_iniAddac.ia_array, addacSize);
1320
1321                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1322
1323                 temp.ia_array = ahp->ah_addac5416_21;
1324                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1325                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1326                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1327         }
1328
1329         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1330
1331         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1332                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1333                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1334
1335                 REG_WRITE(ah, reg, val);
1336
1337                 if (reg >= 0x7800 && reg < 0x78a0
1338                     && ah->ah_config.analog_shiftreg) {
1339                         udelay(100);
1340                 }
1341
1342                 DO_DELAY(regWrites);
1343         }
1344
1345         if (AR_SREV_9280(ah))
1346                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1347
1348         if (AR_SREV_9280(ah))
1349                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1350
1351         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1352                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1353                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1354
1355                 REG_WRITE(ah, reg, val);
1356
1357                 if (reg >= 0x7800 && reg < 0x78a0
1358                     && ah->ah_config.analog_shiftreg) {
1359                         udelay(100);
1360                 }
1361
1362                 DO_DELAY(regWrites);
1363         }
1364
1365         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1366
1367         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1368                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1369                                 regWrites);
1370         }
1371
1372         ath9k_hw_override_ini(ah, chan);
1373         ath9k_hw_set_regs(ah, chan, macmode);
1374         ath9k_hw_init_chain_masks(ah);
1375
1376         status = ath9k_hw_set_txpower(ah, chan,
1377                                       ath9k_regd_get_ctl(ah, chan),
1378                                       ath9k_regd_get_antenna_allowed(ah,
1379                                                                      chan),
1380                                       chan->maxRegTxPower * 2,
1381                                       min((u32) MAX_RATE_POWER,
1382                                           (u32) ah->ah_powerLimit));
1383         if (status != 0) {
1384                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1385                         "error init'ing transmit power\n");
1386                 return -EIO;
1387         }
1388
1389         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1390                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1391                         "ar5416SetRfRegs failed\n");
1392                 return -EIO;
1393         }
1394
1395         return 0;
1396 }
1397
1398 /****************************************/
1399 /* Reset and Channel Switching Routines */
1400 /****************************************/
1401
1402 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1403 {
1404         u32 rfMode = 0;
1405
1406         if (chan == NULL)
1407                 return;
1408
1409         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1410                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1411
1412         if (!AR_SREV_9280_10_OR_LATER(ah))
1413                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1414                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1415
1416         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1417                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1418
1419         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1420 }
1421
1422 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1423 {
1424         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1425 }
1426
1427 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1428 {
1429         u32 regval;
1430
1431         regval = REG_READ(ah, AR_AHB_MODE);
1432         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1433
1434         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1435         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1436
1437         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1438
1439         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1440         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1441
1442         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1443
1444         if (AR_SREV_9285(ah)) {
1445                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1446                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1447         } else {
1448                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1449                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1450         }
1451 }
1452
1453 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1454 {
1455         u32 val;
1456
1457         val = REG_READ(ah, AR_STA_ID1);
1458         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1459         switch (opmode) {
1460         case NL80211_IFTYPE_AP:
1461                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1462                           | AR_STA_ID1_KSRCH_MODE);
1463                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1464                 break;
1465         case NL80211_IFTYPE_ADHOC:
1466                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1467                           | AR_STA_ID1_KSRCH_MODE);
1468                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1469                 break;
1470         case NL80211_IFTYPE_STATION:
1471         case NL80211_IFTYPE_MONITOR:
1472                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1473                 break;
1474         }
1475 }
1476
1477 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1478                                                  u32 coef_scaled,
1479                                                  u32 *coef_mantissa,
1480                                                  u32 *coef_exponent)
1481 {
1482         u32 coef_exp, coef_man;
1483
1484         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1485                 if ((coef_scaled >> coef_exp) & 0x1)
1486                         break;
1487
1488         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1489
1490         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1491
1492         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1493         *coef_exponent = coef_exp - 16;
1494 }
1495
1496 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1497                                      struct ath9k_channel *chan)
1498 {
1499         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1500         u32 clockMhzScaled = 0x64000000;
1501         struct chan_centers centers;
1502
1503         if (IS_CHAN_HALF_RATE(chan))
1504                 clockMhzScaled = clockMhzScaled >> 1;
1505         else if (IS_CHAN_QUARTER_RATE(chan))
1506                 clockMhzScaled = clockMhzScaled >> 2;
1507
1508         ath9k_hw_get_channel_centers(ah, chan, &centers);
1509         coef_scaled = clockMhzScaled / centers.synth_center;
1510
1511         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1512                                       &ds_coef_exp);
1513
1514         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1515                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1516         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1517                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1518
1519         coef_scaled = (9 * coef_scaled) / 10;
1520
1521         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1522                                       &ds_coef_exp);
1523
1524         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1525                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1526         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1527                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1528 }
1529
1530 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1531 {
1532         u32 rst_flags;
1533         u32 tmpReg;
1534
1535         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1536                   AR_RTC_FORCE_WAKE_ON_INT);
1537
1538         if (AR_SREV_9100(ah)) {
1539                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1540                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1541         } else {
1542                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1543                 if (tmpReg &
1544                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1545                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1546                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1547                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1548                 } else {
1549                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1550                 }
1551
1552                 rst_flags = AR_RTC_RC_MAC_WARM;
1553                 if (type == ATH9K_RESET_COLD)
1554                         rst_flags |= AR_RTC_RC_MAC_COLD;
1555         }
1556
1557         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1558         udelay(50);
1559
1560         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1561         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1562                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1563                         "RTC stuck in MAC reset\n");
1564                 return false;
1565         }
1566
1567         if (!AR_SREV_9100(ah))
1568                 REG_WRITE(ah, AR_RC, 0);
1569
1570         ath9k_hw_init_pll(ah, NULL);
1571
1572         if (AR_SREV_9100(ah))
1573                 udelay(50);
1574
1575         return true;
1576 }
1577
1578 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1579 {
1580         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1581                   AR_RTC_FORCE_WAKE_ON_INT);
1582
1583         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1584         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1585
1586         if (!ath9k_hw_wait(ah,
1587                            AR_RTC_STATUS,
1588                            AR_RTC_STATUS_M,
1589                            AR_RTC_STATUS_ON)) {
1590                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1591                 return false;
1592         }
1593
1594         ath9k_hw_read_revisions(ah);
1595
1596         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1597 }
1598
1599 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1600 {
1601         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1602                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1603
1604         switch (type) {
1605         case ATH9K_RESET_POWER_ON:
1606                 return ath9k_hw_set_reset_power_on(ah);
1607                 break;
1608         case ATH9K_RESET_WARM:
1609         case ATH9K_RESET_COLD:
1610                 return ath9k_hw_set_reset(ah, type);
1611                 break;
1612         default:
1613                 return false;
1614         }
1615 }
1616
1617 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1618                               enum ath9k_ht_macmode macmode)
1619 {
1620         u32 phymode;
1621         u32 enableDacFifo = 0;
1622         struct ath_hal_5416 *ahp = AH5416(ah);
1623
1624         if (AR_SREV_9285_10_OR_LATER(ah))
1625                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1626                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1627
1628         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1629                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1630
1631         if (IS_CHAN_HT40(chan)) {
1632                 phymode |= AR_PHY_FC_DYN2040_EN;
1633
1634                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1635                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1636                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1637
1638                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1639                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1640         }
1641         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1642
1643         ath9k_hw_set11nmac2040(ah, macmode);
1644
1645         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1646         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1647 }
1648
1649 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1650                                 struct ath9k_channel *chan)
1651 {
1652         struct ath_hal_5416 *ahp = AH5416(ah);
1653
1654         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1655                 return false;
1656
1657         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1658                 return false;
1659
1660         ahp->ah_chipFullSleep = false;
1661
1662         ath9k_hw_init_pll(ah, chan);
1663
1664         ath9k_hw_set_rfmode(ah, chan);
1665
1666         return true;
1667 }
1668
1669 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1670                                     struct ath9k_channel *chan,
1671                                     enum ath9k_ht_macmode macmode)
1672 {
1673         u32 synthDelay, qnum;
1674
1675         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1676                 if (ath9k_hw_numtxpending(ah, qnum)) {
1677                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1678                                 "Transmit frames pending on queue %d\n", qnum);
1679                         return false;
1680                 }
1681         }
1682
1683         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1684         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1685                            AR_PHY_RFBUS_GRANT_EN)) {
1686                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1687                         "Could not kill baseband RX\n");
1688                 return false;
1689         }
1690
1691         ath9k_hw_set_regs(ah, chan, macmode);
1692
1693         if (AR_SREV_9280_10_OR_LATER(ah)) {
1694                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1695                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1696                                 "failed to set channel\n");
1697                         return false;
1698                 }
1699         } else {
1700                 if (!(ath9k_hw_set_channel(ah, chan))) {
1701                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1702                                 "failed to set channel\n");
1703                         return false;
1704                 }
1705         }
1706
1707         if (ath9k_hw_set_txpower(ah, chan,
1708                                  ath9k_regd_get_ctl(ah, chan),
1709                                  ath9k_regd_get_antenna_allowed(ah, chan),
1710                                  chan->maxRegTxPower * 2,
1711                                  min((u32) MAX_RATE_POWER,
1712                                      (u32) ah->ah_powerLimit)) != 0) {
1713                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1714                         "error init'ing transmit power\n");
1715                 return false;
1716         }
1717
1718         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1719         if (IS_CHAN_B(chan))
1720                 synthDelay = (4 * synthDelay) / 22;
1721         else
1722                 synthDelay /= 10;
1723
1724         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1725
1726         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1727
1728         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1729                 ath9k_hw_set_delta_slope(ah, chan);
1730
1731         if (AR_SREV_9280_10_OR_LATER(ah))
1732                 ath9k_hw_9280_spur_mitigate(ah, chan);
1733         else
1734                 ath9k_hw_spur_mitigate(ah, chan);
1735
1736         if (!chan->oneTimeCalsDone)
1737                 chan->oneTimeCalsDone = true;
1738
1739         return true;
1740 }
1741
1742 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1743 {
1744         int bb_spur = AR_NO_SPUR;
1745         int freq;
1746         int bin, cur_bin;
1747         int bb_spur_off, spur_subchannel_sd;
1748         int spur_freq_sd;
1749         int spur_delta_phase;
1750         int denominator;
1751         int upper, lower, cur_vit_mask;
1752         int tmp, newVal;
1753         int i;
1754         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1755                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1756         };
1757         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1758                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1759         };
1760         int inc[4] = { 0, 100, 0, 0 };
1761         struct chan_centers centers;
1762
1763         int8_t mask_m[123];
1764         int8_t mask_p[123];
1765         int8_t mask_amt;
1766         int tmp_mask;
1767         int cur_bb_spur;
1768         bool is2GHz = IS_CHAN_2GHZ(chan);
1769
1770         memset(&mask_m, 0, sizeof(int8_t) * 123);
1771         memset(&mask_p, 0, sizeof(int8_t) * 123);
1772
1773         ath9k_hw_get_channel_centers(ah, chan, &centers);
1774         freq = centers.synth_center;
1775
1776         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1777         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1778                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1779
1780                 if (is2GHz)
1781                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1782                 else
1783                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1784
1785                 if (AR_NO_SPUR == cur_bb_spur)
1786                         break;
1787                 cur_bb_spur = cur_bb_spur - freq;
1788
1789                 if (IS_CHAN_HT40(chan)) {
1790                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1791                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1792                                 bb_spur = cur_bb_spur;
1793                                 break;
1794                         }
1795                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1796                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1797                         bb_spur = cur_bb_spur;
1798                         break;
1799                 }
1800         }
1801
1802         if (AR_NO_SPUR == bb_spur) {
1803                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1804                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1805                 return;
1806         } else {
1807                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1808                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1809         }
1810
1811         bin = bb_spur * 320;
1812
1813         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1814
1815         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1816                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1817                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1818                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1819         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1820
1821         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1822                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1823                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1824                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1825                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1826         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1827
1828         if (IS_CHAN_HT40(chan)) {
1829                 if (bb_spur < 0) {
1830                         spur_subchannel_sd = 1;
1831                         bb_spur_off = bb_spur + 10;
1832                 } else {
1833                         spur_subchannel_sd = 0;
1834                         bb_spur_off = bb_spur - 10;
1835                 }
1836         } else {
1837                 spur_subchannel_sd = 0;
1838                 bb_spur_off = bb_spur;
1839         }
1840
1841         if (IS_CHAN_HT40(chan))
1842                 spur_delta_phase =
1843                         ((bb_spur * 262144) /
1844                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1845         else
1846                 spur_delta_phase =
1847                         ((bb_spur * 524288) /
1848                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1849
1850         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1851         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1852
1853         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1854                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1855                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1856         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1857
1858         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1859         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1860
1861         cur_bin = -6000;
1862         upper = bin + 100;
1863         lower = bin - 100;
1864
1865         for (i = 0; i < 4; i++) {
1866                 int pilot_mask = 0;
1867                 int chan_mask = 0;
1868                 int bp = 0;
1869                 for (bp = 0; bp < 30; bp++) {
1870                         if ((cur_bin > lower) && (cur_bin < upper)) {
1871                                 pilot_mask = pilot_mask | 0x1 << bp;
1872                                 chan_mask = chan_mask | 0x1 << bp;
1873                         }
1874                         cur_bin += 100;
1875                 }
1876                 cur_bin += inc[i];
1877                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1878                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1879         }
1880
1881         cur_vit_mask = 6100;
1882         upper = bin + 120;
1883         lower = bin - 120;
1884
1885         for (i = 0; i < 123; i++) {
1886                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1887
1888                         /* workaround for gcc bug #37014 */
1889                         volatile int tmp = abs(cur_vit_mask - bin);
1890
1891                         if (tmp < 75)
1892                                 mask_amt = 1;
1893                         else
1894                                 mask_amt = 0;
1895                         if (cur_vit_mask < 0)
1896                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1897                         else
1898                                 mask_p[cur_vit_mask / 100] = mask_amt;
1899                 }
1900                 cur_vit_mask -= 100;
1901         }
1902
1903         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1904                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1905                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1906                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1907                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1908                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1909                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1910                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1911         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1912         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1913
1914         tmp_mask = (mask_m[31] << 28)
1915                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1916                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1917                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1918                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1919                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1920                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1921                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1922         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1923         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1924
1925         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1926                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1927                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1928                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1929                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1930                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1931                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1932                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1933         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1934         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1935
1936         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1937                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1938                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1939                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1940                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1941                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1942                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1943                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1944         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1945         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1946
1947         tmp_mask = (mask_p[15] << 28)
1948                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1949                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1950                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1951                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1952                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1953                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1954                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1955         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1956         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1957
1958         tmp_mask = (mask_p[30] << 28)
1959                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1960                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1961                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1962                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1963                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1964                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1965                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1966         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1967         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1968
1969         tmp_mask = (mask_p[45] << 28)
1970                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1971                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1972                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1973                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1974                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1975                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1976                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1977         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1978         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1979
1980         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1981                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1982                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1983                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1984                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1985                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1986                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1987                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1988         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1989         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1990 }
1991
1992 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1993 {
1994         int bb_spur = AR_NO_SPUR;
1995         int bin, cur_bin;
1996         int spur_freq_sd;
1997         int spur_delta_phase;
1998         int denominator;
1999         int upper, lower, cur_vit_mask;
2000         int tmp, new;
2001         int i;
2002         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2003                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2004         };
2005         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2006                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2007         };
2008         int inc[4] = { 0, 100, 0, 0 };
2009
2010         int8_t mask_m[123];
2011         int8_t mask_p[123];
2012         int8_t mask_amt;
2013         int tmp_mask;
2014         int cur_bb_spur;
2015         bool is2GHz = IS_CHAN_2GHZ(chan);
2016
2017         memset(&mask_m, 0, sizeof(int8_t) * 123);
2018         memset(&mask_p, 0, sizeof(int8_t) * 123);
2019
2020         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2021                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2022                 if (AR_NO_SPUR == cur_bb_spur)
2023                         break;
2024                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2025                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2026                         bb_spur = cur_bb_spur;
2027                         break;
2028                 }
2029         }
2030
2031         if (AR_NO_SPUR == bb_spur)
2032                 return;
2033
2034         bin = bb_spur * 32;
2035
2036         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2037         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2038                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2039                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2040                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2041
2042         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2043
2044         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2045                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2046                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2047                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2048                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2049         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2050
2051         spur_delta_phase = ((bb_spur * 524288) / 100) &
2052                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2053
2054         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2055         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2056
2057         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2058                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2059                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2060         REG_WRITE(ah, AR_PHY_TIMING11, new);
2061
2062         cur_bin = -6000;
2063         upper = bin + 100;
2064         lower = bin - 100;
2065
2066         for (i = 0; i < 4; i++) {
2067                 int pilot_mask = 0;
2068                 int chan_mask = 0;
2069                 int bp = 0;
2070                 for (bp = 0; bp < 30; bp++) {
2071                         if ((cur_bin > lower) && (cur_bin < upper)) {
2072                                 pilot_mask = pilot_mask | 0x1 << bp;
2073                                 chan_mask = chan_mask | 0x1 << bp;
2074                         }
2075                         cur_bin += 100;
2076                 }
2077                 cur_bin += inc[i];
2078                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2079                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2080         }
2081
2082         cur_vit_mask = 6100;
2083         upper = bin + 120;
2084         lower = bin - 120;
2085
2086         for (i = 0; i < 123; i++) {
2087                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2088
2089                         /* workaround for gcc bug #37014 */
2090                         volatile int tmp = abs(cur_vit_mask - bin);
2091
2092                         if (tmp < 75)
2093                                 mask_amt = 1;
2094                         else
2095                                 mask_amt = 0;
2096                         if (cur_vit_mask < 0)
2097                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2098                         else
2099                                 mask_p[cur_vit_mask / 100] = mask_amt;
2100                 }
2101                 cur_vit_mask -= 100;
2102         }
2103
2104         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2105                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2106                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2107                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2108                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2109                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2110                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2111                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2112         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2113         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2114
2115         tmp_mask = (mask_m[31] << 28)
2116                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2117                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2118                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2119                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2120                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2121                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2122                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2123         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2124         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2125
2126         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2127                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2128                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2129                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2130                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2131                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2132                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2133                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2134         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2135         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2136
2137         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2138                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2139                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2140                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2141                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2142                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2143                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2144                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2145         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2146         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2147
2148         tmp_mask = (mask_p[15] << 28)
2149                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2150                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2151                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2152                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2153                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2154                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2155                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2156         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2157         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2158
2159         tmp_mask = (mask_p[30] << 28)
2160                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2161                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2162                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2163                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2164                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2165                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2166                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2167         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2168         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2169
2170         tmp_mask = (mask_p[45] << 28)
2171                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2172                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2173                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2174                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2175                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2176                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2177                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2178         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2179         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2180
2181         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2182                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2183                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2184                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2185                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2186                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2187                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2188                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2189         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2190         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2191 }
2192
2193 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2194                     bool bChannelChange)
2195 {
2196         u32 saveLedState;
2197         struct ath_softc *sc = ah->ah_sc;
2198         struct ath_hal_5416 *ahp = AH5416(ah);
2199         struct ath9k_channel *curchan = ah->ah_curchan;
2200         u32 saveDefAntenna;
2201         u32 macStaId1;
2202         int i, rx_chainmask, r;
2203
2204         ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2205         ahp->ah_txchainmask = sc->sc_tx_chainmask;
2206         ahp->ah_rxchainmask = sc->sc_rx_chainmask;
2207
2208         if (AR_SREV_9280(ah)) {
2209                 ahp->ah_txchainmask &= 0x3;
2210                 ahp->ah_rxchainmask &= 0x3;
2211         }
2212
2213         if (ath9k_regd_check_channel(ah, chan) == NULL) {
2214                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2215                         "invalid channel %u/0x%x; no mapping\n",
2216                         chan->channel, chan->channelFlags);
2217                 return -EINVAL;
2218         }
2219
2220         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2221                 return -EIO;
2222
2223         if (curchan)
2224                 ath9k_hw_getnf(ah, curchan);
2225
2226         if (bChannelChange &&
2227             (ahp->ah_chipFullSleep != true) &&
2228             (ah->ah_curchan != NULL) &&
2229             (chan->channel != ah->ah_curchan->channel) &&
2230             ((chan->channelFlags & CHANNEL_ALL) ==
2231              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2232             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2233                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2234
2235                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2236                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2237                         ath9k_hw_start_nfcal(ah);
2238                         return 0;
2239                 }
2240         }
2241
2242         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2243         if (saveDefAntenna == 0)
2244                 saveDefAntenna = 1;
2245
2246         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2247
2248         saveLedState = REG_READ(ah, AR_CFG_LED) &
2249                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2250                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2251
2252         ath9k_hw_mark_phy_inactive(ah);
2253
2254         if (!ath9k_hw_chip_reset(ah, chan)) {
2255                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2256                 return -EINVAL;
2257         }
2258
2259         if (AR_SREV_9280(ah)) {
2260                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2261                             AR_GPIO_JTAG_DISABLE);
2262
2263                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2264                         if (IS_CHAN_5GHZ(chan))
2265                                 ath9k_hw_set_gpio(ah, 9, 0);
2266                         else
2267                                 ath9k_hw_set_gpio(ah, 9, 1);
2268                 }
2269                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2270         }
2271
2272         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2273         if (r)
2274                 return r;
2275
2276         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2277                 ath9k_hw_set_delta_slope(ah, chan);
2278
2279         if (AR_SREV_9280_10_OR_LATER(ah))
2280                 ath9k_hw_9280_spur_mitigate(ah, chan);
2281         else
2282                 ath9k_hw_spur_mitigate(ah, chan);
2283
2284         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2285                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2286                         "error setting board options\n");
2287                 return -EIO;
2288         }
2289
2290         ath9k_hw_decrease_chain_power(ah, chan);
2291
2292         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2293         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2294                   | macStaId1
2295                   | AR_STA_ID1_RTS_USE_DEF
2296                   | (ah->ah_config.
2297                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2298                   | ahp->ah_staId1Defaults);
2299         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2300
2301         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2302         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2303
2304         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2305
2306         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2307         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2308                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2309
2310         REG_WRITE(ah, AR_ISR, ~0);
2311
2312         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2313
2314         if (AR_SREV_9280_10_OR_LATER(ah)) {
2315                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2316                         return -EIO;
2317         } else {
2318                 if (!(ath9k_hw_set_channel(ah, chan)))
2319                         return -EIO;
2320         }
2321
2322         for (i = 0; i < AR_NUM_DCU; i++)
2323                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2324
2325         ahp->ah_intrTxqs = 0;
2326         for (i = 0; i < ah->ah_caps.total_queues; i++)
2327                 ath9k_hw_resettxqueue(ah, i);
2328
2329         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2330         ath9k_hw_init_qos(ah);
2331
2332 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2333         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2334                 ath9k_enable_rfkill(ah);
2335 #endif
2336         ath9k_hw_init_user_settings(ah);
2337
2338         REG_WRITE(ah, AR_STA_ID1,
2339                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2340
2341         ath9k_hw_set_dma(ah);
2342
2343         REG_WRITE(ah, AR_OBS, 8);
2344
2345         if (ahp->ah_intrMitigation) {
2346
2347                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2348                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2349         }
2350
2351         ath9k_hw_init_bb(ah, chan);
2352
2353         if (!ath9k_hw_init_cal(ah, chan))
2354                 return -EIO;;
2355
2356         rx_chainmask = ahp->ah_rxchainmask;
2357         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2358                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2359                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2360         }
2361
2362         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2363
2364         if (AR_SREV_9100(ah)) {
2365                 u32 mask;
2366                 mask = REG_READ(ah, AR_CFG);
2367                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2368                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2369                                 "CFG Byte Swap Set 0x%x\n", mask);
2370                 } else {
2371                         mask =
2372                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2373                         REG_WRITE(ah, AR_CFG, mask);
2374                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2375                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2376                 }
2377         } else {
2378 #ifdef __BIG_ENDIAN
2379                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2380 #endif
2381         }
2382
2383         return 0;
2384 }
2385
2386 /************************/
2387 /* Key Cache Management */
2388 /************************/
2389
2390 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2391 {
2392         u32 keyType;
2393
2394         if (entry >= ah->ah_caps.keycache_size) {
2395                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2396                         "entry %u out of range\n", entry);
2397                 return false;
2398         }
2399
2400         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2401
2402         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2403         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2404         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2405         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2406         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2407         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2408         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2409         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2410
2411         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2412                 u16 micentry = entry + 64;
2413
2414                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2415                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2416                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2417                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2418
2419         }
2420
2421         if (ah->ah_curchan == NULL)
2422                 return true;
2423
2424         return true;
2425 }
2426
2427 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2428 {
2429         u32 macHi, macLo;
2430
2431         if (entry >= ah->ah_caps.keycache_size) {
2432                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2433                         "entry %u out of range\n", entry);
2434                 return false;
2435         }
2436
2437         if (mac != NULL) {
2438                 macHi = (mac[5] << 8) | mac[4];
2439                 macLo = (mac[3] << 24) |
2440                         (mac[2] << 16) |
2441                         (mac[1] << 8) |
2442                         mac[0];
2443                 macLo >>= 1;
2444                 macLo |= (macHi & 1) << 31;
2445                 macHi >>= 1;
2446         } else {
2447                 macLo = macHi = 0;
2448         }
2449         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2450         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2451
2452         return true;
2453 }
2454
2455 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2456                                  const struct ath9k_keyval *k,
2457                                  const u8 *mac, int xorKey)
2458 {
2459         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2460         u32 key0, key1, key2, key3, key4;
2461         u32 keyType;
2462         u32 xorMask = xorKey ?
2463                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2464                  | ATH9K_KEY_XOR) : 0;
2465         struct ath_hal_5416 *ahp = AH5416(ah);
2466
2467         if (entry >= pCap->keycache_size) {
2468                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2469                         "entry %u out of range\n", entry);
2470                 return false;
2471         }
2472
2473         switch (k->kv_type) {
2474         case ATH9K_CIPHER_AES_OCB:
2475                 keyType = AR_KEYTABLE_TYPE_AES;
2476                 break;
2477         case ATH9K_CIPHER_AES_CCM:
2478                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2479                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2480                                 "AES-CCM not supported by mac rev 0x%x\n",
2481                                 ah->ah_macRev);
2482                         return false;
2483                 }
2484                 keyType = AR_KEYTABLE_TYPE_CCM;
2485                 break;
2486         case ATH9K_CIPHER_TKIP:
2487                 keyType = AR_KEYTABLE_TYPE_TKIP;
2488                 if (ATH9K_IS_MIC_ENABLED(ah)
2489                     && entry + 64 >= pCap->keycache_size) {
2490                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2491                                 "entry %u inappropriate for TKIP\n", entry);
2492                         return false;
2493                 }
2494                 break;
2495         case ATH9K_CIPHER_WEP:
2496                 if (k->kv_len < LEN_WEP40) {
2497                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2498                                 "WEP key length %u too small\n", k->kv_len);
2499                         return false;
2500                 }
2501                 if (k->kv_len <= LEN_WEP40)
2502                         keyType = AR_KEYTABLE_TYPE_40;
2503                 else if (k->kv_len <= LEN_WEP104)
2504                         keyType = AR_KEYTABLE_TYPE_104;
2505                 else
2506                         keyType = AR_KEYTABLE_TYPE_128;
2507                 break;
2508         case ATH9K_CIPHER_CLR:
2509                 keyType = AR_KEYTABLE_TYPE_CLR;
2510                 break;
2511         default:
2512                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2513                         "cipher %u not supported\n", k->kv_type);
2514                 return false;
2515         }
2516
2517         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2518         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2519         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2520         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2521         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2522         if (k->kv_len <= LEN_WEP104)
2523                 key4 &= 0xff;
2524
2525         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2526                 u16 micentry = entry + 64;
2527
2528                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2529                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2530                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2531                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2532                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2533                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2534                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2535
2536                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2537                         u32 mic0, mic1, mic2, mic3, mic4;
2538
2539                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2540                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2541                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2542                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2543                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2544                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2545                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2546                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2547                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2548                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2549                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2550                                   AR_KEYTABLE_TYPE_CLR);
2551
2552                 } else {
2553                         u32 mic0, mic2;
2554
2555                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2556                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2557                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2558                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2559                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2560                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2561                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2562                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2563                                   AR_KEYTABLE_TYPE_CLR);
2564                 }
2565                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2566                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2567                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2568                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2569         } else {
2570                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2571                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2572                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2573                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2574                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2575                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2576
2577                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2578         }
2579
2580         if (ah->ah_curchan == NULL)
2581                 return true;
2582
2583         return true;
2584 }
2585
2586 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2587 {
2588         if (entry < ah->ah_caps.keycache_size) {
2589                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2590                 if (val & AR_KEYTABLE_VALID)
2591                         return true;
2592         }
2593         return false;
2594 }
2595
2596 /******************************/
2597 /* Power Management (Chipset) */
2598 /******************************/
2599
2600 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2601 {
2602         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2603         if (setChip) {
2604                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2605                             AR_RTC_FORCE_WAKE_EN);
2606                 if (!AR_SREV_9100(ah))
2607                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2608
2609                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2610                             AR_RTC_RESET_EN);
2611         }
2612 }
2613
2614 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2615 {
2616         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2617         if (setChip) {
2618                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2619
2620                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2621                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2622                                   AR_RTC_FORCE_WAKE_ON_INT);
2623                 } else {
2624                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2625                                     AR_RTC_FORCE_WAKE_EN);
2626                 }
2627         }
2628 }
2629
2630 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2631                                      int setChip)
2632 {
2633         u32 val;
2634         int i;
2635
2636         if (setChip) {
2637                 if ((REG_READ(ah, AR_RTC_STATUS) &
2638                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2639                         if (ath9k_hw_set_reset_reg(ah,
2640                                            ATH9K_RESET_POWER_ON) != true) {
2641                                 return false;
2642                         }
2643                 }
2644                 if (AR_SREV_9100(ah))
2645                         REG_SET_BIT(ah, AR_RTC_RESET,
2646                                     AR_RTC_RESET_EN);
2647
2648                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2649                             AR_RTC_FORCE_WAKE_EN);
2650                 udelay(50);
2651
2652                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2653                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2654                         if (val == AR_RTC_STATUS_ON)
2655                                 break;
2656                         udelay(50);
2657                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2658                                     AR_RTC_FORCE_WAKE_EN);
2659                 }
2660                 if (i == 0) {
2661                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2662                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2663                         return false;
2664                 }
2665         }
2666
2667         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2668
2669         return true;
2670 }
2671
2672 bool ath9k_hw_setpower(struct ath_hal *ah,
2673                        enum ath9k_power_mode mode)
2674 {
2675         struct ath_hal_5416 *ahp = AH5416(ah);
2676         static const char *modes[] = {
2677                 "AWAKE",
2678                 "FULL-SLEEP",
2679                 "NETWORK SLEEP",
2680                 "UNDEFINED"
2681         };
2682         int status = true, setChip = true;
2683
2684         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2685                 modes[ahp->ah_powerMode], modes[mode],
2686                 setChip ? "set chip " : "");
2687
2688         switch (mode) {
2689         case ATH9K_PM_AWAKE:
2690                 status = ath9k_hw_set_power_awake(ah, setChip);
2691                 break;
2692         case ATH9K_PM_FULL_SLEEP:
2693                 ath9k_set_power_sleep(ah, setChip);
2694                 ahp->ah_chipFullSleep = true;
2695                 break;
2696         case ATH9K_PM_NETWORK_SLEEP:
2697                 ath9k_set_power_network_sleep(ah, setChip);
2698                 break;
2699         default:
2700                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2701                         "Unknown power mode %u\n", mode);
2702                 return false;
2703         }
2704         ahp->ah_powerMode = mode;
2705
2706         return status;
2707 }
2708
2709 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2710 {
2711         struct ath_hal_5416 *ahp = AH5416(ah);
2712         u8 i;
2713
2714         if (ah->ah_isPciExpress != true)
2715                 return;
2716
2717         if (ah->ah_config.pcie_powersave_enable == 2)
2718                 return;
2719
2720         if (restore)
2721                 return;
2722
2723         if (AR_SREV_9280_20_OR_LATER(ah)) {
2724                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2725                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2726                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2727                 }
2728                 udelay(1000);
2729         } else if (AR_SREV_9280(ah) &&
2730                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2731                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2732                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2733
2734                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2735                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2736                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2737
2738                 if (ah->ah_config.pcie_clock_req)
2739                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2740                 else
2741                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2742
2743                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2744                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2745                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2746
2747                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2748
2749                 udelay(1000);
2750         } else {
2751                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2752                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2753                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2754                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2755                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2756                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2757                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2758                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2759                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2760                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2761         }
2762
2763         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2764
2765         if (ah->ah_config.pcie_waen) {
2766                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2767         } else {
2768                 if (AR_SREV_9285(ah))
2769                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2770                 else if (AR_SREV_9280(ah))
2771                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2772                 else
2773                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2774         }
2775
2776 }
2777
2778 /**********************/
2779 /* Interrupt Handling */
2780 /**********************/
2781
2782 bool ath9k_hw_intrpend(struct ath_hal *ah)
2783 {
2784         u32 host_isr;
2785
2786         if (AR_SREV_9100(ah))
2787                 return true;
2788
2789         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2790         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2791                 return true;
2792
2793         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2794         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2795             && (host_isr != AR_INTR_SPURIOUS))
2796                 return true;
2797
2798         return false;
2799 }
2800
2801 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2802 {
2803         u32 isr = 0;
2804         u32 mask2 = 0;
2805         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2806         u32 sync_cause = 0;
2807         bool fatal_int = false;
2808         struct ath_hal_5416 *ahp = AH5416(ah);
2809
2810         if (!AR_SREV_9100(ah)) {
2811                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2812                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2813                             == AR_RTC_STATUS_ON) {
2814                                 isr = REG_READ(ah, AR_ISR);
2815                         }
2816                 }
2817
2818                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2819                         AR_INTR_SYNC_DEFAULT;
2820
2821                 *masked = 0;
2822
2823                 if (!isr && !sync_cause)
2824                         return false;
2825         } else {
2826                 *masked = 0;
2827                 isr = REG_READ(ah, AR_ISR);
2828         }
2829
2830         if (isr) {
2831                 if (isr & AR_ISR_BCNMISC) {
2832                         u32 isr2;
2833                         isr2 = REG_READ(ah, AR_ISR_S2);
2834                         if (isr2 & AR_ISR_S2_TIM)
2835                                 mask2 |= ATH9K_INT_TIM;
2836                         if (isr2 & AR_ISR_S2_DTIM)
2837                                 mask2 |= ATH9K_INT_DTIM;
2838                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2839                                 mask2 |= ATH9K_INT_DTIMSYNC;
2840                         if (isr2 & (AR_ISR_S2_CABEND))
2841                                 mask2 |= ATH9K_INT_CABEND;
2842                         if (isr2 & AR_ISR_S2_GTT)
2843                                 mask2 |= ATH9K_INT_GTT;
2844                         if (isr2 & AR_ISR_S2_CST)
2845                                 mask2 |= ATH9K_INT_CST;
2846                 }
2847
2848                 isr = REG_READ(ah, AR_ISR_RAC);
2849                 if (isr == 0xffffffff) {
2850                         *masked = 0;
2851                         return false;
2852                 }
2853
2854                 *masked = isr & ATH9K_INT_COMMON;
2855
2856                 if (ahp->ah_intrMitigation) {
2857                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2858                                 *masked |= ATH9K_INT_RX;
2859                 }
2860
2861                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2862                         *masked |= ATH9K_INT_RX;
2863                 if (isr &
2864                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2865                      AR_ISR_TXEOL)) {
2866                         u32 s0_s, s1_s;
2867
2868                         *masked |= ATH9K_INT_TX;
2869
2870                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2871                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2872                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2873
2874                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2875                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2876                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2877                 }
2878
2879                 if (isr & AR_ISR_RXORN) {
2880                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2881                                 "receive FIFO overrun interrupt\n");
2882                 }
2883
2884                 if (!AR_SREV_9100(ah)) {
2885                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2886                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2887                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2888                                         *masked |= ATH9K_INT_TIM_TIMER;
2889                         }
2890                 }
2891
2892                 *masked |= mask2;
2893         }
2894
2895         if (AR_SREV_9100(ah))
2896                 return true;
2897
2898         if (sync_cause) {
2899                 fatal_int =
2900                         (sync_cause &
2901                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2902                         ? true : false;
2903
2904                 if (fatal_int) {
2905                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2906                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2907                                         "received PCI FATAL interrupt\n");
2908                         }
2909                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2910                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2911                                         "received PCI PERR interrupt\n");
2912                         }
2913                 }
2914                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2915                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2916                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2917                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2918                         REG_WRITE(ah, AR_RC, 0);
2919                         *masked |= ATH9K_INT_FATAL;
2920                 }
2921                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2922                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2923                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2924                 }
2925
2926                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2927                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2928         }
2929
2930         return true;
2931 }
2932
2933 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2934 {
2935         return AH5416(ah)->ah_maskReg;
2936 }
2937
2938 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2939 {
2940         struct ath_hal_5416 *ahp = AH5416(ah);
2941         u32 omask = ahp->ah_maskReg;
2942         u32 mask, mask2;
2943         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2944
2945         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2946
2947         if (omask & ATH9K_INT_GLOBAL) {
2948                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2949                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2950                 (void) REG_READ(ah, AR_IER);
2951                 if (!AR_SREV_9100(ah)) {
2952                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2953                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2954
2955                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2956                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2957                 }
2958         }
2959
2960         mask = ints & ATH9K_INT_COMMON;
2961         mask2 = 0;
2962
2963         if (ints & ATH9K_INT_TX) {
2964                 if (ahp->ah_txOkInterruptMask)
2965                         mask |= AR_IMR_TXOK;
2966                 if (ahp->ah_txDescInterruptMask)
2967                         mask |= AR_IMR_TXDESC;
2968                 if (ahp->ah_txErrInterruptMask)
2969                         mask |= AR_IMR_TXERR;
2970                 if (ahp->ah_txEolInterruptMask)
2971                         mask |= AR_IMR_TXEOL;
2972         }
2973         if (ints & ATH9K_INT_RX) {
2974                 mask |= AR_IMR_RXERR;
2975                 if (ahp->ah_intrMitigation)
2976                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2977                 else
2978                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2979                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2980                         mask |= AR_IMR_GENTMR;
2981         }
2982
2983         if (ints & (ATH9K_INT_BMISC)) {
2984                 mask |= AR_IMR_BCNMISC;
2985                 if (ints & ATH9K_INT_TIM)
2986                         mask2 |= AR_IMR_S2_TIM;
2987                 if (ints & ATH9K_INT_DTIM)
2988                         mask2 |= AR_IMR_S2_DTIM;
2989                 if (ints & ATH9K_INT_DTIMSYNC)
2990                         mask2 |= AR_IMR_S2_DTIMSYNC;
2991                 if (ints & ATH9K_INT_CABEND)
2992                         mask2 |= (AR_IMR_S2_CABEND);
2993         }
2994
2995         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2996                 mask |= AR_IMR_BCNMISC;
2997                 if (ints & ATH9K_INT_GTT)
2998                         mask2 |= AR_IMR_S2_GTT;
2999                 if (ints & ATH9K_INT_CST)
3000                         mask2 |= AR_IMR_S2_CST;
3001         }
3002
3003         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3004         REG_WRITE(ah, AR_IMR, mask);
3005         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3006                                            AR_IMR_S2_DTIM |
3007                                            AR_IMR_S2_DTIMSYNC |
3008                                            AR_IMR_S2_CABEND |
3009                                            AR_IMR_S2_CABTO |
3010                                            AR_IMR_S2_TSFOOR |
3011                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3012         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3013         ahp->ah_maskReg = ints;
3014
3015         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3016                 if (ints & ATH9K_INT_TIM_TIMER)
3017                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3018                 else
3019                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3020         }
3021
3022         if (ints & ATH9K_INT_GLOBAL) {
3023                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3024                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3025                 if (!AR_SREV_9100(ah)) {
3026                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3027                                   AR_INTR_MAC_IRQ);
3028                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3029
3030
3031                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3032                                   AR_INTR_SYNC_DEFAULT);
3033                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3034                                   AR_INTR_SYNC_DEFAULT);
3035                 }
3036                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3037                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3038         }
3039
3040         return omask;
3041 }
3042
3043 /*******************/
3044 /* Beacon Handling */
3045 /*******************/
3046
3047 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3048 {
3049         struct ath_hal_5416 *ahp = AH5416(ah);
3050         int flags = 0;
3051
3052         ahp->ah_beaconInterval = beacon_period;
3053
3054         switch (ah->ah_opmode) {
3055         case NL80211_IFTYPE_STATION:
3056         case NL80211_IFTYPE_MONITOR:
3057                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3058                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3059                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3060                 flags |= AR_TBTT_TIMER_EN;
3061                 break;
3062         case NL80211_IFTYPE_ADHOC:
3063                 REG_SET_BIT(ah, AR_TXCFG,
3064                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3065                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3066                           TU_TO_USEC(next_beacon +
3067                                      (ahp->ah_atimWindow ? ahp->
3068                                       ah_atimWindow : 1)));
3069                 flags |= AR_NDP_TIMER_EN;
3070         case NL80211_IFTYPE_AP:
3071                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3072                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3073                           TU_TO_USEC(next_beacon -
3074                                      ah->ah_config.
3075                                      dma_beacon_response_time));
3076                 REG_WRITE(ah, AR_NEXT_SWBA,
3077                           TU_TO_USEC(next_beacon -
3078                                      ah->ah_config.
3079                                      sw_beacon_response_time));
3080                 flags |=
3081                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3082                 break;
3083         default:
3084                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3085                         "%s: unsupported opmode: %d\n",
3086                         __func__, ah->ah_opmode);
3087                 return;
3088                 break;
3089         }
3090
3091         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3092         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3093         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3094         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3095
3096         beacon_period &= ~ATH9K_BEACON_ENA;
3097         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3098                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3099                 ath9k_hw_reset_tsf(ah);
3100         }
3101
3102         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3103 }
3104
3105 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3106                                     const struct ath9k_beacon_state *bs)
3107 {
3108         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3109         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3110
3111         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3112
3113         REG_WRITE(ah, AR_BEACON_PERIOD,
3114                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3115         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3116                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3117
3118         REG_RMW_FIELD(ah, AR_RSSI_THR,
3119                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3120
3121         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3122
3123         if (bs->bs_sleepduration > beaconintval)
3124                 beaconintval = bs->bs_sleepduration;
3125
3126         dtimperiod = bs->bs_dtimperiod;
3127         if (bs->bs_sleepduration > dtimperiod)
3128                 dtimperiod = bs->bs_sleepduration;
3129
3130         if (beaconintval == dtimperiod)
3131                 nextTbtt = bs->bs_nextdtim;
3132         else
3133                 nextTbtt = bs->bs_nexttbtt;
3134
3135         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3136         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3137         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3138         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3139
3140         REG_WRITE(ah, AR_NEXT_DTIM,
3141                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3142         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3143
3144         REG_WRITE(ah, AR_SLEEP1,
3145                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3146                   | AR_SLEEP1_ASSUME_DTIM);
3147
3148         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3149                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3150         else
3151                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3152
3153         REG_WRITE(ah, AR_SLEEP2,
3154                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3155
3156         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3157         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3158
3159         REG_SET_BIT(ah, AR_TIMER_MODE,
3160                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3161                     AR_DTIM_TIMER_EN);
3162
3163 }
3164
3165 /*******************/
3166 /* HW Capabilities */
3167 /*******************/
3168
3169 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3170 {
3171         struct ath_hal_5416 *ahp = AH5416(ah);
3172         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3173         u16 capField = 0, eeval;
3174
3175         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3176
3177         ah->ah_currentRD = eeval;
3178
3179         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3180         ah->ah_currentRDExt = eeval;
3181
3182         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3183
3184         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3185             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3186                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3187                         ah->ah_currentRD += 5;
3188                 else if (ah->ah_currentRD == 0x41)
3189                         ah->ah_currentRD = 0x43;
3190                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3191                         "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3192         }
3193
3194         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3195         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3196
3197         if (eeval & AR5416_OPFLAGS_11A) {
3198                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3199                 if (ah->ah_config.ht_enable) {
3200                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3201                                 set_bit(ATH9K_MODE_11NA_HT20,
3202                                         pCap->wireless_modes);
3203                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3204                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3205                                         pCap->wireless_modes);
3206                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3207                                         pCap->wireless_modes);
3208                         }
3209                 }
3210         }
3211
3212         if (eeval & AR5416_OPFLAGS_11G) {
3213                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3214                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3215                 if (ah->ah_config.ht_enable) {
3216                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3217                                 set_bit(ATH9K_MODE_11NG_HT20,
3218                                         pCap->wireless_modes);
3219                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3220                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3221                                         pCap->wireless_modes);
3222                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3223                                         pCap->wireless_modes);
3224                         }
3225                 }
3226         }
3227
3228         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3229         if ((ah->ah_isPciExpress)
3230             || (eeval & AR5416_OPFLAGS_11A)) {
3231                 pCap->rx_chainmask =
3232                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3233         } else {
3234                 pCap->rx_chainmask =
3235                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3236         }
3237
3238         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3239                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3240
3241         pCap->low_2ghz_chan = 2312;
3242         pCap->high_2ghz_chan = 2732;
3243
3244         pCap->low_5ghz_chan = 4920;
3245         pCap->high_5ghz_chan = 6100;
3246
3247         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3248         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3249         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3250
3251         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3252         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3253         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3254
3255         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3256
3257         if (ah->ah_config.ht_enable)
3258                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3259         else
3260                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3261
3262         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3263         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3264         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3265         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3266
3267         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3268                 pCap->total_queues =
3269                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3270         else
3271                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3272
3273         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3274                 pCap->keycache_size =
3275                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3276         else
3277                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3278
3279         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3280         pCap->num_mr_retries = 4;
3281         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3282
3283         if (AR_SREV_9280_10_OR_LATER(ah))
3284                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3285         else
3286                 pCap->num_gpio_pins = AR_NUM_GPIO;
3287
3288         if (AR_SREV_9280_10_OR_LATER(ah)) {
3289                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3290                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3291         } else {
3292                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3293                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3294         }
3295
3296         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3297                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3298                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3299         } else {
3300                 pCap->rts_aggr_limit = (8 * 1024);
3301         }
3302
3303         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3304
3305 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3306         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3307         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3308                 ah->ah_rfkill_gpio =
3309                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3310                 ah->ah_rfkill_polarity =
3311                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3312
3313                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3314         }
3315 #endif
3316
3317         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3318             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3319             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3320             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3321             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3322                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3323         else
3324                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3325
3326         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3327                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3328         else
3329                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3330
3331         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3332                 pCap->reg_cap =
3333                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3334                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3335                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3336                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3337         } else {
3338                 pCap->reg_cap =
3339                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3340                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3341         }
3342
3343         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3344
3345         pCap->num_antcfg_5ghz =
3346                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3347         pCap->num_antcfg_2ghz =
3348                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3349
3350         return true;
3351 }
3352
3353 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3354                             u32 capability, u32 *result)
3355 {
3356         struct ath_hal_5416 *ahp = AH5416(ah);
3357         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3358
3359         switch (type) {
3360         case ATH9K_CAP_CIPHER:
3361                 switch (capability) {
3362                 case ATH9K_CIPHER_AES_CCM:
3363                 case ATH9K_CIPHER_AES_OCB:
3364                 case ATH9K_CIPHER_TKIP:
3365                 case ATH9K_CIPHER_WEP:
3366                 case ATH9K_CIPHER_MIC:
3367                 case ATH9K_CIPHER_CLR:
3368                         return true;
3369                 default:
3370                         return false;
3371                 }
3372         case ATH9K_CAP_TKIP_MIC:
3373                 switch (capability) {
3374                 case 0:
3375                         return true;
3376                 case 1:
3377                         return (ahp->ah_staId1Defaults &
3378                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3379                         false;
3380                 }
3381         case ATH9K_CAP_TKIP_SPLIT:
3382                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3383                         false : true;
3384         case ATH9K_CAP_WME_TKIPMIC:
3385                 return 0;
3386         case ATH9K_CAP_PHYCOUNTERS:
3387                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3388         case ATH9K_CAP_DIVERSITY:
3389                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3390                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3391                         true : false;
3392         case ATH9K_CAP_PHYDIAG:
3393                 return true;
3394         case ATH9K_CAP_MCAST_KEYSRCH:
3395                 switch (capability) {
3396                 case 0:
3397                         return true;
3398                 case 1:
3399                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3400                                 return false;
3401                         } else {
3402                                 return (ahp->ah_staId1Defaults &
3403                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3404                                         false;
3405                         }
3406                 }
3407                 return false;
3408         case ATH9K_CAP_TSF_ADJUST:
3409                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3410                         true : false;
3411         case ATH9K_CAP_RFSILENT:
3412                 if (capability == 3)
3413                         return false;
3414         case ATH9K_CAP_ANT_CFG_2GHZ:
3415                 *result = pCap->num_antcfg_2ghz;
3416                 return true;
3417         case ATH9K_CAP_ANT_CFG_5GHZ:
3418                 *result = pCap->num_antcfg_5ghz;
3419                 return true;
3420         case ATH9K_CAP_TXPOW:
3421                 switch (capability) {
3422                 case 0:
3423                         return 0;
3424                 case 1:
3425                         *result = ah->ah_powerLimit;
3426                         return 0;
3427                 case 2:
3428                         *result = ah->ah_maxPowerLevel;
3429                         return 0;
3430                 case 3:
3431                         *result = ah->ah_tpScale;
3432                         return 0;
3433                 }
3434                 return false;
3435         default:
3436                 return false;
3437         }
3438 }
3439
3440 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3441                             u32 capability, u32 setting, int *status)
3442 {
3443         struct ath_hal_5416 *ahp = AH5416(ah);
3444         u32 v;
3445
3446         switch (type) {
3447         case ATH9K_CAP_TKIP_MIC:
3448                 if (setting)
3449                         ahp->ah_staId1Defaults |=
3450                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3451                 else
3452                         ahp->ah_staId1Defaults &=
3453                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3454                 return true;
3455         case ATH9K_CAP_DIVERSITY:
3456                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3457                 if (setting)
3458                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3459                 else
3460                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3461                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3462                 return true;
3463         case ATH9K_CAP_MCAST_KEYSRCH:
3464                 if (setting)
3465                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3466                 else
3467                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3468                 return true;
3469         case ATH9K_CAP_TSF_ADJUST:
3470                 if (setting)
3471                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3472                 else
3473                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3474                 return true;
3475         default:
3476                 return false;
3477         }
3478 }
3479
3480 /****************************/
3481 /* GPIO / RFKILL / Antennae */
3482 /****************************/
3483
3484 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3485                                          u32 gpio, u32 type)
3486 {
3487         int addr;
3488         u32 gpio_shift, tmp;
3489
3490         if (gpio > 11)
3491                 addr = AR_GPIO_OUTPUT_MUX3;
3492         else if (gpio > 5)
3493                 addr = AR_GPIO_OUTPUT_MUX2;
3494         else
3495                 addr = AR_GPIO_OUTPUT_MUX1;
3496
3497         gpio_shift = (gpio % 6) * 5;
3498
3499         if (AR_SREV_9280_20_OR_LATER(ah)
3500             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3501                 REG_RMW(ah, addr, (type << gpio_shift),
3502                         (0x1f << gpio_shift));
3503         } else {
3504                 tmp = REG_READ(ah, addr);
3505                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3506                 tmp &= ~(0x1f << gpio_shift);
3507                 tmp |= (type << gpio_shift);
3508                 REG_WRITE(ah, addr, tmp);
3509         }
3510 }
3511
3512 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3513 {
3514         u32 gpio_shift;
3515
3516         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3517
3518         gpio_shift = gpio << 1;
3519
3520         REG_RMW(ah,
3521                 AR_GPIO_OE_OUT,
3522                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3523                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3524 }
3525
3526 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3527 {
3528         if (gpio >= ah->ah_caps.num_gpio_pins)
3529                 return 0xffffffff;
3530
3531         if (AR_SREV_9280_10_OR_LATER(ah)) {
3532                 return (MS
3533                         (REG_READ(ah, AR_GPIO_IN_OUT),
3534                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3535         } else {
3536                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3537                         AR_GPIO_BIT(gpio)) != 0;
3538         }
3539 }
3540
3541 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3542                          u32 ah_signal_type)
3543 {
3544         u32 gpio_shift;
3545
3546         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3547
3548         gpio_shift = 2 * gpio;
3549
3550         REG_RMW(ah,
3551                 AR_GPIO_OE_OUT,
3552                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3553                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3554 }
3555
3556 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3557 {
3558         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3559                 AR_GPIO_BIT(gpio));
3560 }
3561
3562 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3563 void ath9k_enable_rfkill(struct ath_hal *ah)
3564 {
3565         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3566                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3567
3568         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3569                     AR_GPIO_INPUT_MUX2_RFSILENT);
3570
3571         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3572         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3573 }
3574 #endif
3575
3576 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3577 {
3578         struct ath9k_channel *chan = ah->ah_curchan;
3579         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3580         u16 ant_config;
3581         u32 halNumAntConfig;
3582
3583         halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3584                 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3585
3586         if (cfg < halNumAntConfig) {
3587                 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3588                                                      cfg, &ant_config)) {
3589                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3590                         return 0;
3591                 }
3592         }
3593
3594         return -EINVAL;
3595 }
3596
3597 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3598 {
3599         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3600 }
3601
3602 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3603 {
3604         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3605 }
3606
3607 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3608                                enum ath9k_ant_setting settings,
3609                                struct ath9k_channel *chan,
3610                                u8 *tx_chainmask,
3611                                u8 *rx_chainmask,
3612                                u8 *antenna_cfgd)
3613 {
3614         struct ath_hal_5416 *ahp = AH5416(ah);
3615         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3616
3617         if (AR_SREV_9280(ah)) {
3618                 if (!tx_chainmask_cfg) {
3619
3620                         tx_chainmask_cfg = *tx_chainmask;
3621                         rx_chainmask_cfg = *rx_chainmask;
3622                 }
3623
3624                 switch (settings) {
3625                 case ATH9K_ANT_FIXED_A:
3626                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3627                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3628                         *antenna_cfgd = true;
3629                         break;
3630                 case ATH9K_ANT_FIXED_B:
3631                         if (ah->ah_caps.tx_chainmask >
3632                             ATH9K_ANTENNA1_CHAINMASK) {
3633                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3634                         }
3635                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3636                         *antenna_cfgd = true;
3637                         break;
3638                 case ATH9K_ANT_VARIABLE:
3639                         *tx_chainmask = tx_chainmask_cfg;
3640                         *rx_chainmask = rx_chainmask_cfg;
3641                         *antenna_cfgd = true;
3642                         break;
3643                 default:
3644                         break;
3645                 }
3646         } else {
3647                 ahp->ah_diversityControl = settings;
3648         }
3649
3650         return true;
3651 }
3652
3653 /*********************/
3654 /* General Operation */
3655 /*********************/
3656
3657 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3658 {
3659         u32 bits = REG_READ(ah, AR_RX_FILTER);
3660         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3661
3662         if (phybits & AR_PHY_ERR_RADAR)
3663                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3664         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3665                 bits |= ATH9K_RX_FILTER_PHYERR;
3666
3667         return bits;
3668 }
3669
3670 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3671 {
3672         u32 phybits;
3673
3674         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3675         phybits = 0;
3676         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3677                 phybits |= AR_PHY_ERR_RADAR;
3678         if (bits & ATH9K_RX_FILTER_PHYERR)
3679                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3680         REG_WRITE(ah, AR_PHY_ERR, phybits);
3681
3682         if (phybits)
3683                 REG_WRITE(ah, AR_RXCFG,
3684                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3685         else
3686                 REG_WRITE(ah, AR_RXCFG,
3687                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3688 }
3689
3690 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3691 {
3692         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3693 }
3694
3695 bool ath9k_hw_disable(struct ath_hal *ah)
3696 {
3697         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3698                 return false;
3699
3700         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3701 }
3702
3703 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3704 {
3705         struct ath9k_channel *chan = ah->ah_curchan;
3706
3707         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3708
3709         if (ath9k_hw_set_txpower(ah, chan,
3710                                  ath9k_regd_get_ctl(ah, chan),
3711                                  ath9k_regd_get_antenna_allowed(ah, chan),
3712                                  chan->maxRegTxPower * 2,
3713                                  min((u32) MAX_RATE_POWER,
3714                                      (u32) ah->ah_powerLimit)) != 0)
3715                 return false;
3716
3717         return true;
3718 }
3719
3720 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3721 {
3722         struct ath_hal_5416 *ahp = AH5416(ah);
3723
3724         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3725 }
3726
3727 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3728 {
3729         struct ath_hal_5416 *ahp = AH5416(ah);
3730
3731         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3732
3733         return true;
3734 }
3735
3736 void ath9k_hw_setopmode(struct ath_hal *ah)
3737 {
3738         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3739 }
3740
3741 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3742 {
3743         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3744         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3745 }
3746
3747 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3748 {
3749         struct ath_hal_5416 *ahp = AH5416(ah);
3750
3751         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3752 }
3753
3754 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3755 {
3756         struct ath_hal_5416 *ahp = AH5416(ah);
3757
3758         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3759
3760         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3761         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3762
3763         return true;
3764 }
3765
3766 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3767 {
3768         struct ath_hal_5416 *ahp = AH5416(ah);
3769
3770         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3771         ahp->ah_assocId = assocId;
3772
3773         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3774         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3775                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3776 }
3777
3778 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3779 {
3780         u64 tsf;
3781
3782         tsf = REG_READ(ah, AR_TSF_U32);
3783         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3784
3785         return tsf;
3786 }
3787
3788 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3789 {
3790         int count;
3791
3792         count = 0;
3793         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3794                 count++;
3795                 if (count > 10) {
3796                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3797                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3798                         break;
3799                 }
3800                 udelay(10);
3801         }
3802         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3803 }
3804
3805 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3806 {
3807         struct ath_hal_5416 *ahp = AH5416(ah);
3808
3809         if (setting)
3810                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3811         else
3812                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3813
3814         return true;
3815 }
3816
3817 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3818 {
3819         struct ath_hal_5416 *ahp = AH5416(ah);
3820
3821         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3822                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3823                 ahp->ah_slottime = (u32) -1;
3824                 return false;
3825         } else {
3826                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3827                 ahp->ah_slottime = us;
3828                 return true;
3829         }
3830 }
3831
3832 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3833 {
3834         u32 macmode;
3835
3836         if (mode == ATH9K_HT_MACMODE_2040 &&
3837             !ah->ah_config.cwm_ignore_extcca)
3838                 macmode = AR_2040_JOINED_RX_CLEAR;
3839         else
3840                 macmode = 0;
3841
3842         REG_WRITE(ah, AR_2040_MODE, macmode);
3843 }