ath9k: Enable dynamic power save in ath9k.
[pandora-kernel.git] / drivers / net / wireless / ath9k / hw.c
1 /*
2  * Copyright (c) 2008 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static int btcoex_enable;
27 module_param(btcoex_enable, bool, 0);
28 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
29
30 #define ATH9K_CLOCK_RATE_CCK            22
31 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
32 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
33
34 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
35 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
36                               enum ath9k_ht_macmode macmode);
37 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
38                               struct ar5416_eeprom_def *pEepData,
39                               u32 reg, u32 value);
40 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
41 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
42
43 /********************/
44 /* Helper Functions */
45 /********************/
46
47 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
48 {
49         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
50         if (!ah->ah_curchan) /* should really check for CCK instead */
51                 return clks / ATH9K_CLOCK_RATE_CCK;
52         if (conf->channel->band == IEEE80211_BAND_2GHZ)
53                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
54         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
55 }
56
57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58 {
59         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60         if (conf_is_ht40(conf))
61                 return ath9k_hw_mac_usec(ah, clks) / 2;
62         else
63                 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
67 {
68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69         if (!ah->ah_curchan) /* should really check for CCK instead */
70                 return usecs *ATH9K_CLOCK_RATE_CCK;
71         if (conf->channel->band == IEEE80211_BAND_2GHZ)
72                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
73         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
74 }
75
76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77 {
78         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
79         if (conf_is_ht40(conf))
80                 return ath9k_hw_mac_clks(ah, usecs) * 2;
81         else
82                 return ath9k_hw_mac_clks(ah, usecs);
83 }
84
85 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
86 {
87         int i;
88
89         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
90                 if ((REG_READ(ah, reg) & mask) == val)
91                         return true;
92
93                 udelay(AH_TIME_QUANTUM);
94         }
95
96         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
97                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
98                 reg, REG_READ(ah, reg), mask, val);
99
100         return false;
101 }
102
103 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
104 {
105         u32 retval;
106         int i;
107
108         for (i = 0, retval = 0; i < n; i++) {
109                 retval = (retval << 1) | (val & 1);
110                 val >>= 1;
111         }
112         return retval;
113 }
114
115 bool ath9k_get_channel_edges(struct ath_hal *ah,
116                              u16 flags, u16 *low,
117                              u16 *high)
118 {
119         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
120
121         if (flags & CHANNEL_5GHZ) {
122                 *low = pCap->low_5ghz_chan;
123                 *high = pCap->high_5ghz_chan;
124                 return true;
125         }
126         if ((flags & CHANNEL_2GHZ)) {
127                 *low = pCap->low_2ghz_chan;
128                 *high = pCap->high_2ghz_chan;
129                 return true;
130         }
131         return false;
132 }
133
134 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
135                            struct ath_rate_table *rates,
136                            u32 frameLen, u16 rateix,
137                            bool shortPreamble)
138 {
139         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
140         u32 kbps;
141
142         kbps = rates->info[rateix].ratekbps;
143
144         if (kbps == 0)
145                 return 0;
146
147         switch (rates->info[rateix].phy) {
148         case WLAN_RC_PHY_CCK:
149                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
150                 if (shortPreamble && rates->info[rateix].short_preamble)
151                         phyTime >>= 1;
152                 numBits = frameLen << 3;
153                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154                 break;
155         case WLAN_RC_PHY_OFDM:
156                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
157                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
159                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160                         txTime = OFDM_SIFS_TIME_QUARTER
161                                 + OFDM_PREAMBLE_TIME_QUARTER
162                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163                 } else if (ah->ah_curchan &&
164                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
165                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
167                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168                         txTime = OFDM_SIFS_TIME_HALF +
169                                 OFDM_PREAMBLE_TIME_HALF
170                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171                 } else {
172                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
174                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176                                 + (numSymbols * OFDM_SYMBOL_TIME);
177                 }
178                 break;
179         default:
180                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
181                         "Unknown phy %u (rate ix %u)\n",
182                         rates->info[rateix].phy, rateix);
183                 txTime = 0;
184                 break;
185         }
186
187         return txTime;
188 }
189
190 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
191 {
192         if (flags & CHANNEL_2GHZ) {
193                 if (freq == 2484)
194                         return 14;
195                 if (freq < 2484)
196                         return (freq - 2407) / 5;
197                 else
198                         return 15 + ((freq - 2512) / 20);
199         } else if (flags & CHANNEL_5GHZ) {
200                 if (ath9k_regd_is_public_safety_sku(ah) &&
201                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
202                         return ((freq * 10) +
203                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
204                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
205                         return (freq - 4000) / 5;
206                 } else {
207                         return (freq - 5000) / 5;
208                 }
209         } else {
210                 if (freq == 2484)
211                         return 14;
212                 if (freq < 2484)
213                         return (freq - 2407) / 5;
214                 if (freq < 5000) {
215                         if (ath9k_regd_is_public_safety_sku(ah)
216                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
217                                 return ((freq * 10) +
218                                         (((freq % 5) ==
219                                           2) ? 5 : 0) - 49400) / 5;
220                         } else if (freq > 4900) {
221                                 return (freq - 4000) / 5;
222                         } else {
223                                 return 15 + ((freq - 2512) / 20);
224                         }
225                 }
226                 return (freq - 5000) / 5;
227         }
228 }
229
230 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
231                                   struct ath9k_channel *chan,
232                                   struct chan_centers *centers)
233 {
234         int8_t extoff;
235         struct ath_hal_5416 *ahp = AH5416(ah);
236
237         if (!IS_CHAN_HT40(chan)) {
238                 centers->ctl_center = centers->ext_center =
239                         centers->synth_center = chan->channel;
240                 return;
241         }
242
243         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
244             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
245                 centers->synth_center =
246                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
247                 extoff = 1;
248         } else {
249                 centers->synth_center =
250                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
251                 extoff = -1;
252         }
253
254         centers->ctl_center =
255                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
256         centers->ext_center =
257                 centers->synth_center + (extoff *
258                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
259                           HT40_CHANNEL_CENTER_SHIFT : 15));
260
261 }
262
263 /******************/
264 /* Chip Revisions */
265 /******************/
266
267 static void ath9k_hw_read_revisions(struct ath_hal *ah)
268 {
269         u32 val;
270
271         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
272
273         if (val == 0xFF) {
274                 val = REG_READ(ah, AR_SREV);
275                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
276                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
277                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
278         } else {
279                 if (!AR_SREV_9100(ah))
280                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
281
282                 ah->ah_macRev = val & AR_SREV_REVISION;
283
284                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
285                         ah->ah_isPciExpress = true;
286         }
287 }
288
289 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
290 {
291         u32 val;
292         int i;
293
294         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
295
296         for (i = 0; i < 8; i++)
297                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
298         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
299         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
300
301         return ath9k_hw_reverse_bits(val, 8);
302 }
303
304 /************************************/
305 /* HW Attach, Detach, Init Routines */
306 /************************************/
307
308 static void ath9k_hw_disablepcie(struct ath_hal *ah)
309 {
310         if (!AR_SREV_9100(ah))
311                 return;
312
313         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
314         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
315         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
316         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
317         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
318         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
319         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
320         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
321         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
322
323         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
324 }
325
326 static bool ath9k_hw_chip_test(struct ath_hal *ah)
327 {
328         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
329         u32 regHold[2];
330         u32 patternData[4] = { 0x55555555,
331                                0xaaaaaaaa,
332                                0x66666666,
333                                0x99999999 };
334         int i, j;
335
336         for (i = 0; i < 2; i++) {
337                 u32 addr = regAddr[i];
338                 u32 wrData, rdData;
339
340                 regHold[i] = REG_READ(ah, addr);
341                 for (j = 0; j < 0x100; j++) {
342                         wrData = (j << 16) | j;
343                         REG_WRITE(ah, addr, wrData);
344                         rdData = REG_READ(ah, addr);
345                         if (rdData != wrData) {
346                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
347                                         "address test failed "
348                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
349                                         addr, wrData, rdData);
350                                 return false;
351                         }
352                 }
353                 for (j = 0; j < 4; j++) {
354                         wrData = patternData[j];
355                         REG_WRITE(ah, addr, wrData);
356                         rdData = REG_READ(ah, addr);
357                         if (wrData != rdData) {
358                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
359                                         "address test failed "
360                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
361                                         addr, wrData, rdData);
362                                 return false;
363                         }
364                 }
365                 REG_WRITE(ah, regAddr[i], regHold[i]);
366         }
367         udelay(100);
368         return true;
369 }
370
371 static const char *ath9k_hw_devname(u16 devid)
372 {
373         switch (devid) {
374         case AR5416_DEVID_PCI:
375                 return "Atheros 5416";
376         case AR5416_DEVID_PCIE:
377                 return "Atheros 5418";
378         case AR9160_DEVID_PCI:
379                 return "Atheros 9160";
380         case AR5416_AR9100_DEVID:
381                 return "Atheros 9100";
382         case AR9280_DEVID_PCI:
383         case AR9280_DEVID_PCIE:
384                 return "Atheros 9280";
385         case AR9285_DEVID_PCIE:
386                 return "Atheros 9285";
387         }
388
389         return NULL;
390 }
391
392 static void ath9k_hw_set_defaults(struct ath_hal *ah)
393 {
394         int i;
395
396         ah->ah_config.dma_beacon_response_time = 2;
397         ah->ah_config.sw_beacon_response_time = 10;
398         ah->ah_config.additional_swba_backoff = 0;
399         ah->ah_config.ack_6mb = 0x0;
400         ah->ah_config.cwm_ignore_extcca = 0;
401         ah->ah_config.pcie_powersave_enable = 0;
402         ah->ah_config.pcie_l1skp_enable = 0;
403         ah->ah_config.pcie_clock_req = 0;
404         ah->ah_config.pcie_power_reset = 0x100;
405         ah->ah_config.pcie_restore = 0;
406         ah->ah_config.pcie_waen = 0;
407         ah->ah_config.analog_shiftreg = 1;
408         ah->ah_config.ht_enable = 1;
409         ah->ah_config.ofdm_trig_low = 200;
410         ah->ah_config.ofdm_trig_high = 500;
411         ah->ah_config.cck_trig_high = 200;
412         ah->ah_config.cck_trig_low = 100;
413         ah->ah_config.enable_ani = 1;
414         ah->ah_config.noise_immunity_level = 4;
415         ah->ah_config.ofdm_weaksignal_det = 1;
416         ah->ah_config.cck_weaksignal_thr = 0;
417         ah->ah_config.spur_immunity_level = 2;
418         ah->ah_config.firstep_level = 0;
419         ah->ah_config.rssi_thr_high = 40;
420         ah->ah_config.rssi_thr_low = 7;
421         ah->ah_config.diversity_control = 0;
422         ah->ah_config.antenna_switch_swap = 0;
423
424         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
425                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
426                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
427         }
428
429         ah->ah_config.intr_mitigation = 1;
430 }
431
432 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
433                                               struct ath_softc *sc,
434                                               void __iomem *mem,
435                                               int *status)
436 {
437         static const u8 defbssidmask[ETH_ALEN] =
438                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
439         struct ath_hal_5416 *ahp;
440         struct ath_hal *ah;
441
442         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
443         if (ahp == NULL) {
444                 DPRINTF(sc, ATH_DBG_FATAL,
445                         "Cannot allocate memory for state block\n");
446                 *status = -ENOMEM;
447                 return NULL;
448         }
449
450         ah = &ahp->ah;
451         ah->ah_sc = sc;
452         ah->ah_sh = mem;
453         ah->ah_magic = AR5416_MAGIC;
454         ah->ah_countryCode = CTRY_DEFAULT;
455         ah->ah_devid = devid;
456         ah->ah_subvendorid = 0;
457
458         ah->ah_flags = 0;
459         if ((devid == AR5416_AR9100_DEVID))
460                 ah->ah_macVersion = AR_SREV_VERSION_9100;
461         if (!AR_SREV_9100(ah))
462                 ah->ah_flags = AH_USE_EEPROM;
463
464         ah->ah_powerLimit = MAX_RATE_POWER;
465         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
466         ahp->ah_atimWindow = 0;
467         ahp->ah_diversityControl = ah->ah_config.diversity_control;
468         ahp->ah_antennaSwitchSwap =
469                 ah->ah_config.antenna_switch_swap;
470         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
471         ahp->ah_beaconInterval = 100;
472         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
473         ahp->ah_slottime = (u32) -1;
474         ahp->ah_acktimeout = (u32) -1;
475         ahp->ah_ctstimeout = (u32) -1;
476         ahp->ah_globaltxtimeout = (u32) -1;
477         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
478
479         ahp->ah_gBeaconRate = 0;
480
481         return ahp;
482 }
483
484 static int ath9k_hw_rfattach(struct ath_hal *ah)
485 {
486         bool rfStatus = false;
487         int ecode = 0;
488
489         rfStatus = ath9k_hw_init_rf(ah, &ecode);
490         if (!rfStatus) {
491                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
492                         "RF setup failed, status %u\n", ecode);
493                 return ecode;
494         }
495
496         return 0;
497 }
498
499 static int ath9k_hw_rf_claim(struct ath_hal *ah)
500 {
501         u32 val;
502
503         REG_WRITE(ah, AR_PHY(0), 0x00000007);
504
505         val = ath9k_hw_get_radiorev(ah);
506         switch (val & AR_RADIO_SREV_MAJOR) {
507         case 0:
508                 val = AR_RAD5133_SREV_MAJOR;
509                 break;
510         case AR_RAD5133_SREV_MAJOR:
511         case AR_RAD5122_SREV_MAJOR:
512         case AR_RAD2133_SREV_MAJOR:
513         case AR_RAD2122_SREV_MAJOR:
514                 break;
515         default:
516                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
517                         "5G Radio Chip Rev 0x%02X is not "
518                         "supported by this driver\n",
519                         ah->ah_analog5GhzRev);
520                 return -EOPNOTSUPP;
521         }
522
523         ah->ah_analog5GhzRev = val;
524
525         return 0;
526 }
527
528 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
529 {
530         u32 sum;
531         int i;
532         u16 eeval;
533         struct ath_hal_5416 *ahp = AH5416(ah);
534
535         sum = 0;
536         for (i = 0; i < 3; i++) {
537                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
538                 sum += eeval;
539                 ahp->ah_macaddr[2 * i] = eeval >> 8;
540                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
541         }
542         if (sum == 0 || sum == 0xffff * 3) {
543                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
544                         "mac address read failed: %pM\n",
545                         ahp->ah_macaddr);
546                 return -EADDRNOTAVAIL;
547         }
548
549         return 0;
550 }
551
552 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
553 {
554         u32 rxgain_type;
555         struct ath_hal_5416 *ahp = AH5416(ah);
556
557         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
558                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
559
560                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
561                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
562                         ar9280Modes_backoff_13db_rxgain_9280_2,
563                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
564                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
565                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
566                         ar9280Modes_backoff_23db_rxgain_9280_2,
567                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
568                 else
569                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
570                         ar9280Modes_original_rxgain_9280_2,
571                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
572         } else
573                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
574                         ar9280Modes_original_rxgain_9280_2,
575                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
576 }
577
578 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
579 {
580         u32 txgain_type;
581         struct ath_hal_5416 *ahp = AH5416(ah);
582
583         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
584                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
585
586                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
587                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
588                         ar9280Modes_high_power_tx_gain_9280_2,
589                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
590                 else
591                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
592                         ar9280Modes_original_tx_gain_9280_2,
593                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
594         } else
595                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
596                 ar9280Modes_original_tx_gain_9280_2,
597                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
598 }
599
600 static int ath9k_hw_post_attach(struct ath_hal *ah)
601 {
602         int ecode;
603
604         if (!ath9k_hw_chip_test(ah)) {
605                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
606                         "hardware self-test failed\n");
607                 return -ENODEV;
608         }
609
610         ecode = ath9k_hw_rf_claim(ah);
611         if (ecode != 0)
612                 return ecode;
613
614         ecode = ath9k_hw_eeprom_attach(ah);
615         if (ecode != 0)
616                 return ecode;
617         ecode = ath9k_hw_rfattach(ah);
618         if (ecode != 0)
619                 return ecode;
620
621         if (!AR_SREV_9100(ah)) {
622                 ath9k_hw_ani_setup(ah);
623                 ath9k_hw_ani_attach(ah);
624         }
625
626         return 0;
627 }
628
629 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
630                                           void __iomem *mem, int *status)
631 {
632         struct ath_hal_5416 *ahp;
633         struct ath_hal *ah;
634         int ecode;
635         u32 i, j;
636
637         ahp = ath9k_hw_newstate(devid, sc, mem, status);
638         if (ahp == NULL)
639                 return NULL;
640
641         ah = &ahp->ah;
642
643         ath9k_hw_set_defaults(ah);
644
645         if (ah->ah_config.intr_mitigation != 0)
646                 ahp->ah_intrMitigation = true;
647
648         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
649                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
650                 ecode = -EIO;
651                 goto bad;
652         }
653
654         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
655                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
656                 ecode = -EIO;
657                 goto bad;
658         }
659
660         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
661                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
662                         ah->ah_config.serialize_regmode =
663                                 SER_REG_MODE_ON;
664                 } else {
665                         ah->ah_config.serialize_regmode =
666                                 SER_REG_MODE_OFF;
667                 }
668         }
669
670         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
671                 "serialize_regmode is %d\n",
672                 ah->ah_config.serialize_regmode);
673
674         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
675             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
676             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
677             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
678                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
679                         "Mac Chip Rev 0x%02x.%x is not supported by "
680                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
681                 ecode = -EOPNOTSUPP;
682                 goto bad;
683         }
684
685         if (AR_SREV_9100(ah)) {
686                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
687                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
688                 ah->ah_isPciExpress = false;
689         }
690         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
691
692         if (AR_SREV_9160_10_OR_LATER(ah)) {
693                 if (AR_SREV_9280_10_OR_LATER(ah)) {
694                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
695                         ahp->ah_adcGainCalData.calData =
696                                 &adc_gain_cal_single_sample;
697                         ahp->ah_adcDcCalData.calData =
698                                 &adc_dc_cal_single_sample;
699                         ahp->ah_adcDcCalInitData.calData =
700                                 &adc_init_dc_cal;
701                 } else {
702                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
703                         ahp->ah_adcGainCalData.calData =
704                                 &adc_gain_cal_multi_sample;
705                         ahp->ah_adcDcCalData.calData =
706                                 &adc_dc_cal_multi_sample;
707                         ahp->ah_adcDcCalInitData.calData =
708                                 &adc_init_dc_cal;
709                 }
710                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
711         }
712
713         if (AR_SREV_9160(ah)) {
714                 ah->ah_config.enable_ani = 1;
715                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
716                                         ATH9K_ANI_FIRSTEP_LEVEL);
717         } else {
718                 ahp->ah_ani_function = ATH9K_ANI_ALL;
719                 if (AR_SREV_9280_10_OR_LATER(ah)) {
720                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
721                 }
722         }
723
724         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
725                 "This Mac Chip Rev 0x%02x.%x is \n",
726                 ah->ah_macVersion, ah->ah_macRev);
727
728         if (AR_SREV_9285_12_OR_LATER(ah)) {
729                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
730                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
731                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
732                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
733
734                 if (ah->ah_config.pcie_clock_req) {
735                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
736                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
737                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
738                 } else {
739                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
740                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
741                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
742                                   2);
743                 }
744         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
745                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
746                                ARRAY_SIZE(ar9285Modes_9285), 6);
747                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
748                                ARRAY_SIZE(ar9285Common_9285), 2);
749
750                 if (ah->ah_config.pcie_clock_req) {
751                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
752                         ar9285PciePhy_clkreq_off_L1_9285,
753                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
754                 } else {
755                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
756                         ar9285PciePhy_clkreq_always_on_L1_9285,
757                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
758                 }
759         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
760                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
761                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
762                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
763                                ARRAY_SIZE(ar9280Common_9280_2), 2);
764
765                 if (ah->ah_config.pcie_clock_req) {
766                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
767                                ar9280PciePhy_clkreq_off_L1_9280,
768                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
769                 } else {
770                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
771                                ar9280PciePhy_clkreq_always_on_L1_9280,
772                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
773                 }
774                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
775                                ar9280Modes_fast_clock_9280_2,
776                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
777         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
778                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
779                                ARRAY_SIZE(ar9280Modes_9280), 6);
780                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
781                                ARRAY_SIZE(ar9280Common_9280), 2);
782         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
783                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
784                                ARRAY_SIZE(ar5416Modes_9160), 6);
785                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
786                                ARRAY_SIZE(ar5416Common_9160), 2);
787                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
788                                ARRAY_SIZE(ar5416Bank0_9160), 2);
789                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
790                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
791                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
792                                ARRAY_SIZE(ar5416Bank1_9160), 2);
793                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
794                                ARRAY_SIZE(ar5416Bank2_9160), 2);
795                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
796                                ARRAY_SIZE(ar5416Bank3_9160), 3);
797                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
798                                ARRAY_SIZE(ar5416Bank6_9160), 3);
799                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
800                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
801                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
802                                ARRAY_SIZE(ar5416Bank7_9160), 2);
803                 if (AR_SREV_9160_11(ah)) {
804                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
805                                        ar5416Addac_91601_1,
806                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
807                 } else {
808                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
809                                        ARRAY_SIZE(ar5416Addac_9160), 2);
810                 }
811         } else if (AR_SREV_9100_OR_LATER(ah)) {
812                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
813                                ARRAY_SIZE(ar5416Modes_9100), 6);
814                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
815                                ARRAY_SIZE(ar5416Common_9100), 2);
816                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
817                                ARRAY_SIZE(ar5416Bank0_9100), 2);
818                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
819                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
820                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
821                                ARRAY_SIZE(ar5416Bank1_9100), 2);
822                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
823                                ARRAY_SIZE(ar5416Bank2_9100), 2);
824                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
825                                ARRAY_SIZE(ar5416Bank3_9100), 3);
826                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
827                                ARRAY_SIZE(ar5416Bank6_9100), 3);
828                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
829                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
830                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
831                                ARRAY_SIZE(ar5416Bank7_9100), 2);
832                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
833                                ARRAY_SIZE(ar5416Addac_9100), 2);
834         } else {
835                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
836                                ARRAY_SIZE(ar5416Modes), 6);
837                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
838                                ARRAY_SIZE(ar5416Common), 2);
839                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
840                                ARRAY_SIZE(ar5416Bank0), 2);
841                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
842                                ARRAY_SIZE(ar5416BB_RfGain), 3);
843                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
844                                ARRAY_SIZE(ar5416Bank1), 2);
845                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
846                                ARRAY_SIZE(ar5416Bank2), 2);
847                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
848                                ARRAY_SIZE(ar5416Bank3), 3);
849                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
850                                ARRAY_SIZE(ar5416Bank6), 3);
851                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
852                                ARRAY_SIZE(ar5416Bank6TPC), 3);
853                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
854                                ARRAY_SIZE(ar5416Bank7), 2);
855                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
856                                ARRAY_SIZE(ar5416Addac), 2);
857         }
858
859         if (ah->ah_isPciExpress)
860                 ath9k_hw_configpcipowersave(ah, 0);
861         else
862                 ath9k_hw_disablepcie(ah);
863
864         ecode = ath9k_hw_post_attach(ah);
865         if (ecode != 0)
866                 goto bad;
867
868         /* rxgain table */
869         if (AR_SREV_9280_20(ah))
870                 ath9k_hw_init_rxgain_ini(ah);
871
872         /* txgain table */
873         if (AR_SREV_9280_20(ah))
874                 ath9k_hw_init_txgain_ini(ah);
875
876         if (ah->ah_devid == AR9280_DEVID_PCI) {
877                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
878                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
879
880                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
881                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
882
883                                 INI_RA(&ahp->ah_iniModes, i, j) =
884                                         ath9k_hw_ini_fixup(ah,
885                                                            &ahp->ah_eeprom.def,
886                                                            reg, val);
887                         }
888                 }
889         }
890
891         if (!ath9k_hw_fill_cap_info(ah)) {
892                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
893                         "failed ath9k_hw_fill_cap_info\n");
894                 ecode = -EINVAL;
895                 goto bad;
896         }
897
898         ecode = ath9k_hw_init_macaddr(ah);
899         if (ecode != 0) {
900                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
901                         "failed initializing mac address\n");
902                 goto bad;
903         }
904
905         if (AR_SREV_9285(ah))
906                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
907         else
908                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
909
910         ath9k_init_nfcal_hist_buffer(ah);
911
912         return ah;
913 bad:
914         if (ahp)
915                 ath9k_hw_detach((struct ath_hal *) ahp);
916         if (status)
917                 *status = ecode;
918
919         return NULL;
920 }
921
922 static void ath9k_hw_init_bb(struct ath_hal *ah,
923                              struct ath9k_channel *chan)
924 {
925         u32 synthDelay;
926
927         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
928         if (IS_CHAN_B(chan))
929                 synthDelay = (4 * synthDelay) / 22;
930         else
931                 synthDelay /= 10;
932
933         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
934
935         udelay(synthDelay + BASE_ACTIVATE_DELAY);
936 }
937
938 static void ath9k_hw_init_qos(struct ath_hal *ah)
939 {
940         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
941         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
942
943         REG_WRITE(ah, AR_QOS_NO_ACK,
944                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
945                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
946                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
947
948         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
949         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
950         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
951         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
952         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
953 }
954
955 static void ath9k_hw_init_pll(struct ath_hal *ah,
956                               struct ath9k_channel *chan)
957 {
958         u32 pll;
959
960         if (AR_SREV_9100(ah)) {
961                 if (chan && IS_CHAN_5GHZ(chan))
962                         pll = 0x1450;
963                 else
964                         pll = 0x1458;
965         } else {
966                 if (AR_SREV_9280_10_OR_LATER(ah)) {
967                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
968
969                         if (chan && IS_CHAN_HALF_RATE(chan))
970                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
971                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
972                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
973
974                         if (chan && IS_CHAN_5GHZ(chan)) {
975                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
976
977
978                                 if (AR_SREV_9280_20(ah)) {
979                                         if (((chan->channel % 20) == 0)
980                                             || ((chan->channel % 10) == 0))
981                                                 pll = 0x2850;
982                                         else
983                                                 pll = 0x142c;
984                                 }
985                         } else {
986                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
987                         }
988
989                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
990
991                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
992
993                         if (chan && IS_CHAN_HALF_RATE(chan))
994                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
995                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
996                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
997
998                         if (chan && IS_CHAN_5GHZ(chan))
999                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1000                         else
1001                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1002                 } else {
1003                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1004
1005                         if (chan && IS_CHAN_HALF_RATE(chan))
1006                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1007                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1008                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1009
1010                         if (chan && IS_CHAN_5GHZ(chan))
1011                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1012                         else
1013                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1014                 }
1015         }
1016         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1017
1018         udelay(RTC_PLL_SETTLE_DELAY);
1019
1020         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1021 }
1022
1023 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1024 {
1025         struct ath_hal_5416 *ahp = AH5416(ah);
1026         int rx_chainmask, tx_chainmask;
1027
1028         rx_chainmask = ahp->ah_rxchainmask;
1029         tx_chainmask = ahp->ah_txchainmask;
1030
1031         switch (rx_chainmask) {
1032         case 0x5:
1033                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1034                             AR_PHY_SWAP_ALT_CHAIN);
1035         case 0x3:
1036                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1037                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1038                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1039                         break;
1040                 }
1041         case 0x1:
1042         case 0x2:
1043         case 0x7:
1044                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1045                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1046                 break;
1047         default:
1048                 break;
1049         }
1050
1051         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1052         if (tx_chainmask == 0x5) {
1053                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1054                             AR_PHY_SWAP_ALT_CHAIN);
1055         }
1056         if (AR_SREV_9100(ah))
1057                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1058                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1059 }
1060
1061 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1062                                           enum nl80211_iftype opmode)
1063 {
1064         struct ath_hal_5416 *ahp = AH5416(ah);
1065
1066         ahp->ah_maskReg = AR_IMR_TXERR |
1067                 AR_IMR_TXURN |
1068                 AR_IMR_RXERR |
1069                 AR_IMR_RXORN |
1070                 AR_IMR_BCNMISC;
1071
1072         if (ahp->ah_intrMitigation)
1073                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1074         else
1075                 ahp->ah_maskReg |= AR_IMR_RXOK;
1076
1077         ahp->ah_maskReg |= AR_IMR_TXOK;
1078
1079         if (opmode == NL80211_IFTYPE_AP)
1080                 ahp->ah_maskReg |= AR_IMR_MIB;
1081
1082         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1083         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1084
1085         if (!AR_SREV_9100(ah)) {
1086                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1087                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1088                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1089         }
1090 }
1091
1092 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1093 {
1094         struct ath_hal_5416 *ahp = AH5416(ah);
1095
1096         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1097                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1098                 ahp->ah_acktimeout = (u32) -1;
1099                 return false;
1100         } else {
1101                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1102                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1103                 ahp->ah_acktimeout = us;
1104                 return true;
1105         }
1106 }
1107
1108 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1109 {
1110         struct ath_hal_5416 *ahp = AH5416(ah);
1111
1112         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1113                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1114                 ahp->ah_ctstimeout = (u32) -1;
1115                 return false;
1116         } else {
1117                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1118                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1119                 ahp->ah_ctstimeout = us;
1120                 return true;
1121         }
1122 }
1123
1124 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1125 {
1126         struct ath_hal_5416 *ahp = AH5416(ah);
1127
1128         if (tu > 0xFFFF) {
1129                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1130                         "bad global tx timeout %u\n", tu);
1131                 ahp->ah_globaltxtimeout = (u32) -1;
1132                 return false;
1133         } else {
1134                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1135                 ahp->ah_globaltxtimeout = tu;
1136                 return true;
1137         }
1138 }
1139
1140 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1141 {
1142         struct ath_hal_5416 *ahp = AH5416(ah);
1143
1144         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1145                 ahp->ah_miscMode);
1146
1147         if (ahp->ah_miscMode != 0)
1148                 REG_WRITE(ah, AR_PCU_MISC,
1149                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1150         if (ahp->ah_slottime != (u32) -1)
1151                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1152         if (ahp->ah_acktimeout != (u32) -1)
1153                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1154         if (ahp->ah_ctstimeout != (u32) -1)
1155                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1156         if (ahp->ah_globaltxtimeout != (u32) -1)
1157                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1158 }
1159
1160 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1161 {
1162         return vendorid == ATHEROS_VENDOR_ID ?
1163                 ath9k_hw_devname(devid) : NULL;
1164 }
1165
1166 void ath9k_hw_detach(struct ath_hal *ah)
1167 {
1168         if (!AR_SREV_9100(ah))
1169                 ath9k_hw_ani_detach(ah);
1170
1171         ath9k_hw_rfdetach(ah);
1172         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1173         kfree(ah);
1174 }
1175
1176 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1177                                 void __iomem *mem, int *error)
1178 {
1179         struct ath_hal *ah = NULL;
1180
1181         switch (devid) {
1182         case AR5416_DEVID_PCI:
1183         case AR5416_DEVID_PCIE:
1184         case AR5416_AR9100_DEVID:
1185         case AR9160_DEVID_PCI:
1186         case AR9280_DEVID_PCI:
1187         case AR9280_DEVID_PCIE:
1188         case AR9285_DEVID_PCIE:
1189                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1190                 break;
1191         default:
1192                 *error = -ENXIO;
1193                 break;
1194         }
1195
1196         return ah;
1197 }
1198
1199 /*******/
1200 /* INI */
1201 /*******/
1202
1203 static void ath9k_hw_override_ini(struct ath_hal *ah,
1204                                   struct ath9k_channel *chan)
1205 {
1206         /*
1207          * Set the RX_ABORT and RX_DIS and clear if off only after
1208          * RXE is set for MAC. This prevents frames with corrupted
1209          * descriptor status.
1210          */
1211         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1212
1213
1214         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1215             AR_SREV_9280_10_OR_LATER(ah))
1216                 return;
1217
1218         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1219 }
1220
1221 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1222                               struct ar5416_eeprom_def *pEepData,
1223                               u32 reg, u32 value)
1224 {
1225         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1226
1227         switch (ah->ah_devid) {
1228         case AR9280_DEVID_PCI:
1229                 if (reg == 0x7894) {
1230                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1231                                 "ini VAL: %x  EEPROM: %x\n", value,
1232                                 (pBase->version & 0xff));
1233
1234                         if ((pBase->version & 0xff) > 0x0a) {
1235                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1236                                         "PWDCLKIND: %d\n",
1237                                         pBase->pwdclkind);
1238                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1239                                 value |= AR_AN_TOP2_PWDCLKIND &
1240                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1241                         } else {
1242                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1243                                         "PWDCLKIND Earlier Rev\n");
1244                         }
1245
1246                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1247                                 "final ini VAL: %x\n", value);
1248                 }
1249                 break;
1250         }
1251
1252         return value;
1253 }
1254
1255 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1256                               struct ar5416_eeprom_def *pEepData,
1257                               u32 reg, u32 value)
1258 {
1259         struct ath_hal_5416 *ahp = AH5416(ah);
1260
1261         if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1262                 return value;
1263         else
1264                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1265 }
1266
1267 static int ath9k_hw_process_ini(struct ath_hal *ah,
1268                                 struct ath9k_channel *chan,
1269                                 enum ath9k_ht_macmode macmode)
1270 {
1271         int i, regWrites = 0;
1272         struct ath_hal_5416 *ahp = AH5416(ah);
1273         u32 modesIndex, freqIndex;
1274         int status;
1275
1276         switch (chan->chanmode) {
1277         case CHANNEL_A:
1278         case CHANNEL_A_HT20:
1279                 modesIndex = 1;
1280                 freqIndex = 1;
1281                 break;
1282         case CHANNEL_A_HT40PLUS:
1283         case CHANNEL_A_HT40MINUS:
1284                 modesIndex = 2;
1285                 freqIndex = 1;
1286                 break;
1287         case CHANNEL_G:
1288         case CHANNEL_G_HT20:
1289         case CHANNEL_B:
1290                 modesIndex = 4;
1291                 freqIndex = 2;
1292                 break;
1293         case CHANNEL_G_HT40PLUS:
1294         case CHANNEL_G_HT40MINUS:
1295                 modesIndex = 3;
1296                 freqIndex = 2;
1297                 break;
1298
1299         default:
1300                 return -EINVAL;
1301         }
1302
1303         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1304
1305         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1306
1307         ath9k_hw_set_addac(ah, chan);
1308
1309         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1310                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1311         } else {
1312                 struct ar5416IniArray temp;
1313                 u32 addacSize =
1314                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1315                         ahp->ah_iniAddac.ia_columns;
1316
1317                 memcpy(ahp->ah_addac5416_21,
1318                        ahp->ah_iniAddac.ia_array, addacSize);
1319
1320                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1321
1322                 temp.ia_array = ahp->ah_addac5416_21;
1323                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1324                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1325                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1326         }
1327
1328         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1329
1330         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1331                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1332                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1333
1334                 REG_WRITE(ah, reg, val);
1335
1336                 if (reg >= 0x7800 && reg < 0x78a0
1337                     && ah->ah_config.analog_shiftreg) {
1338                         udelay(100);
1339                 }
1340
1341                 DO_DELAY(regWrites);
1342         }
1343
1344         if (AR_SREV_9280(ah))
1345                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1346
1347         if (AR_SREV_9280(ah))
1348                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1349
1350         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1351                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1352                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1353
1354                 REG_WRITE(ah, reg, val);
1355
1356                 if (reg >= 0x7800 && reg < 0x78a0
1357                     && ah->ah_config.analog_shiftreg) {
1358                         udelay(100);
1359                 }
1360
1361                 DO_DELAY(regWrites);
1362         }
1363
1364         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1365
1366         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1367                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1368                                 regWrites);
1369         }
1370
1371         ath9k_hw_override_ini(ah, chan);
1372         ath9k_hw_set_regs(ah, chan, macmode);
1373         ath9k_hw_init_chain_masks(ah);
1374
1375         status = ath9k_hw_set_txpower(ah, chan,
1376                                       ath9k_regd_get_ctl(ah, chan),
1377                                       ath9k_regd_get_antenna_allowed(ah,
1378                                                                      chan),
1379                                       chan->maxRegTxPower * 2,
1380                                       min((u32) MAX_RATE_POWER,
1381                                           (u32) ah->ah_powerLimit));
1382         if (status != 0) {
1383                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1384                         "error init'ing transmit power\n");
1385                 return -EIO;
1386         }
1387
1388         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1389                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1390                         "ar5416SetRfRegs failed\n");
1391                 return -EIO;
1392         }
1393
1394         return 0;
1395 }
1396
1397 /****************************************/
1398 /* Reset and Channel Switching Routines */
1399 /****************************************/
1400
1401 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1402 {
1403         u32 rfMode = 0;
1404
1405         if (chan == NULL)
1406                 return;
1407
1408         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1409                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1410
1411         if (!AR_SREV_9280_10_OR_LATER(ah))
1412                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1413                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1414
1415         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1416                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1417
1418         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1419 }
1420
1421 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1422 {
1423         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1424 }
1425
1426 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1427 {
1428         u32 regval;
1429
1430         regval = REG_READ(ah, AR_AHB_MODE);
1431         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1432
1433         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1434         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1435
1436         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1437
1438         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1439         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1440
1441         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1442
1443         if (AR_SREV_9285(ah)) {
1444                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1445                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1446         } else {
1447                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1448                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1449         }
1450 }
1451
1452 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1453 {
1454         u32 val;
1455
1456         val = REG_READ(ah, AR_STA_ID1);
1457         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1458         switch (opmode) {
1459         case NL80211_IFTYPE_AP:
1460                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1461                           | AR_STA_ID1_KSRCH_MODE);
1462                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1463                 break;
1464         case NL80211_IFTYPE_ADHOC:
1465                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1466                           | AR_STA_ID1_KSRCH_MODE);
1467                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1468                 break;
1469         case NL80211_IFTYPE_STATION:
1470         case NL80211_IFTYPE_MONITOR:
1471                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1472                 break;
1473         }
1474 }
1475
1476 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1477                                                  u32 coef_scaled,
1478                                                  u32 *coef_mantissa,
1479                                                  u32 *coef_exponent)
1480 {
1481         u32 coef_exp, coef_man;
1482
1483         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1484                 if ((coef_scaled >> coef_exp) & 0x1)
1485                         break;
1486
1487         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1488
1489         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1490
1491         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1492         *coef_exponent = coef_exp - 16;
1493 }
1494
1495 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1496                                      struct ath9k_channel *chan)
1497 {
1498         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1499         u32 clockMhzScaled = 0x64000000;
1500         struct chan_centers centers;
1501
1502         if (IS_CHAN_HALF_RATE(chan))
1503                 clockMhzScaled = clockMhzScaled >> 1;
1504         else if (IS_CHAN_QUARTER_RATE(chan))
1505                 clockMhzScaled = clockMhzScaled >> 2;
1506
1507         ath9k_hw_get_channel_centers(ah, chan, &centers);
1508         coef_scaled = clockMhzScaled / centers.synth_center;
1509
1510         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1511                                       &ds_coef_exp);
1512
1513         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1514                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1515         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1516                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1517
1518         coef_scaled = (9 * coef_scaled) / 10;
1519
1520         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1521                                       &ds_coef_exp);
1522
1523         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1524                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1525         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1526                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1527 }
1528
1529 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1530 {
1531         u32 rst_flags;
1532         u32 tmpReg;
1533
1534         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1535                   AR_RTC_FORCE_WAKE_ON_INT);
1536
1537         if (AR_SREV_9100(ah)) {
1538                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1539                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1540         } else {
1541                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1542                 if (tmpReg &
1543                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1544                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1545                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1546                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1547                 } else {
1548                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1549                 }
1550
1551                 rst_flags = AR_RTC_RC_MAC_WARM;
1552                 if (type == ATH9K_RESET_COLD)
1553                         rst_flags |= AR_RTC_RC_MAC_COLD;
1554         }
1555
1556         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1557         udelay(50);
1558
1559         REG_WRITE(ah, AR_RTC_RC, 0);
1560         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1561                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1562                         "RTC stuck in MAC reset\n");
1563                 return false;
1564         }
1565
1566         if (!AR_SREV_9100(ah))
1567                 REG_WRITE(ah, AR_RC, 0);
1568
1569         ath9k_hw_init_pll(ah, NULL);
1570
1571         if (AR_SREV_9100(ah))
1572                 udelay(50);
1573
1574         return true;
1575 }
1576
1577 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1578 {
1579         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1580                   AR_RTC_FORCE_WAKE_ON_INT);
1581
1582         REG_WRITE(ah, AR_RTC_RESET, 0);
1583         REG_WRITE(ah, AR_RTC_RESET, 1);
1584
1585         if (!ath9k_hw_wait(ah,
1586                            AR_RTC_STATUS,
1587                            AR_RTC_STATUS_M,
1588                            AR_RTC_STATUS_ON)) {
1589                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1590                 return false;
1591         }
1592
1593         ath9k_hw_read_revisions(ah);
1594
1595         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1596 }
1597
1598 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1599 {
1600         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1601                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1602
1603         switch (type) {
1604         case ATH9K_RESET_POWER_ON:
1605                 return ath9k_hw_set_reset_power_on(ah);
1606                 break;
1607         case ATH9K_RESET_WARM:
1608         case ATH9K_RESET_COLD:
1609                 return ath9k_hw_set_reset(ah, type);
1610                 break;
1611         default:
1612                 return false;
1613         }
1614 }
1615
1616 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1617                               enum ath9k_ht_macmode macmode)
1618 {
1619         u32 phymode;
1620         u32 enableDacFifo = 0;
1621         struct ath_hal_5416 *ahp = AH5416(ah);
1622
1623         if (AR_SREV_9285_10_OR_LATER(ah))
1624                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1625                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1626
1627         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1628                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1629
1630         if (IS_CHAN_HT40(chan)) {
1631                 phymode |= AR_PHY_FC_DYN2040_EN;
1632
1633                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1634                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1635                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1636
1637                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1638                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1639         }
1640         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1641
1642         ath9k_hw_set11nmac2040(ah, macmode);
1643
1644         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1645         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1646 }
1647
1648 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1649                                 struct ath9k_channel *chan)
1650 {
1651         struct ath_hal_5416 *ahp = AH5416(ah);
1652
1653         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1654                 return false;
1655
1656         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1657                 return false;
1658
1659         ahp->ah_chipFullSleep = false;
1660
1661         ath9k_hw_init_pll(ah, chan);
1662
1663         ath9k_hw_set_rfmode(ah, chan);
1664
1665         return true;
1666 }
1667
1668 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1669                                     struct ath9k_channel *chan,
1670                                     enum ath9k_ht_macmode macmode)
1671 {
1672         u32 synthDelay, qnum;
1673
1674         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1675                 if (ath9k_hw_numtxpending(ah, qnum)) {
1676                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1677                                 "Transmit frames pending on queue %d\n", qnum);
1678                         return false;
1679                 }
1680         }
1681
1682         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1683         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1684                            AR_PHY_RFBUS_GRANT_EN)) {
1685                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1686                         "Could not kill baseband RX\n");
1687                 return false;
1688         }
1689
1690         ath9k_hw_set_regs(ah, chan, macmode);
1691
1692         if (AR_SREV_9280_10_OR_LATER(ah)) {
1693                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1694                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1695                                 "failed to set channel\n");
1696                         return false;
1697                 }
1698         } else {
1699                 if (!(ath9k_hw_set_channel(ah, chan))) {
1700                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1701                                 "failed to set channel\n");
1702                         return false;
1703                 }
1704         }
1705
1706         if (ath9k_hw_set_txpower(ah, chan,
1707                                  ath9k_regd_get_ctl(ah, chan),
1708                                  ath9k_regd_get_antenna_allowed(ah, chan),
1709                                  chan->maxRegTxPower * 2,
1710                                  min((u32) MAX_RATE_POWER,
1711                                      (u32) ah->ah_powerLimit)) != 0) {
1712                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1713                         "error init'ing transmit power\n");
1714                 return false;
1715         }
1716
1717         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1718         if (IS_CHAN_B(chan))
1719                 synthDelay = (4 * synthDelay) / 22;
1720         else
1721                 synthDelay /= 10;
1722
1723         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1724
1725         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1726
1727         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1728                 ath9k_hw_set_delta_slope(ah, chan);
1729
1730         if (AR_SREV_9280_10_OR_LATER(ah))
1731                 ath9k_hw_9280_spur_mitigate(ah, chan);
1732         else
1733                 ath9k_hw_spur_mitigate(ah, chan);
1734
1735         if (!chan->oneTimeCalsDone)
1736                 chan->oneTimeCalsDone = true;
1737
1738         return true;
1739 }
1740
1741 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1742 {
1743         int bb_spur = AR_NO_SPUR;
1744         int freq;
1745         int bin, cur_bin;
1746         int bb_spur_off, spur_subchannel_sd;
1747         int spur_freq_sd;
1748         int spur_delta_phase;
1749         int denominator;
1750         int upper, lower, cur_vit_mask;
1751         int tmp, newVal;
1752         int i;
1753         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1754                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1755         };
1756         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1757                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1758         };
1759         int inc[4] = { 0, 100, 0, 0 };
1760         struct chan_centers centers;
1761
1762         int8_t mask_m[123];
1763         int8_t mask_p[123];
1764         int8_t mask_amt;
1765         int tmp_mask;
1766         int cur_bb_spur;
1767         bool is2GHz = IS_CHAN_2GHZ(chan);
1768
1769         memset(&mask_m, 0, sizeof(int8_t) * 123);
1770         memset(&mask_p, 0, sizeof(int8_t) * 123);
1771
1772         ath9k_hw_get_channel_centers(ah, chan, &centers);
1773         freq = centers.synth_center;
1774
1775         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1776         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1777                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1778
1779                 if (is2GHz)
1780                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1781                 else
1782                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1783
1784                 if (AR_NO_SPUR == cur_bb_spur)
1785                         break;
1786                 cur_bb_spur = cur_bb_spur - freq;
1787
1788                 if (IS_CHAN_HT40(chan)) {
1789                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1790                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1791                                 bb_spur = cur_bb_spur;
1792                                 break;
1793                         }
1794                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1795                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1796                         bb_spur = cur_bb_spur;
1797                         break;
1798                 }
1799         }
1800
1801         if (AR_NO_SPUR == bb_spur) {
1802                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1803                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1804                 return;
1805         } else {
1806                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1807                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1808         }
1809
1810         bin = bb_spur * 320;
1811
1812         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1813
1814         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1815                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1816                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1817                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1818         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1819
1820         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1821                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1822                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1823                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1824                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1825         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1826
1827         if (IS_CHAN_HT40(chan)) {
1828                 if (bb_spur < 0) {
1829                         spur_subchannel_sd = 1;
1830                         bb_spur_off = bb_spur + 10;
1831                 } else {
1832                         spur_subchannel_sd = 0;
1833                         bb_spur_off = bb_spur - 10;
1834                 }
1835         } else {
1836                 spur_subchannel_sd = 0;
1837                 bb_spur_off = bb_spur;
1838         }
1839
1840         if (IS_CHAN_HT40(chan))
1841                 spur_delta_phase =
1842                         ((bb_spur * 262144) /
1843                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1844         else
1845                 spur_delta_phase =
1846                         ((bb_spur * 524288) /
1847                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1848
1849         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1850         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1851
1852         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1853                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1854                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1855         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1856
1857         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1858         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1859
1860         cur_bin = -6000;
1861         upper = bin + 100;
1862         lower = bin - 100;
1863
1864         for (i = 0; i < 4; i++) {
1865                 int pilot_mask = 0;
1866                 int chan_mask = 0;
1867                 int bp = 0;
1868                 for (bp = 0; bp < 30; bp++) {
1869                         if ((cur_bin > lower) && (cur_bin < upper)) {
1870                                 pilot_mask = pilot_mask | 0x1 << bp;
1871                                 chan_mask = chan_mask | 0x1 << bp;
1872                         }
1873                         cur_bin += 100;
1874                 }
1875                 cur_bin += inc[i];
1876                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1877                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1878         }
1879
1880         cur_vit_mask = 6100;
1881         upper = bin + 120;
1882         lower = bin - 120;
1883
1884         for (i = 0; i < 123; i++) {
1885                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1886
1887                         /* workaround for gcc bug #37014 */
1888                         volatile int tmp_v = abs(cur_vit_mask - bin);
1889
1890                         if (tmp_v < 75)
1891                                 mask_amt = 1;
1892                         else
1893                                 mask_amt = 0;
1894                         if (cur_vit_mask < 0)
1895                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1896                         else
1897                                 mask_p[cur_vit_mask / 100] = mask_amt;
1898                 }
1899                 cur_vit_mask -= 100;
1900         }
1901
1902         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1903                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1904                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1905                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1906                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1907                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1908                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1909                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1910         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1911         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1912
1913         tmp_mask = (mask_m[31] << 28)
1914                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1915                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1916                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1917                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1918                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1919                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1920                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1921         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1922         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1923
1924         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1925                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1926                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1927                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1928                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1929                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1930                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1931                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1932         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1933         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1934
1935         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1936                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1937                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1938                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1939                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1940                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1941                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1942                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1943         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1944         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1945
1946         tmp_mask = (mask_p[15] << 28)
1947                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1948                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1949                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1950                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1951                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1952                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1953                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1954         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1955         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1956
1957         tmp_mask = (mask_p[30] << 28)
1958                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1959                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1960                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1961                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1962                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1963                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1964                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1965         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1966         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1967
1968         tmp_mask = (mask_p[45] << 28)
1969                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1970                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1971                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1972                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1973                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1974                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1975                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1976         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1977         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1978
1979         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1980                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1981                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1982                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1983                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1984                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1985                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1986                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1987         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1988         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1989 }
1990
1991 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1992 {
1993         int bb_spur = AR_NO_SPUR;
1994         int bin, cur_bin;
1995         int spur_freq_sd;
1996         int spur_delta_phase;
1997         int denominator;
1998         int upper, lower, cur_vit_mask;
1999         int tmp, new;
2000         int i;
2001         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2002                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2003         };
2004         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2005                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2006         };
2007         int inc[4] = { 0, 100, 0, 0 };
2008
2009         int8_t mask_m[123];
2010         int8_t mask_p[123];
2011         int8_t mask_amt;
2012         int tmp_mask;
2013         int cur_bb_spur;
2014         bool is2GHz = IS_CHAN_2GHZ(chan);
2015
2016         memset(&mask_m, 0, sizeof(int8_t) * 123);
2017         memset(&mask_p, 0, sizeof(int8_t) * 123);
2018
2019         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2020                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2021                 if (AR_NO_SPUR == cur_bb_spur)
2022                         break;
2023                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2024                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2025                         bb_spur = cur_bb_spur;
2026                         break;
2027                 }
2028         }
2029
2030         if (AR_NO_SPUR == bb_spur)
2031                 return;
2032
2033         bin = bb_spur * 32;
2034
2035         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2036         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2037                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2038                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2039                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2040
2041         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2042
2043         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2044                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2045                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2046                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2047                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2048         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2049
2050         spur_delta_phase = ((bb_spur * 524288) / 100) &
2051                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2052
2053         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2054         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2055
2056         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2057                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2058                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2059         REG_WRITE(ah, AR_PHY_TIMING11, new);
2060
2061         cur_bin = -6000;
2062         upper = bin + 100;
2063         lower = bin - 100;
2064
2065         for (i = 0; i < 4; i++) {
2066                 int pilot_mask = 0;
2067                 int chan_mask = 0;
2068                 int bp = 0;
2069                 for (bp = 0; bp < 30; bp++) {
2070                         if ((cur_bin > lower) && (cur_bin < upper)) {
2071                                 pilot_mask = pilot_mask | 0x1 << bp;
2072                                 chan_mask = chan_mask | 0x1 << bp;
2073                         }
2074                         cur_bin += 100;
2075                 }
2076                 cur_bin += inc[i];
2077                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2078                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2079         }
2080
2081         cur_vit_mask = 6100;
2082         upper = bin + 120;
2083         lower = bin - 120;
2084
2085         for (i = 0; i < 123; i++) {
2086                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2087
2088                         /* workaround for gcc bug #37014 */
2089                         volatile int tmp_v = abs(cur_vit_mask - bin);
2090
2091                         if (tmp_v < 75)
2092                                 mask_amt = 1;
2093                         else
2094                                 mask_amt = 0;
2095                         if (cur_vit_mask < 0)
2096                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2097                         else
2098                                 mask_p[cur_vit_mask / 100] = mask_amt;
2099                 }
2100                 cur_vit_mask -= 100;
2101         }
2102
2103         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2104                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2105                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2106                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2107                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2108                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2109                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2110                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2111         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2112         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2113
2114         tmp_mask = (mask_m[31] << 28)
2115                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2116                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2117                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2118                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2119                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2120                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2121                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2122         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2123         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2124
2125         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2126                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2127                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2128                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2129                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2130                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2131                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2132                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2133         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2134         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2135
2136         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2137                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2138                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2139                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2140                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2141                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2142                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2143                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2144         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2145         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2146
2147         tmp_mask = (mask_p[15] << 28)
2148                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2149                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2150                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2151                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2152                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2153                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2154                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2155         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2156         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2157
2158         tmp_mask = (mask_p[30] << 28)
2159                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2160                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2161                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2162                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2163                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2164                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2165                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2166         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2167         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2168
2169         tmp_mask = (mask_p[45] << 28)
2170                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2171                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2172                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2173                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2174                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2175                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2176                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2177         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2178         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2179
2180         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2181                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2182                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2183                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2184                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2185                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2186                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2187                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2188         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2189         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2190 }
2191
2192 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2193                     bool bChannelChange)
2194 {
2195         u32 saveLedState;
2196         struct ath_softc *sc = ah->ah_sc;
2197         struct ath_hal_5416 *ahp = AH5416(ah);
2198         struct ath9k_channel *curchan = ah->ah_curchan;
2199         u32 saveDefAntenna;
2200         u32 macStaId1;
2201         int i, rx_chainmask, r;
2202
2203         ahp->ah_extprotspacing = sc->sc_ht_extprotspacing;
2204         ahp->ah_txchainmask = sc->sc_tx_chainmask;
2205         ahp->ah_rxchainmask = sc->sc_rx_chainmask;
2206
2207         if (AR_SREV_9280(ah)) {
2208                 ahp->ah_txchainmask &= 0x3;
2209                 ahp->ah_rxchainmask &= 0x3;
2210         }
2211
2212         if (ath9k_regd_check_channel(ah, chan) == NULL) {
2213                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2214                         "invalid channel %u/0x%x; no mapping\n",
2215                         chan->channel, chan->channelFlags);
2216                 return -EINVAL;
2217         }
2218
2219         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2220                 return -EIO;
2221
2222         if (curchan)
2223                 ath9k_hw_getnf(ah, curchan);
2224
2225         if (bChannelChange &&
2226             (ahp->ah_chipFullSleep != true) &&
2227             (ah->ah_curchan != NULL) &&
2228             (chan->channel != ah->ah_curchan->channel) &&
2229             ((chan->channelFlags & CHANNEL_ALL) ==
2230              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2231             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2232                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2233
2234                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2235                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2236                         ath9k_hw_start_nfcal(ah);
2237                         return 0;
2238                 }
2239         }
2240
2241         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2242         if (saveDefAntenna == 0)
2243                 saveDefAntenna = 1;
2244
2245         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2246
2247         saveLedState = REG_READ(ah, AR_CFG_LED) &
2248                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2249                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2250
2251         ath9k_hw_mark_phy_inactive(ah);
2252
2253         if (!ath9k_hw_chip_reset(ah, chan)) {
2254                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2255                 return -EINVAL;
2256         }
2257
2258         if (AR_SREV_9280(ah)) {
2259                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2260                             AR_GPIO_JTAG_DISABLE);
2261
2262                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2263                         if (IS_CHAN_5GHZ(chan))
2264                                 ath9k_hw_set_gpio(ah, 9, 0);
2265                         else
2266                                 ath9k_hw_set_gpio(ah, 9, 1);
2267                 }
2268                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2269         }
2270
2271         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2272         if (r)
2273                 return r;
2274
2275         /* Setup MFP options for CCMP */
2276         if (AR_SREV_9280_20_OR_LATER(ah)) {
2277                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2278                  * frames when constructing CCMP AAD. */
2279                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2280                               0xc7ff);
2281                 ah->sw_mgmt_crypto = false;
2282         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2283                 /* Disable hardware crypto for management frames */
2284                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2285                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2286                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2287                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2288                 ah->sw_mgmt_crypto = true;
2289         } else
2290                 ah->sw_mgmt_crypto = true;
2291
2292         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2293                 ath9k_hw_set_delta_slope(ah, chan);
2294
2295         if (AR_SREV_9280_10_OR_LATER(ah))
2296                 ath9k_hw_9280_spur_mitigate(ah, chan);
2297         else
2298                 ath9k_hw_spur_mitigate(ah, chan);
2299
2300         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2301                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2302                         "error setting board options\n");
2303                 return -EIO;
2304         }
2305
2306         ath9k_hw_decrease_chain_power(ah, chan);
2307
2308         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2309         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2310                   | macStaId1
2311                   | AR_STA_ID1_RTS_USE_DEF
2312                   | (ah->ah_config.
2313                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2314                   | ahp->ah_staId1Defaults);
2315         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2316
2317         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2318         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2319
2320         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2321
2322         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2323         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2324                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2325
2326         REG_WRITE(ah, AR_ISR, ~0);
2327
2328         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2329
2330         if (AR_SREV_9280_10_OR_LATER(ah)) {
2331                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2332                         return -EIO;
2333         } else {
2334                 if (!(ath9k_hw_set_channel(ah, chan)))
2335                         return -EIO;
2336         }
2337
2338         for (i = 0; i < AR_NUM_DCU; i++)
2339                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2340
2341         ahp->ah_intrTxqs = 0;
2342         for (i = 0; i < ah->ah_caps.total_queues; i++)
2343                 ath9k_hw_resettxqueue(ah, i);
2344
2345         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2346         ath9k_hw_init_qos(ah);
2347
2348 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2349         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2350                 ath9k_enable_rfkill(ah);
2351 #endif
2352         ath9k_hw_init_user_settings(ah);
2353
2354         REG_WRITE(ah, AR_STA_ID1,
2355                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2356
2357         ath9k_hw_set_dma(ah);
2358
2359         REG_WRITE(ah, AR_OBS, 8);
2360
2361         if (ahp->ah_intrMitigation) {
2362
2363                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2364                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2365         }
2366
2367         ath9k_hw_init_bb(ah, chan);
2368
2369         if (!ath9k_hw_init_cal(ah, chan))
2370                 return -EIO;;
2371
2372         rx_chainmask = ahp->ah_rxchainmask;
2373         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2374                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2375                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2376         }
2377
2378         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2379
2380         if (AR_SREV_9100(ah)) {
2381                 u32 mask;
2382                 mask = REG_READ(ah, AR_CFG);
2383                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2384                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2385                                 "CFG Byte Swap Set 0x%x\n", mask);
2386                 } else {
2387                         mask =
2388                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2389                         REG_WRITE(ah, AR_CFG, mask);
2390                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2391                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2392                 }
2393         } else {
2394 #ifdef __BIG_ENDIAN
2395                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2396 #endif
2397         }
2398
2399         return 0;
2400 }
2401
2402 /************************/
2403 /* Key Cache Management */
2404 /************************/
2405
2406 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2407 {
2408         u32 keyType;
2409
2410         if (entry >= ah->ah_caps.keycache_size) {
2411                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2412                         "entry %u out of range\n", entry);
2413                 return false;
2414         }
2415
2416         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2417
2418         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2419         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2420         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2421         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2422         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2423         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2424         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2425         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2426
2427         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2428                 u16 micentry = entry + 64;
2429
2430                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2431                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2432                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2433                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2434
2435         }
2436
2437         if (ah->ah_curchan == NULL)
2438                 return true;
2439
2440         return true;
2441 }
2442
2443 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2444 {
2445         u32 macHi, macLo;
2446
2447         if (entry >= ah->ah_caps.keycache_size) {
2448                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2449                         "entry %u out of range\n", entry);
2450                 return false;
2451         }
2452
2453         if (mac != NULL) {
2454                 macHi = (mac[5] << 8) | mac[4];
2455                 macLo = (mac[3] << 24) |
2456                         (mac[2] << 16) |
2457                         (mac[1] << 8) |
2458                         mac[0];
2459                 macLo >>= 1;
2460                 macLo |= (macHi & 1) << 31;
2461                 macHi >>= 1;
2462         } else {
2463                 macLo = macHi = 0;
2464         }
2465         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2466         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2467
2468         return true;
2469 }
2470
2471 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2472                                  const struct ath9k_keyval *k,
2473                                  const u8 *mac, int xorKey)
2474 {
2475         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2476         u32 key0, key1, key2, key3, key4;
2477         u32 keyType;
2478         u32 xorMask = xorKey ?
2479                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2480                  | ATH9K_KEY_XOR) : 0;
2481         struct ath_hal_5416 *ahp = AH5416(ah);
2482
2483         if (entry >= pCap->keycache_size) {
2484                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2485                         "entry %u out of range\n", entry);
2486                 return false;
2487         }
2488
2489         switch (k->kv_type) {
2490         case ATH9K_CIPHER_AES_OCB:
2491                 keyType = AR_KEYTABLE_TYPE_AES;
2492                 break;
2493         case ATH9K_CIPHER_AES_CCM:
2494                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2495                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2496                                 "AES-CCM not supported by mac rev 0x%x\n",
2497                                 ah->ah_macRev);
2498                         return false;
2499                 }
2500                 keyType = AR_KEYTABLE_TYPE_CCM;
2501                 break;
2502         case ATH9K_CIPHER_TKIP:
2503                 keyType = AR_KEYTABLE_TYPE_TKIP;
2504                 if (ATH9K_IS_MIC_ENABLED(ah)
2505                     && entry + 64 >= pCap->keycache_size) {
2506                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2507                                 "entry %u inappropriate for TKIP\n", entry);
2508                         return false;
2509                 }
2510                 break;
2511         case ATH9K_CIPHER_WEP:
2512                 if (k->kv_len < LEN_WEP40) {
2513                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2514                                 "WEP key length %u too small\n", k->kv_len);
2515                         return false;
2516                 }
2517                 if (k->kv_len <= LEN_WEP40)
2518                         keyType = AR_KEYTABLE_TYPE_40;
2519                 else if (k->kv_len <= LEN_WEP104)
2520                         keyType = AR_KEYTABLE_TYPE_104;
2521                 else
2522                         keyType = AR_KEYTABLE_TYPE_128;
2523                 break;
2524         case ATH9K_CIPHER_CLR:
2525                 keyType = AR_KEYTABLE_TYPE_CLR;
2526                 break;
2527         default:
2528                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2529                         "cipher %u not supported\n", k->kv_type);
2530                 return false;
2531         }
2532
2533         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2534         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2535         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2536         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2537         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2538         if (k->kv_len <= LEN_WEP104)
2539                 key4 &= 0xff;
2540
2541         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2542                 u16 micentry = entry + 64;
2543
2544                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2545                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2546                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2547                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2548                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2549                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2550                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2551
2552                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2553                         u32 mic0, mic1, mic2, mic3, mic4;
2554
2555                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2556                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2557                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2558                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2559                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2560                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2561                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2562                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2563                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2564                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2565                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2566                                   AR_KEYTABLE_TYPE_CLR);
2567
2568                 } else {
2569                         u32 mic0, mic2;
2570
2571                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2572                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2573                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2574                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2575                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2576                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2577                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2578                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2579                                   AR_KEYTABLE_TYPE_CLR);
2580                 }
2581                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2582                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2583                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2584                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2585         } else {
2586                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2587                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2588                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2589                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2590                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2591                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2592
2593                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2594         }
2595
2596         if (ah->ah_curchan == NULL)
2597                 return true;
2598
2599         return true;
2600 }
2601
2602 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2603 {
2604         if (entry < ah->ah_caps.keycache_size) {
2605                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2606                 if (val & AR_KEYTABLE_VALID)
2607                         return true;
2608         }
2609         return false;
2610 }
2611
2612 /******************************/
2613 /* Power Management (Chipset) */
2614 /******************************/
2615
2616 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2617 {
2618         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2619         if (setChip) {
2620                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2621                             AR_RTC_FORCE_WAKE_EN);
2622                 if (!AR_SREV_9100(ah))
2623                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2624
2625                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2626                             AR_RTC_RESET_EN);
2627         }
2628 }
2629
2630 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2631 {
2632         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2633         if (setChip) {
2634                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2635
2636                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2637                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2638                                   AR_RTC_FORCE_WAKE_ON_INT);
2639                 } else {
2640                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2641                                     AR_RTC_FORCE_WAKE_EN);
2642                 }
2643         }
2644 }
2645
2646 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2647                                      int setChip)
2648 {
2649         u32 val;
2650         int i;
2651
2652         if (setChip) {
2653                 if ((REG_READ(ah, AR_RTC_STATUS) &
2654                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2655                         if (ath9k_hw_set_reset_reg(ah,
2656                                            ATH9K_RESET_POWER_ON) != true) {
2657                                 return false;
2658                         }
2659                 }
2660                 if (AR_SREV_9100(ah))
2661                         REG_SET_BIT(ah, AR_RTC_RESET,
2662                                     AR_RTC_RESET_EN);
2663
2664                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2665                             AR_RTC_FORCE_WAKE_EN);
2666                 udelay(50);
2667
2668                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2669                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2670                         if (val == AR_RTC_STATUS_ON)
2671                                 break;
2672                         udelay(50);
2673                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2674                                     AR_RTC_FORCE_WAKE_EN);
2675                 }
2676                 if (i == 0) {
2677                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2678                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2679                         return false;
2680                 }
2681         }
2682
2683         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2684
2685         return true;
2686 }
2687
2688 bool ath9k_hw_setpower(struct ath_hal *ah,
2689                        enum ath9k_power_mode mode)
2690 {
2691         struct ath_hal_5416 *ahp = AH5416(ah);
2692         static const char *modes[] = {
2693                 "AWAKE",
2694                 "FULL-SLEEP",
2695                 "NETWORK SLEEP",
2696                 "UNDEFINED"
2697         };
2698         int status = true, setChip = true;
2699
2700         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2701                 modes[ah->ah_power_mode], modes[mode],
2702                 setChip ? "set chip " : "");
2703
2704         switch (mode) {
2705         case ATH9K_PM_AWAKE:
2706                 status = ath9k_hw_set_power_awake(ah, setChip);
2707                 break;
2708         case ATH9K_PM_FULL_SLEEP:
2709                 ath9k_set_power_sleep(ah, setChip);
2710                 ahp->ah_chipFullSleep = true;
2711                 break;
2712         case ATH9K_PM_NETWORK_SLEEP:
2713                 ath9k_set_power_network_sleep(ah, setChip);
2714                 break;
2715         default:
2716                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2717                         "Unknown power mode %u\n", mode);
2718                 return false;
2719         }
2720         ah->ah_power_mode = mode;
2721
2722         return status;
2723 }
2724
2725 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2726 {
2727         struct ath_hal_5416 *ahp = AH5416(ah);
2728         u8 i;
2729
2730         if (ah->ah_isPciExpress != true)
2731                 return;
2732
2733         if (ah->ah_config.pcie_powersave_enable == 2)
2734                 return;
2735
2736         if (restore)
2737                 return;
2738
2739         if (AR_SREV_9280_20_OR_LATER(ah)) {
2740                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2741                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2742                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2743                 }
2744                 udelay(1000);
2745         } else if (AR_SREV_9280(ah) &&
2746                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2747                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2748                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2749
2750                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2751                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2752                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2753
2754                 if (ah->ah_config.pcie_clock_req)
2755                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2756                 else
2757                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2758
2759                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2760                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2761                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2762
2763                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2764
2765                 udelay(1000);
2766         } else {
2767                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2768                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2769                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2770                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2771                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2772                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2773                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2774                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2775                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2776                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2777         }
2778
2779         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2780
2781         if (ah->ah_config.pcie_waen) {
2782                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2783         } else {
2784                 if (AR_SREV_9285(ah))
2785                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2786                 else if (AR_SREV_9280(ah))
2787                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2788                 else
2789                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2790         }
2791
2792 }
2793
2794 /**********************/
2795 /* Interrupt Handling */
2796 /**********************/
2797
2798 bool ath9k_hw_intrpend(struct ath_hal *ah)
2799 {
2800         u32 host_isr;
2801
2802         if (AR_SREV_9100(ah))
2803                 return true;
2804
2805         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2806         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2807                 return true;
2808
2809         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2810         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2811             && (host_isr != AR_INTR_SPURIOUS))
2812                 return true;
2813
2814         return false;
2815 }
2816
2817 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2818 {
2819         u32 isr = 0;
2820         u32 mask2 = 0;
2821         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2822         u32 sync_cause = 0;
2823         bool fatal_int = false;
2824         struct ath_hal_5416 *ahp = AH5416(ah);
2825
2826         if (!AR_SREV_9100(ah)) {
2827                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2828                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2829                             == AR_RTC_STATUS_ON) {
2830                                 isr = REG_READ(ah, AR_ISR);
2831                         }
2832                 }
2833
2834                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2835                         AR_INTR_SYNC_DEFAULT;
2836
2837                 *masked = 0;
2838
2839                 if (!isr && !sync_cause)
2840                         return false;
2841         } else {
2842                 *masked = 0;
2843                 isr = REG_READ(ah, AR_ISR);
2844         }
2845
2846         if (isr) {
2847                 if (isr & AR_ISR_BCNMISC) {
2848                         u32 isr2;
2849                         isr2 = REG_READ(ah, AR_ISR_S2);
2850                         if (isr2 & AR_ISR_S2_TIM)
2851                                 mask2 |= ATH9K_INT_TIM;
2852                         if (isr2 & AR_ISR_S2_DTIM)
2853                                 mask2 |= ATH9K_INT_DTIM;
2854                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2855                                 mask2 |= ATH9K_INT_DTIMSYNC;
2856                         if (isr2 & (AR_ISR_S2_CABEND))
2857                                 mask2 |= ATH9K_INT_CABEND;
2858                         if (isr2 & AR_ISR_S2_GTT)
2859                                 mask2 |= ATH9K_INT_GTT;
2860                         if (isr2 & AR_ISR_S2_CST)
2861                                 mask2 |= ATH9K_INT_CST;
2862                 }
2863
2864                 isr = REG_READ(ah, AR_ISR_RAC);
2865                 if (isr == 0xffffffff) {
2866                         *masked = 0;
2867                         return false;
2868                 }
2869
2870                 *masked = isr & ATH9K_INT_COMMON;
2871
2872                 if (ahp->ah_intrMitigation) {
2873                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2874                                 *masked |= ATH9K_INT_RX;
2875                 }
2876
2877                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2878                         *masked |= ATH9K_INT_RX;
2879                 if (isr &
2880                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2881                      AR_ISR_TXEOL)) {
2882                         u32 s0_s, s1_s;
2883
2884                         *masked |= ATH9K_INT_TX;
2885
2886                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2887                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2888                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2889
2890                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2891                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2892                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2893                 }
2894
2895                 if (isr & AR_ISR_RXORN) {
2896                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2897                                 "receive FIFO overrun interrupt\n");
2898                 }
2899
2900                 if (!AR_SREV_9100(ah)) {
2901                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2902                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2903                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2904                                         *masked |= ATH9K_INT_TIM_TIMER;
2905                         }
2906                 }
2907
2908                 *masked |= mask2;
2909         }
2910
2911         if (AR_SREV_9100(ah))
2912                 return true;
2913
2914         if (sync_cause) {
2915                 fatal_int =
2916                         (sync_cause &
2917                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2918                         ? true : false;
2919
2920                 if (fatal_int) {
2921                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2922                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2923                                         "received PCI FATAL interrupt\n");
2924                         }
2925                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2926                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2927                                         "received PCI PERR interrupt\n");
2928                         }
2929                 }
2930                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2931                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2932                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2933                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2934                         REG_WRITE(ah, AR_RC, 0);
2935                         *masked |= ATH9K_INT_FATAL;
2936                 }
2937                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2938                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2939                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2940                 }
2941
2942                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2943                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2944         }
2945
2946         return true;
2947 }
2948
2949 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2950 {
2951         return AH5416(ah)->ah_maskReg;
2952 }
2953
2954 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2955 {
2956         struct ath_hal_5416 *ahp = AH5416(ah);
2957         u32 omask = ahp->ah_maskReg;
2958         u32 mask, mask2;
2959         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2960
2961         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2962
2963         if (omask & ATH9K_INT_GLOBAL) {
2964                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2965                 REG