2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 /* We can tune this as we go by monitoring really low values */
23 #define ATH9K_NF_TOO_LOW -60
25 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
26 * is incorrect and we should use the static NF value. Later we can try to
27 * find out why they are reporting these values */
29 static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
31 if (nf > ATH9K_NF_TOO_LOW) {
32 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
33 "noise floor value detected (%d) is "
34 "lower than what we think is a "
35 "reasonable value (%d)\n",
36 nf, ATH9K_NF_TOO_LOW);
42 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
45 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
48 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
49 sort[i] = nfCalBuffer[i];
51 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
52 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
53 if (sort[j] > sort[j - 1]) {
55 sort[j] = sort[j - 1];
60 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
65 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
70 for (i = 0; i < NUM_NF_READINGS; i++) {
71 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
73 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
76 if (h[i].invalidNFcount > 0) {
77 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
78 nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
79 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
81 h[i].invalidNFcount--;
82 h[i].privNF = nfarray[i];
86 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
92 static void ath9k_hw_do_getnf(struct ath_hal *ah,
93 int16_t nfarray[NUM_NF_READINGS])
97 if (AR_SREV_9280_10_OR_LATER(ah))
98 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
100 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
103 nf = 0 - ((nf ^ 0x1ff) + 1);
104 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
105 "NF calibrated [ctl] [chain 0] is %d\n", nf);
108 if (AR_SREV_9280_10_OR_LATER(ah))
109 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
110 AR9280_PHY_CH1_MINCCA_PWR);
112 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
113 AR_PHY_CH1_MINCCA_PWR);
116 nf = 0 - ((nf ^ 0x1ff) + 1);
117 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
118 "NF calibrated [ctl] [chain 1] is %d\n", nf);
121 if (!AR_SREV_9280(ah)) {
122 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
123 AR_PHY_CH2_MINCCA_PWR);
125 nf = 0 - ((nf ^ 0x1ff) + 1);
126 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
127 "NF calibrated [ctl] [chain 2] is %d\n", nf);
131 if (AR_SREV_9280_10_OR_LATER(ah))
132 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
133 AR9280_PHY_EXT_MINCCA_PWR);
135 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
136 AR_PHY_EXT_MINCCA_PWR);
139 nf = 0 - ((nf ^ 0x1ff) + 1);
140 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
141 "NF calibrated [ext] [chain 0] is %d\n", nf);
144 if (AR_SREV_9280_10_OR_LATER(ah))
145 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
146 AR9280_PHY_CH1_EXT_MINCCA_PWR);
148 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
149 AR_PHY_CH1_EXT_MINCCA_PWR);
152 nf = 0 - ((nf ^ 0x1ff) + 1);
153 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
154 "NF calibrated [ext] [chain 1] is %d\n", nf);
157 if (!AR_SREV_9280(ah)) {
158 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
159 AR_PHY_CH2_EXT_MINCCA_PWR);
161 nf = 0 - ((nf ^ 0x1ff) + 1);
162 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
163 "NF calibrated [ext] [chain 2] is %d\n", nf);
168 static bool getNoiseFloorThresh(struct ath_hal *ah,
169 enum ieee80211_band band,
173 case IEEE80211_BAND_5GHZ:
174 *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);
176 case IEEE80211_BAND_2GHZ:
177 *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);
187 static void ath9k_hw_setup_calibration(struct ath_hal *ah,
188 struct hal_cal_list *currCal)
190 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
191 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
192 currCal->calData->calCountMax);
194 switch (currCal->calData->calType) {
195 case IQ_MISMATCH_CAL:
196 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
197 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
198 "starting IQ Mismatch Calibration\n");
201 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
202 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
203 "starting ADC Gain Calibration\n");
206 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
207 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
208 "starting ADC DC Calibration\n");
210 case ADC_DC_INIT_CAL:
211 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
212 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
213 "starting Init ADC DC Calibration\n");
217 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
218 AR_PHY_TIMING_CTRL4_DO_CAL);
221 static void ath9k_hw_reset_calibration(struct ath_hal *ah,
222 struct hal_cal_list *currCal)
224 struct ath_hal_5416 *ahp = AH5416(ah);
227 ath9k_hw_setup_calibration(ah, currCal);
229 currCal->calState = CAL_RUNNING;
231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
232 ahp->ah_Meas0.sign[i] = 0;
233 ahp->ah_Meas1.sign[i] = 0;
234 ahp->ah_Meas2.sign[i] = 0;
235 ahp->ah_Meas3.sign[i] = 0;
238 ahp->ah_CalSamples = 0;
241 static void ath9k_hw_per_calibration(struct ath_hal *ah,
242 struct ath9k_channel *ichan,
244 struct hal_cal_list *currCal,
247 struct ath_hal_5416 *ahp = AH5416(ah);
251 if (currCal->calState == CAL_RUNNING) {
252 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
253 AR_PHY_TIMING_CTRL4_DO_CAL)) {
255 currCal->calData->calCollect(ah);
256 ahp->ah_CalSamples++;
258 if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) {
259 int i, numChains = 0;
260 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
261 if (rxchainmask & (1 << i))
265 currCal->calData->calPostProc(ah, numChains);
266 ichan->CalValid |= currCal->calData->calType;
267 currCal->calState = CAL_DONE;
270 ath9k_hw_setup_calibration(ah, currCal);
273 } else if (!(ichan->CalValid & currCal->calData->calType)) {
274 ath9k_hw_reset_calibration(ah, currCal);
278 /* Assumes you are talking about the currently configured channel */
279 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
280 enum hal_cal_types calType)
282 struct ath_hal_5416 *ahp = AH5416(ah);
283 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
285 switch (calType & ahp->ah_suppCals) {
286 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
290 if (conf->channel->band == IEEE80211_BAND_5GHZ &&
298 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
300 struct ath_hal_5416 *ahp = AH5416(ah);
303 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
304 ahp->ah_totalPowerMeasI[i] +=
305 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
306 ahp->ah_totalPowerMeasQ[i] +=
307 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
308 ahp->ah_totalIqCorrMeas[i] +=
309 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
310 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
311 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
312 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
313 ahp->ah_totalPowerMeasQ[i],
314 ahp->ah_totalIqCorrMeas[i]);
318 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
320 struct ath_hal_5416 *ahp = AH5416(ah);
323 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
324 ahp->ah_totalAdcIOddPhase[i] +=
325 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
326 ahp->ah_totalAdcIEvenPhase[i] +=
327 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
328 ahp->ah_totalAdcQOddPhase[i] +=
329 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
330 ahp->ah_totalAdcQEvenPhase[i] +=
331 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
333 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
334 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
335 "oddq=0x%08x; evenq=0x%08x;\n",
336 ahp->ah_CalSamples, i,
337 ahp->ah_totalAdcIOddPhase[i],
338 ahp->ah_totalAdcIEvenPhase[i],
339 ahp->ah_totalAdcQOddPhase[i],
340 ahp->ah_totalAdcQEvenPhase[i]);
344 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
346 struct ath_hal_5416 *ahp = AH5416(ah);
349 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
350 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
351 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
352 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
353 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
354 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
355 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
356 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
357 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
359 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
360 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
361 "oddq=0x%08x; evenq=0x%08x;\n",
362 ahp->ah_CalSamples, i,
363 ahp->ah_totalAdcDcOffsetIOddPhase[i],
364 ahp->ah_totalAdcDcOffsetIEvenPhase[i],
365 ahp->ah_totalAdcDcOffsetQOddPhase[i],
366 ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
370 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
372 struct ath_hal_5416 *ahp = AH5416(ah);
373 u32 powerMeasQ, powerMeasI, iqCorrMeas;
374 u32 qCoffDenom, iCoffDenom;
375 int32_t qCoff, iCoff;
378 for (i = 0; i < numChains; i++) {
379 powerMeasI = ahp->ah_totalPowerMeasI[i];
380 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
381 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
383 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
384 "Starting IQ Cal and Correction for Chain %d\n",
387 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
388 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
389 i, ahp->ah_totalIqCorrMeas[i]);
393 if (iqCorrMeas > 0x80000000) {
394 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
398 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
399 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
400 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
401 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
402 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
405 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
406 qCoffDenom = powerMeasQ / 64;
408 if (powerMeasQ != 0) {
409 iCoff = iqCorrMeas / iCoffDenom;
410 qCoff = powerMeasI / qCoffDenom - 64;
411 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
412 "Chn %d iCoff = 0x%08x\n", i, iCoff);
413 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
414 "Chn %d qCoff = 0x%08x\n", i, qCoff);
416 iCoff = iCoff & 0x3f;
417 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
418 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
419 if (iqCorrNeg == 0x0)
420 iCoff = 0x40 - iCoff;
424 else if (qCoff <= -16)
427 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
428 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
431 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
432 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
434 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
435 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
437 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
438 "IQ Cal and Correction done for Chain %d\n",
443 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
444 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
447 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
449 struct ath_hal_5416 *ahp = AH5416(ah);
450 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
451 u32 qGainMismatch, iGainMismatch, val, i;
453 for (i = 0; i < numChains; i++) {
454 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
455 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
456 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
457 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
459 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
460 "Starting ADC Gain Cal for Chain %d\n", i);
462 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
463 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
465 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
466 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
468 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
469 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
471 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
472 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
475 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
477 ((iEvenMeasOffset * 32) /
478 iOddMeasOffset) & 0x3f;
480 ((qOddMeasOffset * 32) /
481 qEvenMeasOffset) & 0x3f;
483 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
484 "Chn %d gain_mismatch_i = 0x%08x\n", i,
486 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
487 "Chn %d gain_mismatch_q = 0x%08x\n", i,
490 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
492 val |= (qGainMismatch) | (iGainMismatch << 6);
493 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
495 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
496 "ADC Gain Cal done for Chain %d\n", i);
500 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
501 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
502 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
505 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
507 struct ath_hal_5416 *ahp = AH5416(ah);
508 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
509 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
510 const struct hal_percal_data *calData =
511 ahp->ah_cal_list_curr->calData;
513 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
515 for (i = 0; i < numChains; i++) {
516 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
517 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
518 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
519 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
521 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
522 "Starting ADC DC Offset Cal for Chain %d\n", i);
524 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
525 "Chn %d pwr_meas_odd_i = %d\n", i,
527 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
528 "Chn %d pwr_meas_even_i = %d\n", i,
530 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
531 "Chn %d pwr_meas_odd_q = %d\n", i,
533 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
534 "Chn %d pwr_meas_even_q = %d\n", i,
537 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
539 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
542 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
543 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
545 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
546 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
549 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
551 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
552 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
554 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
555 "ADC DC Offset Cal done for Chain %d\n", i);
558 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
559 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
560 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
563 /* This is done for the currently configured channel */
564 bool ath9k_hw_reset_calvalid(struct ath_hal *ah)
566 struct ath_hal_5416 *ahp = AH5416(ah);
567 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
568 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
573 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
579 if (currCal->calState != CAL_DONE) {
580 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
581 "Calibration state incorrect, %d\n",
586 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
589 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
590 "Resetting Cal %d state for channel %u\n",
591 currCal->calData->calType, conf->channel->center_freq);
593 ah->ah_curchan->CalValid &= ~currCal->calData->calType;
594 currCal->calState = CAL_WAITING;
599 void ath9k_hw_start_nfcal(struct ath_hal *ah)
601 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
602 AR_PHY_AGC_CONTROL_ENABLE_NF);
603 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
604 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
605 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
608 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
610 struct ath9k_nfcal_hist *h;
613 const u32 ar5416_cca_regs[6] = {
623 if (AR_SREV_9280(ah))
630 for (i = 0; i < NUM_NF_READINGS; i++) {
631 if (chainmask & (1 << i)) {
632 val = REG_READ(ah, ar5416_cca_regs[i]);
634 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
635 REG_WRITE(ah, ar5416_cca_regs[i], val);
639 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
640 AR_PHY_AGC_CONTROL_ENABLE_NF);
641 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
642 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
643 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
645 for (j = 0; j < 1000; j++) {
646 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
647 AR_PHY_AGC_CONTROL_NF) == 0)
652 for (i = 0; i < NUM_NF_READINGS; i++) {
653 if (chainmask & (1 << i)) {
654 val = REG_READ(ah, ar5416_cca_regs[i]);
656 val |= (((u32) (-50) << 1) & 0x1ff);
657 REG_WRITE(ah, ar5416_cca_regs[i], val);
662 int16_t ath9k_hw_getnf(struct ath_hal *ah,
663 struct ath9k_channel *chan)
665 int16_t nf, nfThresh;
666 int16_t nfarray[NUM_NF_READINGS] = { 0 };
667 struct ath9k_nfcal_hist *h;
668 struct ieee80211_channel *c = chan->chan;
671 if (AR_SREV_9280(ah))
676 chan->channelFlags &= (~CHANNEL_CW_INT);
677 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
678 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
679 "NF did not complete in calibration window\n");
681 chan->rawNoiseFloor = nf;
682 return chan->rawNoiseFloor;
684 ath9k_hw_do_getnf(ah, nfarray);
686 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
688 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
689 "noise floor failed detected; "
690 "detected %d, threshold %d\n",
692 chan->channelFlags |= CHANNEL_CW_INT;
698 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
699 chan->rawNoiseFloor = h[0].privNF;
701 return chan->rawNoiseFloor;
704 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
708 for (i = 0; i < NUM_NF_READINGS; i++) {
709 ah->nfCalHist[i].currIndex = 0;
710 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
711 ah->nfCalHist[i].invalidNFcount =
712 AR_PHY_CCA_FILTERWINDOW_LENGTH;
713 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
714 ah->nfCalHist[i].nfCalBuffer[j] =
715 AR_PHY_CCA_MAX_GOOD_VALUE;
721 s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
725 if (chan->rawNoiseFloor == 0)
728 nf = chan->rawNoiseFloor;
730 if (!ath9k_hw_nf_in_range(ah, nf))
731 nf = ATH_DEFAULT_NOISE_FLOOR;
736 bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
737 u8 rxchainmask, bool longcal,
740 struct ath_hal_5416 *ahp = AH5416(ah);
741 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
746 (currCal->calState == CAL_RUNNING ||
747 currCal->calState == CAL_WAITING)) {
748 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
751 ahp->ah_cal_list_curr = currCal = currCal->calNext;
753 if (currCal->calState == CAL_WAITING) {
755 ath9k_hw_reset_calibration(ah, currCal);
761 ath9k_hw_getnf(ah, chan);
762 ath9k_hw_loadnf(ah, ah->ah_curchan);
763 ath9k_hw_start_nfcal(ah);
765 if (chan->channelFlags & CHANNEL_CW_INT)
766 chan->channelFlags &= ~CHANNEL_CW_INT;
772 static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
776 int i, offset, offs_6_1, offs_0;
777 u32 ccomp_org, reg_field;
788 if (AR_SREV_9285_11(ah)) {
789 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
793 for (i = 0; i < ARRAY_SIZE(regList); i++)
794 regList[i][1] = REG_READ(ah, regList[i][0]);
796 regVal = REG_READ(ah, 0x7834);
798 REG_WRITE(ah, 0x7834, regVal);
799 regVal = REG_READ(ah, 0x9808);
800 regVal |= (0x1 << 27);
801 REG_WRITE(ah, 0x9808, regVal);
803 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
804 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
805 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
806 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
807 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
808 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
809 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
810 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);
811 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
812 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
813 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
814 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
815 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
816 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);
818 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
820 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
821 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
823 for (i = 6; i > 0; i--) {
824 regVal = REG_READ(ah, 0x7834);
825 regVal |= (1 << (19 + i));
826 REG_WRITE(ah, 0x7834, regVal);
828 regVal = REG_READ(ah, 0x7834);
829 regVal &= (~(0x1 << (19 + i)));
830 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
831 regVal |= (reg_field << (19 + i));
832 REG_WRITE(ah, 0x7834, regVal);
835 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
837 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
838 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
839 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
840 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
842 offset = (offs_6_1<<1) | offs_0;
844 offs_6_1 = offset>>1;
847 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
848 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
850 regVal = REG_READ(ah, 0x7834);
852 REG_WRITE(ah, 0x7834, regVal);
853 regVal = REG_READ(ah, 0x9808);
854 regVal &= (~(0x1 << 27));
855 REG_WRITE(ah, 0x9808, regVal);
857 for (i = 0; i < ARRAY_SIZE(regList); i++)
858 REG_WRITE(ah, regList[i][0], regList[i][1]);
860 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
862 if (AR_SREV_9285_11(ah))
863 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
867 bool ath9k_hw_init_cal(struct ath_hal *ah,
868 struct ath9k_channel *chan)
870 struct ath_hal_5416 *ahp = AH5416(ah);
872 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
873 REG_READ(ah, AR_PHY_AGC_CONTROL) |
874 AR_PHY_AGC_CONTROL_CAL);
876 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
877 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
878 "offset calibration failed to complete in 1ms; "
879 "noisy environment?\n");
883 if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
884 ath9k_hw_9285_pa_cal(ah);
886 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
887 REG_READ(ah, AR_PHY_AGC_CONTROL) |
888 AR_PHY_AGC_CONTROL_NF);
890 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
892 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
893 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
894 INIT_CAL(&ahp->ah_adcGainCalData);
895 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
896 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
897 "enabling ADC Gain Calibration.\n");
899 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
900 INIT_CAL(&ahp->ah_adcDcCalData);
901 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
902 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
903 "enabling ADC DC Calibration.\n");
905 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
906 INIT_CAL(&ahp->ah_iqCalData);
907 INSERT_CAL(ahp, &ahp->ah_iqCalData);
908 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
909 "enabling IQ Calibration.\n");
912 ahp->ah_cal_list_curr = ahp->ah_cal_list;
914 if (ahp->ah_cal_list_curr)
915 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);
923 const struct hal_percal_data iq_cal_multi_sample = {
927 ath9k_hw_iqcal_collect,
930 const struct hal_percal_data iq_cal_single_sample = {
934 ath9k_hw_iqcal_collect,
937 const struct hal_percal_data adc_gain_cal_multi_sample = {
941 ath9k_hw_adc_gaincal_collect,
942 ath9k_hw_adc_gaincal_calibrate
944 const struct hal_percal_data adc_gain_cal_single_sample = {
948 ath9k_hw_adc_gaincal_collect,
949 ath9k_hw_adc_gaincal_calibrate
951 const struct hal_percal_data adc_dc_cal_multi_sample = {
955 ath9k_hw_adc_dccal_collect,
956 ath9k_hw_adc_dccal_calibrate
958 const struct hal_percal_data adc_dc_cal_single_sample = {
962 ath9k_hw_adc_dccal_collect,
963 ath9k_hw_adc_dccal_calibrate
965 const struct hal_percal_data adc_init_dc_cal = {
969 ath9k_hw_adc_dccal_collect,
970 ath9k_hw_adc_dccal_calibrate