2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
77 static int ath_max_4ms_framelen[4][32] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
104 /*********************/
105 /* Aggregation logic */
106 /*********************/
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 struct ath_txq *txq = tid->ac->txq;
132 WARN_ON(!tid->paused);
134 spin_lock_bh(&txq->axq_lock);
137 if (skb_queue_empty(&tid->buf_q))
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
143 spin_unlock_bh(&txq->axq_lock);
146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
154 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
156 struct ath_txq *txq = tid->ac->txq;
159 struct list_head bf_head;
160 struct ath_tx_status ts;
161 struct ath_frame_info *fi;
163 INIT_LIST_HEAD(&bf_head);
165 memset(&ts, 0, sizeof(ts));
166 spin_lock_bh(&txq->axq_lock);
168 while ((skb = __skb_dequeue(&tid->buf_q))) {
169 fi = get_frame_info(skb);
172 spin_unlock_bh(&txq->axq_lock);
173 if (bf && fi->retries) {
174 list_add_tail(&bf->list, &bf_head);
175 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
176 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
178 ath_tx_send_normal(sc, txq, NULL, skb);
180 spin_lock_bh(&txq->axq_lock);
183 spin_unlock_bh(&txq->axq_lock);
186 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
191 index = ATH_BA_INDEX(tid->seq_start, seqno);
192 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
194 __clear_bit(cindex, tid->tx_buf);
196 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
197 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
198 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
202 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
207 index = ATH_BA_INDEX(tid->seq_start, seqno);
208 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
209 __set_bit(cindex, tid->tx_buf);
211 if (index >= ((tid->baw_tail - tid->baw_head) &
212 (ATH_TID_MAX_BUFS - 1))) {
213 tid->baw_tail = cindex;
214 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
219 * TODO: For frame(s) that are in the retry state, we will reuse the
220 * sequence number(s) without setting the retry bit. The
221 * alternative is to give up on these and BAR the receiver's window
224 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
225 struct ath_atx_tid *tid)
230 struct list_head bf_head;
231 struct ath_tx_status ts;
232 struct ath_frame_info *fi;
234 memset(&ts, 0, sizeof(ts));
235 INIT_LIST_HEAD(&bf_head);
237 while ((skb = __skb_dequeue(&tid->buf_q))) {
238 fi = get_frame_info(skb);
242 spin_unlock(&txq->axq_lock);
243 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
244 spin_lock(&txq->axq_lock);
248 list_add_tail(&bf->list, &bf_head);
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
253 spin_unlock(&txq->axq_lock);
254 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
255 spin_lock(&txq->axq_lock);
258 tid->seq_next = tid->seq_start;
259 tid->baw_tail = tid->baw_head;
262 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
265 struct ath_frame_info *fi = get_frame_info(skb);
266 struct ath_buf *bf = fi->bf;
267 struct ieee80211_hdr *hdr;
269 TX_STAT_INC(txq->axq_qnum, a_retries);
270 if (fi->retries++ > 0)
273 hdr = (struct ieee80211_hdr *)skb->data;
274 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
275 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
276 sizeof(*hdr), DMA_TO_DEVICE);
279 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
281 struct ath_buf *bf = NULL;
283 spin_lock_bh(&sc->tx.txbuflock);
285 if (unlikely(list_empty(&sc->tx.txbuf))) {
286 spin_unlock_bh(&sc->tx.txbuflock);
290 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
294 spin_unlock_bh(&sc->tx.txbuflock);
299 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
301 spin_lock_bh(&sc->tx.txbuflock);
302 list_add_tail(&bf->list, &sc->tx.txbuf);
303 spin_unlock_bh(&sc->tx.txbuflock);
306 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
310 tbf = ath_tx_get_buffer(sc);
314 ATH_TXBUF_RESET(tbf);
316 tbf->bf_mpdu = bf->bf_mpdu;
317 tbf->bf_buf_addr = bf->bf_buf_addr;
318 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
319 tbf->bf_state = bf->bf_state;
324 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
325 struct ath_tx_status *ts, int txok,
326 int *nframes, int *nbad)
328 struct ath_frame_info *fi;
330 u32 ba[WME_BA_BMP_SIZE >> 5];
337 isaggr = bf_isaggr(bf);
339 seq_st = ts->ts_seqnum;
340 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
344 fi = get_frame_info(bf->bf_mpdu);
345 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
348 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
356 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
357 struct ath_buf *bf, struct list_head *bf_q,
358 struct ath_tx_status *ts, int txok, bool retry)
360 struct ath_node *an = NULL;
362 struct ieee80211_sta *sta;
363 struct ieee80211_hw *hw = sc->hw;
364 struct ieee80211_hdr *hdr;
365 struct ieee80211_tx_info *tx_info;
366 struct ath_atx_tid *tid = NULL;
367 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
368 struct list_head bf_head;
369 struct sk_buff_head bf_pending;
370 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
371 u32 ba[WME_BA_BMP_SIZE >> 5];
372 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
373 bool rc_update = true, isba;
374 struct ieee80211_tx_rate rates[4];
375 struct ath_frame_info *fi;
378 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
381 hdr = (struct ieee80211_hdr *)skb->data;
383 tx_info = IEEE80211_SKB_CB(skb);
385 memcpy(rates, tx_info->control.rates, sizeof(rates));
389 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
393 INIT_LIST_HEAD(&bf_head);
395 bf_next = bf->bf_next;
397 if (!bf->bf_stale || bf_next != NULL)
398 list_move_tail(&bf->list, &bf_head);
400 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
408 an = (struct ath_node *)sta->drv_priv;
409 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
410 tid = ATH_AN_2_TID(an, tidno);
411 isba = ts->ts_flags & ATH9K_TX_BA;
414 * The hardware occasionally sends a tx status for the wrong TID.
415 * In this case, the BA status cannot be considered valid and all
416 * subframes need to be retransmitted
418 * Only BlockAcks have a TID and therefore normal Acks cannot be
421 if (isba && tidno != ts->tid)
424 isaggr = bf_isaggr(bf);
425 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
427 if (isaggr && txok) {
428 if (ts->ts_flags & ATH9K_TX_BA) {
429 seq_st = ts->ts_seqnum;
430 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
433 * AR5416 can become deaf/mute when BA
434 * issue happens. Chip needs to be reset.
435 * But AP code may have sychronization issues
436 * when perform internal reset in this routine.
437 * Only enable reset in STA mode for now.
439 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
444 __skb_queue_head_init(&bf_pending);
446 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
448 u16 seqno = bf->bf_state.seqno;
450 txfail = txpending = sendbar = 0;
451 bf_next = bf->bf_next;
454 tx_info = IEEE80211_SKB_CB(skb);
455 fi = get_frame_info(skb);
457 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
458 /* transmit completion, subframe is
459 * acked by block ack */
461 } else if (!isaggr && txok) {
462 /* transmit completion */
465 if ((tid->state & AGGR_CLEANUP) || !retry) {
467 * cleanup in progress, just fail
468 * the un-acked sub-frames
473 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
474 if (txok || !an->sleeping)
475 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
486 * Make sure the last desc is reclaimed if it
487 * not a holding desc.
489 INIT_LIST_HEAD(&bf_head);
490 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
491 bf_next != NULL || !bf_last->bf_stale)
492 list_move_tail(&bf->list, &bf_head);
494 if (!txpending || (tid->state & AGGR_CLEANUP)) {
496 * complete the acked-ones/xretried ones; update
499 spin_lock_bh(&txq->axq_lock);
500 ath_tx_update_baw(sc, tid, seqno);
501 spin_unlock_bh(&txq->axq_lock);
503 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
504 memcpy(tx_info->control.rates, rates, sizeof(rates));
505 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
509 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
512 /* retry the un-acked ones */
513 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
514 if (bf->bf_next == NULL && bf_last->bf_stale) {
517 tbf = ath_clone_txbuf(sc, bf_last);
519 * Update tx baw and complete the
520 * frame with failed status if we
524 spin_lock_bh(&txq->axq_lock);
525 ath_tx_update_baw(sc, tid, seqno);
526 spin_unlock_bh(&txq->axq_lock);
528 ath_tx_complete_buf(sc, bf, txq,
540 * Put this buffer to the temporary pending
541 * queue to retain ordering
543 __skb_queue_tail(&bf_pending, skb);
549 /* prepend un-acked frames to the beginning of the pending frame queue */
550 if (!skb_queue_empty(&bf_pending)) {
552 ieee80211_sta_set_buffered(sta, tid->tidno, true);
554 spin_lock_bh(&txq->axq_lock);
555 skb_queue_splice(&bf_pending, &tid->buf_q);
557 ath_tx_queue_tid(txq, tid);
559 if (ts->ts_status & ATH9K_TXERR_FILT)
560 tid->ac->clear_ps_filter = true;
562 spin_unlock_bh(&txq->axq_lock);
565 if (tid->state & AGGR_CLEANUP) {
566 ath_tx_flush_tid(sc, tid);
568 if (tid->baw_head == tid->baw_tail) {
569 tid->state &= ~AGGR_ADDBA_COMPLETE;
570 tid->state &= ~AGGR_CLEANUP;
577 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
578 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
582 static bool ath_lookup_legacy(struct ath_buf *bf)
585 struct ieee80211_tx_info *tx_info;
586 struct ieee80211_tx_rate *rates;
590 tx_info = IEEE80211_SKB_CB(skb);
591 rates = tx_info->control.rates;
593 for (i = 0; i < 4; i++) {
594 if (!rates[i].count || rates[i].idx < 0)
597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
604 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
605 struct ath_atx_tid *tid)
608 struct ieee80211_tx_info *tx_info;
609 struct ieee80211_tx_rate *rates;
610 u32 max_4ms_framelen, frmlen;
611 u16 aggr_limit, legacy = 0;
615 tx_info = IEEE80211_SKB_CB(skb);
616 rates = tx_info->control.rates;
619 * Find the lowest frame length among the rate series that will have a
620 * 4ms transmit duration.
621 * TODO - TXOP limit needs to be considered.
623 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
625 for (i = 0; i < 4; i++) {
626 if (rates[i].count) {
628 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
633 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
638 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
641 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
642 max_4ms_framelen = min(max_4ms_framelen, frmlen);
647 * limit aggregate size by the minimum rate if rate selected is
648 * not a probe rate, if rate selected is a probe rate then
649 * avoid aggregation of this packet.
651 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
654 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
655 aggr_limit = min((max_4ms_framelen * 3) / 8,
656 (u32)ATH_AMPDU_LIMIT_MAX);
658 aggr_limit = min(max_4ms_framelen,
659 (u32)ATH_AMPDU_LIMIT_MAX);
662 * h/w can accept aggregates up to 16 bit lengths (65535).
663 * The IE, however can hold up to 65536, which shows up here
664 * as zero. Ignore 65536 since we are constrained by hw.
666 if (tid->an->maxampdu)
667 aggr_limit = min(aggr_limit, tid->an->maxampdu);
673 * Returns the number of delimiters to be added to
674 * meet the minimum required mpdudensity.
676 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
677 struct ath_buf *bf, u16 frmlen,
680 #define FIRST_DESC_NDELIMS 60
681 struct sk_buff *skb = bf->bf_mpdu;
682 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
683 u32 nsymbits, nsymbols;
686 int width, streams, half_gi, ndelim, mindelim;
687 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
689 /* Select standard number of delimiters based on frame length alone */
690 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
693 * If encryption enabled, hardware requires some more padding between
695 * TODO - this could be improved to be dependent on the rate.
696 * The hardware can keep up at lower rates, but not higher rates
698 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
699 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
700 ndelim += ATH_AGGR_ENCRYPTDELIM;
703 * Add delimiter when using RTS/CTS with aggregation
704 * and non enterprise AR9003 card
706 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
707 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
708 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
711 * Convert desired mpdu density from microeconds to bytes based
712 * on highest rate in rate series (i.e. first rate) to determine
713 * required minimum length for subframe. Take into account
714 * whether high rate is 20 or 40Mhz and half or full GI.
716 * If there is no mpdu density restriction, no further calculation
720 if (tid->an->mpdudensity == 0)
723 rix = tx_info->control.rates[0].idx;
724 flags = tx_info->control.rates[0].flags;
725 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
726 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
729 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
731 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
736 streams = HT_RC_2_STREAMS(rix);
737 nsymbits = bits_per_symbol[rix % 8][width] * streams;
738 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
740 if (frmlen < minlen) {
741 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
742 ndelim = max(mindelim, ndelim);
748 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
750 struct ath_atx_tid *tid,
751 struct list_head *bf_q,
754 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
755 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
756 int rl = 0, nframes = 0, ndelim, prev_al = 0;
757 u16 aggr_limit = 0, al = 0, bpad = 0,
758 al_delta, h_baw = tid->baw_size / 2;
759 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
760 struct ieee80211_tx_info *tx_info;
761 struct ath_frame_info *fi;
766 skb = skb_peek(&tid->buf_q);
767 fi = get_frame_info(skb);
770 bf = ath_tx_setup_buffer(sc, txq, tid, skb, true);
775 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
776 seqno = bf->bf_state.seqno;
780 /* do not step over block-ack window */
781 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
782 status = ATH_AGGR_BAW_CLOSED;
787 aggr_limit = ath_lookup_rate(sc, bf, tid);
791 /* do not exceed aggregation limit */
792 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
795 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
796 ath_lookup_legacy(bf))) {
797 status = ATH_AGGR_LIMITED;
801 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
802 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
805 /* do not exceed subframe limit */
806 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
807 status = ATH_AGGR_LIMITED;
811 /* add padding for previous frame to aggregation length */
812 al += bpad + al_delta;
815 * Get the delimiters needed to meet the MPDU
816 * density for this node.
818 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
820 bpad = PADBYTES(al_delta) + (ndelim << 2);
825 /* link buffers of this frame to the aggregate */
827 ath_tx_addto_baw(sc, tid, seqno);
828 bf->bf_state.ndelim = ndelim;
830 __skb_unlink(skb, &tid->buf_q);
831 list_add_tail(&bf->list, bf_q);
833 bf_prev->bf_next = bf;
837 } while (!skb_queue_empty(&tid->buf_q));
847 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
848 * width - 0 for 20 MHz, 1 for 40 MHz
849 * half_gi - to use 4us v/s 3.6 us for symbol time
851 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
852 int width, int half_gi, bool shortPreamble)
854 u32 nbits, nsymbits, duration, nsymbols;
857 /* find number of symbols: PLCP + data */
858 streams = HT_RC_2_STREAMS(rix);
859 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
860 nsymbits = bits_per_symbol[rix % 8][width] * streams;
861 nsymbols = (nbits + nsymbits - 1) / nsymbits;
864 duration = SYMBOL_TIME(nsymbols);
866 duration = SYMBOL_TIME_HALFGI(nsymbols);
868 /* addup duration for legacy/ht training and signal fields */
869 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
874 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
875 struct ath_tx_info *info, int len)
877 struct ath_hw *ah = sc->sc_ah;
879 struct ieee80211_tx_info *tx_info;
880 struct ieee80211_tx_rate *rates;
881 const struct ieee80211_rate *rate;
882 struct ieee80211_hdr *hdr;
887 tx_info = IEEE80211_SKB_CB(skb);
888 rates = tx_info->control.rates;
889 hdr = (struct ieee80211_hdr *)skb->data;
891 /* set dur_update_en for l-sig computation except for PS-Poll frames */
892 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
895 * We check if Short Preamble is needed for the CTS rate by
896 * checking the BSS's global flag.
897 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
899 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
900 info->rtscts_rate = rate->hw_value;
901 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
902 info->rtscts_rate |= rate->hw_value_short;
904 for (i = 0; i < 4; i++) {
905 bool is_40, is_sgi, is_sp;
908 if (!rates[i].count || (rates[i].idx < 0))
912 info->rates[i].Tries = rates[i].count;
914 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
915 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
916 info->flags |= ATH9K_TXDESC_RTSENA;
917 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
918 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
919 info->flags |= ATH9K_TXDESC_CTSENA;
922 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
923 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
924 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
925 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
927 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
928 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
929 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
931 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
933 info->rates[i].Rate = rix | 0x80;
934 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
935 ah->txchainmask, info->rates[i].Rate);
936 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
937 is_40, is_sgi, is_sp);
938 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
939 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
944 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
945 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
946 !(rate->flags & IEEE80211_RATE_ERP_G))
947 phy = WLAN_RC_PHY_CCK;
949 phy = WLAN_RC_PHY_OFDM;
951 info->rates[i].Rate = rate->hw_value;
952 if (rate->hw_value_short) {
953 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
954 info->rates[i].Rate |= rate->hw_value_short;
959 if (bf->bf_state.bfs_paprd)
960 info->rates[i].ChSel = ah->txchainmask;
962 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
963 ah->txchainmask, info->rates[i].Rate);
965 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
966 phy, rate->bitrate * 100, len, rix, is_sp);
969 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
970 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
971 info->flags &= ~ATH9K_TXDESC_RTSENA;
973 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
974 if (info->flags & ATH9K_TXDESC_RTSENA)
975 info->flags &= ~ATH9K_TXDESC_CTSENA;
978 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
980 struct ieee80211_hdr *hdr;
981 enum ath9k_pkt_type htype;
984 hdr = (struct ieee80211_hdr *)skb->data;
985 fc = hdr->frame_control;
987 if (ieee80211_is_beacon(fc))
988 htype = ATH9K_PKT_TYPE_BEACON;
989 else if (ieee80211_is_probe_resp(fc))
990 htype = ATH9K_PKT_TYPE_PROBE_RESP;
991 else if (ieee80211_is_atim(fc))
992 htype = ATH9K_PKT_TYPE_ATIM;
993 else if (ieee80211_is_pspoll(fc))
994 htype = ATH9K_PKT_TYPE_PSPOLL;
996 htype = ATH9K_PKT_TYPE_NORMAL;
1001 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1002 struct ath_txq *txq, int len)
1004 struct ath_hw *ah = sc->sc_ah;
1005 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1006 struct ath_buf *bf_first = bf;
1007 struct ath_tx_info info;
1008 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1010 memset(&info, 0, sizeof(info));
1011 info.is_first = true;
1012 info.is_last = true;
1013 info.txpower = MAX_RATE_POWER;
1014 info.qcu = txq->axq_qnum;
1016 info.flags = ATH9K_TXDESC_INTREQ;
1017 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1018 info.flags |= ATH9K_TXDESC_NOACK;
1019 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1020 info.flags |= ATH9K_TXDESC_LDPC;
1022 ath_buf_set_rate(sc, bf, &info, len);
1024 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1025 info.flags |= ATH9K_TXDESC_CLRDMASK;
1027 if (bf->bf_state.bfs_paprd)
1028 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1032 struct sk_buff *skb = bf->bf_mpdu;
1033 struct ath_frame_info *fi = get_frame_info(skb);
1035 info.type = get_hw_packet_type(skb);
1037 info.link = bf->bf_next->bf_daddr;
1041 info.buf_addr[0] = bf->bf_buf_addr;
1042 info.buf_len[0] = skb->len;
1043 info.pkt_len = fi->framelen;
1044 info.keyix = fi->keyix;
1045 info.keytype = fi->keytype;
1049 info.aggr = AGGR_BUF_FIRST;
1050 else if (!bf->bf_next)
1051 info.aggr = AGGR_BUF_LAST;
1053 info.aggr = AGGR_BUF_MIDDLE;
1055 info.ndelim = bf->bf_state.ndelim;
1056 info.aggr_len = len;
1059 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1064 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1065 struct ath_atx_tid *tid)
1068 enum ATH_AGGR_STATUS status;
1069 struct ieee80211_tx_info *tx_info;
1070 struct list_head bf_q;
1074 if (skb_queue_empty(&tid->buf_q))
1077 INIT_LIST_HEAD(&bf_q);
1079 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1082 * no frames picked up to be aggregated;
1083 * block-ack window is not open.
1085 if (list_empty(&bf_q))
1088 bf = list_first_entry(&bf_q, struct ath_buf, list);
1089 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1090 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1092 if (tid->ac->clear_ps_filter) {
1093 tid->ac->clear_ps_filter = false;
1094 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1096 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1099 /* if only one frame, send as non-aggregate */
1100 if (bf == bf->bf_lastbf) {
1101 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1102 bf->bf_state.bf_type = BUF_AMPDU;
1104 TX_STAT_INC(txq->axq_qnum, a_aggr);
1107 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1108 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1109 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1110 status != ATH_AGGR_BAW_CLOSED);
1113 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1116 struct ath_atx_tid *txtid;
1117 struct ath_node *an;
1119 an = (struct ath_node *)sta->drv_priv;
1120 txtid = ATH_AN_2_TID(an, tid);
1122 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1125 txtid->state |= AGGR_ADDBA_PROGRESS;
1126 txtid->paused = true;
1127 *ssn = txtid->seq_start = txtid->seq_next;
1129 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1130 txtid->baw_head = txtid->baw_tail = 0;
1135 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1137 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1138 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1139 struct ath_txq *txq = txtid->ac->txq;
1141 if (txtid->state & AGGR_CLEANUP)
1144 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1145 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1149 spin_lock_bh(&txq->axq_lock);
1150 txtid->paused = true;
1153 * If frames are still being transmitted for this TID, they will be
1154 * cleaned up during tx completion. To prevent race conditions, this
1155 * TID can only be reused after all in-progress subframes have been
1158 if (txtid->baw_head != txtid->baw_tail)
1159 txtid->state |= AGGR_CLEANUP;
1161 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1162 spin_unlock_bh(&txq->axq_lock);
1164 ath_tx_flush_tid(sc, txtid);
1167 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1168 struct ath_node *an)
1170 struct ath_atx_tid *tid;
1171 struct ath_atx_ac *ac;
1172 struct ath_txq *txq;
1176 for (tidno = 0, tid = &an->tid[tidno];
1177 tidno < WME_NUM_TID; tidno++, tid++) {
1182 spin_lock_bh(&txq->axq_lock);
1185 spin_unlock_bh(&txq->axq_lock);
1189 buffered = !skb_queue_empty(&tid->buf_q);
1192 list_del(&tid->list);
1196 list_del(&ac->list);
1199 spin_unlock_bh(&txq->axq_lock);
1201 ieee80211_sta_set_buffered(sta, tidno, buffered);
1205 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1207 struct ath_atx_tid *tid;
1208 struct ath_atx_ac *ac;
1209 struct ath_txq *txq;
1212 for (tidno = 0, tid = &an->tid[tidno];
1213 tidno < WME_NUM_TID; tidno++, tid++) {
1218 spin_lock_bh(&txq->axq_lock);
1219 ac->clear_ps_filter = true;
1221 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1222 ath_tx_queue_tid(txq, tid);
1223 ath_txq_schedule(sc, txq);
1226 spin_unlock_bh(&txq->axq_lock);
1230 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1232 struct ath_atx_tid *txtid;
1233 struct ath_node *an;
1235 an = (struct ath_node *)sta->drv_priv;
1237 if (sc->sc_flags & SC_OP_TXAGGR) {
1238 txtid = ATH_AN_2_TID(an, tid);
1240 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1241 txtid->state |= AGGR_ADDBA_COMPLETE;
1242 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1243 ath_tx_resume_tid(sc, txtid);
1247 /********************/
1248 /* Queue Management */
1249 /********************/
1251 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1252 struct ath_txq *txq)
1254 struct ath_atx_ac *ac, *ac_tmp;
1255 struct ath_atx_tid *tid, *tid_tmp;
1257 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1258 list_del(&ac->list);
1260 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1261 list_del(&tid->list);
1263 ath_tid_drain(sc, txq, tid);
1268 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1270 struct ath_hw *ah = sc->sc_ah;
1271 struct ath9k_tx_queue_info qi;
1272 static const int subtype_txq_to_hwq[] = {
1273 [WME_AC_BE] = ATH_TXQ_AC_BE,
1274 [WME_AC_BK] = ATH_TXQ_AC_BK,
1275 [WME_AC_VI] = ATH_TXQ_AC_VI,
1276 [WME_AC_VO] = ATH_TXQ_AC_VO,
1280 memset(&qi, 0, sizeof(qi));
1281 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1282 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1283 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1284 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1285 qi.tqi_physCompBuf = 0;
1288 * Enable interrupts only for EOL and DESC conditions.
1289 * We mark tx descriptors to receive a DESC interrupt
1290 * when a tx queue gets deep; otherwise waiting for the
1291 * EOL to reap descriptors. Note that this is done to
1292 * reduce interrupt load and this only defers reaping
1293 * descriptors, never transmitting frames. Aside from
1294 * reducing interrupts this also permits more concurrency.
1295 * The only potential downside is if the tx queue backs
1296 * up in which case the top half of the kernel may backup
1297 * due to a lack of tx descriptors.
1299 * The UAPSD queue is an exception, since we take a desc-
1300 * based intr on the EOSP frames.
1302 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1303 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1304 TXQ_FLAG_TXERRINT_ENABLE;
1306 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1307 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1309 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1310 TXQ_FLAG_TXDESCINT_ENABLE;
1312 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1313 if (axq_qnum == -1) {
1315 * NB: don't print a message, this happens
1316 * normally on parts with too few tx queues
1320 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1321 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1323 txq->axq_qnum = axq_qnum;
1324 txq->mac80211_qnum = -1;
1325 txq->axq_link = NULL;
1326 INIT_LIST_HEAD(&txq->axq_q);
1327 INIT_LIST_HEAD(&txq->axq_acq);
1328 spin_lock_init(&txq->axq_lock);
1330 txq->axq_ampdu_depth = 0;
1331 txq->axq_tx_inprogress = false;
1332 sc->tx.txqsetup |= 1<<axq_qnum;
1334 txq->txq_headidx = txq->txq_tailidx = 0;
1335 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1336 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1338 return &sc->tx.txq[axq_qnum];
1341 int ath_txq_update(struct ath_softc *sc, int qnum,
1342 struct ath9k_tx_queue_info *qinfo)
1344 struct ath_hw *ah = sc->sc_ah;
1346 struct ath9k_tx_queue_info qi;
1348 if (qnum == sc->beacon.beaconq) {
1350 * XXX: for beacon queue, we just save the parameter.
1351 * It will be picked up by ath_beaconq_config when
1354 sc->beacon.beacon_qi = *qinfo;
1358 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1360 ath9k_hw_get_txq_props(ah, qnum, &qi);
1361 qi.tqi_aifs = qinfo->tqi_aifs;
1362 qi.tqi_cwmin = qinfo->tqi_cwmin;
1363 qi.tqi_cwmax = qinfo->tqi_cwmax;
1364 qi.tqi_burstTime = qinfo->tqi_burstTime;
1365 qi.tqi_readyTime = qinfo->tqi_readyTime;
1367 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1368 ath_err(ath9k_hw_common(sc->sc_ah),
1369 "Unable to update hardware queue %u!\n", qnum);
1372 ath9k_hw_resettxqueue(ah, qnum);
1378 int ath_cabq_update(struct ath_softc *sc)
1380 struct ath9k_tx_queue_info qi;
1381 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1382 int qnum = sc->beacon.cabq->axq_qnum;
1384 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1386 * Ensure the readytime % is within the bounds.
1388 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1389 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1390 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1391 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1393 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1394 sc->config.cabqReadytime) / 100;
1395 ath_txq_update(sc, qnum, &qi);
1400 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1402 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1403 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1406 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1407 struct list_head *list, bool retry_tx)
1408 __releases(txq->axq_lock)
1409 __acquires(txq->axq_lock)
1411 struct ath_buf *bf, *lastbf;
1412 struct list_head bf_head;
1413 struct ath_tx_status ts;
1415 memset(&ts, 0, sizeof(ts));
1416 ts.ts_status = ATH9K_TX_FLUSH;
1417 INIT_LIST_HEAD(&bf_head);
1419 while (!list_empty(list)) {
1420 bf = list_first_entry(list, struct ath_buf, list);
1423 list_del(&bf->list);
1425 ath_tx_return_buffer(sc, bf);
1429 lastbf = bf->bf_lastbf;
1430 list_cut_position(&bf_head, list, &lastbf->list);
1433 if (bf_is_ampdu_not_probing(bf))
1434 txq->axq_ampdu_depth--;
1436 spin_unlock_bh(&txq->axq_lock);
1438 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1441 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1442 spin_lock_bh(&txq->axq_lock);
1447 * Drain a given TX queue (could be Beacon or Data)
1449 * This assumes output has been stopped and
1450 * we do not need to block ath_tx_tasklet.
1452 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1454 spin_lock_bh(&txq->axq_lock);
1455 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1456 int idx = txq->txq_tailidx;
1458 while (!list_empty(&txq->txq_fifo[idx])) {
1459 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1462 INCR(idx, ATH_TXFIFO_DEPTH);
1464 txq->txq_tailidx = idx;
1467 txq->axq_link = NULL;
1468 txq->axq_tx_inprogress = false;
1469 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1471 /* flush any pending frames if aggregation is enabled */
1472 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1473 ath_txq_drain_pending_buffers(sc, txq);
1475 spin_unlock_bh(&txq->axq_lock);
1478 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1480 struct ath_hw *ah = sc->sc_ah;
1481 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1482 struct ath_txq *txq;
1486 if (sc->sc_flags & SC_OP_INVALID)
1489 ath9k_hw_abort_tx_dma(ah);
1491 /* Check if any queue remains active */
1492 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1493 if (!ATH_TXQ_SETUP(sc, i))
1496 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1501 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1503 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1504 if (!ATH_TXQ_SETUP(sc, i))
1508 * The caller will resume queues with ieee80211_wake_queues.
1509 * Mark the queue as not stopped to prevent ath_tx_complete
1510 * from waking the queue too early.
1512 txq = &sc->tx.txq[i];
1513 txq->stopped = false;
1514 ath_draintxq(sc, txq, retry_tx);
1520 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1522 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1523 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1526 /* For each axq_acq entry, for each tid, try to schedule packets
1527 * for transmit until ampdu_depth has reached min Q depth.
1529 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1531 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1532 struct ath_atx_tid *tid, *last_tid;
1534 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1535 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1538 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1539 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1541 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1542 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1543 list_del(&ac->list);
1546 while (!list_empty(&ac->tid_q)) {
1547 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1549 list_del(&tid->list);
1555 ath_tx_sched_aggr(sc, txq, tid);
1558 * add tid to round-robin queue if more frames
1559 * are pending for the tid
1561 if (!skb_queue_empty(&tid->buf_q))
1562 ath_tx_queue_tid(txq, tid);
1564 if (tid == last_tid ||
1565 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1569 if (!list_empty(&ac->tid_q)) {
1572 list_add_tail(&ac->list, &txq->axq_acq);
1576 if (ac == last_ac ||
1577 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1587 * Insert a chain of ath_buf (descriptors) on a txq and
1588 * assume the descriptors are already chained together by caller.
1590 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1591 struct list_head *head, bool internal)
1593 struct ath_hw *ah = sc->sc_ah;
1594 struct ath_common *common = ath9k_hw_common(ah);
1595 struct ath_buf *bf, *bf_last;
1596 bool puttxbuf = false;
1600 * Insert the frame on the outbound list and
1601 * pass it on to the hardware.
1604 if (list_empty(head))
1607 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1608 bf = list_first_entry(head, struct ath_buf, list);
1609 bf_last = list_entry(head->prev, struct ath_buf, list);
1611 ath_dbg(common, ATH_DBG_QUEUE,
1612 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1614 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1615 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1616 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1619 list_splice_tail_init(head, &txq->axq_q);
1621 if (txq->axq_link) {
1622 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1623 ath_dbg(common, ATH_DBG_XMIT,
1624 "link[%u] (%p)=%llx (%p)\n",
1625 txq->axq_qnum, txq->axq_link,
1626 ito64(bf->bf_daddr), bf->bf_desc);
1630 txq->axq_link = bf_last->bf_desc;
1634 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1635 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1636 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1637 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1641 TX_STAT_INC(txq->axq_qnum, txstart);
1642 ath9k_hw_txstart(ah, txq->axq_qnum);
1647 if (bf_is_ampdu_not_probing(bf))
1648 txq->axq_ampdu_depth++;
1652 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1653 struct sk_buff *skb, struct ath_tx_control *txctl)
1655 struct ath_frame_info *fi = get_frame_info(skb);
1656 struct list_head bf_head;
1660 * Do not queue to h/w when any of the following conditions is true:
1661 * - there are pending frames in software queue
1662 * - the TID is currently paused for ADDBA/BAR request
1663 * - seqno is not within block-ack window
1664 * - h/w queue depth exceeds low water mark
1666 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1667 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1668 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1670 * Add this frame to software queue for scheduling later
1673 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1674 __skb_queue_tail(&tid->buf_q, skb);
1675 if (!txctl->an || !txctl->an->sleeping)
1676 ath_tx_queue_tid(txctl->txq, tid);
1680 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1684 bf->bf_state.bf_type = BUF_AMPDU;
1685 INIT_LIST_HEAD(&bf_head);
1686 list_add(&bf->list, &bf_head);
1688 /* Add sub-frame to BAW */
1689 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1691 /* Queue to h/w without aggregation */
1692 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1694 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1695 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1698 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1699 struct ath_atx_tid *tid, struct sk_buff *skb)
1701 struct ath_frame_info *fi = get_frame_info(skb);
1702 struct list_head bf_head;
1707 bf = ath_tx_setup_buffer(sc, txq, tid, skb, false);
1712 INIT_LIST_HEAD(&bf_head);
1713 list_add_tail(&bf->list, &bf_head);
1714 bf->bf_state.bf_type = 0;
1716 /* update starting sequence number for subsequent ADDBA request */
1718 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1722 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1723 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1724 TX_STAT_INC(txq->axq_qnum, queued);
1727 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1730 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1731 struct ieee80211_sta *sta = tx_info->control.sta;
1732 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1733 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1734 struct ath_frame_info *fi = get_frame_info(skb);
1735 struct ath_node *an = NULL;
1736 enum ath9k_key_type keytype;
1738 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1741 an = (struct ath_node *) sta->drv_priv;
1743 memset(fi, 0, sizeof(*fi));
1745 fi->keyix = hw_key->hw_key_idx;
1746 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1747 fi->keyix = an->ps_key;
1749 fi->keyix = ATH9K_TXKEYIX_INVALID;
1750 fi->keytype = keytype;
1751 fi->framelen = framelen;
1754 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1756 struct ath_hw *ah = sc->sc_ah;
1757 struct ath9k_channel *curchan = ah->curchan;
1758 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1759 (curchan->channelFlags & CHANNEL_5GHZ) &&
1760 (chainmask == 0x7) && (rate < 0x90))
1767 * Assign a descriptor (and sequence number if necessary,
1768 * and map buffer for DMA. Frees skb on error
1770 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1771 struct ath_txq *txq,
1772 struct ath_atx_tid *tid,
1773 struct sk_buff *skb,
1776 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1777 struct ath_frame_info *fi = get_frame_info(skb);
1778 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1782 bf = ath_tx_get_buffer(sc);
1784 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1788 ATH_TXBUF_RESET(bf);
1791 seqno = tid->seq_next;
1792 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1793 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1794 bf->bf_state.seqno = seqno;
1799 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1800 skb->len, DMA_TO_DEVICE);
1801 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1803 bf->bf_buf_addr = 0;
1804 ath_err(ath9k_hw_common(sc->sc_ah),
1805 "dma_mapping_error() on TX\n");
1806 ath_tx_return_buffer(sc, bf);
1816 __skb_unlink(skb, &tid->buf_q);
1817 dev_kfree_skb_any(skb);
1821 /* FIXME: tx power */
1822 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1823 struct ath_tx_control *txctl)
1825 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1826 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1827 struct ath_atx_tid *tid = NULL;
1831 spin_lock_bh(&txctl->txq->axq_lock);
1832 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1833 ieee80211_is_data_qos(hdr->frame_control)) {
1834 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1835 IEEE80211_QOS_CTL_TID_MASK;
1836 tid = ATH_AN_2_TID(txctl->an, tidno);
1838 WARN_ON(tid->ac->txq != txctl->txq);
1841 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1843 * Try aggregation if it's a unicast data frame
1844 * and the destination is HT capable.
1846 ath_tx_send_ampdu(sc, tid, skb, txctl);
1848 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1852 bf->bf_state.bfs_paprd = txctl->paprd;
1855 bf->bf_state.bfs_paprd_timestamp = jiffies;
1857 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1861 spin_unlock_bh(&txctl->txq->axq_lock);
1864 /* Upon failure caller should free skb */
1865 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1866 struct ath_tx_control *txctl)
1868 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1869 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1870 struct ieee80211_sta *sta = info->control.sta;
1871 struct ieee80211_vif *vif = info->control.vif;
1872 struct ath_softc *sc = hw->priv;
1873 struct ath_txq *txq = txctl->txq;
1874 int padpos, padsize;
1875 int frmlen = skb->len + FCS_LEN;
1878 /* NOTE: sta can be NULL according to net/mac80211.h */
1880 txctl->an = (struct ath_node *)sta->drv_priv;
1882 if (info->control.hw_key)
1883 frmlen += info->control.hw_key->icv_len;
1886 * As a temporary workaround, assign seq# here; this will likely need
1887 * to be cleaned up to work better with Beacon transmission and virtual
1890 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1891 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1892 sc->tx.seq_no += 0x10;
1893 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1894 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1897 /* Add the padding after the header if this is not already done */
1898 padpos = ath9k_cmn_padpos(hdr->frame_control);
1899 padsize = padpos & 3;
1900 if (padsize && skb->len > padpos) {
1901 if (skb_headroom(skb) < padsize)
1904 skb_push(skb, padsize);
1905 memmove(skb->data, skb->data + padsize, padpos);
1906 hdr = (struct ieee80211_hdr *) skb->data;
1909 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1910 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1911 !ieee80211_is_data(hdr->frame_control))
1912 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1914 setup_frame_info(hw, skb, frmlen);
1917 * At this point, the vif, hw_key and sta pointers in the tx control
1918 * info are no longer valid (overwritten by the ath_frame_info data.
1921 q = skb_get_queue_mapping(skb);
1922 spin_lock_bh(&txq->axq_lock);
1923 if (txq == sc->tx.txq_map[q] &&
1924 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1925 ieee80211_stop_queue(sc->hw, q);
1928 spin_unlock_bh(&txq->axq_lock);
1930 ath_tx_start_dma(sc, skb, txctl);
1938 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1939 int tx_flags, struct ath_txq *txq)
1941 struct ieee80211_hw *hw = sc->hw;
1942 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1943 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1944 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1945 int q, padpos, padsize;
1947 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1949 if (tx_flags & ATH_TX_BAR)
1950 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1952 if (!(tx_flags & ATH_TX_ERROR))
1953 /* Frame was ACKed */
1954 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1956 padpos = ath9k_cmn_padpos(hdr->frame_control);
1957 padsize = padpos & 3;
1958 if (padsize && skb->len>padpos+padsize) {
1960 * Remove MAC header padding before giving the frame back to
1963 memmove(skb->data + padsize, skb->data, padpos);
1964 skb_pull(skb, padsize);
1967 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1968 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1969 ath_dbg(common, ATH_DBG_PS,
1970 "Going back to sleep after having received TX status (0x%lx)\n",
1971 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1973 PS_WAIT_FOR_PSPOLL_DATA |
1974 PS_WAIT_FOR_TX_ACK));
1977 q = skb_get_queue_mapping(skb);
1978 if (txq == sc->tx.txq_map[q]) {
1979 spin_lock_bh(&txq->axq_lock);
1980 if (WARN_ON(--txq->pending_frames < 0))
1981 txq->pending_frames = 0;
1983 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1984 ieee80211_wake_queue(sc->hw, q);
1987 spin_unlock_bh(&txq->axq_lock);
1990 ieee80211_tx_status(hw, skb);
1993 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1994 struct ath_txq *txq, struct list_head *bf_q,
1995 struct ath_tx_status *ts, int txok, int sendbar)
1997 struct sk_buff *skb = bf->bf_mpdu;
1998 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1999 unsigned long flags;
2003 tx_flags = ATH_TX_BAR;
2006 tx_flags |= ATH_TX_ERROR;
2008 if (ts->ts_status & ATH9K_TXERR_FILT)
2009 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2011 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2012 bf->bf_buf_addr = 0;
2014 if (bf->bf_state.bfs_paprd) {
2015 if (time_after(jiffies,
2016 bf->bf_state.bfs_paprd_timestamp +
2017 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2018 dev_kfree_skb_any(skb);
2020 complete(&sc->paprd_complete);
2022 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2023 ath_tx_complete(sc, skb, tx_flags, txq);
2025 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2026 * accidentally reference it later.
2031 * Return the list of ath_buf of this mpdu to free queue
2033 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2034 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2035 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2038 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2039 struct ath_tx_status *ts, int nframes, int nbad,
2042 struct sk_buff *skb = bf->bf_mpdu;
2043 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2044 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2045 struct ieee80211_hw *hw = sc->hw;
2046 struct ath_hw *ah = sc->sc_ah;
2050 tx_info->status.ack_signal = ts->ts_rssi;
2052 tx_rateindex = ts->ts_rateindex;
2053 WARN_ON(tx_rateindex >= hw->max_rates);
2055 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2056 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2058 BUG_ON(nbad > nframes);
2060 tx_info->status.ampdu_len = nframes;
2061 tx_info->status.ampdu_ack_len = nframes - nbad;
2063 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2064 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2066 * If an underrun error is seen assume it as an excessive
2067 * retry only if max frame trigger level has been reached
2068 * (2 KB for single stream, and 4 KB for dual stream).
2069 * Adjust the long retry as if the frame was tried
2070 * hw->max_rate_tries times to affect how rate control updates
2071 * PER for the failed rate.
2072 * In case of congestion on the bus penalizing this type of
2073 * underruns should help hardware actually transmit new frames
2074 * successfully by eventually preferring slower rates.
2075 * This itself should also alleviate congestion on the bus.
2077 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2078 ATH9K_TX_DELIM_UNDERRUN)) &&
2079 ieee80211_is_data(hdr->frame_control) &&
2080 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2081 tx_info->status.rates[tx_rateindex].count =
2085 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2086 tx_info->status.rates[i].count = 0;
2087 tx_info->status.rates[i].idx = -1;
2090 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2093 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2094 struct ath_tx_status *ts, struct ath_buf *bf,
2095 struct list_head *bf_head)
2096 __releases(txq->axq_lock)
2097 __acquires(txq->axq_lock)
2102 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2103 txq->axq_tx_inprogress = false;
2104 if (bf_is_ampdu_not_probing(bf))
2105 txq->axq_ampdu_depth--;
2107 spin_unlock_bh(&txq->axq_lock);
2109 if (!bf_isampdu(bf)) {
2110 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2111 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2113 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2115 spin_lock_bh(&txq->axq_lock);
2117 if (sc->sc_flags & SC_OP_TXAGGR)
2118 ath_txq_schedule(sc, txq);
2121 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2123 struct ath_hw *ah = sc->sc_ah;
2124 struct ath_common *common = ath9k_hw_common(ah);
2125 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2126 struct list_head bf_head;
2127 struct ath_desc *ds;
2128 struct ath_tx_status ts;
2131 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2132 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2135 spin_lock_bh(&txq->axq_lock);
2137 if (work_pending(&sc->hw_reset_work))
2140 if (list_empty(&txq->axq_q)) {
2141 txq->axq_link = NULL;
2142 if (sc->sc_flags & SC_OP_TXAGGR)
2143 ath_txq_schedule(sc, txq);
2146 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2149 * There is a race condition that a BH gets scheduled
2150 * after sw writes TxE and before hw re-load the last
2151 * descriptor to get the newly chained one.
2152 * Software must keep the last DONE descriptor as a
2153 * holding descriptor - software does so by marking
2154 * it with the STALE flag.
2159 if (list_is_last(&bf_held->list, &txq->axq_q))
2162 bf = list_entry(bf_held->list.next, struct ath_buf,
2166 lastbf = bf->bf_lastbf;
2167 ds = lastbf->bf_desc;
2169 memset(&ts, 0, sizeof(ts));
2170 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2171 if (status == -EINPROGRESS)
2174 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2177 * Remove ath_buf's of the same transmit unit from txq,
2178 * however leave the last descriptor back as the holding
2179 * descriptor for hw.
2181 lastbf->bf_stale = true;
2182 INIT_LIST_HEAD(&bf_head);
2183 if (!list_is_singular(&lastbf->list))
2184 list_cut_position(&bf_head,
2185 &txq->axq_q, lastbf->list.prev);
2188 list_del(&bf_held->list);
2189 ath_tx_return_buffer(sc, bf_held);
2192 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2194 spin_unlock_bh(&txq->axq_lock);
2197 static void ath_tx_complete_poll_work(struct work_struct *work)
2199 struct ath_softc *sc = container_of(work, struct ath_softc,
2200 tx_complete_work.work);
2201 struct ath_txq *txq;
2203 bool needreset = false;
2204 #ifdef CONFIG_ATH9K_DEBUGFS
2205 sc->tx_complete_poll_work_seen++;
2208 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2209 if (ATH_TXQ_SETUP(sc, i)) {
2210 txq = &sc->tx.txq[i];
2211 spin_lock_bh(&txq->axq_lock);
2212 if (txq->axq_depth) {
2213 if (txq->axq_tx_inprogress) {
2215 spin_unlock_bh(&txq->axq_lock);
2218 txq->axq_tx_inprogress = true;
2221 spin_unlock_bh(&txq->axq_lock);
2225 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2226 "tx hung, resetting the chip\n");
2227 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2228 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2231 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2232 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2237 void ath_tx_tasklet(struct ath_softc *sc)
2240 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2242 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2244 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2245 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2246 ath_tx_processq(sc, &sc->tx.txq[i]);
2250 void ath_tx_edma_tasklet(struct ath_softc *sc)
2252 struct ath_tx_status ts;
2253 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2254 struct ath_hw *ah = sc->sc_ah;
2255 struct ath_txq *txq;
2256 struct ath_buf *bf, *lastbf;
2257 struct list_head bf_head;
2261 if (work_pending(&sc->hw_reset_work))
2264 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2265 if (status == -EINPROGRESS)
2267 if (status == -EIO) {
2268 ath_dbg(common, ATH_DBG_XMIT,
2269 "Error processing tx status\n");
2273 /* Skip beacon completions */
2274 if (ts.qid == sc->beacon.beaconq)
2277 txq = &sc->tx.txq[ts.qid];
2279 spin_lock_bh(&txq->axq_lock);
2281 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2282 spin_unlock_bh(&txq->axq_lock);
2286 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2287 struct ath_buf, list);
2288 lastbf = bf->bf_lastbf;
2290 INIT_LIST_HEAD(&bf_head);
2291 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2294 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2295 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2297 if (!list_empty(&txq->axq_q)) {
2298 struct list_head bf_q;
2300 INIT_LIST_HEAD(&bf_q);
2301 txq->axq_link = NULL;
2302 list_splice_tail_init(&txq->axq_q, &bf_q);
2303 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2307 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2308 spin_unlock_bh(&txq->axq_lock);
2316 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2318 struct ath_descdma *dd = &sc->txsdma;
2319 u8 txs_len = sc->sc_ah->caps.txs_len;
2321 dd->dd_desc_len = size * txs_len;
2322 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2323 &dd->dd_desc_paddr, GFP_KERNEL);
2330 static int ath_tx_edma_init(struct ath_softc *sc)
2334 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2336 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2337 sc->txsdma.dd_desc_paddr,
2338 ATH_TXSTATUS_RING_SIZE);
2343 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2345 struct ath_descdma *dd = &sc->txsdma;
2347 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2351 int ath_tx_init(struct ath_softc *sc, int nbufs)
2353 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2356 spin_lock_init(&sc->tx.txbuflock);
2358 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2362 "Failed to allocate tx descriptors: %d\n", error);
2366 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2367 "beacon", ATH_BCBUF, 1, 1);
2370 "Failed to allocate beacon descriptors: %d\n", error);
2374 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2376 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2377 error = ath_tx_edma_init(sc);
2389 void ath_tx_cleanup(struct ath_softc *sc)
2391 if (sc->beacon.bdma.dd_desc_len != 0)
2392 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2394 if (sc->tx.txdma.dd_desc_len != 0)
2395 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2397 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2398 ath_tx_edma_cleanup(sc);
2401 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2403 struct ath_atx_tid *tid;
2404 struct ath_atx_ac *ac;
2407 for (tidno = 0, tid = &an->tid[tidno];
2408 tidno < WME_NUM_TID;
2412 tid->seq_start = tid->seq_next = 0;
2413 tid->baw_size = WME_MAX_BA;
2414 tid->baw_head = tid->baw_tail = 0;
2416 tid->paused = false;
2417 tid->state &= ~AGGR_CLEANUP;
2418 __skb_queue_head_init(&tid->buf_q);
2419 acno = TID_TO_WME_AC(tidno);
2420 tid->ac = &an->ac[acno];
2421 tid->state &= ~AGGR_ADDBA_COMPLETE;
2422 tid->state &= ~AGGR_ADDBA_PROGRESS;
2425 for (acno = 0, ac = &an->ac[acno];
2426 acno < WME_NUM_AC; acno++, ac++) {
2428 ac->clear_ps_filter = true;
2429 ac->txq = sc->tx.txq_map[acno];
2430 INIT_LIST_HEAD(&ac->tid_q);
2434 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2436 struct ath_atx_ac *ac;
2437 struct ath_atx_tid *tid;
2438 struct ath_txq *txq;
2441 for (tidno = 0, tid = &an->tid[tidno];
2442 tidno < WME_NUM_TID; tidno++, tid++) {
2447 spin_lock_bh(&txq->axq_lock);
2450 list_del(&tid->list);
2455 list_del(&ac->list);
2456 tid->ac->sched = false;
2459 ath_tid_drain(sc, txq, tid);
2460 tid->state &= ~AGGR_ADDBA_COMPLETE;
2461 tid->state &= ~AGGR_CLEANUP;
2463 spin_unlock_bh(&txq->axq_lock);