drivers/net/wireless/ath/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/nl80211.h>
  20 #include <linux/pci.h>
  21 #include <linux/pci-aspm.h>
  22 #include <linux/ath9k_platform.h>
  23 #include <linux/module.h>
  24 #include "ath9k.h"
  25
  26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
  27         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  28         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  30         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  31         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32
  33         /* AR9285 card for Asus */
  34         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  35                          0x002B,
  36                          PCI_VENDOR_ID_AZWAVE,
  37                          0x2C37),
  38           .driver_data = ATH9K_PCI_BT_ANT_DIV },
  39
  40         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  41         { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
  42         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
  43         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
  44         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
  45
  46         /* PCI-E CUS198 */
  47         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  48                          0x0032,
  49                          PCI_VENDOR_ID_AZWAVE,
  50                          0x2086),
  51           .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
  52         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  53                          0x0032,
  54                          PCI_VENDOR_ID_AZWAVE,
  55                          0x1237),
  56           .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
  57         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  58                          0x0032,
  59                          PCI_VENDOR_ID_AZWAVE,
  60                          0x2126),
  61           .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
  62
  63         /* PCI-E CUS230 */
  64         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  65                          0x0032,
  66                          PCI_VENDOR_ID_AZWAVE,
  67                          0x2152),
  68           .driver_data = ATH9K_PCI_CUS230 | ATH9K_PCI_BT_ANT_DIV },
  69         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  70                          0x0032,
  71                          PCI_VENDOR_ID_FOXCONN,
  72                          0xE075),
  73           .driver_data = ATH9K_PCI_CUS230 | ATH9K_PCI_BT_ANT_DIV },
  74
  75         /* WB225 */
  76         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  77                          0x0032,
  78                          PCI_VENDOR_ID_ATHEROS,
  79                          0x3119),
  80           .driver_data = ATH9K_PCI_BT_ANT_DIV },
  81         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  82                          0x0032,
  83                          PCI_VENDOR_ID_ATHEROS,
  84                          0x3122),
  85           .driver_data = ATH9K_PCI_BT_ANT_DIV },
  86         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  87                          0x0032,
  88                          0x185F, /* WNC */
  89                          0x3119),
  90           .driver_data = ATH9K_PCI_BT_ANT_DIV },
  91         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  92                          0x0032,
  93                          0x185F, /* WNC */
  94                          0x3027),
  95           .driver_data = ATH9K_PCI_BT_ANT_DIV },
  96         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  97                          0x0032,
  98                          PCI_VENDOR_ID_SAMSUNG,
  99                          0x4105),
 100           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 101         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 102                          0x0032,
 103                          PCI_VENDOR_ID_SAMSUNG,
 104                          0x4106),
 105           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 106         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 107                          0x0032,
 108                          PCI_VENDOR_ID_SAMSUNG,
 109                          0x410D),
 110           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 111         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 112                          0x0032,
 113                          PCI_VENDOR_ID_SAMSUNG,
 114                          0x410E),
 115           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 116         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 117                          0x0032,
 118                          PCI_VENDOR_ID_SAMSUNG,
 119                          0x410F),
 120           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 121         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 122                          0x0032,
 123                          PCI_VENDOR_ID_SAMSUNG,
 124                          0xC706),
 125           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 126         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 127                          0x0032,
 128                          PCI_VENDOR_ID_SAMSUNG,
 129                          0xC680),
 130           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 131         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 132                          0x0032,
 133                          PCI_VENDOR_ID_SAMSUNG,
 134                          0xC708),
 135           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 136         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 137                          0x0032,
 138                          PCI_VENDOR_ID_LENOVO,
 139                          0x3218),
 140           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 141         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 142                          0x0032,
 143                          PCI_VENDOR_ID_LENOVO,
 144                          0x3219),
 145           .driver_data = ATH9K_PCI_BT_ANT_DIV },
 146
 147         { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
 148         { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */
 149
 150         /* PCI-E CUS217 */
 151         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 152                          0x0034,
 153                          PCI_VENDOR_ID_AZWAVE,
 154                          0x2116),
 155           .driver_data = ATH9K_PCI_CUS217 },
 156         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 157                          0x0034,
 158                          0x11AD, /* LITEON */
 159                          0x6661),
 160           .driver_data = ATH9K_PCI_CUS217 },
 161
 162         /* AR9462 with WoW support */
 163         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 164                          0x0034,
 165                          PCI_VENDOR_ID_ATHEROS,
 166                          0x3117),
 167           .driver_data = ATH9K_PCI_WOW },
 168         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 169                          0x0034,
 170                          PCI_VENDOR_ID_LENOVO,
 171                          0x3214),
 172           .driver_data = ATH9K_PCI_WOW },
 173         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 174                          0x0034,
 175                          PCI_VENDOR_ID_ATTANSIC,
 176                          0x0091),
 177           .driver_data = ATH9K_PCI_WOW },
 178         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 179                          0x0034,
 180                          PCI_VENDOR_ID_AZWAVE,
 181                          0x2110),
 182           .driver_data = ATH9K_PCI_WOW },
 183         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 184                          0x0034,
 185                          PCI_VENDOR_ID_ASUSTEK,
 186                          0x850E),
 187           .driver_data = ATH9K_PCI_WOW },
 188         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 189                          0x0034,
 190                          0x11AD, /* LITEON */
 191                          0x6631),
 192           .driver_data = ATH9K_PCI_WOW },
 193         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 194                          0x0034,
 195                          0x11AD, /* LITEON */
 196                          0x6641),
 197           .driver_data = ATH9K_PCI_WOW },
 198         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 199                          0x0034,
 200                          PCI_VENDOR_ID_HP,
 201                          0x1864),
 202           .driver_data = ATH9K_PCI_WOW },
 203         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 204                          0x0034,
 205                          0x14CD, /* USI */
 206                          0x0063),
 207           .driver_data = ATH9K_PCI_WOW },
 208         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 209                          0x0034,
 210                          0x14CD, /* USI */
 211                          0x0064),
 212           .driver_data = ATH9K_PCI_WOW },
 213         { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
 214                          0x0034,
 215                          0x10CF, /* Fujitsu */
 216                          0x1783),
 217           .driver_data = ATH9K_PCI_WOW },
 218
 219         { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E  AR9462 */
 220         { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E  AR1111/AR9485 */
 221         { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E  AR9565 */
 222         { 0 }
 223 };
 224
 225
 226 /* return bus cachesize in 4B word units */
 227 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
 228 {
 229         struct ath_softc *sc = (struct ath_softc *) common->priv;
 230         u8 u8tmp;
 231
 232         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
 233         *csz = (int)u8tmp;
 234
 235         /*
 236          * This check was put in to avoid "unpleasant" consequences if
 237          * the bootrom has not fully initialized all PCI devices.
 238          * Sometimes the cache line size register is not set
 239          */
 240
 241         if (*csz == 0)
 242                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
 243 }
 244
 245 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 246 {
 247         struct ath_softc *sc = (struct ath_softc *) common->priv;
 248         struct ath9k_platform_data *pdata = sc->dev->platform_data;
 249
 250         if (pdata) {
 251                 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
 252                         ath_err(common,
 253                                 "%s: eeprom read failed, offset %08x is out of range\n",
 254                                 __func__, off);
 255                 }
 256
 257                 *data = pdata->eeprom_data[off];
 258         } else {
 259                 struct ath_hw *ah = (struct ath_hw *) common->ah;
 260
 261                 common->ops->read(ah, AR5416_EEPROM_OFFSET +
 262                                       (off << AR5416_EEPROM_S));
 263
 264                 if (!ath9k_hw_wait(ah,
 265                                    AR_EEPROM_STATUS_DATA,
 266                                    AR_EEPROM_STATUS_DATA_BUSY |
 267                                    AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
 268                                    AH_WAIT_TIMEOUT)) {
 269                         return false;
 270                 }
 271
 272                 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
 273                            AR_EEPROM_STATUS_DATA_VAL);
 274         }
 275
 276         return true;
 277 }
 278
 279 /* Need to be called after we discover btcoex capabilities */
 280 static void ath_pci_aspm_init(struct ath_common *common)
 281 {
 282         struct ath_softc *sc = (struct ath_softc *) common->priv;
 283         struct ath_hw *ah = sc->sc_ah;
 284         struct pci_dev *pdev = to_pci_dev(sc->dev);
 285         struct pci_dev *parent;
 286         u16 aspm;
 287
 288         if (!ah->is_pciexpress)
 289                 return;
 290
 291         parent = pdev->bus->self;
 292         if (!parent)
 293                 return;
 294
 295         if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
 296             (AR_SREV_9285(ah))) {
 297                 /* Bluetooth coexistence requires disabling ASPM. */
 298                 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
 299                         PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
 300
 301                 /*
 302                  * Both upstream and downstream PCIe components should
 303                  * have the same ASPM settings.
 304                  */
 305                 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
 306                         PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
 307
 308                 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
 309                 return;
 310         }
 311
 312         pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
 313         if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
 314                 ah->aspm_enabled = true;
 315                 /* Initialize PCIe PM and SERDES registers. */
 316                 ath9k_hw_configpcipowersave(ah, false);
 317                 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
 318         }
 319 }
 320
 321 static const struct ath_bus_ops ath_pci_bus_ops = {
 322         .ath_bus_type = ATH_PCI,
 323         .read_cachesize = ath_pci_read_cachesize,
 324         .eeprom_read = ath_pci_eeprom_read,
 325         .aspm_init = ath_pci_aspm_init,
 326 };
 327
 328 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 329 {
 330         struct ath_softc *sc;
 331         struct ieee80211_hw *hw;
 332         u8 csz;
 333         u32 val;
 334         int ret = 0;
 335         char hw_name[64];
 336
 337         if (pcim_enable_device(pdev))
 338                 return -EIO;
 339
 340         ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 341         if (ret) {
 342                 pr_err("32-bit DMA not available\n");
 343                 return ret;
 344         }
 345
 346         ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 347         if (ret) {
 348                 pr_err("32-bit DMA consistent DMA enable failed\n");
 349                 return ret;
 350         }
 351
 352         /*
 353          * Cache line size is used to size and align various
 354          * structures used to communicate with the hardware.
 355          */
 356         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 357         if (csz == 0) {
 358                 /*
 359                  * Linux 2.4.18 (at least) writes the cache line size
 360                  * register as a 16-bit wide register which is wrong.
 361                  * We must have this setup properly for rx buffer
 362                  * DMA to work so force a reasonable value here if it
 363                  * comes up zero.
 364                  */
 365                 csz = L1_CACHE_BYTES / sizeof(u32);
 366                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 367         }
 368         /*
 369          * The default setting of latency timer yields poor results,
 370          * set it to the value used by other systems. It may be worth
 371          * tweaking this setting more.
 372          */
 373         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 374
 375         pci_set_master(pdev);
 376
 377         /*
 378          * Disable the RETRY_TIMEOUT register (0x41) to keep
 379          * PCI Tx retries from interfering with C3 CPU state.
 380          */
 381         pci_read_config_dword(pdev, 0x40, &val);
 382         if ((val & 0x0000ff00) != 0)
 383                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 384
 385         ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
 386         if (ret) {
 387                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 388                 return -ENODEV;
 389         }
 390
 391         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 392         if (!hw) {
 393                 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
 394                 return -ENOMEM;
 395         }
 396
 397         SET_IEEE80211_DEV(hw, &pdev->dev);
 398         pci_set_drvdata(pdev, hw);
 399
 400         sc = hw->priv;
 401         sc->hw = hw;
 402         sc->dev = &pdev->dev;
 403         sc->mem = pcim_iomap_table(pdev)[0];
 404         sc->driver_data = id->driver_data;
 405
 406         /* Will be cleared in ath9k_start() */
 407         set_bit(SC_OP_INVALID, &sc->sc_flags);
 408
 409         ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
 410         if (ret) {
 411                 dev_err(&pdev->dev, "request_irq failed\n");
 412                 goto err_irq;
 413         }
 414
 415         sc->irq = pdev->irq;
 416
 417         ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
 418         if (ret) {
 419                 dev_err(&pdev->dev, "Failed to initialize device\n");
 420                 goto err_init;
 421         }
 422
 423         ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
 424         wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
 425                    hw_name, (unsigned long)sc->mem, pdev->irq);
 426
 427         return 0;
 428
 429 err_init:
 430         free_irq(sc->irq, sc);
 431 err_irq:
 432         ieee80211_free_hw(hw);
 433         return ret;
 434 }
 435
 436 static void ath_pci_remove(struct pci_dev *pdev)
 437 {
 438         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 439         struct ath_softc *sc = hw->priv;
 440
 441         if (!is_ath9k_unloaded)
 442                 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
 443         ath9k_deinit_device(sc);
 444         free_irq(sc->irq, sc);
 445         ieee80211_free_hw(sc->hw);
 446 }
 447
 448 #ifdef CONFIG_PM_SLEEP
 449
 450 static int ath_pci_suspend(struct device *device)
 451 {
 452         struct pci_dev *pdev = to_pci_dev(device);
 453         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 454         struct ath_softc *sc = hw->priv;
 455
 456         if (sc->wow_enabled)
 457                 return 0;
 458
 459         /* The device has to be moved to FULLSLEEP forcibly.
 460          * Otherwise the chip never moved to full sleep,
 461          * when no interface is up.
 462          */
 463         ath9k_stop_btcoex(sc);
 464         ath9k_hw_disable(sc->sc_ah);
 465         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 466
 467         return 0;
 468 }
 469
 470 static int ath_pci_resume(struct device *device)
 471 {
 472         struct pci_dev *pdev = to_pci_dev(device);
 473         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 474         struct ath_softc *sc = hw->priv;
 475         struct ath_hw *ah = sc->sc_ah;
 476         struct ath_common *common = ath9k_hw_common(ah);
 477         u32 val;
 478
 479         /*
 480          * Suspend/Resume resets the PCI configuration space, so we have to
 481          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 482          * PCI Tx retries from interfering with C3 CPU state
 483          */
 484         pci_read_config_dword(pdev, 0x40, &val);
 485         if ((val & 0x0000ff00) != 0)
 486                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 487
 488         ath_pci_aspm_init(common);
 489         ah->reset_power_on = false;
 490
 491         return 0;
 492 }
 493
 494 static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume);
 495
 496 #define ATH9K_PM_OPS    (&ath9k_pm_ops)
 497
 498 #else /* !CONFIG_PM_SLEEP */
 499
 500 #define ATH9K_PM_OPS    NULL
 501
 502 #endif /* !CONFIG_PM_SLEEP */
 503
 504
 505 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 506
 507 static struct pci_driver ath_pci_driver = {
 508         .name       = "ath9k",
 509         .id_table   = ath_pci_id_table,
 510         .probe      = ath_pci_probe,
 511         .remove     = ath_pci_remove,
 512         .driver.pm  = ATH9K_PM_OPS,
 513 };
 514
 515 int ath_pci_init(void)
 516 {
 517         return pci_register_driver(&ath_pci_driver);
 518 }
 519
 520 void ath_pci_exit(void)
 521 {
 522         pci_unregister_driver(&ath_pci_driver);
 523 }