2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info = "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
120 sc->hw_rate_table[ATH9K_MODE_11G];
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
134 sc->hw_rate_table[ATH9K_MODE_11A];
142 static void ath_update_txpow(struct ath_softc *sc)
144 struct ath_hw *ah = sc->sc_ah;
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
155 static u8 parse_mpdudensity(u8 mpdudensity)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
208 if (rate_table == NULL)
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
217 maxrates = rate_table->rate_cnt;
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
252 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
255 struct ath_hw *ah = sc->sc_ah;
256 bool fastcc = true, stopped;
257 struct ieee80211_channel *channel = hw->conf.channel;
260 if (sc->sc_flags & SC_OP_INVALID)
266 * This is only performed if the channel settings have
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
274 ath9k_hw_set_interrupts(ah, 0);
275 ath_drain_all_txq(sc, false);
276 stopped = ath_stoprecv(sc);
278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
287 sc->sc_ah->curchan->channel,
288 channel->center_freq, sc->tx_chan_width);
290 spin_lock_bh(&sc->sc_resetlock);
292 r = ath9k_hw_reset(ah, hchan, fastcc);
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
301 spin_unlock_bh(&sc->sc_resetlock);
303 sc->sc_flags &= ~SC_OP_FULL_RESET;
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
314 ath9k_hw_set_interrupts(ah, sc->imask);
317 ath9k_ps_restore(sc);
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
328 static void ath_ani_calibrate(unsigned long data)
330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
336 u32 cal_interval, short_cal_interval;
338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
345 spin_lock(&sc->ani_lock);
346 if (sc->sc_flags & SC_OP_SCANNING)
349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
355 /* Long calibration runs independently of short calibration. */
356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
359 sc->ani.longcal_timer = timestamp;
362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
371 if ((timestamp - sc->ani.resetcal_timer) >=
372 ATH_RESTART_CALINTERVAL) {
373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
375 sc->ani.resetcal_timer = timestamp;
379 /* Verify whether we must check ANI */
380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
382 sc->ani.checkani_timer = timestamp;
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
406 ath9k_ps_restore(sc);
409 spin_unlock(&sc->ani_lock);
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
415 cal_interval = ATH_LONG_CALINTERVAL;
416 if (sc->sc_ah->config.enable_ani)
417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
418 if (!sc->ani.caldone)
419 cal_interval = min(cal_interval, (u32)short_cal_interval);
421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
424 static void ath_start_ani(struct ath_softc *sc)
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
442 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
454 sc->tx_chainmask, sc->rx_chainmask);
457 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
461 an = (struct ath_node *)sta->drv_priv;
463 if (sc->sc_flags & SC_OP_TXAGGR) {
464 ath_tx_node_init(sc, an);
465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
471 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
473 struct ath_node *an = (struct ath_node *)sta->drv_priv;
475 if (sc->sc_flags & SC_OP_TXAGGR)
476 ath_tx_node_cleanup(sc, an);
479 static void ath9k_tasklet(unsigned long data)
481 struct ath_softc *sc = (struct ath_softc *)data;
482 u32 status = sc->intrstatus;
486 if (status & ATH9K_INT_FATAL) {
487 ath_reset(sc, false);
488 ath9k_ps_restore(sc);
492 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
493 spin_lock_bh(&sc->rx.rxflushlock);
494 ath_rx_tasklet(sc, 0);
495 spin_unlock_bh(&sc->rx.rxflushlock);
498 if (status & ATH9K_INT_TX)
501 if ((status & ATH9K_INT_TSFOOR) &&
502 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
504 * TSF sync does not look correct; remain awake to sync with
507 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
508 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
511 /* re-enable hardware interrupt */
512 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
513 ath9k_ps_restore(sc);
516 irqreturn_t ath_isr(int irq, void *dev)
518 #define SCHED_INTR ( \
528 struct ath_softc *sc = dev;
529 struct ath_hw *ah = sc->sc_ah;
530 enum ath9k_int status;
534 * The hardware is not ready/present, don't
535 * touch anything. Note this can happen early
536 * on if the IRQ is shared.
538 if (sc->sc_flags & SC_OP_INVALID)
542 /* shared irq, not for us */
544 if (!ath9k_hw_intrpend(ah))
548 * Figure out the reason(s) for the interrupt. Note
549 * that the hal returns a pseudo-ISR that may include
550 * bits we haven't explicitly enabled so we mask the
551 * value to insure we only process bits we requested.
553 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
554 status &= sc->imask; /* discard unasked-for bits */
557 * If there are no status bits set, then this interrupt was not
558 * for me (should have been caught above).
563 /* Cache the status */
564 sc->intrstatus = status;
566 if (status & SCHED_INTR)
570 * If a FATAL or RXORN interrupt is received, we have to reset the
573 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
576 if (status & ATH9K_INT_SWBA)
577 tasklet_schedule(&sc->bcon_tasklet);
579 if (status & ATH9K_INT_TXURN)
580 ath9k_hw_updatetxtriglevel(ah, true);
582 if (status & ATH9K_INT_MIB) {
584 * Disable interrupts until we service the MIB
585 * interrupt; otherwise it will continue to
588 ath9k_hw_set_interrupts(ah, 0);
590 * Let the hal handle the event. We assume
591 * it will clear whatever condition caused
594 ath9k_hw_procmibevent(ah, &sc->nodestats);
595 ath9k_hw_set_interrupts(ah, sc->imask);
598 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
599 if (status & ATH9K_INT_TIM_TIMER) {
600 /* Clear RxAbort bit so that we can
602 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
603 ath9k_hw_setrxabort(sc->sc_ah, 0);
604 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
609 ath_debug_stat_interrupt(sc, status);
612 /* turn off every interrupt except SWBA */
613 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
614 tasklet_schedule(&sc->intr_tq);
622 static u32 ath_get_extchanmode(struct ath_softc *sc,
623 struct ieee80211_channel *chan,
624 enum nl80211_channel_type channel_type)
628 switch (chan->band) {
629 case IEEE80211_BAND_2GHZ:
630 switch(channel_type) {
631 case NL80211_CHAN_NO_HT:
632 case NL80211_CHAN_HT20:
633 chanmode = CHANNEL_G_HT20;
635 case NL80211_CHAN_HT40PLUS:
636 chanmode = CHANNEL_G_HT40PLUS;
638 case NL80211_CHAN_HT40MINUS:
639 chanmode = CHANNEL_G_HT40MINUS;
643 case IEEE80211_BAND_5GHZ:
644 switch(channel_type) {
645 case NL80211_CHAN_NO_HT:
646 case NL80211_CHAN_HT20:
647 chanmode = CHANNEL_A_HT20;
649 case NL80211_CHAN_HT40PLUS:
650 chanmode = CHANNEL_A_HT40PLUS;
652 case NL80211_CHAN_HT40MINUS:
653 chanmode = CHANNEL_A_HT40MINUS;
664 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
665 struct ath9k_keyval *hk, const u8 *addr,
671 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
672 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
676 * Group key installation - only two key cache entries are used
677 * regardless of splitmic capability since group key is only
678 * used either for TX or RX.
681 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
682 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
687 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
690 /* TX and RX keys share the same key cache entry. */
691 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
692 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
693 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
696 /* Separate key cache entries for TX and RX */
698 /* TX key goes at first index, RX key at +32. */
699 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
700 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
701 /* TX MIC entry failed. No need to proceed further */
702 DPRINTF(sc, ATH_DBG_FATAL,
703 "Setting TX MIC Key Failed\n");
707 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
708 /* XXX delete tx key on failure? */
709 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
712 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
716 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
717 if (test_bit(i, sc->keymap) ||
718 test_bit(i + 64, sc->keymap))
719 continue; /* At least one part of TKIP key allocated */
721 (test_bit(i + 32, sc->keymap) ||
722 test_bit(i + 64 + 32, sc->keymap)))
723 continue; /* At least one part of TKIP key allocated */
725 /* Found a free slot for a TKIP key */
731 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
735 /* First, try to find slots that would not be available for TKIP. */
737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 (test_bit(i + 32, sc->keymap) ||
740 test_bit(i + 64, sc->keymap) ||
741 test_bit(i + 64 + 32, sc->keymap)))
743 if (!test_bit(i + 32, sc->keymap) &&
744 (test_bit(i, sc->keymap) ||
745 test_bit(i + 64, sc->keymap) ||
746 test_bit(i + 64 + 32, sc->keymap)))
748 if (!test_bit(i + 64, sc->keymap) &&
749 (test_bit(i , sc->keymap) ||
750 test_bit(i + 32, sc->keymap) ||
751 test_bit(i + 64 + 32, sc->keymap)))
753 if (!test_bit(i + 64 + 32, sc->keymap) &&
754 (test_bit(i, sc->keymap) ||
755 test_bit(i + 32, sc->keymap) ||
756 test_bit(i + 64, sc->keymap)))
760 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
761 if (!test_bit(i, sc->keymap) &&
762 test_bit(i + 64, sc->keymap))
764 if (test_bit(i, sc->keymap) &&
765 !test_bit(i + 64, sc->keymap))
770 /* No partially used TKIP slots, pick any available slot */
771 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
772 /* Do not allow slots that could be needed for TKIP group keys
773 * to be used. This limitation could be removed if we know that
774 * TKIP will not be used. */
775 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
778 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
780 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
784 if (!test_bit(i, sc->keymap))
785 return i; /* Found a free slot for a key */
788 /* No free slot found */
792 static int ath_key_config(struct ath_softc *sc,
793 struct ieee80211_vif *vif,
794 struct ieee80211_sta *sta,
795 struct ieee80211_key_conf *key)
797 struct ath9k_keyval hk;
798 const u8 *mac = NULL;
802 memset(&hk, 0, sizeof(hk));
806 hk.kv_type = ATH9K_CIPHER_WEP;
809 hk.kv_type = ATH9K_CIPHER_TKIP;
812 hk.kv_type = ATH9K_CIPHER_AES_CCM;
818 hk.kv_len = key->keylen;
819 memcpy(hk.kv_val, key->key, key->keylen);
821 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
822 /* For now, use the default keys for broadcast keys. This may
823 * need to change with virtual interfaces. */
825 } else if (key->keyidx) {
830 if (vif->type != NL80211_IFTYPE_AP) {
831 /* Only keyidx 0 should be used with unicast key, but
832 * allow this for client mode for now. */
841 if (key->alg == ALG_TKIP)
842 idx = ath_reserve_key_cache_slot_tkip(sc);
844 idx = ath_reserve_key_cache_slot(sc);
846 return -ENOSPC; /* no free key cache entries */
849 if (key->alg == ALG_TKIP)
850 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
851 vif->type == NL80211_IFTYPE_AP);
853 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
858 set_bit(idx, sc->keymap);
859 if (key->alg == ALG_TKIP) {
860 set_bit(idx + 64, sc->keymap);
862 set_bit(idx + 32, sc->keymap);
863 set_bit(idx + 64 + 32, sc->keymap);
870 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
872 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
873 if (key->hw_key_idx < IEEE80211_WEP_NKID)
876 clear_bit(key->hw_key_idx, sc->keymap);
877 if (key->alg != ALG_TKIP)
880 clear_bit(key->hw_key_idx + 64, sc->keymap);
882 clear_bit(key->hw_key_idx + 32, sc->keymap);
883 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
887 static void setup_ht_cap(struct ath_softc *sc,
888 struct ieee80211_sta_ht_cap *ht_info)
890 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
891 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
892 u8 tx_streams, rx_streams;
894 ht_info->ht_supported = true;
895 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
896 IEEE80211_HT_CAP_SM_PS |
897 IEEE80211_HT_CAP_SGI_40 |
898 IEEE80211_HT_CAP_DSSSCCK40;
900 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
901 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
903 /* set up supported mcs set */
904 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
905 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
906 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908 if (tx_streams != rx_streams) {
909 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
910 tx_streams, rx_streams);
911 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
912 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
913 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
916 ht_info->mcs.rx_mask[0] = 0xff;
918 ht_info->mcs.rx_mask[1] = 0xff;
920 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
923 static void ath9k_bss_assoc_info(struct ath_softc *sc,
924 struct ieee80211_vif *vif,
925 struct ieee80211_bss_conf *bss_conf)
928 if (bss_conf->assoc) {
929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
930 bss_conf->aid, sc->curbssid);
932 /* New association, store aid */
933 sc->curaid = bss_conf->aid;
934 ath9k_hw_write_associd(sc);
937 * Request a re-configuration of Beacon related timers
938 * on the receipt of the first Beacon frame (i.e.,
939 * after time sync with the AP).
941 sc->sc_flags |= SC_OP_BEACON_SYNC;
943 /* Configure the beacon */
944 ath_beacon_config(sc, vif);
946 /* Reset rssi stats */
947 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
948 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
950 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
954 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
957 del_timer_sync(&sc->ani.timer);
961 /********************************/
963 /********************************/
965 static void ath_led_blink_work(struct work_struct *work)
967 struct ath_softc *sc = container_of(work, struct ath_softc,
968 ath_led_blink_work.work);
970 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
973 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
974 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
978 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
980 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
981 (sc->sc_flags & SC_OP_LED_ON) ?
982 msecs_to_jiffies(sc->led_off_duration) :
983 msecs_to_jiffies(sc->led_on_duration));
985 sc->led_on_duration = sc->led_on_cnt ?
986 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
987 ATH_LED_ON_DURATION_IDLE;
988 sc->led_off_duration = sc->led_off_cnt ?
989 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
990 ATH_LED_OFF_DURATION_IDLE;
991 sc->led_on_cnt = sc->led_off_cnt = 0;
992 if (sc->sc_flags & SC_OP_LED_ON)
993 sc->sc_flags &= ~SC_OP_LED_ON;
995 sc->sc_flags |= SC_OP_LED_ON;
998 static void ath_led_brightness(struct led_classdev *led_cdev,
999 enum led_brightness brightness)
1001 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1002 struct ath_softc *sc = led->sc;
1004 switch (brightness) {
1006 if (led->led_type == ATH_LED_ASSOC ||
1007 led->led_type == ATH_LED_RADIO) {
1008 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1009 (led->led_type == ATH_LED_RADIO));
1010 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1011 if (led->led_type == ATH_LED_RADIO)
1012 sc->sc_flags &= ~SC_OP_LED_ON;
1018 if (led->led_type == ATH_LED_ASSOC) {
1019 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1020 queue_delayed_work(sc->hw->workqueue,
1021 &sc->ath_led_blink_work, 0);
1022 } else if (led->led_type == ATH_LED_RADIO) {
1023 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1024 sc->sc_flags |= SC_OP_LED_ON;
1034 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1040 led->led_cdev.name = led->name;
1041 led->led_cdev.default_trigger = trigger;
1042 led->led_cdev.brightness_set = ath_led_brightness;
1044 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1046 DPRINTF(sc, ATH_DBG_FATAL,
1047 "Failed to register led:%s", led->name);
1049 led->registered = 1;
1053 static void ath_unregister_led(struct ath_led *led)
1055 if (led->registered) {
1056 led_classdev_unregister(&led->led_cdev);
1057 led->registered = 0;
1061 static void ath_deinit_leds(struct ath_softc *sc)
1063 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1064 ath_unregister_led(&sc->assoc_led);
1065 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1066 ath_unregister_led(&sc->tx_led);
1067 ath_unregister_led(&sc->rx_led);
1068 ath_unregister_led(&sc->radio_led);
1069 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1072 static void ath_init_leds(struct ath_softc *sc)
1077 /* Configure gpio 1 for output */
1078 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1079 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1080 /* LED off, active low */
1081 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1083 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1085 trigger = ieee80211_get_radio_led_name(sc->hw);
1086 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1087 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1088 ret = ath_register_led(sc, &sc->radio_led, trigger);
1089 sc->radio_led.led_type = ATH_LED_RADIO;
1093 trigger = ieee80211_get_assoc_led_name(sc->hw);
1094 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1095 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1096 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1097 sc->assoc_led.led_type = ATH_LED_ASSOC;
1101 trigger = ieee80211_get_tx_led_name(sc->hw);
1102 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1103 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1104 ret = ath_register_led(sc, &sc->tx_led, trigger);
1105 sc->tx_led.led_type = ATH_LED_TX;
1109 trigger = ieee80211_get_rx_led_name(sc->hw);
1110 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1111 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1112 ret = ath_register_led(sc, &sc->rx_led, trigger);
1113 sc->rx_led.led_type = ATH_LED_RX;
1120 ath_deinit_leds(sc);
1123 void ath_radio_enable(struct ath_softc *sc)
1125 struct ath_hw *ah = sc->sc_ah;
1126 struct ieee80211_channel *channel = sc->hw->conf.channel;
1129 ath9k_ps_wakeup(sc);
1130 ath9k_hw_configpcipowersave(ah, 0);
1133 ah->curchan = ath_get_curchannel(sc, sc->hw);
1135 spin_lock_bh(&sc->sc_resetlock);
1136 r = ath9k_hw_reset(ah, ah->curchan, false);
1138 DPRINTF(sc, ATH_DBG_FATAL,
1139 "Unable to reset channel %u (%uMhz) ",
1140 "reset status %d\n",
1141 channel->center_freq, r);
1143 spin_unlock_bh(&sc->sc_resetlock);
1145 ath_update_txpow(sc);
1146 if (ath_startrecv(sc) != 0) {
1147 DPRINTF(sc, ATH_DBG_FATAL,
1148 "Unable to restart recv logic\n");
1152 if (sc->sc_flags & SC_OP_BEACONS)
1153 ath_beacon_config(sc, NULL); /* restart beacons */
1155 /* Re-Enable interrupts */
1156 ath9k_hw_set_interrupts(ah, sc->imask);
1159 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1160 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1161 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1163 ieee80211_wake_queues(sc->hw);
1164 ath9k_ps_restore(sc);
1167 void ath_radio_disable(struct ath_softc *sc)
1169 struct ath_hw *ah = sc->sc_ah;
1170 struct ieee80211_channel *channel = sc->hw->conf.channel;
1173 ath9k_ps_wakeup(sc);
1174 ieee80211_stop_queues(sc->hw);
1177 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1178 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1180 /* Disable interrupts */
1181 ath9k_hw_set_interrupts(ah, 0);
1183 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1184 ath_stoprecv(sc); /* turn off frame recv */
1185 ath_flushrecv(sc); /* flush recv queue */
1188 ah->curchan = ath_get_curchannel(sc, sc->hw);
1190 spin_lock_bh(&sc->sc_resetlock);
1191 r = ath9k_hw_reset(ah, ah->curchan, false);
1193 DPRINTF(sc, ATH_DBG_FATAL,
1194 "Unable to reset channel %u (%uMhz) "
1195 "reset status %d\n",
1196 channel->center_freq, r);
1198 spin_unlock_bh(&sc->sc_resetlock);
1200 ath9k_hw_phy_disable(ah);
1201 ath9k_hw_configpcipowersave(ah, 1);
1202 ath9k_ps_restore(sc);
1203 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1206 /*******************/
1208 /*******************/
1210 static bool ath_is_rfkill_set(struct ath_softc *sc)
1212 struct ath_hw *ah = sc->sc_ah;
1214 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1215 ah->rfkill_polarity;
1218 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1220 struct ath_wiphy *aphy = hw->priv;
1221 struct ath_softc *sc = aphy->sc;
1222 bool blocked = !!ath_is_rfkill_set(sc);
1224 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1227 ath_radio_disable(sc);
1229 ath_radio_enable(sc);
1232 static void ath_start_rfkill_poll(struct ath_softc *sc)
1234 struct ath_hw *ah = sc->sc_ah;
1236 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1237 wiphy_rfkill_start_polling(sc->hw->wiphy);
1240 void ath_cleanup(struct ath_softc *sc)
1243 free_irq(sc->irq, sc);
1244 ath_bus_cleanup(sc);
1245 kfree(sc->sec_wiphy);
1246 ieee80211_free_hw(sc->hw);
1249 void ath_detach(struct ath_softc *sc)
1251 struct ieee80211_hw *hw = sc->hw;
1254 ath9k_ps_wakeup(sc);
1256 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1258 ath_deinit_leds(sc);
1259 cancel_work_sync(&sc->chan_work);
1260 cancel_delayed_work_sync(&sc->wiphy_work);
1262 for (i = 0; i < sc->num_sec_wiphy; i++) {
1263 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1266 sc->sec_wiphy[i] = NULL;
1267 ieee80211_unregister_hw(aphy->hw);
1268 ieee80211_free_hw(aphy->hw);
1270 ieee80211_unregister_hw(hw);
1274 tasklet_kill(&sc->intr_tq);
1275 tasklet_kill(&sc->bcon_tasklet);
1277 if (!(sc->sc_flags & SC_OP_INVALID))
1278 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1280 /* cleanup tx queues */
1281 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1282 if (ATH_TXQ_SETUP(sc, i))
1283 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1285 ath9k_hw_detach(sc->sc_ah);
1286 ath9k_exit_debug(sc);
1287 ath9k_ps_restore(sc);
1290 static int ath9k_reg_notifier(struct wiphy *wiphy,
1291 struct regulatory_request *request)
1293 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1294 struct ath_wiphy *aphy = hw->priv;
1295 struct ath_softc *sc = aphy->sc;
1296 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1298 return ath_reg_notifier_apply(wiphy, request, reg);
1301 static int ath_init(u16 devid, struct ath_softc *sc)
1303 struct ath_hw *ah = NULL;
1308 /* XXX: hardware will not be ready until ath_open() being called */
1309 sc->sc_flags |= SC_OP_INVALID;
1311 if (ath9k_init_debug(sc) < 0)
1312 printk(KERN_ERR "Unable to create debugfs files\n");
1314 spin_lock_init(&sc->wiphy_lock);
1315 spin_lock_init(&sc->sc_resetlock);
1316 spin_lock_init(&sc->sc_serial_rw);
1317 spin_lock_init(&sc->ani_lock);
1318 mutex_init(&sc->mutex);
1319 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1320 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1324 * Cache line size is used to size and align various
1325 * structures used to communicate with the hardware.
1327 ath_read_cachesize(sc, &csz);
1328 /* XXX assert csz is non-zero */
1329 sc->cachelsz = csz << 2; /* convert to bytes */
1331 ah = ath9k_hw_attach(devid, sc, &status);
1333 DPRINTF(sc, ATH_DBG_FATAL,
1334 "Unable to attach hardware; HAL status %d\n", status);
1340 /* Get the hardware key cache size. */
1341 sc->keymax = ah->caps.keycache_size;
1342 if (sc->keymax > ATH_KEYMAX) {
1343 DPRINTF(sc, ATH_DBG_ANY,
1344 "Warning, using only %u entries in %u key cache\n",
1345 ATH_KEYMAX, sc->keymax);
1346 sc->keymax = ATH_KEYMAX;
1350 * Reset the key cache since some parts do not
1351 * reset the contents on initial power up.
1353 for (i = 0; i < sc->keymax; i++)
1354 ath9k_hw_keyreset(ah, (u16) i);
1359 /* default to MONITOR mode */
1360 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1362 /* Setup rate tables */
1364 ath_rate_attach(sc);
1365 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1366 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1369 * Allocate hardware transmit queues: one queue for
1370 * beacon frames and one data queue for each QoS
1371 * priority. Note that the hal handles reseting
1372 * these queues at the needed time.
1374 sc->beacon.beaconq = ath_beaconq_setup(ah);
1375 if (sc->beacon.beaconq == -1) {
1376 DPRINTF(sc, ATH_DBG_FATAL,
1377 "Unable to setup a beacon xmit queue\n");
1381 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1382 if (sc->beacon.cabq == NULL) {
1383 DPRINTF(sc, ATH_DBG_FATAL,
1384 "Unable to setup CAB xmit queue\n");
1389 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1390 ath_cabq_update(sc);
1392 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1393 sc->tx.hwq_map[i] = -1;
1395 /* Setup data queues */
1396 /* NB: ensure BK queue is the lowest priority h/w queue */
1397 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
1399 "Unable to setup xmit queue for BK traffic\n");
1404 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1405 DPRINTF(sc, ATH_DBG_FATAL,
1406 "Unable to setup xmit queue for BE traffic\n");
1410 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1411 DPRINTF(sc, ATH_DBG_FATAL,
1412 "Unable to setup xmit queue for VI traffic\n");
1416 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1417 DPRINTF(sc, ATH_DBG_FATAL,
1418 "Unable to setup xmit queue for VO traffic\n");
1423 /* Initializes the noise floor to a reasonable default value.
1424 * Later on this will be updated during ANI processing. */
1426 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1427 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1429 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1430 ATH9K_CIPHER_TKIP, NULL)) {
1432 * Whether we should enable h/w TKIP MIC.
1433 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1434 * report WMM capable, so it's always safe to turn on
1435 * TKIP MIC in this case.
1437 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1442 * Check whether the separate key cache entries
1443 * are required to handle both tx+rx MIC keys.
1444 * With split mic keys the number of stations is limited
1445 * to 27 otherwise 59.
1447 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448 ATH9K_CIPHER_TKIP, NULL)
1449 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_MIC, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1455 /* turn on mcast key search if possible */
1456 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1457 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1460 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1462 /* 11n Capabilities */
1463 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1464 sc->sc_flags |= SC_OP_TXAGGR;
1465 sc->sc_flags |= SC_OP_RXAGGR;
1468 sc->tx_chainmask = ah->caps.tx_chainmask;
1469 sc->rx_chainmask = ah->caps.rx_chainmask;
1471 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1472 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1474 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1475 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1477 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1479 /* initialize beacon slots */
1480 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1481 sc->beacon.bslot[i] = NULL;
1482 sc->beacon.bslot_aphy[i] = NULL;
1485 /* setup channels and rates */
1487 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1488 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1489 sc->rates[IEEE80211_BAND_2GHZ];
1490 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1491 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1492 ARRAY_SIZE(ath9k_2ghz_chantable);
1494 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1495 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1496 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1497 sc->rates[IEEE80211_BAND_5GHZ];
1498 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1499 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1500 ARRAY_SIZE(ath9k_5ghz_chantable);
1503 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1504 ath9k_hw_btcoex_enable(sc->sc_ah);
1508 /* cleanup tx queues */
1509 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1510 if (ATH_TXQ_SETUP(sc, i))
1511 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1514 ath9k_hw_detach(ah);
1515 ath9k_exit_debug(sc);
1520 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1522 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1523 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1524 IEEE80211_HW_SIGNAL_DBM |
1525 IEEE80211_HW_AMPDU_AGGREGATION |
1526 IEEE80211_HW_SUPPORTS_PS |
1527 IEEE80211_HW_PS_NULLFUNC_STACK |
1528 IEEE80211_HW_SPECTRUM_MGMT;
1530 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1531 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1533 hw->wiphy->interface_modes =
1534 BIT(NL80211_IFTYPE_AP) |
1535 BIT(NL80211_IFTYPE_STATION) |
1536 BIT(NL80211_IFTYPE_ADHOC) |
1537 BIT(NL80211_IFTYPE_MESH_POINT);
1541 hw->channel_change_time = 5000;
1542 hw->max_listen_interval = 10;
1543 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1544 hw->sta_data_size = sizeof(struct ath_node);
1545 hw->vif_data_size = sizeof(struct ath_vif);
1547 hw->rate_control_algorithm = "ath9k_rate_control";
1549 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1550 &sc->sbands[IEEE80211_BAND_2GHZ];
1551 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1552 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1553 &sc->sbands[IEEE80211_BAND_5GHZ];
1556 int ath_attach(u16 devid, struct ath_softc *sc)
1558 struct ieee80211_hw *hw = sc->hw;
1560 struct ath_regulatory *reg;
1562 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1564 error = ath_init(devid, sc);
1568 /* get mac address from hardware and set in mac80211 */
1570 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1572 ath_set_hw_capab(sc, hw);
1574 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1575 ath9k_reg_notifier);
1579 reg = &sc->sc_ah->regulatory;
1581 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1582 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1583 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1584 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1587 /* initialize tx/rx engine */
1588 error = ath_tx_init(sc, ATH_TXBUF);
1592 error = ath_rx_init(sc, ATH_RXBUF);
1596 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1597 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1598 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1600 error = ieee80211_register_hw(hw);
1602 if (!ath_is_world_regd(reg)) {
1603 error = regulatory_hint(hw->wiphy, reg->alpha2);
1608 /* Initialize LED control */
1611 ath_start_rfkill_poll(sc);
1616 /* cleanup tx queues */
1617 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1618 if (ATH_TXQ_SETUP(sc, i))
1619 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1621 ath9k_hw_detach(sc->sc_ah);
1622 ath9k_exit_debug(sc);
1627 int ath_reset(struct ath_softc *sc, bool retry_tx)
1629 struct ath_hw *ah = sc->sc_ah;
1630 struct ieee80211_hw *hw = sc->hw;
1633 ath9k_hw_set_interrupts(ah, 0);
1634 ath_drain_all_txq(sc, retry_tx);
1638 spin_lock_bh(&sc->sc_resetlock);
1639 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1641 DPRINTF(sc, ATH_DBG_FATAL,
1642 "Unable to reset hardware; reset status %d\n", r);
1643 spin_unlock_bh(&sc->sc_resetlock);
1645 if (ath_startrecv(sc) != 0)
1646 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1649 * We may be doing a reset in response to a request
1650 * that changes the channel so update any state that
1651 * might change as a result.
1653 ath_cache_conf_rate(sc, &hw->conf);
1655 ath_update_txpow(sc);
1657 if (sc->sc_flags & SC_OP_BEACONS)
1658 ath_beacon_config(sc, NULL); /* restart beacons */
1660 ath9k_hw_set_interrupts(ah, sc->imask);
1664 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1665 if (ATH_TXQ_SETUP(sc, i)) {
1666 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1667 ath_txq_schedule(sc, &sc->tx.txq[i]);
1668 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1677 * This function will allocate both the DMA descriptor structure, and the
1678 * buffers it contains. These are used to contain the descriptors used
1681 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1682 struct list_head *head, const char *name,
1683 int nbuf, int ndesc)
1685 #define DS2PHYS(_dd, _ds) \
1686 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1687 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1688 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1690 struct ath_desc *ds;
1692 int i, bsize, error;
1694 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1697 INIT_LIST_HEAD(head);
1698 /* ath_desc must be a multiple of DWORDs */
1699 if ((sizeof(struct ath_desc) % 4) != 0) {
1700 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1701 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1706 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1709 * Need additional DMA memory because we can't use
1710 * descriptors that cross the 4K page boundary. Assume
1711 * one skipped descriptor per 4K page.
1713 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1715 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1718 while (ndesc_skipped) {
1719 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1720 dd->dd_desc_len += dma_len;
1722 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1726 /* allocate descriptors */
1727 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1728 &dd->dd_desc_paddr, GFP_KERNEL);
1729 if (dd->dd_desc == NULL) {
1734 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1735 name, ds, (u32) dd->dd_desc_len,
1736 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1738 /* allocate buffers */
1739 bsize = sizeof(struct ath_buf) * nbuf;
1740 bf = kzalloc(bsize, GFP_KERNEL);
1747 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1749 bf->bf_daddr = DS2PHYS(dd, ds);
1751 if (!(sc->sc_ah->caps.hw_caps &
1752 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1754 * Skip descriptor addresses which can cause 4KB
1755 * boundary crossing (addr + length) with a 32 dword
1758 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1759 ASSERT((caddr_t) bf->bf_desc <
1760 ((caddr_t) dd->dd_desc +
1765 bf->bf_daddr = DS2PHYS(dd, ds);
1768 list_add_tail(&bf->list, head);
1772 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1775 memset(dd, 0, sizeof(*dd));
1777 #undef ATH_DESC_4KB_BOUND_CHECK
1778 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1782 void ath_descdma_cleanup(struct ath_softc *sc,
1783 struct ath_descdma *dd,
1784 struct list_head *head)
1786 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1789 INIT_LIST_HEAD(head);
1790 kfree(dd->dd_bufptr);
1791 memset(dd, 0, sizeof(*dd));
1794 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1800 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1803 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1806 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1809 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1812 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1819 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1824 case ATH9K_WME_AC_VO:
1827 case ATH9K_WME_AC_VI:
1830 case ATH9K_WME_AC_BE:
1833 case ATH9K_WME_AC_BK:
1844 /* XXX: Remove me once we don't depend on ath9k_channel for all
1845 * this redundant data */
1846 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1847 struct ath9k_channel *ichan)
1849 struct ieee80211_channel *chan = hw->conf.channel;
1850 struct ieee80211_conf *conf = &hw->conf;
1852 ichan->channel = chan->center_freq;
1855 if (chan->band == IEEE80211_BAND_2GHZ) {
1856 ichan->chanmode = CHANNEL_G;
1857 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1859 ichan->chanmode = CHANNEL_A;
1860 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1863 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1865 if (conf_is_ht(conf)) {
1866 if (conf_is_ht40(conf))
1867 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1869 ichan->chanmode = ath_get_extchanmode(sc, chan,
1870 conf->channel_type);
1874 /**********************/
1875 /* mac80211 callbacks */
1876 /**********************/
1878 static int ath9k_start(struct ieee80211_hw *hw)
1880 struct ath_wiphy *aphy = hw->priv;
1881 struct ath_softc *sc = aphy->sc;
1882 struct ieee80211_channel *curchan = hw->conf.channel;
1883 struct ath9k_channel *init_channel;
1886 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1887 "initial channel: %d MHz\n", curchan->center_freq);
1889 mutex_lock(&sc->mutex);
1891 if (ath9k_wiphy_started(sc)) {
1892 if (sc->chan_idx == curchan->hw_value) {
1894 * Already on the operational channel, the new wiphy
1895 * can be marked active.
1897 aphy->state = ATH_WIPHY_ACTIVE;
1898 ieee80211_wake_queues(hw);
1901 * Another wiphy is on another channel, start the new
1902 * wiphy in paused state.
1904 aphy->state = ATH_WIPHY_PAUSED;
1905 ieee80211_stop_queues(hw);
1907 mutex_unlock(&sc->mutex);
1910 aphy->state = ATH_WIPHY_ACTIVE;
1912 /* setup initial channel */
1914 sc->chan_idx = curchan->hw_value;
1916 init_channel = ath_get_curchannel(sc, hw);
1918 /* Reset SERDES registers */
1919 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1922 * The basic interface to setting the hardware in a good
1923 * state is ``reset''. On return the hardware is known to
1924 * be powered up and with interrupts disabled. This must
1925 * be followed by initialization of the appropriate bits
1926 * and then setup of the interrupt mask.
1928 spin_lock_bh(&sc->sc_resetlock);
1929 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1931 DPRINTF(sc, ATH_DBG_FATAL,
1932 "Unable to reset hardware; reset status %d "
1933 "(freq %u MHz)\n", r,
1934 curchan->center_freq);
1935 spin_unlock_bh(&sc->sc_resetlock);
1938 spin_unlock_bh(&sc->sc_resetlock);
1941 * This is needed only to setup initial state
1942 * but it's best done after a reset.
1944 ath_update_txpow(sc);
1947 * Setup the hardware after reset:
1948 * The receive engine is set going.
1949 * Frame transmit is handled entirely
1950 * in the frame output path; there's nothing to do
1951 * here except setup the interrupt mask.
1953 if (ath_startrecv(sc) != 0) {
1954 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1959 /* Setup our intr mask. */
1960 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1961 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1962 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1964 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1965 sc->imask |= ATH9K_INT_GTT;
1967 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1968 sc->imask |= ATH9K_INT_CST;
1970 ath_cache_conf_rate(sc, &hw->conf);
1972 sc->sc_flags &= ~SC_OP_INVALID;
1974 /* Disable BMISS interrupt when we're not associated */
1975 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1976 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1978 ieee80211_wake_queues(hw);
1981 mutex_unlock(&sc->mutex);
1986 static int ath9k_tx(struct ieee80211_hw *hw,
1987 struct sk_buff *skb)
1989 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1990 struct ath_wiphy *aphy = hw->priv;
1991 struct ath_softc *sc = aphy->sc;
1992 struct ath_tx_control txctl;
1993 int hdrlen, padsize;
1995 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
1996 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1997 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2001 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2002 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2004 * mac80211 does not set PM field for normal data frames, so we
2005 * need to update that based on the current PS mode.
2007 if (ieee80211_is_data(hdr->frame_control) &&
2008 !ieee80211_is_nullfunc(hdr->frame_control) &&
2009 !ieee80211_has_pm(hdr->frame_control)) {
2010 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2011 "while in PS mode\n");
2012 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2016 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2018 * We are using PS-Poll and mac80211 can request TX while in
2019 * power save mode. Need to wake up hardware for the TX to be
2020 * completed and if needed, also for RX of buffered frames.
2022 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2023 ath9k_ps_wakeup(sc);
2024 ath9k_hw_setrxabort(sc->sc_ah, 0);
2025 if (ieee80211_is_pspoll(hdr->frame_control)) {
2026 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2027 "buffered frame\n");
2028 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2030 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2031 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2034 * The actual restore operation will happen only after
2035 * the sc_flags bit is cleared. We are just dropping
2036 * the ps_usecount here.
2038 ath9k_ps_restore(sc);
2041 memset(&txctl, 0, sizeof(struct ath_tx_control));
2044 * As a temporary workaround, assign seq# here; this will likely need
2045 * to be cleaned up to work better with Beacon transmission and virtual
2048 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2049 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2050 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2051 sc->tx.seq_no += 0x10;
2052 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2053 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2056 /* Add the padding after the header if this is not already done */
2057 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2059 padsize = hdrlen % 4;
2060 if (skb_headroom(skb) < padsize)
2062 skb_push(skb, padsize);
2063 memmove(skb->data, skb->data + padsize, hdrlen);
2066 /* Check if a tx queue is available */
2068 txctl.txq = ath_test_get_txq(sc, skb);
2072 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2074 if (ath_tx_start(hw, skb, &txctl) != 0) {
2075 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2081 dev_kfree_skb_any(skb);
2085 static void ath9k_stop(struct ieee80211_hw *hw)
2087 struct ath_wiphy *aphy = hw->priv;
2088 struct ath_softc *sc = aphy->sc;
2090 aphy->state = ATH_WIPHY_INACTIVE;
2092 if (sc->sc_flags & SC_OP_INVALID) {
2093 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2097 mutex_lock(&sc->mutex);
2099 ieee80211_stop_queues(hw);
2101 if (ath9k_wiphy_started(sc)) {
2102 mutex_unlock(&sc->mutex);
2103 return; /* another wiphy still in use */
2106 /* make sure h/w will not generate any interrupt
2107 * before setting the invalid flag. */
2108 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2110 if (!(sc->sc_flags & SC_OP_INVALID)) {
2111 ath_drain_all_txq(sc, false);
2113 ath9k_hw_phy_disable(sc->sc_ah);
2115 sc->rx.rxlink = NULL;
2117 wiphy_rfkill_stop_polling(sc->hw->wiphy);
2119 /* disable HAL and put h/w to sleep */
2120 ath9k_hw_disable(sc->sc_ah);
2121 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2123 sc->sc_flags |= SC_OP_INVALID;
2125 mutex_unlock(&sc->mutex);
2127 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2130 static int ath9k_add_interface(struct ieee80211_hw *hw,
2131 struct ieee80211_if_init_conf *conf)
2133 struct ath_wiphy *aphy = hw->priv;
2134 struct ath_softc *sc = aphy->sc;
2135 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2136 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2139 mutex_lock(&sc->mutex);
2141 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2147 switch (conf->type) {
2148 case NL80211_IFTYPE_STATION:
2149 ic_opmode = NL80211_IFTYPE_STATION;
2151 case NL80211_IFTYPE_ADHOC:
2152 case NL80211_IFTYPE_AP:
2153 case NL80211_IFTYPE_MESH_POINT:
2154 if (sc->nbcnvifs >= ATH_BCBUF) {
2158 ic_opmode = conf->type;
2161 DPRINTF(sc, ATH_DBG_FATAL,
2162 "Interface type %d not yet supported\n", conf->type);
2167 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2169 /* Set the VIF opmode */
2170 avp->av_opmode = ic_opmode;
2175 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2176 ath9k_set_bssid_mask(hw);
2179 goto out; /* skip global settings for secondary vif */
2181 if (ic_opmode == NL80211_IFTYPE_AP) {
2182 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2183 sc->sc_flags |= SC_OP_TSF_RESET;
2186 /* Set the device opmode */
2187 sc->sc_ah->opmode = ic_opmode;
2190 * Enable MIB interrupts when there are hardware phy counters.
2191 * Note we only do this (at the moment) for station mode.
2193 if ((conf->type == NL80211_IFTYPE_STATION) ||
2194 (conf->type == NL80211_IFTYPE_ADHOC) ||
2195 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2196 if (ath9k_hw_phycounters(sc->sc_ah))
2197 sc->imask |= ATH9K_INT_MIB;
2198 sc->imask |= ATH9K_INT_TSFOOR;
2201 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2203 if (conf->type == NL80211_IFTYPE_AP ||
2204 conf->type == NL80211_IFTYPE_ADHOC ||
2205 conf->type == NL80211_IFTYPE_MONITOR)
2209 mutex_unlock(&sc->mutex);
2213 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2214 struct ieee80211_if_init_conf *conf)
2216 struct ath_wiphy *aphy = hw->priv;
2217 struct ath_softc *sc = aphy->sc;
2218 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2221 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2223 mutex_lock(&sc->mutex);
2226 del_timer_sync(&sc->ani.timer);
2228 /* Reclaim beacon resources */
2229 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2230 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2231 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2232 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2233 ath_beacon_return(sc, avp);
2236 sc->sc_flags &= ~SC_OP_BEACONS;
2238 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2239 if (sc->beacon.bslot[i] == conf->vif) {
2240 printk(KERN_DEBUG "%s: vif had allocated beacon "
2241 "slot\n", __func__);
2242 sc->beacon.bslot[i] = NULL;
2243 sc->beacon.bslot_aphy[i] = NULL;
2249 mutex_unlock(&sc->mutex);
2252 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2254 struct ath_wiphy *aphy = hw->priv;
2255 struct ath_softc *sc = aphy->sc;
2256 struct ieee80211_conf *conf = &hw->conf;
2257 struct ath_hw *ah = sc->sc_ah;
2259 mutex_lock(&sc->mutex);
2261 if (changed & IEEE80211_CONF_CHANGE_PS) {
2262 if (conf->flags & IEEE80211_CONF_PS) {
2263 if (!(ah->caps.hw_caps &
2264 ATH9K_HW_CAP_AUTOSLEEP)) {
2265 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2266 sc->imask |= ATH9K_INT_TIM_TIMER;
2267 ath9k_hw_set_interrupts(sc->sc_ah,
2270 ath9k_hw_setrxabort(sc->sc_ah, 1);
2272 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2274 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2275 if (!(ah->caps.hw_caps &
2276 ATH9K_HW_CAP_AUTOSLEEP)) {
2277 ath9k_hw_setrxabort(sc->sc_ah, 0);
2278 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2279 SC_OP_WAIT_FOR_CAB |
2280 SC_OP_WAIT_FOR_PSPOLL_DATA |
2281 SC_OP_WAIT_FOR_TX_ACK);
2282 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2283 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2284 ath9k_hw_set_interrupts(sc->sc_ah,
2291 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2292 struct ieee80211_channel *curchan = hw->conf.channel;
2293 int pos = curchan->hw_value;
2295 aphy->chan_idx = pos;
2296 aphy->chan_is_ht = conf_is_ht(conf);
2298 if (aphy->state == ATH_WIPHY_SCAN ||
2299 aphy->state == ATH_WIPHY_ACTIVE)
2300 ath9k_wiphy_pause_all_forced(sc, aphy);
2303 * Do not change operational channel based on a paused
2306 goto skip_chan_change;
2309 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2310 curchan->center_freq);
2312 /* XXX: remove me eventualy */
2313 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2315 ath_update_chainmask(sc, conf_is_ht(conf));
2317 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2318 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2319 mutex_unlock(&sc->mutex);
2325 if (changed & IEEE80211_CONF_CHANGE_POWER)
2326 sc->config.txpowlimit = 2 * conf->power_level;
2328 mutex_unlock(&sc->mutex);
2333 #define SUPPORTED_FILTERS \
2334 (FIF_PROMISC_IN_BSS | \
2338 FIF_BCN_PRBRESP_PROMISC | \
2341 /* FIXME: sc->sc_full_reset ? */
2342 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2343 unsigned int changed_flags,
2344 unsigned int *total_flags,
2346 struct dev_mc_list *mclist)
2348 struct ath_wiphy *aphy = hw->priv;
2349 struct ath_softc *sc = aphy->sc;
2352 changed_flags &= SUPPORTED_FILTERS;
2353 *total_flags &= SUPPORTED_FILTERS;
2355 sc->rx.rxfilter = *total_flags;
2356 ath9k_ps_wakeup(sc);
2357 rfilt = ath_calcrxfilter(sc);
2358 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2359 ath9k_ps_restore(sc);
2361 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2364 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2365 struct ieee80211_vif *vif,
2366 enum sta_notify_cmd cmd,
2367 struct ieee80211_sta *sta)
2369 struct ath_wiphy *aphy = hw->priv;
2370 struct ath_softc *sc = aphy->sc;
2373 case STA_NOTIFY_ADD:
2374 ath_node_attach(sc, sta);
2376 case STA_NOTIFY_REMOVE:
2377 ath_node_detach(sc, sta);
2384 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2385 const struct ieee80211_tx_queue_params *params)
2387 struct ath_wiphy *aphy = hw->priv;
2388 struct ath_softc *sc = aphy->sc;
2389 struct ath9k_tx_queue_info qi;
2392 if (queue >= WME_NUM_AC)
2395 mutex_lock(&sc->mutex);
2397 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2399 qi.tqi_aifs = params->aifs;
2400 qi.tqi_cwmin = params->cw_min;
2401 qi.tqi_cwmax = params->cw_max;
2402 qi.tqi_burstTime = params->txop;
2403 qnum = ath_get_hal_qnum(queue, sc);
2405 DPRINTF(sc, ATH_DBG_CONFIG,
2406 "Configure tx [queue/halq] [%d/%d], "
2407 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2408 queue, qnum, params->aifs, params->cw_min,
2409 params->cw_max, params->txop);
2411 ret = ath_txq_update(sc, qnum, &qi);
2413 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2415 mutex_unlock(&sc->mutex);
2420 static int ath9k_set_key(struct ieee80211_hw *hw,
2421 enum set_key_cmd cmd,
2422 struct ieee80211_vif *vif,
2423 struct ieee80211_sta *sta,
2424 struct ieee80211_key_conf *key)
2426 struct ath_wiphy *aphy = hw->priv;
2427 struct ath_softc *sc = aphy->sc;
2430 if (modparam_nohwcrypt)
2433 mutex_lock(&sc->mutex);
2434 ath9k_ps_wakeup(sc);
2435 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2439 ret = ath_key_config(sc, vif, sta, key);
2441 key->hw_key_idx = ret;
2442 /* push IV and Michael MIC generation to stack */
2443 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2444 if (key->alg == ALG_TKIP)
2445 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2446 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2447 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2452 ath_key_delete(sc, key);
2458 ath9k_ps_restore(sc);
2459 mutex_unlock(&sc->mutex);
2464 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2465 struct ieee80211_vif *vif,
2466 struct ieee80211_bss_conf *bss_conf,
2469 struct ath_wiphy *aphy = hw->priv;
2470 struct ath_softc *sc = aphy->sc;
2471 struct ath_hw *ah = sc->sc_ah;
2472 struct ath_vif *avp = (void *)vif->drv_priv;
2476 mutex_lock(&sc->mutex);
2479 * TODO: Need to decide which hw opmode to use for
2480 * multi-interface cases
2481 * XXX: This belongs into add_interface!
2483 if (vif->type == NL80211_IFTYPE_AP &&
2484 ah->opmode != NL80211_IFTYPE_AP) {
2485 ah->opmode = NL80211_IFTYPE_STATION;
2486 ath9k_hw_setopmode(ah);
2487 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2489 ath9k_hw_write_associd(sc);
2490 /* Request full reset to get hw opmode changed properly */
2491 sc->sc_flags |= SC_OP_FULL_RESET;
2494 if ((changed & BSS_CHANGED_BSSID) &&
2495 !is_zero_ether_addr(bss_conf->bssid)) {
2496 switch (vif->type) {
2497 case NL80211_IFTYPE_STATION:
2498 case NL80211_IFTYPE_ADHOC:
2499 case NL80211_IFTYPE_MESH_POINT:
2501 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2502 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2504 ath9k_hw_write_associd(sc);
2506 /* Set aggregation protection mode parameters */
2507 sc->config.ath_aggr_prot = 0;
2509 DPRINTF(sc, ATH_DBG_CONFIG,
2510 "RX filter 0x%x bssid %pM aid 0x%x\n",
2511 rfilt, sc->curbssid, sc->curaid);
2513 /* need to reconfigure the beacon */
2514 sc->sc_flags &= ~SC_OP_BEACONS ;
2522 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2523 (vif->type == NL80211_IFTYPE_AP) ||
2524 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2525 if ((changed & BSS_CHANGED_BEACON) ||
2526 (changed & BSS_CHANGED_BEACON_ENABLED &&
2527 bss_conf->enable_beacon)) {
2529 * Allocate and setup the beacon frame.
2531 * Stop any previous beacon DMA. This may be
2532 * necessary, for example, when an ibss merge
2533 * causes reconfiguration; we may be called
2534 * with beacon transmission active.
2536 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2538 error = ath_beacon_alloc(aphy, vif);
2540 ath_beacon_config(sc, vif);
2544 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2545 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2546 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2547 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2548 ath9k_hw_keysetmac(sc->sc_ah,
2553 /* Only legacy IBSS for now */
2554 if (vif->type == NL80211_IFTYPE_ADHOC)
2555 ath_update_chainmask(sc, 0);
2557 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2558 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2559 bss_conf->use_short_preamble);
2560 if (bss_conf->use_short_preamble)
2561 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2563 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2566 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2567 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2568 bss_conf->use_cts_prot);
2569 if (bss_conf->use_cts_prot &&
2570 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2571 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2573 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2576 if (changed & BSS_CHANGED_ASSOC) {
2577 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2579 ath9k_bss_assoc_info(sc, vif, bss_conf);
2583 * The HW TSF has to be reset when the beacon interval changes.
2584 * We set the flag here, and ath_beacon_config_ap() would take this
2585 * into account when it gets called through the subsequent
2586 * config_interface() call - with IFCC_BEACON in the changed field.
2589 if (changed & BSS_CHANGED_BEACON_INT) {
2590 sc->sc_flags |= SC_OP_TSF_RESET;
2591 sc->beacon_interval = bss_conf->beacon_int;
2594 mutex_unlock(&sc->mutex);
2597 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2600 struct ath_wiphy *aphy = hw->priv;
2601 struct ath_softc *sc = aphy->sc;
2603 mutex_lock(&sc->mutex);
2604 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2605 mutex_unlock(&sc->mutex);
2610 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2612 struct ath_wiphy *aphy = hw->priv;
2613 struct ath_softc *sc = aphy->sc;
2615 mutex_lock(&sc->mutex);
2616 ath9k_hw_settsf64(sc->sc_ah, tsf);
2617 mutex_unlock(&sc->mutex);
2620 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2622 struct ath_wiphy *aphy = hw->priv;
2623 struct ath_softc *sc = aphy->sc;
2625 mutex_lock(&sc->mutex);
2626 ath9k_hw_reset_tsf(sc->sc_ah);
2627 mutex_unlock(&sc->mutex);
2630 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2631 enum ieee80211_ampdu_mlme_action action,
2632 struct ieee80211_sta *sta,
2635 struct ath_wiphy *aphy = hw->priv;
2636 struct ath_softc *sc = aphy->sc;
2640 case IEEE80211_AMPDU_RX_START:
2641 if (!(sc->sc_flags & SC_OP_RXAGGR))
2644 case IEEE80211_AMPDU_RX_STOP:
2646 case IEEE80211_AMPDU_TX_START:
2647 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2649 DPRINTF(sc, ATH_DBG_FATAL,
2650 "Unable to start TX aggregation\n");
2652 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2654 case IEEE80211_AMPDU_TX_STOP:
2655 ret = ath_tx_aggr_stop(sc, sta, tid);
2657 DPRINTF(sc, ATH_DBG_FATAL,
2658 "Unable to stop TX aggregation\n");
2660 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2662 case IEEE80211_AMPDU_TX_OPERATIONAL:
2663 ath_tx_aggr_resume(sc, sta, tid);
2666 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2672 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2674 struct ath_wiphy *aphy = hw->priv;
2675 struct ath_softc *sc = aphy->sc;
2677 if (ath9k_wiphy_scanning(sc)) {
2678 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2681 * Do not allow the concurrent scanning state for now. This
2682 * could be improved with scanning control moved into ath9k.
2687 aphy->state = ATH_WIPHY_SCAN;
2688 ath9k_wiphy_pause_all_forced(sc, aphy);
2690 spin_lock_bh(&sc->ani_lock);
2691 sc->sc_flags |= SC_OP_SCANNING;
2692 spin_unlock_bh(&sc->ani_lock);
2695 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2697 struct ath_wiphy *aphy = hw->priv;
2698 struct ath_softc *sc = aphy->sc;
2700 spin_lock_bh(&sc->ani_lock);
2701 aphy->state = ATH_WIPHY_ACTIVE;
2702 sc->sc_flags &= ~SC_OP_SCANNING;
2703 sc->sc_flags |= SC_OP_FULL_RESET;
2704 spin_unlock_bh(&sc->ani_lock);
2707 struct ieee80211_ops ath9k_ops = {
2709 .start = ath9k_start,
2711 .add_interface = ath9k_add_interface,
2712 .remove_interface = ath9k_remove_interface,
2713 .config = ath9k_config,
2714 .configure_filter = ath9k_configure_filter,
2715 .sta_notify = ath9k_sta_notify,
2716 .conf_tx = ath9k_conf_tx,
2717 .bss_info_changed = ath9k_bss_info_changed,
2718 .set_key = ath9k_set_key,
2719 .get_tsf = ath9k_get_tsf,
2720 .set_tsf = ath9k_set_tsf,
2721 .reset_tsf = ath9k_reset_tsf,
2722 .ampdu_action = ath9k_ampdu_action,
2723 .sw_scan_start = ath9k_sw_scan_start,
2724 .sw_scan_complete = ath9k_sw_scan_complete,
2725 .rfkill_poll = ath9k_rfkill_poll_state,
2731 } ath_mac_bb_names[] = {
2732 { AR_SREV_VERSION_5416_PCI, "5416" },
2733 { AR_SREV_VERSION_5416_PCIE, "5418" },
2734 { AR_SREV_VERSION_9100, "9100" },
2735 { AR_SREV_VERSION_9160, "9160" },
2736 { AR_SREV_VERSION_9280, "9280" },
2737 { AR_SREV_VERSION_9285, "9285" }
2743 } ath_rf_names[] = {
2745 { AR_RAD5133_SREV_MAJOR, "5133" },
2746 { AR_RAD5122_SREV_MAJOR, "5122" },
2747 { AR_RAD2133_SREV_MAJOR, "2133" },
2748 { AR_RAD2122_SREV_MAJOR, "2122" }
2752 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2755 ath_mac_bb_name(u32 mac_bb_version)
2759 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2760 if (ath_mac_bb_names[i].version == mac_bb_version) {
2761 return ath_mac_bb_names[i].name;
2769 * Return the RF name. "????" is returned if the RF is unknown.
2772 ath_rf_name(u16 rf_version)
2776 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2777 if (ath_rf_names[i].version == rf_version) {
2778 return ath_rf_names[i].name;
2785 static int __init ath9k_init(void)
2789 /* Register rate control algorithm */
2790 error = ath_rate_control_register();
2793 "ath9k: Unable to register rate control "
2799 error = ath9k_debug_create_root();
2802 "ath9k: Unable to create debugfs root: %d\n",
2804 goto err_rate_unregister;
2807 error = ath_pci_init();
2810 "ath9k: No PCI devices found, driver not installed.\n");
2812 goto err_remove_root;
2815 error = ath_ahb_init();
2827 ath9k_debug_remove_root();
2828 err_rate_unregister:
2829 ath_rate_control_unregister();
2833 module_init(ath9k_init);
2835 static void __exit ath9k_exit(void)
2839 ath9k_debug_remove_root();
2840 ath_rate_control_unregister();
2841 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2843 module_exit(ath9k_exit);