2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
34 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
49 #define AR5416_AR9100_DEVID 0x000b
51 #define AR_SUBVENDOR_ID_NOG 0x0e11
52 #define AR_SUBVENDOR_ID_NEW_A 0x7065
53 #define AR5416_MAGIC 0x19641014
55 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
56 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
59 #define AR9300_NUM_BT_WEIGHTS 4
60 #define AR9300_NUM_WLAN_WEIGHTS 4
62 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
64 #define ATH_DEFAULT_NOISE_FLOOR -95
66 #define ATH9K_RSSI_BAD -128
68 #define ATH9K_NUM_CHANNELS 38
70 /* Register read/write primitives */
71 #define REG_WRITE(_ah, _reg, _val) \
72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
74 #define REG_READ(_ah, _reg) \
75 (_ah)->reg_ops.read((_ah), (_reg))
77 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
80 #define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
83 #define ENABLE_REGWRITE_BUFFER(_ah) \
85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
89 #define REGWRITE_BUFFER_FLUSH(_ah) \
91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
95 #define SM(_v, _f) (((_v) << _f##_S) & _f)
96 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
97 #define REG_RMW_FIELD(_a, _r, _f, _v) \
98 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
99 #define REG_READ_FIELD(_a, _r, _f) \
100 (((REG_READ(_a, _r) & _f) >> _f##_S))
101 #define REG_SET_BIT(_a, _r, _f) \
102 REG_RMW(_a, _r, (_f), 0)
103 #define REG_CLR_BIT(_a, _r, _f) \
104 REG_RMW(_a, _r, 0, (_f))
106 #define DO_DELAY(x) do { \
107 if (((++(x) % 64) == 0) && \
108 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
113 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
114 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
116 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
117 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
119 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
120 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
121 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
124 #define AR_GPIOD_MASK 0x00001FFF
125 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
127 #define BASE_ACTIVATE_DELAY 100
128 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
129 #define COEF_SCALE_S 24
130 #define HT40_CHANNEL_CENTER_SHIFT 10
132 #define ATH9K_ANTENNA0_CHAINMASK 0x1
133 #define ATH9K_ANTENNA1_CHAINMASK 0x2
135 #define ATH9K_NUM_DMA_DEBUG_REGS 8
136 #define ATH9K_NUM_QUEUES 10
138 #define MAX_RATE_POWER 63
139 #define AH_WAIT_TIMEOUT 100000 /* (us) */
140 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
141 #define AH_TIME_QUANTUM 10
142 #define AR_KEYTABLE_SIZE 128
143 #define POWER_UP_TIME 10000
144 #define SPUR_RSSI_THRESH 40
146 #define CAB_TIMEOUT_VAL 10
147 #define BEACON_TIMEOUT_VAL 10
148 #define MIN_BEACON_TIMEOUT_VAL 1
151 #define INIT_CONFIG_STATUS 0x00000000
152 #define INIT_RSSI_THR 0x00000700
153 #define INIT_BCON_CNTRL_REG 0x00000000
155 #define TU_TO_USEC(_tu) ((_tu) << 10)
157 #define ATH9K_HW_RX_HP_QDEPTH 16
158 #define ATH9K_HW_RX_LP_QDEPTH 128
160 #define PAPRD_GAIN_TABLE_ENTRIES 32
161 #define PAPRD_TABLE_SZ 24
163 enum ath_hw_txq_subtype {
170 enum ath_ini_subsys {
178 ATH9K_HW_CAP_HT = BIT(0),
179 ATH9K_HW_CAP_RFSILENT = BIT(1),
180 ATH9K_HW_CAP_CST = BIT(2),
181 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
182 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
183 ATH9K_HW_CAP_EDMA = BIT(6),
184 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
185 ATH9K_HW_CAP_LDPC = BIT(8),
186 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
187 ATH9K_HW_CAP_SGI_20 = BIT(10),
188 ATH9K_HW_CAP_PAPRD = BIT(11),
189 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
190 ATH9K_HW_CAP_2GHZ = BIT(13),
191 ATH9K_HW_CAP_5GHZ = BIT(14),
192 ATH9K_HW_CAP_APM = BIT(15),
195 struct ath9k_hw_capabilities {
196 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
209 bool pcie_lcr_extsync_en;
212 struct ath9k_ops_config {
213 int dma_beacon_response_time;
214 int sw_beacon_response_time;
215 int additional_swba_backoff;
217 u32 cwm_ignore_extcca;
218 u8 pcie_powersave_enable;
219 bool pcieSerDesWrite;
229 int serialize_regmode;
230 bool rx_intr_mitigation;
231 bool tx_intr_mitigation;
232 #define SPUR_DISABLE 0
233 #define SPUR_ENABLE_IOCTL 1
234 #define SPUR_ENABLE_EEPROM 2
235 #define AR_SPUR_5413_1 1640
236 #define AR_SPUR_5413_2 1200
237 #define AR_NO_SPUR 0x8000
238 #define AR_BASE_FREQ_2GHZ 2300
239 #define AR_BASE_FREQ_5GHZ 4900
240 #define AR_SPUR_FEEQ_BOUND_HT40 19
241 #define AR_SPUR_FEEQ_BOUND_HT20 10
243 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
245 u16 ani_poll_interval; /* ANI poll interval in ms */
249 ATH9K_INT_RX = 0x00000001,
250 ATH9K_INT_RXDESC = 0x00000002,
251 ATH9K_INT_RXHP = 0x00000001,
252 ATH9K_INT_RXLP = 0x00000002,
253 ATH9K_INT_RXNOFRM = 0x00000008,
254 ATH9K_INT_RXEOL = 0x00000010,
255 ATH9K_INT_RXORN = 0x00000020,
256 ATH9K_INT_TX = 0x00000040,
257 ATH9K_INT_TXDESC = 0x00000080,
258 ATH9K_INT_TIM_TIMER = 0x00000100,
259 ATH9K_INT_BB_WATCHDOG = 0x00000400,
260 ATH9K_INT_TXURN = 0x00000800,
261 ATH9K_INT_MIB = 0x00001000,
262 ATH9K_INT_RXPHY = 0x00004000,
263 ATH9K_INT_RXKCM = 0x00008000,
264 ATH9K_INT_SWBA = 0x00010000,
265 ATH9K_INT_BMISS = 0x00040000,
266 ATH9K_INT_BNR = 0x00100000,
267 ATH9K_INT_TIM = 0x00200000,
268 ATH9K_INT_DTIM = 0x00400000,
269 ATH9K_INT_DTIMSYNC = 0x00800000,
270 ATH9K_INT_GPIO = 0x01000000,
271 ATH9K_INT_CABEND = 0x02000000,
272 ATH9K_INT_TSFOOR = 0x04000000,
273 ATH9K_INT_GENTIMER = 0x08000000,
274 ATH9K_INT_CST = 0x10000000,
275 ATH9K_INT_GTT = 0x20000000,
276 ATH9K_INT_FATAL = 0x40000000,
277 ATH9K_INT_GLOBAL = 0x80000000,
278 ATH9K_INT_BMISC = ATH9K_INT_TIM |
283 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
295 ATH9K_INT_NOCARD = 0xffffffff
298 #define CHANNEL_CW_INT 0x00002
299 #define CHANNEL_CCK 0x00020
300 #define CHANNEL_OFDM 0x00040
301 #define CHANNEL_2GHZ 0x00080
302 #define CHANNEL_5GHZ 0x00100
303 #define CHANNEL_PASSIVE 0x00200
304 #define CHANNEL_DYN 0x00400
305 #define CHANNEL_HALF 0x04000
306 #define CHANNEL_QUARTER 0x08000
307 #define CHANNEL_HT20 0x10000
308 #define CHANNEL_HT40PLUS 0x20000
309 #define CHANNEL_HT40MINUS 0x40000
311 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
312 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
313 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
314 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
315 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
316 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
317 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
318 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
319 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
320 #define CHANNEL_ALL \
329 struct ath9k_hw_cal_data {
337 bool nfcal_interference;
338 u16 small_signal_gain[AR9300_MAX_CHAINS];
339 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
340 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
343 struct ath9k_channel {
344 struct ieee80211_channel *chan;
345 struct ar5416AniState ani;
352 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
353 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
354 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
355 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
356 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
357 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
358 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
359 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
360 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
361 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
362 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
363 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
365 /* These macros check chanmode and not channelFlags */
366 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
367 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
368 ((_c)->chanmode == CHANNEL_G_HT20))
369 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
370 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
371 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
372 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
373 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
375 enum ath9k_power_mode {
378 ATH9K_PM_NETWORK_SLEEP,
382 enum ath9k_tp_scale {
383 ATH9K_TP_SCALE_MAX = 0,
391 SER_REG_MODE_OFF = 0,
393 SER_REG_MODE_AUTO = 2,
396 enum ath9k_rx_qtype {
402 struct ath9k_beacon_state {
406 #define ATH9K_BEACON_PERIOD 0x0000ffff
407 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
410 u16 bs_cfpmaxduration;
413 u16 bs_bmissthreshold;
414 u32 bs_sleepduration;
415 u32 bs_tsfoor_threshold;
418 struct chan_centers {
425 ATH9K_RESET_POWER_ON,
430 struct ath9k_hw_version {
440 enum ath_usb_dev usbdev;
443 /* Generic TSF timer definitions */
445 #define ATH_MAX_GEN_TIMER 16
447 #define AR_GENTMR_BIT(_index) (1 << (_index))
450 * Using de Bruijin sequence to look up 1's index in a 32 bit number
451 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
453 #define debruijn32 0x077CB531U
455 struct ath_gen_timer_configuration {
462 struct ath_gen_timer {
463 void (*trigger)(void *arg);
464 void (*overflow)(void *arg);
469 struct ath_gen_timer_table {
470 u32 gen_timer_index[32];
471 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
473 unsigned long timer_bits;
478 struct ath_hw_antcomb_conf {
485 * struct ath_hw_radar_conf - radar detection initialization parameters
487 * @pulse_inband: threshold for checking the ratio of in-band power
488 * to total power for short radar pulses (half dB steps)
489 * @pulse_inband_step: threshold for checking an in-band power to total
490 * power ratio increase for short radar pulses (half dB steps)
491 * @pulse_height: threshold for detecting the beginning of a short
492 * radar pulse (dB step)
493 * @pulse_rssi: threshold for detecting if a short radar pulse is
495 * @pulse_maxlen: maximum pulse length (0.8 us steps)
497 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
498 * @radar_inband: threshold for checking the ratio of in-band power
499 * to total power for long radar pulses (half dB steps)
500 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
502 * @ext_channel: enable extension channel radar detection
504 struct ath_hw_radar_conf {
505 unsigned int pulse_inband;
506 unsigned int pulse_inband_step;
507 unsigned int pulse_height;
508 unsigned int pulse_rssi;
509 unsigned int pulse_maxlen;
511 unsigned int radar_rssi;
512 unsigned int radar_inband;
519 * struct ath_hw_private_ops - callbacks used internally by hardware code
521 * This structure contains private callbacks designed to only be used internally
522 * by the hardware core.
524 * @init_cal_settings: setup types of calibrations supported
525 * @init_cal: starts actual calibration
527 * @init_mode_regs: Initializes mode registers
528 * @init_mode_gain_regs: Initialize TX/RX gain registers
530 * @rf_set_freq: change frequency
531 * @spur_mitigate_freq: spur mitigation
532 * @rf_alloc_ext_banks:
533 * @rf_free_ext_banks:
535 * @compute_pll_control: compute the PLL control value to use for
536 * AR_RTC_PLL_CONTROL for a given channel
537 * @setup_calibration: set up calibration
538 * @iscal_supported: used to query if a type of calibration is supported
540 * @ani_cache_ini_regs: cache the values for ANI from the initial
541 * register settings through the register initialization.
543 struct ath_hw_private_ops {
544 /* Calibration ops */
545 void (*init_cal_settings)(struct ath_hw *ah);
546 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
548 void (*init_mode_regs)(struct ath_hw *ah);
549 void (*init_mode_gain_regs)(struct ath_hw *ah);
550 void (*setup_calibration)(struct ath_hw *ah,
551 struct ath9k_cal_list *currCal);
554 int (*rf_set_freq)(struct ath_hw *ah,
555 struct ath9k_channel *chan);
556 void (*spur_mitigate_freq)(struct ath_hw *ah,
557 struct ath9k_channel *chan);
558 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
559 void (*rf_free_ext_banks)(struct ath_hw *ah);
560 bool (*set_rf_regs)(struct ath_hw *ah,
561 struct ath9k_channel *chan,
563 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
564 void (*init_bb)(struct ath_hw *ah,
565 struct ath9k_channel *chan);
566 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
567 void (*olc_init)(struct ath_hw *ah);
568 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
569 void (*mark_phy_inactive)(struct ath_hw *ah);
570 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
571 bool (*rfbus_req)(struct ath_hw *ah);
572 void (*rfbus_done)(struct ath_hw *ah);
573 void (*restore_chainmask)(struct ath_hw *ah);
574 void (*set_diversity)(struct ath_hw *ah, bool value);
575 u32 (*compute_pll_control)(struct ath_hw *ah,
576 struct ath9k_channel *chan);
577 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
579 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
580 void (*set_radar_params)(struct ath_hw *ah,
581 struct ath_hw_radar_conf *conf);
584 void (*ani_cache_ini_regs)(struct ath_hw *ah);
588 * struct ath_hw_ops - callbacks used by hardware code and driver code
590 * This structure contains callbacks designed to to be used internally by
591 * hardware code and also by the lower level driver.
593 * @config_pci_powersave:
594 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
597 void (*config_pci_powersave)(struct ath_hw *ah,
600 void (*rx_enable)(struct ath_hw *ah);
601 void (*set_desc_link)(void *ds, u32 link);
602 void (*get_desc_link)(void *ds, u32 **link);
603 bool (*calibrate)(struct ath_hw *ah,
604 struct ath9k_channel *chan,
607 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
608 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
609 bool is_firstseg, bool is_is_lastseg,
610 const void *ds0, dma_addr_t buf_addr,
612 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
613 struct ath_tx_status *ts);
614 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
615 u32 pktLen, enum ath9k_pkt_type type,
616 u32 txPower, u32 keyIx,
617 enum ath9k_key_type keyType,
619 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
621 u32 durUpdateEn, u32 rtsctsRate,
623 struct ath9k_11n_rate_series series[],
624 u32 nseries, u32 flags);
625 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
627 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
629 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
630 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
631 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
634 struct ath_nf_limits {
641 #define AH_USE_EEPROM 0x1
642 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
645 struct ath_ops reg_ops;
647 struct ieee80211_hw *hw;
648 struct ath_common common;
649 struct ath9k_hw_version hw_version;
650 struct ath9k_ops_config config;
651 struct ath9k_hw_capabilities caps;
652 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
653 struct ath9k_channel *curchan;
656 struct ar5416_eeprom_def def;
657 struct ar5416_eeprom_4k map4k;
658 struct ar9287_eeprom map9287;
659 struct ar9300_eeprom ar9300_eep;
661 const struct eeprom_ops *eep_ops;
666 bool need_an_top2_fixup;
670 struct ath_nf_limits nf_2g;
671 struct ath_nf_limits nf_5g;
679 enum nl80211_iftype opmode;
680 enum ath9k_power_mode power_mode;
682 struct ath9k_hw_cal_data *caldata;
683 struct ath9k_pacal_info pacal_info;
684 struct ar5416Stats stats;
685 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
687 int16_t curchan_rad_index;
688 enum ath9k_int imask;
690 u32 txok_interrupt_mask;
691 u32 txerr_interrupt_mask;
692 u32 txdesc_interrupt_mask;
693 u32 txeol_interrupt_mask;
694 u32 txurn_interrupt_mask;
700 struct ath9k_cal_list iq_caldata;
701 struct ath9k_cal_list adcgain_caldata;
702 struct ath9k_cal_list adcdc_caldata;
703 struct ath9k_cal_list tempCompCalData;
704 struct ath9k_cal_list *cal_list;
705 struct ath9k_cal_list *cal_list_last;
706 struct ath9k_cal_list *cal_list_curr;
707 #define totalPowerMeasI meas0.unsign
708 #define totalPowerMeasQ meas1.unsign
709 #define totalIqCorrMeas meas2.sign
710 #define totalAdcIOddPhase meas0.unsign
711 #define totalAdcIEvenPhase meas1.unsign
712 #define totalAdcQOddPhase meas2.unsign
713 #define totalAdcQEvenPhase meas3.unsign
714 #define totalAdcDcOffsetIOddPhase meas0.sign
715 #define totalAdcDcOffsetIEvenPhase meas1.sign
716 #define totalAdcDcOffsetQOddPhase meas2.sign
717 #define totalAdcDcOffsetQEvenPhase meas3.sign
719 u32 unsign[AR5416_MAX_CHAINS];
720 int32_t sign[AR5416_MAX_CHAINS];
723 u32 unsign[AR5416_MAX_CHAINS];
724 int32_t sign[AR5416_MAX_CHAINS];
727 u32 unsign[AR5416_MAX_CHAINS];
728 int32_t sign[AR5416_MAX_CHAINS];
731 u32 unsign[AR5416_MAX_CHAINS];
732 int32_t sign[AR5416_MAX_CHAINS];
736 u32 sta_id1_defaults;
742 } enable_32kHz_clock;
744 /* Private to hardware code */
745 struct ath_hw_private_ops private_ops;
746 /* Accessed by the lower level driver */
747 struct ath_hw_ops ops;
749 /* Used to program the radio on non single-chip devices */
750 u32 *analogBank0Data;
751 u32 *analogBank1Data;
752 u32 *analogBank2Data;
753 u32 *analogBank3Data;
754 u32 *analogBank6Data;
755 u32 *analogBank6TPCData;
756 u32 *analogBank7Data;
768 int totalSizeDesired[5];
772 enum ath9k_ani_cmd ani_function;
774 /* Bluetooth coexistance */
775 struct ath_btcoex_hw btcoex_hw;
776 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
777 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
783 struct ath_hw_radar_conf radar_conf;
785 u32 originalGain[22];
792 struct ar5416IniArray iniModes;
793 struct ar5416IniArray iniCommon;
794 struct ar5416IniArray iniBank0;
795 struct ar5416IniArray iniBB_RfGain;
796 struct ar5416IniArray iniBank1;
797 struct ar5416IniArray iniBank2;
798 struct ar5416IniArray iniBank3;
799 struct ar5416IniArray iniBank6;
800 struct ar5416IniArray iniBank6TPC;
801 struct ar5416IniArray iniBank7;
802 struct ar5416IniArray iniAddac;
803 struct ar5416IniArray iniPcieSerdes;
804 struct ar5416IniArray iniPcieSerdesLowPower;
805 struct ar5416IniArray iniModesAdditional;
806 struct ar5416IniArray iniModesAdditional_40M;
807 struct ar5416IniArray iniModesRxGain;
808 struct ar5416IniArray iniModesTxGain;
809 struct ar5416IniArray iniModes_9271_1_0_only;
810 struct ar5416IniArray iniCckfirNormal;
811 struct ar5416IniArray iniCckfirJapan2484;
812 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
813 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
814 struct ar5416IniArray iniModes_9271_ANI_reg;
815 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
816 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
818 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
819 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
820 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
821 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
823 u32 intr_gen_timer_trigger;
824 u32 intr_gen_timer_thresh;
825 struct ath_gen_timer_table hw_gen_timers;
827 struct ar9003_txs *ts_ring;
834 u32 bb_watchdog_last_status;
835 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
837 unsigned int paprd_target_power;
838 unsigned int paprd_training_power;
839 unsigned int paprd_ratemask;
840 unsigned int paprd_ratemask_ht40;
841 bool paprd_table_write_done;
842 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
843 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
845 * Store the permanent value of Reg 0x4004in WARegVal
846 * so we dont have to R/M/W. We should not be reading
847 * this register when in sleep states.
851 /* Enterprise mode cap */
858 enum ath_bus_type ath_bus_type;
859 void (*read_cachesize)(struct ath_common *common, int *csz);
860 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
861 void (*bt_coex_prep)(struct ath_common *common);
862 void (*extn_synch_en)(struct ath_common *common);
865 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
870 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
872 return &(ath9k_hw_common(ah)->regulatory);
875 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
877 return &ah->private_ops;
880 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
885 static inline u8 get_streams(int mask)
887 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
890 /* Initialization, Detach, Reset */
891 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
892 void ath9k_hw_deinit(struct ath_hw *ah);
893 int ath9k_hw_init(struct ath_hw *ah);
894 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
895 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
896 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
897 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
899 /* GPIO / RFKILL / Antennae */
900 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
901 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
902 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
904 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
905 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
906 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
907 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
908 struct ath_hw_antcomb_conf *antconf);
909 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
910 struct ath_hw_antcomb_conf *antconf);
912 /* General Operation */
913 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
914 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
915 int column, unsigned int *writecnt);
916 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
917 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
919 u32 frameLen, u16 rateix, bool shortPreamble);
920 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
921 struct ath9k_channel *chan,
922 struct chan_centers *centers);
923 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
924 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
925 bool ath9k_hw_phy_disable(struct ath_hw *ah);
926 bool ath9k_hw_disable(struct ath_hw *ah);
927 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
928 void ath9k_hw_setopmode(struct ath_hw *ah);
929 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
930 void ath9k_hw_setbssidmask(struct ath_hw *ah);
931 void ath9k_hw_write_associd(struct ath_hw *ah);
932 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
933 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
934 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
935 void ath9k_hw_reset_tsf(struct ath_hw *ah);
936 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
937 void ath9k_hw_init_global_settings(struct ath_hw *ah);
938 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
939 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
940 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
941 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
942 const struct ath9k_beacon_state *bs);
943 bool ath9k_hw_check_alive(struct ath_hw *ah);
945 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
947 /* Generic hw timer primitives */
948 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
949 void (*trigger)(void *),
950 void (*overflow)(void *),
953 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
954 struct ath_gen_timer *timer,
957 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
959 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
960 void ath_gen_timer_isr(struct ath_hw *hw);
962 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
965 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
968 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
969 u32 *coef_mantissa, u32 *coef_exponent);
972 * Code Specific to AR5008, AR9001 or AR9002,
973 * we stuff these here to avoid callbacks for AR9003.
975 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
976 int ar9002_hw_rf_claim(struct ath_hw *ah);
977 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
978 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
979 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
982 * Code specific to AR9003, we stuff these here to avoid callbacks
985 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
986 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
987 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
988 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
989 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
990 struct ath9k_hw_cal_data *caldata,
992 int ar9003_paprd_create_curve(struct ath_hw *ah,
993 struct ath9k_hw_cal_data *caldata, int chain);
994 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
995 int ar9003_paprd_init_table(struct ath_hw *ah);
996 bool ar9003_paprd_is_done(struct ath_hw *ah);
997 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
999 /* Hardware family op attach helpers */
1000 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1001 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1002 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1004 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1005 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1007 void ar9002_hw_attach_ops(struct ath_hw *ah);
1008 void ar9003_hw_attach_ops(struct ath_hw *ah);
1010 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1012 * ANI work can be shared between all families but a next
1013 * generation implementation of ANI will be used only for AR9003 only
1014 * for now as the other families still need to be tested with the same
1015 * next generation ANI. Feel free to start testing it though for the
1016 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1018 extern int modparam_force_new_ani;
1019 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1020 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1021 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1023 #define ATH_PCIE_CAP_LINK_CTRL 0x70
1024 #define ATH_PCIE_CAP_LINK_L0S 1
1025 #define ATH_PCIE_CAP_LINK_L1 2
1027 #define ATH9K_CLOCK_RATE_CCK 22
1028 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1029 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1030 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44