2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
48 #define AR5416_AR9100_DEVID 0x000b
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71 #define ENABLE_REGWRITE_BUFFER(_ah) \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
77 #define DISABLE_REGWRITE_BUFFER(_ah) \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
83 #define REGWRITE_BUFFER_FLUSH(_ah) \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
89 #define SM(_v, _f) (((_v) << _f##_S) & _f)
90 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
91 #define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93 #define REG_RMW_FIELD(_a, _r, _f, _v) \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
96 #define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
98 #define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100 #define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
103 #define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
108 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
117 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
121 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
125 #define AR_GPIOD_MASK 0x00001FFF
126 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
128 #define BASE_ACTIVATE_DELAY 100
129 #define RTC_PLL_SETTLE_DELAY 100
130 #define COEF_SCALE_S 24
131 #define HT40_CHANNEL_CENTER_SHIFT 10
133 #define ATH9K_ANTENNA0_CHAINMASK 0x1
134 #define ATH9K_ANTENNA1_CHAINMASK 0x2
136 #define ATH9K_NUM_DMA_DEBUG_REGS 8
137 #define ATH9K_NUM_QUEUES 10
139 #define MAX_RATE_POWER 63
140 #define AH_WAIT_TIMEOUT 100000 /* (us) */
141 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
142 #define AH_TIME_QUANTUM 10
143 #define AR_KEYTABLE_SIZE 128
144 #define POWER_UP_TIME 10000
145 #define SPUR_RSSI_THRESH 40
147 #define CAB_TIMEOUT_VAL 10
148 #define BEACON_TIMEOUT_VAL 10
149 #define MIN_BEACON_TIMEOUT_VAL 1
152 #define INIT_CONFIG_STATUS 0x00000000
153 #define INIT_RSSI_THR 0x00000700
154 #define INIT_BCON_CNTRL_REG 0x00000000
156 #define TU_TO_USEC(_tu) ((_tu) << 10)
158 #define ATH9K_HW_RX_HP_QDEPTH 16
159 #define ATH9K_HW_RX_LP_QDEPTH 128
161 enum ath_ini_subsys {
171 ATH9K_MODE_11NA_HT20,
172 ATH9K_MODE_11NG_HT20,
173 ATH9K_MODE_11NA_HT40PLUS,
174 ATH9K_MODE_11NA_HT40MINUS,
175 ATH9K_MODE_11NG_HT40PLUS,
176 ATH9K_MODE_11NG_HT40MINUS,
181 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
182 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
183 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
184 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
185 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
186 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
187 ATH9K_HW_CAP_VEOL = BIT(6),
188 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
189 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
190 ATH9K_HW_CAP_HT = BIT(9),
191 ATH9K_HW_CAP_GTT = BIT(10),
192 ATH9K_HW_CAP_FASTCC = BIT(11),
193 ATH9K_HW_CAP_RFSILENT = BIT(12),
194 ATH9K_HW_CAP_CST = BIT(13),
195 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
196 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
197 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
198 ATH9K_HW_CAP_EDMA = BIT(17),
199 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
200 ATH9K_HW_CAP_LDPC = BIT(19),
201 ATH9K_HW_CAP_FASTCLOCK = BIT(20),
202 ATH9K_HW_CAP_SGI_20 = BIT(21),
205 enum ath9k_capability_type {
206 ATH9K_CAP_CIPHER = 0,
208 ATH9K_CAP_TKIP_SPLIT,
210 ATH9K_CAP_MCAST_KEYSRCH,
214 struct ath9k_hw_capabilities {
215 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
216 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
219 u16 low_5ghz_chan, high_5ghz_chan;
220 u16 low_2ghz_chan, high_2ghz_chan;
224 u16 tx_triglevel_max;
236 struct ath9k_ops_config {
237 int dma_beacon_response_time;
238 int sw_beacon_response_time;
239 int additional_swba_backoff;
241 int cwm_ignore_extcca;
242 u8 pcie_powersave_enable;
252 int serialize_regmode;
253 bool rx_intr_mitigation;
254 bool tx_intr_mitigation;
255 #define SPUR_DISABLE 0
256 #define SPUR_ENABLE_IOCTL 1
257 #define SPUR_ENABLE_EEPROM 2
258 #define AR_EEPROM_MODAL_SPURS 5
259 #define AR_SPUR_5413_1 1640
260 #define AR_SPUR_5413_2 1200
261 #define AR_NO_SPUR 0x8000
262 #define AR_BASE_FREQ_2GHZ 2300
263 #define AR_BASE_FREQ_5GHZ 4900
264 #define AR_SPUR_FEEQ_BOUND_HT40 19
265 #define AR_SPUR_FEEQ_BOUND_HT20 10
267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
272 ATH9K_INT_RX = 0x00000001,
273 ATH9K_INT_RXDESC = 0x00000002,
274 ATH9K_INT_RXHP = 0x00000001,
275 ATH9K_INT_RXLP = 0x00000002,
276 ATH9K_INT_RXNOFRM = 0x00000008,
277 ATH9K_INT_RXEOL = 0x00000010,
278 ATH9K_INT_RXORN = 0x00000020,
279 ATH9K_INT_TX = 0x00000040,
280 ATH9K_INT_TXDESC = 0x00000080,
281 ATH9K_INT_TIM_TIMER = 0x00000100,
282 ATH9K_INT_BB_WATCHDOG = 0x00000400,
283 ATH9K_INT_TXURN = 0x00000800,
284 ATH9K_INT_MIB = 0x00001000,
285 ATH9K_INT_RXPHY = 0x00004000,
286 ATH9K_INT_RXKCM = 0x00008000,
287 ATH9K_INT_SWBA = 0x00010000,
288 ATH9K_INT_BMISS = 0x00040000,
289 ATH9K_INT_BNR = 0x00100000,
290 ATH9K_INT_TIM = 0x00200000,
291 ATH9K_INT_DTIM = 0x00400000,
292 ATH9K_INT_DTIMSYNC = 0x00800000,
293 ATH9K_INT_GPIO = 0x01000000,
294 ATH9K_INT_CABEND = 0x02000000,
295 ATH9K_INT_TSFOOR = 0x04000000,
296 ATH9K_INT_GENTIMER = 0x08000000,
297 ATH9K_INT_CST = 0x10000000,
298 ATH9K_INT_GTT = 0x20000000,
299 ATH9K_INT_FATAL = 0x40000000,
300 ATH9K_INT_GLOBAL = 0x80000000,
301 ATH9K_INT_BMISC = ATH9K_INT_TIM |
306 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
318 ATH9K_INT_NOCARD = 0xffffffff
321 #define CHANNEL_CW_INT 0x00002
322 #define CHANNEL_CCK 0x00020
323 #define CHANNEL_OFDM 0x00040
324 #define CHANNEL_2GHZ 0x00080
325 #define CHANNEL_5GHZ 0x00100
326 #define CHANNEL_PASSIVE 0x00200
327 #define CHANNEL_DYN 0x00400
328 #define CHANNEL_HALF 0x04000
329 #define CHANNEL_QUARTER 0x08000
330 #define CHANNEL_HT20 0x10000
331 #define CHANNEL_HT40PLUS 0x20000
332 #define CHANNEL_HT40MINUS 0x40000
334 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
335 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
336 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
337 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
338 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
339 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
340 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
341 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
342 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
343 #define CHANNEL_ALL \
352 struct ath9k_channel {
353 struct ieee80211_channel *chan;
358 bool oneTimeCalsDone;
361 int16_t rawNoiseFloor;
364 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
365 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
366 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
367 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
368 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
369 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
370 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
371 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
372 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
373 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
374 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
375 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
377 /* These macros check chanmode and not channelFlags */
378 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
379 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
380 ((_c)->chanmode == CHANNEL_G_HT20))
381 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
382 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
383 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
384 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
385 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
387 enum ath9k_power_mode {
390 ATH9K_PM_NETWORK_SLEEP,
394 enum ath9k_tp_scale {
395 ATH9K_TP_SCALE_MAX = 0,
403 SER_REG_MODE_OFF = 0,
405 SER_REG_MODE_AUTO = 2,
408 enum ath9k_rx_qtype {
414 struct ath9k_beacon_state {
418 #define ATH9K_BEACON_PERIOD 0x0000ffff
419 #define ATH9K_BEACON_ENA 0x00800000
420 #define ATH9K_BEACON_RESET_TSF 0x01000000
421 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
424 u16 bs_cfpmaxduration;
427 u16 bs_bmissthreshold;
428 u32 bs_sleepduration;
429 u32 bs_tsfoor_threshold;
432 struct chan_centers {
439 ATH9K_RESET_POWER_ON,
444 struct ath9k_hw_version {
456 /* Generic TSF timer definitions */
458 #define ATH_MAX_GEN_TIMER 16
460 #define AR_GENTMR_BIT(_index) (1 << (_index))
463 * Using de Bruijin sequence to look up 1's index in a 32 bit number
464 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
466 #define debruijn32 0x077CB531U
468 struct ath_gen_timer_configuration {
475 struct ath_gen_timer {
476 void (*trigger)(void *arg);
477 void (*overflow)(void *arg);
482 struct ath_gen_timer_table {
483 u32 gen_timer_index[32];
484 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
486 unsigned long timer_bits;
492 * struct ath_hw_private_ops - callbacks used internally by hardware code
494 * This structure contains private callbacks designed to only be used internally
495 * by the hardware core.
497 * @init_cal_settings: setup types of calibrations supported
498 * @init_cal: starts actual calibration
500 * @init_mode_regs: Initializes mode registers
501 * @init_mode_gain_regs: Initialize TX/RX gain registers
502 * @macversion_supported: If this specific mac revision is supported
504 * @rf_set_freq: change frequency
505 * @spur_mitigate_freq: spur mitigation
506 * @rf_alloc_ext_banks:
507 * @rf_free_ext_banks:
509 * @compute_pll_control: compute the PLL control value to use for
510 * AR_RTC_PLL_CONTROL for a given channel
511 * @setup_calibration: set up calibration
512 * @iscal_supported: used to query if a type of calibration is supported
513 * @loadnf: load noise floor read from each chain on the CCA registers
515 * @ani_reset: reset ANI parameters to default values
516 * @ani_lower_immunity: lower the noise immunity level. The level controls
517 * the power-based packet detection on hardware. If a power jump is
518 * detected the adapter takes it as an indication that a packet has
519 * arrived. The level ranges from 0-5. Each level corresponds to a
520 * few dB more of noise immunity. If you have a strong time-varying
521 * interference that is causing false detections (OFDM timing errors or
522 * CCK timing errors) the level can be increased.
524 struct ath_hw_private_ops {
525 /* Calibration ops */
526 void (*init_cal_settings)(struct ath_hw *ah);
527 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
529 void (*init_mode_regs)(struct ath_hw *ah);
530 void (*init_mode_gain_regs)(struct ath_hw *ah);
531 bool (*macversion_supported)(u32 macversion);
532 void (*setup_calibration)(struct ath_hw *ah,
533 struct ath9k_cal_list *currCal);
534 bool (*iscal_supported)(struct ath_hw *ah,
535 enum ath9k_cal_types calType);
538 int (*rf_set_freq)(struct ath_hw *ah,
539 struct ath9k_channel *chan);
540 void (*spur_mitigate_freq)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
543 void (*rf_free_ext_banks)(struct ath_hw *ah);
544 bool (*set_rf_regs)(struct ath_hw *ah,
545 struct ath9k_channel *chan,
547 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
548 void (*init_bb)(struct ath_hw *ah,
549 struct ath9k_channel *chan);
550 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
551 void (*olc_init)(struct ath_hw *ah);
552 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
553 void (*mark_phy_inactive)(struct ath_hw *ah);
554 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
555 bool (*rfbus_req)(struct ath_hw *ah);
556 void (*rfbus_done)(struct ath_hw *ah);
557 void (*enable_rfkill)(struct ath_hw *ah);
558 void (*restore_chainmask)(struct ath_hw *ah);
559 void (*set_diversity)(struct ath_hw *ah, bool value);
560 u32 (*compute_pll_control)(struct ath_hw *ah,
561 struct ath9k_channel *chan);
562 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
564 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
565 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
568 void (*ani_reset)(struct ath_hw *ah);
569 void (*ani_lower_immunity)(struct ath_hw *ah);
573 * struct ath_hw_ops - callbacks used by hardware code and driver code
575 * This structure contains callbacks designed to to be used internally by
576 * hardware code and also by the lower level driver.
578 * @config_pci_powersave:
579 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
581 * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
582 * thresholds being reached or having overflowed.
583 * @ani_monitor: called periodically by the core driver to collect
584 * MIB stats and adjust ANI if specific thresholds have been reached.
587 void (*config_pci_powersave)(struct ath_hw *ah,
590 void (*rx_enable)(struct ath_hw *ah);
591 void (*set_desc_link)(void *ds, u32 link);
592 void (*get_desc_link)(void *ds, u32 **link);
593 bool (*calibrate)(struct ath_hw *ah,
594 struct ath9k_channel *chan,
597 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
598 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
599 bool is_firstseg, bool is_is_lastseg,
600 const void *ds0, dma_addr_t buf_addr,
602 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
603 struct ath_tx_status *ts);
604 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
605 u32 pktLen, enum ath9k_pkt_type type,
606 u32 txPower, u32 keyIx,
607 enum ath9k_key_type keyType,
609 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
611 u32 durUpdateEn, u32 rtsctsRate,
613 struct ath9k_11n_rate_series series[],
614 u32 nseries, u32 flags);
615 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
617 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
619 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
620 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
621 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
623 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
626 void (*ani_proc_mib_event)(struct ath_hw *ah);
627 void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
631 struct ieee80211_hw *hw;
632 struct ath_common common;
633 struct ath9k_hw_version hw_version;
634 struct ath9k_ops_config config;
635 struct ath9k_hw_capabilities caps;
636 struct ath9k_channel channels[38];
637 struct ath9k_channel *curchan;
640 struct ar5416_eeprom_def def;
641 struct ar5416_eeprom_4k map4k;
642 struct ar9287_eeprom map9287;
643 struct ar9300_eeprom ar9300_eep;
645 const struct eeprom_ops *eep_ops;
649 bool need_an_top2_fixup;
662 enum nl80211_iftype opmode;
663 enum ath9k_power_mode power_mode;
665 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
666 struct ath9k_pacal_info pacal_info;
667 struct ar5416Stats stats;
668 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
670 int16_t curchan_rad_index;
671 enum ath9k_int imask;
673 u32 txok_interrupt_mask;
674 u32 txerr_interrupt_mask;
675 u32 txdesc_interrupt_mask;
676 u32 txeol_interrupt_mask;
677 u32 txurn_interrupt_mask;
682 enum ath9k_cal_types supp_cals;
683 struct ath9k_cal_list iq_caldata;
684 struct ath9k_cal_list adcgain_caldata;
685 struct ath9k_cal_list adcdc_calinitdata;
686 struct ath9k_cal_list adcdc_caldata;
687 struct ath9k_cal_list tempCompCalData;
688 struct ath9k_cal_list *cal_list;
689 struct ath9k_cal_list *cal_list_last;
690 struct ath9k_cal_list *cal_list_curr;
691 #define totalPowerMeasI meas0.unsign
692 #define totalPowerMeasQ meas1.unsign
693 #define totalIqCorrMeas meas2.sign
694 #define totalAdcIOddPhase meas0.unsign
695 #define totalAdcIEvenPhase meas1.unsign
696 #define totalAdcQOddPhase meas2.unsign
697 #define totalAdcQEvenPhase meas3.unsign
698 #define totalAdcDcOffsetIOddPhase meas0.sign
699 #define totalAdcDcOffsetIEvenPhase meas1.sign
700 #define totalAdcDcOffsetQOddPhase meas2.sign
701 #define totalAdcDcOffsetQEvenPhase meas3.sign
703 u32 unsign[AR5416_MAX_CHAINS];
704 int32_t sign[AR5416_MAX_CHAINS];
707 u32 unsign[AR5416_MAX_CHAINS];
708 int32_t sign[AR5416_MAX_CHAINS];
711 u32 unsign[AR5416_MAX_CHAINS];
712 int32_t sign[AR5416_MAX_CHAINS];
715 u32 unsign[AR5416_MAX_CHAINS];
716 int32_t sign[AR5416_MAX_CHAINS];
720 u32 sta_id1_defaults;
726 } enable_32kHz_clock;
728 /* Private to hardware code */
729 struct ath_hw_private_ops private_ops;
730 /* Accessed by the lower level driver */
731 struct ath_hw_ops ops;
733 /* Used to program the radio on non single-chip devices */
734 u32 *analogBank0Data;
735 u32 *analogBank1Data;
736 u32 *analogBank2Data;
737 u32 *analogBank3Data;
738 u32 *analogBank6Data;
739 u32 *analogBank6TPCData;
740 u32 *analogBank7Data;
745 int16_t txpower_indexoffset;
754 struct ar5416AniState *curani;
755 struct ar5416AniState ani[255];
756 int totalSizeDesired[5];
760 enum ath9k_ani_cmd ani_function;
762 /* Bluetooth coexistance */
763 struct ath_btcoex_hw btcoex_hw;
769 u32 originalGain[22];
774 struct ar5416IniArray iniModes;
775 struct ar5416IniArray iniCommon;
776 struct ar5416IniArray iniBank0;
777 struct ar5416IniArray iniBB_RfGain;
778 struct ar5416IniArray iniBank1;
779 struct ar5416IniArray iniBank2;
780 struct ar5416IniArray iniBank3;
781 struct ar5416IniArray iniBank6;
782 struct ar5416IniArray iniBank6TPC;
783 struct ar5416IniArray iniBank7;
784 struct ar5416IniArray iniAddac;
785 struct ar5416IniArray iniPcieSerdes;
786 struct ar5416IniArray iniPcieSerdesLowPower;
787 struct ar5416IniArray iniModesAdditional;
788 struct ar5416IniArray iniModesRxGain;
789 struct ar5416IniArray iniModesTxGain;
790 struct ar5416IniArray iniModes_9271_1_0_only;
791 struct ar5416IniArray iniCckfirNormal;
792 struct ar5416IniArray iniCckfirJapan2484;
793 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
794 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
795 struct ar5416IniArray iniModes_9271_ANI_reg;
796 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
797 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
799 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
800 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
801 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
802 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
804 u32 intr_gen_timer_trigger;
805 u32 intr_gen_timer_thresh;
806 struct ath_gen_timer_table hw_gen_timers;
808 struct ar9003_txs *ts_ring;
815 u32 bb_watchdog_last_status;
816 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
819 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
824 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
826 return &(ath9k_hw_common(ah)->regulatory);
829 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
831 return &ah->private_ops;
834 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
839 /* Initialization, Detach, Reset */
840 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
841 void ath9k_hw_deinit(struct ath_hw *ah);
842 int ath9k_hw_init(struct ath_hw *ah);
843 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
844 bool bChannelChange);
845 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
846 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
847 u32 capability, u32 *result);
848 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
849 u32 capability, u32 setting, int *status);
850 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
852 /* Key Cache Management */
853 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
854 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
855 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
856 const struct ath9k_keyval *k,
858 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
860 /* GPIO / RFKILL / Antennae */
861 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
862 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
863 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
865 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
866 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
867 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
869 /* General Operation */
870 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
871 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
872 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
873 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
875 u32 frameLen, u16 rateix, bool shortPreamble);
876 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
877 struct ath9k_channel *chan,
878 struct chan_centers *centers);
879 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
880 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
881 bool ath9k_hw_phy_disable(struct ath_hw *ah);
882 bool ath9k_hw_disable(struct ath_hw *ah);
883 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
884 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
885 void ath9k_hw_setopmode(struct ath_hw *ah);
886 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
887 void ath9k_hw_setbssidmask(struct ath_hw *ah);
888 void ath9k_hw_write_associd(struct ath_hw *ah);
889 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
890 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
891 void ath9k_hw_reset_tsf(struct ath_hw *ah);
892 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
893 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
894 void ath9k_hw_init_global_settings(struct ath_hw *ah);
895 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
896 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
897 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
898 const struct ath9k_beacon_state *bs);
899 bool ath9k_hw_check_alive(struct ath_hw *ah);
901 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
903 /* Generic hw timer primitives */
904 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
905 void (*trigger)(void *),
906 void (*overflow)(void *),
909 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
910 struct ath_gen_timer *timer,
913 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
915 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
916 void ath_gen_timer_isr(struct ath_hw *hw);
917 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
919 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
922 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
925 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
926 u32 *coef_mantissa, u32 *coef_exponent);
929 * Code Specific to AR5008, AR9001 or AR9002,
930 * we stuff these here to avoid callbacks for AR9003.
932 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
933 int ar9002_hw_rf_claim(struct ath_hw *ah);
934 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
935 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
936 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
939 * Code specific to AR9003, we stuff these here to avoid callbacks
942 void ar9003_hw_set_nf_limits(struct ath_hw *ah);
943 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
944 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
945 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
947 /* Hardware family op attach helpers */
948 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
949 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
950 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
952 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
953 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
955 void ar9002_hw_attach_ops(struct ath_hw *ah);
956 void ar9003_hw_attach_ops(struct ath_hw *ah);
959 * ANI work can be shared between all families but a next
960 * generation implementation of ANI will be used only for AR9003 only
961 * for now as the other families still need to be tested with the same
962 * next generation ANI.
964 void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
966 #define ATH_PCIE_CAP_LINK_CTRL 0x70
967 #define ATH_PCIE_CAP_LINK_L0S 1
968 #define ATH_PCIE_CAP_LINK_L1 2
970 #define ATH9K_CLOCK_RATE_CCK 22
971 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
972 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
973 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44