drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static void ath9k_hw_newstate(struct ath_hw *ah)
 441 {
 442         ah->hw_version.magic = AR5416_MAGIC;
 443         ah->regulatory.country_code = CTRY_DEFAULT;
 444         ah->hw_version.subvendorid = 0;
 445
 446         ah->ah_flags = 0;
 447         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 448                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 449         if (!AR_SREV_9100(ah))
 450                 ah->ah_flags = AH_USE_EEPROM;
 451
 452         ah->regulatory.power_limit = MAX_RATE_POWER;
 453         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 454         ah->atim_window = 0;
 455         ah->diversity_control = ah->config.diversity_control;
 456         ah->antenna_switch_swap =
 457                 ah->config.antenna_switch_swap;
 458         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 459         ah->beacon_interval = 100;
 460         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 461         ah->slottime = (u32) -1;
 462         ah->acktimeout = (u32) -1;
 463         ah->ctstimeout = (u32) -1;
 464         ah->globaltxtimeout = (u32) -1;
 465
 466         ah->gbeacon_rate = 0;
 467
 468         ah->power_mode = ATH9K_PM_UNDEFINED;
 469 }
 470
 471 static int ath9k_hw_rfattach(struct ath_hw *ah)
 472 {
 473         bool rfStatus = false;
 474         int ecode = 0;
 475
 476         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 477         if (!rfStatus) {
 478                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 479                         "RF setup failed, status: %u\n", ecode);
 480                 return ecode;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 487 {
 488         u32 val;
 489
 490         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 491
 492         val = ath9k_hw_get_radiorev(ah);
 493         switch (val & AR_RADIO_SREV_MAJOR) {
 494         case 0:
 495                 val = AR_RAD5133_SREV_MAJOR;
 496                 break;
 497         case AR_RAD5133_SREV_MAJOR:
 498         case AR_RAD5122_SREV_MAJOR:
 499         case AR_RAD2133_SREV_MAJOR:
 500         case AR_RAD2122_SREV_MAJOR:
 501                 break;
 502         default:
 503                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 504                         "Radio Chip Rev 0x%02X not supported\n",
 505                         val & AR_RADIO_SREV_MAJOR);
 506                 return -EOPNOTSUPP;
 507         }
 508
 509         ah->hw_version.analog5GhzRev = val;
 510
 511         return 0;
 512 }
 513
 514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 515 {
 516         u32 sum;
 517         int i;
 518         u16 eeval;
 519
 520         sum = 0;
 521         for (i = 0; i < 3; i++) {
 522                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 523                 sum += eeval;
 524                 ah->macaddr[2 * i] = eeval >> 8;
 525                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 526         }
 527         if (sum == 0 || sum == 0xffff * 3)
 528                 return -EADDRNOTAVAIL;
 529
 530         return 0;
 531 }
 532
 533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 534 {
 535         u32 rxgain_type;
 536
 537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 538                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 539
 540                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 541                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 542                         ar9280Modes_backoff_13db_rxgain_9280_2,
 543                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 544                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 545                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 546                         ar9280Modes_backoff_23db_rxgain_9280_2,
 547                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 548                 else
 549                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 550                         ar9280Modes_original_rxgain_9280_2,
 551                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 552         } else {
 553                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 554                         ar9280Modes_original_rxgain_9280_2,
 555                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 556         }
 557 }
 558
 559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 560 {
 561         u32 txgain_type;
 562
 563         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 564                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 565
 566                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 567                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 568                         ar9280Modes_high_power_tx_gain_9280_2,
 569                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 570                 else
 571                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                         ar9280Modes_original_tx_gain_9280_2,
 573                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 574         } else {
 575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 576                 ar9280Modes_original_tx_gain_9280_2,
 577                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 578         }
 579 }
 580
 581 static int ath9k_hw_post_attach(struct ath_hw *ah)
 582 {
 583         int ecode;
 584
 585         if (!ath9k_hw_chip_test(ah))
 586                 return -ENODEV;
 587
 588         ecode = ath9k_hw_rf_claim(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591
 592         ecode = ath9k_hw_eeprom_attach(ah);
 593         if (ecode != 0)
 594                 return ecode;
 595
 596         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 597                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 598
 599         ecode = ath9k_hw_rfattach(ah);
 600         if (ecode != 0)
 601                 return ecode;
 602
 603         if (!AR_SREV_9100(ah)) {
 604                 ath9k_hw_ani_setup(ah);
 605                 ath9k_hw_ani_attach(ah);
 606         }
 607
 608         return 0;
 609 }
 610
 611 static bool ath9k_hw_devid_supported(u16 devid)
 612 {
 613         switch (devid) {
 614         case AR5416_DEVID_PCI:
 615         case AR5416_DEVID_PCIE:
 616         case AR5416_AR9100_DEVID:
 617         case AR9160_DEVID_PCI:
 618         case AR9280_DEVID_PCI:
 619         case AR9280_DEVID_PCIE:
 620         case AR9285_DEVID_PCIE:
 621         case AR5416_DEVID_AR9287_PCI:
 622         case AR5416_DEVID_AR9287_PCIE:
 623                 return true;
 624         default:
 625                 break;
 626         }
 627         return false;
 628 }
 629
 630 static bool ath9k_hw_macversion_supported(u32 macversion)
 631 {
 632         switch (macversion) {
 633         case AR_SREV_VERSION_5416_PCI:
 634         case AR_SREV_VERSION_5416_PCIE:
 635         case AR_SREV_VERSION_9160:
 636         case AR_SREV_VERSION_9100:
 637         case AR_SREV_VERSION_9280:
 638         case AR_SREV_VERSION_9285:
 639         case AR_SREV_VERSION_9287:
 640                 return true;
 641         default:
 642                 break;
 643         }
 644         return false;
 645 }
 646
 647 int ath9k_hw_attach(struct ath_hw *ah)
 648 {
 649         int r;
 650         u32 i, j;
 651
 652         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 653                 r = -EOPNOTSUPP;
 654                 goto bad;
 655         }
 656
 657         ath9k_hw_newstate(ah);
 658         ath9k_hw_set_defaults(ah);
 659
 660         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 661                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 662                 r = -EIO;
 663                 goto bad;
 664         }
 665
 666         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 667                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 668                 r = -EIO;
 669                 goto bad;
 670         }
 671
 672         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 673                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 674                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 675                         ah->config.serialize_regmode =
 676                                 SER_REG_MODE_ON;
 677                 } else {
 678                         ah->config.serialize_regmode =
 679                                 SER_REG_MODE_OFF;
 680                 }
 681         }
 682
 683         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 684                 ah->config.serialize_regmode);
 685
 686         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 687                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 688                         "Mac Chip Rev 0x%02x.%x is not supported by "
 689                         "this driver\n", ah->hw_version.macVersion,
 690                         ah->hw_version.macRev);
 691                 r = -EOPNOTSUPP;
 692                 goto bad;
 693         }
 694
 695         if (AR_SREV_9100(ah)) {
 696                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 697                 ah->supp_cals = IQ_MISMATCH_CAL;
 698                 ah->is_pciexpress = false;
 699         }
 700         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 701
 702         if (AR_SREV_9160_10_OR_LATER(ah)) {
 703                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 704                         ah->iq_caldata.calData = &iq_cal_single_sample;
 705                         ah->adcgain_caldata.calData =
 706                                 &adc_gain_cal_single_sample;
 707                         ah->adcdc_caldata.calData =
 708                                 &adc_dc_cal_single_sample;
 709                         ah->adcdc_calinitdata.calData =
 710                                 &adc_init_dc_cal;
 711                 } else {
 712                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 713                         ah->adcgain_caldata.calData =
 714                                 &adc_gain_cal_multi_sample;
 715                         ah->adcdc_caldata.calData =
 716                                 &adc_dc_cal_multi_sample;
 717                         ah->adcdc_calinitdata.calData =
 718                                 &adc_init_dc_cal;
 719                 }
 720                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 721         }
 722
 723         ah->ani_function = ATH9K_ANI_ALL;
 724         if (AR_SREV_9280_10_OR_LATER(ah))
 725                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 726         if (AR_SREV_9287_11_OR_LATER(ah)) {
 727                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 728                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 729                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 730                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 731                 if (ah->config.pcie_clock_req)
 732                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 733                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 734                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 735                 else
 736                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 737                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 738                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 739                                         2);
 740         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 741                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 742                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 743                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 744                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 745
 746                 if (ah->config.pcie_clock_req)
 747                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 748                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 749                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 750                 else
 751                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 752                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 753                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 754                                   2);
 755         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 756
 757
 758                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 759                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 760                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 761                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 762
 763                 if (ah->config.pcie_clock_req) {
 764                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 765                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 766                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 767                 } else {
 768                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 769                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 770                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 771                                   2);
 772                 }
 773         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 774                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 775                                ARRAY_SIZE(ar9285Modes_9285), 6);
 776                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 777                                ARRAY_SIZE(ar9285Common_9285), 2);
 778
 779                 if (ah->config.pcie_clock_req) {
 780                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 781                         ar9285PciePhy_clkreq_off_L1_9285,
 782                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 783                 } else {
 784                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 785                         ar9285PciePhy_clkreq_always_on_L1_9285,
 786                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 787                 }
 788         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 789                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 790                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 791                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 792                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 793
 794                 if (ah->config.pcie_clock_req) {
 795                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 796                                ar9280PciePhy_clkreq_off_L1_9280,
 797                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 798                 } else {
 799                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 800                                ar9280PciePhy_clkreq_always_on_L1_9280,
 801                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 802                 }
 803                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 804                                ar9280Modes_fast_clock_9280_2,
 805                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 806         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 807                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 808                                ARRAY_SIZE(ar9280Modes_9280), 6);
 809                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 810                                ARRAY_SIZE(ar9280Common_9280), 2);
 811         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 812                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 813                                ARRAY_SIZE(ar5416Modes_9160), 6);
 814                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 815                                ARRAY_SIZE(ar5416Common_9160), 2);
 816                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 817                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 818                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 819                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 820                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 821                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 822                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 823                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 824                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 825                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 826                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 827                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 828                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 829                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 830                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 831                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 832                 if (AR_SREV_9160_11(ah)) {
 833                         INIT_INI_ARRAY(&ah->iniAddac,
 834                                        ar5416Addac_91601_1,
 835                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 836                 } else {
 837                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 838                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 839                 }
 840         } else if (AR_SREV_9100_OR_LATER(ah)) {
 841                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 842                                ARRAY_SIZE(ar5416Modes_9100), 6);
 843                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 844                                ARRAY_SIZE(ar5416Common_9100), 2);
 845                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 846                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 847                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 848                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 849                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 850                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 851                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 852                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 853                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 854                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 855                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 856                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 857                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 858                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 859                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 860                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 861                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 862                                ARRAY_SIZE(ar5416Addac_9100), 2);
 863         } else {
 864                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 865                                ARRAY_SIZE(ar5416Modes), 6);
 866                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 867                                ARRAY_SIZE(ar5416Common), 2);
 868                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 869                                ARRAY_SIZE(ar5416Bank0), 2);
 870                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 871                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 872                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 873                                ARRAY_SIZE(ar5416Bank1), 2);
 874                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 875                                ARRAY_SIZE(ar5416Bank2), 2);
 876                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 877                                ARRAY_SIZE(ar5416Bank3), 3);
 878                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 879                                ARRAY_SIZE(ar5416Bank6), 3);
 880                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 881                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 882                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 883                                ARRAY_SIZE(ar5416Bank7), 2);
 884                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 885                                ARRAY_SIZE(ar5416Addac), 2);
 886         }
 887
 888         if (ah->is_pciexpress)
 889                 ath9k_hw_configpcipowersave(ah, 0);
 890         else
 891                 ath9k_hw_disablepcie(ah);
 892
 893         r = ath9k_hw_post_attach(ah);
 894         if (r)
 895                 goto bad;
 896
 897         if (AR_SREV_9287_11(ah))
 898                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 899                 ar9287Modes_rx_gain_9287_1_1,
 900                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 901         else if (AR_SREV_9287_10(ah))
 902                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 903                 ar9287Modes_rx_gain_9287_1_0,
 904                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 905         else if (AR_SREV_9280_20(ah))
 906                 ath9k_hw_init_rxgain_ini(ah);
 907
 908         if (AR_SREV_9287_11(ah)) {
 909                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 910                 ar9287Modes_tx_gain_9287_1_1,
 911                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 912         } else if (AR_SREV_9287_10(ah)) {
 913                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 914                 ar9287Modes_tx_gain_9287_1_0,
 915                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 916         } else if (AR_SREV_9280_20(ah)) {
 917                 ath9k_hw_init_txgain_ini(ah);
 918         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 919                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 920
 921                 /* txgain table */
 922                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 923                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 924                         ar9285Modes_high_power_tx_gain_9285_1_2,
 925                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 926                 } else {
 927                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 928                         ar9285Modes_original_tx_gain_9285_1_2,
 929                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 930                 }
 931
 932         }
 933
 934         ath9k_hw_fill_cap_info(ah);
 935
 936         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 937             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 938
 939                 /* EEPROM Fixup */
 940                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 941                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 942
 943                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 944                                 u32 val = INI_RA(&ah->iniModes, i, j);
 945
 946                                 INI_RA(&ah->iniModes, i, j) =
 947                                         ath9k_hw_ini_fixup(ah,
 948                                                            &ah->eeprom.def,
 949                                                            reg, val);
 950                         }
 951                 }
 952         }
 953
 954         r = ath9k_hw_init_macaddr(ah);
 955         if (r) {
 956                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 957                         "Failed to initialize MAC address\n");
 958                 goto bad;
 959         }
 960
 961         if (AR_SREV_9285(ah))
 962                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 963         else
 964                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 965
 966         ath9k_init_nfcal_hist_buffer(ah);
 967
 968         return 0;
 969 bad:
 970         ath9k_hw_detach(ah);
 971         return r;
 972 }
 973
 974 static void ath9k_hw_init_bb(struct ath_hw *ah,
 975                              struct ath9k_channel *chan)
 976 {
 977         u32 synthDelay;
 978
 979         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 980         if (IS_CHAN_B(chan))
 981                 synthDelay = (4 * synthDelay) / 22;
 982         else
 983                 synthDelay /= 10;
 984
 985         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 986
 987         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 988 }
 989
 990 static void ath9k_hw_init_qos(struct ath_hw *ah)
 991 {
 992         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 993         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 994
 995         REG_WRITE(ah, AR_QOS_NO_ACK,
 996                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 997                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 998                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 999
1000         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1001         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1002         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1003         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1004         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1005 }
1006
1007 static void ath9k_hw_init_pll(struct ath_hw *ah,
1008                               struct ath9k_channel *chan)
1009 {
1010         u32 pll;
1011
1012         if (AR_SREV_9100(ah)) {
1013                 if (chan && IS_CHAN_5GHZ(chan))
1014                         pll = 0x1450;
1015                 else
1016                         pll = 0x1458;
1017         } else {
1018                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1019                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1020
1021                         if (chan && IS_CHAN_HALF_RATE(chan))
1022                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1023                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1024                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1025
1026                         if (chan && IS_CHAN_5GHZ(chan)) {
1027                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1028
1029
1030                                 if (AR_SREV_9280_20(ah)) {
1031                                         if (((chan->channel % 20) == 0)
1032                                             || ((chan->channel % 10) == 0))
1033                                                 pll = 0x2850;
1034                                         else
1035                                                 pll = 0x142c;
1036                                 }
1037                         } else {
1038                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1039                         }
1040
1041                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1042
1043                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1044
1045                         if (chan && IS_CHAN_HALF_RATE(chan))
1046                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1047                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1048                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1049
1050                         if (chan && IS_CHAN_5GHZ(chan))
1051                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1052                         else
1053                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1054                 } else {
1055                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1056
1057                         if (chan && IS_CHAN_HALF_RATE(chan))
1058                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1059                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1060                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1061
1062                         if (chan && IS_CHAN_5GHZ(chan))
1063                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1064                         else
1065                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1066                 }
1067         }
1068         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1069
1070         udelay(RTC_PLL_SETTLE_DELAY);
1071
1072         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1073 }
1074
1075 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1076 {
1077         int rx_chainmask, tx_chainmask;
1078
1079         rx_chainmask = ah->rxchainmask;
1080         tx_chainmask = ah->txchainmask;
1081
1082         switch (rx_chainmask) {
1083         case 0x5:
1084                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1085                             AR_PHY_SWAP_ALT_CHAIN);
1086         case 0x3:
1087                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1088                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1089                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1090                         break;
1091                 }
1092         case 0x1:
1093         case 0x2:
1094         case 0x7:
1095                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1096                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1097                 break;
1098         default:
1099                 break;
1100         }
1101
1102         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1103         if (tx_chainmask == 0x5) {
1104                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1105                             AR_PHY_SWAP_ALT_CHAIN);
1106         }
1107         if (AR_SREV_9100(ah))
1108                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1109                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1110 }
1111
1112 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1113                                           enum nl80211_iftype opmode)
1114 {
1115         ah->mask_reg = AR_IMR_TXERR |
1116                 AR_IMR_TXURN |
1117                 AR_IMR_RXERR |
1118                 AR_IMR_RXORN |
1119                 AR_IMR_BCNMISC;
1120
1121         if (ah->config.intr_mitigation)
1122                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1123         else
1124                 ah->mask_reg |= AR_IMR_RXOK;
1125
1126         ah->mask_reg |= AR_IMR_TXOK;
1127
1128         if (opmode == NL80211_IFTYPE_AP)
1129                 ah->mask_reg |= AR_IMR_MIB;
1130
1131         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1132         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1133
1134         if (!AR_SREV_9100(ah)) {
1135                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1136                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1137                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1138         }
1139 }
1140
1141 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1142 {
1143         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1144                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1145                 ah->acktimeout = (u32) -1;
1146                 return false;
1147         } else {
1148                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1149                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1150                 ah->acktimeout = us;
1151                 return true;
1152         }
1153 }
1154
1155 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1156 {
1157         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1158                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1159                 ah->ctstimeout = (u32) -1;
1160                 return false;
1161         } else {
1162                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1163                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1164                 ah->ctstimeout = us;
1165                 return true;
1166         }
1167 }
1168
1169 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1170 {
1171         if (tu > 0xFFFF) {
1172                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1173                         "bad global tx timeout %u\n", tu);
1174                 ah->globaltxtimeout = (u32) -1;
1175                 return false;
1176         } else {
1177                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1178                 ah->globaltxtimeout = tu;
1179                 return true;
1180         }
1181 }
1182
1183 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1184 {
1185         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1186                 ah->misc_mode);
1187
1188         if (ah->misc_mode != 0)
1189                 REG_WRITE(ah, AR_PCU_MISC,
1190                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1191         if (ah->slottime != (u32) -1)
1192                 ath9k_hw_setslottime(ah, ah->slottime);
1193         if (ah->acktimeout != (u32) -1)
1194                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1195         if (ah->ctstimeout != (u32) -1)
1196                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1197         if (ah->globaltxtimeout != (u32) -1)
1198                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1199 }
1200
1201 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1202 {
1203         return vendorid == ATHEROS_VENDOR_ID ?
1204                 ath9k_hw_devname(devid) : NULL;
1205 }
1206
1207 void ath9k_hw_detach(struct ath_hw *ah)
1208 {
1209         if (!AR_SREV_9100(ah))
1210                 ath9k_hw_ani_detach(ah);
1211
1212         ath9k_hw_rfdetach(ah);
1213         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1214         kfree(ah);
1215 }
1216
1217 /*******/
1218 /* INI */
1219 /*******/
1220
1221 static void ath9k_hw_override_ini(struct ath_hw *ah,
1222                                   struct ath9k_channel *chan)
1223 {
1224         /*
1225          * Set the RX_ABORT and RX_DIS and clear if off only after
1226          * RXE is set for MAC. This prevents frames with corrupted
1227          * descriptor status.
1228          */
1229         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1230
1231
1232         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1233             AR_SREV_9280_10_OR_LATER(ah))
1234                 return;
1235
1236         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1237 }
1238
1239 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1240                               struct ar5416_eeprom_def *pEepData,
1241                               u32 reg, u32 value)
1242 {
1243         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1244
1245         switch (ah->hw_version.devid) {
1246         case AR9280_DEVID_PCI:
1247                 if (reg == 0x7894) {
1248                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1249                                 "ini VAL: %x  EEPROM: %x\n", value,
1250                                 (pBase->version & 0xff));
1251
1252                         if ((pBase->version & 0xff) > 0x0a) {
1253                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1254                                         "PWDCLKIND: %d\n",
1255                                         pBase->pwdclkind);
1256                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1257                                 value |= AR_AN_TOP2_PWDCLKIND &
1258                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1259                         } else {
1260                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1261                                         "PWDCLKIND Earlier Rev\n");
1262                         }
1263
1264                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1265                                 "final ini VAL: %x\n", value);
1266                 }
1267                 break;
1268         }
1269
1270         return value;
1271 }
1272
1273 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1274                               struct ar5416_eeprom_def *pEepData,
1275                               u32 reg, u32 value)
1276 {
1277         if (ah->eep_map == EEP_MAP_4KBITS)
1278                 return value;
1279         else
1280                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1281 }
1282
1283 static void ath9k_olc_init(struct ath_hw *ah)
1284 {
1285         u32 i;
1286
1287         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1288                 ah->originalGain[i] =
1289                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1290                                         AR_PHY_TX_GAIN);
1291         ah->PDADCdelta = 0;
1292 }
1293
1294 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1295                               struct ath9k_channel *chan)
1296 {
1297         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1298
1299         if (IS_CHAN_B(chan))
1300                 ctl |= CTL_11B;
1301         else if (IS_CHAN_G(chan))
1302                 ctl |= CTL_11G;
1303         else
1304                 ctl |= CTL_11A;
1305
1306         return ctl;
1307 }
1308
1309 static int ath9k_hw_process_ini(struct ath_hw *ah,
1310                                 struct ath9k_channel *chan,
1311                                 enum ath9k_ht_macmode macmode)
1312 {
1313         int i, regWrites = 0;
1314         struct ieee80211_channel *channel = chan->chan;
1315         u32 modesIndex, freqIndex;
1316
1317         switch (chan->chanmode) {
1318         case CHANNEL_A:
1319         case CHANNEL_A_HT20:
1320                 modesIndex = 1;
1321                 freqIndex = 1;
1322                 break;
1323         case CHANNEL_A_HT40PLUS:
1324         case CHANNEL_A_HT40MINUS:
1325                 modesIndex = 2;
1326                 freqIndex = 1;
1327                 break;
1328         case CHANNEL_G:
1329         case CHANNEL_G_HT20:
1330         case CHANNEL_B:
1331                 modesIndex = 4;
1332                 freqIndex = 2;
1333                 break;
1334         case CHANNEL_G_HT40PLUS:
1335         case CHANNEL_G_HT40MINUS:
1336                 modesIndex = 3;
1337                 freqIndex = 2;
1338                 break;
1339
1340         default:
1341                 return -EINVAL;
1342         }
1343
1344         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1345         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1346         ah->eep_ops->set_addac(ah, chan);
1347
1348         if (AR_SREV_5416_22_OR_LATER(ah)) {
1349                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1350         } else {
1351                 struct ar5416IniArray temp;
1352                 u32 addacSize =
1353                         sizeof(u32) * ah->iniAddac.ia_rows *
1354                         ah->iniAddac.ia_columns;
1355
1356                 memcpy(ah->addac5416_21,
1357                        ah->iniAddac.ia_array, addacSize);
1358
1359                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1360
1361                 temp.ia_array = ah->addac5416_21;
1362                 temp.ia_columns = ah->iniAddac.ia_columns;
1363                 temp.ia_rows = ah->iniAddac.ia_rows;
1364                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1365         }
1366
1367         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1368
1369         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1370                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1371                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1372
1373                 REG_WRITE(ah, reg, val);
1374
1375                 if (reg >= 0x7800 && reg < 0x78a0
1376                     && ah->config.analog_shiftreg) {
1377                         udelay(100);
1378                 }
1379
1380                 DO_DELAY(regWrites);
1381         }
1382
1383         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1384                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1385
1386         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1387             AR_SREV_9287_10_OR_LATER(ah))
1388                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1389
1390         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1391                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1392                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1393
1394                 REG_WRITE(ah, reg, val);
1395
1396                 if (reg >= 0x7800 && reg < 0x78a0
1397                     && ah->config.analog_shiftreg) {
1398                         udelay(100);
1399                 }
1400
1401                 DO_DELAY(regWrites);
1402         }
1403
1404         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1405
1406         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1407                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1408                                 regWrites);
1409         }
1410
1411         ath9k_hw_override_ini(ah, chan);
1412         ath9k_hw_set_regs(ah, chan, macmode);
1413         ath9k_hw_init_chain_masks(ah);
1414
1415         if (OLC_FOR_AR9280_20_LATER)
1416                 ath9k_olc_init(ah);
1417
1418         ah->eep_ops->set_txpower(ah, chan,
1419                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1420                                  channel->max_antenna_gain * 2,
1421                                  channel->max_power * 2,
1422                                  min((u32) MAX_RATE_POWER,
1423                                  (u32) ah->regulatory.power_limit));
1424
1425         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1426                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1427                         "ar5416SetRfRegs failed\n");
1428                 return -EIO;
1429         }
1430
1431         return 0;
1432 }
1433
1434 /****************************************/
1435 /* Reset and Channel Switching Routines */
1436 /****************************************/
1437
1438 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1439 {
1440         u32 rfMode = 0;
1441
1442         if (chan == NULL)
1443                 return;
1444
1445         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1446                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1447
1448         if (!AR_SREV_9280_10_OR_LATER(ah))
1449                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1450                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1451
1452         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1453                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1454
1455         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1456 }
1457
1458 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1459 {
1460         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1461 }
1462
1463 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1464 {
1465         u32 regval;
1466
1467         regval = REG_READ(ah, AR_AHB_MODE);
1468         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1469
1470         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1471         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1472
1473         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1474
1475         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1476         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1477
1478         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1479
1480         if (AR_SREV_9285(ah)) {
1481                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1482                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1483         } else {
1484                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1485                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1486         }
1487 }
1488
1489 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1490 {
1491         u32 val;
1492
1493         val = REG_READ(ah, AR_STA_ID1);
1494         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1495         switch (opmode) {
1496         case NL80211_IFTYPE_AP:
1497                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1498                           | AR_STA_ID1_KSRCH_MODE);
1499                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1500                 break;
1501         case NL80211_IFTYPE_ADHOC:
1502         case NL80211_IFTYPE_MESH_POINT:
1503                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1504                           | AR_STA_ID1_KSRCH_MODE);
1505                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1506                 break;
1507         case NL80211_IFTYPE_STATION:
1508         case NL80211_IFTYPE_MONITOR:
1509                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1510                 break;
1511         }
1512 }
1513
1514 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1515                                                  u32 coef_scaled,
1516                                                  u32 *coef_mantissa,
1517                                                  u32 *coef_exponent)
1518 {
1519         u32 coef_exp, coef_man;
1520
1521         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1522                 if ((coef_scaled >> coef_exp) & 0x1)
1523                         break;
1524
1525         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1526
1527         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1528
1529         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1530         *coef_exponent = coef_exp - 16;
1531 }
1532
1533 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1534                                      struct ath9k_channel *chan)
1535 {
1536         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1537         u32 clockMhzScaled = 0x64000000;
1538         struct chan_centers centers;
1539
1540         if (IS_CHAN_HALF_RATE(chan))
1541                 clockMhzScaled = clockMhzScaled >> 1;
1542         else if (IS_CHAN_QUARTER_RATE(chan))
1543                 clockMhzScaled = clockMhzScaled >> 2;
1544
1545         ath9k_hw_get_channel_centers(ah, chan, &centers);
1546         coef_scaled = clockMhzScaled / centers.synth_center;
1547
1548         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1549                                       &ds_coef_exp);
1550
1551         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1552                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1553         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1554                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1555
1556         coef_scaled = (9 * coef_scaled) / 10;
1557
1558         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1559                                       &ds_coef_exp);
1560
1561         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1562                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1563         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1564                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1565 }
1566
1567 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1568 {
1569         u32 rst_flags;
1570         u32 tmpReg;
1571
1572         if (AR_SREV_9100(ah)) {
1573                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1574                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1575                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1576                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1577                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1578         }
1579
1580         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1581                   AR_RTC_FORCE_WAKE_ON_INT);
1582
1583         if (AR_SREV_9100(ah)) {
1584                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1585                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1586         } else {
1587                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1588                 if (tmpReg &
1589                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1590                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1591                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1592                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1593                 } else {
1594                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1595                 }
1596
1597                 rst_flags = AR_RTC_RC_MAC_WARM;
1598                 if (type == ATH9K_RESET_COLD)
1599                         rst_flags |= AR_RTC_RC_MAC_COLD;
1600         }
1601
1602         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1603         udelay(50);
1604
1605         REG_WRITE(ah, AR_RTC_RC, 0);
1606         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1607                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1608                         "RTC stuck in MAC reset\n");
1609                 return false;
1610         }
1611
1612         if (!AR_SREV_9100(ah))
1613                 REG_WRITE(ah, AR_RC, 0);
1614
1615         ath9k_hw_init_pll(ah, NULL);
1616
1617         if (AR_SREV_9100(ah))
1618                 udelay(50);
1619
1620         return true;
1621 }
1622
1623 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1624 {
1625         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1626                   AR_RTC_FORCE_WAKE_ON_INT);
1627
1628         REG_WRITE(ah, AR_RTC_RESET, 0);
1629         udelay(2);
1630         REG_WRITE(ah, AR_RTC_RESET, 1);
1631
1632         if (!ath9k_hw_wait(ah,
1633                            AR_RTC_STATUS,
1634                            AR_RTC_STATUS_M,
1635                            AR_RTC_STATUS_ON,
1636                            AH_WAIT_TIMEOUT)) {
1637                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1638                 return false;
1639         }
1640
1641         ath9k_hw_read_revisions(ah);
1642
1643         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1644 }
1645
1646 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1647 {
1648         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1649                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1650
1651         switch (type) {
1652         case ATH9K_RESET_POWER_ON:
1653                 return ath9k_hw_set_reset_power_on(ah);
1654         case ATH9K_RESET_WARM:
1655         case ATH9K_RESET_COLD:
1656                 return ath9k_hw_set_reset(ah, type);
1657         default:
1658                 return false;
1659         }
1660 }
1661
1662 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1663                               enum ath9k_ht_macmode macmode)
1664 {
1665         u32 phymode;
1666         u32 enableDacFifo = 0;
1667
1668         if (AR_SREV_9285_10_OR_LATER(ah))
1669                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1670                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1671
1672         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1673                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1674
1675         if (IS_CHAN_HT40(chan)) {
1676                 phymode |= AR_PHY_FC_DYN2040_EN;
1677
1678                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1679                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1680                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1681
1682                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1683                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1684         }
1685         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1686
1687         ath9k_hw_set11nmac2040(ah, macmode);
1688
1689         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1690         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1691 }
1692
1693 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1694                                 struct ath9k_channel *chan)
1695 {
1696         if (OLC_FOR_AR9280_20_LATER) {
1697                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1698                         return false;
1699         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1700                 return false;
1701
1702         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1703                 return false;
1704
1705         ah->chip_fullsleep = false;
1706         ath9k_hw_init_pll(ah, chan);
1707         ath9k_hw_set_rfmode(ah, chan);
1708
1709         return true;
1710 }
1711
1712 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1713                                     struct ath9k_channel *chan,
1714                                     enum ath9k_ht_macmode macmode)
1715 {
1716         struct ieee80211_channel *channel = chan->chan;
1717         u32 synthDelay, qnum;
1718
1719         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1720                 if (ath9k_hw_numtxpending(ah, qnum)) {
1721                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1722                                 "Transmit frames pending on queue %d\n", qnum);
1723                         return false;
1724                 }
1725         }
1726
1727         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1728         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1729                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1730                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1731                         "Could not kill baseband RX\n");
1732                 return false;
1733         }
1734
1735         ath9k_hw_set_regs(ah, chan, macmode);
1736
1737         if (AR_SREV_9280_10_OR_LATER(ah)) {
1738                 ath9k_hw_ar9280_set_channel(ah, chan);
1739         } else {
1740                 if (!(ath9k_hw_set_channel(ah, chan))) {
1741                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1742                                 "Failed to set channel\n");
1743                         return false;
1744                 }
1745         }
1746
1747         ah->eep_ops->set_txpower(ah, chan,
1748                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1749                              channel->max_antenna_gain * 2,
1750                              channel->max_power * 2,
1751                              min((u32) MAX_RATE_POWER,
1752                              (u32) ah->regulatory.power_limit));
1753
1754         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1755         if (IS_CHAN_B(chan))
1756                 synthDelay = (4 * synthDelay) / 22;
1757         else
1758                 synthDelay /= 10;
1759
1760         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1761
1762         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1763
1764         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1765                 ath9k_hw_set_delta_slope(ah, chan);
1766
1767         if (AR_SREV_9280_10_OR_LATER(ah))
1768                 ath9k_hw_9280_spur_mitigate(ah, chan);
1769         else
1770                 ath9k_hw_spur_mitigate(ah, chan);
1771
1772         if (!chan->oneTimeCalsDone)
1773                 chan->oneTimeCalsDone = true;
1774
1775         return true;
1776 }
1777
1778 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1779 {
1780         int bb_spur = AR_NO_SPUR;
1781         int freq;
1782         int bin, cur_bin;
1783         int bb_spur_off, spur_subchannel_sd;
1784         int spur_freq_sd;
1785         int spur_delta_phase;
1786         int denominator;
1787         int upper, lower, cur_vit_mask;
1788         int tmp, newVal;
1789         int i;
1790         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1791                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1792         };
1793         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1794                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1795         };
1796         int inc[4] = { 0, 100, 0, 0 };
1797         struct chan_centers centers;
1798
1799         int8_t mask_m[123];
1800         int8_t mask_p[123];
1801         int8_t mask_amt;
1802         int tmp_mask;
1803         int cur_bb_spur;
1804         bool is2GHz = IS_CHAN_2GHZ(chan);
1805
1806         memset(&mask_m, 0, sizeof(int8_t) * 123);
1807         memset(&mask_p, 0, sizeof(int8_t) * 123);
1808
1809         ath9k_hw_get_channel_centers(ah, chan, &centers);
1810         freq = centers.synth_center;
1811
1812         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1813         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1814                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1815
1816                 if (is2GHz)
1817                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1818                 else
1819                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1820
1821                 if (AR_NO_SPUR == cur_bb_spur)
1822                         break;
1823                 cur_bb_spur = cur_bb_spur - freq;
1824
1825                 if (IS_CHAN_HT40(chan)) {
1826                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1827                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1828                                 bb_spur = cur_bb_spur;
1829                                 break;
1830                         }
1831                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1832                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1833                         bb_spur = cur_bb_spur;
1834                         break;
1835                 }
1836         }
1837
1838         if (AR_NO_SPUR == bb_spur) {
1839                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1840                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1841                 return;
1842         } else {
1843                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1844                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1845         }
1846
1847         bin = bb_spur * 320;
1848
1849         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1850
1851         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1852                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1853                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1854                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1855         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1856
1857         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1858                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1859                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1860                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1861                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1862         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1863
1864         if (IS_CHAN_HT40(chan)) {
1865                 if (bb_spur < 0) {
1866                         spur_subchannel_sd = 1;
1867                         bb_spur_off = bb_spur + 10;
1868                 } else {
1869                         spur_subchannel_sd = 0;
1870                         bb_spur_off = bb_spur - 10;
1871                 }
1872         } else {
1873                 spur_subchannel_sd = 0;
1874                 bb_spur_off = bb_spur;
1875         }
1876
1877         if (IS_CHAN_HT40(chan))
1878                 spur_delta_phase =
1879                         ((bb_spur * 262144) /
1880                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1881         else
1882                 spur_delta_phase =
1883                         ((bb_spur * 524288) /
1884                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1885
1886         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1887         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1888
1889         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1890                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1891                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1892         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1893
1894         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1895         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1896
1897         cur_bin = -6000;
1898         upper = bin + 100;
1899         lower = bin - 100;
1900
1901         for (i = 0; i < 4; i++) {
1902                 int pilot_mask = 0;
1903                 int chan_mask = 0;
1904                 int bp = 0;
1905                 for (bp = 0; bp < 30; bp++) {
1906                         if ((cur_bin > lower) && (cur_bin < upper)) {
1907                                 pilot_mask = pilot_mask | 0x1 << bp;
1908                                 chan_mask = chan_mask | 0x1 << bp;
1909                         }
1910                         cur_bin += 100;
1911                 }
1912                 cur_bin += inc[i];
1913                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1914                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1915         }
1916
1917         cur_vit_mask = 6100;
1918         upper = bin + 120;
1919         lower = bin - 120;
1920
1921         for (i = 0; i < 123; i++) {
1922                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1923
1924                         /* workaround for gcc bug #37014 */
1925                         volatile int tmp_v = abs(cur_vit_mask - bin);
1926
1927                         if (tmp_v < 75)
1928                                 mask_amt = 1;
1929                         else
1930                                 mask_amt = 0;
1931                         if (cur_vit_mask < 0)
1932                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1933                         else
1934                                 mask_p[cur_vit_mask / 100] = mask_amt;
1935                 }
1936                 cur_vit_mask -= 100;
1937         }
1938
1939         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1940                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1941                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1942                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1943                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1944                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1945                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1946                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1947         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1948         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1949
1950         tmp_mask = (mask_m[31] << 28)
1951                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1952                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1953                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1954                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1955                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1956                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1957                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1958         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1959         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1960
1961         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1962                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1963                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1964                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1965                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1966                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1967                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1968                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1969         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1970         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1971
1972         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1973                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1974                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1975                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1976                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1977                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1978                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1979                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1980         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1981         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1982
1983         tmp_mask = (mask_p[15] << 28)
1984                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1985                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1986                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1987                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1988                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1989                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1990                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1991         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1992         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1993
1994         tmp_mask = (mask_p[30] << 28)
1995                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1996                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1997                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1998                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1999                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2000                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2001                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2002         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2003         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2004
2005         tmp_mask = (mask_p[45] << 28)
2006                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2007                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2008                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2009                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2010                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2011                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2012                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2013         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2014         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2015
2016         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2017                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2018                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2019                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2020                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2021                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2022                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2023                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2024         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2025         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2026 }
2027
2028 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2029 {
2030         int bb_spur = AR_NO_SPUR;
2031         int bin, cur_bin;
2032         int spur_freq_sd;
2033         int spur_delta_phase;
2034         int denominator;
2035         int upper, lower, cur_vit_mask;
2036         int tmp, new;
2037         int i;
2038         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2039                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2040         };
2041         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2042                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2043         };
2044         int inc[4] = { 0, 100, 0, 0 };
2045
2046         int8_t mask_m[123];
2047         int8_t mask_p[123];
2048         int8_t mask_amt;
2049         int tmp_mask;
2050         int cur_bb_spur;
2051         bool is2GHz = IS_CHAN_2GHZ(chan);
2052
2053         memset(&mask_m, 0, sizeof(int8_t) * 123);
2054         memset(&mask_p, 0, sizeof(int8_t) * 123);
2055
2056         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2057                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2058                 if (AR_NO_SPUR == cur_bb_spur)
2059                         break;
2060                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2061                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2062                         bb_spur = cur_bb_spur;
2063                         break;
2064                 }
2065         }
2066
2067         if (AR_NO_SPUR == bb_spur)
2068                 return;
2069
2070         bin = bb_spur * 32;
2071
2072         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2073         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2074                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2075                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2076                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2077
2078         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2079
2080         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2081                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2082                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2083                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2084                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2085         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2086
2087         spur_delta_phase = ((bb_spur * 524288) / 100) &
2088                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2089
2090         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2091         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2092
2093         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2094                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2095                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2096         REG_WRITE(ah, AR_PHY_TIMING11, new);
2097
2098         cur_bin = -6000;
2099         upper = bin + 100;
2100         lower = bin - 100;
2101
2102         for (i = 0; i < 4; i++) {
2103                 int pilot_mask = 0;
2104                 int chan_mask = 0;
2105                 int bp = 0;
2106                 for (bp = 0; bp < 30; bp++) {
2107                         if ((cur_bin > lower) && (cur_bin < upper)) {
2108                                 pilot_mask = pilot_mask | 0x1 << bp;
2109                                 chan_mask = chan_mask | 0x1 << bp;
2110                         }
2111                         cur_bin += 100;
2112                 }
2113                 cur_bin += inc[i];
2114                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2115                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2116         }
2117
2118         cur_vit_mask = 6100;
2119         upper = bin + 120;
2120         lower = bin - 120;
2121
2122         for (i = 0; i < 123; i++) {
2123                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2124
2125                         /* workaround for gcc bug #37014 */
2126                         volatile int tmp_v = abs(cur_vit_mask - bin);
2127
2128                         if (tmp_v < 75)
2129                                 mask_amt = 1;
2130                         else
2131                                 mask_amt = 0;
2132                         if (cur_vit_mask < 0)
2133                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2134                         else
2135                                 mask_p[cur_vit_mask / 100] = mask_amt;
2136                 }
2137                 cur_vit_mask -= 100;
2138         }
2139
2140         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2141                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2142                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2143                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2144                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2145                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2146                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2147                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2148         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2149         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2150
2151         tmp_mask = (mask_m[31] << 28)
2152                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2153                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2154                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2155                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2156                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2157                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2158                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2159         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2160         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2161
2162         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2163                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2164                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2165                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2166                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2167                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2168                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2169                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2170         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2171         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2172
2173         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2174                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2175                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2176                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2177                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2178                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2179                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2180                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2181         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2182         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2183
2184         tmp_mask = (mask_p[15] << 28)
2185                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2186                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2187                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2188                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2189                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2190                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2191                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2192         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2193         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2194
2195         tmp_mask = (mask_p[30] << 28)
2196                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2197                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2198                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2199                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2200                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2201                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2202                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2203         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2204         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2205
2206         tmp_mask = (mask_p[45] << 28)
2207                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2208                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2209                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2210                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2211                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2212                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2213                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2214         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2215         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2216
2217         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2218                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2219                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2220                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2221                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2222                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2223                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2224                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2225         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2226         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2227 }
2228
2229 static void ath9k_enable_rfkill(struct ath_hw *ah)
2230 {
2231         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2232                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2233
2234         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2235                     AR_GPIO_INPUT_MUX2_RFSILENT);
2236
2237         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2238         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2239 }
2240
2241 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2242                     bool bChannelChange)
2243 {
2244         u32 saveLedState;
2245         struct ath_softc *sc = ah->ah_sc;
2246         struct ath9k_channel *curchan = ah->curchan;
2247         u32 saveDefAntenna;
2248         u32 macStaId1;
2249         int i, rx_chainmask, r;
2250
2251         ah->extprotspacing = sc->ht_extprotspacing;
2252         ah->txchainmask = sc->tx_chainmask;
2253         ah->rxchainmask = sc->rx_chainmask;
2254
2255         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2256                 return -EIO;
2257
2258         if (curchan)
2259                 ath9k_hw_getnf(ah, curchan);
2260
2261         if (bChannelChange &&
2262             (ah->chip_fullsleep != true) &&
2263             (ah->curchan != NULL) &&
2264             (chan->channel != ah->curchan->channel) &&
2265             ((chan->channelFlags & CHANNEL_ALL) ==
2266              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2267             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2268                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2269
2270                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2271                         ath9k_hw_loadnf(ah, ah->curchan);
2272                         ath9k_hw_start_nfcal(ah);
2273                         return 0;
2274                 }
2275         }
2276
2277         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2278         if (saveDefAntenna == 0)
2279                 saveDefAntenna = 1;
2280
2281         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2282
2283         saveLedState = REG_READ(ah, AR_CFG_LED) &
2284                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2285                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2286
2287         ath9k_hw_mark_phy_inactive(ah);
2288
2289         if (!ath9k_hw_chip_reset(ah, chan)) {
2290                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2291                 return -EINVAL;
2292         }
2293
2294         if (AR_SREV_9280_10_OR_LATER(ah))
2295                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2296
2297         if (AR_SREV_9287_10_OR_LATER(ah)) {
2298                 /* Enable ASYNC FIFO */
2299                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2300                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2301                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2302                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2303                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2304                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2305                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2306         }
2307         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2308         if (r)
2309                 return r;
2310
2311         /* Setup MFP options for CCMP */
2312         if (AR_SREV_9280_20_OR_LATER(ah)) {
2313                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2314                  * frames when constructing CCMP AAD. */
2315                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2316                               0xc7ff);
2317                 ah->sw_mgmt_crypto = false;
2318         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2319                 /* Disable hardware crypto for management frames */
2320                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2321                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2322                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2323                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2324                 ah->sw_mgmt_crypto = true;
2325         } else
2326                 ah->sw_mgmt_crypto = true;
2327
2328         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2329                 ath9k_hw_set_delta_slope(ah, chan);
2330
2331         if (AR_SREV_9280_10_OR_LATER(ah))
2332                 ath9k_hw_9280_spur_mitigate(ah, chan);
2333         else
2334                 ath9k_hw_spur_mitigate(ah, chan);
2335
2336         ah->eep_ops->set_board_values(ah, chan);
2337
2338         ath9k_hw_decrease_chain_power(ah, chan);
2339
2340         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2341         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2342                   | macStaId1
2343                   | AR_STA_ID1_RTS_USE_DEF
2344                   | (ah->config.
2345                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2346                   | ah->sta_id1_defaults);
2347         ath9k_hw_set_operating_mode(ah, ah->opmode);
2348
2349         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2350         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2351
2352         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2353
2354         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2355         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2356                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2357
2358         REG_WRITE(ah, AR_ISR, ~0);
2359
2360         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2361
2362         if (AR_SREV_9280_10_OR_LATER(ah))
2363                 ath9k_hw_ar9280_set_channel(ah, chan);
2364         else
2365                 if (!(ath9k_hw_set_channel(ah, chan)))
2366                         return -EIO;
2367
2368         for (i = 0; i < AR_NUM_DCU; i++)
2369                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2370
2371         ah->intr_txqs = 0;
2372         for (i = 0; i < ah->caps.total_queues; i++)
2373                 ath9k_hw_resettxqueue(ah, i);
2374
2375         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2376         ath9k_hw_init_qos(ah);
2377
2378         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2379                 ath9k_enable_rfkill(ah);
2380
2381         ath9k_hw_init_user_settings(ah);
2382
2383         if (AR_SREV_9287_10_OR_LATER(ah)) {
2384                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2385                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2386                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2387                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2388                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2389                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2390
2391                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2392                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2393
2394                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2395                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2396                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2397                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2398         }
2399         if (AR_SREV_9287_10_OR_LATER(ah)) {
2400                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2401                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2402         }
2403
2404         REG_WRITE(ah, AR_STA_ID1,
2405                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2406
2407         ath9k_hw_set_dma(ah);
2408
2409         REG_WRITE(ah, AR_OBS, 8);
2410
2411         if (ah->config.intr_mitigation) {
2412                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2413                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2414         }
2415
2416         ath9k_hw_init_bb(ah, chan);
2417
2418         if (!ath9k_hw_init_cal(ah, chan))
2419                 return -EIO;
2420
2421         rx_chainmask = ah->rxchainmask;
2422         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2423                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2424                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2425         }
2426
2427         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2428
2429         if (AR_SREV_9100(ah)) {
2430                 u32 mask;
2431                 mask = REG_READ(ah, AR_CFG);
2432                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2433                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2434                                 "CFG Byte Swap Set 0x%x\n", mask);
2435                 } else {
2436                         mask =
2437                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2438                         REG_WRITE(ah, AR_CFG, mask);
2439                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2440                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2441                 }
2442         } else {
2443 #ifdef __BIG_ENDIAN
2444                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2445 #endif
2446         }
2447
2448         return 0;
2449 }
2450
2451 /************************/
2452 /* Key Cache Management */
2453 /************************/
2454
2455 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2456 {
2457         u32 keyType;
2458
2459         if (entry >= ah->caps.keycache_size) {
2460                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2461                         "keychache entry %u out of range\n", entry);
2462                 return false;
2463         }
2464
2465         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2466
2467         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2468         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2469         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2470         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2471         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2472         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2473         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2474         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2475
2476         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2477                 u16 micentry = entry + 64;
2478
2479                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2480                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2481                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2482                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2483
2484         }
2485
2486         if (ah->curchan == NULL)
2487                 return true;
2488
2489         return true;
2490 }
2491
2492 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2493 {
2494         u32 macHi, macLo;
2495
2496         if (entry >= ah->caps.keycache_size) {
2497                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2498                         "keychache entry %u out of range\n", entry);
2499                 return false;
2500         }
2501
2502         if (mac != NULL) {
2503                 macHi = (mac[5] << 8) | mac[4];
2504                 macLo = (mac[3] << 24) |
2505                         (mac[2] << 16) |
2506                         (mac[1] << 8) |
2507                         mac[0];
2508                 macLo >>= 1;
2509                 macLo |= (macHi & 1) << 31;
2510                 macHi >>= 1;
2511         } else {
2512                 macLo = macHi = 0;
2513         }
2514         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2515         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2516
2517         return true;
2518 }
2519
2520 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2521                                  const struct ath9k_keyval *k,
2522                                  const u8 *mac)
2523 {
2524         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2525         u32 key0, key1, key2, key3, key4;
2526         u32 keyType;
2527
2528         if (entry >= pCap->keycache_size) {
2529                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2530                         "keycache entry %u out of range\n", entry);
2531                 return false;
2532         }
2533
2534         switch (k->kv_type) {
2535         case ATH9K_CIPHER_AES_OCB:
2536                 keyType = AR_KEYTABLE_TYPE_AES;
2537                 break;
2538         case ATH9K_CIPHER_AES_CCM:
2539                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2540                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2541                                 "AES-CCM not supported by mac rev 0x%x\n",
2542                                 ah->hw_version.macRev);
2543                         return false;
2544                 }
2545                 keyType = AR_KEYTABLE_TYPE_CCM;
2546                 break;
2547         case ATH9K_CIPHER_TKIP:
2548                 keyType = AR_KEYTABLE_TYPE_TKIP;
2549                 if (ATH9K_IS_MIC_ENABLED(ah)
2550                     && entry + 64 >= pCap->keycache_size) {
2551                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2552                                 "entry %u inappropriate for TKIP\n", entry);
2553                         return false;
2554                 }
2555                 break;
2556         case ATH9K_CIPHER_WEP:
2557                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2558                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2559                                 "WEP key length %u too small\n", k->kv_len);
2560                         return false;
2561                 }
2562                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2563                         keyType = AR_KEYTABLE_TYPE_40;
2564                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2565                         keyType = AR_KEYTABLE_TYPE_104;
2566                 else
2567                         keyType = AR_KEYTABLE_TYPE_128;
2568                 break;
2569         case ATH9K_CIPHER_CLR:
2570                 keyType = AR_KEYTABLE_TYPE_CLR;
2571                 break;
2572         default:
2573                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2574                         "cipher %u not supported\n", k->kv_type);
2575                 return false;
2576         }
2577
2578         key0 = get_unaligned_le32(k->kv_val + 0);
2579         key1 = get_unaligned_le16(k->kv_val + 4);
2580         key2 = get_unaligned_le32(k->kv_val + 6);
2581         key3 = get_unaligned_le16(k->kv_val + 10);
2582         key4 = get_unaligned_le32(k->kv_val + 12);
2583         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2584                 key4 &= 0xff;
2585
2586         /*
2587          * Note: Key cache registers access special memory area that requires
2588          * two 32-bit writes to actually update the values in the internal
2589          * memory. Consequently, the exact order and pairs used here must be
2590          * maintained.
2591          */
2592
2593         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2594                 u16 micentry = entry + 64;
2595
2596                 /*
2597                  * Write inverted key[47:0] first to avoid Michael MIC errors
2598                  * on frames that could be sent or received at the same time.
2599                  * The correct key will be written in the end once everything
2600                  * else is ready.
2601                  */
2602                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2603                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2604
2605                 /* Write key[95:48] */
2606                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2607                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2608
2609                 /* Write key[127:96] and key type */
2610                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2611                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2612
2613                 /* Write MAC address for the entry */
2614                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2615
2616                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2617                         /*
2618                          * TKIP uses two key cache entries:
2619                          * Michael MIC TX/RX keys in the same key cache entry
2620                          * (idx = main index + 64):
2621                          * key0 [31:0] = RX key [31:0]
2622                          * key1 [15:0] = TX key [31:16]
2623                          * key1 [31:16] = reserved
2624                          * key2 [31:0] = RX key [63:32]
2625                          * key3 [15:0] = TX key [15:0]
2626                          * key3 [31:16] = reserved
2627                          * key4 [31:0] = TX key [63:32]
2628                          */
2629                         u32 mic0, mic1, mic2, mic3, mic4;
2630
2631                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2632                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2633                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2634                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2635                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2636
2637                         /* Write RX[31:0] and TX[31:16] */
2638                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2639                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2640
2641                         /* Write RX[63:32] and TX[15:0] */
2642                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2643                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2644
2645                         /* Write TX[63:32] and keyType(reserved) */
2646                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2647                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2648                                   AR_KEYTABLE_TYPE_CLR);
2649
2650                 } else {
2651                         /*
2652                          * TKIP uses four key cache entries (two for group
2653                          * keys):
2654                          * Michael MIC TX/RX keys are in different key cache
2655                          * entries (idx = main index + 64 for TX and
2656                          * main index + 32 + 96 for RX):
2657                          * key0 [31:0] = TX/RX MIC key [31:0]
2658                          * key1 [31:0] = reserved
2659                          * key2 [31:0] = TX/RX MIC key [63:32]
2660                          * key3 [31:0] = reserved
2661                          * key4 [31:0] = reserved
2662                          *
2663                          * Upper layer code will call this function separately
2664                          * for TX and RX keys when these registers offsets are
2665                          * used.
2666                          */
2667                         u32 mic0, mic2;
2668
2669                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2670                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2671
2672                         /* Write MIC key[31:0] */
2673                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2674                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2675
2676                         /* Write MIC key[63:32] */
2677                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2678                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2679
2680                         /* Write TX[63:32] and keyType(reserved) */
2681                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2682                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2683                                   AR_KEYTABLE_TYPE_CLR);
2684                 }
2685
2686                 /* MAC address registers are reserved for the MIC entry */
2687                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2688                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2689
2690                 /*
2691                  * Write the correct (un-inverted) key[47:0] last to enable
2692                  * TKIP now that all other registers are set with correct
2693                  * values.
2694                  */
2695                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2696                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2697         } else {
2698                 /* Write key[47:0] */
2699                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2700                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2701
2702                 /* Write key[95:48] */
2703                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2704                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2705
2706                 /* Write key[127:96] and key type */
2707                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2708                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2709
2710                 /* Write MAC address for the entry */
2711                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2712         }
2713
2714         return true;
2715 }
2716
2717 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2718 {
2719         if (entry < ah->caps.keycache_size) {
2720                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2721                 if (val & AR_KEYTABLE_VALID)
2722                         return true;
2723         }
2724         return false;
2725 }
2726
2727 /******************************/
2728 /* Power Management (Chipset) */
2729 /******************************/
2730
2731 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2732 {
2733         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2734         if (setChip) {
2735                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2736                             AR_RTC_FORCE_WAKE_EN);
2737                 if (!AR_SREV_9100(ah))
2738                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2739
2740                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2741                             AR_RTC_RESET_EN);
2742         }
2743 }
2744
2745 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2746 {
2747         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2748         if (setChip) {
2749                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2750
2751                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2752                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2753                                   AR_RTC_FORCE_WAKE_ON_INT);
2754                 } else {
2755                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2756                                     AR_RTC_FORCE_WAKE_EN);
2757                 }
2758         }
2759 }
2760
2761 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2762 {
2763         u32 val;
2764         int i;
2765
2766         if (setChip) {
2767                 if ((REG_READ(ah, AR_RTC_STATUS) &
2768                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2769                         if (ath9k_hw_set_reset_reg(ah,
2770                                            ATH9K_RESET_POWER_ON) != true) {
2771                                 return false;
2772                         }
2773                 }
2774                 if (AR_SREV_9100(ah))
2775                         REG_SET_BIT(ah, AR_RTC_RESET,
2776                                     AR_RTC_RESET_EN);
2777
2778                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2779                             AR_RTC_FORCE_WAKE_EN);
2780                 udelay(50);
2781
2782                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2783                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2784                         if (val == AR_RTC_STATUS_ON)
2785                                 break;
2786                         udelay(50);
2787                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2788                                     AR_RTC_FORCE_WAKE_EN);
2789                 }
2790                 if (i == 0) {
2791                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2792                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2793                         return false;
2794                 }
2795         }
2796
2797         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2798
2799         return true;
2800 }
2801
2802 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2803                                      enum ath9k_power_mode mode)
2804 {
2805         int status = true, setChip = true;
2806         static const char *modes[] = {
2807                 "AWAKE",
2808                 "FULL-SLEEP",
2809                 "NETWORK SLEEP",
2810                 "UNDEFINED"
2811         };
2812
2813         if (ah->power_mode == mode)
2814                 return status;
2815
2816         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2817                 modes[ah->power_mode], modes[mode]);
2818
2819         switch (mode) {
2820         case ATH9K_PM_AWAKE:
2821                 status = ath9k_hw_set_power_awake(ah, setChip);
2822                 break;
2823         case ATH9K_PM_FULL_SLEEP:
2824                 ath9k_set_power_sleep(ah, setChip);
2825                 ah->chip_fullsleep = true;
2826                 break;
2827         case ATH9K_PM_NETWORK_SLEEP:
2828                 ath9k_set_power_network_sleep(ah, setChip);
2829                 break;
2830         default:
2831                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2832                         "Unknown power mode %u\n", mode);
2833                 return false;
2834         }
2835         ah->power_mode = mode;
2836
2837         return status;
2838 }
2839
2840 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2841 {
2842         unsigned long flags;
2843         bool ret;
2844
2845         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2846         ret = ath9k_hw_setpower_nolock(ah, mode);
2847         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2848
2849         return ret;
2850 }
2851
2852 void ath9k_ps_wakeup(struct ath_softc *sc)
2853 {
2854         unsigned long flags;
2855
2856         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2857         if (++sc->ps_usecount != 1)
2858                 goto unlock;
2859
2860         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2861
2862  unlock:
2863         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2864 }
2865
2866 void ath9k_ps_restore(struct ath_softc *sc)
2867 {
2868         unsigned long flags;
2869
2870         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2871         if (--sc->ps_usecount != 0)
2872                 goto unlock;
2873
2874         if (sc->ps_enabled &&
2875             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2876                               SC_OP_WAIT_FOR_CAB |
2877                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2878                               SC_OP_WAIT_FOR_TX_ACK)))
2879                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2880
2881  unlock:
2882         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2883 }
2884
2885 /*
2886  * Helper for ASPM support.
2887  *
2888  * Disable PLL when in L0s as well as receiver clock when in L1.
2889  * This power saving option must be enabled through the SerDes.
2890  *
2891  * Programming the SerDes must go through the same 288 bit serial shift
2892  * register as the other analog registers.  Hence the 9 writes.
2893  */
2894 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2895 {
2896         u8 i;
2897
2898         if (ah->is_pciexpress != true)
2899                 return;
2900
2901         /* Do not touch SerDes registers */
2902         if (ah->config.pcie_powersave_enable == 2)
2903                 return;
2904
2905         /* Nothing to do on restore for 11N */
2906         if (restore)
2907                 return;
2908
2909         if (AR_SREV_9280_20_OR_LATER(ah)) {
2910                 /*
2911                  * AR9280 2.0 or later chips use SerDes values from the
2912                  * initvals.h initialized depending on chipset during
2913                  * ath9k_hw_attach()
2914                  */
2915                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2916                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2917                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2918                 }
2919         } else if (AR_SREV_9280(ah) &&
2920                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2921                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2922                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2923
2924                 /* RX shut off when elecidle is asserted */
2925                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2926                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2927                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2928
2929                 /* Shut off CLKREQ active in L1 */
2930                 if (ah->config.pcie_clock_req)
2931                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2932                 else
2933                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2934
2935                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2936                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2937                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2938
2939                 /* Load the new settings */
2940                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2941
2942         } else {
2943                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2944                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2945
2946                 /* RX shut off when elecidle is asserted */
2947                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2948                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2949                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2950
2951                 /*
2952                  * Ignore ah->ah_config.pcie_clock_req setting for
2953                  * pre-AR9280 11n
2954                  */
2955                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2956
2957                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2958                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2959                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2960
2961                 /* Load the new settings */
2962                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2963         }
2964
2965         udelay(1000);
2966
2967         /* set bit 19 to allow forcing of pcie core into L1 state */
2968         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2969
2970         /* Several PCIe massages to ensure proper behaviour */
2971         if (ah->config.pcie_waen) {
2972                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2973         } else {
2974                 if (AR_SREV_9285(ah))
2975                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2976                 /*
2977                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2978                  * otherwise card may disappear.
2979                  */
2980                 else if (AR_SREV_9280(ah))
2981                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2982                 else
2983                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2984         }
2985 }
2986
2987 /**********************/
2988 /* Interrupt Handling */
2989 /**********************/
2990
2991 bool ath9k_hw_intrpend(struct ath_hw *ah)
2992 {
2993         u32 host_isr;
2994
2995         if (AR_SREV_9100(ah))
2996                 return true;
2997
2998         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2999         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3000                 return true;
3001
3002         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3003         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3004             && (host_isr != AR_INTR_SPURIOUS))
3005                 return true;
3006
3007         return false;
3008 }
3009
3010 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3011 {
3012         u32 isr = 0;
3013         u32 mask2 = 0;
3014         struct ath9k_hw_capabilities *pCap = &ah->caps;
3015         u32 sync_cause = 0;
3016         bool fatal_int = false;
3017
3018         if (!AR_SREV_9100(ah)) {
3019                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3020                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3021                             == AR_RTC_STATUS_ON) {
3022                                 isr = REG_READ(ah, AR_ISR);
3023                         }
3024                 }
3025
3026                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3027                         AR_INTR_SYNC_DEFAULT;
3028
3029                 *masked = 0;
3030
3031                 if (!isr && !sync_cause)
3032                         return false;
3033         } else {
3034                 *masked = 0;
3035                 isr = REG_READ(ah, AR_ISR);
3036         }
3037
3038         if (isr) {
3039                 if (isr & AR_ISR_BCNMISC) {
3040                         u32 isr2;
3041                         isr2 = REG_READ(ah, AR_ISR_S2);
3042                         if (isr2 & AR_ISR_S2_TIM)
3043                                 mask2 |= ATH9K_INT_TIM;
3044                         if (isr2 & AR_ISR_S2_DTIM)
3045                                 mask2 |= ATH9K_INT_DTIM;
3046                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3047                                 mask2 |= ATH9K_INT_DTIMSYNC;
3048                         if (isr2 & (AR_ISR_S2_CABEND))
3049                                 mask2 |= ATH9K_INT_CABEND;
3050                         if (isr2 & AR_ISR_S2_GTT)
3051                                 mask2 |= ATH9K_INT_GTT;
3052                         if (isr2 & AR_ISR_S2_CST)
3053                                 mask2 |= ATH9K_INT_CST;
3054                         if (isr2 & AR_ISR_S2_TSFOOR)
3055                                 mask2 |= ATH9K_INT_TSFOOR;
3056                 }
3057
3058                 isr = REG_READ(ah, AR_ISR_RAC);
3059                 if (isr == 0xffffffff) {
3060                         *masked = 0;
3061                         return false;
3062                 }
3063
3064                 *masked = isr & ATH9K_INT_COMMON;
3065
3066                 if (ah->config.intr_mitigation) {
3067                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3068                                 *masked |= ATH9K_INT_RX;
3069                 }
3070
3071                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3072                         *masked |= ATH9K_INT_RX;
3073                 if (isr &
3074                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3075                      AR_ISR_TXEOL)) {
3076                         u32 s0_s, s1_s;
3077
3078                         *masked |= ATH9K_INT_TX;
3079
3080                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3081                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3082                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3083
3084                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3085                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3086                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3087                 }
3088
3089                 if (isr & AR_ISR_RXORN) {
3090                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3091                                 "receive FIFO overrun interrupt\n");
3092                 }
3093
3094                 if (!AR_SREV_9100(ah)) {
3095                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3096                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3097                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3098                                         *masked |= ATH9K_INT_TIM_TIMER;
3099                         }
3100                 }
3101
3102                 *masked |= mask2;
3103         }
3104
3105         if (AR_SREV_9100(ah))
3106                 return true;
3107
3108         if (sync_cause) {
3109                 fatal_int =
3110                         (sync_cause &
3111                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3112                         ? true : false;
3113
3114                 if (fatal_int) {
3115                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3116                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3117                                         "received PCI FATAL interrupt\n");
3118                         }
3119                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3120                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3121                                         "received PCI PERR interrupt\n");
3122                         }
3123                         *masked |= ATH9K_INT_FATAL;
3124                 }
3125                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3126                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3127                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3128                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3129                         REG_WRITE(ah, AR_RC, 0);
3130                         *masked |= ATH9K_INT_FATAL;
3131                 }
3132                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3133                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3134                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3135                 }
3136
3137                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3138                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3139         }
3140
3141         return true;
3142 }
3143
3144 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3145 {
3146         u32 omask = ah->mask_reg;
3147         u32 mask, mask2;
3148         struct ath9k_hw_capabilities *pCap = &ah->caps;
3149
3150         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3151
3152         if (omask & ATH9K_INT_GLOBAL) {
3153                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3154                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3155                 (void) REG_READ(ah, AR_IER);
3156                 if (!AR_SREV_9100(ah)) {
3157                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3158                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3159
3160                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3161                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3162                 }
3163         }
3164
3165         mask = ints & ATH9K_INT_COMMON;
3166         mask2 = 0;
3167
3168         if (ints & ATH9K_INT_TX) {
3169                 if (ah->txok_interrupt_mask)
3170                         mask |= AR_IMR_TXOK;
3171                 if (ah->txdesc_interrupt_mask)
3172                         mask |= AR_IMR_TXDESC;
3173                 if (ah->txerr_interrupt_mask)
3174                         mask |= AR_IMR_TXERR;
3175                 if (ah->txeol_interrupt_mask)
3176                         mask |= AR_IMR_TXEOL;
3177         }
3178         if (ints & ATH9K_INT_RX) {
3179                 mask |= AR_IMR_RXERR;
3180                 if (ah->config.intr_mitigation)
3181                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3182                 else
3183                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3184                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3185                         mask |= AR_IMR_GENTMR;
3186         }
3187
3188         if (ints & (ATH9K_INT_BMISC)) {
3189                 mask |= AR_IMR_BCNMISC;
3190                 if (ints & ATH9K_INT_TIM)
3191                         mask2 |= AR_IMR_S2_TIM;
3192                 if (ints & ATH9K_INT_DTIM)
3193                         mask2 |= AR_IMR_S2_DTIM;
3194                 if (ints & ATH9K_INT_DTIMSYNC)
3195                         mask2 |= AR_IMR_S2_DTIMSYNC;
3196                 if (ints & ATH9K_INT_CABEND)
3197                         mask2 |= AR_IMR_S2_CABEND;
3198                 if (ints & ATH9K_INT_TSFOOR)
3199                         mask2 |= AR_IMR_S2_TSFOOR;
3200         }
3201
3202         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3203                 mask |= AR_IMR_BCNMISC;
3204                 if (ints & ATH9K_INT_GTT)
3205                         mask2 |= AR_IMR_S2_GTT;
3206                 if (ints & ATH9K_INT_CST)
3207                         mask2 |= AR_IMR_S2_CST;
3208         }
3209
3210         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3211         REG_WRITE(ah, AR_IMR, mask);
3212         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3213                                            AR_IMR_S2_DTIM |
3214                                            AR_IMR_S2_DTIMSYNC |
3215                                            AR_IMR_S2_CABEND |
3216                                            AR_IMR_S2_CABTO |
3217                                            AR_IMR_S2_TSFOOR |
3218                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3219         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3220         ah->mask_reg = ints;
3221
3222         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3223                 if (ints & ATH9K_INT_TIM_TIMER)
3224                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3225                 else
3226                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3227         }
3228
3229         if (ints & ATH9K_INT_GLOBAL) {
3230                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3231                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3232                 if (!AR_SREV_9100(ah)) {
3233                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3234                                   AR_INTR_MAC_IRQ);
3235                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3236
3237
3238                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3239                                   AR_INTR_SYNC_DEFAULT);
3240                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3241                                   AR_INTR_SYNC_DEFAULT);
3242                 }
3243                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3244                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3245         }
3246
3247         return omask;
3248 }
3249
3250 /*******************/
3251 /* Beacon Handling */
3252 /*******************/
3253
3254 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3255 {
3256         int flags = 0;
3257
3258         ah->beacon_interval = beacon_period;
3259
3260         switch (ah->opmode) {
3261         case NL80211_IFTYPE_STATION:
3262         case NL80211_IFTYPE_MONITOR:
3263                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3264                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3265                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3266                 flags |= AR_TBTT_TIMER_EN;
3267                 break;
3268         case NL80211_IFTYPE_ADHOC:
3269         case NL80211_IFTYPE_MESH_POINT:
3270                 REG_SET_BIT(ah, AR_TXCFG,
3271                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3272                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3273                           TU_TO_USEC(next_beacon +
3274                                      (ah->atim_window ? ah->
3275                                       atim_window : 1)));
3276                 flags |= AR_NDP_TIMER_EN;
3277         case NL80211_IFTYPE_AP:
3278                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3279                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3280                           TU_TO_USEC(next_beacon -
3281                                      ah->config.
3282                                      dma_beacon_response_time));
3283                 REG_WRITE(ah, AR_NEXT_SWBA,
3284                           TU_TO_USEC(next_beacon -
3285                                      ah->config.
3286                                      sw_beacon_response_time));
3287                 flags |=
3288                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3289                 break;
3290         default:
3291                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3292                         "%s: unsupported opmode: %d\n",
3293                         __func__, ah->opmode);
3294                 return;
3295                 break;
3296         }
3297
3298         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3299         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3300         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3301         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3302
3303         beacon_period &= ~ATH9K_BEACON_ENA;
3304         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3305                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3306                 ath9k_hw_reset_tsf(ah);
3307         }
3308
3309         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3310 }
3311
3312 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3313                                     const struct ath9k_beacon_state *bs)
3314 {
3315         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3316         struct ath9k_hw_capabilities *pCap = &ah->caps;
3317
3318         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3319
3320         REG_WRITE(ah, AR_BEACON_PERIOD,
3321                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3322         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3323                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3324
3325         REG_RMW_FIELD(ah, AR_RSSI_THR,
3326                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3327
3328         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3329
3330         if (bs->bs_sleepduration > beaconintval)
3331                 beaconintval = bs->bs_sleepduration;
3332
3333         dtimperiod = bs->bs_dtimperiod;
3334         if (bs->bs_sleepduration > dtimperiod)
3335                 dtimperiod = bs->bs_sleepduration;
3336
3337         if (beaconintval == dtimperiod)
3338                 nextTbtt = bs->bs_nextdtim;
3339         else
3340                 nextTbtt = bs->bs_nexttbtt;
3341
3342         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3343         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3344         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3345         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3346
3347         REG_WRITE(ah, AR_NEXT_DTIM,
3348                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3349         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3350
3351         REG_WRITE(ah, AR_SLEEP1,
3352                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3353                   | AR_SLEEP1_ASSUME_DTIM);
3354
3355         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3356                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3357         else
3358                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3359
3360         REG_WRITE(ah, AR_SLEEP2,
3361                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3362
3363         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3364         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3365
3366         REG_SET_BIT(ah, AR_TIMER_MODE,
3367                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3368                     AR_DTIM_TIMER_EN);
3369
3370         /* TSF Out of Range Threshold */
3371         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3372 }
3373
3374 /*******************/
3375 /* HW Capabilities */
3376 /*******************/
3377
3378 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3379 {
3380         struct ath9k_hw_capabilities *pCap = &ah->caps;
3381         u16 capField = 0, eeval;
3382
3383         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3384         ah->regulatory.current_rd = eeval;
3385
3386         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3387         if (AR_SREV_9285_10_OR_LATER(ah))
3388                 eeval |= AR9285_RDEXT_DEFAULT;
3389         ah->regulatory.current_rd_ext = eeval;
3390
3391         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3392
3393         if (ah->opmode != NL80211_IFTYPE_AP &&
3394             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3395                 if (ah->regulatory.current_rd == 0x64 ||
3396                     ah->regulatory.current_rd == 0x65)
3397                         ah->regulatory.current_rd += 5;
3398                 else if (ah->regulatory.current_rd == 0x41)
3399                         ah->regulatory.current_rd = 0x43;
3400                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3401                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3402         }
3403
3404         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3405         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3406
3407         if (eeval & AR5416_OPFLAGS_11A) {
3408                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3409                 if (ah->config.ht_enable) {
3410                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3411                                 set_bit(ATH9K_MODE_11NA_HT20,
3412                                         pCap->wireless_modes);
3413                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3414                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3415                                         pCap->wireless_modes);
3416                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3417                                         pCap->wireless_modes);
3418                         }
3419                 }
3420         }
3421
3422         if (eeval & AR5416_OPFLAGS_11G) {
3423                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3424                 if (ah->config.ht_enable) {
3425                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3426                                 set_bit(ATH9K_MODE_11NG_HT20,
3427                                         pCap->wireless_modes);
3428                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3429                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3430                                         pCap->wireless_modes);
3431                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3432                                         pCap->wireless_modes);
3433                         }
3434                 }
3435         }
3436
3437         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3438         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3439             !(eeval & AR5416_OPFLAGS_11A))
3440                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3441         else
3442                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3443
3444         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3445                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3446
3447         pCap->low_2ghz_chan = 2312;
3448         pCap->high_2ghz_chan = 2732;
3449
3450         pCap->low_5ghz_chan = 4920;
3451         pCap->high_5ghz_chan = 6100;
3452
3453         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3454         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3455         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3456
3457         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3458         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3459         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3460
3461         if (ah->config.ht_enable)
3462                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3463         else
3464                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3465
3466         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3467         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3468         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3469         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3470
3471         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3472                 pCap->total_queues =
3473                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3474         else
3475                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3476
3477         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3478                 pCap->keycache_size =
3479                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3480         else
3481                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3482
3483         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3484         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3485
3486         if (AR_SREV_9285_10_OR_LATER(ah))
3487                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3488         else if (AR_SREV_9280_10_OR_LATER(ah))
3489                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3490         else
3491                 pCap->num_gpio_pins = AR_NUM_GPIO;
3492
3493         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3494                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3495                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3496         } else {
3497                 pCap->rts_aggr_limit = (8 * 1024);
3498         }
3499
3500         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3501
3502 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3503         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3504         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3505                 ah->rfkill_gpio =
3506                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3507                 ah->rfkill_polarity =
3508                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3509
3510                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3511         }
3512 #endif
3513
3514         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3515             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3516             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3517             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3518             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3519             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3520                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3521         else
3522                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3523
3524         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3525                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3526         else
3527                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3528
3529         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3530                 pCap->reg_cap =
3531                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3532                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3533                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3534                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3535         } else {
3536                 pCap->reg_cap =
3537                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3538                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3539         }
3540
3541         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3542
3543         pCap->num_antcfg_5ghz =
3544                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3545         pCap->num_antcfg_2ghz =
3546                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3547
3548         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3549                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3550                 ah->btactive_gpio = 6;
3551                 ah->wlanactive_gpio = 5;
3552         }
3553 }
3554
3555 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3556                             u32 capability, u32 *result)
3557 {
3558         switch (type) {
3559         case ATH9K_CAP_CIPHER:
3560                 switch (capability) {
3561                 case ATH9K_CIPHER_AES_CCM:
3562                 case ATH9K_CIPHER_AES_OCB:
3563                 case ATH9K_CIPHER_TKIP:
3564                 case ATH9K_CIPHER_WEP:
3565                 case ATH9K_CIPHER_MIC:
3566                 case ATH9K_CIPHER_CLR:
3567                         return true;
3568                 default:
3569                         return false;
3570                 }
3571         case ATH9K_CAP_TKIP_MIC:
3572                 switch (capability) {
3573                 case 0:
3574                         return true;
3575                 case 1:
3576                         return (ah->sta_id1_defaults &
3577                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3578                         false;
3579                 }
3580         case ATH9K_CAP_TKIP_SPLIT:
3581                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3582                         false : true;
3583         case ATH9K_CAP_DIVERSITY:
3584                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3585                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3586                         true : false;
3587         case ATH9K_CAP_MCAST_KEYSRCH:
3588                 switch (capability) {
3589                 case 0:
3590                         return true;
3591                 case 1:
3592                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3593                                 return false;
3594                         } else {
3595                                 return (ah->sta_id1_defaults &
3596                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3597                                         false;
3598                         }
3599                 }
3600                 return false;
3601         case ATH9K_CAP_TXPOW:
3602                 switch (capability) {
3603                 case 0:
3604                         return 0;
3605                 case 1:
3606                         *result = ah->regulatory.power_limit;
3607                         return 0;
3608                 case 2:
3609                         *result = ah->regulatory.max_power_level;
3610                         return 0;
3611                 case 3:
3612                         *result = ah->regulatory.tp_scale;
3613                         return 0;
3614                 }
3615                 return false;
3616         case ATH9K_CAP_DS:
3617                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3618                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3619                         ? false : true;
3620         default:
3621                 return false;
3622         }
3623 }
3624
3625 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3626                             u32 capability, u32 setting, int *status)
3627 {
3628         u32 v;
3629
3630         switch (type) {
3631         case ATH9K_CAP_TKIP_MIC:
3632                 if (setting)
3633                         ah->sta_id1_defaults |=
3634                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3635                 else
3636                         ah->sta_id1_defaults &=
3637                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3638                 return true;
3639         case ATH9K_CAP_DIVERSITY:
3640                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3641                 if (setting)
3642                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3643                 else
3644                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3645                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3646                 return true;
3647         case ATH9K_CAP_MCAST_KEYSRCH:
3648                 if (setting)
3649                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3650                 else
3651                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3652                 return true;
3653         default:
3654                 return false;
3655         }
3656 }
3657
3658 /****************************/
3659 /* GPIO / RFKILL / Antennae */
3660 /****************************/
3661
3662 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3663                                          u32 gpio, u32 type)
3664 {
3665         int addr;
3666         u32 gpio_shift, tmp;
3667
3668         if (gpio > 11)
3669                 addr = AR_GPIO_OUTPUT_MUX3;
3670         else if (gpio > 5)
3671                 addr = AR_GPIO_OUTPUT_MUX2;
3672         else
3673                 addr = AR_GPIO_OUTPUT_MUX1;
3674
3675         gpio_shift = (gpio % 6) * 5;
3676
3677         if (AR_SREV_9280_20_OR_LATER(ah)
3678             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3679                 REG_RMW(ah, addr, (type << gpio_shift),
3680                         (0x1f << gpio_shift));
3681         } else {
3682                 tmp = REG_READ(ah, addr);
3683                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3684                 tmp &= ~(0x1f << gpio_shift);
3685                 tmp |= (type << gpio_shift);
3686                 REG_WRITE(ah, addr, tmp);
3687         }
3688 }
3689
3690 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3691 {
3692         u32 gpio_shift;
3693
3694         ASSERT(gpio < ah->caps.num_gpio_pins);
3695
3696         gpio_shift = gpio << 1;
3697
3698         REG_RMW(ah,
3699                 AR_GPIO_OE_OUT,
3700                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3701                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3702 }
3703
3704 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3705 {
3706 #define MS_REG_READ(x, y) \
3707         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3708
3709         if (gpio >= ah->caps.num_gpio_pins)
3710                 return 0xffffffff;
3711
3712         if (AR_SREV_9287_10_OR_LATER(ah))
3713                 return MS_REG_READ(AR9287, gpio) != 0;
3714         else if (AR_SREV_9285_10_OR_LATER(ah))
3715                 return MS_REG_READ(AR9285, gpio) != 0;
3716         else if (AR_SREV_9280_10_OR_LATER(ah))
3717                 return MS_REG_READ(AR928X, gpio) != 0;
3718         else
3719                 return MS_REG_READ(AR, gpio) != 0;
3720 }
3721
3722 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3723                          u32 ah_signal_type)
3724 {
3725         u32 gpio_shift;
3726
3727         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3728
3729         gpio_shift = 2 * gpio;
3730
3731         REG_RMW(ah,
3732                 AR_GPIO_OE_OUT,
3733                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3734                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3735 }
3736
3737 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3738 {
3739         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3740                 AR_GPIO_BIT(gpio));
3741 }
3742
3743 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3744 {
3745         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3746 }
3747
3748 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3749 {
3750         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3751 }
3752
3753 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3754                                enum ath9k_ant_setting settings,
3755                                struct ath9k_channel *chan,
3756                                u8 *tx_chainmask,
3757                                u8 *rx_chainmask,
3758                                u8 *antenna_cfgd)
3759 {
3760         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3761
3762         if (AR_SREV_9280(ah)) {
3763                 if (!tx_chainmask_cfg) {
3764
3765                         tx_chainmask_cfg = *tx_chainmask;
3766                         rx_chainmask_cfg = *rx_chainmask;
3767                 }
3768
3769                 switch (settings) {
3770                 case ATH9K_ANT_FIXED_A:
3771                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3772                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3773                         *antenna_cfgd = true;
3774                         break;
3775                 case ATH9K_ANT_FIXED_B:
3776                         if (ah->caps.tx_chainmask >
3777                             ATH9K_ANTENNA1_CHAINMASK) {
3778                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3779                         }
3780                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3781                         *antenna_cfgd = true;
3782                         break;
3783                 case ATH9K_ANT_VARIABLE:
3784                         *tx_chainmask = tx_chainmask_cfg;
3785                         *rx_chainmask = rx_chainmask_cfg;
3786                         *antenna_cfgd = true;
3787                         break;
3788                 default:
3789                         break;
3790                 }
3791         } else {
3792                 ah->diversity_control = settings;
3793         }
3794
3795         return true;
3796 }
3797
3798 /*********************/
3799 /* General Operation */
3800 /*********************/
3801
3802 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3803 {
3804         u32 bits = REG_READ(ah, AR_RX_FILTER);
3805         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3806
3807         if (phybits & AR_PHY_ERR_RADAR)
3808                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3809         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3810                 bits |= ATH9K_RX_FILTER_PHYERR;
3811
3812         return bits;
3813 }
3814
3815 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3816 {
3817         u32 phybits;
3818
3819         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3820         phybits = 0;
3821         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3822                 phybits |= AR_PHY_ERR_RADAR;
3823         if (bits & ATH9K_RX_FILTER_PHYERR)
3824                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3825         REG_WRITE(ah, AR_PHY_ERR, phybits);
3826
3827         if (phybits)
3828                 REG_WRITE(ah, AR_RXCFG,
3829                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3830         else
3831                 REG_WRITE(ah, AR_RXCFG,
3832                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3833 }
3834
3835 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3836 {
3837         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3838 }
3839
3840 bool ath9k_hw_disable(struct ath_hw *ah)
3841 {
3842         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3843                 return false;
3844
3845         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3846 }
3847
3848 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3849 {
3850         struct ath9k_channel *chan = ah->curchan;
3851         struct ieee80211_channel *channel = chan->chan;
3852
3853         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3854
3855         ah->eep_ops->set_txpower(ah, chan,
3856                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3857                                  channel->max_antenna_gain * 2,
3858                                  channel->max_power * 2,
3859                                  min((u32) MAX_RATE_POWER,
3860                                  (u32) ah->regulatory.power_limit));
3861 }
3862
3863 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3864 {
3865         memcpy(ah->macaddr, mac, ETH_ALEN);
3866 }
3867
3868 void ath9k_hw_setopmode(struct ath_hw *ah)
3869 {
3870         ath9k_hw_set_operating_mode(ah, ah->opmode);
3871 }
3872
3873 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3874 {
3875         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3876         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3877 }
3878
3879 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3880 {
3881         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3882         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3883 }
3884
3885 void ath9k_hw_write_associd(struct ath_softc *sc)
3886 {
3887         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3888         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3889                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3890 }
3891
3892 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3893 {
3894         u64 tsf;
3895
3896         tsf = REG_READ(ah, AR_TSF_U32);
3897         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3898
3899         return tsf;
3900 }
3901
3902 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3903 {
3904         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3905         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3906 }
3907
3908 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3909 {
3910         ath9k_ps_wakeup(ah->ah_sc);
3911         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3912                            AH_TSF_WRITE_TIMEOUT))
3913                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3914                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3915
3916         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3917         ath9k_ps_restore(ah->ah_sc);
3918 }
3919
3920 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3921 {
3922         if (setting)
3923                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3924         else
3925                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3926
3927         return true;
3928 }
3929
3930 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3931 {
3932         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3933                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3934                 ah->slottime = (u32) -1;
3935                 return false;
3936         } else {
3937                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3938                 ah->slottime = us;
3939                 return true;
3940         }
3941 }
3942
3943 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3944 {
3945         u32 macmode;
3946
3947         if (mode == ATH9K_HT_MACMODE_2040 &&
3948             !ah->config.cwm_ignore_extcca)
3949                 macmode = AR_2040_JOINED_RX_CLEAR;
3950         else
3951                 macmode = 0;
3952
3953         REG_WRITE(ah, AR_2040_MODE, macmode);
3954 }
3955
3956 /***************************/
3957 /*  Bluetooth Coexistence  */
3958 /***************************/
3959
3960 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3961 {
3962         /* connect bt_active to baseband */
3963         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3964                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3965                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3966
3967         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3968                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3969
3970         /* Set input mux for bt_active to gpio pin */
3971         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3972                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3973                         ah->btactive_gpio);
3974
3975         /* Configure the desired gpio port for input */
3976         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3977
3978         /* Configure the desired GPIO port for TX_FRAME output */
3979         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3980                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3981 }