2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init ath9k_init(void)
37 module_init(ath9k_init);
39 static void __exit ath9k_exit(void)
43 module_exit(ath9k_exit);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
99 if (conf_is_ht40(conf))
102 common->clockrate = clockrate;
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
107 struct ath_common *common = ath9k_hw_common(ah);
109 return usecs * common->clockrate;
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
116 BUG_ON(timeout < AH_TIME_QUANTUM);
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
122 udelay(AH_TIME_QUANTUM);
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
131 EXPORT_SYMBOL(ath9k_hw_wait);
133 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
144 REGWRITE_BUFFER_FLUSH(ah);
147 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
161 u32 frameLen, u16 rateix,
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
254 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
261 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
264 val = REG_READ(ah, AR_SREV);
265 ah->hw_version.macVersion =
266 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
267 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
268 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
270 if (!AR_SREV_9100(ah))
271 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
273 ah->hw_version.macRev = val & AR_SREV_REVISION;
275 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
276 ah->is_pciexpress = true;
280 /************************************/
281 /* HW Attach, Detach, Init Routines */
282 /************************************/
284 static void ath9k_hw_disablepcie(struct ath_hw *ah)
286 if (!AR_SREV_5416(ah))
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
302 /* This should work for all families including legacy */
303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
305 struct ath_common *common = ath9k_hw_common(ah);
306 u32 regAddr[2] = { AR_STA_ID0 };
308 static const u32 patternData[4] = {
309 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
319 for (i = 0; i < loop_max; i++) {
320 u32 addr = regAddr[i];
323 regHold[i] = REG_READ(ah, addr);
324 for (j = 0; j < 0x100; j++) {
325 wrData = (j << 16) | j;
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (rdData != wrData) {
330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
331 addr, wrData, rdData);
335 for (j = 0; j < 4; j++) {
336 wrData = patternData[j];
337 REG_WRITE(ah, addr, wrData);
338 rdData = REG_READ(ah, addr);
339 if (wrData != rdData) {
341 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
342 addr, wrData, rdData);
346 REG_WRITE(ah, regAddr[i], regHold[i]);
353 static void ath9k_hw_init_config(struct ath_hw *ah)
357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
363 ah->config.pcie_clock_req = 0;
364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
366 ah->config.enable_ani = true;
368 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
369 ah->config.spurchans[i][0] = AR_NO_SPUR;
370 ah->config.spurchans[i][1] = AR_NO_SPUR;
373 /* PAPRD needs some more work to be enabled */
374 ah->config.paprd_disable = 1;
376 ah->config.rx_intr_mitigation = true;
377 ah->config.pcieSerDesWrite = true;
380 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
381 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
382 * This means we use it for all AR5416 devices, and the few
383 * minor PCI AR9280 devices out there.
385 * Serialization is required because these devices do not handle
386 * well the case of two concurrent reads/writes due to the latency
387 * involved. During one read/write another read/write can be issued
388 * on another CPU while the previous read/write may still be working
389 * on our hardware, if we hit this case the hardware poops in a loop.
390 * We prevent this by serializing reads and writes.
392 * This issue is not present on PCI-Express devices or pre-AR5416
393 * devices (legacy, 802.11abg).
395 if (num_possible_cpus() > 1)
396 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
399 static void ath9k_hw_init_defaults(struct ath_hw *ah)
401 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
403 regulatory->country_code = CTRY_DEFAULT;
404 regulatory->power_limit = MAX_RATE_POWER;
405 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
407 ah->hw_version.magic = AR5416_MAGIC;
408 ah->hw_version.subvendorid = 0;
411 ah->sta_id1_defaults =
412 AR_STA_ID1_CRPT_MIC_ENABLE |
413 AR_STA_ID1_MCAST_KSRCH;
414 if (AR_SREV_9100(ah))
415 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
416 ah->enable_32kHz_clock = DONT_USE_32KHZ;
418 ah->globaltxtimeout = (u32) -1;
419 ah->power_mode = ATH9K_PM_UNDEFINED;
422 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
424 struct ath_common *common = ath9k_hw_common(ah);
428 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
431 for (i = 0; i < 3; i++) {
432 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
434 common->macaddr[2 * i] = eeval >> 8;
435 common->macaddr[2 * i + 1] = eeval & 0xff;
437 if (sum == 0 || sum == 0xffff * 3)
438 return -EADDRNOTAVAIL;
443 static int ath9k_hw_post_init(struct ath_hw *ah)
445 struct ath_common *common = ath9k_hw_common(ah);
448 if (common->bus_ops->ath_bus_type != ATH_USB) {
449 if (!ath9k_hw_chip_test(ah))
453 if (!AR_SREV_9300_20_OR_LATER(ah)) {
454 ecode = ar9002_hw_rf_claim(ah);
459 ecode = ath9k_hw_eeprom_init(ah);
463 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
464 "Eeprom VER: %d, REV: %d\n",
465 ah->eep_ops->get_eeprom_ver(ah),
466 ah->eep_ops->get_eeprom_rev(ah));
468 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
470 ath_err(ath9k_hw_common(ah),
471 "Failed allocating banks for external radio\n");
472 ath9k_hw_rf_free_ext_banks(ah);
476 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
477 ath9k_hw_ani_setup(ah);
478 ath9k_hw_ani_init(ah);
484 static void ath9k_hw_attach_ops(struct ath_hw *ah)
486 if (AR_SREV_9300_20_OR_LATER(ah))
487 ar9003_hw_attach_ops(ah);
489 ar9002_hw_attach_ops(ah);
492 /* Called for all hardware families */
493 static int __ath9k_hw_init(struct ath_hw *ah)
495 struct ath_common *common = ath9k_hw_common(ah);
498 ath9k_hw_read_revisions(ah);
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
510 ath_err(common, "Couldn't reset chip\n");
514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
517 ath9k_hw_attach_ops(ah);
519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
520 ath_err(common, "Couldn't wakeup chip\n");
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
528 ah->config.serialize_regmode =
531 ah->config.serialize_regmode =
536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
537 ah->config.serialize_regmode);
539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 case AR_SREV_VERSION_9340:
559 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
560 ah->hw_version.macVersion, ah->hw_version.macRev);
564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
565 ah->is_pciexpress = false;
567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
568 ath9k_hw_init_cal_settings(ah);
570 ah->ani_function = ATH9K_ANI_ALL;
571 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
573 if (!AR_SREV_9300_20_OR_LATER(ah))
574 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
576 ath9k_hw_init_mode_regs(ah);
579 if (ah->is_pciexpress)
580 ath9k_hw_configpcipowersave(ah, 0, 0);
582 ath9k_hw_disablepcie(ah);
584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ar9002_hw_cck_chan14_spread(ah);
587 r = ath9k_hw_post_init(ah);
591 ath9k_hw_init_mode_gain_regs(ah);
592 r = ath9k_hw_fill_cap_info(ah);
596 r = ath9k_hw_init_macaddr(ah);
598 ath_err(common, "Failed to initialize MAC address\n");
602 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
603 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
607 ah->bb_watchdog_timeout_ms = 25;
609 common->state = ATH_HW_INITIALIZED;
614 int ath9k_hw_init(struct ath_hw *ah)
617 struct ath_common *common = ath9k_hw_common(ah);
619 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
620 switch (ah->hw_version.devid) {
621 case AR5416_DEVID_PCI:
622 case AR5416_DEVID_PCIE:
623 case AR5416_AR9100_DEVID:
624 case AR9160_DEVID_PCI:
625 case AR9280_DEVID_PCI:
626 case AR9280_DEVID_PCIE:
627 case AR9285_DEVID_PCIE:
628 case AR9287_DEVID_PCI:
629 case AR9287_DEVID_PCIE:
630 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE:
632 case AR9300_DEVID_AR9485_PCIE:
633 case AR9300_DEVID_AR9340:
636 if (common->bus_ops->ath_bus_type == ATH_USB)
638 ath_err(common, "Hardware device ID 0x%04x not supported\n",
639 ah->hw_version.devid);
643 ret = __ath9k_hw_init(ah);
646 "Unable to initialize hardware; initialization status: %d\n",
653 EXPORT_SYMBOL(ath9k_hw_init);
655 static void ath9k_hw_init_qos(struct ath_hw *ah)
657 ENABLE_REGWRITE_BUFFER(ah);
659 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
660 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
662 REG_WRITE(ah, AR_QOS_NO_ACK,
663 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
664 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
665 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
667 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
668 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
673 REGWRITE_BUFFER_FLUSH(ah);
676 unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
678 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
680 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
682 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
685 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
687 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
689 static void ath9k_hw_init_pll(struct ath_hw *ah,
690 struct ath9k_channel *chan)
694 if (AR_SREV_9485(ah)) {
696 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
697 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
698 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
699 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
700 AR_CH0_DPLL2_KD, 0x40);
701 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
702 AR_CH0_DPLL2_KI, 0x4);
704 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
705 AR_CH0_BB_DPLL1_REFDIV, 0x5);
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
707 AR_CH0_BB_DPLL1_NINI, 0x58);
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
709 AR_CH0_BB_DPLL1_NFRAC, 0x0);
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
714 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
716 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
718 /* program BB PLL phase_shift to 0x6 */
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
720 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
725 } else if (AR_SREV_9340(ah)) {
726 u32 regval, pll2_divint, pll2_divfrac, refdiv;
728 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
731 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
734 if (ah->is_clk_25mhz) {
736 pll2_divfrac = 0x1eb85;
744 regval = REG_READ(ah, AR_PHY_PLL_MODE);
745 regval |= (0x1 << 16);
746 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
749 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
750 (pll2_divint << 18) | pll2_divfrac);
753 regval = REG_READ(ah, AR_PHY_PLL_MODE);
754 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
755 (0x4 << 26) | (0x18 << 19);
756 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
757 REG_WRITE(ah, AR_PHY_PLL_MODE,
758 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
762 pll = ath9k_hw_compute_pll_control(ah, chan);
764 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
766 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
769 /* Switch the core clock for ar9271 to 117Mhz */
770 if (AR_SREV_9271(ah)) {
772 REG_WRITE(ah, 0x50040, 0x304);
775 udelay(RTC_PLL_SETTLE_DELAY);
777 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
779 if (AR_SREV_9340(ah)) {
780 if (ah->is_clk_25mhz) {
781 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
782 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
783 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
785 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
786 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
787 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
793 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
794 enum nl80211_iftype opmode)
796 u32 sync_default = AR_INTR_SYNC_DEFAULT;
797 u32 imr_reg = AR_IMR_TXERR |
803 if (AR_SREV_9340(ah))
804 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
806 if (AR_SREV_9300_20_OR_LATER(ah)) {
807 imr_reg |= AR_IMR_RXOK_HP;
808 if (ah->config.rx_intr_mitigation)
809 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
811 imr_reg |= AR_IMR_RXOK_LP;
814 if (ah->config.rx_intr_mitigation)
815 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
817 imr_reg |= AR_IMR_RXOK;
820 if (ah->config.tx_intr_mitigation)
821 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
823 imr_reg |= AR_IMR_TXOK;
825 if (opmode == NL80211_IFTYPE_AP)
826 imr_reg |= AR_IMR_MIB;
828 ENABLE_REGWRITE_BUFFER(ah);
830 REG_WRITE(ah, AR_IMR, imr_reg);
831 ah->imrs2_reg |= AR_IMR_S2_GTT;
832 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
834 if (!AR_SREV_9100(ah)) {
835 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
836 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
837 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
840 REGWRITE_BUFFER_FLUSH(ah);
842 if (AR_SREV_9300_20_OR_LATER(ah)) {
843 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
844 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
845 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
846 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
850 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
852 u32 val = ath9k_hw_mac_to_clks(ah, us);
853 val = min(val, (u32) 0xFFFF);
854 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
857 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
859 u32 val = ath9k_hw_mac_to_clks(ah, us);
860 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
861 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
864 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
866 u32 val = ath9k_hw_mac_to_clks(ah, us);
867 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
868 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
871 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
874 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
875 "bad global tx timeout %u\n", tu);
876 ah->globaltxtimeout = (u32) -1;
879 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
880 ah->globaltxtimeout = tu;
885 void ath9k_hw_init_global_settings(struct ath_hw *ah)
887 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
892 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
895 if (ah->misc_mode != 0)
896 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
898 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
903 /* As defined by IEEE 802.11-2007 17.3.8.6 */
904 slottime = ah->slottime + 3 * ah->coverage_class;
905 acktimeout = slottime + sifstime;
908 * Workaround for early ACK timeouts, add an offset to match the
909 * initval's 64us ack timeout value.
910 * This was initially only meant to work around an issue with delayed
911 * BA frames in some implementations, but it has been found to fix ACK
912 * timeout issues in other cases as well.
914 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
915 acktimeout += 64 - sifstime - ah->slottime;
917 ath9k_hw_setslottime(ah, ah->slottime);
918 ath9k_hw_set_ack_timeout(ah, acktimeout);
919 ath9k_hw_set_cts_timeout(ah, acktimeout);
920 if (ah->globaltxtimeout != (u32) -1)
921 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
923 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
925 void ath9k_hw_deinit(struct ath_hw *ah)
927 struct ath_common *common = ath9k_hw_common(ah);
929 if (common->state < ATH_HW_INITIALIZED)
932 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
935 ath9k_hw_rf_free_ext_banks(ah);
937 EXPORT_SYMBOL(ath9k_hw_deinit);
943 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
945 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
949 else if (IS_CHAN_G(chan))
957 /****************************************/
958 /* Reset and Channel Switching Routines */
959 /****************************************/
961 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
963 struct ath_common *common = ath9k_hw_common(ah);
965 ENABLE_REGWRITE_BUFFER(ah);
968 * set AHB_MODE not to do cacheline prefetches
970 if (!AR_SREV_9300_20_OR_LATER(ah))
971 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
974 * let mac dma reads be in 128 byte chunks
976 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
978 REGWRITE_BUFFER_FLUSH(ah);
981 * Restore TX Trigger Level to its pre-reset value.
982 * The initial value depends on whether aggregation is enabled, and is
983 * adjusted whenever underruns are detected.
985 if (!AR_SREV_9300_20_OR_LATER(ah))
986 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
988 ENABLE_REGWRITE_BUFFER(ah);
991 * let mac dma writes be in 128 byte chunks
993 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
996 * Setup receive FIFO threshold to hold off TX activities
998 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1000 if (AR_SREV_9300_20_OR_LATER(ah)) {
1001 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1002 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1004 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1005 ah->caps.rx_status_len);
1009 * reduce the number of usable entries in PCU TXBUF to avoid
1010 * wrap around issues.
1012 if (AR_SREV_9285(ah)) {
1013 /* For AR9285 the number of Fifos are reduced to half.
1014 * So set the usable tx buf size also to half to
1015 * avoid data/delimiter underruns
1017 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1018 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1019 } else if (!AR_SREV_9271(ah)) {
1020 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1021 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1024 REGWRITE_BUFFER_FLUSH(ah);
1026 if (AR_SREV_9300_20_OR_LATER(ah))
1027 ath9k_hw_reset_txstatus_ring(ah);
1030 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1032 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1033 u32 set = AR_STA_ID1_KSRCH_MODE;
1036 case NL80211_IFTYPE_ADHOC:
1037 case NL80211_IFTYPE_MESH_POINT:
1038 set |= AR_STA_ID1_ADHOC;
1039 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1041 case NL80211_IFTYPE_AP:
1042 set |= AR_STA_ID1_STA_AP;
1044 case NL80211_IFTYPE_STATION:
1045 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1048 if (!ah->is_monitoring)
1052 REG_RMW(ah, AR_STA_ID1, set, mask);
1055 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1056 u32 *coef_mantissa, u32 *coef_exponent)
1058 u32 coef_exp, coef_man;
1060 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1061 if ((coef_scaled >> coef_exp) & 0x1)
1064 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1066 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1068 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1069 *coef_exponent = coef_exp - 16;
1072 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1077 if (AR_SREV_9100(ah)) {
1078 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1079 AR_RTC_DERIVED_CLK_PERIOD, 1);
1080 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1083 ENABLE_REGWRITE_BUFFER(ah);
1085 if (AR_SREV_9300_20_OR_LATER(ah)) {
1086 REG_WRITE(ah, AR_WA, ah->WARegVal);
1090 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1091 AR_RTC_FORCE_WAKE_ON_INT);
1093 if (AR_SREV_9100(ah)) {
1094 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1095 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1097 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1099 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1100 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1102 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1105 if (!AR_SREV_9300_20_OR_LATER(ah))
1107 REG_WRITE(ah, AR_RC, val);
1109 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1110 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1112 rst_flags = AR_RTC_RC_MAC_WARM;
1113 if (type == ATH9K_RESET_COLD)
1114 rst_flags |= AR_RTC_RC_MAC_COLD;
1117 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1119 REGWRITE_BUFFER_FLUSH(ah);
1123 REG_WRITE(ah, AR_RTC_RC, 0);
1124 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1126 "RTC stuck in MAC reset\n");
1130 if (!AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_RC, 0);
1133 if (AR_SREV_9100(ah))
1139 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1141 ENABLE_REGWRITE_BUFFER(ah);
1143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_WRITE(ah, AR_WA, ah->WARegVal);
1148 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1149 AR_RTC_FORCE_WAKE_ON_INT);
1151 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1152 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1154 REG_WRITE(ah, AR_RTC_RESET, 0);
1156 REGWRITE_BUFFER_FLUSH(ah);
1158 if (!AR_SREV_9300_20_OR_LATER(ah))
1161 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1162 REG_WRITE(ah, AR_RC, 0);
1164 REG_WRITE(ah, AR_RTC_RESET, 1);
1166 if (!ath9k_hw_wait(ah,
1171 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1172 "RTC not waking up\n");
1176 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1179 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1181 if (AR_SREV_9300_20_OR_LATER(ah)) {
1182 REG_WRITE(ah, AR_WA, ah->WARegVal);
1186 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1187 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1190 case ATH9K_RESET_POWER_ON:
1191 return ath9k_hw_set_reset_power_on(ah);
1192 case ATH9K_RESET_WARM:
1193 case ATH9K_RESET_COLD:
1194 return ath9k_hw_set_reset(ah, type);
1200 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1201 struct ath9k_channel *chan)
1203 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1204 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1206 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1209 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1212 ah->chip_fullsleep = false;
1213 ath9k_hw_init_pll(ah, chan);
1214 ath9k_hw_set_rfmode(ah, chan);
1219 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1220 struct ath9k_channel *chan)
1222 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1223 struct ath_common *common = ath9k_hw_common(ah);
1224 struct ieee80211_channel *channel = chan->chan;
1228 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1229 if (ath9k_hw_numtxpending(ah, qnum)) {
1230 ath_dbg(common, ATH_DBG_QUEUE,
1231 "Transmit frames pending on queue %d\n", qnum);
1236 if (!ath9k_hw_rfbus_req(ah)) {
1237 ath_err(common, "Could not kill baseband RX\n");
1241 ath9k_hw_set_channel_regs(ah, chan);
1243 r = ath9k_hw_rf_set_freq(ah, chan);
1245 ath_err(common, "Failed to set channel\n");
1248 ath9k_hw_set_clockrate(ah);
1250 ah->eep_ops->set_txpower(ah, chan,
1251 ath9k_regd_get_ctl(regulatory, chan),
1252 channel->max_antenna_gain * 2,
1253 channel->max_power * 2,
1254 min((u32) MAX_RATE_POWER,
1255 (u32) regulatory->power_limit), false);
1257 ath9k_hw_rfbus_done(ah);
1259 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1260 ath9k_hw_set_delta_slope(ah, chan);
1262 ath9k_hw_spur_mitigate_freq(ah, chan);
1267 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1269 u32 gpio_mask = ah->gpio_mask;
1272 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1273 if (!(gpio_mask & 1))
1276 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1277 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1281 bool ath9k_hw_check_alive(struct ath_hw *ah)
1286 if (AR_SREV_9285_12_OR_LATER(ah))
1290 reg = REG_READ(ah, AR_OBS_BUS_1);
1292 if ((reg & 0x7E7FFFEF) == 0x00702400)
1295 switch (reg & 0x7E000B00) {
1303 } while (count-- > 0);
1307 EXPORT_SYMBOL(ath9k_hw_check_alive);
1309 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1310 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1312 struct ath_common *common = ath9k_hw_common(ah);
1314 struct ath9k_channel *curchan = ah->curchan;
1320 ah->txchainmask = common->tx_chainmask;
1321 ah->rxchainmask = common->rx_chainmask;
1323 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
1324 ath9k_hw_abortpcurecv(ah);
1325 if (!ath9k_hw_stopdmarecv(ah)) {
1326 ath_dbg(common, ATH_DBG_XMIT,
1327 "Failed to stop receive dma\n");
1328 bChannelChange = false;
1332 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1335 if (curchan && !ah->chip_fullsleep)
1336 ath9k_hw_getnf(ah, curchan);
1338 ah->caldata = caldata;
1340 (chan->channel != caldata->channel ||
1341 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1342 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1343 /* Operating channel changed, reset channel calibration data */
1344 memset(caldata, 0, sizeof(*caldata));
1345 ath9k_init_nfcal_hist_buffer(ah, chan);
1348 if (bChannelChange &&
1349 (ah->chip_fullsleep != true) &&
1350 (ah->curchan != NULL) &&
1351 (chan->channel != ah->curchan->channel) &&
1352 ((chan->channelFlags & CHANNEL_ALL) ==
1353 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1354 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1356 if (ath9k_hw_channel_change(ah, chan)) {
1357 ath9k_hw_loadnf(ah, ah->curchan);
1358 ath9k_hw_start_nfcal(ah, true);
1359 if (AR_SREV_9271(ah))
1360 ar9002_hw_load_ani_reg(ah, chan);
1365 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1366 if (saveDefAntenna == 0)
1369 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1371 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1372 if (AR_SREV_9100(ah) ||
1373 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1374 tsf = ath9k_hw_gettsf64(ah);
1376 saveLedState = REG_READ(ah, AR_CFG_LED) &
1377 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1378 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1380 ath9k_hw_mark_phy_inactive(ah);
1382 ah->paprd_table_write_done = false;
1384 /* Only required on the first reset */
1385 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1387 AR9271_RESET_POWER_DOWN_CONTROL,
1388 AR9271_RADIO_RF_RST);
1392 if (!ath9k_hw_chip_reset(ah, chan)) {
1393 ath_err(common, "Chip reset failed\n");
1397 /* Only required on the first reset */
1398 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1399 ah->htc_reset_init = false;
1401 AR9271_RESET_POWER_DOWN_CONTROL,
1402 AR9271_GATE_MAC_CTL);
1408 ath9k_hw_settsf64(ah, tsf);
1410 if (AR_SREV_9280_20_OR_LATER(ah))
1411 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1413 if (!AR_SREV_9300_20_OR_LATER(ah))
1414 ar9002_hw_enable_async_fifo(ah);
1416 r = ath9k_hw_process_ini(ah, chan);
1421 * Some AR91xx SoC devices frequently fail to accept TSF writes
1422 * right after the chip reset. When that happens, write a new
1423 * value after the initvals have been applied, with an offset
1424 * based on measured time difference
1426 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1428 ath9k_hw_settsf64(ah, tsf);
1431 /* Setup MFP options for CCMP */
1432 if (AR_SREV_9280_20_OR_LATER(ah)) {
1433 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1434 * frames when constructing CCMP AAD. */
1435 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1437 ah->sw_mgmt_crypto = false;
1438 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1439 /* Disable hardware crypto for management frames */
1440 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1441 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1442 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1443 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1444 ah->sw_mgmt_crypto = true;
1446 ah->sw_mgmt_crypto = true;
1448 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1449 ath9k_hw_set_delta_slope(ah, chan);
1451 ath9k_hw_spur_mitigate_freq(ah, chan);
1452 ah->eep_ops->set_board_values(ah, chan);
1454 ENABLE_REGWRITE_BUFFER(ah);
1456 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1457 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1459 | AR_STA_ID1_RTS_USE_DEF
1461 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1462 | ah->sta_id1_defaults);
1463 ath_hw_setbssidmask(common);
1464 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1465 ath9k_hw_write_associd(ah);
1466 REG_WRITE(ah, AR_ISR, ~0);
1467 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1469 REGWRITE_BUFFER_FLUSH(ah);
1471 ath9k_hw_set_operating_mode(ah, ah->opmode);
1473 r = ath9k_hw_rf_set_freq(ah, chan);
1477 ath9k_hw_set_clockrate(ah);
1479 ENABLE_REGWRITE_BUFFER(ah);
1481 for (i = 0; i < AR_NUM_DCU; i++)
1482 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1484 REGWRITE_BUFFER_FLUSH(ah);
1487 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1488 ath9k_hw_resettxqueue(ah, i);
1490 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1491 ath9k_hw_ani_cache_ini_regs(ah);
1492 ath9k_hw_init_qos(ah);
1494 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1495 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1497 ath9k_hw_init_global_settings(ah);
1499 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1500 ar9002_hw_update_async_fifo(ah);
1501 ar9002_hw_enable_wep_aggregation(ah);
1504 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1506 ath9k_hw_set_dma(ah);
1508 REG_WRITE(ah, AR_OBS, 8);
1510 if (ah->config.rx_intr_mitigation) {
1511 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1512 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1515 if (ah->config.tx_intr_mitigation) {
1516 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1517 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1520 ath9k_hw_init_bb(ah, chan);
1522 if (!ath9k_hw_init_cal(ah, chan))
1525 ENABLE_REGWRITE_BUFFER(ah);
1527 ath9k_hw_restore_chainmask(ah);
1528 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1530 REGWRITE_BUFFER_FLUSH(ah);
1533 * For big endian systems turn on swapping for descriptors
1535 if (AR_SREV_9100(ah)) {
1537 mask = REG_READ(ah, AR_CFG);
1538 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1539 ath_dbg(common, ATH_DBG_RESET,
1540 "CFG Byte Swap Set 0x%x\n", mask);
1543 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1544 REG_WRITE(ah, AR_CFG, mask);
1545 ath_dbg(common, ATH_DBG_RESET,
1546 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1549 if (common->bus_ops->ath_bus_type == ATH_USB) {
1550 /* Configure AR9271 target WLAN */
1551 if (AR_SREV_9271(ah))
1552 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1554 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1557 else if (AR_SREV_9340(ah))
1558 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1560 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1564 if (ah->btcoex_hw.enabled)
1565 ath9k_hw_btcoex_enable(ah);
1567 if (AR_SREV_9300_20_OR_LATER(ah))
1568 ar9003_hw_bb_watchdog_config(ah);
1570 ath9k_hw_apply_gpio_override(ah);
1574 EXPORT_SYMBOL(ath9k_hw_reset);
1576 /******************************/
1577 /* Power Management (Chipset) */
1578 /******************************/
1581 * Notify Power Mgt is disabled in self-generated frames.
1582 * If requested, force chip to sleep.
1584 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1586 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1589 * Clear the RTC force wake bit to allow the
1590 * mac to go to sleep.
1592 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1593 AR_RTC_FORCE_WAKE_EN);
1594 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1595 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1597 /* Shutdown chip. Active low */
1598 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1599 REG_CLR_BIT(ah, (AR_RTC_RESET),
1603 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1604 if (AR_SREV_9300_20_OR_LATER(ah))
1605 REG_WRITE(ah, AR_WA,
1606 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1610 * Notify Power Management is enabled in self-generating
1611 * frames. If request, set power mode of chip to
1612 * auto/normal. Duration in units of 128us (1/8 TU).
1614 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1616 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1618 struct ath9k_hw_capabilities *pCap = &ah->caps;
1620 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1621 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1622 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1623 AR_RTC_FORCE_WAKE_ON_INT);
1626 * Clear the RTC force wake bit to allow the
1627 * mac to go to sleep.
1629 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1630 AR_RTC_FORCE_WAKE_EN);
1634 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1635 if (AR_SREV_9300_20_OR_LATER(ah))
1636 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1639 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1644 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1645 if (AR_SREV_9300_20_OR_LATER(ah)) {
1646 REG_WRITE(ah, AR_WA, ah->WARegVal);
1651 if ((REG_READ(ah, AR_RTC_STATUS) &
1652 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1653 if (ath9k_hw_set_reset_reg(ah,
1654 ATH9K_RESET_POWER_ON) != true) {
1657 if (!AR_SREV_9300_20_OR_LATER(ah))
1658 ath9k_hw_init_pll(ah, NULL);
1660 if (AR_SREV_9100(ah))
1661 REG_SET_BIT(ah, AR_RTC_RESET,
1664 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1665 AR_RTC_FORCE_WAKE_EN);
1668 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1669 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1670 if (val == AR_RTC_STATUS_ON)
1673 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1674 AR_RTC_FORCE_WAKE_EN);
1677 ath_err(ath9k_hw_common(ah),
1678 "Failed to wakeup in %uus\n",
1679 POWER_UP_TIME / 20);
1684 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1689 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1691 struct ath_common *common = ath9k_hw_common(ah);
1692 int status = true, setChip = true;
1693 static const char *modes[] = {
1700 if (ah->power_mode == mode)
1703 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1704 modes[ah->power_mode], modes[mode]);
1707 case ATH9K_PM_AWAKE:
1708 status = ath9k_hw_set_power_awake(ah, setChip);
1710 case ATH9K_PM_FULL_SLEEP:
1711 ath9k_set_power_sleep(ah, setChip);
1712 ah->chip_fullsleep = true;
1714 case ATH9K_PM_NETWORK_SLEEP:
1715 ath9k_set_power_network_sleep(ah, setChip);
1718 ath_err(common, "Unknown power mode %u\n", mode);
1721 ah->power_mode = mode;
1724 * XXX: If this warning never comes up after a while then
1725 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1726 * ath9k_hw_setpower() return type void.
1729 if (!(ah->ah_flags & AH_UNPLUGGED))
1730 ATH_DBG_WARN_ON_ONCE(!status);
1734 EXPORT_SYMBOL(ath9k_hw_setpower);
1736 /*******************/
1737 /* Beacon Handling */
1738 /*******************/
1740 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1744 ENABLE_REGWRITE_BUFFER(ah);
1746 switch (ah->opmode) {
1747 case NL80211_IFTYPE_ADHOC:
1748 case NL80211_IFTYPE_MESH_POINT:
1749 REG_SET_BIT(ah, AR_TXCFG,
1750 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1751 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1752 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1753 flags |= AR_NDP_TIMER_EN;
1754 case NL80211_IFTYPE_AP:
1755 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1756 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1757 TU_TO_USEC(ah->config.dma_beacon_response_time));
1758 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1759 TU_TO_USEC(ah->config.sw_beacon_response_time));
1761 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1764 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1765 "%s: unsupported opmode: %d\n",
1766 __func__, ah->opmode);
1771 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1772 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1773 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1774 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1776 REGWRITE_BUFFER_FLUSH(ah);
1778 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1780 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1782 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1783 const struct ath9k_beacon_state *bs)
1785 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1786 struct ath9k_hw_capabilities *pCap = &ah->caps;
1787 struct ath_common *common = ath9k_hw_common(ah);
1789 ENABLE_REGWRITE_BUFFER(ah);
1791 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1793 REG_WRITE(ah, AR_BEACON_PERIOD,
1794 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1795 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1796 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1798 REGWRITE_BUFFER_FLUSH(ah);
1800 REG_RMW_FIELD(ah, AR_RSSI_THR,
1801 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1803 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1805 if (bs->bs_sleepduration > beaconintval)
1806 beaconintval = bs->bs_sleepduration;
1808 dtimperiod = bs->bs_dtimperiod;
1809 if (bs->bs_sleepduration > dtimperiod)
1810 dtimperiod = bs->bs_sleepduration;
1812 if (beaconintval == dtimperiod)
1813 nextTbtt = bs->bs_nextdtim;
1815 nextTbtt = bs->bs_nexttbtt;
1817 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1818 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1819 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1820 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1822 ENABLE_REGWRITE_BUFFER(ah);
1824 REG_WRITE(ah, AR_NEXT_DTIM,
1825 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1826 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1828 REG_WRITE(ah, AR_SLEEP1,
1829 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1830 | AR_SLEEP1_ASSUME_DTIM);
1832 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1833 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1835 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1837 REG_WRITE(ah, AR_SLEEP2,
1838 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1840 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1841 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1843 REGWRITE_BUFFER_FLUSH(ah);
1845 REG_SET_BIT(ah, AR_TIMER_MODE,
1846 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1849 /* TSF Out of Range Threshold */
1850 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1852 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1854 /*******************/
1855 /* HW Capabilities */
1856 /*******************/
1858 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1860 struct ath9k_hw_capabilities *pCap = &ah->caps;
1861 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1862 struct ath_common *common = ath9k_hw_common(ah);
1863 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1866 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1868 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1869 regulatory->current_rd = eeval;
1871 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1872 if (AR_SREV_9285_12_OR_LATER(ah))
1873 eeval |= AR9285_RDEXT_DEFAULT;
1874 regulatory->current_rd_ext = eeval;
1876 if (ah->opmode != NL80211_IFTYPE_AP &&
1877 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1878 if (regulatory->current_rd == 0x64 ||
1879 regulatory->current_rd == 0x65)
1880 regulatory->current_rd += 5;
1881 else if (regulatory->current_rd == 0x41)
1882 regulatory->current_rd = 0x43;
1883 ath_dbg(common, ATH_DBG_REGULATORY,
1884 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1887 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1888 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1890 "no band has been marked as supported in EEPROM\n");
1894 if (eeval & AR5416_OPFLAGS_11A)
1895 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1897 if (eeval & AR5416_OPFLAGS_11G)
1898 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1900 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1902 * For AR9271 we will temporarilly uses the rx chainmax as read from
1905 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1906 !(eeval & AR5416_OPFLAGS_11A) &&
1907 !(AR_SREV_9271(ah)))
1908 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1909 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1910 else if (AR_SREV_9100(ah))
1911 pCap->rx_chainmask = 0x7;
1913 /* Use rx_chainmask from EEPROM. */
1914 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1916 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1918 /* enable key search for every frame in an aggregate */
1919 if (AR_SREV_9300_20_OR_LATER(ah))
1920 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1922 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1924 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
1925 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1927 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1929 if (AR_SREV_9271(ah))
1930 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1931 else if (AR_DEVID_7010(ah))
1932 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1933 else if (AR_SREV_9285_12_OR_LATER(ah))
1934 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1935 else if (AR_SREV_9280_20_OR_LATER(ah))
1936 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1938 pCap->num_gpio_pins = AR_NUM_GPIO;
1940 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1941 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1942 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1944 pCap->rts_aggr_limit = (8 * 1024);
1947 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1948 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1949 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1951 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1952 ah->rfkill_polarity =
1953 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1955 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1958 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1959 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1961 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1963 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1964 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1966 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1968 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1969 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1970 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1972 if (AR_SREV_9285(ah)) {
1973 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1974 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1976 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1979 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1982 if (AR_SREV_9300_20_OR_LATER(ah)) {
1983 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1984 if (!AR_SREV_9485(ah))
1985 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1987 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1988 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1989 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1990 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1991 pCap->txs_len = sizeof(struct ar9003_txs);
1992 if (!ah->config.paprd_disable &&
1993 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1994 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1996 pCap->tx_desc_len = sizeof(struct ath_desc);
1997 if (AR_SREV_9280_20(ah) &&
1998 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1999 AR5416_EEP_MINOR_VER_16) ||
2000 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2001 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2004 if (AR_SREV_9300_20_OR_LATER(ah))
2005 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2007 if (AR_SREV_9300_20_OR_LATER(ah))
2008 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2010 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2011 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2013 if (AR_SREV_9285(ah))
2014 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2016 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2017 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2018 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2020 if (AR_SREV_9300_20_OR_LATER(ah)) {
2021 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2022 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2027 if (AR_SREV_9485_10(ah)) {
2028 pCap->pcie_lcr_extsync_en = true;
2029 pCap->pcie_lcr_offset = 0x80;
2032 tx_chainmask = pCap->tx_chainmask;
2033 rx_chainmask = pCap->rx_chainmask;
2034 while (tx_chainmask || rx_chainmask) {
2035 if (tx_chainmask & BIT(0))
2036 pCap->max_txchains++;
2037 if (rx_chainmask & BIT(0))
2038 pCap->max_rxchains++;
2047 /****************************/
2048 /* GPIO / RFKILL / Antennae */
2049 /****************************/
2051 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2055 u32 gpio_shift, tmp;
2058 addr = AR_GPIO_OUTPUT_MUX3;
2060 addr = AR_GPIO_OUTPUT_MUX2;
2062 addr = AR_GPIO_OUTPUT_MUX1;
2064 gpio_shift = (gpio % 6) * 5;
2066 if (AR_SREV_9280_20_OR_LATER(ah)
2067 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2068 REG_RMW(ah, addr, (type << gpio_shift),
2069 (0x1f << gpio_shift));
2071 tmp = REG_READ(ah, addr);
2072 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2073 tmp &= ~(0x1f << gpio_shift);
2074 tmp |= (type << gpio_shift);
2075 REG_WRITE(ah, addr, tmp);
2079 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2083 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2085 if (AR_DEVID_7010(ah)) {
2087 REG_RMW(ah, AR7010_GPIO_OE,
2088 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2089 (AR7010_GPIO_OE_MASK << gpio_shift));
2093 gpio_shift = gpio << 1;
2096 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2097 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2099 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2101 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2103 #define MS_REG_READ(x, y) \
2104 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2106 if (gpio >= ah->caps.num_gpio_pins)
2109 if (AR_DEVID_7010(ah)) {
2111 val = REG_READ(ah, AR7010_GPIO_IN);
2112 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2113 } else if (AR_SREV_9300_20_OR_LATER(ah))
2114 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2115 AR_GPIO_BIT(gpio)) != 0;
2116 else if (AR_SREV_9271(ah))
2117 return MS_REG_READ(AR9271, gpio) != 0;
2118 else if (AR_SREV_9287_11_OR_LATER(ah))
2119 return MS_REG_READ(AR9287, gpio) != 0;
2120 else if (AR_SREV_9285_12_OR_LATER(ah))
2121 return MS_REG_READ(AR9285, gpio) != 0;
2122 else if (AR_SREV_9280_20_OR_LATER(ah))
2123 return MS_REG_READ(AR928X, gpio) != 0;
2125 return MS_REG_READ(AR, gpio) != 0;
2127 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2129 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2134 if (AR_DEVID_7010(ah)) {
2136 REG_RMW(ah, AR7010_GPIO_OE,
2137 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2138 (AR7010_GPIO_OE_MASK << gpio_shift));
2142 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2143 gpio_shift = 2 * gpio;
2146 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2147 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2149 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2151 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2153 if (AR_DEVID_7010(ah)) {
2155 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2160 if (AR_SREV_9271(ah))
2163 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2166 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2168 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2170 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2172 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2174 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2176 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2178 EXPORT_SYMBOL(ath9k_hw_setantenna);
2180 /*********************/
2181 /* General Operation */
2182 /*********************/
2184 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2186 u32 bits = REG_READ(ah, AR_RX_FILTER);
2187 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2189 if (phybits & AR_PHY_ERR_RADAR)
2190 bits |= ATH9K_RX_FILTER_PHYRADAR;
2191 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2192 bits |= ATH9K_RX_FILTER_PHYERR;
2196 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2198 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2202 ENABLE_REGWRITE_BUFFER(ah);
2204 REG_WRITE(ah, AR_RX_FILTER, bits);
2207 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2208 phybits |= AR_PHY_ERR_RADAR;
2209 if (bits & ATH9K_RX_FILTER_PHYERR)
2210 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2211 REG_WRITE(ah, AR_PHY_ERR, phybits);
2214 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2216 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2218 REGWRITE_BUFFER_FLUSH(ah);
2220 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2222 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2224 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2227 ath9k_hw_init_pll(ah, NULL);
2230 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2232 bool ath9k_hw_disable(struct ath_hw *ah)
2234 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2237 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2240 ath9k_hw_init_pll(ah, NULL);
2243 EXPORT_SYMBOL(ath9k_hw_disable);
2245 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2247 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2248 struct ath9k_channel *chan = ah->curchan;
2249 struct ieee80211_channel *channel = chan->chan;
2251 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2253 ah->eep_ops->set_txpower(ah, chan,
2254 ath9k_regd_get_ctl(regulatory, chan),
2255 channel->max_antenna_gain * 2,
2256 channel->max_power * 2,
2257 min((u32) MAX_RATE_POWER,
2258 (u32) regulatory->power_limit), test);
2260 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2262 void ath9k_hw_setopmode(struct ath_hw *ah)
2264 ath9k_hw_set_operating_mode(ah, ah->opmode);
2266 EXPORT_SYMBOL(ath9k_hw_setopmode);
2268 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2270 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2271 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2273 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2275 void ath9k_hw_write_associd(struct ath_hw *ah)
2277 struct ath_common *common = ath9k_hw_common(ah);
2279 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2280 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2281 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2283 EXPORT_SYMBOL(ath9k_hw_write_associd);
2285 #define ATH9K_MAX_TSF_READ 10
2287 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2289 u32 tsf_lower, tsf_upper1, tsf_upper2;
2292 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2293 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2294 tsf_lower = REG_READ(ah, AR_TSF_L32);
2295 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2296 if (tsf_upper2 == tsf_upper1)
2298 tsf_upper1 = tsf_upper2;
2301 WARN_ON( i == ATH9K_MAX_TSF_READ );
2303 return (((u64)tsf_upper1 << 32) | tsf_lower);
2305 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2307 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2309 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2310 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2312 EXPORT_SYMBOL(ath9k_hw_settsf64);
2314 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2316 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2317 AH_TSF_WRITE_TIMEOUT))
2318 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2319 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2321 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2323 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2325 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2328 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2330 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2332 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2334 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2336 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2339 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2340 macmode = AR_2040_JOINED_RX_CLEAR;
2344 REG_WRITE(ah, AR_2040_MODE, macmode);
2347 /* HW Generic timers configuration */
2349 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2351 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2352 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2353 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2354 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2355 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2356 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2357 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2358 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2359 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2360 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2361 AR_NDP2_TIMER_MODE, 0x0002},
2362 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2363 AR_NDP2_TIMER_MODE, 0x0004},
2364 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2365 AR_NDP2_TIMER_MODE, 0x0008},
2366 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2367 AR_NDP2_TIMER_MODE, 0x0010},
2368 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2369 AR_NDP2_TIMER_MODE, 0x0020},
2370 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2371 AR_NDP2_TIMER_MODE, 0x0040},
2372 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2373 AR_NDP2_TIMER_MODE, 0x0080}
2376 /* HW generic timer primitives */
2378 /* compute and clear index of rightmost 1 */
2379 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2389 return timer_table->gen_timer_index[b];
2392 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2394 return REG_READ(ah, AR_TSF_L32);
2396 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2398 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2399 void (*trigger)(void *),
2400 void (*overflow)(void *),
2404 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2405 struct ath_gen_timer *timer;
2407 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2409 if (timer == NULL) {
2410 ath_err(ath9k_hw_common(ah),
2411 "Failed to allocate memory for hw timer[%d]\n",
2416 /* allocate a hardware generic timer slot */
2417 timer_table->timers[timer_index] = timer;
2418 timer->index = timer_index;
2419 timer->trigger = trigger;
2420 timer->overflow = overflow;
2425 EXPORT_SYMBOL(ath_gen_timer_alloc);
2427 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2428 struct ath_gen_timer *timer,
2432 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2433 u32 tsf, timer_next;
2435 BUG_ON(!timer_period);
2437 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2439 tsf = ath9k_hw_gettsf32(ah);
2441 timer_next = tsf + trig_timeout;
2443 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2444 "current tsf %x period %x timer_next %x\n",
2445 tsf, timer_period, timer_next);
2448 * Program generic timer registers
2450 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2452 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2454 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2455 gen_tmr_configuration[timer->index].mode_mask);
2457 /* Enable both trigger and thresh interrupt masks */
2458 REG_SET_BIT(ah, AR_IMR_S5,
2459 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2460 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2462 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2464 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2466 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2468 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2469 (timer->index >= ATH_MAX_GEN_TIMER)) {
2473 /* Clear generic timer enable bits. */
2474 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2475 gen_tmr_configuration[timer->index].mode_mask);
2477 /* Disable both trigger and thresh interrupt masks */
2478 REG_CLR_BIT(ah, AR_IMR_S5,
2479 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2480 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2482 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2484 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2486 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2488 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2490 /* free the hardware generic timer slot */
2491 timer_table->timers[timer->index] = NULL;
2494 EXPORT_SYMBOL(ath_gen_timer_free);
2497 * Generic Timer Interrupts handling
2499 void ath_gen_timer_isr(struct ath_hw *ah)
2501 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2502 struct ath_gen_timer *timer;
2503 struct ath_common *common = ath9k_hw_common(ah);
2504 u32 trigger_mask, thresh_mask, index;
2506 /* get hardware generic timer interrupt status */
2507 trigger_mask = ah->intr_gen_timer_trigger;
2508 thresh_mask = ah->intr_gen_timer_thresh;
2509 trigger_mask &= timer_table->timer_mask.val;
2510 thresh_mask &= timer_table->timer_mask.val;
2512 trigger_mask &= ~thresh_mask;
2514 while (thresh_mask) {
2515 index = rightmost_index(timer_table, &thresh_mask);
2516 timer = timer_table->timers[index];
2518 ath_dbg(common, ATH_DBG_HWTIMER,
2519 "TSF overflow for Gen timer %d\n", index);
2520 timer->overflow(timer->arg);
2523 while (trigger_mask) {
2524 index = rightmost_index(timer_table, &trigger_mask);
2525 timer = timer_table->timers[index];
2527 ath_dbg(common, ATH_DBG_HWTIMER,
2528 "Gen timer[%d] trigger\n", index);
2529 timer->trigger(timer->arg);
2532 EXPORT_SYMBOL(ath_gen_timer_isr);
2538 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2540 ah->htc_reset_init = true;
2542 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2547 } ath_mac_bb_names[] = {
2548 /* Devices with external radios */
2549 { AR_SREV_VERSION_5416_PCI, "5416" },
2550 { AR_SREV_VERSION_5416_PCIE, "5418" },
2551 { AR_SREV_VERSION_9100, "9100" },
2552 { AR_SREV_VERSION_9160, "9160" },
2553 /* Single-chip solutions */
2554 { AR_SREV_VERSION_9280, "9280" },
2555 { AR_SREV_VERSION_9285, "9285" },
2556 { AR_SREV_VERSION_9287, "9287" },
2557 { AR_SREV_VERSION_9271, "9271" },
2558 { AR_SREV_VERSION_9300, "9300" },
2559 { AR_SREV_VERSION_9485, "9485" },
2562 /* For devices with external radios */
2566 } ath_rf_names[] = {
2568 { AR_RAD5133_SREV_MAJOR, "5133" },
2569 { AR_RAD5122_SREV_MAJOR, "5122" },
2570 { AR_RAD2133_SREV_MAJOR, "2133" },
2571 { AR_RAD2122_SREV_MAJOR, "2122" }
2575 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2577 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2581 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2582 if (ath_mac_bb_names[i].version == mac_bb_version) {
2583 return ath_mac_bb_names[i].name;
2591 * Return the RF name. "????" is returned if the RF is unknown.
2592 * Used for devices with external radios.
2594 static const char *ath9k_hw_rf_name(u16 rf_version)
2598 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2599 if (ath_rf_names[i].version == rf_version) {
2600 return ath_rf_names[i].name;
2607 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2611 /* chipsets >= AR9280 are single-chip */
2612 if (AR_SREV_9280_20_OR_LATER(ah)) {
2613 used = snprintf(hw_name, len,
2614 "Atheros AR%s Rev:%x",
2615 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2616 ah->hw_version.macRev);
2619 used = snprintf(hw_name, len,
2620 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2621 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2622 ah->hw_version.macRev,
2623 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2624 AR_RADIO_SREV_MAJOR)),
2625 ah->hw_version.phyRev);
2628 hw_name[used] = '\0';
2630 EXPORT_SYMBOL(ath9k_hw_name);