2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
40 /********************/
41 /* Helper Functions */
42 /********************/
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
63 return ath9k_hw_mac_usec(ah, clks);
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
84 return ath9k_hw_mac_clks(ah, usecs);
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
115 val = ioread32(ah->ah_sc->mem + reg_offset);
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 BUG_ON(timeout < AH_TIME_QUANTUM);
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
129 udelay(AH_TIME_QUANTUM);
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
178 kbps = rates->info[rateix].ratekbps;
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
296 return ath9k_hw_reverse_bits(val, 8);
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
305 if (AR_SREV_9100(ah))
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
325 u32 patternData[4] = { 0x55555555,
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
360 REG_WRITE(ah, regAddr[i], regHold[i]);
367 static const char *ath9k_hw_devname(u16 devid)
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 case AR5416_DEVID_AR9287_PCI:
384 case AR5416_DEVID_AR9287_PCIE:
385 return "Atheros 9287";
391 static void ath9k_hw_init_config(struct ath_hw *ah)
395 ah->config.dma_beacon_response_time = 2;
396 ah->config.sw_beacon_response_time = 10;
397 ah->config.additional_swba_backoff = 0;
398 ah->config.ack_6mb = 0x0;
399 ah->config.cwm_ignore_extcca = 0;
400 ah->config.pcie_powersave_enable = 0;
401 ah->config.pcie_clock_req = 0;
402 ah->config.pcie_waen = 0;
403 ah->config.analog_shiftreg = 1;
404 ah->config.ht_enable = 1;
405 ah->config.ofdm_trig_low = 200;
406 ah->config.ofdm_trig_high = 500;
407 ah->config.cck_trig_high = 200;
408 ah->config.cck_trig_low = 100;
409 ah->config.enable_ani = 1;
410 ah->config.diversity_control = 0;
411 ah->config.antenna_switch_swap = 0;
413 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
414 ah->config.spurchans[i][0] = AR_NO_SPUR;
415 ah->config.spurchans[i][1] = AR_NO_SPUR;
418 ah->config.intr_mitigation = true;
421 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423 * This means we use it for all AR5416 devices, and the few
424 * minor PCI AR9280 devices out there.
426 * Serialization is required because these devices do not handle
427 * well the case of two concurrent reads/writes due to the latency
428 * involved. During one read/write another read/write can be issued
429 * on another CPU while the previous read/write may still be working
430 * on our hardware, if we hit this case the hardware poops in a loop.
431 * We prevent this by serializing reads and writes.
433 * This issue is not present on PCI-Express devices or pre-AR5416
434 * devices (legacy, 802.11abg).
436 if (num_possible_cpus() > 1)
437 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
442 ah->hw_version.magic = AR5416_MAGIC;
443 ah->regulatory.country_code = CTRY_DEFAULT;
444 ah->hw_version.subvendorid = 0;
447 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
448 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
449 if (!AR_SREV_9100(ah))
450 ah->ah_flags = AH_USE_EEPROM;
452 ah->regulatory.power_limit = MAX_RATE_POWER;
453 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
455 ah->diversity_control = ah->config.diversity_control;
456 ah->antenna_switch_swap =
457 ah->config.antenna_switch_swap;
458 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
459 ah->beacon_interval = 100;
460 ah->enable_32kHz_clock = DONT_USE_32KHZ;
461 ah->slottime = (u32) -1;
462 ah->acktimeout = (u32) -1;
463 ah->ctstimeout = (u32) -1;
464 ah->globaltxtimeout = (u32) -1;
466 ah->gbeacon_rate = 0;
468 ah->power_mode = ATH9K_PM_UNDEFINED;
471 static int ath9k_hw_rfattach(struct ath_hw *ah)
473 bool rfStatus = false;
476 rfStatus = ath9k_hw_init_rf(ah, &ecode);
478 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
479 "RF setup failed, status: %u\n", ecode);
486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
490 REG_WRITE(ah, AR_PHY(0), 0x00000007);
492 val = ath9k_hw_get_radiorev(ah);
493 switch (val & AR_RADIO_SREV_MAJOR) {
495 val = AR_RAD5133_SREV_MAJOR;
497 case AR_RAD5133_SREV_MAJOR:
498 case AR_RAD5122_SREV_MAJOR:
499 case AR_RAD2133_SREV_MAJOR:
500 case AR_RAD2122_SREV_MAJOR:
503 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
504 "Radio Chip Rev 0x%02X not supported\n",
505 val & AR_RADIO_SREV_MAJOR);
509 ah->hw_version.analog5GhzRev = val;
514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
521 for (i = 0; i < 3; i++) {
522 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
524 ah->macaddr[2 * i] = eeval >> 8;
525 ah->macaddr[2 * i + 1] = eeval & 0xff;
527 if (sum == 0 || sum == 0xffff * 3)
528 return -EADDRNOTAVAIL;
533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
537 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
538 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
540 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
541 INIT_INI_ARRAY(&ah->iniModesRxGain,
542 ar9280Modes_backoff_13db_rxgain_9280_2,
543 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
544 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
545 INIT_INI_ARRAY(&ah->iniModesRxGain,
546 ar9280Modes_backoff_23db_rxgain_9280_2,
547 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
549 INIT_INI_ARRAY(&ah->iniModesRxGain,
550 ar9280Modes_original_rxgain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
553 INIT_INI_ARRAY(&ah->iniModesRxGain,
554 ar9280Modes_original_rxgain_9280_2,
555 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
563 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
564 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
566 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
567 INIT_INI_ARRAY(&ah->iniModesTxGain,
568 ar9280Modes_high_power_tx_gain_9280_2,
569 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
571 INIT_INI_ARRAY(&ah->iniModesTxGain,
572 ar9280Modes_original_tx_gain_9280_2,
573 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
575 INIT_INI_ARRAY(&ah->iniModesTxGain,
576 ar9280Modes_original_tx_gain_9280_2,
577 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
581 static int ath9k_hw_post_init(struct ath_hw *ah)
585 if (!ath9k_hw_chip_test(ah))
588 ecode = ath9k_hw_rf_claim(ah);
592 ecode = ath9k_hw_eeprom_init(ah);
596 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
597 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
599 ecode = ath9k_hw_rfattach(ah);
603 if (!AR_SREV_9100(ah)) {
604 ath9k_hw_ani_setup(ah);
605 ath9k_hw_ani_init(ah);
611 static bool ath9k_hw_devid_supported(u16 devid)
614 case AR5416_DEVID_PCI:
615 case AR5416_DEVID_PCIE:
616 case AR5416_AR9100_DEVID:
617 case AR9160_DEVID_PCI:
618 case AR9280_DEVID_PCI:
619 case AR9280_DEVID_PCIE:
620 case AR9285_DEVID_PCIE:
621 case AR5416_DEVID_AR9287_PCI:
622 case AR5416_DEVID_AR9287_PCIE:
630 static bool ath9k_hw_macversion_supported(u32 macversion)
632 switch (macversion) {
633 case AR_SREV_VERSION_5416_PCI:
634 case AR_SREV_VERSION_5416_PCIE:
635 case AR_SREV_VERSION_9160:
636 case AR_SREV_VERSION_9100:
637 case AR_SREV_VERSION_9280:
638 case AR_SREV_VERSION_9285:
639 case AR_SREV_VERSION_9287:
647 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
649 if (AR_SREV_9160_10_OR_LATER(ah)) {
650 if (AR_SREV_9280_10_OR_LATER(ah)) {
651 ah->iq_caldata.calData = &iq_cal_single_sample;
652 ah->adcgain_caldata.calData =
653 &adc_gain_cal_single_sample;
654 ah->adcdc_caldata.calData =
655 &adc_dc_cal_single_sample;
656 ah->adcdc_calinitdata.calData =
659 ah->iq_caldata.calData = &iq_cal_multi_sample;
660 ah->adcgain_caldata.calData =
661 &adc_gain_cal_multi_sample;
662 ah->adcdc_caldata.calData =
663 &adc_dc_cal_multi_sample;
664 ah->adcdc_calinitdata.calData =
667 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
671 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
673 if (AR_SREV_9287_11_OR_LATER(ah)) {
674 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
675 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
676 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
677 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
678 if (ah->config.pcie_clock_req)
679 INIT_INI_ARRAY(&ah->iniPcieSerdes,
680 ar9287PciePhy_clkreq_off_L1_9287_1_1,
681 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
683 INIT_INI_ARRAY(&ah->iniPcieSerdes,
684 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
685 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
687 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
688 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
689 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
690 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
691 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
693 if (ah->config.pcie_clock_req)
694 INIT_INI_ARRAY(&ah->iniPcieSerdes,
695 ar9287PciePhy_clkreq_off_L1_9287_1_0,
696 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
698 INIT_INI_ARRAY(&ah->iniPcieSerdes,
699 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
700 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
702 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
705 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
706 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
707 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
708 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
710 if (ah->config.pcie_clock_req) {
711 INIT_INI_ARRAY(&ah->iniPcieSerdes,
712 ar9285PciePhy_clkreq_off_L1_9285_1_2,
713 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
715 INIT_INI_ARRAY(&ah->iniPcieSerdes,
716 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
717 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
720 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
721 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
722 ARRAY_SIZE(ar9285Modes_9285), 6);
723 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
724 ARRAY_SIZE(ar9285Common_9285), 2);
726 if (ah->config.pcie_clock_req) {
727 INIT_INI_ARRAY(&ah->iniPcieSerdes,
728 ar9285PciePhy_clkreq_off_L1_9285,
729 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
731 INIT_INI_ARRAY(&ah->iniPcieSerdes,
732 ar9285PciePhy_clkreq_always_on_L1_9285,
733 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
735 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
736 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
737 ARRAY_SIZE(ar9280Modes_9280_2), 6);
738 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
739 ARRAY_SIZE(ar9280Common_9280_2), 2);
741 if (ah->config.pcie_clock_req) {
742 INIT_INI_ARRAY(&ah->iniPcieSerdes,
743 ar9280PciePhy_clkreq_off_L1_9280,
744 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
746 INIT_INI_ARRAY(&ah->iniPcieSerdes,
747 ar9280PciePhy_clkreq_always_on_L1_9280,
748 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
750 INIT_INI_ARRAY(&ah->iniModesAdditional,
751 ar9280Modes_fast_clock_9280_2,
752 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
753 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
754 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
755 ARRAY_SIZE(ar9280Modes_9280), 6);
756 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
757 ARRAY_SIZE(ar9280Common_9280), 2);
758 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
759 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
760 ARRAY_SIZE(ar5416Modes_9160), 6);
761 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
762 ARRAY_SIZE(ar5416Common_9160), 2);
763 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
764 ARRAY_SIZE(ar5416Bank0_9160), 2);
765 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
766 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
767 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
768 ARRAY_SIZE(ar5416Bank1_9160), 2);
769 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
770 ARRAY_SIZE(ar5416Bank2_9160), 2);
771 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
772 ARRAY_SIZE(ar5416Bank3_9160), 3);
773 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
774 ARRAY_SIZE(ar5416Bank6_9160), 3);
775 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
776 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
777 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
778 ARRAY_SIZE(ar5416Bank7_9160), 2);
779 if (AR_SREV_9160_11(ah)) {
780 INIT_INI_ARRAY(&ah->iniAddac,
782 ARRAY_SIZE(ar5416Addac_91601_1), 2);
784 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
785 ARRAY_SIZE(ar5416Addac_9160), 2);
787 } else if (AR_SREV_9100_OR_LATER(ah)) {
788 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
789 ARRAY_SIZE(ar5416Modes_9100), 6);
790 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
791 ARRAY_SIZE(ar5416Common_9100), 2);
792 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
793 ARRAY_SIZE(ar5416Bank0_9100), 2);
794 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
795 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
796 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
797 ARRAY_SIZE(ar5416Bank1_9100), 2);
798 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
799 ARRAY_SIZE(ar5416Bank2_9100), 2);
800 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
801 ARRAY_SIZE(ar5416Bank3_9100), 3);
802 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
803 ARRAY_SIZE(ar5416Bank6_9100), 3);
804 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
805 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
806 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
807 ARRAY_SIZE(ar5416Bank7_9100), 2);
808 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
809 ARRAY_SIZE(ar5416Addac_9100), 2);
811 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
812 ARRAY_SIZE(ar5416Modes), 6);
813 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
814 ARRAY_SIZE(ar5416Common), 2);
815 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
816 ARRAY_SIZE(ar5416Bank0), 2);
817 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
818 ARRAY_SIZE(ar5416BB_RfGain), 3);
819 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
820 ARRAY_SIZE(ar5416Bank1), 2);
821 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
822 ARRAY_SIZE(ar5416Bank2), 2);
823 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
824 ARRAY_SIZE(ar5416Bank3), 3);
825 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
826 ARRAY_SIZE(ar5416Bank6), 3);
827 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
828 ARRAY_SIZE(ar5416Bank6TPC), 3);
829 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
830 ARRAY_SIZE(ar5416Bank7), 2);
831 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
832 ARRAY_SIZE(ar5416Addac), 2);
836 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
838 if (AR_SREV_9287_11(ah))
839 INIT_INI_ARRAY(&ah->iniModesRxGain,
840 ar9287Modes_rx_gain_9287_1_1,
841 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
842 else if (AR_SREV_9287_10(ah))
843 INIT_INI_ARRAY(&ah->iniModesRxGain,
844 ar9287Modes_rx_gain_9287_1_0,
845 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
846 else if (AR_SREV_9280_20(ah))
847 ath9k_hw_init_rxgain_ini(ah);
849 if (AR_SREV_9287_11(ah)) {
850 INIT_INI_ARRAY(&ah->iniModesTxGain,
851 ar9287Modes_tx_gain_9287_1_1,
852 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
853 } else if (AR_SREV_9287_10(ah)) {
854 INIT_INI_ARRAY(&ah->iniModesTxGain,
855 ar9287Modes_tx_gain_9287_1_0,
856 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
857 } else if (AR_SREV_9280_20(ah)) {
858 ath9k_hw_init_txgain_ini(ah);
859 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
860 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
863 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
864 INIT_INI_ARRAY(&ah->iniModesTxGain,
865 ar9285Modes_high_power_tx_gain_9285_1_2,
866 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
868 INIT_INI_ARRAY(&ah->iniModesTxGain,
869 ar9285Modes_original_tx_gain_9285_1_2,
870 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
876 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
880 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
881 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
884 for (i = 0; i < ah->iniModes.ia_rows; i++) {
885 u32 reg = INI_RA(&ah->iniModes, i, 0);
887 for (j = 1; j < ah->iniModes.ia_columns; j++) {
888 u32 val = INI_RA(&ah->iniModes, i, j);
890 INI_RA(&ah->iniModes, i, j) =
891 ath9k_hw_ini_fixup(ah,
899 int ath9k_hw_init(struct ath_hw *ah)
903 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
906 ath9k_hw_init_defaults(ah);
907 ath9k_hw_init_config(ah);
909 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
910 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
914 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
915 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
919 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
920 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
921 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
922 ah->config.serialize_regmode =
925 ah->config.serialize_regmode =
930 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
931 ah->config.serialize_regmode);
933 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
934 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
935 "Mac Chip Rev 0x%02x.%x is not supported by "
936 "this driver\n", ah->hw_version.macVersion,
937 ah->hw_version.macRev);
941 if (AR_SREV_9100(ah)) {
942 ah->iq_caldata.calData = &iq_cal_multi_sample;
943 ah->supp_cals = IQ_MISMATCH_CAL;
944 ah->is_pciexpress = false;
946 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
948 ath9k_hw_init_cal_settings(ah);
950 ah->ani_function = ATH9K_ANI_ALL;
951 if (AR_SREV_9280_10_OR_LATER(ah))
952 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
954 ath9k_hw_init_mode_regs(ah);
956 if (ah->is_pciexpress)
957 ath9k_hw_configpcipowersave(ah, 0);
959 ath9k_hw_disablepcie(ah);
961 r = ath9k_hw_post_init(ah);
965 ath9k_hw_init_mode_gain_regs(ah);
966 ath9k_hw_fill_cap_info(ah);
967 ath9k_hw_init_11a_eeprom_fix(ah);
969 r = ath9k_hw_init_macaddr(ah);
971 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
972 "Failed to initialize MAC address\n");
976 if (AR_SREV_9285(ah))
977 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
979 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
981 ath9k_init_nfcal_hist_buffer(ah);
986 static void ath9k_hw_init_bb(struct ath_hw *ah,
987 struct ath9k_channel *chan)
991 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
993 synthDelay = (4 * synthDelay) / 22;
997 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
999 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1002 static void ath9k_hw_init_qos(struct ath_hw *ah)
1004 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1005 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1007 REG_WRITE(ah, AR_QOS_NO_ACK,
1008 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1009 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1010 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1012 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1013 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1014 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1015 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1016 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1019 static void ath9k_hw_init_pll(struct ath_hw *ah,
1020 struct ath9k_channel *chan)
1024 if (AR_SREV_9100(ah)) {
1025 if (chan && IS_CHAN_5GHZ(chan))
1030 if (AR_SREV_9280_10_OR_LATER(ah)) {
1031 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1033 if (chan && IS_CHAN_HALF_RATE(chan))
1034 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1035 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1036 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1038 if (chan && IS_CHAN_5GHZ(chan)) {
1039 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1042 if (AR_SREV_9280_20(ah)) {
1043 if (((chan->channel % 20) == 0)
1044 || ((chan->channel % 10) == 0))
1050 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1053 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1055 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1057 if (chan && IS_CHAN_HALF_RATE(chan))
1058 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1059 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1060 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1062 if (chan && IS_CHAN_5GHZ(chan))
1063 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1065 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1067 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1069 if (chan && IS_CHAN_HALF_RATE(chan))
1070 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1071 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1072 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1074 if (chan && IS_CHAN_5GHZ(chan))
1075 pll |= SM(0xa, AR_RTC_PLL_DIV);
1077 pll |= SM(0xb, AR_RTC_PLL_DIV);
1080 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1082 udelay(RTC_PLL_SETTLE_DELAY);
1084 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1087 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1089 int rx_chainmask, tx_chainmask;
1091 rx_chainmask = ah->rxchainmask;
1092 tx_chainmask = ah->txchainmask;
1094 switch (rx_chainmask) {
1096 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1097 AR_PHY_SWAP_ALT_CHAIN);
1099 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1100 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1101 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1107 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1108 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1114 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1115 if (tx_chainmask == 0x5) {
1116 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1117 AR_PHY_SWAP_ALT_CHAIN);
1119 if (AR_SREV_9100(ah))
1120 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1121 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1124 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1125 enum nl80211_iftype opmode)
1127 ah->mask_reg = AR_IMR_TXERR |
1133 if (ah->config.intr_mitigation)
1134 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1136 ah->mask_reg |= AR_IMR_RXOK;
1138 ah->mask_reg |= AR_IMR_TXOK;
1140 if (opmode == NL80211_IFTYPE_AP)
1141 ah->mask_reg |= AR_IMR_MIB;
1143 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1144 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1146 if (!AR_SREV_9100(ah)) {
1147 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1148 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1149 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1153 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1155 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1156 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1157 ah->acktimeout = (u32) -1;
1160 REG_RMW_FIELD(ah, AR_TIME_OUT,
1161 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1162 ah->acktimeout = us;
1167 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1169 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1170 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1171 ah->ctstimeout = (u32) -1;
1174 REG_RMW_FIELD(ah, AR_TIME_OUT,
1175 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1176 ah->ctstimeout = us;
1181 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1184 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1185 "bad global tx timeout %u\n", tu);
1186 ah->globaltxtimeout = (u32) -1;
1189 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1190 ah->globaltxtimeout = tu;
1195 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1197 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1200 if (ah->misc_mode != 0)
1201 REG_WRITE(ah, AR_PCU_MISC,
1202 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1203 if (ah->slottime != (u32) -1)
1204 ath9k_hw_setslottime(ah, ah->slottime);
1205 if (ah->acktimeout != (u32) -1)
1206 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1207 if (ah->ctstimeout != (u32) -1)
1208 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1209 if (ah->globaltxtimeout != (u32) -1)
1210 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1213 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1215 return vendorid == ATHEROS_VENDOR_ID ?
1216 ath9k_hw_devname(devid) : NULL;
1219 void ath9k_hw_detach(struct ath_hw *ah)
1221 if (!AR_SREV_9100(ah))
1222 ath9k_hw_ani_disable(ah);
1224 ath9k_hw_rf_free(ah);
1225 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1234 static void ath9k_hw_override_ini(struct ath_hw *ah,
1235 struct ath9k_channel *chan)
1238 * Set the RX_ABORT and RX_DIS and clear if off only after
1239 * RXE is set for MAC. This prevents frames with corrupted
1240 * descriptor status.
1242 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1245 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1246 AR_SREV_9280_10_OR_LATER(ah))
1249 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1252 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1253 struct ar5416_eeprom_def *pEepData,
1256 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1258 switch (ah->hw_version.devid) {
1259 case AR9280_DEVID_PCI:
1260 if (reg == 0x7894) {
1261 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1262 "ini VAL: %x EEPROM: %x\n", value,
1263 (pBase->version & 0xff));
1265 if ((pBase->version & 0xff) > 0x0a) {
1266 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1269 value &= ~AR_AN_TOP2_PWDCLKIND;
1270 value |= AR_AN_TOP2_PWDCLKIND &
1271 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1273 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1274 "PWDCLKIND Earlier Rev\n");
1277 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1278 "final ini VAL: %x\n", value);
1286 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1287 struct ar5416_eeprom_def *pEepData,
1290 if (ah->eep_map == EEP_MAP_4KBITS)
1293 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1296 static void ath9k_olc_init(struct ath_hw *ah)
1300 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1301 ah->originalGain[i] =
1302 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1307 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1308 struct ath9k_channel *chan)
1310 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1312 if (IS_CHAN_B(chan))
1314 else if (IS_CHAN_G(chan))
1322 static int ath9k_hw_process_ini(struct ath_hw *ah,
1323 struct ath9k_channel *chan,
1324 enum ath9k_ht_macmode macmode)
1326 int i, regWrites = 0;
1327 struct ieee80211_channel *channel = chan->chan;
1328 u32 modesIndex, freqIndex;
1330 switch (chan->chanmode) {
1332 case CHANNEL_A_HT20:
1336 case CHANNEL_A_HT40PLUS:
1337 case CHANNEL_A_HT40MINUS:
1342 case CHANNEL_G_HT20:
1347 case CHANNEL_G_HT40PLUS:
1348 case CHANNEL_G_HT40MINUS:
1357 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1358 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1359 ah->eep_ops->set_addac(ah, chan);
1361 if (AR_SREV_5416_22_OR_LATER(ah)) {
1362 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1364 struct ar5416IniArray temp;
1366 sizeof(u32) * ah->iniAddac.ia_rows *
1367 ah->iniAddac.ia_columns;
1369 memcpy(ah->addac5416_21,
1370 ah->iniAddac.ia_array, addacSize);
1372 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1374 temp.ia_array = ah->addac5416_21;
1375 temp.ia_columns = ah->iniAddac.ia_columns;
1376 temp.ia_rows = ah->iniAddac.ia_rows;
1377 REG_WRITE_ARRAY(&temp, 1, regWrites);
1380 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1382 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1383 u32 reg = INI_RA(&ah->iniModes, i, 0);
1384 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1386 REG_WRITE(ah, reg, val);
1388 if (reg >= 0x7800 && reg < 0x78a0
1389 && ah->config.analog_shiftreg) {
1393 DO_DELAY(regWrites);
1396 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1397 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1399 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1400 AR_SREV_9287_10_OR_LATER(ah))
1401 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1403 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1404 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1405 u32 val = INI_RA(&ah->iniCommon, i, 1);
1407 REG_WRITE(ah, reg, val);
1409 if (reg >= 0x7800 && reg < 0x78a0
1410 && ah->config.analog_shiftreg) {
1414 DO_DELAY(regWrites);
1417 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1419 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1420 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1424 ath9k_hw_override_ini(ah, chan);
1425 ath9k_hw_set_regs(ah, chan, macmode);
1426 ath9k_hw_init_chain_masks(ah);
1428 if (OLC_FOR_AR9280_20_LATER)
1431 ah->eep_ops->set_txpower(ah, chan,
1432 ath9k_regd_get_ctl(&ah->regulatory, chan),
1433 channel->max_antenna_gain * 2,
1434 channel->max_power * 2,
1435 min((u32) MAX_RATE_POWER,
1436 (u32) ah->regulatory.power_limit));
1438 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1439 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1440 "ar5416SetRfRegs failed\n");
1447 /****************************************/
1448 /* Reset and Channel Switching Routines */
1449 /****************************************/
1451 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1458 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1459 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1461 if (!AR_SREV_9280_10_OR_LATER(ah))
1462 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1463 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1465 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1466 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1468 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1471 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1473 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1476 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1480 regval = REG_READ(ah, AR_AHB_MODE);
1481 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1483 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1484 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1486 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1488 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1489 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1491 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1493 if (AR_SREV_9285(ah)) {
1494 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1495 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1497 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1498 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1502 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1506 val = REG_READ(ah, AR_STA_ID1);
1507 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1509 case NL80211_IFTYPE_AP:
1510 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1511 | AR_STA_ID1_KSRCH_MODE);
1512 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1514 case NL80211_IFTYPE_ADHOC:
1515 case NL80211_IFTYPE_MESH_POINT:
1516 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1517 | AR_STA_ID1_KSRCH_MODE);
1518 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1520 case NL80211_IFTYPE_STATION:
1521 case NL80211_IFTYPE_MONITOR:
1522 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1527 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1532 u32 coef_exp, coef_man;
1534 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1535 if ((coef_scaled >> coef_exp) & 0x1)
1538 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1540 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1542 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1543 *coef_exponent = coef_exp - 16;
1546 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1547 struct ath9k_channel *chan)
1549 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1550 u32 clockMhzScaled = 0x64000000;
1551 struct chan_centers centers;
1553 if (IS_CHAN_HALF_RATE(chan))
1554 clockMhzScaled = clockMhzScaled >> 1;
1555 else if (IS_CHAN_QUARTER_RATE(chan))
1556 clockMhzScaled = clockMhzScaled >> 2;
1558 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1559 coef_scaled = clockMhzScaled / centers.synth_center;
1561 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1564 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1565 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1566 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1567 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1569 coef_scaled = (9 * coef_scaled) / 10;
1571 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1574 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1575 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1576 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1577 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1580 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1585 if (AR_SREV_9100(ah)) {
1586 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1587 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1588 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1589 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1590 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1593 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1594 AR_RTC_FORCE_WAKE_ON_INT);
1596 if (AR_SREV_9100(ah)) {
1597 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1598 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1600 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1602 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1603 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1604 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1605 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1607 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1610 rst_flags = AR_RTC_RC_MAC_WARM;
1611 if (type == ATH9K_RESET_COLD)
1612 rst_flags |= AR_RTC_RC_MAC_COLD;
1615 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1618 REG_WRITE(ah, AR_RTC_RC, 0);
1619 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1620 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1621 "RTC stuck in MAC reset\n");
1625 if (!AR_SREV_9100(ah))
1626 REG_WRITE(ah, AR_RC, 0);
1628 ath9k_hw_init_pll(ah, NULL);
1630 if (AR_SREV_9100(ah))
1636 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1638 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1639 AR_RTC_FORCE_WAKE_ON_INT);
1641 REG_WRITE(ah, AR_RTC_RESET, 0);
1643 REG_WRITE(ah, AR_RTC_RESET, 1);
1645 if (!ath9k_hw_wait(ah,
1650 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1654 ath9k_hw_read_revisions(ah);
1656 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1659 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1661 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1662 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1665 case ATH9K_RESET_POWER_ON:
1666 return ath9k_hw_set_reset_power_on(ah);
1667 case ATH9K_RESET_WARM:
1668 case ATH9K_RESET_COLD:
1669 return ath9k_hw_set_reset(ah, type);
1675 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1676 enum ath9k_ht_macmode macmode)
1679 u32 enableDacFifo = 0;
1681 if (AR_SREV_9285_10_OR_LATER(ah))
1682 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1683 AR_PHY_FC_ENABLE_DAC_FIFO);
1685 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1686 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1688 if (IS_CHAN_HT40(chan)) {
1689 phymode |= AR_PHY_FC_DYN2040_EN;
1691 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1692 (chan->chanmode == CHANNEL_G_HT40PLUS))
1693 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1695 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1696 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1698 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1700 ath9k_hw_set11nmac2040(ah, macmode);
1702 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1703 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1706 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1707 struct ath9k_channel *chan)
1709 if (OLC_FOR_AR9280_20_LATER) {
1710 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1712 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1715 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1718 ah->chip_fullsleep = false;
1719 ath9k_hw_init_pll(ah, chan);
1720 ath9k_hw_set_rfmode(ah, chan);
1725 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1726 struct ath9k_channel *chan,
1727 enum ath9k_ht_macmode macmode)
1729 struct ieee80211_channel *channel = chan->chan;
1730 u32 synthDelay, qnum;
1732 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1733 if (ath9k_hw_numtxpending(ah, qnum)) {
1734 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1735 "Transmit frames pending on queue %d\n", qnum);
1740 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1741 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1742 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1743 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1744 "Could not kill baseband RX\n");
1748 ath9k_hw_set_regs(ah, chan, macmode);
1750 if (AR_SREV_9280_10_OR_LATER(ah)) {
1751 ath9k_hw_ar9280_set_channel(ah, chan);
1753 if (!(ath9k_hw_set_channel(ah, chan))) {
1754 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1755 "Failed to set channel\n");
1760 ah->eep_ops->set_txpower(ah, chan,
1761 ath9k_regd_get_ctl(&ah->regulatory, chan),
1762 channel->max_antenna_gain * 2,
1763 channel->max_power * 2,
1764 min((u32) MAX_RATE_POWER,
1765 (u32) ah->regulatory.power_limit));
1767 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1768 if (IS_CHAN_B(chan))
1769 synthDelay = (4 * synthDelay) / 22;
1773 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1775 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1777 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1778 ath9k_hw_set_delta_slope(ah, chan);
1780 if (AR_SREV_9280_10_OR_LATER(ah))
1781 ath9k_hw_9280_spur_mitigate(ah, chan);
1783 ath9k_hw_spur_mitigate(ah, chan);
1785 if (!chan->oneTimeCalsDone)
1786 chan->oneTimeCalsDone = true;
1791 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1793 int bb_spur = AR_NO_SPUR;
1796 int bb_spur_off, spur_subchannel_sd;
1798 int spur_delta_phase;
1800 int upper, lower, cur_vit_mask;
1803 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1804 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1806 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1807 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1809 int inc[4] = { 0, 100, 0, 0 };
1810 struct chan_centers centers;
1817 bool is2GHz = IS_CHAN_2GHZ(chan);
1819 memset(&mask_m, 0, sizeof(int8_t) * 123);
1820 memset(&mask_p, 0, sizeof(int8_t) * 123);
1822 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1823 freq = centers.synth_center;
1825 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1826 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1827 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1830 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1832 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1834 if (AR_NO_SPUR == cur_bb_spur)
1836 cur_bb_spur = cur_bb_spur - freq;
1838 if (IS_CHAN_HT40(chan)) {
1839 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1840 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1841 bb_spur = cur_bb_spur;
1844 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1845 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1846 bb_spur = cur_bb_spur;
1851 if (AR_NO_SPUR == bb_spur) {
1852 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1853 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1856 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1857 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1860 bin = bb_spur * 320;
1862 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1864 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1865 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1866 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1867 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1868 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1870 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1871 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1872 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1873 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1874 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1875 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1877 if (IS_CHAN_HT40(chan)) {
1879 spur_subchannel_sd = 1;
1880 bb_spur_off = bb_spur + 10;
1882 spur_subchannel_sd = 0;
1883 bb_spur_off = bb_spur - 10;
1886 spur_subchannel_sd = 0;
1887 bb_spur_off = bb_spur;
1890 if (IS_CHAN_HT40(chan))
1892 ((bb_spur * 262144) /
1893 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1896 ((bb_spur * 524288) /
1897 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1899 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1900 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1902 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1903 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1904 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1905 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1907 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1908 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1914 for (i = 0; i < 4; i++) {
1918 for (bp = 0; bp < 30; bp++) {
1919 if ((cur_bin > lower) && (cur_bin < upper)) {
1920 pilot_mask = pilot_mask | 0x1 << bp;
1921 chan_mask = chan_mask | 0x1 << bp;
1926 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1927 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1930 cur_vit_mask = 6100;
1934 for (i = 0; i < 123; i++) {
1935 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1937 /* workaround for gcc bug #37014 */
1938 volatile int tmp_v = abs(cur_vit_mask - bin);
1944 if (cur_vit_mask < 0)
1945 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1947 mask_p[cur_vit_mask / 100] = mask_amt;
1949 cur_vit_mask -= 100;
1952 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1953 | (mask_m[48] << 26) | (mask_m[49] << 24)
1954 | (mask_m[50] << 22) | (mask_m[51] << 20)
1955 | (mask_m[52] << 18) | (mask_m[53] << 16)
1956 | (mask_m[54] << 14) | (mask_m[55] << 12)
1957 | (mask_m[56] << 10) | (mask_m[57] << 8)
1958 | (mask_m[58] << 6) | (mask_m[59] << 4)
1959 | (mask_m[60] << 2) | (mask_m[61] << 0);
1960 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1961 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1963 tmp_mask = (mask_m[31] << 28)
1964 | (mask_m[32] << 26) | (mask_m[33] << 24)
1965 | (mask_m[34] << 22) | (mask_m[35] << 20)
1966 | (mask_m[36] << 18) | (mask_m[37] << 16)
1967 | (mask_m[48] << 14) | (mask_m[39] << 12)
1968 | (mask_m[40] << 10) | (mask_m[41] << 8)
1969 | (mask_m[42] << 6) | (mask_m[43] << 4)
1970 | (mask_m[44] << 2) | (mask_m[45] << 0);
1971 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1972 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1974 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1975 | (mask_m[18] << 26) | (mask_m[18] << 24)
1976 | (mask_m[20] << 22) | (mask_m[20] << 20)
1977 | (mask_m[22] << 18) | (mask_m[22] << 16)
1978 | (mask_m[24] << 14) | (mask_m[24] << 12)
1979 | (mask_m[25] << 10) | (mask_m[26] << 8)
1980 | (mask_m[27] << 6) | (mask_m[28] << 4)
1981 | (mask_m[29] << 2) | (mask_m[30] << 0);
1982 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1983 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1985 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1986 | (mask_m[2] << 26) | (mask_m[3] << 24)
1987 | (mask_m[4] << 22) | (mask_m[5] << 20)
1988 | (mask_m[6] << 18) | (mask_m[7] << 16)
1989 | (mask_m[8] << 14) | (mask_m[9] << 12)
1990 | (mask_m[10] << 10) | (mask_m[11] << 8)
1991 | (mask_m[12] << 6) | (mask_m[13] << 4)
1992 | (mask_m[14] << 2) | (mask_m[15] << 0);
1993 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1994 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1996 tmp_mask = (mask_p[15] << 28)
1997 | (mask_p[14] << 26) | (mask_p[13] << 24)
1998 | (mask_p[12] << 22) | (mask_p[11] << 20)
1999 | (mask_p[10] << 18) | (mask_p[9] << 16)
2000 | (mask_p[8] << 14) | (mask_p[7] << 12)
2001 | (mask_p[6] << 10) | (mask_p[5] << 8)
2002 | (mask_p[4] << 6) | (mask_p[3] << 4)
2003 | (mask_p[2] << 2) | (mask_p[1] << 0);
2004 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2005 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2007 tmp_mask = (mask_p[30] << 28)
2008 | (mask_p[29] << 26) | (mask_p[28] << 24)
2009 | (mask_p[27] << 22) | (mask_p[26] << 20)
2010 | (mask_p[25] << 18) | (mask_p[24] << 16)
2011 | (mask_p[23] << 14) | (mask_p[22] << 12)
2012 | (mask_p[21] << 10) | (mask_p[20] << 8)
2013 | (mask_p[19] << 6) | (mask_p[18] << 4)
2014 | (mask_p[17] << 2) | (mask_p[16] << 0);
2015 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2016 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2018 tmp_mask = (mask_p[45] << 28)
2019 | (mask_p[44] << 26) | (mask_p[43] << 24)
2020 | (mask_p[42] << 22) | (mask_p[41] << 20)
2021 | (mask_p[40] << 18) | (mask_p[39] << 16)
2022 | (mask_p[38] << 14) | (mask_p[37] << 12)
2023 | (mask_p[36] << 10) | (mask_p[35] << 8)
2024 | (mask_p[34] << 6) | (mask_p[33] << 4)
2025 | (mask_p[32] << 2) | (mask_p[31] << 0);
2026 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2027 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2029 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2030 | (mask_p[59] << 26) | (mask_p[58] << 24)
2031 | (mask_p[57] << 22) | (mask_p[56] << 20)
2032 | (mask_p[55] << 18) | (mask_p[54] << 16)
2033 | (mask_p[53] << 14) | (mask_p[52] << 12)
2034 | (mask_p[51] << 10) | (mask_p[50] << 8)
2035 | (mask_p[49] << 6) | (mask_p[48] << 4)
2036 | (mask_p[47] << 2) | (mask_p[46] << 0);
2037 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2038 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2041 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2043 int bb_spur = AR_NO_SPUR;
2046 int spur_delta_phase;
2048 int upper, lower, cur_vit_mask;
2051 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2052 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2054 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2055 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2057 int inc[4] = { 0, 100, 0, 0 };
2064 bool is2GHz = IS_CHAN_2GHZ(chan);
2066 memset(&mask_m, 0, sizeof(int8_t) * 123);
2067 memset(&mask_p, 0, sizeof(int8_t) * 123);
2069 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2070 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2071 if (AR_NO_SPUR == cur_bb_spur)
2073 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2074 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2075 bb_spur = cur_bb_spur;
2080 if (AR_NO_SPUR == bb_spur)
2085 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2086 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2087 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2088 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2089 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2091 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2093 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2094 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2095 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2096 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2097 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2098 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2100 spur_delta_phase = ((bb_spur * 524288) / 100) &
2101 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2103 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2104 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2106 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2107 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2108 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2109 REG_WRITE(ah, AR_PHY_TIMING11, new);
2115 for (i = 0; i < 4; i++) {
2119 for (bp = 0; bp < 30; bp++) {
2120 if ((cur_bin > lower) && (cur_bin < upper)) {
2121 pilot_mask = pilot_mask | 0x1 << bp;
2122 chan_mask = chan_mask | 0x1 << bp;
2127 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2128 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2131 cur_vit_mask = 6100;
2135 for (i = 0; i < 123; i++) {
2136 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2138 /* workaround for gcc bug #37014 */
2139 volatile int tmp_v = abs(cur_vit_mask - bin);
2145 if (cur_vit_mask < 0)
2146 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2148 mask_p[cur_vit_mask / 100] = mask_amt;
2150 cur_vit_mask -= 100;
2153 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2154 | (mask_m[48] << 26) | (mask_m[49] << 24)
2155 | (mask_m[50] << 22) | (mask_m[51] << 20)
2156 | (mask_m[52] << 18) | (mask_m[53] << 16)
2157 | (mask_m[54] << 14) | (mask_m[55] << 12)
2158 | (mask_m[56] << 10) | (mask_m[57] << 8)
2159 | (mask_m[58] << 6) | (mask_m[59] << 4)
2160 | (mask_m[60] << 2) | (mask_m[61] << 0);
2161 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2162 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2164 tmp_mask = (mask_m[31] << 28)
2165 | (mask_m[32] << 26) | (mask_m[33] << 24)
2166 | (mask_m[34] << 22) | (mask_m[35] << 20)
2167 | (mask_m[36] << 18) | (mask_m[37] << 16)
2168 | (mask_m[48] << 14) | (mask_m[39] << 12)
2169 | (mask_m[40] << 10) | (mask_m[41] << 8)
2170 | (mask_m[42] << 6) | (mask_m[43] << 4)
2171 | (mask_m[44] << 2) | (mask_m[45] << 0);
2172 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2173 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2175 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2176 | (mask_m[18] << 26) | (mask_m[18] << 24)
2177 | (mask_m[20] << 22) | (mask_m[20] << 20)
2178 | (mask_m[22] << 18) | (mask_m[22] << 16)
2179 | (mask_m[24] << 14) | (mask_m[24] << 12)
2180 | (mask_m[25] << 10) | (mask_m[26] << 8)
2181 | (mask_m[27] << 6) | (mask_m[28] << 4)
2182 | (mask_m[29] << 2) | (mask_m[30] << 0);
2183 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2184 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2186 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2187 | (mask_m[2] << 26) | (mask_m[3] << 24)
2188 | (mask_m[4] << 22) | (mask_m[5] << 20)
2189 | (mask_m[6] << 18) | (mask_m[7] << 16)
2190 | (mask_m[8] << 14) | (mask_m[9] << 12)
2191 | (mask_m[10] << 10) | (mask_m[11] << 8)
2192 | (mask_m[12] << 6) | (mask_m[13] << 4)
2193 | (mask_m[14] << 2) | (mask_m[15] << 0);
2194 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2195 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2197 tmp_mask = (mask_p[15] << 28)
2198 | (mask_p[14] << 26) | (mask_p[13] << 24)
2199 | (mask_p[12] << 22) | (mask_p[11] << 20)
2200 | (mask_p[10] << 18) | (mask_p[9] << 16)
2201 | (mask_p[8] << 14) | (mask_p[7] << 12)
2202 | (mask_p[6] << 10) | (mask_p[5] << 8)
2203 | (mask_p[4] << 6) | (mask_p[3] << 4)
2204 | (mask_p[2] << 2) | (mask_p[1] << 0);
2205 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2206 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2208 tmp_mask = (mask_p[30] << 28)
2209 | (mask_p[29] << 26) | (mask_p[28] << 24)
2210 | (mask_p[27] << 22) | (mask_p[26] << 20)
2211 | (mask_p[25] << 18) | (mask_p[24] << 16)
2212 | (mask_p[23] << 14) | (mask_p[22] << 12)
2213 | (mask_p[21] << 10) | (mask_p[20] << 8)
2214 | (mask_p[19] << 6) | (mask_p[18] << 4)
2215 | (mask_p[17] << 2) | (mask_p[16] << 0);
2216 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2217 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2219 tmp_mask = (mask_p[45] << 28)
2220 | (mask_p[44] << 26) | (mask_p[43] << 24)
2221 | (mask_p[42] << 22) | (mask_p[41] << 20)
2222 | (mask_p[40] << 18) | (mask_p[39] << 16)
2223 | (mask_p[38] << 14) | (mask_p[37] << 12)
2224 | (mask_p[36] << 10) | (mask_p[35] << 8)
2225 | (mask_p[34] << 6) | (mask_p[33] << 4)
2226 | (mask_p[32] << 2) | (mask_p[31] << 0);
2227 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2228 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2230 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2231 | (mask_p[59] << 26) | (mask_p[58] << 24)
2232 | (mask_p[57] << 22) | (mask_p[56] << 20)
2233 | (mask_p[55] << 18) | (mask_p[54] << 16)
2234 | (mask_p[53] << 14) | (mask_p[52] << 12)
2235 | (mask_p[51] << 10) | (mask_p[50] << 8)
2236 | (mask_p[49] << 6) | (mask_p[48] << 4)
2237 | (mask_p[47] << 2) | (mask_p[46] << 0);
2238 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2239 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2242 static void ath9k_enable_rfkill(struct ath_hw *ah)
2244 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2245 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2247 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2248 AR_GPIO_INPUT_MUX2_RFSILENT);
2250 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2251 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2254 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2255 bool bChannelChange)
2258 struct ath_softc *sc = ah->ah_sc;
2259 struct ath9k_channel *curchan = ah->curchan;
2262 int i, rx_chainmask, r;
2264 ah->extprotspacing = sc->ht_extprotspacing;
2265 ah->txchainmask = sc->tx_chainmask;
2266 ah->rxchainmask = sc->rx_chainmask;
2268 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2272 ath9k_hw_getnf(ah, curchan);
2274 if (bChannelChange &&
2275 (ah->chip_fullsleep != true) &&
2276 (ah->curchan != NULL) &&
2277 (chan->channel != ah->curchan->channel) &&
2278 ((chan->channelFlags & CHANNEL_ALL) ==
2279 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2280 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2281 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2283 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2284 ath9k_hw_loadnf(ah, ah->curchan);
2285 ath9k_hw_start_nfcal(ah);
2290 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2291 if (saveDefAntenna == 0)
2294 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2296 saveLedState = REG_READ(ah, AR_CFG_LED) &
2297 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2298 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2300 ath9k_hw_mark_phy_inactive(ah);
2302 if (!ath9k_hw_chip_reset(ah, chan)) {
2303 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2307 if (AR_SREV_9280_10_OR_LATER(ah))
2308 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2310 if (AR_SREV_9287_10_OR_LATER(ah)) {
2311 /* Enable ASYNC FIFO */
2312 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2313 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2314 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2315 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2316 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2317 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2318 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2320 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2324 /* Setup MFP options for CCMP */
2325 if (AR_SREV_9280_20_OR_LATER(ah)) {
2326 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2327 * frames when constructing CCMP AAD. */
2328 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2330 ah->sw_mgmt_crypto = false;
2331 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2332 /* Disable hardware crypto for management frames */
2333 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2334 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2335 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2336 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2337 ah->sw_mgmt_crypto = true;
2339 ah->sw_mgmt_crypto = true;
2341 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2342 ath9k_hw_set_delta_slope(ah, chan);
2344 if (AR_SREV_9280_10_OR_LATER(ah))
2345 ath9k_hw_9280_spur_mitigate(ah, chan);
2347 ath9k_hw_spur_mitigate(ah, chan);
2349 ah->eep_ops->set_board_values(ah, chan);
2351 ath9k_hw_decrease_chain_power(ah, chan);
2353 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2354 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2356 | AR_STA_ID1_RTS_USE_DEF
2358 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2359 | ah->sta_id1_defaults);
2360 ath9k_hw_set_operating_mode(ah, ah->opmode);
2362 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2363 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2365 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2367 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2368 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2369 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2371 REG_WRITE(ah, AR_ISR, ~0);
2373 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2375 if (AR_SREV_9280_10_OR_LATER(ah))
2376 ath9k_hw_ar9280_set_channel(ah, chan);
2378 if (!(ath9k_hw_set_channel(ah, chan)))
2381 for (i = 0; i < AR_NUM_DCU; i++)
2382 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2385 for (i = 0; i < ah->caps.total_queues; i++)
2386 ath9k_hw_resettxqueue(ah, i);
2388 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2389 ath9k_hw_init_qos(ah);
2391 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2392 ath9k_enable_rfkill(ah);
2394 ath9k_hw_init_user_settings(ah);
2396 if (AR_SREV_9287_10_OR_LATER(ah)) {
2397 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2398 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2399 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2400 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2401 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2402 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2404 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2405 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2407 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2408 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2409 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2410 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2412 if (AR_SREV_9287_10_OR_LATER(ah)) {
2413 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2414 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2417 REG_WRITE(ah, AR_STA_ID1,
2418 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2420 ath9k_hw_set_dma(ah);
2422 REG_WRITE(ah, AR_OBS, 8);
2424 if (ah->config.intr_mitigation) {
2425 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2426 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2429 ath9k_hw_init_bb(ah, chan);
2431 if (!ath9k_hw_init_cal(ah, chan))
2434 rx_chainmask = ah->rxchainmask;
2435 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2436 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2437 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2440 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2442 if (AR_SREV_9100(ah)) {
2444 mask = REG_READ(ah, AR_CFG);
2445 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2446 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2447 "CFG Byte Swap Set 0x%x\n", mask);
2450 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2451 REG_WRITE(ah, AR_CFG, mask);
2452 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2453 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2457 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2464 /************************/
2465 /* Key Cache Management */
2466 /************************/
2468 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2472 if (entry >= ah->caps.keycache_size) {
2473 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2474 "keychache entry %u out of range\n", entry);
2478 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2480 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2481 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2482 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2483 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2484 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2485 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2486 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2487 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2489 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2490 u16 micentry = entry + 64;
2492 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2493 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2494 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2495 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2499 if (ah->curchan == NULL)
2505 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2509 if (entry >= ah->caps.keycache_size) {
2510 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2511 "keychache entry %u out of range\n", entry);
2516 macHi = (mac[5] << 8) | mac[4];
2517 macLo = (mac[3] << 24) |
2522 macLo |= (macHi & 1) << 31;
2527 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2528 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2533 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2534 const struct ath9k_keyval *k,
2537 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2538 u32 key0, key1, key2, key3, key4;
2541 if (entry >= pCap->keycache_size) {
2542 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2543 "keycache entry %u out of range\n", entry);
2547 switch (k->kv_type) {
2548 case ATH9K_CIPHER_AES_OCB:
2549 keyType = AR_KEYTABLE_TYPE_AES;
2551 case ATH9K_CIPHER_AES_CCM:
2552 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2553 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2554 "AES-CCM not supported by mac rev 0x%x\n",
2555 ah->hw_version.macRev);
2558 keyType = AR_KEYTABLE_TYPE_CCM;
2560 case ATH9K_CIPHER_TKIP:
2561 keyType = AR_KEYTABLE_TYPE_TKIP;
2562 if (ATH9K_IS_MIC_ENABLED(ah)
2563 && entry + 64 >= pCap->keycache_size) {
2564 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2565 "entry %u inappropriate for TKIP\n", entry);
2569 case ATH9K_CIPHER_WEP:
2570 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2571 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2572 "WEP key length %u too small\n", k->kv_len);
2575 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2576 keyType = AR_KEYTABLE_TYPE_40;
2577 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2578 keyType = AR_KEYTABLE_TYPE_104;
2580 keyType = AR_KEYTABLE_TYPE_128;
2582 case ATH9K_CIPHER_CLR:
2583 keyType = AR_KEYTABLE_TYPE_CLR;
2586 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2587 "cipher %u not supported\n", k->kv_type);
2591 key0 = get_unaligned_le32(k->kv_val + 0);
2592 key1 = get_unaligned_le16(k->kv_val + 4);
2593 key2 = get_unaligned_le32(k->kv_val + 6);
2594 key3 = get_unaligned_le16(k->kv_val + 10);
2595 key4 = get_unaligned_le32(k->kv_val + 12);
2596 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2600 * Note: Key cache registers access special memory area that requires
2601 * two 32-bit writes to actually update the values in the internal
2602 * memory. Consequently, the exact order and pairs used here must be
2606 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2607 u16 micentry = entry + 64;
2610 * Write inverted key[47:0] first to avoid Michael MIC errors
2611 * on frames that could be sent or received at the same time.
2612 * The correct key will be written in the end once everything
2615 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2616 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2618 /* Write key[95:48] */
2619 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2620 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2622 /* Write key[127:96] and key type */
2623 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2624 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2626 /* Write MAC address for the entry */
2627 (void) ath9k_hw_keysetmac(ah, entry, mac);
2629 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2631 * TKIP uses two key cache entries:
2632 * Michael MIC TX/RX keys in the same key cache entry
2633 * (idx = main index + 64):
2634 * key0 [31:0] = RX key [31:0]
2635 * key1 [15:0] = TX key [31:16]
2636 * key1 [31:16] = reserved
2637 * key2 [31:0] = RX key [63:32]
2638 * key3 [15:0] = TX key [15:0]
2639 * key3 [31:16] = reserved
2640 * key4 [31:0] = TX key [63:32]
2642 u32 mic0, mic1, mic2, mic3, mic4;
2644 mic0 = get_unaligned_le32(k->kv_mic + 0);
2645 mic2 = get_unaligned_le32(k->kv_mic + 4);
2646 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2647 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2648 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2650 /* Write RX[31:0] and TX[31:16] */
2651 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2652 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2654 /* Write RX[63:32] and TX[15:0] */
2655 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2656 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2658 /* Write TX[63:32] and keyType(reserved) */
2659 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2660 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2661 AR_KEYTABLE_TYPE_CLR);
2665 * TKIP uses four key cache entries (two for group
2667 * Michael MIC TX/RX keys are in different key cache
2668 * entries (idx = main index + 64 for TX and
2669 * main index + 32 + 96 for RX):
2670 * key0 [31:0] = TX/RX MIC key [31:0]
2671 * key1 [31:0] = reserved
2672 * key2 [31:0] = TX/RX MIC key [63:32]
2673 * key3 [31:0] = reserved
2674 * key4 [31:0] = reserved
2676 * Upper layer code will call this function separately
2677 * for TX and RX keys when these registers offsets are
2682 mic0 = get_unaligned_le32(k->kv_mic + 0);
2683 mic2 = get_unaligned_le32(k->kv_mic + 4);
2685 /* Write MIC key[31:0] */
2686 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2687 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2689 /* Write MIC key[63:32] */
2690 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2691 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2693 /* Write TX[63:32] and keyType(reserved) */
2694 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2695 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2696 AR_KEYTABLE_TYPE_CLR);
2699 /* MAC address registers are reserved for the MIC entry */
2700 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2701 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2704 * Write the correct (un-inverted) key[47:0] last to enable
2705 * TKIP now that all other registers are set with correct
2708 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2709 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2711 /* Write key[47:0] */
2712 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2713 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2715 /* Write key[95:48] */
2716 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2717 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2719 /* Write key[127:96] and key type */
2720 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2721 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2723 /* Write MAC address for the entry */
2724 (void) ath9k_hw_keysetmac(ah, entry, mac);
2730 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2732 if (entry < ah->caps.keycache_size) {
2733 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2734 if (val & AR_KEYTABLE_VALID)
2740 /******************************/
2741 /* Power Management (Chipset) */
2742 /******************************/
2744 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2746 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2748 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2749 AR_RTC_FORCE_WAKE_EN);
2750 if (!AR_SREV_9100(ah))
2751 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2753 REG_CLR_BIT(ah, (AR_RTC_RESET),
2758 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2760 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2762 struct ath9k_hw_capabilities *pCap = &ah->caps;
2764 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2765 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2766 AR_RTC_FORCE_WAKE_ON_INT);
2768 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2769 AR_RTC_FORCE_WAKE_EN);
2774 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2780 if ((REG_READ(ah, AR_RTC_STATUS) &
2781 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2782 if (ath9k_hw_set_reset_reg(ah,
2783 ATH9K_RESET_POWER_ON) != true) {
2787 if (AR_SREV_9100(ah))
2788 REG_SET_BIT(ah, AR_RTC_RESET,
2791 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2792 AR_RTC_FORCE_WAKE_EN);
2795 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2796 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2797 if (val == AR_RTC_STATUS_ON)
2800 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2801 AR_RTC_FORCE_WAKE_EN);
2804 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2805 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2810 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2815 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2816 enum ath9k_power_mode mode)
2818 int status = true, setChip = true;
2819 static const char *modes[] = {
2826 if (ah->power_mode == mode)
2829 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2830 modes[ah->power_mode], modes[mode]);
2833 case ATH9K_PM_AWAKE:
2834 status = ath9k_hw_set_power_awake(ah, setChip);
2836 case ATH9K_PM_FULL_SLEEP:
2837 ath9k_set_power_sleep(ah, setChip);
2838 ah->chip_fullsleep = true;
2840 case ATH9K_PM_NETWORK_SLEEP:
2841 ath9k_set_power_network_sleep(ah, setChip);
2844 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2845 "Unknown power mode %u\n", mode);
2848 ah->power_mode = mode;
2853 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2855 unsigned long flags;
2858 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2859 ret = ath9k_hw_setpower_nolock(ah, mode);
2860 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2865 void ath9k_ps_wakeup(struct ath_softc *sc)
2867 unsigned long flags;
2869 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2870 if (++sc->ps_usecount != 1)
2873 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2876 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2879 void ath9k_ps_restore(struct ath_softc *sc)
2881 unsigned long flags;
2883 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2884 if (--sc->ps_usecount != 0)
2887 if (sc->ps_enabled &&
2888 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2889 SC_OP_WAIT_FOR_CAB |
2890 SC_OP_WAIT_FOR_PSPOLL_DATA |
2891 SC_OP_WAIT_FOR_TX_ACK)))
2892 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2895 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2899 * Helper for ASPM support.
2901 * Disable PLL when in L0s as well as receiver clock when in L1.
2902 * This power saving option must be enabled through the SerDes.
2904 * Programming the SerDes must go through the same 288 bit serial shift
2905 * register as the other analog registers. Hence the 9 writes.
2907 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2911 if (ah->is_pciexpress != true)
2914 /* Do not touch SerDes registers */
2915 if (ah->config.pcie_powersave_enable == 2)
2918 /* Nothing to do on restore for 11N */
2922 if (AR_SREV_9280_20_OR_LATER(ah)) {
2924 * AR9280 2.0 or later chips use SerDes values from the
2925 * initvals.h initialized depending on chipset during
2928 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2929 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2930 INI_RA(&ah->iniPcieSerdes, i, 1));
2932 } else if (AR_SREV_9280(ah) &&
2933 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2934 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2935 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2937 /* RX shut off when elecidle is asserted */
2938 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2939 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2940 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2942 /* Shut off CLKREQ active in L1 */
2943 if (ah->config.pcie_clock_req)
2944 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2946 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2948 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2949 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2950 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2952 /* Load the new settings */
2953 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2956 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2957 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2959 /* RX shut off when elecidle is asserted */
2960 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2961 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2962 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2965 * Ignore ah->ah_config.pcie_clock_req setting for
2968 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2970 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2971 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2972 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2974 /* Load the new settings */
2975 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2980 /* set bit 19 to allow forcing of pcie core into L1 state */
2981 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2983 /* Several PCIe massages to ensure proper behaviour */
2984 if (ah->config.pcie_waen) {
2985 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2987 if (AR_SREV_9285(ah))
2988 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2990 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2991 * otherwise card may disappear.
2993 else if (AR_SREV_9280(ah))
2994 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2996 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3000 /**********************/
3001 /* Interrupt Handling */
3002 /**********************/
3004 bool ath9k_hw_intrpend(struct ath_hw *ah)
3008 if (AR_SREV_9100(ah))
3011 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3012 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3015 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3016 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3017 && (host_isr != AR_INTR_SPURIOUS))
3023 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3027 struct ath9k_hw_capabilities *pCap = &ah->caps;
3029 bool fatal_int = false;
3031 if (!AR_SREV_9100(ah)) {
3032 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3033 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3034 == AR_RTC_STATUS_ON) {
3035 isr = REG_READ(ah, AR_ISR);
3039 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3040 AR_INTR_SYNC_DEFAULT;
3044 if (!isr && !sync_cause)
3048 isr = REG_READ(ah, AR_ISR);
3052 if (isr & AR_ISR_BCNMISC) {
3054 isr2 = REG_READ(ah, AR_ISR_S2);
3055 if (isr2 & AR_ISR_S2_TIM)
3056 mask2 |= ATH9K_INT_TIM;
3057 if (isr2 & AR_ISR_S2_DTIM)
3058 mask2 |= ATH9K_INT_DTIM;
3059 if (isr2 & AR_ISR_S2_DTIMSYNC)
3060 mask2 |= ATH9K_INT_DTIMSYNC;
3061 if (isr2 & (AR_ISR_S2_CABEND))
3062 mask2 |= ATH9K_INT_CABEND;
3063 if (isr2 & AR_ISR_S2_GTT)
3064 mask2 |= ATH9K_INT_GTT;
3065 if (isr2 & AR_ISR_S2_CST)
3066 mask2 |= ATH9K_INT_CST;
3067 if (isr2 & AR_ISR_S2_TSFOOR)
3068 mask2 |= ATH9K_INT_TSFOOR;
3071 isr = REG_READ(ah, AR_ISR_RAC);
3072 if (isr == 0xffffffff) {
3077 *masked = isr & ATH9K_INT_COMMON;
3079 if (ah->config.intr_mitigation) {
3080 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3081 *masked |= ATH9K_INT_RX;
3084 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3085 *masked |= ATH9K_INT_RX;
3087 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3091 *masked |= ATH9K_INT_TX;
3093 s0_s = REG_READ(ah, AR_ISR_S0_S);
3094 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3095 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3097 s1_s = REG_READ(ah, AR_ISR_S1_S);
3098 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3099 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3102 if (isr & AR_ISR_RXORN) {
3103 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3104 "receive FIFO overrun interrupt\n");
3107 if (!AR_SREV_9100(ah)) {
3108 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3109 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3110 if (isr5 & AR_ISR_S5_TIM_TIMER)
3111 *masked |= ATH9K_INT_TIM_TIMER;
3118 if (AR_SREV_9100(ah))
3124 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3128 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3129 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3130 "received PCI FATAL interrupt\n");
3132 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3133 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3134 "received PCI PERR interrupt\n");
3136 *masked |= ATH9K_INT_FATAL;
3138 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3139 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3140 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3141 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3142 REG_WRITE(ah, AR_RC, 0);
3143 *masked |= ATH9K_INT_FATAL;
3145 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3146 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3147 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3150 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3151 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3157 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3159 u32 omask = ah->mask_reg;
3161 struct ath9k_hw_capabilities *pCap = &ah->caps;
3163 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3165 if (omask & ATH9K_INT_GLOBAL) {
3166 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3167 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3168 (void) REG_READ(ah, AR_IER);
3169 if (!AR_SREV_9100(ah)) {
3170 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3171 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3173 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3174 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3178 mask = ints & ATH9K_INT_COMMON;
3181 if (ints & ATH9K_INT_TX) {
3182 if (ah->txok_interrupt_mask)
3183 mask |= AR_IMR_TXOK;
3184 if (ah->txdesc_interrupt_mask)
3185 mask |= AR_IMR_TXDESC;
3186 if (ah->txerr_interrupt_mask)
3187 mask |= AR_IMR_TXERR;
3188 if (ah->txeol_interrupt_mask)
3189 mask |= AR_IMR_TXEOL;
3191 if (ints & ATH9K_INT_RX) {
3192 mask |= AR_IMR_RXERR;
3193 if (ah->config.intr_mitigation)
3194 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3196 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3197 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3198 mask |= AR_IMR_GENTMR;
3201 if (ints & (ATH9K_INT_BMISC)) {
3202 mask |= AR_IMR_BCNMISC;
3203 if (ints & ATH9K_INT_TIM)
3204 mask2 |= AR_IMR_S2_TIM;
3205 if (ints & ATH9K_INT_DTIM)
3206 mask2 |= AR_IMR_S2_DTIM;
3207 if (ints & ATH9K_INT_DTIMSYNC)
3208 mask2 |= AR_IMR_S2_DTIMSYNC;
3209 if (ints & ATH9K_INT_CABEND)
3210 mask2 |= AR_IMR_S2_CABEND;
3211 if (ints & ATH9K_INT_TSFOOR)
3212 mask2 |= AR_IMR_S2_TSFOOR;
3215 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3216 mask |= AR_IMR_BCNMISC;
3217 if (ints & ATH9K_INT_GTT)
3218 mask2 |= AR_IMR_S2_GTT;
3219 if (ints & ATH9K_INT_CST)
3220 mask2 |= AR_IMR_S2_CST;
3223 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3224 REG_WRITE(ah, AR_IMR, mask);
3225 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3227 AR_IMR_S2_DTIMSYNC |
3231 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3232 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3233 ah->mask_reg = ints;
3235 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3236 if (ints & ATH9K_INT_TIM_TIMER)
3237 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3239 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3242 if (ints & ATH9K_INT_GLOBAL) {
3243 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3244 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3245 if (!AR_SREV_9100(ah)) {
3246 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3248 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3251 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3252 AR_INTR_SYNC_DEFAULT);
3253 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3254 AR_INTR_SYNC_DEFAULT);
3256 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3257 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3263 /*******************/
3264 /* Beacon Handling */
3265 /*******************/
3267 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3271 ah->beacon_interval = beacon_period;
3273 switch (ah->opmode) {
3274 case NL80211_IFTYPE_STATION:
3275 case NL80211_IFTYPE_MONITOR:
3276 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3277 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3278 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3279 flags |= AR_TBTT_TIMER_EN;
3281 case NL80211_IFTYPE_ADHOC:
3282 case NL80211_IFTYPE_MESH_POINT:
3283 REG_SET_BIT(ah, AR_TXCFG,
3284 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3285 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3286 TU_TO_USEC(next_beacon +
3287 (ah->atim_window ? ah->
3289 flags |= AR_NDP_TIMER_EN;
3290 case NL80211_IFTYPE_AP:
3291 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3292 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3293 TU_TO_USEC(next_beacon -
3295 dma_beacon_response_time));
3296 REG_WRITE(ah, AR_NEXT_SWBA,
3297 TU_TO_USEC(next_beacon -
3299 sw_beacon_response_time));
3301 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3304 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3305 "%s: unsupported opmode: %d\n",
3306 __func__, ah->opmode);
3311 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3312 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3313 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3314 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3316 beacon_period &= ~ATH9K_BEACON_ENA;
3317 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3318 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3319 ath9k_hw_reset_tsf(ah);
3322 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3325 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3326 const struct ath9k_beacon_state *bs)
3328 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3329 struct ath9k_hw_capabilities *pCap = &ah->caps;
3331 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3333 REG_WRITE(ah, AR_BEACON_PERIOD,
3334 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3335 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3336 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3338 REG_RMW_FIELD(ah, AR_RSSI_THR,
3339 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3341 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3343 if (bs->bs_sleepduration > beaconintval)
3344 beaconintval = bs->bs_sleepduration;
3346 dtimperiod = bs->bs_dtimperiod;
3347 if (bs->bs_sleepduration > dtimperiod)
3348 dtimperiod = bs->bs_sleepduration;
3350 if (beaconintval == dtimperiod)
3351 nextTbtt = bs->bs_nextdtim;
3353 nextTbtt = bs->bs_nexttbtt;
3355 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3356 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3357 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3358 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3360 REG_WRITE(ah, AR_NEXT_DTIM,
3361 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3362 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3364 REG_WRITE(ah, AR_SLEEP1,
3365 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3366 | AR_SLEEP1_ASSUME_DTIM);
3368 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3369 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3371 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3373 REG_WRITE(ah, AR_SLEEP2,
3374 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3376 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3377 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3379 REG_SET_BIT(ah, AR_TIMER_MODE,
3380 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3383 /* TSF Out of Range Threshold */
3384 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3387 /*******************/
3388 /* HW Capabilities */
3389 /*******************/
3391 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3393 struct ath9k_hw_capabilities *pCap = &ah->caps;
3394 u16 capField = 0, eeval;
3396 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3397 ah->regulatory.current_rd = eeval;
3399 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3400 if (AR_SREV_9285_10_OR_LATER(ah))
3401 eeval |= AR9285_RDEXT_DEFAULT;
3402 ah->regulatory.current_rd_ext = eeval;
3404 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3406 if (ah->opmode != NL80211_IFTYPE_AP &&
3407 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3408 if (ah->regulatory.current_rd == 0x64 ||
3409 ah->regulatory.current_rd == 0x65)
3410 ah->regulatory.current_rd += 5;
3411 else if (ah->regulatory.current_rd == 0x41)
3412 ah->regulatory.current_rd = 0x43;
3413 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3414 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3417 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3418 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3420 if (eeval & AR5416_OPFLAGS_11A) {
3421 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3422 if (ah->config.ht_enable) {
3423 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3424 set_bit(ATH9K_MODE_11NA_HT20,
3425 pCap->wireless_modes);
3426 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3427 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3428 pCap->wireless_modes);
3429 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3430 pCap->wireless_modes);
3435 if (eeval & AR5416_OPFLAGS_11G) {
3436 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3437 if (ah->config.ht_enable) {
3438 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3439 set_bit(ATH9K_MODE_11NG_HT20,
3440 pCap->wireless_modes);
3441 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3442 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3443 pCap->wireless_modes);
3444 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3445 pCap->wireless_modes);
3450 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3451 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3452 !(eeval & AR5416_OPFLAGS_11A))
3453 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3455 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3457 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3458 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3460 pCap->low_2ghz_chan = 2312;
3461 pCap->high_2ghz_chan = 2732;
3463 pCap->low_5ghz_chan = 4920;
3464 pCap->high_5ghz_chan = 6100;
3466 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3467 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3468 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3470 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3471 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3472 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3474 if (ah->config.ht_enable)
3475 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3477 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3479 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3480 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3481 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3482 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3484 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3485 pCap->total_queues =
3486 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3488 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3490 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3491 pCap->keycache_size =
3492 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3494 pCap->keycache_size = AR_KEYTABLE_SIZE;
3496 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3497 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3499 if (AR_SREV_9285_10_OR_LATER(ah))
3500 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3501 else if (AR_SREV_9280_10_OR_LATER(ah))
3502 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3504 pCap->num_gpio_pins = AR_NUM_GPIO;
3506 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3507 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3508 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3510 pCap->rts_aggr_limit = (8 * 1024);
3513 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3515 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3516 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3517 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3519 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3520 ah->rfkill_polarity =
3521 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3523 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3527 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3528 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3529 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3530 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3531 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3532 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3533 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3535 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3537 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3538 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3540 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3542 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3544 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3545 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3546 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3547 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3550 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3551 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3554 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3556 pCap->num_antcfg_5ghz =
3557 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3558 pCap->num_antcfg_2ghz =
3559 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3561 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3562 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3563 ah->btactive_gpio = 6;
3564 ah->wlanactive_gpio = 5;
3568 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3569 u32 capability, u32 *result)
3572 case ATH9K_CAP_CIPHER:
3573 switch (capability) {
3574 case ATH9K_CIPHER_AES_CCM:
3575 case ATH9K_CIPHER_AES_OCB:
3576 case ATH9K_CIPHER_TKIP:
3577 case ATH9K_CIPHER_WEP:
3578 case ATH9K_CIPHER_MIC:
3579 case ATH9K_CIPHER_CLR:
3584 case ATH9K_CAP_TKIP_MIC:
3585 switch (capability) {
3589 return (ah->sta_id1_defaults &
3590 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3593 case ATH9K_CAP_TKIP_SPLIT:
3594 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3596 case ATH9K_CAP_DIVERSITY:
3597 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3598 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3600 case ATH9K_CAP_MCAST_KEYSRCH:
3601 switch (capability) {
3605 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3608 return (ah->sta_id1_defaults &
3609 AR_STA_ID1_MCAST_KSRCH) ? true :
3614 case ATH9K_CAP_TXPOW:
3615 switch (capability) {
3619 *result = ah->regulatory.power_limit;
3622 *result = ah->regulatory.max_power_level;
3625 *result = ah->regulatory.tp_scale;
3630 return (AR_SREV_9280_20_OR_LATER(ah) &&
3631 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3638 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3639 u32 capability, u32 setting, int *status)
3644 case ATH9K_CAP_TKIP_MIC:
3646 ah->sta_id1_defaults |=
3647 AR_STA_ID1_CRPT_MIC_ENABLE;
3649 ah->sta_id1_defaults &=
3650 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3652 case ATH9K_CAP_DIVERSITY:
3653 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3655 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3657 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3658 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3660 case ATH9K_CAP_MCAST_KEYSRCH:
3662 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3664 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3671 /****************************/
3672 /* GPIO / RFKILL / Antennae */
3673 /****************************/
3675 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3679 u32 gpio_shift, tmp;
3682 addr = AR_GPIO_OUTPUT_MUX3;
3684 addr = AR_GPIO_OUTPUT_MUX2;
3686 addr = AR_GPIO_OUTPUT_MUX1;
3688 gpio_shift = (gpio % 6) * 5;
3690 if (AR_SREV_9280_20_OR_LATER(ah)
3691 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3692 REG_RMW(ah, addr, (type << gpio_shift),
3693 (0x1f << gpio_shift));
3695 tmp = REG_READ(ah, addr);
3696 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3697 tmp &= ~(0x1f << gpio_shift);
3698 tmp |= (type << gpio_shift);
3699 REG_WRITE(ah, addr, tmp);
3703 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3707 ASSERT(gpio < ah->caps.num_gpio_pins);
3709 gpio_shift = gpio << 1;
3713 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3714 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3717 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3719 #define MS_REG_READ(x, y) \
3720 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3722 if (gpio >= ah->caps.num_gpio_pins)
3725 if (AR_SREV_9287_10_OR_LATER(ah))
3726 return MS_REG_READ(AR9287, gpio) != 0;
3727 else if (AR_SREV_9285_10_OR_LATER(ah))
3728 return MS_REG_READ(AR9285, gpio) != 0;
3729 else if (AR_SREV_9280_10_OR_LATER(ah))
3730 return MS_REG_READ(AR928X, gpio) != 0;
3732 return MS_REG_READ(AR, gpio) != 0;
3735 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3740 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3742 gpio_shift = 2 * gpio;
3746 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3747 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3750 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3752 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3756 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3758 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3761 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3763 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3766 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3767 enum ath9k_ant_setting settings,
3768 struct ath9k_channel *chan,
3773 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3775 if (AR_SREV_9280(ah)) {
3776 if (!tx_chainmask_cfg) {
3778 tx_chainmask_cfg = *tx_chainmask;
3779 rx_chainmask_cfg = *rx_chainmask;
3783 case ATH9K_ANT_FIXED_A:
3784 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3785 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3786 *antenna_cfgd = true;
3788 case ATH9K_ANT_FIXED_B:
3789 if (ah->caps.tx_chainmask >
3790 ATH9K_ANTENNA1_CHAINMASK) {
3791 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3793 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3794 *antenna_cfgd = true;
3796 case ATH9K_ANT_VARIABLE:
3797 *tx_chainmask = tx_chainmask_cfg;
3798 *rx_chainmask = rx_chainmask_cfg;
3799 *antenna_cfgd = true;
3805 ah->diversity_control = settings;
3811 /*********************/
3812 /* General Operation */
3813 /*********************/
3815 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3817 u32 bits = REG_READ(ah, AR_RX_FILTER);
3818 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3820 if (phybits & AR_PHY_ERR_RADAR)
3821 bits |= ATH9K_RX_FILTER_PHYRADAR;
3822 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3823 bits |= ATH9K_RX_FILTER_PHYERR;
3828 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3832 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3834 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3835 phybits |= AR_PHY_ERR_RADAR;
3836 if (bits & ATH9K_RX_FILTER_PHYERR)
3837 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3838 REG_WRITE(ah, AR_PHY_ERR, phybits);
3841 REG_WRITE(ah, AR_RXCFG,
3842 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3844 REG_WRITE(ah, AR_RXCFG,
3845 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3848 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3850 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3853 bool ath9k_hw_disable(struct ath_hw *ah)
3855 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3858 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3861 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3863 struct ath9k_channel *chan = ah->curchan;
3864 struct ieee80211_channel *channel = chan->chan;
3866 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3868 ah->eep_ops->set_txpower(ah, chan,
3869 ath9k_regd_get_ctl(&ah->regulatory, chan),
3870 channel->max_antenna_gain * 2,
3871 channel->max_power * 2,
3872 min((u32) MAX_RATE_POWER,
3873 (u32) ah->regulatory.power_limit));
3876 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3878 memcpy(ah->macaddr, mac, ETH_ALEN);
3881 void ath9k_hw_setopmode(struct ath_hw *ah)
3883 ath9k_hw_set_operating_mode(ah, ah->opmode);
3886 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3888 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3889 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3892 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3894 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3895 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3898 void ath9k_hw_write_associd(struct ath_softc *sc)
3900 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3901 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3902 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3905 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3909 tsf = REG_READ(ah, AR_TSF_U32);
3910 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3915 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3917 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3918 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3921 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3923 ath9k_ps_wakeup(ah->ah_sc);
3924 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3925 AH_TSF_WRITE_TIMEOUT))
3926 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3927 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3929 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3930 ath9k_ps_restore(ah->ah_sc);
3933 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3936 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3938 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3943 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3945 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3946 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3947 ah->slottime = (u32) -1;
3950 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3956 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3960 if (mode == ATH9K_HT_MACMODE_2040 &&
3961 !ah->config.cwm_ignore_extcca)
3962 macmode = AR_2040_JOINED_RX_CLEAR;
3966 REG_WRITE(ah, AR_2040_MODE, macmode);
3969 /***************************/
3970 /* Bluetooth Coexistence */
3971 /***************************/
3973 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3975 /* connect bt_active to baseband */
3976 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3977 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3978 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3980 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3981 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3983 /* Set input mux for bt_active to gpio pin */
3984 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3985 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3988 /* Configure the desired gpio port for input */
3989 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3991 /* Configure the desired GPIO port for TX_FRAME output */
3992 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3993 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);