drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33
  34 MODULE_AUTHOR("Atheros Communications");
  35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  37 MODULE_LICENSE("Dual BSD/GPL");
  38
  39 static int __init ath9k_init(void)
  40 {
  41         return 0;
  42 }
  43 module_init(ath9k_init);
  44
  45 static void __exit ath9k_exit(void)
  46 {
  47         return;
  48 }
  49 module_exit(ath9k_exit);
  50
  51 /********************/
  52 /* Helper Functions */
  53 /********************/
  54
  55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  56 {
  57         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  58
  59         if (!ah->curchan) /* should really check for CCK instead */
  60                 return usecs *ATH9K_CLOCK_RATE_CCK;
  61         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  62                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  63         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  64 }
  65
  66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  69
  70         if (conf_is_ht40(conf))
  71                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  72         else
  73                 return ath9k_hw_mac_clks(ah, usecs);
  74 }
  75
  76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  77 {
  78         int i;
  79
  80         BUG_ON(timeout < AH_TIME_QUANTUM);
  81
  82         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  83                 if ((REG_READ(ah, reg) & mask) == val)
  84                         return true;
  85
  86                 udelay(AH_TIME_QUANTUM);
  87         }
  88
  89         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  90                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  91                   timeout, reg, REG_READ(ah, reg), mask, val);
  92
  93         return false;
  94 }
  95 EXPORT_SYMBOL(ath9k_hw_wait);
  96
  97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  98 {
  99         u32 retval;
 100         int i;
 101
 102         for (i = 0, retval = 0; i < n; i++) {
 103                 retval = (retval << 1) | (val & 1);
 104                 val >>= 1;
 105         }
 106         return retval;
 107 }
 108
 109 bool ath9k_get_channel_edges(struct ath_hw *ah,
 110                              u16 flags, u16 *low,
 111                              u16 *high)
 112 {
 113         struct ath9k_hw_capabilities *pCap = &ah->caps;
 114
 115         if (flags & CHANNEL_5GHZ) {
 116                 *low = pCap->low_5ghz_chan;
 117                 *high = pCap->high_5ghz_chan;
 118                 return true;
 119         }
 120         if ((flags & CHANNEL_2GHZ)) {
 121                 *low = pCap->low_2ghz_chan;
 122                 *high = pCap->high_2ghz_chan;
 123                 return true;
 124         }
 125         return false;
 126 }
 127
 128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 129                            u8 phy, int kbps,
 130                            u32 frameLen, u16 rateix,
 131                            bool shortPreamble)
 132 {
 133         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 134
 135         if (kbps == 0)
 136                 return 0;
 137
 138         switch (phy) {
 139         case WLAN_RC_PHY_CCK:
 140                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 141                 if (shortPreamble)
 142                         phyTime >>= 1;
 143                 numBits = frameLen << 3;
 144                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 145                 break;
 146         case WLAN_RC_PHY_OFDM:
 147                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 148                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 149                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 150                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 151                         txTime = OFDM_SIFS_TIME_QUARTER
 152                                 + OFDM_PREAMBLE_TIME_QUARTER
 153                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 154                 } else if (ah->curchan &&
 155                            IS_CHAN_HALF_RATE(ah->curchan)) {
 156                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 157                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 158                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 159                         txTime = OFDM_SIFS_TIME_HALF +
 160                                 OFDM_PREAMBLE_TIME_HALF
 161                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 162                 } else {
 163                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 164                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 165                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 166                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 167                                 + (numSymbols * OFDM_SYMBOL_TIME);
 168                 }
 169                 break;
 170         default:
 171                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 172                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 173                 txTime = 0;
 174                 break;
 175         }
 176
 177         return txTime;
 178 }
 179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 180
 181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 182                                   struct ath9k_channel *chan,
 183                                   struct chan_centers *centers)
 184 {
 185         int8_t extoff;
 186
 187         if (!IS_CHAN_HT40(chan)) {
 188                 centers->ctl_center = centers->ext_center =
 189                         centers->synth_center = chan->channel;
 190                 return;
 191         }
 192
 193         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 194             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 195                 centers->synth_center =
 196                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 197                 extoff = 1;
 198         } else {
 199                 centers->synth_center =
 200                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 201                 extoff = -1;
 202         }
 203
 204         centers->ctl_center =
 205                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 206         /* 25 MHz spacing is supported by hw but not on upper layers */
 207         centers->ext_center =
 208                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 209 }
 210
 211 /******************/
 212 /* Chip Revisions */
 213 /******************/
 214
 215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 216 {
 217         u32 val;
 218
 219         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 220
 221         if (val == 0xFF) {
 222                 val = REG_READ(ah, AR_SREV);
 223                 ah->hw_version.macVersion =
 224                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 225                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 226                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 227         } else {
 228                 if (!AR_SREV_9100(ah))
 229                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 230
 231                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 232
 233                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 234                         ah->is_pciexpress = true;
 235         }
 236 }
 237
 238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 239 {
 240         u32 val;
 241         int i;
 242
 243         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 244
 245         for (i = 0; i < 8; i++)
 246                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 247         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 248         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 249
 250         return ath9k_hw_reverse_bits(val, 8);
 251 }
 252
 253 /************************************/
 254 /* HW Attach, Detach, Init Routines */
 255 /************************************/
 256
 257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 258 {
 259         if (AR_SREV_9100(ah))
 260                 return;
 261
 262         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 268         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 269         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 270         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 271
 272         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 273 }
 274
 275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 276 {
 277         struct ath_common *common = ath9k_hw_common(ah);
 278         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 279         u32 regHold[2];
 280         u32 patternData[4] = { 0x55555555,
 281                                0xaaaaaaaa,
 282                                0x66666666,
 283                                0x99999999 };
 284         int i, j;
 285
 286         for (i = 0; i < 2; i++) {
 287                 u32 addr = regAddr[i];
 288                 u32 wrData, rdData;
 289
 290                 regHold[i] = REG_READ(ah, addr);
 291                 for (j = 0; j < 0x100; j++) {
 292                         wrData = (j << 16) | j;
 293                         REG_WRITE(ah, addr, wrData);
 294                         rdData = REG_READ(ah, addr);
 295                         if (rdData != wrData) {
 296                                 ath_print(common, ATH_DBG_FATAL,
 297                                           "address test failed "
 298                                           "addr: 0x%08x - wr:0x%08x != "
 299                                           "rd:0x%08x\n",
 300                                           addr, wrData, rdData);
 301                                 return false;
 302                         }
 303                 }
 304                 for (j = 0; j < 4; j++) {
 305                         wrData = patternData[j];
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (wrData != rdData) {
 309                                 ath_print(common, ATH_DBG_FATAL,
 310                                           "address test failed "
 311                                           "addr: 0x%08x - wr:0x%08x != "
 312                                           "rd:0x%08x\n",
 313                                           addr, wrData, rdData);
 314                                 return false;
 315                         }
 316                 }
 317                 REG_WRITE(ah, regAddr[i], regHold[i]);
 318         }
 319         udelay(100);
 320
 321         return true;
 322 }
 323
 324 static void ath9k_hw_init_config(struct ath_hw *ah)
 325 {
 326         int i;
 327
 328         ah->config.dma_beacon_response_time = 2;
 329         ah->config.sw_beacon_response_time = 10;
 330         ah->config.additional_swba_backoff = 0;
 331         ah->config.ack_6mb = 0x0;
 332         ah->config.cwm_ignore_extcca = 0;
 333         ah->config.pcie_powersave_enable = 0;
 334         ah->config.pcie_clock_req = 0;
 335         ah->config.pcie_waen = 0;
 336         ah->config.analog_shiftreg = 1;
 337         ah->config.ofdm_trig_low = 200;
 338         ah->config.ofdm_trig_high = 500;
 339         ah->config.cck_trig_high = 200;
 340         ah->config.cck_trig_low = 100;
 341         ah->config.enable_ani = 1;
 342
 343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 344                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 345                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 346         }
 347
 348         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 349                 ah->config.ht_enable = 1;
 350         else
 351                 ah->config.ht_enable = 0;
 352
 353         ah->config.rx_intr_mitigation = true;
 354
 355         /*
 356          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 357          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 358          * This means we use it for all AR5416 devices, and the few
 359          * minor PCI AR9280 devices out there.
 360          *
 361          * Serialization is required because these devices do not handle
 362          * well the case of two concurrent reads/writes due to the latency
 363          * involved. During one read/write another read/write can be issued
 364          * on another CPU while the previous read/write may still be working
 365          * on our hardware, if we hit this case the hardware poops in a loop.
 366          * We prevent this by serializing reads and writes.
 367          *
 368          * This issue is not present on PCI-Express devices or pre-AR5416
 369          * devices (legacy, 802.11abg).
 370          */
 371         if (num_possible_cpus() > 1)
 372                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 373 }
 374 EXPORT_SYMBOL(ath9k_hw_init);
 375
 376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 377 {
 378         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 379
 380         regulatory->country_code = CTRY_DEFAULT;
 381         regulatory->power_limit = MAX_RATE_POWER;
 382         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 383
 384         ah->hw_version.magic = AR5416_MAGIC;
 385         ah->hw_version.subvendorid = 0;
 386
 387         ah->ah_flags = 0;
 388         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 389                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 390         if (!AR_SREV_9100(ah))
 391                 ah->ah_flags = AH_USE_EEPROM;
 392
 393         ah->atim_window = 0;
 394         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 395         ah->beacon_interval = 100;
 396         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 397         ah->slottime = (u32) -1;
 398         ah->globaltxtimeout = (u32) -1;
 399         ah->power_mode = ATH9K_PM_UNDEFINED;
 400 }
 401
 402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 403 {
 404         u32 val;
 405
 406         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 407
 408         val = ath9k_hw_get_radiorev(ah);
 409         switch (val & AR_RADIO_SREV_MAJOR) {
 410         case 0:
 411                 val = AR_RAD5133_SREV_MAJOR;
 412                 break;
 413         case AR_RAD5133_SREV_MAJOR:
 414         case AR_RAD5122_SREV_MAJOR:
 415         case AR_RAD2133_SREV_MAJOR:
 416         case AR_RAD2122_SREV_MAJOR:
 417                 break;
 418         default:
 419                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 420                           "Radio Chip Rev 0x%02X not supported\n",
 421                           val & AR_RADIO_SREV_MAJOR);
 422                 return -EOPNOTSUPP;
 423         }
 424
 425         ah->hw_version.analog5GhzRev = val;
 426
 427         return 0;
 428 }
 429
 430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 431 {
 432         struct ath_common *common = ath9k_hw_common(ah);
 433         u32 sum;
 434         int i;
 435         u16 eeval;
 436
 437         sum = 0;
 438         for (i = 0; i < 3; i++) {
 439                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 440                 sum += eeval;
 441                 common->macaddr[2 * i] = eeval >> 8;
 442                 common->macaddr[2 * i + 1] = eeval & 0xff;
 443         }
 444         if (sum == 0 || sum == 0xffff * 3)
 445                 return -EADDRNOTAVAIL;
 446
 447         return 0;
 448 }
 449
 450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 451 {
 452         u32 rxgain_type;
 453
 454         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 455                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 456
 457                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 458                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 459                         ar9280Modes_backoff_13db_rxgain_9280_2,
 460                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 461                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 462                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 463                         ar9280Modes_backoff_23db_rxgain_9280_2,
 464                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 465                 else
 466                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 467                         ar9280Modes_original_rxgain_9280_2,
 468                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 469         } else {
 470                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 471                         ar9280Modes_original_rxgain_9280_2,
 472                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 473         }
 474 }
 475
 476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 477 {
 478         u32 txgain_type;
 479
 480         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 481                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 482
 483                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 484                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 485                         ar9280Modes_high_power_tx_gain_9280_2,
 486                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 487                 else
 488                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 489                         ar9280Modes_original_tx_gain_9280_2,
 490                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 491         } else {
 492                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 493                 ar9280Modes_original_tx_gain_9280_2,
 494                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 495         }
 496 }
 497
 498 static int ath9k_hw_post_init(struct ath_hw *ah)
 499 {
 500         int ecode;
 501
 502         if (!ath9k_hw_chip_test(ah))
 503                 return -ENODEV;
 504
 505         ecode = ath9k_hw_rf_claim(ah);
 506         if (ecode != 0)
 507                 return ecode;
 508
 509         ecode = ath9k_hw_eeprom_init(ah);
 510         if (ecode != 0)
 511                 return ecode;
 512
 513         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 514                   "Eeprom VER: %d, REV: %d\n",
 515                   ah->eep_ops->get_eeprom_ver(ah),
 516                   ah->eep_ops->get_eeprom_rev(ah));
 517
 518         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 519                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 520                 if (ecode) {
 521                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 522                                   "Failed allocating banks for "
 523                                   "external radio\n");
 524                         return ecode;
 525                 }
 526         }
 527
 528         if (!AR_SREV_9100(ah)) {
 529                 ath9k_hw_ani_setup(ah);
 530                 ath9k_hw_ani_init(ah);
 531         }
 532
 533         return 0;
 534 }
 535
 536 static bool ath9k_hw_devid_supported(u16 devid)
 537 {
 538         switch (devid) {
 539         case AR5416_DEVID_PCI:
 540         case AR5416_DEVID_PCIE:
 541         case AR5416_AR9100_DEVID:
 542         case AR9160_DEVID_PCI:
 543         case AR9280_DEVID_PCI:
 544         case AR9280_DEVID_PCIE:
 545         case AR9285_DEVID_PCIE:
 546         case AR5416_DEVID_AR9287_PCI:
 547         case AR5416_DEVID_AR9287_PCIE:
 548         case AR9271_USB:
 549         case AR2427_DEVID_PCIE:
 550                 return true;
 551         default:
 552                 break;
 553         }
 554         return false;
 555 }
 556
 557 static bool ath9k_hw_macversion_supported(u32 macversion)
 558 {
 559         switch (macversion) {
 560         case AR_SREV_VERSION_5416_PCI:
 561         case AR_SREV_VERSION_5416_PCIE:
 562         case AR_SREV_VERSION_9160:
 563         case AR_SREV_VERSION_9100:
 564         case AR_SREV_VERSION_9280:
 565         case AR_SREV_VERSION_9285:
 566         case AR_SREV_VERSION_9287:
 567         case AR_SREV_VERSION_9271:
 568                 return true;
 569         default:
 570                 break;
 571         }
 572         return false;
 573 }
 574
 575 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 576 {
 577         if (AR_SREV_9160_10_OR_LATER(ah)) {
 578                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 579                         ah->iq_caldata.calData = &iq_cal_single_sample;
 580                         ah->adcgain_caldata.calData =
 581                                 &adc_gain_cal_single_sample;
 582                         ah->adcdc_caldata.calData =
 583                                 &adc_dc_cal_single_sample;
 584                         ah->adcdc_calinitdata.calData =
 585                                 &adc_init_dc_cal;
 586                 } else {
 587                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 588                         ah->adcgain_caldata.calData =
 589                                 &adc_gain_cal_multi_sample;
 590                         ah->adcdc_caldata.calData =
 591                                 &adc_dc_cal_multi_sample;
 592                         ah->adcdc_calinitdata.calData =
 593                                 &adc_init_dc_cal;
 594                 }
 595                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 596         }
 597 }
 598
 599 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 600 {
 601         if (AR_SREV_9271(ah)) {
 602                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 603                                ARRAY_SIZE(ar9271Modes_9271), 6);
 604                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 605                                ARRAY_SIZE(ar9271Common_9271), 2);
 606                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 607                                ar9271Modes_9271_1_0_only,
 608                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 609                 return;
 610         }
 611
 612         if (AR_SREV_9287_11_OR_LATER(ah)) {
 613                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 614                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 615                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 616                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 617                 if (ah->config.pcie_clock_req)
 618                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 619                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 620                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 621                 else
 622                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 623                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 624                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 625                                         2);
 626         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 627                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 628                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 629                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 630                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 631
 632                 if (ah->config.pcie_clock_req)
 633                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 634                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 635                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 636                 else
 637                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 638                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 639                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 640                                   2);
 641         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 642
 643
 644                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 645                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 646                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 647                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 648
 649                 if (ah->config.pcie_clock_req) {
 650                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 651                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 652                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 653                 } else {
 654                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 655                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 656                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 657                                   2);
 658                 }
 659         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 660                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 661                                ARRAY_SIZE(ar9285Modes_9285), 6);
 662                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 663                                ARRAY_SIZE(ar9285Common_9285), 2);
 664
 665                 if (ah->config.pcie_clock_req) {
 666                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 667                         ar9285PciePhy_clkreq_off_L1_9285,
 668                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 669                 } else {
 670                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 671                         ar9285PciePhy_clkreq_always_on_L1_9285,
 672                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 673                 }
 674         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 675                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 676                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 677                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 678                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 679
 680                 if (ah->config.pcie_clock_req) {
 681                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 682                                ar9280PciePhy_clkreq_off_L1_9280,
 683                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 684                 } else {
 685                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 686                                ar9280PciePhy_clkreq_always_on_L1_9280,
 687                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 688                 }
 689                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 690                                ar9280Modes_fast_clock_9280_2,
 691                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 692         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 693                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 694                                ARRAY_SIZE(ar9280Modes_9280), 6);
 695                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 696                                ARRAY_SIZE(ar9280Common_9280), 2);
 697         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 698                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 699                                ARRAY_SIZE(ar5416Modes_9160), 6);
 700                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 701                                ARRAY_SIZE(ar5416Common_9160), 2);
 702                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 703                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 704                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 705                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 706                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 707                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 708                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 709                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 710                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 711                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 712                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 713                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 714                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 715                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 716                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 717                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 718                 if (AR_SREV_9160_11(ah)) {
 719                         INIT_INI_ARRAY(&ah->iniAddac,
 720                                        ar5416Addac_91601_1,
 721                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 722                 } else {
 723                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 724                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 725                 }
 726         } else if (AR_SREV_9100_OR_LATER(ah)) {
 727                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 728                                ARRAY_SIZE(ar5416Modes_9100), 6);
 729                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 730                                ARRAY_SIZE(ar5416Common_9100), 2);
 731                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 732                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 733                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 734                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 735                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 736                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 737                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 738                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 739                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 740                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 741                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 742                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 743                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 744                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 745                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 746                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 747                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 748                                ARRAY_SIZE(ar5416Addac_9100), 2);
 749         } else {
 750                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 751                                ARRAY_SIZE(ar5416Modes), 6);
 752                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 753                                ARRAY_SIZE(ar5416Common), 2);
 754                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 755                                ARRAY_SIZE(ar5416Bank0), 2);
 756                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 757                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 758                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 759                                ARRAY_SIZE(ar5416Bank1), 2);
 760                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 761                                ARRAY_SIZE(ar5416Bank2), 2);
 762                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 763                                ARRAY_SIZE(ar5416Bank3), 3);
 764                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 765                                ARRAY_SIZE(ar5416Bank6), 3);
 766                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 767                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 768                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 769                                ARRAY_SIZE(ar5416Bank7), 2);
 770                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 771                                ARRAY_SIZE(ar5416Addac), 2);
 772         }
 773 }
 774
 775 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 776 {
 777         if (AR_SREV_9287_11_OR_LATER(ah))
 778                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 779                 ar9287Modes_rx_gain_9287_1_1,
 780                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 781         else if (AR_SREV_9287_10(ah))
 782                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 783                 ar9287Modes_rx_gain_9287_1_0,
 784                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 785         else if (AR_SREV_9280_20(ah))
 786                 ath9k_hw_init_rxgain_ini(ah);
 787
 788         if (AR_SREV_9287_11_OR_LATER(ah)) {
 789                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 790                 ar9287Modes_tx_gain_9287_1_1,
 791                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 792         } else if (AR_SREV_9287_10(ah)) {
 793                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 794                 ar9287Modes_tx_gain_9287_1_0,
 795                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 796         } else if (AR_SREV_9280_20(ah)) {
 797                 ath9k_hw_init_txgain_ini(ah);
 798         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 799                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 800
 801                 /* txgain table */
 802                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 803                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 804                         ar9285Modes_high_power_tx_gain_9285_1_2,
 805                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 806                 } else {
 807                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 808                         ar9285Modes_original_tx_gain_9285_1_2,
 809                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 810                 }
 811
 812         }
 813 }
 814
 815 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 816 {
 817         u32 i, j;
 818
 819         if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 820
 821                 /* EEPROM Fixup */
 822                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 823                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 824
 825                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 826                                 u32 val = INI_RA(&ah->iniModes, i, j);
 827
 828                                 INI_RA(&ah->iniModes, i, j) =
 829                                         ath9k_hw_ini_fixup(ah,
 830                                                            &ah->eeprom.def,
 831                                                            reg, val);
 832                         }
 833                 }
 834         }
 835 }
 836
 837 int ath9k_hw_init(struct ath_hw *ah)
 838 {
 839         struct ath_common *common = ath9k_hw_common(ah);
 840         int r = 0;
 841
 842         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 843                 ath_print(common, ATH_DBG_FATAL,
 844                           "Unsupported device ID: 0x%0x\n",
 845                           ah->hw_version.devid);
 846                 return -EOPNOTSUPP;
 847         }
 848
 849         ath9k_hw_init_defaults(ah);
 850         ath9k_hw_init_config(ah);
 851
 852         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 853                 ath_print(common, ATH_DBG_FATAL,
 854                           "Couldn't reset chip\n");
 855                 return -EIO;
 856         }
 857
 858         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 859                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 860                 return -EIO;
 861         }
 862
 863         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 864                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 865                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 866                         ah->config.serialize_regmode =
 867                                 SER_REG_MODE_ON;
 868                 } else {
 869                         ah->config.serialize_regmode =
 870                                 SER_REG_MODE_OFF;
 871                 }
 872         }
 873
 874         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 875                 ah->config.serialize_regmode);
 876
 877         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 878                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 879         else
 880                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 881
 882         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 883                 ath_print(common, ATH_DBG_FATAL,
 884                           "Mac Chip Rev 0x%02x.%x is not supported by "
 885                           "this driver\n", ah->hw_version.macVersion,
 886                           ah->hw_version.macRev);
 887                 return -EOPNOTSUPP;
 888         }
 889
 890         if (AR_SREV_9100(ah)) {
 891                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 892                 ah->supp_cals = IQ_MISMATCH_CAL;
 893                 ah->is_pciexpress = false;
 894         }
 895
 896         if (AR_SREV_9271(ah))
 897                 ah->is_pciexpress = false;
 898
 899         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 900
 901         ath9k_hw_init_cal_settings(ah);
 902
 903         ah->ani_function = ATH9K_ANI_ALL;
 904         if (AR_SREV_9280_10_OR_LATER(ah)) {
 905                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 906                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 907                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 908         } else {
 909                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 910                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 911         }
 912
 913         ath9k_hw_init_mode_regs(ah);
 914
 915         if (ah->is_pciexpress)
 916                 ath9k_hw_configpcipowersave(ah, 0, 0);
 917         else
 918                 ath9k_hw_disablepcie(ah);
 919
 920         /* Support for Japan ch.14 (2484) spread */
 921         if (AR_SREV_9287_11_OR_LATER(ah)) {
 922                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 923                        ar9287Common_normal_cck_fir_coeff_92871_1,
 924                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 925                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 926                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 927                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 928         }
 929
 930         r = ath9k_hw_post_init(ah);
 931         if (r)
 932                 return r;
 933
 934         ath9k_hw_init_mode_gain_regs(ah);
 935         r = ath9k_hw_fill_cap_info(ah);
 936         if (r)
 937                 return r;
 938
 939         ath9k_hw_init_eeprom_fix(ah);
 940
 941         r = ath9k_hw_init_macaddr(ah);
 942         if (r) {
 943                 ath_print(common, ATH_DBG_FATAL,
 944                           "Failed to initialize MAC address\n");
 945                 return r;
 946         }
 947
 948         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 949                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 950         else
 951                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 952
 953         ath9k_init_nfcal_hist_buffer(ah);
 954
 955         common->state = ATH_HW_INITIALIZED;
 956
 957         return 0;
 958 }
 959
 960 static void ath9k_hw_init_bb(struct ath_hw *ah,
 961                              struct ath9k_channel *chan)
 962 {
 963         u32 synthDelay;
 964
 965         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 966         if (IS_CHAN_B(chan))
 967                 synthDelay = (4 * synthDelay) / 22;
 968         else
 969                 synthDelay /= 10;
 970
 971         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 972
 973         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 974 }
 975
 976 static void ath9k_hw_init_qos(struct ath_hw *ah)
 977 {
 978         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 979         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 980
 981         REG_WRITE(ah, AR_QOS_NO_ACK,
 982                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 983                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 984                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 985
 986         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 987         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 988         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 989         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 990         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 991 }
 992
 993 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
 994 {
 995         u32 lcr;
 996         u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
 997
 998         lcr = REG_READ(ah , 0x5100c);
 999         lcr |= 0x80;
1000
1001         REG_WRITE(ah, 0x5100c, lcr);
1002         REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1003         REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1004
1005         lcr &= ~0x80;
1006         REG_WRITE(ah, 0x5100c, lcr);
1007 }
1008
1009 static void ath9k_hw_init_pll(struct ath_hw *ah,
1010                               struct ath9k_channel *chan)
1011 {
1012         u32 pll;
1013
1014         if (AR_SREV_9100(ah)) {
1015                 if (chan && IS_CHAN_5GHZ(chan))
1016                         pll = 0x1450;
1017                 else
1018                         pll = 0x1458;
1019         } else {
1020                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1021                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1022
1023                         if (chan && IS_CHAN_HALF_RATE(chan))
1024                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1025                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1026                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1027
1028                         if (chan && IS_CHAN_5GHZ(chan)) {
1029                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1030
1031
1032                                 if (AR_SREV_9280_20(ah)) {
1033                                         if (((chan->channel % 20) == 0)
1034                                             || ((chan->channel % 10) == 0))
1035                                                 pll = 0x2850;
1036                                         else
1037                                                 pll = 0x142c;
1038                                 }
1039                         } else {
1040                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1041                         }
1042
1043                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1044
1045                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1046
1047                         if (chan && IS_CHAN_HALF_RATE(chan))
1048                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1049                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1050                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1051
1052                         if (chan && IS_CHAN_5GHZ(chan))
1053                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1054                         else
1055                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1056                 } else {
1057                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1058
1059                         if (chan && IS_CHAN_HALF_RATE(chan))
1060                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1061                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1062                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1063
1064                         if (chan && IS_CHAN_5GHZ(chan))
1065                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1066                         else
1067                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1068                 }
1069         }
1070         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1071
1072         /* Switch the core clock for ar9271 to 117Mhz */
1073         if (AR_SREV_9271(ah)) {
1074                 if ((pll == 0x142c) || (pll == 0x2850) ) {
1075                         udelay(500);
1076                         /* set CLKOBS to output AHB clock */
1077                         REG_WRITE(ah, 0x7020, 0xe);
1078                         /*
1079                          * 0x304: 117Mhz, ahb_ratio: 1x1
1080                          * 0x306: 40Mhz, ahb_ratio: 1x1
1081                          */
1082                         REG_WRITE(ah, 0x50040, 0x304);
1083                         /*
1084                          * makes adjustments for the baud dividor to keep the
1085                          * targetted baud rate based on the used core clock.
1086                          */
1087                         ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1088                                                     AR9271_TARGET_BAUD_RATE);
1089                 }
1090         }
1091
1092         udelay(RTC_PLL_SETTLE_DELAY);
1093
1094         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1095 }
1096
1097 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1098 {
1099         int rx_chainmask, tx_chainmask;
1100
1101         rx_chainmask = ah->rxchainmask;
1102         tx_chainmask = ah->txchainmask;
1103
1104         switch (rx_chainmask) {
1105         case 0x5:
1106                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1107                             AR_PHY_SWAP_ALT_CHAIN);
1108         case 0x3:
1109                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1110                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1111                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1112                         break;
1113                 }
1114         case 0x1:
1115         case 0x2:
1116         case 0x7:
1117                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1118                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1119                 break;
1120         default:
1121                 break;
1122         }
1123
1124         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1125         if (tx_chainmask == 0x5) {
1126                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1127                             AR_PHY_SWAP_ALT_CHAIN);
1128         }
1129         if (AR_SREV_9100(ah))
1130                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1131                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1132 }
1133
1134 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1135                                           enum nl80211_iftype opmode)
1136 {
1137         ah->mask_reg = AR_IMR_TXERR |
1138                 AR_IMR_TXURN |
1139                 AR_IMR_RXERR |
1140                 AR_IMR_RXORN |
1141                 AR_IMR_BCNMISC;
1142
1143         if (ah->config.rx_intr_mitigation)
1144                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1145         else
1146                 ah->mask_reg |= AR_IMR_RXOK;
1147
1148         ah->mask_reg |= AR_IMR_TXOK;
1149
1150         if (opmode == NL80211_IFTYPE_AP)
1151                 ah->mask_reg |= AR_IMR_MIB;
1152
1153         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1154         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1155
1156         if (!AR_SREV_9100(ah)) {
1157                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1158                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1159                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1160         }
1161 }
1162
1163 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1164 {
1165         u32 val = ath9k_hw_mac_to_clks(ah, us);
1166         val = min(val, (u32) 0xFFFF);
1167         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1168 }
1169
1170 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1171 {
1172         u32 val = ath9k_hw_mac_to_clks(ah, us);
1173         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1174         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1175 }
1176
1177 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1178 {
1179         u32 val = ath9k_hw_mac_to_clks(ah, us);
1180         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1181         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1182 }
1183
1184 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1185 {
1186         if (tu > 0xFFFF) {
1187                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1188                           "bad global tx timeout %u\n", tu);
1189                 ah->globaltxtimeout = (u32) -1;
1190                 return false;
1191         } else {
1192                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1193                 ah->globaltxtimeout = tu;
1194                 return true;
1195         }
1196 }
1197
1198 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1199 {
1200         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1201         int acktimeout;
1202         int slottime;
1203         int sifstime;
1204
1205         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1206                   ah->misc_mode);
1207
1208         if (ah->misc_mode != 0)
1209                 REG_WRITE(ah, AR_PCU_MISC,
1210                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1211
1212         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1213                 sifstime = 16;
1214         else
1215                 sifstime = 10;
1216
1217         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1218         slottime = ah->slottime + 3 * ah->coverage_class;
1219         acktimeout = slottime + sifstime;
1220         ath9k_hw_setslottime(ah, slottime);
1221         ath9k_hw_set_ack_timeout(ah, acktimeout);
1222         ath9k_hw_set_cts_timeout(ah, acktimeout);
1223         if (ah->globaltxtimeout != (u32) -1)
1224                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1225 }
1226 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1227
1228 void ath9k_hw_deinit(struct ath_hw *ah)
1229 {
1230         struct ath_common *common = ath9k_hw_common(ah);
1231
1232         if (common->state <= ATH_HW_INITIALIZED)
1233                 goto free_hw;
1234
1235         if (!AR_SREV_9100(ah))
1236                 ath9k_hw_ani_disable(ah);
1237
1238         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1239
1240 free_hw:
1241         if (!AR_SREV_9280_10_OR_LATER(ah))
1242                 ath9k_hw_rf_free_ext_banks(ah);
1243         kfree(ah);
1244         ah = NULL;
1245 }
1246 EXPORT_SYMBOL(ath9k_hw_deinit);
1247
1248 /*******/
1249 /* INI */
1250 /*******/
1251
1252 static void ath9k_hw_override_ini(struct ath_hw *ah,
1253                                   struct ath9k_channel *chan)
1254 {
1255         u32 val;
1256
1257         if (AR_SREV_9271(ah)) {
1258                 /*
1259                  * Enable spectral scan to solution for issues with stuck
1260                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1261                  * AR9271 1.1
1262                  */
1263                 if (AR_SREV_9271_10(ah)) {
1264                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1265                               AR_PHY_SPECTRAL_SCAN_ENABLE;
1266                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1267                 }
1268                 else if (AR_SREV_9271_11(ah))
1269                         /*
1270                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1271                          * present on AR9271 1.1
1272                          */
1273                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1274                 return;
1275         }
1276
1277         /*
1278          * Set the RX_ABORT and RX_DIS and clear if off only after
1279          * RXE is set for MAC. This prevents frames with corrupted
1280          * descriptor status.
1281          */
1282         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1283
1284         if (AR_SREV_9280_10_OR_LATER(ah)) {
1285                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1286                                (~AR_PCU_MISC_MODE2_HWWAR1);
1287
1288                 if (AR_SREV_9287_10_OR_LATER(ah))
1289                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1290
1291                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1292         }
1293
1294         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1295             AR_SREV_9280_10_OR_LATER(ah))
1296                 return;
1297         /*
1298          * Disable BB clock gating
1299          * Necessary to avoid issues on AR5416 2.0
1300          */
1301         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1302 }
1303
1304 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1305                               struct ar5416_eeprom_def *pEepData,
1306                               u32 reg, u32 value)
1307 {
1308         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1309         struct ath_common *common = ath9k_hw_common(ah);
1310
1311         switch (ah->hw_version.devid) {
1312         case AR9280_DEVID_PCI:
1313                 if (reg == 0x7894) {
1314                         ath_print(common, ATH_DBG_EEPROM,
1315                                 "ini VAL: %x  EEPROM: %x\n", value,
1316                                 (pBase->version & 0xff));
1317
1318                         if ((pBase->version & 0xff) > 0x0a) {
1319                                 ath_print(common, ATH_DBG_EEPROM,
1320                                           "PWDCLKIND: %d\n",
1321                                           pBase->pwdclkind);
1322                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1323                                 value |= AR_AN_TOP2_PWDCLKIND &
1324                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1325                         } else {
1326                                 ath_print(common, ATH_DBG_EEPROM,
1327                                           "PWDCLKIND Earlier Rev\n");
1328                         }
1329
1330                         ath_print(common, ATH_DBG_EEPROM,
1331                                   "final ini VAL: %x\n", value);
1332                 }
1333                 break;
1334         }
1335
1336         return value;
1337 }
1338
1339 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1340                               struct ar5416_eeprom_def *pEepData,
1341                               u32 reg, u32 value)
1342 {
1343         if (ah->eep_map == EEP_MAP_4KBITS)
1344                 return value;
1345         else
1346                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1347 }
1348
1349 static void ath9k_olc_init(struct ath_hw *ah)
1350 {
1351         u32 i;
1352
1353         if (OLC_FOR_AR9287_10_LATER) {
1354                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1355                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1356                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1357                                 AR9287_AN_TXPC0_TXPCMODE,
1358                                 AR9287_AN_TXPC0_TXPCMODE_S,
1359                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1360                 udelay(100);
1361         } else {
1362                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1363                         ah->originalGain[i] =
1364                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1365                                                 AR_PHY_TX_GAIN);
1366                 ah->PDADCdelta = 0;
1367         }
1368 }
1369
1370 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1371                               struct ath9k_channel *chan)
1372 {
1373         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1374
1375         if (IS_CHAN_B(chan))
1376                 ctl |= CTL_11B;
1377         else if (IS_CHAN_G(chan))
1378                 ctl |= CTL_11G;
1379         else
1380                 ctl |= CTL_11A;
1381
1382         return ctl;
1383 }
1384
1385 static int ath9k_hw_process_ini(struct ath_hw *ah,
1386                                 struct ath9k_channel *chan)
1387 {
1388         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1389         int i, regWrites = 0;
1390         struct ieee80211_channel *channel = chan->chan;
1391         u32 modesIndex, freqIndex;
1392
1393         switch (chan->chanmode) {
1394         case CHANNEL_A:
1395         case CHANNEL_A_HT20:
1396                 modesIndex = 1;
1397                 freqIndex = 1;
1398                 break;
1399         case CHANNEL_A_HT40PLUS:
1400         case CHANNEL_A_HT40MINUS:
1401                 modesIndex = 2;
1402                 freqIndex = 1;
1403                 break;
1404         case CHANNEL_G:
1405         case CHANNEL_G_HT20:
1406         case CHANNEL_B:
1407                 modesIndex = 4;
1408                 freqIndex = 2;
1409                 break;
1410         case CHANNEL_G_HT40PLUS:
1411         case CHANNEL_G_HT40MINUS:
1412                 modesIndex = 3;
1413                 freqIndex = 2;
1414                 break;
1415
1416         default:
1417                 return -EINVAL;
1418         }
1419
1420         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1421         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1422         ah->eep_ops->set_addac(ah, chan);
1423
1424         if (AR_SREV_5416_22_OR_LATER(ah)) {
1425                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1426         } else {
1427                 struct ar5416IniArray temp;
1428                 u32 addacSize =
1429                         sizeof(u32) * ah->iniAddac.ia_rows *
1430                         ah->iniAddac.ia_columns;
1431
1432                 memcpy(ah->addac5416_21,
1433                        ah->iniAddac.ia_array, addacSize);
1434
1435                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1436
1437                 temp.ia_array = ah->addac5416_21;
1438                 temp.ia_columns = ah->iniAddac.ia_columns;
1439                 temp.ia_rows = ah->iniAddac.ia_rows;
1440                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1441         }
1442
1443         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1444
1445         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1446                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1447                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1448
1449                 REG_WRITE(ah, reg, val);
1450
1451                 if (reg >= 0x7800 && reg < 0x78a0
1452                     && ah->config.analog_shiftreg) {
1453                         udelay(100);
1454                 }
1455
1456                 DO_DELAY(regWrites);
1457         }
1458
1459         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1460                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1461
1462         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1463             AR_SREV_9287_10_OR_LATER(ah))
1464                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1465
1466         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1467                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1468                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1469
1470                 REG_WRITE(ah, reg, val);
1471
1472                 if (reg >= 0x7800 && reg < 0x78a0
1473                     && ah->config.analog_shiftreg) {
1474                         udelay(100);
1475                 }
1476
1477                 DO_DELAY(regWrites);
1478         }
1479
1480         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1481
1482         if (AR_SREV_9271_10(ah))
1483                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1484                                 modesIndex, regWrites);
1485
1486         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1487                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1488                                 regWrites);
1489         }
1490
1491         ath9k_hw_override_ini(ah, chan);
1492         ath9k_hw_set_regs(ah, chan);
1493         ath9k_hw_init_chain_masks(ah);
1494
1495         if (OLC_FOR_AR9280_20_LATER)
1496                 ath9k_olc_init(ah);
1497
1498         ah->eep_ops->set_txpower(ah, chan,
1499                                  ath9k_regd_get_ctl(regulatory, chan),
1500                                  channel->max_antenna_gain * 2,
1501                                  channel->max_power * 2,
1502                                  min((u32) MAX_RATE_POWER,
1503                                  (u32) regulatory->power_limit));
1504
1505         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1506                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1507                           "ar5416SetRfRegs failed\n");
1508                 return -EIO;
1509         }
1510
1511         return 0;
1512 }
1513
1514 /****************************************/
1515 /* Reset and Channel Switching Routines */
1516 /****************************************/
1517
1518 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1519 {
1520         u32 rfMode = 0;
1521
1522         if (chan == NULL)
1523                 return;
1524
1525         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1526                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1527
1528         if (!AR_SREV_9280_10_OR_LATER(ah))
1529                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1530                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1531
1532         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1533                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1534
1535         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1536 }
1537
1538 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1539 {
1540         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1541 }
1542
1543 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1544 {
1545         u32 regval;
1546
1547         /*
1548          * set AHB_MODE not to do cacheline prefetches
1549         */
1550         regval = REG_READ(ah, AR_AHB_MODE);
1551         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1552
1553         /*
1554          * let mac dma reads be in 128 byte chunks
1555          */
1556         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1557         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1558
1559         /*
1560          * Restore TX Trigger Level to its pre-reset value.
1561          * The initial value depends on whether aggregation is enabled, and is
1562          * adjusted whenever underruns are detected.
1563          */
1564         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1565
1566         /*
1567          * let mac dma writes be in 128 byte chunks
1568          */
1569         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1570         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1571
1572         /*
1573          * Setup receive FIFO threshold to hold off TX activities
1574          */
1575         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1576
1577         /*
1578          * reduce the number of usable entries in PCU TXBUF to avoid
1579          * wrap around issues.
1580          */
1581         if (AR_SREV_9285(ah)) {
1582                 /* For AR9285 the number of Fifos are reduced to half.
1583                  * So set the usable tx buf size also to half to
1584                  * avoid data/delimiter underruns
1585                  */
1586                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1587                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1588         } else if (!AR_SREV_9271(ah)) {
1589                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1590                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1591         }
1592 }
1593
1594 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1595 {
1596         u32 val;
1597
1598         val = REG_READ(ah, AR_STA_ID1);
1599         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1600         switch (opmode) {
1601         case NL80211_IFTYPE_AP:
1602                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1603                           | AR_STA_ID1_KSRCH_MODE);
1604                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1605                 break;
1606         case NL80211_IFTYPE_ADHOC:
1607         case NL80211_IFTYPE_MESH_POINT:
1608                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1609                           | AR_STA_ID1_KSRCH_MODE);
1610                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1611                 break;
1612         case NL80211_IFTYPE_STATION:
1613         case NL80211_IFTYPE_MONITOR:
1614                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1615                 break;
1616         }
1617 }
1618
1619 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1620                                                  u32 coef_scaled,
1621                                                  u32 *coef_mantissa,
1622                                                  u32 *coef_exponent)
1623 {
1624         u32 coef_exp, coef_man;
1625
1626         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1627                 if ((coef_scaled >> coef_exp) & 0x1)
1628                         break;
1629
1630         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1631
1632         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1633
1634         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1635         *coef_exponent = coef_exp - 16;
1636 }
1637
1638 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1639                                      struct ath9k_channel *chan)
1640 {
1641         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1642         u32 clockMhzScaled = 0x64000000;
1643         struct chan_centers centers;
1644
1645         if (IS_CHAN_HALF_RATE(chan))
1646                 clockMhzScaled = clockMhzScaled >> 1;
1647         else if (IS_CHAN_QUARTER_RATE(chan))
1648                 clockMhzScaled = clockMhzScaled >> 2;
1649
1650         ath9k_hw_get_channel_centers(ah, chan, &centers);
1651         coef_scaled = clockMhzScaled / centers.synth_center;
1652
1653         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1654                                       &ds_coef_exp);
1655
1656         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1657                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1658         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1659                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1660
1661         coef_scaled = (9 * coef_scaled) / 10;
1662
1663         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1664                                       &ds_coef_exp);
1665
1666         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1667                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1668         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1669                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1670 }
1671
1672 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1673 {
1674         u32 rst_flags;
1675         u32 tmpReg;
1676
1677         if (AR_SREV_9100(ah)) {
1678                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1679                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1680                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1681                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1682                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1683         }
1684
1685         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1686                   AR_RTC_FORCE_WAKE_ON_INT);
1687
1688         if (AR_SREV_9100(ah)) {
1689                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1690                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1691         } else {
1692                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1693                 if (tmpReg &
1694                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1695                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1696                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1697                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1698                 } else {
1699                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1700                 }
1701
1702                 rst_flags = AR_RTC_RC_MAC_WARM;
1703                 if (type == ATH9K_RESET_COLD)
1704                         rst_flags |= AR_RTC_RC_MAC_COLD;
1705         }
1706
1707         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1708         udelay(50);
1709
1710         REG_WRITE(ah, AR_RTC_RC, 0);
1711         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1712                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1713                           "RTC stuck in MAC reset\n");
1714                 return false;
1715         }
1716
1717         if (!AR_SREV_9100(ah))
1718                 REG_WRITE(ah, AR_RC, 0);
1719
1720         if (AR_SREV_9100(ah))
1721                 udelay(50);
1722
1723         return true;
1724 }
1725
1726 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1727 {
1728         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1729                   AR_RTC_FORCE_WAKE_ON_INT);
1730
1731         if (!AR_SREV_9100(ah))
1732                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1733
1734         REG_WRITE(ah, AR_RTC_RESET, 0);
1735         udelay(2);
1736
1737         if (!AR_SREV_9100(ah))
1738                 REG_WRITE(ah, AR_RC, 0);
1739
1740         REG_WRITE(ah, AR_RTC_RESET, 1);
1741
1742         if (!ath9k_hw_wait(ah,
1743                            AR_RTC_STATUS,
1744                            AR_RTC_STATUS_M,
1745                            AR_RTC_STATUS_ON,
1746                            AH_WAIT_TIMEOUT)) {
1747                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1748                           "RTC not waking up\n");
1749                 return false;
1750         }
1751
1752         ath9k_hw_read_revisions(ah);
1753
1754         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1755 }
1756
1757 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1758 {
1759         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1760                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1761
1762         switch (type) {
1763         case ATH9K_RESET_POWER_ON:
1764                 return ath9k_hw_set_reset_power_on(ah);
1765         case ATH9K_RESET_WARM:
1766         case ATH9K_RESET_COLD:
1767                 return ath9k_hw_set_reset(ah, type);
1768         default:
1769                 return false;
1770         }
1771 }
1772
1773 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1774 {
1775         u32 phymode;
1776         u32 enableDacFifo = 0;
1777
1778         if (AR_SREV_9285_10_OR_LATER(ah))
1779                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1780                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1781
1782         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1783                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1784
1785         if (IS_CHAN_HT40(chan)) {
1786                 phymode |= AR_PHY_FC_DYN2040_EN;
1787
1788                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1789                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1790                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1791
1792         }
1793         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1794
1795         ath9k_hw_set11nmac2040(ah);
1796
1797         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1798         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1799 }
1800
1801 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1802                                 struct ath9k_channel *chan)
1803 {
1804         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1805                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1806                         return false;
1807         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1808                 return false;
1809
1810         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1811                 return false;
1812
1813         ah->chip_fullsleep = false;
1814         ath9k_hw_init_pll(ah, chan);
1815         ath9k_hw_set_rfmode(ah, chan);
1816
1817         return true;
1818 }
1819
1820 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1821                                     struct ath9k_channel *chan)
1822 {
1823         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1824         struct ath_common *common = ath9k_hw_common(ah);
1825         struct ieee80211_channel *channel = chan->chan;
1826         u32 synthDelay, qnum;
1827         int r;
1828
1829         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1830                 if (ath9k_hw_numtxpending(ah, qnum)) {
1831                         ath_print(common, ATH_DBG_QUEUE,
1832                                   "Transmit frames pending on "
1833                                   "queue %d\n", qnum);
1834                         return false;
1835                 }
1836         }
1837
1838         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1839         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1840                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1841                 ath_print(common, ATH_DBG_FATAL,
1842                           "Could not kill baseband RX\n");
1843                 return false;
1844         }
1845
1846         ath9k_hw_set_regs(ah, chan);
1847
1848         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1849         if (r) {
1850                 ath_print(common, ATH_DBG_FATAL,
1851                           "Failed to set channel\n");
1852                 return false;
1853         }
1854
1855         ah->eep_ops->set_txpower(ah, chan,
1856                              ath9k_regd_get_ctl(regulatory, chan),
1857                              channel->max_antenna_gain * 2,
1858                              channel->max_power * 2,
1859                              min((u32) MAX_RATE_POWER,
1860                              (u32) regulatory->power_limit));
1861
1862         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1863         if (IS_CHAN_B(chan))
1864                 synthDelay = (4 * synthDelay) / 22;
1865         else
1866                 synthDelay /= 10;
1867
1868         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1869
1870         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1871
1872         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1873                 ath9k_hw_set_delta_slope(ah, chan);
1874
1875         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1876
1877         if (!chan->oneTimeCalsDone)
1878                 chan->oneTimeCalsDone = true;
1879
1880         return true;
1881 }
1882
1883 static void ath9k_enable_rfkill(struct ath_hw *ah)
1884 {
1885         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1886                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1887
1888         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1889                     AR_GPIO_INPUT_MUX2_RFSILENT);
1890
1891         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1892         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1893 }
1894
1895 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1896                     bool bChannelChange)
1897 {
1898         struct ath_common *common = ath9k_hw_common(ah);
1899         u32 saveLedState;
1900         struct ath9k_channel *curchan = ah->curchan;
1901         u32 saveDefAntenna;
1902         u32 macStaId1;
1903         u64 tsf = 0;
1904         int i, rx_chainmask, r;
1905
1906         ah->txchainmask = common->tx_chainmask;
1907         ah->rxchainmask = common->rx_chainmask;
1908
1909         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1910                 return -EIO;
1911
1912         if (curchan && !ah->chip_fullsleep)
1913                 ath9k_hw_getnf(ah, curchan);
1914
1915         if (bChannelChange &&
1916             (ah->chip_fullsleep != true) &&
1917             (ah->curchan != NULL) &&
1918             (chan->channel != ah->curchan->channel) &&
1919             ((chan->channelFlags & CHANNEL_ALL) ==
1920              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1921              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1922              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1923
1924                 if (ath9k_hw_channel_change(ah, chan)) {
1925                         ath9k_hw_loadnf(ah, ah->curchan);
1926                         ath9k_hw_start_nfcal(ah);
1927                         return 0;
1928                 }
1929         }
1930
1931         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1932         if (saveDefAntenna == 0)
1933                 saveDefAntenna = 1;
1934
1935         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1936
1937         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1938         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1939                 tsf = ath9k_hw_gettsf64(ah);
1940
1941         saveLedState = REG_READ(ah, AR_CFG_LED) &
1942                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1943                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1944
1945         ath9k_hw_mark_phy_inactive(ah);
1946
1947         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1948                 REG_WRITE(ah,
1949                           AR9271_RESET_POWER_DOWN_CONTROL,
1950                           AR9271_RADIO_RF_RST);
1951                 udelay(50);
1952         }
1953
1954         if (!ath9k_hw_chip_reset(ah, chan)) {
1955                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1956                 return -EINVAL;
1957         }
1958
1959         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1960                 ah->htc_reset_init = false;
1961                 REG_WRITE(ah,
1962                           AR9271_RESET_POWER_DOWN_CONTROL,
1963                           AR9271_GATE_MAC_CTL);
1964                 udelay(50);
1965         }
1966
1967         /* Restore TSF */
1968         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1969                 ath9k_hw_settsf64(ah, tsf);
1970
1971         if (AR_SREV_9280_10_OR_LATER(ah))
1972                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1973
1974         if (AR_SREV_9287_12_OR_LATER(ah)) {
1975                 /* Enable ASYNC FIFO */
1976                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1977                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1978                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1979                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1980                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1981                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1982                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1983         }
1984         r = ath9k_hw_process_ini(ah, chan);
1985         if (r)
1986                 return r;
1987
1988         /* Setup MFP options for CCMP */
1989         if (AR_SREV_9280_20_OR_LATER(ah)) {
1990                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1991                  * frames when constructing CCMP AAD. */
1992                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1993                               0xc7ff);
1994                 ah->sw_mgmt_crypto = false;
1995         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1996                 /* Disable hardware crypto for management frames */
1997                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1998                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1999                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2000                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2001                 ah->sw_mgmt_crypto = true;
2002         } else
2003                 ah->sw_mgmt_crypto = true;
2004
2005         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2006                 ath9k_hw_set_delta_slope(ah, chan);
2007
2008         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2009         ah->eep_ops->set_board_values(ah, chan);
2010
2011         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2012         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2013                   | macStaId1
2014                   | AR_STA_ID1_RTS_USE_DEF
2015                   | (ah->config.
2016                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2017                   | ah->sta_id1_defaults);
2018         ath9k_hw_set_operating_mode(ah, ah->opmode);
2019
2020         ath_hw_setbssidmask(common);
2021
2022         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2023
2024         ath9k_hw_write_associd(ah);
2025
2026         REG_WRITE(ah, AR_ISR, ~0);
2027
2028         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2029
2030         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2031         if (r)
2032                 return r;
2033
2034         for (i = 0; i < AR_NUM_DCU; i++)
2035                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2036
2037         ah->intr_txqs = 0;
2038         for (i = 0; i < ah->caps.total_queues; i++)
2039                 ath9k_hw_resettxqueue(ah, i);
2040
2041         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2042         ath9k_hw_init_qos(ah);
2043
2044         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2045                 ath9k_enable_rfkill(ah);
2046
2047         ath9k_hw_init_global_settings(ah);
2048
2049         if (AR_SREV_9287_12_OR_LATER(ah)) {
2050                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2051                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2052                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2053                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2054                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2055                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2056
2057                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2058                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2059
2060                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2061                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2062                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2063                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2064         }
2065         if (AR_SREV_9287_12_OR_LATER(ah)) {
2066                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2067                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2068         }
2069
2070         REG_WRITE(ah, AR_STA_ID1,
2071                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2072
2073         ath9k_hw_set_dma(ah);
2074
2075         REG_WRITE(ah, AR_OBS, 8);
2076
2077         if (ah->config.rx_intr_mitigation) {
2078                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2079                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2080         }
2081
2082         ath9k_hw_init_bb(ah, chan);
2083
2084         if (!ath9k_hw_init_cal(ah, chan))
2085                 return -EIO;
2086
2087         rx_chainmask = ah->rxchainmask;
2088         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2089                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2090                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2091         }
2092
2093         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2094
2095         /*
2096          * For big endian systems turn on swapping for descriptors
2097          */
2098         if (AR_SREV_9100(ah)) {
2099                 u32 mask;
2100                 mask = REG_READ(ah, AR_CFG);
2101                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2102                         ath_print(common, ATH_DBG_RESET,
2103                                 "CFG Byte Swap Set 0x%x\n", mask);
2104                 } else {
2105                         mask =
2106                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2107                         REG_WRITE(ah, AR_CFG, mask);
2108                         ath_print(common, ATH_DBG_RESET,
2109                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2110                 }
2111         } else {
2112                 /* Configure AR9271 target WLAN */
2113                 if (AR_SREV_9271(ah))
2114                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2115 #ifdef __BIG_ENDIAN
2116                 else
2117                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2118 #endif
2119         }
2120
2121         if (ah->btcoex_hw.enabled)
2122                 ath9k_hw_btcoex_enable(ah);
2123
2124         return 0;
2125 }
2126 EXPORT_SYMBOL(ath9k_hw_reset);
2127
2128 /************************/
2129 /* Key Cache Management */
2130 /************************/
2131
2132 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2133 {
2134         u32 keyType;
2135
2136         if (entry >= ah->caps.keycache_size) {
2137                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2138                           "keychache entry %u out of range\n", entry);
2139                 return false;
2140         }
2141
2142         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2143
2144         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2145         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2146         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2147         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2148         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2149         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2150         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2151         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2152
2153         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2154                 u16 micentry = entry + 64;
2155
2156                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2157                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2158                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2159                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2160
2161         }
2162
2163         return true;
2164 }
2165 EXPORT_SYMBOL(ath9k_hw_keyreset);
2166
2167 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2168 {
2169         u32 macHi, macLo;
2170
2171         if (entry >= ah->caps.keycache_size) {
2172                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2173                           "keychache entry %u out of range\n", entry);
2174                 return false;
2175         }
2176
2177         if (mac != NULL) {
2178                 macHi = (mac[5] << 8) | mac[4];
2179                 macLo = (mac[3] << 24) |
2180                         (mac[2] << 16) |
2181                         (mac[1] << 8) |
2182                         mac[0];
2183                 macLo >>= 1;
2184                 macLo |= (macHi & 1) << 31;
2185                 macHi >>= 1;
2186         } else {
2187                 macLo = macHi = 0;
2188         }
2189         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2190         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2191
2192         return true;
2193 }
2194 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2195
2196 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2197                                  const struct ath9k_keyval *k,
2198                                  const u8 *mac)
2199 {
2200         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2201         struct ath_common *common = ath9k_hw_common(ah);
2202         u32 key0, key1, key2, key3, key4;
2203         u32 keyType;
2204
2205         if (entry >= pCap->keycache_size) {
2206                 ath_print(common, ATH_DBG_FATAL,
2207                           "keycache entry %u out of range\n", entry);
2208                 return false;
2209         }
2210
2211         switch (k->kv_type) {
2212         case ATH9K_CIPHER_AES_OCB:
2213                 keyType = AR_KEYTABLE_TYPE_AES;
2214                 break;
2215         case ATH9K_CIPHER_AES_CCM:
2216                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2217                         ath_print(common, ATH_DBG_ANY,
2218                                   "AES-CCM not supported by mac rev 0x%x\n",
2219                                   ah->hw_version.macRev);
2220                         return false;
2221                 }
2222                 keyType = AR_KEYTABLE_TYPE_CCM;
2223                 break;
2224         case ATH9K_CIPHER_TKIP:
2225                 keyType = AR_KEYTABLE_TYPE_TKIP;
2226                 if (ATH9K_IS_MIC_ENABLED(ah)
2227                     && entry + 64 >= pCap->keycache_size) {
2228                         ath_print(common, ATH_DBG_ANY,
2229                                   "entry %u inappropriate for TKIP\n", entry);
2230                         return false;
2231                 }
2232                 break;
2233         case ATH9K_CIPHER_WEP:
2234                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2235                         ath_print(common, ATH_DBG_ANY,
2236                                   "WEP key length %u too small\n", k->kv_len);
2237                         return false;
2238                 }
2239                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2240                         keyType = AR_KEYTABLE_TYPE_40;
2241                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2242                         keyType = AR_KEYTABLE_TYPE_104;
2243                 else
2244                         keyType = AR_KEYTABLE_TYPE_128;
2245                 break;
2246         case ATH9K_CIPHER_CLR:
2247                 keyType = AR_KEYTABLE_TYPE_CLR;
2248                 break;
2249         default:
2250                 ath_print(common, ATH_DBG_FATAL,
2251                           "cipher %u not supported\n", k->kv_type);
2252                 return false;
2253         }
2254
2255         key0 = get_unaligned_le32(k->kv_val + 0);
2256         key1 = get_unaligned_le16(k->kv_val + 4);
2257         key2 = get_unaligned_le32(k->kv_val + 6);
2258         key3 = get_unaligned_le16(k->kv_val + 10);
2259         key4 = get_unaligned_le32(k->kv_val + 12);
2260         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2261                 key4 &= 0xff;
2262
2263         /*
2264          * Note: Key cache registers access special memory area that requires
2265          * two 32-bit writes to actually update the values in the internal
2266          * memory. Consequently, the exact order and pairs used here must be
2267          * maintained.
2268          */
2269
2270         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2271                 u16 micentry = entry + 64;
2272
2273                 /*
2274                  * Write inverted key[47:0] first to avoid Michael MIC errors
2275                  * on frames that could be sent or received at the same time.
2276                  * The correct key will be written in the end once everything
2277                  * else is ready.
2278                  */
2279                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2280                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2281
2282                 /* Write key[95:48] */
2283                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2284                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2285
2286                 /* Write key[127:96] and key type */
2287                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2288                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2289
2290                 /* Write MAC address for the entry */
2291                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2292
2293                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2294                         /*
2295                          * TKIP uses two key cache entries:
2296                          * Michael MIC TX/RX keys in the same key cache entry
2297                          * (idx = main index + 64):
2298                          * key0 [31:0] = RX key [31:0]
2299                          * key1 [15:0] = TX key [31:16]
2300                          * key1 [31:16] = reserved
2301                          * key2 [31:0] = RX key [63:32]
2302                          * key3 [15:0] = TX key [15:0]
2303                          * key3 [31:16] = reserved
2304                          * key4 [31:0] = TX key [63:32]
2305                          */
2306                         u32 mic0, mic1, mic2, mic3, mic4;
2307
2308                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2309                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2310                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2311                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2312                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2313
2314                         /* Write RX[31:0] and TX[31:16] */
2315                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2316                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2317
2318                         /* Write RX[63:32] and TX[15:0] */
2319                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2320                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2321
2322                         /* Write TX[63:32] and keyType(reserved) */
2323                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2324                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2325                                   AR_KEYTABLE_TYPE_CLR);
2326
2327                 } else {
2328                         /*
2329                          * TKIP uses four key cache entries (two for group
2330                          * keys):
2331                          * Michael MIC TX/RX keys are in different key cache
2332                          * entries (idx = main index + 64 for TX and
2333                          * main index + 32 + 96 for RX):
2334                          * key0 [31:0] = TX/RX MIC key [31:0]
2335                          * key1 [31:0] = reserved
2336                          * key2 [31:0] = TX/RX MIC key [63:32]
2337                          * key3 [31:0] = reserved
2338                          * key4 [31:0] = reserved
2339                          *
2340                          * Upper layer code will call this function separately
2341                          * for TX and RX keys when these registers offsets are
2342                          * used.
2343                          */
2344                         u32 mic0, mic2;
2345
2346                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2347                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2348
2349                         /* Write MIC key[31:0] */
2350                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2351                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2352
2353                         /* Write MIC key[63:32] */
2354                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2355                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2356
2357                         /* Write TX[63:32] and keyType(reserved) */
2358                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2359                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2360                                   AR_KEYTABLE_TYPE_CLR);
2361                 }
2362
2363                 /* MAC address registers are reserved for the MIC entry */
2364                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2365                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2366
2367                 /*
2368                  * Write the correct (un-inverted) key[47:0] last to enable
2369                  * TKIP now that all other registers are set with correct
2370                  * values.
2371                  */
2372                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2373                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2374         } else {
2375                 /* Write key[47:0] */
2376                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2377                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2378
2379                 /* Write key[95:48] */
2380                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2381                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2382
2383                 /* Write key[127:96] and key type */
2384                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2385                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2386
2387                 /* Write MAC address for the entry */
2388                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2389         }
2390
2391         return true;
2392 }
2393 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2394
2395 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2396 {
2397         if (entry < ah->caps.keycache_size) {
2398                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2399                 if (val & AR_KEYTABLE_VALID)
2400                         return true;
2401         }
2402         return false;
2403 }
2404 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2405
2406 /******************************/
2407 /* Power Management (Chipset) */
2408 /******************************/
2409
2410 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2411 {
2412         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2413         if (setChip) {
2414                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2415                             AR_RTC_FORCE_WAKE_EN);
2416                 if (!AR_SREV_9100(ah))
2417                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2418
2419                 if(!AR_SREV_5416(ah))
2420                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2421                                     AR_RTC_RESET_EN);
2422         }
2423 }
2424
2425 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2426 {
2427         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2428         if (setChip) {
2429                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2430
2431                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2432                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2433                                   AR_RTC_FORCE_WAKE_ON_INT);
2434                 } else {
2435                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2436                                     AR_RTC_FORCE_WAKE_EN);
2437                 }
2438         }
2439 }
2440
2441 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2442 {
2443         u32 val;
2444         int i;
2445
2446         if (setChip) {
2447                 if ((REG_READ(ah, AR_RTC_STATUS) &
2448                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2449                         if (ath9k_hw_set_reset_reg(ah,
2450                                            ATH9K_RESET_POWER_ON) != true) {
2451                                 return false;
2452                         }
2453                         ath9k_hw_init_pll(ah, NULL);
2454                 }
2455                 if (AR_SREV_9100(ah))
2456                         REG_SET_BIT(ah, AR_RTC_RESET,
2457                                     AR_RTC_RESET_EN);
2458
2459                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2460                             AR_RTC_FORCE_WAKE_EN);
2461                 udelay(50);
2462
2463                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2464                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2465                         if (val == AR_RTC_STATUS_ON)
2466                                 break;
2467                         udelay(50);
2468                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2469                                     AR_RTC_FORCE_WAKE_EN);
2470                 }
2471                 if (i == 0) {
2472                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2473                                   "Failed to wakeup in %uus\n",
2474                                   POWER_UP_TIME / 20);
2475                         return false;
2476                 }
2477         }
2478
2479         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2480
2481         return true;
2482 }
2483
2484 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2485 {
2486         struct ath_common *common = ath9k_hw_common(ah);
2487         int status = true, setChip = true;
2488         static const char *modes[] = {
2489                 "AWAKE",
2490                 "FULL-SLEEP",
2491                 "NETWORK SLEEP",
2492                 "UNDEFINED"
2493         };
2494
2495         if (ah->power_mode == mode)
2496                 return status;
2497
2498         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2499                   modes[ah->power_mode], modes[mode]);
2500
2501         switch (mode) {
2502         case ATH9K_PM_AWAKE:
2503                 status = ath9k_hw_set_power_awake(ah, setChip);
2504                 break;
2505         case ATH9K_PM_FULL_SLEEP:
2506                 ath9k_set_power_sleep(ah, setChip);
2507                 ah->chip_fullsleep = true;
2508                 break;
2509         case ATH9K_PM_NETWORK_SLEEP:
2510                 ath9k_set_power_network_sleep(ah, setChip);
2511                 break;
2512         default:
2513                 ath_print(common, ATH_DBG_FATAL,
2514                           "Unknown power mode %u\n", mode);
2515                 return false;
2516         }
2517         ah->power_mode = mode;
2518
2519         return status;
2520 }
2521 EXPORT_SYMBOL(ath9k_hw_setpower);
2522
2523 /*
2524  * Helper for ASPM support.
2525  *
2526  * Disable PLL when in L0s as well as receiver clock when in L1.
2527  * This power saving option must be enabled through the SerDes.
2528  *
2529  * Programming the SerDes must go through the same 288 bit serial shift
2530  * register as the other analog registers.  Hence the 9 writes.
2531  */
2532 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2533 {
2534         u8 i;
2535         u32 val;
2536
2537         if (ah->is_pciexpress != true)
2538                 return;
2539
2540         /* Do not touch SerDes registers */
2541         if (ah->config.pcie_powersave_enable == 2)
2542                 return;
2543
2544         /* Nothing to do on restore for 11N */
2545         if (!restore) {
2546                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2547                         /*
2548                          * AR9280 2.0 or later chips use SerDes values from the
2549                          * initvals.h initialized depending on chipset during
2550                          * ath9k_hw_init()
2551                          */
2552                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2553                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2554                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2555                         }
2556                 } else if (AR_SREV_9280(ah) &&
2557                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2558                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2559                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2560
2561                         /* RX shut off when elecidle is asserted */
2562                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2563                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2564                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2565
2566                         /* Shut off CLKREQ active in L1 */
2567                         if (ah->config.pcie_clock_req)
2568                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2569                         else
2570                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2571
2572                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2573                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2574                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2575
2576                         /* Load the new settings */
2577                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2578
2579                 } else {
2580                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2581                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2582
2583                         /* RX shut off when elecidle is asserted */
2584                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2585                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2586                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2587
2588                         /*
2589                          * Ignore ah->ah_config.pcie_clock_req setting for
2590                          * pre-AR9280 11n
2591                          */
2592                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2593
2594                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2595                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2596                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2597
2598                         /* Load the new settings */
2599                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2600                 }
2601
2602                 udelay(1000);
2603
2604                 /* set bit 19 to allow forcing of pcie core into L1 state */
2605                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2606
2607                 /* Several PCIe massages to ensure proper behaviour */
2608                 if (ah->config.pcie_waen) {
2609                         val = ah->config.pcie_waen;
2610                         if (!power_off)
2611                                 val &= (~AR_WA_D3_L1_DISABLE);
2612                 } else {
2613                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2614                             AR_SREV_9287(ah)) {
2615                                 val = AR9285_WA_DEFAULT;
2616                                 if (!power_off)
2617                                         val &= (~AR_WA_D3_L1_DISABLE);
2618                         } else if (AR_SREV_9280(ah)) {
2619                                 /*
2620                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2621                                  * set otherwise card may disappear.
2622                                  */
2623                                 val = AR9280_WA_DEFAULT;
2624                                 if (!power_off)
2625                                         val &= (~AR_WA_D3_L1_DISABLE);
2626                         } else
2627                                 val = AR_WA_DEFAULT;
2628                 }
2629
2630                 REG_WRITE(ah, AR_WA, val);
2631         }
2632
2633         if (power_off) {
2634                 /*
2635                  * Set PCIe workaround bits
2636                  * bit 14 in WA register (disable L1) should only
2637                  * be set when device enters D3 and be cleared
2638                  * when device comes back to D0.
2639                  */
2640                 if (ah->config.pcie_waen) {
2641                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2642                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2643                 } else {
2644                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2645                               AR_SREV_9287(ah)) &&
2646                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2647                             (AR_SREV_9280(ah) &&
2648                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2649                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2650                         }
2651                 }
2652         }
2653 }
2654 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2655
2656 /**********************/
2657 /* Interrupt Handling */
2658 /**********************/
2659
2660 bool ath9k_hw_intrpend(struct ath_hw *ah)
2661 {
2662         u32 host_isr;
2663
2664         if (AR_SREV_9100(ah))
2665                 return true;
2666
2667         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2668         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2669                 return true;
2670
2671         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2672         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2673             && (host_isr != AR_INTR_SPURIOUS))
2674                 return true;
2675
2676         return false;
2677 }
2678 EXPORT_SYMBOL(ath9k_hw_intrpend);
2679
2680 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2681 {
2682         u32 isr = 0;
2683         u32 mask2 = 0;
2684         struct ath9k_hw_capabilities *pCap = &ah->caps;
2685         u32 sync_cause = 0;
2686         bool fatal_int = false;
2687         struct ath_common *common = ath9k_hw_common(ah);
2688
2689         if (!AR_SREV_9100(ah)) {
2690                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2691                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2692                             == AR_RTC_STATUS_ON) {
2693                                 isr = REG_READ(ah, AR_ISR);
2694                         }
2695                 }
2696
2697                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2698                         AR_INTR_SYNC_DEFAULT;
2699
2700                 *masked = 0;
2701
2702                 if (!isr && !sync_cause)
2703                         return false;
2704         } else {
2705                 *masked = 0;
2706                 isr = REG_READ(ah, AR_ISR);
2707         }
2708
2709         if (isr) {
2710                 if (isr & AR_ISR_BCNMISC) {
2711                         u32 isr2;
2712                         isr2 = REG_READ(ah, AR_ISR_S2);
2713                         if (isr2 & AR_ISR_S2_TIM)
2714                                 mask2 |= ATH9K_INT_TIM;
2715                         if (isr2 & AR_ISR_S2_DTIM)
2716                                 mask2 |= ATH9K_INT_DTIM;
2717                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2718                                 mask2 |= ATH9K_INT_DTIMSYNC;
2719                         if (isr2 & (AR_ISR_S2_CABEND))
2720                                 mask2 |= ATH9K_INT_CABEND;
2721                         if (isr2 & AR_ISR_S2_GTT)
2722                                 mask2 |= ATH9K_INT_GTT;
2723                         if (isr2 & AR_ISR_S2_CST)
2724                                 mask2 |= ATH9K_INT_CST;
2725                         if (isr2 & AR_ISR_S2_TSFOOR)
2726                                 mask2 |= ATH9K_INT_TSFOOR;
2727                 }
2728
2729                 isr = REG_READ(ah, AR_ISR_RAC);
2730                 if (isr == 0xffffffff) {
2731                         *masked = 0;
2732                         return false;
2733                 }
2734
2735                 *masked = isr & ATH9K_INT_COMMON;
2736
2737                 if (ah->config.rx_intr_mitigation) {
2738                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2739                                 *masked |= ATH9K_INT_RX;
2740                 }
2741
2742                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2743                         *masked |= ATH9K_INT_RX;
2744                 if (isr &
2745                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2746                      AR_ISR_TXEOL)) {
2747                         u32 s0_s, s1_s;
2748
2749                         *masked |= ATH9K_INT_TX;
2750
2751                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2752                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2753                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2754
2755                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2756                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2757                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2758                 }
2759
2760                 if (isr & AR_ISR_RXORN) {
2761                         ath_print(common, ATH_DBG_INTERRUPT,
2762                                   "receive FIFO overrun interrupt\n");
2763                 }
2764
2765                 if (!AR_SREV_9100(ah)) {
2766                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2767                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2768                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2769                                         *masked |= ATH9K_INT_TIM_TIMER;
2770                         }
2771                 }
2772
2773                 *masked |= mask2;
2774         }
2775
2776         if (AR_SREV_9100(ah))
2777                 return true;
2778
2779         if (isr & AR_ISR_GENTMR) {
2780                 u32 s5_s;
2781
2782                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2783                 if (isr & AR_ISR_GENTMR) {
2784                         ah->intr_gen_timer_trigger =
2785                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2786
2787                         ah->intr_gen_timer_thresh =
2788                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2789
2790                         if (ah->intr_gen_timer_trigger)
2791                                 *masked |= ATH9K_INT_GENTIMER;
2792
2793                 }
2794         }
2795
2796         if (sync_cause) {
2797                 fatal_int =
2798                         (sync_cause &
2799                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2800                         ? true : false;
2801
2802                 if (fatal_int) {
2803                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2804                                 ath_print(common, ATH_DBG_ANY,
2805                                           "received PCI FATAL interrupt\n");
2806                         }
2807                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2808                                 ath_print(common, ATH_DBG_ANY,
2809                                           "received PCI PERR interrupt\n");
2810                         }
2811                         *masked |= ATH9K_INT_FATAL;
2812                 }
2813                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2814                         ath_print(common, ATH_DBG_INTERRUPT,
2815                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2816                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2817                         REG_WRITE(ah, AR_RC, 0);
2818                         *masked |= ATH9K_INT_FATAL;
2819                 }
2820                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2821                         ath_print(common, ATH_DBG_INTERRUPT,
2822                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2823                 }
2824
2825                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2826                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2827         }
2828
2829         return true;
2830 }
2831 EXPORT_SYMBOL(ath9k_hw_getisr);
2832
2833 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2834 {
2835         u32 omask = ah->mask_reg;
2836         u32 mask, mask2;
2837         struct ath9k_hw_capabilities *pCap = &ah->caps;
2838         struct ath_common *common = ath9k_hw_common(ah);
2839
2840         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2841
2842         if (omask & ATH9K_INT_GLOBAL) {
2843                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2844                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2845                 (void) REG_READ(ah, AR_IER);
2846                 if (!AR_SREV_9100(ah)) {
2847                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2848                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2849
2850                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2851                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2852                 }
2853         }
2854
2855         mask = ints & ATH9K_INT_COMMON;
2856         mask2 = 0;
2857
2858         if (ints & ATH9K_INT_TX) {
2859                 if (ah->txok_interrupt_mask)
2860                         mask |= AR_IMR_TXOK;
2861                 if (ah->txdesc_interrupt_mask)
2862                         mask |= AR_IMR_TXDESC;
2863                 if (ah->txerr_interrupt_mask)
2864                         mask |= AR_IMR_TXERR;
2865                 if (ah->txeol_interrupt_mask)
2866                         mask |= AR_IMR_TXEOL;
2867         }
2868         if (ints & ATH9K_INT_RX) {
2869                 mask |= AR_IMR_RXERR;
2870                 if (ah->config.rx_intr_mitigation)
2871                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2872                 else
2873                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2874                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2875                         mask |= AR_IMR_GENTMR;
2876         }
2877
2878         if (ints & (ATH9K_INT_BMISC)) {
2879                 mask |= AR_IMR_BCNMISC;
2880                 if (ints & ATH9K_INT_TIM)
2881                         mask2 |= AR_IMR_S2_TIM;
2882                 if (ints & ATH9K_INT_DTIM)
2883                         mask2 |= AR_IMR_S2_DTIM;
2884                 if (ints & ATH9K_INT_DTIMSYNC)
2885                         mask2 |= AR_IMR_S2_DTIMSYNC;
2886                 if (ints & ATH9K_INT_CABEND)
2887                         mask2 |= AR_IMR_S2_CABEND;
2888                 if (ints & ATH9K_INT_TSFOOR)
2889                         mask2 |= AR_IMR_S2_TSFOOR;
2890         }
2891
2892         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2893                 mask |= AR_IMR_BCNMISC;
2894                 if (ints & ATH9K_INT_GTT)
2895                         mask2 |= AR_IMR_S2_GTT;
2896                 if (ints & ATH9K_INT_CST)
2897                         mask2 |= AR_IMR_S2_CST;
2898         }
2899
2900         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2901         REG_WRITE(ah, AR_IMR, mask);
2902         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2903                                            AR_IMR_S2_DTIM |
2904                                            AR_IMR_S2_DTIMSYNC |
2905                                            AR_IMR_S2_CABEND |
2906                                            AR_IMR_S2_CABTO |
2907                                            AR_IMR_S2_TSFOOR |
2908                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2909         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2910         ah->mask_reg = ints;
2911
2912         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2913                 if (ints & ATH9K_INT_TIM_TIMER)
2914                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2915                 else
2916                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2917         }
2918
2919         if (ints & ATH9K_INT_GLOBAL) {
2920                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2921                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2922                 if (!AR_SREV_9100(ah)) {
2923                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2924                                   AR_INTR_MAC_IRQ);
2925                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2926
2927
2928                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2929                                   AR_INTR_SYNC_DEFAULT);
2930                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2931                                   AR_INTR_SYNC_DEFAULT);
2932                 }
2933                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2934                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2935         }
2936
2937         return omask;
2938 }
2939 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2940
2941 /*******************/
2942 /* Beacon Handling */
2943 /*******************/
2944
2945 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2946 {
2947         int flags = 0;
2948
2949         ah->beacon_interval = beacon_period;
2950
2951         switch (ah->opmode) {
2952         case NL80211_IFTYPE_STATION:
2953         case NL80211_IFTYPE_MONITOR:
2954                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2955                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2956                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2957                 flags |= AR_TBTT_TIMER_EN;
2958                 break;
2959         case NL80211_IFTYPE_ADHOC:
2960         case NL80211_IFTYPE_MESH_POINT:
2961                 REG_SET_BIT(ah, AR_TXCFG,
2962                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2963                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2964                           TU_TO_USEC(next_beacon +
2965                                      (ah->atim_window ? ah->
2966                                       atim_window : 1)));
2967                 flags |= AR_NDP_TIMER_EN;
2968         case NL80211_IFTYPE_AP:
2969                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2970                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2971                           TU_TO_USEC(next_beacon -
2972                                      ah->config.
2973                                      dma_beacon_response_time));
2974                 REG_WRITE(ah, AR_NEXT_SWBA,
2975                           TU_TO_USEC(next_beacon -
2976                                      ah->config.
2977                                      sw_beacon_response_time));
2978                 flags |=
2979                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2980                 break;
2981         default:
2982                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2983                           "%s: unsupported opmode: %d\n",
2984                           __func__, ah->opmode);
2985                 return;
2986                 break;
2987         }
2988
2989         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2990         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2991         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2992         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2993
2994         beacon_period &= ~ATH9K_BEACON_ENA;
2995         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2996                 ath9k_hw_reset_tsf(ah);
2997         }
2998
2999         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3000 }
3001 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3002
3003 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3004                                     const struct ath9k_beacon_state *bs)
3005 {
3006         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3007         struct ath9k_hw_capabilities *pCap = &ah->caps;
3008         struct ath_common *common = ath9k_hw_common(ah);
3009
3010         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3011
3012         REG_WRITE(ah, AR_BEACON_PERIOD,
3013                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3014         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3015                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3016
3017         REG_RMW_FIELD(ah, AR_RSSI_THR,
3018                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3019
3020         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3021
3022         if (bs->bs_sleepduration > beaconintval)
3023                 beaconintval = bs->bs_sleepduration;
3024
3025         dtimperiod = bs->bs_dtimperiod;
3026         if (bs->bs_sleepduration > dtimperiod)
3027                 dtimperiod = bs->bs_sleepduration;
3028
3029         if (beaconintval == dtimperiod)
3030                 nextTbtt = bs->bs_nextdtim;
3031         else
3032                 nextTbtt = bs->bs_nexttbtt;
3033
3034         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3035         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3036         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3037         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3038
3039         REG_WRITE(ah, AR_NEXT_DTIM,
3040                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3041         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3042
3043         REG_WRITE(ah, AR_SLEEP1,
3044                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3045                   | AR_SLEEP1_ASSUME_DTIM);
3046
3047         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3048                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3049         else
3050                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3051
3052         REG_WRITE(ah, AR_SLEEP2,
3053                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3054
3055         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3056         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3057
3058         REG_SET_BIT(ah, AR_TIMER_MODE,
3059                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3060                     AR_DTIM_TIMER_EN);
3061
3062         /* TSF Out of Range Threshold */
3063         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3064 }
3065 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3066
3067 /*******************/
3068 /* HW Capabilities */
3069 /*******************/
3070
3071 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3072 {
3073         struct ath9k_hw_capabilities *pCap = &ah->caps;
3074         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3075         struct ath_common *common = ath9k_hw_common(ah);
3076         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3077
3078         u16 capField = 0, eeval;
3079
3080         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3081         regulatory->current_rd = eeval;
3082
3083         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3084         if (AR_SREV_9285_10_OR_LATER(ah))
3085                 eeval |= AR9285_RDEXT_DEFAULT;
3086         regulatory->current_rd_ext = eeval;
3087
3088         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3089
3090         if (ah->opmode != NL80211_IFTYPE_AP &&
3091             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3092                 if (regulatory->current_rd == 0x64 ||
3093                     regulatory->current_rd == 0x65)
3094                         regulatory->current_rd += 5;
3095                 else if (regulatory->current_rd == 0x41)
3096                         regulatory->current_rd = 0x43;
3097                 ath_print(common, ATH_DBG_REGULATORY,
3098                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3099         }
3100
3101         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3102         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3103                 ath_print(common, ATH_DBG_FATAL,
3104                           "no band has been marked as supported in EEPROM.\n");
3105                 return -EINVAL;
3106         }
3107
3108         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3109
3110         if (eeval & AR5416_OPFLAGS_11A) {
3111                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3112                 if (ah->config.ht_enable) {
3113                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3114                                 set_bit(ATH9K_MODE_11NA_HT20,
3115                                         pCap->wireless_modes);
3116                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3117                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3118                                         pCap->wireless_modes);
3119                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3120                                         pCap->wireless_modes);
3121                         }
3122                 }
3123         }
3124
3125         if (eeval & AR5416_OPFLAGS_11G) {
3126                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3127                 if (ah->config.ht_enable) {
3128                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3129                                 set_bit(ATH9K_MODE_11NG_HT20,
3130                                         pCap->wireless_modes);
3131                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3132                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3133                                         pCap->wireless_modes);
3134                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3135                                         pCap->wireless_modes);
3136                         }
3137                 }
3138         }
3139
3140         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3141         /*
3142          * For AR9271 we will temporarilly uses the rx chainmax as read from
3143          * the EEPROM.
3144          */
3145         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3146             !(eeval & AR5416_OPFLAGS_11A) &&
3147             !(AR_SREV_9271(ah)))
3148                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3149                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3150         else
3151                 /* Use rx_chainmask from EEPROM. */
3152                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3153
3154         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3155                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3156
3157         pCap->low_2ghz_chan = 2312;
3158         pCap->high_2ghz_chan = 2732;
3159
3160         pCap->low_5ghz_chan = 4920;
3161         pCap->high_5ghz_chan = 6100;
3162
3163         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3164         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3165         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3166
3167         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3168         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3169         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3170
3171         if (ah->config.ht_enable)
3172                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3173         else
3174                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3175
3176         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3177         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3178         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3179         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3180
3181         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3182                 pCap->total_queues =
3183                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3184         else
3185                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3186
3187         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3188                 pCap->keycache_size =
3189                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3190         else
3191                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3192
3193         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3194
3195         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3196                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3197         else
3198                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3199
3200         if (AR_SREV_9285_10_OR_LATER(ah))
3201                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3202         else if (AR_SREV_9280_10_OR_LATER(ah))
3203                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3204         else
3205                 pCap->num_gpio_pins = AR_NUM_GPIO;
3206
3207         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3208                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3209                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3210         } else {
3211                 pCap->rts_aggr_limit = (8 * 1024);
3212         }
3213
3214         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3215
3216 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3217         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3218         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3219                 ah->rfkill_gpio =
3220                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3221                 ah->rfkill_polarity =
3222                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3223
3224                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3225         }
3226 #endif
3227
3228         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3229
3230         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3231                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3232         else
3233                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3234
3235         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3236                 pCap->reg_cap =
3237                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3238                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3239                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3240                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3241         } else {
3242                 pCap->reg_cap =
3243                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3244                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3245         }
3246
3247         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3248         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3249             AR_SREV_5416(ah))
3250                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3251
3252         pCap->num_antcfg_5ghz =
3253                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3254         pCap->num_antcfg_2ghz =
3255                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3256
3257         if (AR_SREV_9280_10_OR_LATER(ah) &&
3258             ath9k_hw_btcoex_supported(ah)) {
3259                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3260                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3261
3262                 if (AR_SREV_9285(ah)) {
3263                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3264                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3265                 } else {
3266                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3267                 }
3268         } else {
3269                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3270         }
3271
3272         return 0;
3273 }
3274
3275 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3276                             u32 capability, u32 *result)
3277 {
3278         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3279         switch (type) {
3280         case ATH9K_CAP_CIPHER:
3281                 switch (capability) {
3282                 case ATH9K_CIPHER_AES_CCM:
3283                 case ATH9K_CIPHER_AES_OCB:
3284                 case ATH9K_CIPHER_TKIP:
3285                 case ATH9K_CIPHER_WEP:
3286                 case ATH9K_CIPHER_MIC:
3287                 case ATH9K_CIPHER_CLR:
3288                         return true;
3289                 default:
3290                         return false;
3291                 }
3292         case ATH9K_CAP_TKIP_MIC:
3293                 switch (capability) {
3294                 case 0:
3295                         return true;
3296                 case 1:
3297                         return (ah->sta_id1_defaults &
3298                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3299                         false;
3300                 }
3301         case ATH9K_CAP_TKIP_SPLIT:
3302                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3303                         false : true;
3304         case ATH9K_CAP_DIVERSITY:
3305                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3306                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3307                         true : false;
3308         case ATH9K_CAP_MCAST_KEYSRCH:
3309                 switch (capability) {
3310                 case 0:
3311                         return true;
3312                 case 1:
3313                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3314                                 return false;
3315                         } else {
3316                                 return (ah->sta_id1_defaults &
3317                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3318                                         false;
3319                         }
3320                 }
3321                 return false;
3322         case ATH9K_CAP_TXPOW:
3323                 switch (capability) {
3324                 case 0:
3325                         return 0;
3326                 case 1:
3327                         *result = regulatory->power_limit;
3328                         return 0;
3329                 case 2:
3330                         *result = regulatory->max_power_level;
3331                         return 0;
3332                 case 3:
3333                         *result = regulatory->tp_scale;
3334                         return 0;
3335                 }
3336                 return false;
3337         case ATH9K_CAP_DS:
3338                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3339                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3340                         ? false : true;
3341         default:
3342                 return false;
3343         }
3344 }
3345 EXPORT_SYMBOL(ath9k_hw_getcapability);
3346
3347 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3348                             u32 capability, u32 setting, int *status)
3349 {
3350         u32 v;
3351
3352         switch (type) {
3353         case ATH9K_CAP_TKIP_MIC:
3354                 if (setting)
3355                         ah->sta_id1_defaults |=
3356                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3357                 else
3358                         ah->sta_id1_defaults &=
3359                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3360                 return true;
3361         case ATH9K_CAP_DIVERSITY:
3362                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3363                 if (setting)
3364                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3365                 else
3366                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3367                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3368                 return true;
3369         case ATH9K_CAP_MCAST_KEYSRCH:
3370                 if (setting)
3371                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3372                 else
3373                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3374                 return true;
3375         default:
3376                 return false;
3377         }
3378 }
3379 EXPORT_SYMBOL(ath9k_hw_setcapability);
3380
3381 /****************************/
3382 /* GPIO / RFKILL / Antennae */
3383 /****************************/
3384
3385 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3386                                          u32 gpio, u32 type)
3387 {
3388         int addr;
3389         u32 gpio_shift, tmp;
3390
3391         if (gpio > 11)
3392                 addr = AR_GPIO_OUTPUT_MUX3;
3393         else if (gpio > 5)
3394                 addr = AR_GPIO_OUTPUT_MUX2;
3395         else
3396                 addr = AR_GPIO_OUTPUT_MUX1;
3397
3398         gpio_shift = (gpio % 6) * 5;
3399
3400         if (AR_SREV_9280_20_OR_LATER(ah)
3401             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3402                 REG_RMW(ah, addr, (type << gpio_shift),
3403                         (0x1f << gpio_shift));
3404         } else {
3405                 tmp = REG_READ(ah, addr);
3406                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3407                 tmp &= ~(0x1f << gpio_shift);
3408                 tmp |= (type << gpio_shift);
3409                 REG_WRITE(ah, addr, tmp);
3410         }
3411 }
3412
3413 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3414 {
3415         u32 gpio_shift;
3416
3417         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3418
3419         gpio_shift = gpio << 1;
3420
3421         REG_RMW(ah,
3422                 AR_GPIO_OE_OUT,
3423                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3424                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3425 }
3426 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3427
3428 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3429 {
3430 #define MS_REG_READ(x, y) \
3431         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3432
3433         if (gpio >= ah->caps.num_gpio_pins)
3434                 return 0xffffffff;
3435
3436         if (AR_SREV_9287_10_OR_LATER(ah))
3437                 return MS_REG_READ(AR9287, gpio) != 0;
3438         else if (AR_SREV_9285_10_OR_LATER(ah))
3439                 return MS_REG_READ(AR9285, gpio) != 0;
3440         else if (AR_SREV_9280_10_OR_LATER(ah))
3441                 return MS_REG_READ(AR928X, gpio) != 0;
3442         else
3443                 return MS_REG_READ(AR, gpio) != 0;
3444 }
3445 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3446
3447 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3448                          u32 ah_signal_type)
3449 {
3450         u32 gpio_shift;
3451
3452         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3453
3454         gpio_shift = 2 * gpio;
3455
3456         REG_RMW(ah,
3457                 AR_GPIO_OE_OUT,
3458                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3459                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3460 }
3461 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3462
3463 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3464 {
3465         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3466                 AR_GPIO_BIT(gpio));
3467 }
3468 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3469
3470 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3471 {
3472         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3473 }
3474 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3475
3476 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3477 {
3478         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3479 }
3480 EXPORT_SYMBOL(ath9k_hw_setantenna);
3481
3482 /*********************/
3483 /* General Operation */
3484 /*********************/
3485
3486 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3487 {
3488         u32 bits = REG_READ(ah, AR_RX_FILTER);
3489         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3490
3491         if (phybits & AR_PHY_ERR_RADAR)
3492                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3493         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3494                 bits |= ATH9K_RX_FILTER_PHYERR;
3495
3496         return bits;
3497 }
3498 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3499
3500 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3501 {
3502         u32 phybits;
3503
3504         REG_WRITE(ah, AR_RX_FILTER, bits);
3505
3506         phybits = 0;
3507         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3508                 phybits |= AR_PHY_ERR_RADAR;
3509         if (bits & ATH9K_RX_FILTER_PHYERR)
3510                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3511         REG_WRITE(ah, AR_PHY_ERR, phybits);
3512
3513         if (phybits)
3514                 REG_WRITE(ah, AR_RXCFG,
3515                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3516         else
3517                 REG_WRITE(ah, AR_RXCFG,
3518                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3519 }
3520 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3521
3522 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3523 {
3524         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3525                 return false;
3526
3527         ath9k_hw_init_pll(ah, NULL);
3528         return true;
3529 }
3530 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3531
3532 bool ath9k_hw_disable(struct ath_hw *ah)
3533 {
3534         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3535                 return false;
3536
3537         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3538                 return false;
3539
3540         ath9k_hw_init_pll(ah, NULL);
3541         return true;
3542 }
3543 EXPORT_SYMBOL(ath9k_hw_disable);
3544
3545 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3546 {
3547         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3548         struct ath9k_channel *chan = ah->curchan;
3549         struct ieee80211_channel *channel = chan->chan;
3550
3551         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3552
3553         ah->eep_ops->set_txpower(ah, chan,
3554                                  ath9k_regd_get_ctl(regulatory, chan),
3555                                  channel->max_antenna_gain * 2,
3556                                  channel->max_power * 2,
3557                                  min((u32) MAX_RATE_POWER,
3558                                  (u32) regulatory->power_limit));
3559 }
3560 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3561
3562 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3563 {
3564         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3565 }
3566 EXPORT_SYMBOL(ath9k_hw_setmac);
3567
3568 void ath9k_hw_setopmode(struct ath_hw *ah)
3569 {
3570         ath9k_hw_set_operating_mode(ah, ah->opmode);
3571 }
3572 EXPORT_SYMBOL(ath9k_hw_setopmode);
3573
3574 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3575 {
3576         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3577         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3578 }
3579 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3580
3581 void ath9k_hw_write_associd(struct ath_hw *ah)
3582 {
3583         struct ath_common *common = ath9k_hw_common(ah);
3584
3585         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3586         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3587                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3588 }
3589 EXPORT_SYMBOL(ath9k_hw_write_associd);
3590
3591 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3592 {
3593         u64 tsf;
3594
3595         tsf = REG_READ(ah, AR_TSF_U32);
3596         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3597
3598         return tsf;
3599 }
3600 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3601
3602 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3603 {
3604         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3605         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3606 }
3607 EXPORT_SYMBOL(ath9k_hw_settsf64);
3608
3609 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3610 {
3611         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3612                            AH_TSF_WRITE_TIMEOUT))
3613                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3614                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3615
3616         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3617 }
3618 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3619
3620 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3621 {
3622         if (setting)
3623                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3624         else
3625                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3626 }
3627 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3628
3629 /*
3630  *  Extend 15-bit time stamp from rx descriptor to
3631  *  a full 64-bit TSF using the current h/w TSF.
3632 */
3633 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3634 {
3635         u64 tsf;
3636
3637         tsf = ath9k_hw_gettsf64(ah);
3638         if ((tsf & 0x7fff) < rstamp)
3639                 tsf -= 0x8000;
3640         return (tsf & ~0x7fff) | rstamp;
3641 }
3642 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3643
3644 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3645 {
3646         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3647         u32 macmode;
3648
3649         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3650                 macmode = AR_2040_JOINED_RX_CLEAR;
3651         else
3652                 macmode = 0;
3653
3654         REG_WRITE(ah, AR_2040_MODE, macmode);
3655 }
3656
3657 /* HW Generic timers configuration */
3658
3659 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3660 {
3661         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3662         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3663         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3664         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3665         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3666         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3667         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3668         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3669         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3670         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3671                                 AR_NDP2_TIMER_MODE, 0x0002},
3672         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3673                                 AR_NDP2_TIMER_MODE, 0x0004},
3674         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3675                                 AR_NDP2_TIMER_MODE, 0x0008},
3676         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3677                                 AR_NDP2_TIMER_MODE, 0x0010},
3678         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3679                                 AR_NDP2_TIMER_MODE, 0x0020},
3680         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3681                                 AR_NDP2_TIMER_MODE, 0x0040},
3682         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3683                                 AR_NDP2_TIMER_MODE, 0x0080}
3684 };
3685
3686 /* HW generic timer primitives */
3687
3688 /* compute and clear index of rightmost 1 */
3689 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3690 {
3691         u32 b;
3692
3693         b = *mask;
3694         b &= (0-b);
3695         *mask &= ~b;
3696         b *= debruijn32;
3697         b >>= 27;
3698
3699         return timer_table->gen_timer_index[b];
3700 }
3701
3702 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3703 {
3704         return REG_READ(ah, AR_TSF_L32);
3705 }
3706 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3707
3708 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3709                                           void (*trigger)(void *),
3710                                           void (*overflow)(void *),
3711                                           void *arg,
3712                                           u8 timer_index)
3713 {
3714         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3715         struct ath_gen_timer *timer;
3716
3717         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3718
3719         if (timer == NULL) {
3720                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3721                           "Failed to allocate memory"
3722                           "for hw timer[%d]\n", timer_index);
3723                 return NULL;
3724         }
3725
3726         /* allocate a hardware generic timer slot */
3727         timer_table->timers[timer_index] = timer;
3728         timer->index = timer_index;
3729         timer->trigger = trigger;
3730         timer->overflow = overflow;
3731         timer->arg = arg;
3732
3733         return timer;
3734 }
3735 EXPORT_SYMBOL(ath_gen_timer_alloc);
3736
3737 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3738                               struct ath_gen_timer *timer,
3739                               u32 timer_next,
3740                               u32 timer_period)
3741 {
3742         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3743         u32 tsf;
3744
3745         BUG_ON(!timer_period);
3746
3747         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3748
3749         tsf = ath9k_hw_gettsf32(ah);
3750
3751         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3752                   "curent tsf %x period %x"
3753                   "timer_next %x\n", tsf, timer_period, timer_next);
3754
3755         /*
3756          * Pull timer_next forward if the current TSF already passed it
3757          * because of software latency
3758          */
3759         if (timer_next < tsf)
3760                 timer_next = tsf + timer_period;
3761
3762         /*
3763          * Program generic timer registers
3764          */
3765         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3766                  timer_next);
3767         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3768                   timer_period);
3769         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3770                     gen_tmr_configuration[timer->index].mode_mask);
3771
3772         /* Enable both trigger and thresh interrupt masks */
3773         REG_SET_BIT(ah, AR_IMR_S5,
3774                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3775                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3776 }
3777 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3778
3779 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3780 {
3781         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3782
3783         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3784                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3785                 return;
3786         }
3787
3788         /* Clear generic timer enable bits. */
3789         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3790                         gen_tmr_configuration[timer->index].mode_mask);
3791
3792         /* Disable both trigger and thresh interrupt masks */
3793         REG_CLR_BIT(ah, AR_IMR_S5,
3794                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3795                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3796
3797         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3798 }
3799 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3800
3801 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3802 {
3803         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3804
3805         /* free the hardware generic timer slot */
3806         timer_table->timers[timer->index] = NULL;
3807         kfree(timer);
3808 }
3809 EXPORT_SYMBOL(ath_gen_timer_free);
3810
3811 /*
3812  * Generic Timer Interrupts handling
3813  */
3814 void ath_gen_timer_isr(struct ath_hw *ah)
3815 {
3816         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3817         struct ath_gen_timer *timer;
3818         struct ath_common *common = ath9k_hw_common(ah);
3819         u32 trigger_mask, thresh_mask, index;
3820
3821         /* get hardware generic timer interrupt status */
3822         trigger_mask = ah->intr_gen_timer_trigger;
3823         thresh_mask = ah->intr_gen_timer_thresh;
3824         trigger_mask &= timer_table->timer_mask.val;
3825         thresh_mask &= timer_table->timer_mask.val;
3826
3827         trigger_mask &= ~thresh_mask;
3828
3829         while (thresh_mask) {
3830                 index = rightmost_index(timer_table, &thresh_mask);
3831                 timer = timer_table->timers[index];
3832                 BUG_ON(!timer);
3833                 ath_print(common, ATH_DBG_HWTIMER,
3834                           "TSF overflow for Gen timer %d\n", index);
3835                 timer->overflow(timer->arg);
3836         }
3837
3838         while (trigger_mask) {
3839                 index = rightmost_index(timer_table, &trigger_mask);
3840                 timer = timer_table->timers[index];
3841                 BUG_ON(!timer);
3842                 ath_print(common, ATH_DBG_HWTIMER,
3843                           "Gen timer[%d] trigger\n", index);
3844                 timer->trigger(timer->arg);
3845         }
3846 }
3847 EXPORT_SYMBOL(ath_gen_timer_isr);
3848
3849 static struct {
3850         u32 version;
3851         const char * name;
3852 } ath_mac_bb_names[] = {
3853         /* Devices with external radios */
3854         { AR_SREV_VERSION_5416_PCI,     "5416" },
3855         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3856         { AR_SREV_VERSION_9100,         "9100" },
3857         { AR_SREV_VERSION_9160,         "9160" },
3858         /* Single-chip solutions */
3859         { AR_SREV_VERSION_9280,         "9280" },
3860         { AR_SREV_VERSION_9285,         "9285" },
3861         { AR_SREV_VERSION_9287,         "9287" },
3862         { AR_SREV_VERSION_9271,         "9271" },
3863 };
3864
3865 /* For devices with external radios */
3866 static struct {
3867         u16 version;
3868         const char * name;
3869 } ath_rf_names[] = {
3870         { 0,                            "5133" },
3871         { AR_RAD5133_SREV_MAJOR,        "5133" },
3872         { AR_RAD5122_SREV_MAJOR,        "5122" },
3873         { AR_RAD2133_SREV_MAJOR,        "2133" },
3874         { AR_RAD2122_SREV_MAJOR,        "2122" }
3875 };
3876
3877 /*
3878  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3879  */
3880 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3881 {
3882         int i;
3883
3884         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3885                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3886                         return ath_mac_bb_names[i].name;
3887                 }
3888         }
3889
3890         return "????";
3891 }
3892
3893 /*
3894  * Return the RF name. "????" is returned if the RF is unknown.
3895  * Used for devices with external radios.
3896  */
3897 static const char *ath9k_hw_rf_name(u16 rf_version)
3898 {
3899         int i;
3900
3901         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3902                 if (ath_rf_names[i].version == rf_version) {
3903                         return ath_rf_names[i].name;
3904                 }
3905         }
3906
3907         return "????";
3908 }
3909
3910 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3911 {
3912         int used;
3913
3914         /* chipsets >= AR9280 are single-chip */
3915         if (AR_SREV_9280_10_OR_LATER(ah)) {
3916                 used = snprintf(hw_name, len,
3917                                "Atheros AR%s Rev:%x",
3918                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3919                                ah->hw_version.macRev);
3920         }
3921         else {
3922                 used = snprintf(hw_name, len,
3923                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3924                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3925                                ah->hw_version.macRev,
3926                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3927                                                 AR_RADIO_SREV_MAJOR)),
3928                                ah->hw_version.phyRev);
3929         }
3930
3931         hw_name[used] = '\0';
3932 }
3933 EXPORT_SYMBOL(ath9k_hw_name);