drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 #define ATH9K_CLOCK_RATE_CCK            22
  27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  29 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32
  33 MODULE_AUTHOR("Atheros Communications");
  34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  36 MODULE_LICENSE("Dual BSD/GPL");
  37
  38 static int __init ath9k_init(void)
  39 {
  40         return 0;
  41 }
  42 module_init(ath9k_init);
  43
  44 static void __exit ath9k_exit(void)
  45 {
  46         return;
  47 }
  48 module_exit(ath9k_exit);
  49
  50 /* Private hardware callbacks */
  51
  52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  55 }
  56
  57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  58 {
  59         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  60 }
  61
  62 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  63 {
  64         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  65
  66         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  67 }
  68
  69 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  70                                         struct ath9k_channel *chan)
  71 {
  72         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  73 }
  74
  75 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  76 {
  77         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  78                 return;
  79
  80         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  81 }
  82
  83 /********************/
  84 /* Helper Functions */
  85 /********************/
  86
  87 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  88 {
  89         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  90
  91         if (!ah->curchan) /* should really check for CCK instead */
  92                 return usecs *ATH9K_CLOCK_RATE_CCK;
  93         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  94                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  95
  96         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
  97                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
  98         else
  99                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 100 }
 101
 102 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 103 {
 104         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 105
 106         if (conf_is_ht40(conf))
 107                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 108         else
 109                 return ath9k_hw_mac_clks(ah, usecs);
 110 }
 111
 112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 113 {
 114         int i;
 115
 116         BUG_ON(timeout < AH_TIME_QUANTUM);
 117
 118         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 119                 if ((REG_READ(ah, reg) & mask) == val)
 120                         return true;
 121
 122                 udelay(AH_TIME_QUANTUM);
 123         }
 124
 125         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 126                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 127                   timeout, reg, REG_READ(ah, reg), mask, val);
 128
 129         return false;
 130 }
 131 EXPORT_SYMBOL(ath9k_hw_wait);
 132
 133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 134 {
 135         u32 retval;
 136         int i;
 137
 138         for (i = 0, retval = 0; i < n; i++) {
 139                 retval = (retval << 1) | (val & 1);
 140                 val >>= 1;
 141         }
 142         return retval;
 143 }
 144
 145 bool ath9k_get_channel_edges(struct ath_hw *ah,
 146                              u16 flags, u16 *low,
 147                              u16 *high)
 148 {
 149         struct ath9k_hw_capabilities *pCap = &ah->caps;
 150
 151         if (flags & CHANNEL_5GHZ) {
 152                 *low = pCap->low_5ghz_chan;
 153                 *high = pCap->high_5ghz_chan;
 154                 return true;
 155         }
 156         if ((flags & CHANNEL_2GHZ)) {
 157                 *low = pCap->low_2ghz_chan;
 158                 *high = pCap->high_2ghz_chan;
 159                 return true;
 160         }
 161         return false;
 162 }
 163
 164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 165                            u8 phy, int kbps,
 166                            u32 frameLen, u16 rateix,
 167                            bool shortPreamble)
 168 {
 169         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 170
 171         if (kbps == 0)
 172                 return 0;
 173
 174         switch (phy) {
 175         case WLAN_RC_PHY_CCK:
 176                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 177                 if (shortPreamble)
 178                         phyTime >>= 1;
 179                 numBits = frameLen << 3;
 180                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 181                 break;
 182         case WLAN_RC_PHY_OFDM:
 183                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME_QUARTER
 188                                 + OFDM_PREAMBLE_TIME_QUARTER
 189                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 190                 } else if (ah->curchan &&
 191                            IS_CHAN_HALF_RATE(ah->curchan)) {
 192                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 193                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 194                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 195                         txTime = OFDM_SIFS_TIME_HALF +
 196                                 OFDM_PREAMBLE_TIME_HALF
 197                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 198                 } else {
 199                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 200                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 201                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 202                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 203                                 + (numSymbols * OFDM_SYMBOL_TIME);
 204                 }
 205                 break;
 206         default:
 207                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 208                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 209                 txTime = 0;
 210                 break;
 211         }
 212
 213         return txTime;
 214 }
 215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 216
 217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 218                                   struct ath9k_channel *chan,
 219                                   struct chan_centers *centers)
 220 {
 221         int8_t extoff;
 222
 223         if (!IS_CHAN_HT40(chan)) {
 224                 centers->ctl_center = centers->ext_center =
 225                         centers->synth_center = chan->channel;
 226                 return;
 227         }
 228
 229         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 230             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 231                 centers->synth_center =
 232                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 233                 extoff = 1;
 234         } else {
 235                 centers->synth_center =
 236                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = -1;
 238         }
 239
 240         centers->ctl_center =
 241                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 242         /* 25 MHz spacing is supported by hw but not on upper layers */
 243         centers->ext_center =
 244                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 245 }
 246
 247 /******************/
 248 /* Chip Revisions */
 249 /******************/
 250
 251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 252 {
 253         u32 val;
 254
 255         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 256
 257         if (val == 0xFF) {
 258                 val = REG_READ(ah, AR_SREV);
 259                 ah->hw_version.macVersion =
 260                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 261                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 262                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 263         } else {
 264                 if (!AR_SREV_9100(ah))
 265                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 266
 267                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 268
 269                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 270                         ah->is_pciexpress = true;
 271         }
 272 }
 273
 274 /************************************/
 275 /* HW Attach, Detach, Init Routines */
 276 /************************************/
 277
 278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 279 {
 280         if (AR_SREV_9100(ah))
 281                 return;
 282
 283         ENABLE_REGWRITE_BUFFER(ah);
 284
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 288         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 294
 295         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 296
 297         REGWRITE_BUFFER_FLUSH(ah);
 298         DISABLE_REGWRITE_BUFFER(ah);
 299 }
 300
 301 /* This should work for all families including legacy */
 302 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 303 {
 304         struct ath_common *common = ath9k_hw_common(ah);
 305         u32 regAddr[2] = { AR_STA_ID0 };
 306         u32 regHold[2];
 307         u32 patternData[4] = { 0x55555555,
 308                                0xaaaaaaaa,
 309                                0x66666666,
 310                                0x99999999 };
 311         int i, j, loop_max;
 312
 313         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 314                 loop_max = 2;
 315                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 316         } else
 317                 loop_max = 1;
 318
 319         for (i = 0; i < loop_max; i++) {
 320                 u32 addr = regAddr[i];
 321                 u32 wrData, rdData;
 322
 323                 regHold[i] = REG_READ(ah, addr);
 324                 for (j = 0; j < 0x100; j++) {
 325                         wrData = (j << 16) | j;
 326                         REG_WRITE(ah, addr, wrData);
 327                         rdData = REG_READ(ah, addr);
 328                         if (rdData != wrData) {
 329                                 ath_print(common, ATH_DBG_FATAL,
 330                                           "address test failed "
 331                                           "addr: 0x%08x - wr:0x%08x != "
 332                                           "rd:0x%08x\n",
 333                                           addr, wrData, rdData);
 334                                 return false;
 335                         }
 336                 }
 337                 for (j = 0; j < 4; j++) {
 338                         wrData = patternData[j];
 339                         REG_WRITE(ah, addr, wrData);
 340                         rdData = REG_READ(ah, addr);
 341                         if (wrData != rdData) {
 342                                 ath_print(common, ATH_DBG_FATAL,
 343                                           "address test failed "
 344                                           "addr: 0x%08x - wr:0x%08x != "
 345                                           "rd:0x%08x\n",
 346                                           addr, wrData, rdData);
 347                                 return false;
 348                         }
 349                 }
 350                 REG_WRITE(ah, regAddr[i], regHold[i]);
 351         }
 352         udelay(100);
 353
 354         return true;
 355 }
 356
 357 static void ath9k_hw_init_config(struct ath_hw *ah)
 358 {
 359         int i;
 360
 361         ah->config.dma_beacon_response_time = 2;
 362         ah->config.sw_beacon_response_time = 10;
 363         ah->config.additional_swba_backoff = 0;
 364         ah->config.ack_6mb = 0x0;
 365         ah->config.cwm_ignore_extcca = 0;
 366         ah->config.pcie_powersave_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_waen = 0;
 369         ah->config.analog_shiftreg = 1;
 370         ah->config.ofdm_trig_low = 200;
 371         ah->config.ofdm_trig_high = 500;
 372         ah->config.cck_trig_high = 200;
 373         ah->config.cck_trig_low = 100;
 374
 375         /*
 376          * For now ANI is disabled for AR9003, it is still
 377          * being tested.
 378          */
 379         if (!AR_SREV_9300_20_OR_LATER(ah))
 380                 ah->config.enable_ani = 1;
 381
 382         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 383                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 384                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 385         }
 386
 387         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 388                 ah->config.ht_enable = 1;
 389         else
 390                 ah->config.ht_enable = 0;
 391
 392         ah->config.rx_intr_mitigation = true;
 393
 394         /*
 395          * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
 396          * used by AR9003, but it is showing reliability issues.
 397          * It will take a while to fix so this is currently disabled.
 398          */
 399
 400         /*
 401          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 402          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 403          * This means we use it for all AR5416 devices, and the few
 404          * minor PCI AR9280 devices out there.
 405          *
 406          * Serialization is required because these devices do not handle
 407          * well the case of two concurrent reads/writes due to the latency
 408          * involved. During one read/write another read/write can be issued
 409          * on another CPU while the previous read/write may still be working
 410          * on our hardware, if we hit this case the hardware poops in a loop.
 411          * We prevent this by serializing reads and writes.
 412          *
 413          * This issue is not present on PCI-Express devices or pre-AR5416
 414          * devices (legacy, 802.11abg).
 415          */
 416         if (num_possible_cpus() > 1)
 417                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 418 }
 419
 420 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 421 {
 422         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 423
 424         regulatory->country_code = CTRY_DEFAULT;
 425         regulatory->power_limit = MAX_RATE_POWER;
 426         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 427
 428         ah->hw_version.magic = AR5416_MAGIC;
 429         ah->hw_version.subvendorid = 0;
 430
 431         ah->ah_flags = 0;
 432         if (!AR_SREV_9100(ah))
 433                 ah->ah_flags = AH_USE_EEPROM;
 434
 435         ah->atim_window = 0;
 436         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 437         ah->beacon_interval = 100;
 438         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 439         ah->slottime = (u32) -1;
 440         ah->globaltxtimeout = (u32) -1;
 441         ah->power_mode = ATH9K_PM_UNDEFINED;
 442 }
 443
 444 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 445 {
 446         struct ath_common *common = ath9k_hw_common(ah);
 447         u32 sum;
 448         int i;
 449         u16 eeval;
 450         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 451
 452         sum = 0;
 453         for (i = 0; i < 3; i++) {
 454                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 455                 sum += eeval;
 456                 common->macaddr[2 * i] = eeval >> 8;
 457                 common->macaddr[2 * i + 1] = eeval & 0xff;
 458         }
 459         if (sum == 0 || sum == 0xffff * 3)
 460                 return -EADDRNOTAVAIL;
 461
 462         return 0;
 463 }
 464
 465 static int ath9k_hw_post_init(struct ath_hw *ah)
 466 {
 467         int ecode;
 468
 469         if (!AR_SREV_9271(ah)) {
 470                 if (!ath9k_hw_chip_test(ah))
 471                         return -ENODEV;
 472         }
 473
 474         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 475                 ecode = ar9002_hw_rf_claim(ah);
 476                 if (ecode != 0)
 477                         return ecode;
 478         }
 479
 480         ecode = ath9k_hw_eeprom_init(ah);
 481         if (ecode != 0)
 482                 return ecode;
 483
 484         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 485                   "Eeprom VER: %d, REV: %d\n",
 486                   ah->eep_ops->get_eeprom_ver(ah),
 487                   ah->eep_ops->get_eeprom_rev(ah));
 488
 489         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 490         if (ecode) {
 491                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 492                           "Failed allocating banks for "
 493                           "external radio\n");
 494                 return ecode;
 495         }
 496
 497         if (!AR_SREV_9100(ah)) {
 498                 ath9k_hw_ani_setup(ah);
 499                 ath9k_hw_ani_init(ah);
 500         }
 501
 502         return 0;
 503 }
 504
 505 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 506 {
 507         if (AR_SREV_9300_20_OR_LATER(ah))
 508                 ar9003_hw_attach_ops(ah);
 509         else
 510                 ar9002_hw_attach_ops(ah);
 511 }
 512
 513 /* Called for all hardware families */
 514 static int __ath9k_hw_init(struct ath_hw *ah)
 515 {
 516         struct ath_common *common = ath9k_hw_common(ah);
 517         int r = 0;
 518
 519         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 520                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 521
 522         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 523                 ath_print(common, ATH_DBG_FATAL,
 524                           "Couldn't reset chip\n");
 525                 return -EIO;
 526         }
 527
 528         ath9k_hw_init_defaults(ah);
 529         ath9k_hw_init_config(ah);
 530
 531         ath9k_hw_attach_ops(ah);
 532
 533         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 534                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 535                 return -EIO;
 536         }
 537
 538         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 539                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 540                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 541                         ah->config.serialize_regmode =
 542                                 SER_REG_MODE_ON;
 543                 } else {
 544                         ah->config.serialize_regmode =
 545                                 SER_REG_MODE_OFF;
 546                 }
 547         }
 548
 549         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 550                 ah->config.serialize_regmode);
 551
 552         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 553                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 554         else
 555                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 556
 557         if (!ath9k_hw_macversion_supported(ah)) {
 558                 ath_print(common, ATH_DBG_FATAL,
 559                           "Mac Chip Rev 0x%02x.%x is not supported by "
 560                           "this driver\n", ah->hw_version.macVersion,
 561                           ah->hw_version.macRev);
 562                 return -EOPNOTSUPP;
 563         }
 564
 565         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 566                 ah->is_pciexpress = false;
 567
 568         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 569         ath9k_hw_init_cal_settings(ah);
 570
 571         ah->ani_function = ATH9K_ANI_ALL;
 572         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 573                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 574
 575         ath9k_hw_init_mode_regs(ah);
 576
 577         /*
 578          * Configire PCIE after Ini init. SERDES values now come from ini file
 579          * This enables PCIe low power mode.
 580          */
 581         if (AR_SREV_9300_20_OR_LATER(ah)) {
 582                 u32 regval;
 583                 unsigned int i;
 584
 585                 /* Set Bits 16 and 17 in the AR_WA register. */
 586                 regval = REG_READ(ah, AR_WA);
 587                 regval |= 0x00030000;
 588                 REG_WRITE(ah, AR_WA, regval);
 589
 590                 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
 591                         REG_WRITE(ah,
 592                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
 593                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
 594                 }
 595         }
 596
 597         if (ah->is_pciexpress)
 598                 ath9k_hw_configpcipowersave(ah, 0, 0);
 599         else
 600                 ath9k_hw_disablepcie(ah);
 601
 602         if (!AR_SREV_9300_20_OR_LATER(ah))
 603                 ar9002_hw_cck_chan14_spread(ah);
 604
 605         r = ath9k_hw_post_init(ah);
 606         if (r)
 607                 return r;
 608
 609         ath9k_hw_init_mode_gain_regs(ah);
 610         r = ath9k_hw_fill_cap_info(ah);
 611         if (r)
 612                 return r;
 613
 614         r = ath9k_hw_init_macaddr(ah);
 615         if (r) {
 616                 ath_print(common, ATH_DBG_FATAL,
 617                           "Failed to initialize MAC address\n");
 618                 return r;
 619         }
 620
 621         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 622                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 623         else
 624                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 625
 626         if (AR_SREV_9300_20_OR_LATER(ah))
 627                 ar9003_hw_set_nf_limits(ah);
 628
 629         ath9k_init_nfcal_hist_buffer(ah);
 630
 631         common->state = ATH_HW_INITIALIZED;
 632
 633         return 0;
 634 }
 635
 636 int ath9k_hw_init(struct ath_hw *ah)
 637 {
 638         int ret;
 639         struct ath_common *common = ath9k_hw_common(ah);
 640
 641         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 642         switch (ah->hw_version.devid) {
 643         case AR5416_DEVID_PCI:
 644         case AR5416_DEVID_PCIE:
 645         case AR5416_AR9100_DEVID:
 646         case AR9160_DEVID_PCI:
 647         case AR9280_DEVID_PCI:
 648         case AR9280_DEVID_PCIE:
 649         case AR9285_DEVID_PCIE:
 650         case AR9287_DEVID_PCI:
 651         case AR9287_DEVID_PCIE:
 652         case AR2427_DEVID_PCIE:
 653         case AR9300_DEVID_PCIE:
 654                 break;
 655         default:
 656                 if (common->bus_ops->ath_bus_type == ATH_USB)
 657                         break;
 658                 ath_print(common, ATH_DBG_FATAL,
 659                           "Hardware device ID 0x%04x not supported\n",
 660                           ah->hw_version.devid);
 661                 return -EOPNOTSUPP;
 662         }
 663
 664         ret = __ath9k_hw_init(ah);
 665         if (ret) {
 666                 ath_print(common, ATH_DBG_FATAL,
 667                           "Unable to initialize hardware; "
 668                           "initialization status: %d\n", ret);
 669                 return ret;
 670         }
 671
 672         return 0;
 673 }
 674 EXPORT_SYMBOL(ath9k_hw_init);
 675
 676 static void ath9k_hw_init_qos(struct ath_hw *ah)
 677 {
 678         ENABLE_REGWRITE_BUFFER(ah);
 679
 680         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 681         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 682
 683         REG_WRITE(ah, AR_QOS_NO_ACK,
 684                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 685                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 686                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 687
 688         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 689         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 690         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 691         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 692         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 693
 694         REGWRITE_BUFFER_FLUSH(ah);
 695         DISABLE_REGWRITE_BUFFER(ah);
 696 }
 697
 698 static void ath9k_hw_init_pll(struct ath_hw *ah,
 699                               struct ath9k_channel *chan)
 700 {
 701         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 702
 703         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 704
 705         /* Switch the core clock for ar9271 to 117Mhz */
 706         if (AR_SREV_9271(ah)) {
 707                 udelay(500);
 708                 REG_WRITE(ah, 0x50040, 0x304);
 709         }
 710
 711         udelay(RTC_PLL_SETTLE_DELAY);
 712
 713         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 714 }
 715
 716 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 717                                           enum nl80211_iftype opmode)
 718 {
 719         u32 imr_reg = AR_IMR_TXERR |
 720                 AR_IMR_TXURN |
 721                 AR_IMR_RXERR |
 722                 AR_IMR_RXORN |
 723                 AR_IMR_BCNMISC;
 724
 725         if (AR_SREV_9300_20_OR_LATER(ah)) {
 726                 imr_reg |= AR_IMR_RXOK_HP;
 727                 if (ah->config.rx_intr_mitigation)
 728                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 729                 else
 730                         imr_reg |= AR_IMR_RXOK_LP;
 731
 732         } else {
 733                 if (ah->config.rx_intr_mitigation)
 734                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 735                 else
 736                         imr_reg |= AR_IMR_RXOK;
 737         }
 738
 739         if (ah->config.tx_intr_mitigation)
 740                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 741         else
 742                 imr_reg |= AR_IMR_TXOK;
 743
 744         if (opmode == NL80211_IFTYPE_AP)
 745                 imr_reg |= AR_IMR_MIB;
 746
 747         ENABLE_REGWRITE_BUFFER(ah);
 748
 749         REG_WRITE(ah, AR_IMR, imr_reg);
 750         ah->imrs2_reg |= AR_IMR_S2_GTT;
 751         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 752
 753         if (!AR_SREV_9100(ah)) {
 754                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 755                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 756                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 757         }
 758
 759         REGWRITE_BUFFER_FLUSH(ah);
 760         DISABLE_REGWRITE_BUFFER(ah);
 761
 762         if (AR_SREV_9300_20_OR_LATER(ah)) {
 763                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 764                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 765                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 766                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 767         }
 768 }
 769
 770 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 771 {
 772         u32 val = ath9k_hw_mac_to_clks(ah, us);
 773         val = min(val, (u32) 0xFFFF);
 774         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 775 }
 776
 777 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 778 {
 779         u32 val = ath9k_hw_mac_to_clks(ah, us);
 780         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 781         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 782 }
 783
 784 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 785 {
 786         u32 val = ath9k_hw_mac_to_clks(ah, us);
 787         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 788         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 789 }
 790
 791 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 792 {
 793         if (tu > 0xFFFF) {
 794                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 795                           "bad global tx timeout %u\n", tu);
 796                 ah->globaltxtimeout = (u32) -1;
 797                 return false;
 798         } else {
 799                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 800                 ah->globaltxtimeout = tu;
 801                 return true;
 802         }
 803 }
 804
 805 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 806 {
 807         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 808         int acktimeout;
 809         int slottime;
 810         int sifstime;
 811
 812         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 813                   ah->misc_mode);
 814
 815         if (ah->misc_mode != 0)
 816                 REG_WRITE(ah, AR_PCU_MISC,
 817                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 818
 819         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 820                 sifstime = 16;
 821         else
 822                 sifstime = 10;
 823
 824         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 825         slottime = ah->slottime + 3 * ah->coverage_class;
 826         acktimeout = slottime + sifstime;
 827
 828         /*
 829          * Workaround for early ACK timeouts, add an offset to match the
 830          * initval's 64us ack timeout value.
 831          * This was initially only meant to work around an issue with delayed
 832          * BA frames in some implementations, but it has been found to fix ACK
 833          * timeout issues in other cases as well.
 834          */
 835         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 836                 acktimeout += 64 - sifstime - ah->slottime;
 837
 838         ath9k_hw_setslottime(ah, slottime);
 839         ath9k_hw_set_ack_timeout(ah, acktimeout);
 840         ath9k_hw_set_cts_timeout(ah, acktimeout);
 841         if (ah->globaltxtimeout != (u32) -1)
 842                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 843 }
 844 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 845
 846 void ath9k_hw_deinit(struct ath_hw *ah)
 847 {
 848         struct ath_common *common = ath9k_hw_common(ah);
 849
 850         if (common->state < ATH_HW_INITIALIZED)
 851                 goto free_hw;
 852
 853         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 854
 855 free_hw:
 856         ath9k_hw_rf_free_ext_banks(ah);
 857 }
 858 EXPORT_SYMBOL(ath9k_hw_deinit);
 859
 860 /*******/
 861 /* INI */
 862 /*******/
 863
 864 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 865 {
 866         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 867
 868         if (IS_CHAN_B(chan))
 869                 ctl |= CTL_11B;
 870         else if (IS_CHAN_G(chan))
 871                 ctl |= CTL_11G;
 872         else
 873                 ctl |= CTL_11A;
 874
 875         return ctl;
 876 }
 877
 878 /****************************************/
 879 /* Reset and Channel Switching Routines */
 880 /****************************************/
 881
 882 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 883 {
 884         struct ath_common *common = ath9k_hw_common(ah);
 885         u32 regval;
 886
 887         ENABLE_REGWRITE_BUFFER(ah);
 888
 889         /*
 890          * set AHB_MODE not to do cacheline prefetches
 891         */
 892         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 893                 regval = REG_READ(ah, AR_AHB_MODE);
 894                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 895         }
 896
 897         /*
 898          * let mac dma reads be in 128 byte chunks
 899          */
 900         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 901         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 902
 903         REGWRITE_BUFFER_FLUSH(ah);
 904         DISABLE_REGWRITE_BUFFER(ah);
 905
 906         /*
 907          * Restore TX Trigger Level to its pre-reset value.
 908          * The initial value depends on whether aggregation is enabled, and is
 909          * adjusted whenever underruns are detected.
 910          */
 911         if (!AR_SREV_9300_20_OR_LATER(ah))
 912                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 913
 914         ENABLE_REGWRITE_BUFFER(ah);
 915
 916         /*
 917          * let mac dma writes be in 128 byte chunks
 918          */
 919         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 920         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 921
 922         /*
 923          * Setup receive FIFO threshold to hold off TX activities
 924          */
 925         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 926
 927         if (AR_SREV_9300_20_OR_LATER(ah)) {
 928                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 929                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 930
 931                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 932                         ah->caps.rx_status_len);
 933         }
 934
 935         /*
 936          * reduce the number of usable entries in PCU TXBUF to avoid
 937          * wrap around issues.
 938          */
 939         if (AR_SREV_9285(ah)) {
 940                 /* For AR9285 the number of Fifos are reduced to half.
 941                  * So set the usable tx buf size also to half to
 942                  * avoid data/delimiter underruns
 943                  */
 944                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 945                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 946         } else if (!AR_SREV_9271(ah)) {
 947                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 948                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 949         }
 950
 951         REGWRITE_BUFFER_FLUSH(ah);
 952         DISABLE_REGWRITE_BUFFER(ah);
 953
 954         if (AR_SREV_9300_20_OR_LATER(ah))
 955                 ath9k_hw_reset_txstatus_ring(ah);
 956 }
 957
 958 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 959 {
 960         u32 val;
 961
 962         val = REG_READ(ah, AR_STA_ID1);
 963         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 964         switch (opmode) {
 965         case NL80211_IFTYPE_AP:
 966                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 967                           | AR_STA_ID1_KSRCH_MODE);
 968                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 969                 break;
 970         case NL80211_IFTYPE_ADHOC:
 971         case NL80211_IFTYPE_MESH_POINT:
 972                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 973                           | AR_STA_ID1_KSRCH_MODE);
 974                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 975                 break;
 976         case NL80211_IFTYPE_STATION:
 977         case NL80211_IFTYPE_MONITOR:
 978                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 979                 break;
 980         }
 981 }
 982
 983 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 984                                    u32 *coef_mantissa, u32 *coef_exponent)
 985 {
 986         u32 coef_exp, coef_man;
 987
 988         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 989                 if ((coef_scaled >> coef_exp) & 0x1)
 990                         break;
 991
 992         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 993
 994         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 995
 996         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 997         *coef_exponent = coef_exp - 16;
 998 }
 999
1000 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1001 {
1002         u32 rst_flags;
1003         u32 tmpReg;
1004
1005         if (AR_SREV_9100(ah)) {
1006                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1007                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1008                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1009                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1010                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1011         }
1012
1013         ENABLE_REGWRITE_BUFFER(ah);
1014
1015         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1016                   AR_RTC_FORCE_WAKE_ON_INT);
1017
1018         if (AR_SREV_9100(ah)) {
1019                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1020                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1021         } else {
1022                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1023                 if (tmpReg &
1024                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1025                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1026                         u32 val;
1027                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1028
1029                         val = AR_RC_HOSTIF;
1030                         if (!AR_SREV_9300_20_OR_LATER(ah))
1031                                 val |= AR_RC_AHB;
1032                         REG_WRITE(ah, AR_RC, val);
1033
1034                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1035                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1036
1037                 rst_flags = AR_RTC_RC_MAC_WARM;
1038                 if (type == ATH9K_RESET_COLD)
1039                         rst_flags |= AR_RTC_RC_MAC_COLD;
1040         }
1041
1042         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1043
1044         REGWRITE_BUFFER_FLUSH(ah);
1045         DISABLE_REGWRITE_BUFFER(ah);
1046
1047         udelay(50);
1048
1049         REG_WRITE(ah, AR_RTC_RC, 0);
1050         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1051                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1052                           "RTC stuck in MAC reset\n");
1053                 return false;
1054         }
1055
1056         if (!AR_SREV_9100(ah))
1057                 REG_WRITE(ah, AR_RC, 0);
1058
1059         if (AR_SREV_9100(ah))
1060                 udelay(50);
1061
1062         return true;
1063 }
1064
1065 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1066 {
1067         ENABLE_REGWRITE_BUFFER(ah);
1068
1069         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1070                   AR_RTC_FORCE_WAKE_ON_INT);
1071
1072         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1073                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1074
1075         REG_WRITE(ah, AR_RTC_RESET, 0);
1076
1077         REGWRITE_BUFFER_FLUSH(ah);
1078         DISABLE_REGWRITE_BUFFER(ah);
1079
1080         if (!AR_SREV_9300_20_OR_LATER(ah))
1081                 udelay(2);
1082
1083         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1084                 REG_WRITE(ah, AR_RC, 0);
1085
1086         REG_WRITE(ah, AR_RTC_RESET, 1);
1087
1088         if (!ath9k_hw_wait(ah,
1089                            AR_RTC_STATUS,
1090                            AR_RTC_STATUS_M,
1091                            AR_RTC_STATUS_ON,
1092                            AH_WAIT_TIMEOUT)) {
1093                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1094                           "RTC not waking up\n");
1095                 return false;
1096         }
1097
1098         ath9k_hw_read_revisions(ah);
1099
1100         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1101 }
1102
1103 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1104 {
1105         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1106                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1107
1108         switch (type) {
1109         case ATH9K_RESET_POWER_ON:
1110                 return ath9k_hw_set_reset_power_on(ah);
1111         case ATH9K_RESET_WARM:
1112         case ATH9K_RESET_COLD:
1113                 return ath9k_hw_set_reset(ah, type);
1114         default:
1115                 return false;
1116         }
1117 }
1118
1119 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1120                                 struct ath9k_channel *chan)
1121 {
1122         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1123                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1124                         return false;
1125         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1126                 return false;
1127
1128         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1129                 return false;
1130
1131         ah->chip_fullsleep = false;
1132         ath9k_hw_init_pll(ah, chan);
1133         ath9k_hw_set_rfmode(ah, chan);
1134
1135         return true;
1136 }
1137
1138 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1139                                     struct ath9k_channel *chan)
1140 {
1141         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1142         struct ath_common *common = ath9k_hw_common(ah);
1143         struct ieee80211_channel *channel = chan->chan;
1144         u32 qnum;
1145         int r;
1146
1147         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1148                 if (ath9k_hw_numtxpending(ah, qnum)) {
1149                         ath_print(common, ATH_DBG_QUEUE,
1150                                   "Transmit frames pending on "
1151                                   "queue %d\n", qnum);
1152                         return false;
1153                 }
1154         }
1155
1156         if (!ath9k_hw_rfbus_req(ah)) {
1157                 ath_print(common, ATH_DBG_FATAL,
1158                           "Could not kill baseband RX\n");
1159                 return false;
1160         }
1161
1162         ath9k_hw_set_channel_regs(ah, chan);
1163
1164         r = ath9k_hw_rf_set_freq(ah, chan);
1165         if (r) {
1166                 ath_print(common, ATH_DBG_FATAL,
1167                           "Failed to set channel\n");
1168                 return false;
1169         }
1170
1171         ah->eep_ops->set_txpower(ah, chan,
1172                              ath9k_regd_get_ctl(regulatory, chan),
1173                              channel->max_antenna_gain * 2,
1174                              channel->max_power * 2,
1175                              min((u32) MAX_RATE_POWER,
1176                              (u32) regulatory->power_limit));
1177
1178         ath9k_hw_rfbus_done(ah);
1179
1180         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1181                 ath9k_hw_set_delta_slope(ah, chan);
1182
1183         ath9k_hw_spur_mitigate_freq(ah, chan);
1184
1185         if (!chan->oneTimeCalsDone)
1186                 chan->oneTimeCalsDone = true;
1187
1188         return true;
1189 }
1190
1191 bool ath9k_hw_check_alive(struct ath_hw *ah)
1192 {
1193         int count = 50;
1194         u32 reg;
1195
1196         if (AR_SREV_9285_10_OR_LATER(ah))
1197                 return true;
1198
1199         do {
1200                 reg = REG_READ(ah, AR_OBS_BUS_1);
1201
1202                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1203                         continue;
1204
1205                 switch (reg & 0x7E000B00) {
1206                 case 0x1E000000:
1207                 case 0x52000B00:
1208                 case 0x18000B00:
1209                         continue;
1210                 default:
1211                         return true;
1212                 }
1213         } while (count-- > 0);
1214
1215         return false;
1216 }
1217 EXPORT_SYMBOL(ath9k_hw_check_alive);
1218
1219 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1220                     bool bChannelChange)
1221 {
1222         struct ath_common *common = ath9k_hw_common(ah);
1223         u32 saveLedState;
1224         struct ath9k_channel *curchan = ah->curchan;
1225         u32 saveDefAntenna;
1226         u32 macStaId1;
1227         u64 tsf = 0;
1228         int i, r;
1229
1230         ah->txchainmask = common->tx_chainmask;
1231         ah->rxchainmask = common->rx_chainmask;
1232
1233         if (!ah->chip_fullsleep) {
1234                 ath9k_hw_abortpcurecv(ah);
1235                 if (!ath9k_hw_stopdmarecv(ah))
1236                         ath_print(common, ATH_DBG_XMIT,
1237                                 "Failed to stop receive dma\n");
1238         }
1239
1240         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1241                 return -EIO;
1242
1243         if (curchan && !ah->chip_fullsleep)
1244                 ath9k_hw_getnf(ah, curchan);
1245
1246         if (bChannelChange &&
1247             (ah->chip_fullsleep != true) &&
1248             (ah->curchan != NULL) &&
1249             (chan->channel != ah->curchan->channel) &&
1250             ((chan->channelFlags & CHANNEL_ALL) ==
1251              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1252             !AR_SREV_9280(ah)) {
1253
1254                 if (ath9k_hw_channel_change(ah, chan)) {
1255                         ath9k_hw_loadnf(ah, ah->curchan);
1256                         ath9k_hw_start_nfcal(ah);
1257                         return 0;
1258                 }
1259         }
1260
1261         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1262         if (saveDefAntenna == 0)
1263                 saveDefAntenna = 1;
1264
1265         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1266
1267         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1268         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1269                 tsf = ath9k_hw_gettsf64(ah);
1270
1271         saveLedState = REG_READ(ah, AR_CFG_LED) &
1272                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1273                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1274
1275         ath9k_hw_mark_phy_inactive(ah);
1276
1277         /* Only required on the first reset */
1278         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1279                 REG_WRITE(ah,
1280                           AR9271_RESET_POWER_DOWN_CONTROL,
1281                           AR9271_RADIO_RF_RST);
1282                 udelay(50);
1283         }
1284
1285         if (!ath9k_hw_chip_reset(ah, chan)) {
1286                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1287                 return -EINVAL;
1288         }
1289
1290         /* Only required on the first reset */
1291         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1292                 ah->htc_reset_init = false;
1293                 REG_WRITE(ah,
1294                           AR9271_RESET_POWER_DOWN_CONTROL,
1295                           AR9271_GATE_MAC_CTL);
1296                 udelay(50);
1297         }
1298
1299         /* Restore TSF */
1300         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1301                 ath9k_hw_settsf64(ah, tsf);
1302
1303         if (AR_SREV_9280_10_OR_LATER(ah))
1304                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1305
1306         r = ath9k_hw_process_ini(ah, chan);
1307         if (r)
1308                 return r;
1309
1310         /* Setup MFP options for CCMP */
1311         if (AR_SREV_9280_20_OR_LATER(ah)) {
1312                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1313                  * frames when constructing CCMP AAD. */
1314                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1315                               0xc7ff);
1316                 ah->sw_mgmt_crypto = false;
1317         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1318                 /* Disable hardware crypto for management frames */
1319                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1320                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1321                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1322                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1323                 ah->sw_mgmt_crypto = true;
1324         } else
1325                 ah->sw_mgmt_crypto = true;
1326
1327         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1328                 ath9k_hw_set_delta_slope(ah, chan);
1329
1330         ath9k_hw_spur_mitigate_freq(ah, chan);
1331         ah->eep_ops->set_board_values(ah, chan);
1332
1333         ath9k_hw_set_operating_mode(ah, ah->opmode);
1334
1335         ENABLE_REGWRITE_BUFFER(ah);
1336
1337         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1338         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1339                   | macStaId1
1340                   | AR_STA_ID1_RTS_USE_DEF
1341                   | (ah->config.
1342                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1343                   | ah->sta_id1_defaults);
1344         ath_hw_setbssidmask(common);
1345         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1346         ath9k_hw_write_associd(ah);
1347         REG_WRITE(ah, AR_ISR, ~0);
1348         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1349
1350         REGWRITE_BUFFER_FLUSH(ah);
1351         DISABLE_REGWRITE_BUFFER(ah);
1352
1353         r = ath9k_hw_rf_set_freq(ah, chan);
1354         if (r)
1355                 return r;
1356
1357         ENABLE_REGWRITE_BUFFER(ah);
1358
1359         for (i = 0; i < AR_NUM_DCU; i++)
1360                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1361
1362         REGWRITE_BUFFER_FLUSH(ah);
1363         DISABLE_REGWRITE_BUFFER(ah);
1364
1365         ah->intr_txqs = 0;
1366         for (i = 0; i < ah->caps.total_queues; i++)
1367                 ath9k_hw_resettxqueue(ah, i);
1368
1369         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1370         ath9k_hw_init_qos(ah);
1371
1372         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1373                 ath9k_enable_rfkill(ah);
1374
1375         ath9k_hw_init_global_settings(ah);
1376
1377         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1378                 ar9002_hw_enable_async_fifo(ah);
1379                 ar9002_hw_enable_wep_aggregation(ah);
1380         }
1381
1382         REG_WRITE(ah, AR_STA_ID1,
1383                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1384
1385         ath9k_hw_set_dma(ah);
1386
1387         REG_WRITE(ah, AR_OBS, 8);
1388
1389         if (ah->config.rx_intr_mitigation) {
1390                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1391                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1392         }
1393
1394         if (ah->config.tx_intr_mitigation) {
1395                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1396                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1397         }
1398
1399         ath9k_hw_init_bb(ah, chan);
1400
1401         if (!ath9k_hw_init_cal(ah, chan))
1402                 return -EIO;
1403
1404         ENABLE_REGWRITE_BUFFER(ah);
1405
1406         ath9k_hw_restore_chainmask(ah);
1407         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1408
1409         REGWRITE_BUFFER_FLUSH(ah);
1410         DISABLE_REGWRITE_BUFFER(ah);
1411
1412         /*
1413          * For big endian systems turn on swapping for descriptors
1414          */
1415         if (AR_SREV_9100(ah)) {
1416                 u32 mask;
1417                 mask = REG_READ(ah, AR_CFG);
1418                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1419                         ath_print(common, ATH_DBG_RESET,
1420                                 "CFG Byte Swap Set 0x%x\n", mask);
1421                 } else {
1422                         mask =
1423                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1424                         REG_WRITE(ah, AR_CFG, mask);
1425                         ath_print(common, ATH_DBG_RESET,
1426                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1427                 }
1428         } else {
1429                 /* Configure AR9271 target WLAN */
1430                 if (AR_SREV_9271(ah))
1431                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1432 #ifdef __BIG_ENDIAN
1433                 else
1434                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1435 #endif
1436         }
1437
1438         if (ah->btcoex_hw.enabled)
1439                 ath9k_hw_btcoex_enable(ah);
1440
1441         if (AR_SREV_9300_20_OR_LATER(ah)) {
1442                 ath9k_hw_loadnf(ah, curchan);
1443                 ath9k_hw_start_nfcal(ah);
1444         }
1445
1446         return 0;
1447 }
1448 EXPORT_SYMBOL(ath9k_hw_reset);
1449
1450 /************************/
1451 /* Key Cache Management */
1452 /************************/
1453
1454 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1455 {
1456         u32 keyType;
1457
1458         if (entry >= ah->caps.keycache_size) {
1459                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1460                           "keychache entry %u out of range\n", entry);
1461                 return false;
1462         }
1463
1464         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1465
1466         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1467         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1468         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1469         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1470         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1471         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1472         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1473         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1474
1475         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1476                 u16 micentry = entry + 64;
1477
1478                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1479                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1480                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1481                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1482
1483         }
1484
1485         return true;
1486 }
1487 EXPORT_SYMBOL(ath9k_hw_keyreset);
1488
1489 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1490 {
1491         u32 macHi, macLo;
1492
1493         if (entry >= ah->caps.keycache_size) {
1494                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1495                           "keychache entry %u out of range\n", entry);
1496                 return false;
1497         }
1498
1499         if (mac != NULL) {
1500                 macHi = (mac[5] << 8) | mac[4];
1501                 macLo = (mac[3] << 24) |
1502                         (mac[2] << 16) |
1503                         (mac[1] << 8) |
1504                         mac[0];
1505                 macLo >>= 1;
1506                 macLo |= (macHi & 1) << 31;
1507                 macHi >>= 1;
1508         } else {
1509                 macLo = macHi = 0;
1510         }
1511         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1512         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1513
1514         return true;
1515 }
1516 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1517
1518 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1519                                  const struct ath9k_keyval *k,
1520                                  const u8 *mac)
1521 {
1522         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1523         struct ath_common *common = ath9k_hw_common(ah);
1524         u32 key0, key1, key2, key3, key4;
1525         u32 keyType;
1526
1527         if (entry >= pCap->keycache_size) {
1528                 ath_print(common, ATH_DBG_FATAL,
1529                           "keycache entry %u out of range\n", entry);
1530                 return false;
1531         }
1532
1533         switch (k->kv_type) {
1534         case ATH9K_CIPHER_AES_OCB:
1535                 keyType = AR_KEYTABLE_TYPE_AES;
1536                 break;
1537         case ATH9K_CIPHER_AES_CCM:
1538                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1539                         ath_print(common, ATH_DBG_ANY,
1540                                   "AES-CCM not supported by mac rev 0x%x\n",
1541                                   ah->hw_version.macRev);
1542                         return false;
1543                 }
1544                 keyType = AR_KEYTABLE_TYPE_CCM;
1545                 break;
1546         case ATH9K_CIPHER_TKIP:
1547                 keyType = AR_KEYTABLE_TYPE_TKIP;
1548                 if (ATH9K_IS_MIC_ENABLED(ah)
1549                     && entry + 64 >= pCap->keycache_size) {
1550                         ath_print(common, ATH_DBG_ANY,
1551                                   "entry %u inappropriate for TKIP\n", entry);
1552                         return false;
1553                 }
1554                 break;
1555         case ATH9K_CIPHER_WEP:
1556                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1557                         ath_print(common, ATH_DBG_ANY,
1558                                   "WEP key length %u too small\n", k->kv_len);
1559                         return false;
1560                 }
1561                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1562                         keyType = AR_KEYTABLE_TYPE_40;
1563                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1564                         keyType = AR_KEYTABLE_TYPE_104;
1565                 else
1566                         keyType = AR_KEYTABLE_TYPE_128;
1567                 break;
1568         case ATH9K_CIPHER_CLR:
1569                 keyType = AR_KEYTABLE_TYPE_CLR;
1570                 break;
1571         default:
1572                 ath_print(common, ATH_DBG_FATAL,
1573                           "cipher %u not supported\n", k->kv_type);
1574                 return false;
1575         }
1576
1577         key0 = get_unaligned_le32(k->kv_val + 0);
1578         key1 = get_unaligned_le16(k->kv_val + 4);
1579         key2 = get_unaligned_le32(k->kv_val + 6);
1580         key3 = get_unaligned_le16(k->kv_val + 10);
1581         key4 = get_unaligned_le32(k->kv_val + 12);
1582         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1583                 key4 &= 0xff;
1584
1585         /*
1586          * Note: Key cache registers access special memory area that requires
1587          * two 32-bit writes to actually update the values in the internal
1588          * memory. Consequently, the exact order and pairs used here must be
1589          * maintained.
1590          */
1591
1592         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1593                 u16 micentry = entry + 64;
1594
1595                 /*
1596                  * Write inverted key[47:0] first to avoid Michael MIC errors
1597                  * on frames that could be sent or received at the same time.
1598                  * The correct key will be written in the end once everything
1599                  * else is ready.
1600                  */
1601                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1602                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1603
1604                 /* Write key[95:48] */
1605                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1606                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1607
1608                 /* Write key[127:96] and key type */
1609                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1610                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1611
1612                 /* Write MAC address for the entry */
1613                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1614
1615                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1616                         /*
1617                          * TKIP uses two key cache entries:
1618                          * Michael MIC TX/RX keys in the same key cache entry
1619                          * (idx = main index + 64):
1620                          * key0 [31:0] = RX key [31:0]
1621                          * key1 [15:0] = TX key [31:16]
1622                          * key1 [31:16] = reserved
1623                          * key2 [31:0] = RX key [63:32]
1624                          * key3 [15:0] = TX key [15:0]
1625                          * key3 [31:16] = reserved
1626                          * key4 [31:0] = TX key [63:32]
1627                          */
1628                         u32 mic0, mic1, mic2, mic3, mic4;
1629
1630                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1631                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1632                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1633                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1634                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1635
1636                         /* Write RX[31:0] and TX[31:16] */
1637                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1638                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1639
1640                         /* Write RX[63:32] and TX[15:0] */
1641                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1642                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1643
1644                         /* Write TX[63:32] and keyType(reserved) */
1645                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1646                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1647                                   AR_KEYTABLE_TYPE_CLR);
1648
1649                 } else {
1650                         /*
1651                          * TKIP uses four key cache entries (two for group
1652                          * keys):
1653                          * Michael MIC TX/RX keys are in different key cache
1654                          * entries (idx = main index + 64 for TX and
1655                          * main index + 32 + 96 for RX):
1656                          * key0 [31:0] = TX/RX MIC key [31:0]
1657                          * key1 [31:0] = reserved
1658                          * key2 [31:0] = TX/RX MIC key [63:32]
1659                          * key3 [31:0] = reserved
1660                          * key4 [31:0] = reserved
1661                          *
1662                          * Upper layer code will call this function separately
1663                          * for TX and RX keys when these registers offsets are
1664                          * used.
1665                          */
1666                         u32 mic0, mic2;
1667
1668                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1669                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1670
1671                         /* Write MIC key[31:0] */
1672                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1673                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1674
1675                         /* Write MIC key[63:32] */
1676                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1677                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1678
1679                         /* Write TX[63:32] and keyType(reserved) */
1680                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1681                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1682                                   AR_KEYTABLE_TYPE_CLR);
1683                 }
1684
1685                 /* MAC address registers are reserved for the MIC entry */
1686                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1687                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1688
1689                 /*
1690                  * Write the correct (un-inverted) key[47:0] last to enable
1691                  * TKIP now that all other registers are set with correct
1692                  * values.
1693                  */
1694                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1695                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1696         } else {
1697                 /* Write key[47:0] */
1698                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1699                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1700
1701                 /* Write key[95:48] */
1702                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1703                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1704
1705                 /* Write key[127:96] and key type */
1706                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1707                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1708
1709                 /* Write MAC address for the entry */
1710                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1711         }
1712
1713         return true;
1714 }
1715 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1716
1717 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1718 {
1719         if (entry < ah->caps.keycache_size) {
1720                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1721                 if (val & AR_KEYTABLE_VALID)
1722                         return true;
1723         }
1724         return false;
1725 }
1726 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1727
1728 /******************************/
1729 /* Power Management (Chipset) */
1730 /******************************/
1731
1732 /*
1733  * Notify Power Mgt is disabled in self-generated frames.
1734  * If requested, force chip to sleep.
1735  */
1736 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1737 {
1738         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1739         if (setChip) {
1740                 /*
1741                  * Clear the RTC force wake bit to allow the
1742                  * mac to go to sleep.
1743                  */
1744                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1745                             AR_RTC_FORCE_WAKE_EN);
1746                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1747                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1748
1749                 /* Shutdown chip. Active low */
1750                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1751                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1752                                     AR_RTC_RESET_EN);
1753         }
1754 }
1755
1756 /*
1757  * Notify Power Management is enabled in self-generating
1758  * frames. If request, set power mode of chip to
1759  * auto/normal.  Duration in units of 128us (1/8 TU).
1760  */
1761 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1762 {
1763         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1764         if (setChip) {
1765                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1766
1767                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1768                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1769                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1770                                   AR_RTC_FORCE_WAKE_ON_INT);
1771                 } else {
1772                         /*
1773                          * Clear the RTC force wake bit to allow the
1774                          * mac to go to sleep.
1775                          */
1776                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1777                                     AR_RTC_FORCE_WAKE_EN);
1778                 }
1779         }
1780 }
1781
1782 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1783 {
1784         u32 val;
1785         int i;
1786
1787         if (setChip) {
1788                 if ((REG_READ(ah, AR_RTC_STATUS) &
1789                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1790                         if (ath9k_hw_set_reset_reg(ah,
1791                                            ATH9K_RESET_POWER_ON) != true) {
1792                                 return false;
1793                         }
1794                         if (!AR_SREV_9300_20_OR_LATER(ah))
1795                                 ath9k_hw_init_pll(ah, NULL);
1796                 }
1797                 if (AR_SREV_9100(ah))
1798                         REG_SET_BIT(ah, AR_RTC_RESET,
1799                                     AR_RTC_RESET_EN);
1800
1801                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1802                             AR_RTC_FORCE_WAKE_EN);
1803                 udelay(50);
1804
1805                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1806                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1807                         if (val == AR_RTC_STATUS_ON)
1808                                 break;
1809                         udelay(50);
1810                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1811                                     AR_RTC_FORCE_WAKE_EN);
1812                 }
1813                 if (i == 0) {
1814                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1815                                   "Failed to wakeup in %uus\n",
1816                                   POWER_UP_TIME / 20);
1817                         return false;
1818                 }
1819         }
1820
1821         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1822
1823         return true;
1824 }
1825
1826 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1827 {
1828         struct ath_common *common = ath9k_hw_common(ah);
1829         int status = true, setChip = true;
1830         static const char *modes[] = {
1831                 "AWAKE",
1832                 "FULL-SLEEP",
1833                 "NETWORK SLEEP",
1834                 "UNDEFINED"
1835         };
1836
1837         if (ah->power_mode == mode)
1838                 return status;
1839
1840         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1841                   modes[ah->power_mode], modes[mode]);
1842
1843         switch (mode) {
1844         case ATH9K_PM_AWAKE:
1845                 status = ath9k_hw_set_power_awake(ah, setChip);
1846                 break;
1847         case ATH9K_PM_FULL_SLEEP:
1848                 ath9k_set_power_sleep(ah, setChip);
1849                 ah->chip_fullsleep = true;
1850                 break;
1851         case ATH9K_PM_NETWORK_SLEEP:
1852                 ath9k_set_power_network_sleep(ah, setChip);
1853                 break;
1854         default:
1855                 ath_print(common, ATH_DBG_FATAL,
1856                           "Unknown power mode %u\n", mode);
1857                 return false;
1858         }
1859         ah->power_mode = mode;
1860
1861         return status;
1862 }
1863 EXPORT_SYMBOL(ath9k_hw_setpower);
1864
1865 /*******************/
1866 /* Beacon Handling */
1867 /*******************/
1868
1869 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1870 {
1871         int flags = 0;
1872
1873         ah->beacon_interval = beacon_period;
1874
1875         ENABLE_REGWRITE_BUFFER(ah);
1876
1877         switch (ah->opmode) {
1878         case NL80211_IFTYPE_STATION:
1879         case NL80211_IFTYPE_MONITOR:
1880                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1881                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1882                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1883                 flags |= AR_TBTT_TIMER_EN;
1884                 break;
1885         case NL80211_IFTYPE_ADHOC:
1886         case NL80211_IFTYPE_MESH_POINT:
1887                 REG_SET_BIT(ah, AR_TXCFG,
1888                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1889                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1890                           TU_TO_USEC(next_beacon +
1891                                      (ah->atim_window ? ah->
1892                                       atim_window : 1)));
1893                 flags |= AR_NDP_TIMER_EN;
1894         case NL80211_IFTYPE_AP:
1895                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1896                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1897                           TU_TO_USEC(next_beacon -
1898                                      ah->config.
1899                                      dma_beacon_response_time));
1900                 REG_WRITE(ah, AR_NEXT_SWBA,
1901                           TU_TO_USEC(next_beacon -
1902                                      ah->config.
1903                                      sw_beacon_response_time));
1904                 flags |=
1905                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1906                 break;
1907         default:
1908                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1909                           "%s: unsupported opmode: %d\n",
1910                           __func__, ah->opmode);
1911                 return;
1912                 break;
1913         }
1914
1915         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1916         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1917         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1918         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1919
1920         REGWRITE_BUFFER_FLUSH(ah);
1921         DISABLE_REGWRITE_BUFFER(ah);
1922
1923         beacon_period &= ~ATH9K_BEACON_ENA;
1924         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1925                 ath9k_hw_reset_tsf(ah);
1926         }
1927
1928         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1929 }
1930 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1931
1932 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1933                                     const struct ath9k_beacon_state *bs)
1934 {
1935         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1936         struct ath9k_hw_capabilities *pCap = &ah->caps;
1937         struct ath_common *common = ath9k_hw_common(ah);
1938
1939         ENABLE_REGWRITE_BUFFER(ah);
1940
1941         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1942
1943         REG_WRITE(ah, AR_BEACON_PERIOD,
1944                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1945         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1946                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1947
1948         REGWRITE_BUFFER_FLUSH(ah);
1949         DISABLE_REGWRITE_BUFFER(ah);
1950
1951         REG_RMW_FIELD(ah, AR_RSSI_THR,
1952                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1953
1954         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1955
1956         if (bs->bs_sleepduration > beaconintval)
1957                 beaconintval = bs->bs_sleepduration;
1958
1959         dtimperiod = bs->bs_dtimperiod;
1960         if (bs->bs_sleepduration > dtimperiod)
1961                 dtimperiod = bs->bs_sleepduration;
1962
1963         if (beaconintval == dtimperiod)
1964                 nextTbtt = bs->bs_nextdtim;
1965         else
1966                 nextTbtt = bs->bs_nexttbtt;
1967
1968         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1969         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1970         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1971         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1972
1973         ENABLE_REGWRITE_BUFFER(ah);
1974
1975         REG_WRITE(ah, AR_NEXT_DTIM,
1976                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1977         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1978
1979         REG_WRITE(ah, AR_SLEEP1,
1980                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1981                   | AR_SLEEP1_ASSUME_DTIM);
1982
1983         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1984                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1985         else
1986                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1987
1988         REG_WRITE(ah, AR_SLEEP2,
1989                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1990
1991         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1992         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1993
1994         REGWRITE_BUFFER_FLUSH(ah);
1995         DISABLE_REGWRITE_BUFFER(ah);
1996
1997         REG_SET_BIT(ah, AR_TIMER_MODE,
1998                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1999                     AR_DTIM_TIMER_EN);
2000
2001         /* TSF Out of Range Threshold */
2002         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2003 }
2004 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2005
2006 /*******************/
2007 /* HW Capabilities */
2008 /*******************/
2009
2010 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2011 {
2012         struct ath9k_hw_capabilities *pCap = &ah->caps;
2013         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2014         struct ath_common *common = ath9k_hw_common(ah);
2015         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2016
2017         u16 capField = 0, eeval;
2018
2019         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2020         regulatory->current_rd = eeval;
2021
2022         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2023         if (AR_SREV_9285_10_OR_LATER(ah))
2024                 eeval |= AR9285_RDEXT_DEFAULT;
2025         regulatory->current_rd_ext = eeval;
2026
2027         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2028
2029         if (ah->opmode != NL80211_IFTYPE_AP &&
2030             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2031                 if (regulatory->current_rd == 0x64 ||
2032                     regulatory->current_rd == 0x65)
2033                         regulatory->current_rd += 5;
2034                 else if (regulatory->current_rd == 0x41)
2035                         regulatory->current_rd = 0x43;
2036                 ath_print(common, ATH_DBG_REGULATORY,
2037                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2038         }
2039
2040         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2041         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2042                 ath_print(common, ATH_DBG_FATAL,
2043                           "no band has been marked as supported in EEPROM.\n");
2044                 return -EINVAL;
2045         }
2046
2047         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2048
2049         if (eeval & AR5416_OPFLAGS_11A) {
2050                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2051                 if (ah->config.ht_enable) {
2052                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2053                                 set_bit(ATH9K_MODE_11NA_HT20,
2054                                         pCap->wireless_modes);
2055                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2056                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2057                                         pCap->wireless_modes);
2058                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2059                                         pCap->wireless_modes);
2060                         }
2061                 }
2062         }
2063
2064         if (eeval & AR5416_OPFLAGS_11G) {
2065                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2066                 if (ah->config.ht_enable) {
2067                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2068                                 set_bit(ATH9K_MODE_11NG_HT20,
2069                                         pCap->wireless_modes);
2070                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2071                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2072                                         pCap->wireless_modes);
2073                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2074                                         pCap->wireless_modes);
2075                         }
2076                 }
2077         }
2078
2079         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2080         /*
2081          * For AR9271 we will temporarilly uses the rx chainmax as read from
2082          * the EEPROM.
2083          */
2084         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2085             !(eeval & AR5416_OPFLAGS_11A) &&
2086             !(AR_SREV_9271(ah)))
2087                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2088                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2089         else
2090                 /* Use rx_chainmask from EEPROM. */
2091                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2092
2093         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2094                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2095
2096         pCap->low_2ghz_chan = 2312;
2097         pCap->high_2ghz_chan = 2732;
2098
2099         pCap->low_5ghz_chan = 4920;
2100         pCap->high_5ghz_chan = 6100;
2101
2102         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2103         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2104         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2105
2106         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2107         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2108         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2109
2110         if (ah->config.ht_enable)
2111                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2112         else
2113                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2114
2115         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2116         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2117         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2118         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2119
2120         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2121                 pCap->total_queues =
2122                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2123         else
2124                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2125
2126         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2127                 pCap->keycache_size =
2128                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2129         else
2130                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2131
2132         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2133
2134         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2135                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2136         else
2137                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2138
2139         if (AR_SREV_9271(ah))
2140                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2141         else if (AR_SREV_9285_10_OR_LATER(ah))
2142                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2143         else if (AR_SREV_9280_10_OR_LATER(ah))
2144                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2145         else
2146                 pCap->num_gpio_pins = AR_NUM_GPIO;
2147
2148         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2149                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2150                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2151         } else {
2152                 pCap->rts_aggr_limit = (8 * 1024);
2153         }
2154
2155         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2156
2157 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2158         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2159         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2160                 ah->rfkill_gpio =
2161                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2162                 ah->rfkill_polarity =
2163                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2164
2165                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2166         }
2167 #endif
2168         if (AR_SREV_9271(ah))
2169                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2170         else
2171                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2172
2173         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2174                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2175         else
2176                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2177
2178         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2179                 pCap->reg_cap =
2180                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2181                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2182                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2183                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2184         } else {
2185                 pCap->reg_cap =
2186                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2187                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2188         }
2189
2190         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2191         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2192             AR_SREV_5416(ah))
2193                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2194
2195         pCap->num_antcfg_5ghz =
2196                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2197         pCap->num_antcfg_2ghz =
2198                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2199
2200         if (AR_SREV_9280_10_OR_LATER(ah) &&
2201             ath9k_hw_btcoex_supported(ah)) {
2202                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2203                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2204
2205                 if (AR_SREV_9285(ah)) {
2206                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2207                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2208                 } else {
2209                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2210                 }
2211         } else {
2212                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2213         }
2214
2215         if (AR_SREV_9300_20_OR_LATER(ah)) {
2216                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2217                                  ATH9K_HW_CAP_FASTCLOCK;
2218                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2219                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2220                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2221                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2222                 pCap->txs_len = sizeof(struct ar9003_txs);
2223         } else {
2224                 pCap->tx_desc_len = sizeof(struct ath_desc);
2225                 if (AR_SREV_9280_20(ah) &&
2226                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2227                       AR5416_EEP_MINOR_VER_16) ||
2228                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2229                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2230         }
2231
2232         if (AR_SREV_9300_20_OR_LATER(ah))
2233                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2234
2235         return 0;
2236 }
2237
2238 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2239                             u32 capability, u32 *result)
2240 {
2241         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2242         switch (type) {
2243         case ATH9K_CAP_CIPHER:
2244                 switch (capability) {
2245                 case ATH9K_CIPHER_AES_CCM:
2246                 case ATH9K_CIPHER_AES_OCB:
2247                 case ATH9K_CIPHER_TKIP:
2248                 case ATH9K_CIPHER_WEP:
2249                 case ATH9K_CIPHER_MIC:
2250                 case ATH9K_CIPHER_CLR:
2251                         return true;
2252                 default:
2253                         return false;
2254                 }
2255         case ATH9K_CAP_TKIP_MIC:
2256                 switch (capability) {
2257                 case 0:
2258                         return true;
2259                 case 1:
2260                         return (ah->sta_id1_defaults &
2261                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2262                         false;
2263                 }
2264         case ATH9K_CAP_TKIP_SPLIT:
2265                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2266                         false : true;
2267         case ATH9K_CAP_MCAST_KEYSRCH:
2268                 switch (capability) {
2269                 case 0:
2270                         return true;
2271                 case 1:
2272                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2273                                 return false;
2274                         } else {
2275                                 return (ah->sta_id1_defaults &
2276                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2277                                         false;
2278                         }
2279                 }
2280                 return false;
2281         case ATH9K_CAP_TXPOW:
2282                 switch (capability) {
2283                 case 0:
2284                         return 0;
2285                 case 1:
2286                         *result = regulatory->power_limit;
2287                         return 0;
2288                 case 2:
2289                         *result = regulatory->max_power_level;
2290                         return 0;
2291                 case 3:
2292                         *result = regulatory->tp_scale;
2293                         return 0;
2294                 }
2295                 return false;
2296         case ATH9K_CAP_DS:
2297                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2298                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2299                         ? false : true;
2300         default:
2301                 return false;
2302         }
2303 }
2304 EXPORT_SYMBOL(ath9k_hw_getcapability);
2305
2306 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2307                             u32 capability, u32 setting, int *status)
2308 {
2309         switch (type) {
2310         case ATH9K_CAP_TKIP_MIC:
2311                 if (setting)
2312                         ah->sta_id1_defaults |=
2313                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2314                 else
2315                         ah->sta_id1_defaults &=
2316                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2317                 return true;
2318         case ATH9K_CAP_MCAST_KEYSRCH:
2319                 if (setting)
2320                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2321                 else
2322                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2323                 return true;
2324         default:
2325                 return false;
2326         }
2327 }
2328 EXPORT_SYMBOL(ath9k_hw_setcapability);
2329
2330 /****************************/
2331 /* GPIO / RFKILL / Antennae */
2332 /****************************/
2333
2334 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2335                                          u32 gpio, u32 type)
2336 {
2337         int addr;
2338         u32 gpio_shift, tmp;
2339
2340         if (gpio > 11)
2341                 addr = AR_GPIO_OUTPUT_MUX3;
2342         else if (gpio > 5)
2343                 addr = AR_GPIO_OUTPUT_MUX2;
2344         else
2345                 addr = AR_GPIO_OUTPUT_MUX1;
2346
2347         gpio_shift = (gpio % 6) * 5;
2348
2349         if (AR_SREV_9280_20_OR_LATER(ah)
2350             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2351                 REG_RMW(ah, addr, (type << gpio_shift),
2352                         (0x1f << gpio_shift));
2353         } else {
2354                 tmp = REG_READ(ah, addr);
2355                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2356                 tmp &= ~(0x1f << gpio_shift);
2357                 tmp |= (type << gpio_shift);
2358                 REG_WRITE(ah, addr, tmp);
2359         }
2360 }
2361
2362 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2363 {
2364         u32 gpio_shift;
2365
2366         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2367
2368         gpio_shift = gpio << 1;
2369
2370         REG_RMW(ah,
2371                 AR_GPIO_OE_OUT,
2372                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2373                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2374 }
2375 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2376
2377 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2378 {
2379 #define MS_REG_READ(x, y) \
2380         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2381
2382         if (gpio >= ah->caps.num_gpio_pins)
2383                 return 0xffffffff;
2384
2385         if (AR_SREV_9300_20_OR_LATER(ah))
2386                 return MS_REG_READ(AR9300, gpio) != 0;
2387         else if (AR_SREV_9271(ah))
2388                 return MS_REG_READ(AR9271, gpio) != 0;
2389         else if (AR_SREV_9287_10_OR_LATER(ah))
2390                 return MS_REG_READ(AR9287, gpio) != 0;
2391         else if (AR_SREV_9285_10_OR_LATER(ah))
2392                 return MS_REG_READ(AR9285, gpio) != 0;
2393         else if (AR_SREV_9280_10_OR_LATER(ah))
2394                 return MS_REG_READ(AR928X, gpio) != 0;
2395         else
2396                 return MS_REG_READ(AR, gpio) != 0;
2397 }
2398 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2399
2400 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2401                          u32 ah_signal_type)
2402 {
2403         u32 gpio_shift;
2404
2405         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2406
2407         gpio_shift = 2 * gpio;
2408
2409         REG_RMW(ah,
2410                 AR_GPIO_OE_OUT,
2411                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2412                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2413 }
2414 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2415
2416 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2417 {
2418         if (AR_SREV_9271(ah))
2419                 val = ~val;
2420
2421         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2422                 AR_GPIO_BIT(gpio));
2423 }
2424 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2425
2426 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2427 {
2428         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2429 }
2430 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2431
2432 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2433 {
2434         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2435 }
2436 EXPORT_SYMBOL(ath9k_hw_setantenna);
2437
2438 /*********************/
2439 /* General Operation */
2440 /*********************/
2441
2442 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2443 {
2444         u32 bits = REG_READ(ah, AR_RX_FILTER);
2445         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2446
2447         if (phybits & AR_PHY_ERR_RADAR)
2448                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2449         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2450                 bits |= ATH9K_RX_FILTER_PHYERR;
2451
2452         return bits;
2453 }
2454 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2455
2456 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2457 {
2458         u32 phybits;
2459
2460         ENABLE_REGWRITE_BUFFER(ah);
2461
2462         REG_WRITE(ah, AR_RX_FILTER, bits);
2463
2464         phybits = 0;
2465         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2466                 phybits |= AR_PHY_ERR_RADAR;
2467         if (bits & ATH9K_RX_FILTER_PHYERR)
2468                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2469         REG_WRITE(ah, AR_PHY_ERR, phybits);
2470
2471         if (phybits)
2472                 REG_WRITE(ah, AR_RXCFG,
2473                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2474         else
2475                 REG_WRITE(ah, AR_RXCFG,
2476                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2477
2478         REGWRITE_BUFFER_FLUSH(ah);
2479         DISABLE_REGWRITE_BUFFER(ah);
2480 }
2481 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2482
2483 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2484 {
2485         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2486                 return false;
2487
2488         ath9k_hw_init_pll(ah, NULL);
2489         return true;
2490 }
2491 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2492
2493 bool ath9k_hw_disable(struct ath_hw *ah)
2494 {
2495         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2496                 return false;
2497
2498         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2499                 return false;
2500
2501         ath9k_hw_init_pll(ah, NULL);
2502         return true;
2503 }
2504 EXPORT_SYMBOL(ath9k_hw_disable);
2505
2506 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2507 {
2508         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2509         struct ath9k_channel *chan = ah->curchan;
2510         struct ieee80211_channel *channel = chan->chan;
2511
2512         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2513
2514         ah->eep_ops->set_txpower(ah, chan,
2515                                  ath9k_regd_get_ctl(regulatory, chan),
2516                                  channel->max_antenna_gain * 2,
2517                                  channel->max_power * 2,
2518                                  min((u32) MAX_RATE_POWER,
2519                                  (u32) regulatory->power_limit));
2520 }
2521 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2522
2523 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2524 {
2525         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2526 }
2527 EXPORT_SYMBOL(ath9k_hw_setmac);
2528
2529 void ath9k_hw_setopmode(struct ath_hw *ah)
2530 {
2531         ath9k_hw_set_operating_mode(ah, ah->opmode);
2532 }
2533 EXPORT_SYMBOL(ath9k_hw_setopmode);
2534
2535 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2536 {
2537         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2538         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2539 }
2540 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2541
2542 void ath9k_hw_write_associd(struct ath_hw *ah)
2543 {
2544         struct ath_common *common = ath9k_hw_common(ah);
2545
2546         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2547         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2548                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2549 }
2550 EXPORT_SYMBOL(ath9k_hw_write_associd);
2551
2552 #define ATH9K_MAX_TSF_READ 10
2553
2554 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2555 {
2556         u32 tsf_lower, tsf_upper1, tsf_upper2;
2557         int i;
2558
2559         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2560         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2561                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2562                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2563                 if (tsf_upper2 == tsf_upper1)
2564                         break;
2565                 tsf_upper1 = tsf_upper2;
2566         }
2567
2568         WARN_ON( i == ATH9K_MAX_TSF_READ );
2569
2570         return (((u64)tsf_upper1 << 32) | tsf_lower);
2571 }
2572 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2573
2574 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2575 {
2576         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2577         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2578 }
2579 EXPORT_SYMBOL(ath9k_hw_settsf64);
2580
2581 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2582 {
2583         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2584                            AH_TSF_WRITE_TIMEOUT))
2585                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2586                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2587
2588         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2589 }
2590 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2591
2592 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2593 {
2594         if (setting)
2595                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2596         else
2597                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2598 }
2599 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2600
2601 /*
2602  *  Extend 15-bit time stamp from rx descriptor to
2603  *  a full 64-bit TSF using the current h/w TSF.
2604 */
2605 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2606 {
2607         u64 tsf;
2608
2609         tsf = ath9k_hw_gettsf64(ah);
2610         if ((tsf & 0x7fff) < rstamp)
2611                 tsf -= 0x8000;
2612         return (tsf & ~0x7fff) | rstamp;
2613 }
2614 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2615
2616 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2617 {
2618         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2619         u32 macmode;
2620
2621         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2622                 macmode = AR_2040_JOINED_RX_CLEAR;
2623         else
2624                 macmode = 0;
2625
2626         REG_WRITE(ah, AR_2040_MODE, macmode);
2627 }
2628
2629 /* HW Generic timers configuration */
2630
2631 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2632 {
2633         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2634         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2635         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2636         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2637         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2638         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2639         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2640         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2641         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2642         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2643                                 AR_NDP2_TIMER_MODE, 0x0002},
2644         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2645                                 AR_NDP2_TIMER_MODE, 0x0004},
2646         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2647                                 AR_NDP2_TIMER_MODE, 0x0008},
2648         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2649                                 AR_NDP2_TIMER_MODE, 0x0010},
2650         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2651                                 AR_NDP2_TIMER_MODE, 0x0020},
2652         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2653                                 AR_NDP2_TIMER_MODE, 0x0040},
2654         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2655                                 AR_NDP2_TIMER_MODE, 0x0080}
2656 };
2657
2658 /* HW generic timer primitives */
2659
2660 /* compute and clear index of rightmost 1 */
2661 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2662 {
2663         u32 b;
2664
2665         b = *mask;
2666         b &= (0-b);
2667         *mask &= ~b;
2668         b *= debruijn32;
2669         b >>= 27;
2670
2671         return timer_table->gen_timer_index[b];
2672 }
2673
2674 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2675 {
2676         return REG_READ(ah, AR_TSF_L32);
2677 }
2678 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2679
2680 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2681                                           void (*trigger)(void *),
2682                                           void (*overflow)(void *),
2683                                           void *arg,
2684                                           u8 timer_index)
2685 {
2686         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2687         struct ath_gen_timer *timer;
2688
2689         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2690
2691         if (timer == NULL) {
2692                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2693                           "Failed to allocate memory"
2694                           "for hw timer[%d]\n", timer_index);
2695                 return NULL;
2696         }
2697
2698         /* allocate a hardware generic timer slot */
2699         timer_table->timers[timer_index] = timer;
2700         timer->index = timer_index;
2701         timer->trigger = trigger;
2702         timer->overflow = overflow;
2703         timer->arg = arg;
2704
2705         return timer;
2706 }
2707 EXPORT_SYMBOL(ath_gen_timer_alloc);
2708
2709 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2710                               struct ath_gen_timer *timer,
2711                               u32 timer_next,
2712                               u32 timer_period)
2713 {
2714         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2715         u32 tsf;
2716
2717         BUG_ON(!timer_period);
2718
2719         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2720
2721         tsf = ath9k_hw_gettsf32(ah);
2722
2723         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2724                   "curent tsf %x period %x"
2725                   "timer_next %x\n", tsf, timer_period, timer_next);
2726
2727         /*
2728          * Pull timer_next forward if the current TSF already passed it
2729          * because of software latency
2730          */
2731         if (timer_next < tsf)
2732                 timer_next = tsf + timer_period;
2733
2734         /*
2735          * Program generic timer registers
2736          */
2737         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2738                  timer_next);
2739         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2740                   timer_period);
2741         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2742                     gen_tmr_configuration[timer->index].mode_mask);
2743
2744         /* Enable both trigger and thresh interrupt masks */
2745         REG_SET_BIT(ah, AR_IMR_S5,
2746                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2747                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2748 }
2749 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2750
2751 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2752 {
2753         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2754
2755         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2756                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2757                 return;
2758         }
2759
2760         /* Clear generic timer enable bits. */
2761         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2762                         gen_tmr_configuration[timer->index].mode_mask);
2763
2764         /* Disable both trigger and thresh interrupt masks */
2765         REG_CLR_BIT(ah, AR_IMR_S5,
2766                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2767                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2768
2769         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2770 }
2771 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2772
2773 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2774 {
2775         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2776
2777         /* free the hardware generic timer slot */
2778         timer_table->timers[timer->index] = NULL;
2779         kfree(timer);
2780 }
2781 EXPORT_SYMBOL(ath_gen_timer_free);
2782
2783 /*
2784  * Generic Timer Interrupts handling
2785  */
2786 void ath_gen_timer_isr(struct ath_hw *ah)
2787 {
2788         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2789         struct ath_gen_timer *timer;
2790         struct ath_common *common = ath9k_hw_common(ah);
2791         u32 trigger_mask, thresh_mask, index;
2792
2793         /* get hardware generic timer interrupt status */
2794         trigger_mask = ah->intr_gen_timer_trigger;
2795         thresh_mask = ah->intr_gen_timer_thresh;
2796         trigger_mask &= timer_table->timer_mask.val;
2797         thresh_mask &= timer_table->timer_mask.val;
2798
2799         trigger_mask &= ~thresh_mask;
2800
2801         while (thresh_mask) {
2802                 index = rightmost_index(timer_table, &thresh_mask);
2803                 timer = timer_table->timers[index];
2804                 BUG_ON(!timer);
2805                 ath_print(common, ATH_DBG_HWTIMER,
2806                           "TSF overflow for Gen timer %d\n", index);
2807                 timer->overflow(timer->arg);
2808         }
2809
2810         while (trigger_mask) {
2811                 index = rightmost_index(timer_table, &trigger_mask);
2812                 timer = timer_table->timers[index];
2813                 BUG_ON(!timer);
2814                 ath_print(common, ATH_DBG_HWTIMER,
2815                           "Gen timer[%d] trigger\n", index);
2816                 timer->trigger(timer->arg);
2817         }
2818 }
2819 EXPORT_SYMBOL(ath_gen_timer_isr);
2820
2821 /********/
2822 /* HTC  */
2823 /********/
2824
2825 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2826 {
2827         ah->htc_reset_init = true;
2828 }
2829 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2830
2831 static struct {
2832         u32 version;
2833         const char * name;
2834 } ath_mac_bb_names[] = {
2835         /* Devices with external radios */
2836         { AR_SREV_VERSION_5416_PCI,     "5416" },
2837         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2838         { AR_SREV_VERSION_9100,         "9100" },
2839         { AR_SREV_VERSION_9160,         "9160" },
2840         /* Single-chip solutions */
2841         { AR_SREV_VERSION_9280,         "9280" },
2842         { AR_SREV_VERSION_9285,         "9285" },
2843         { AR_SREV_VERSION_9287,         "9287" },
2844         { AR_SREV_VERSION_9271,         "9271" },
2845         { AR_SREV_VERSION_9300,         "9300" },
2846 };
2847
2848 /* For devices with external radios */
2849 static struct {
2850         u16 version;
2851         const char * name;
2852 } ath_rf_names[] = {
2853         { 0,                            "5133" },
2854         { AR_RAD5133_SREV_MAJOR,        "5133" },
2855         { AR_RAD5122_SREV_MAJOR,        "5122" },
2856         { AR_RAD2133_SREV_MAJOR,        "2133" },
2857         { AR_RAD2122_SREV_MAJOR,        "2122" }
2858 };
2859
2860 /*
2861  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2862  */
2863 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2864 {
2865         int i;
2866
2867         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2868                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2869                         return ath_mac_bb_names[i].name;
2870                 }
2871         }
2872
2873         return "????";
2874 }
2875
2876 /*
2877  * Return the RF name. "????" is returned if the RF is unknown.
2878  * Used for devices with external radios.
2879  */
2880 static const char *ath9k_hw_rf_name(u16 rf_version)
2881 {
2882         int i;
2883
2884         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2885                 if (ath_rf_names[i].version == rf_version) {
2886                         return ath_rf_names[i].name;
2887                 }
2888         }
2889
2890         return "????";
2891 }
2892
2893 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2894 {
2895         int used;
2896
2897         /* chipsets >= AR9280 are single-chip */
2898         if (AR_SREV_9280_10_OR_LATER(ah)) {
2899                 used = snprintf(hw_name, len,
2900                                "Atheros AR%s Rev:%x",
2901                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2902                                ah->hw_version.macRev);
2903         }
2904         else {
2905                 used = snprintf(hw_name, len,
2906                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2907                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2908                                ah->hw_version.macRev,
2909                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2910                                                 AR_RADIO_SREV_MAJOR)),
2911                                ah->hw_version.phyRev);
2912         }
2913
2914         hw_name[used] = '\0';
2915 }
2916 EXPORT_SYMBOL(ath9k_hw_name);