drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  27
  28 MODULE_AUTHOR("Atheros Communications");
  29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  31 MODULE_LICENSE("Dual BSD/GPL");
  32
  33 static int __init ath9k_init(void)
  34 {
  35         return 0;
  36 }
  37 module_init(ath9k_init);
  38
  39 static void __exit ath9k_exit(void)
  40 {
  41         return;
  42 }
  43 module_exit(ath9k_exit);
  44
  45 /* Private hardware callbacks */
  46
  47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  48 {
  49         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  50 }
  51
  52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  55 }
  56
  57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  58 {
  59         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  60
  61         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  62 }
  63
  64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  65                                         struct ath9k_channel *chan)
  66 {
  67         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  68 }
  69
  70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  71 {
  72         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  73                 return;
  74
  75         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  76 }
  77
  78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
  79 {
  80         /* You will not have this callback if using the old ANI */
  81         if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
  82                 return;
  83
  84         ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
  85 }
  86
  87 /********************/
  88 /* Helper Functions */
  89 /********************/
  90
  91 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  92 {
  93         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  94
  95         if (!ah->curchan) /* should really check for CCK instead */
  96                 return usecs *ATH9K_CLOCK_RATE_CCK;
  97         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  98                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  99
 100         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
 101                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
 102         else
 103                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 104 }
 105
 106 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 107 {
 108         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 109
 110         if (conf_is_ht40(conf))
 111                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 112         else
 113                 return ath9k_hw_mac_clks(ah, usecs);
 114 }
 115
 116 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 117 {
 118         int i;
 119
 120         BUG_ON(timeout < AH_TIME_QUANTUM);
 121
 122         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 123                 if ((REG_READ(ah, reg) & mask) == val)
 124                         return true;
 125
 126                 udelay(AH_TIME_QUANTUM);
 127         }
 128
 129         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 130                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 131                   timeout, reg, REG_READ(ah, reg), mask, val);
 132
 133         return false;
 134 }
 135 EXPORT_SYMBOL(ath9k_hw_wait);
 136
 137 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 138 {
 139         u32 retval;
 140         int i;
 141
 142         for (i = 0, retval = 0; i < n; i++) {
 143                 retval = (retval << 1) | (val & 1);
 144                 val >>= 1;
 145         }
 146         return retval;
 147 }
 148
 149 bool ath9k_get_channel_edges(struct ath_hw *ah,
 150                              u16 flags, u16 *low,
 151                              u16 *high)
 152 {
 153         struct ath9k_hw_capabilities *pCap = &ah->caps;
 154
 155         if (flags & CHANNEL_5GHZ) {
 156                 *low = pCap->low_5ghz_chan;
 157                 *high = pCap->high_5ghz_chan;
 158                 return true;
 159         }
 160         if ((flags & CHANNEL_2GHZ)) {
 161                 *low = pCap->low_2ghz_chan;
 162                 *high = pCap->high_2ghz_chan;
 163                 return true;
 164         }
 165         return false;
 166 }
 167
 168 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 169                            u8 phy, int kbps,
 170                            u32 frameLen, u16 rateix,
 171                            bool shortPreamble)
 172 {
 173         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 174
 175         if (kbps == 0)
 176                 return 0;
 177
 178         switch (phy) {
 179         case WLAN_RC_PHY_CCK:
 180                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 181                 if (shortPreamble)
 182                         phyTime >>= 1;
 183                 numBits = frameLen << 3;
 184                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 185                 break;
 186         case WLAN_RC_PHY_OFDM:
 187                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 188                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 189                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 190                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 191                         txTime = OFDM_SIFS_TIME_QUARTER
 192                                 + OFDM_PREAMBLE_TIME_QUARTER
 193                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 194                 } else if (ah->curchan &&
 195                            IS_CHAN_HALF_RATE(ah->curchan)) {
 196                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 197                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 198                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 199                         txTime = OFDM_SIFS_TIME_HALF +
 200                                 OFDM_PREAMBLE_TIME_HALF
 201                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 202                 } else {
 203                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 204                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 205                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 206                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 207                                 + (numSymbols * OFDM_SYMBOL_TIME);
 208                 }
 209                 break;
 210         default:
 211                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 212                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 213                 txTime = 0;
 214                 break;
 215         }
 216
 217         return txTime;
 218 }
 219 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 220
 221 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 222                                   struct ath9k_channel *chan,
 223                                   struct chan_centers *centers)
 224 {
 225         int8_t extoff;
 226
 227         if (!IS_CHAN_HT40(chan)) {
 228                 centers->ctl_center = centers->ext_center =
 229                         centers->synth_center = chan->channel;
 230                 return;
 231         }
 232
 233         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 234             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 235                 centers->synth_center =
 236                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = 1;
 238         } else {
 239                 centers->synth_center =
 240                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 241                 extoff = -1;
 242         }
 243
 244         centers->ctl_center =
 245                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 246         /* 25 MHz spacing is supported by hw but not on upper layers */
 247         centers->ext_center =
 248                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 249 }
 250
 251 /******************/
 252 /* Chip Revisions */
 253 /******************/
 254
 255 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 256 {
 257         u32 val;
 258
 259         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 260
 261         if (val == 0xFF) {
 262                 val = REG_READ(ah, AR_SREV);
 263                 ah->hw_version.macVersion =
 264                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 265                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 266                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 267         } else {
 268                 if (!AR_SREV_9100(ah))
 269                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 270
 271                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 272
 273                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 274                         ah->is_pciexpress = true;
 275         }
 276 }
 277
 278 /************************************/
 279 /* HW Attach, Detach, Init Routines */
 280 /************************************/
 281
 282 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 283 {
 284         if (AR_SREV_9100(ah))
 285                 return;
 286
 287         ENABLE_REGWRITE_BUFFER(ah);
 288
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 298
 299         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 300
 301         REGWRITE_BUFFER_FLUSH(ah);
 302         DISABLE_REGWRITE_BUFFER(ah);
 303 }
 304
 305 /* This should work for all families including legacy */
 306 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 307 {
 308         struct ath_common *common = ath9k_hw_common(ah);
 309         u32 regAddr[2] = { AR_STA_ID0 };
 310         u32 regHold[2];
 311         u32 patternData[4] = { 0x55555555,
 312                                0xaaaaaaaa,
 313                                0x66666666,
 314                                0x99999999 };
 315         int i, j, loop_max;
 316
 317         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 318                 loop_max = 2;
 319                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 320         } else
 321                 loop_max = 1;
 322
 323         for (i = 0; i < loop_max; i++) {
 324                 u32 addr = regAddr[i];
 325                 u32 wrData, rdData;
 326
 327                 regHold[i] = REG_READ(ah, addr);
 328                 for (j = 0; j < 0x100; j++) {
 329                         wrData = (j << 16) | j;
 330                         REG_WRITE(ah, addr, wrData);
 331                         rdData = REG_READ(ah, addr);
 332                         if (rdData != wrData) {
 333                                 ath_print(common, ATH_DBG_FATAL,
 334                                           "address test failed "
 335                                           "addr: 0x%08x - wr:0x%08x != "
 336                                           "rd:0x%08x\n",
 337                                           addr, wrData, rdData);
 338                                 return false;
 339                         }
 340                 }
 341                 for (j = 0; j < 4; j++) {
 342                         wrData = patternData[j];
 343                         REG_WRITE(ah, addr, wrData);
 344                         rdData = REG_READ(ah, addr);
 345                         if (wrData != rdData) {
 346                                 ath_print(common, ATH_DBG_FATAL,
 347                                           "address test failed "
 348                                           "addr: 0x%08x - wr:0x%08x != "
 349                                           "rd:0x%08x\n",
 350                                           addr, wrData, rdData);
 351                                 return false;
 352                         }
 353                 }
 354                 REG_WRITE(ah, regAddr[i], regHold[i]);
 355         }
 356         udelay(100);
 357
 358         return true;
 359 }
 360
 361 static void ath9k_hw_init_config(struct ath_hw *ah)
 362 {
 363         int i;
 364
 365         ah->config.dma_beacon_response_time = 2;
 366         ah->config.sw_beacon_response_time = 10;
 367         ah->config.additional_swba_backoff = 0;
 368         ah->config.ack_6mb = 0x0;
 369         ah->config.cwm_ignore_extcca = 0;
 370         ah->config.pcie_powersave_enable = 0;
 371         ah->config.pcie_clock_req = 0;
 372         ah->config.pcie_waen = 0;
 373         ah->config.analog_shiftreg = 1;
 374         ah->config.ofdm_trig_low = 200;
 375         ah->config.ofdm_trig_high = 500;
 376         ah->config.cck_trig_high = 200;
 377         ah->config.cck_trig_low = 100;
 378         ah->config.enable_ani = true;
 379
 380         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 381                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 382                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 383         }
 384
 385         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 386                 ah->config.ht_enable = 1;
 387         else
 388                 ah->config.ht_enable = 0;
 389
 390         ah->config.rx_intr_mitigation = true;
 391         ah->config.pcieSerDesWrite = true;
 392
 393         /*
 394          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 395          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 396          * This means we use it for all AR5416 devices, and the few
 397          * minor PCI AR9280 devices out there.
 398          *
 399          * Serialization is required because these devices do not handle
 400          * well the case of two concurrent reads/writes due to the latency
 401          * involved. During one read/write another read/write can be issued
 402          * on another CPU while the previous read/write may still be working
 403          * on our hardware, if we hit this case the hardware poops in a loop.
 404          * We prevent this by serializing reads and writes.
 405          *
 406          * This issue is not present on PCI-Express devices or pre-AR5416
 407          * devices (legacy, 802.11abg).
 408          */
 409         if (num_possible_cpus() > 1)
 410                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 411 }
 412
 413 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 414 {
 415         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 416
 417         regulatory->country_code = CTRY_DEFAULT;
 418         regulatory->power_limit = MAX_RATE_POWER;
 419         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 420
 421         ah->hw_version.magic = AR5416_MAGIC;
 422         ah->hw_version.subvendorid = 0;
 423
 424         ah->ah_flags = 0;
 425         if (!AR_SREV_9100(ah))
 426                 ah->ah_flags = AH_USE_EEPROM;
 427
 428         ah->atim_window = 0;
 429         ah->sta_id1_defaults =
 430                 AR_STA_ID1_CRPT_MIC_ENABLE |
 431                 AR_STA_ID1_MCAST_KSRCH;
 432         ah->beacon_interval = 100;
 433         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 434         ah->slottime = (u32) -1;
 435         ah->globaltxtimeout = (u32) -1;
 436         ah->power_mode = ATH9K_PM_UNDEFINED;
 437 }
 438
 439 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 440 {
 441         struct ath_common *common = ath9k_hw_common(ah);
 442         u32 sum;
 443         int i;
 444         u16 eeval;
 445         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 446
 447         sum = 0;
 448         for (i = 0; i < 3; i++) {
 449                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 450                 sum += eeval;
 451                 common->macaddr[2 * i] = eeval >> 8;
 452                 common->macaddr[2 * i + 1] = eeval & 0xff;
 453         }
 454         if (sum == 0 || sum == 0xffff * 3)
 455                 return -EADDRNOTAVAIL;
 456
 457         return 0;
 458 }
 459
 460 static int ath9k_hw_post_init(struct ath_hw *ah)
 461 {
 462         int ecode;
 463
 464         if (!AR_SREV_9271(ah)) {
 465                 if (!ath9k_hw_chip_test(ah))
 466                         return -ENODEV;
 467         }
 468
 469         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 470                 ecode = ar9002_hw_rf_claim(ah);
 471                 if (ecode != 0)
 472                         return ecode;
 473         }
 474
 475         ecode = ath9k_hw_eeprom_init(ah);
 476         if (ecode != 0)
 477                 return ecode;
 478
 479         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 480                   "Eeprom VER: %d, REV: %d\n",
 481                   ah->eep_ops->get_eeprom_ver(ah),
 482                   ah->eep_ops->get_eeprom_rev(ah));
 483
 484         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 485         if (ecode) {
 486                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 487                           "Failed allocating banks for "
 488                           "external radio\n");
 489                 return ecode;
 490         }
 491
 492         if (!AR_SREV_9100(ah)) {
 493                 ath9k_hw_ani_setup(ah);
 494                 ath9k_hw_ani_init(ah);
 495         }
 496
 497         return 0;
 498 }
 499
 500 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 501 {
 502         if (AR_SREV_9300_20_OR_LATER(ah))
 503                 ar9003_hw_attach_ops(ah);
 504         else
 505                 ar9002_hw_attach_ops(ah);
 506 }
 507
 508 /* Called for all hardware families */
 509 static int __ath9k_hw_init(struct ath_hw *ah)
 510 {
 511         struct ath_common *common = ath9k_hw_common(ah);
 512         int r = 0;
 513
 514         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 515                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 516
 517         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 518                 ath_print(common, ATH_DBG_FATAL,
 519                           "Couldn't reset chip\n");
 520                 return -EIO;
 521         }
 522
 523         ath9k_hw_init_defaults(ah);
 524         ath9k_hw_init_config(ah);
 525
 526         ath9k_hw_attach_ops(ah);
 527
 528         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 529                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 530                 return -EIO;
 531         }
 532
 533         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 534                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 535                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 536                         ah->config.serialize_regmode =
 537                                 SER_REG_MODE_ON;
 538                 } else {
 539                         ah->config.serialize_regmode =
 540                                 SER_REG_MODE_OFF;
 541                 }
 542         }
 543
 544         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 545                 ah->config.serialize_regmode);
 546
 547         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 548                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 549         else
 550                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 551
 552         if (!ath9k_hw_macversion_supported(ah)) {
 553                 ath_print(common, ATH_DBG_FATAL,
 554                           "Mac Chip Rev 0x%02x.%x is not supported by "
 555                           "this driver\n", ah->hw_version.macVersion,
 556                           ah->hw_version.macRev);
 557                 return -EOPNOTSUPP;
 558         }
 559
 560         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 561                 ah->is_pciexpress = false;
 562
 563         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 564         ath9k_hw_init_cal_settings(ah);
 565
 566         ah->ani_function = ATH9K_ANI_ALL;
 567         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 568                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 569         if (!AR_SREV_9300_20_OR_LATER(ah))
 570                 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 571
 572         ath9k_hw_init_mode_regs(ah);
 573
 574         /*
 575          * Read back AR_WA into a permanent copy and set bits 14 and 17.
 576          * We need to do this to avoid RMW of this register. We cannot
 577          * read the reg when chip is asleep.
 578          */
 579         ah->WARegVal = REG_READ(ah, AR_WA);
 580         ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
 581                          AR_WA_ASPM_TIMER_BASED_DISABLE);
 582
 583         if (ah->is_pciexpress)
 584                 ath9k_hw_configpcipowersave(ah, 0, 0);
 585         else
 586                 ath9k_hw_disablepcie(ah);
 587
 588         if (!AR_SREV_9300_20_OR_LATER(ah))
 589                 ar9002_hw_cck_chan14_spread(ah);
 590
 591         r = ath9k_hw_post_init(ah);
 592         if (r)
 593                 return r;
 594
 595         ath9k_hw_init_mode_gain_regs(ah);
 596         r = ath9k_hw_fill_cap_info(ah);
 597         if (r)
 598                 return r;
 599
 600         r = ath9k_hw_init_macaddr(ah);
 601         if (r) {
 602                 ath_print(common, ATH_DBG_FATAL,
 603                           "Failed to initialize MAC address\n");
 604                 return r;
 605         }
 606
 607         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 608                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 609         else
 610                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 611
 612         if (AR_SREV_9300_20_OR_LATER(ah))
 613                 ar9003_hw_set_nf_limits(ah);
 614
 615         ath9k_init_nfcal_hist_buffer(ah);
 616         ah->bb_watchdog_timeout_ms = 25;
 617
 618         common->state = ATH_HW_INITIALIZED;
 619
 620         return 0;
 621 }
 622
 623 int ath9k_hw_init(struct ath_hw *ah)
 624 {
 625         int ret;
 626         struct ath_common *common = ath9k_hw_common(ah);
 627
 628         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 629         switch (ah->hw_version.devid) {
 630         case AR5416_DEVID_PCI:
 631         case AR5416_DEVID_PCIE:
 632         case AR5416_AR9100_DEVID:
 633         case AR9160_DEVID_PCI:
 634         case AR9280_DEVID_PCI:
 635         case AR9280_DEVID_PCIE:
 636         case AR9285_DEVID_PCIE:
 637         case AR9287_DEVID_PCI:
 638         case AR9287_DEVID_PCIE:
 639         case AR2427_DEVID_PCIE:
 640         case AR9300_DEVID_PCIE:
 641                 break;
 642         default:
 643                 if (common->bus_ops->ath_bus_type == ATH_USB)
 644                         break;
 645                 ath_print(common, ATH_DBG_FATAL,
 646                           "Hardware device ID 0x%04x not supported\n",
 647                           ah->hw_version.devid);
 648                 return -EOPNOTSUPP;
 649         }
 650
 651         ret = __ath9k_hw_init(ah);
 652         if (ret) {
 653                 ath_print(common, ATH_DBG_FATAL,
 654                           "Unable to initialize hardware; "
 655                           "initialization status: %d\n", ret);
 656                 return ret;
 657         }
 658
 659         return 0;
 660 }
 661 EXPORT_SYMBOL(ath9k_hw_init);
 662
 663 static void ath9k_hw_init_qos(struct ath_hw *ah)
 664 {
 665         ENABLE_REGWRITE_BUFFER(ah);
 666
 667         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 668         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 669
 670         REG_WRITE(ah, AR_QOS_NO_ACK,
 671                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 672                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 673                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 674
 675         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 676         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 677         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 678         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 679         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 680
 681         REGWRITE_BUFFER_FLUSH(ah);
 682         DISABLE_REGWRITE_BUFFER(ah);
 683 }
 684
 685 static void ath9k_hw_init_pll(struct ath_hw *ah,
 686                               struct ath9k_channel *chan)
 687 {
 688         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 689
 690         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 691
 692         /* Switch the core clock for ar9271 to 117Mhz */
 693         if (AR_SREV_9271(ah)) {
 694                 udelay(500);
 695                 REG_WRITE(ah, 0x50040, 0x304);
 696         }
 697
 698         udelay(RTC_PLL_SETTLE_DELAY);
 699
 700         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 701 }
 702
 703 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 704                                           enum nl80211_iftype opmode)
 705 {
 706         u32 imr_reg = AR_IMR_TXERR |
 707                 AR_IMR_TXURN |
 708                 AR_IMR_RXERR |
 709                 AR_IMR_RXORN |
 710                 AR_IMR_BCNMISC;
 711
 712         if (AR_SREV_9300_20_OR_LATER(ah)) {
 713                 imr_reg |= AR_IMR_RXOK_HP;
 714                 if (ah->config.rx_intr_mitigation)
 715                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 716                 else
 717                         imr_reg |= AR_IMR_RXOK_LP;
 718
 719         } else {
 720                 if (ah->config.rx_intr_mitigation)
 721                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 722                 else
 723                         imr_reg |= AR_IMR_RXOK;
 724         }
 725
 726         if (ah->config.tx_intr_mitigation)
 727                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 728         else
 729                 imr_reg |= AR_IMR_TXOK;
 730
 731         if (opmode == NL80211_IFTYPE_AP)
 732                 imr_reg |= AR_IMR_MIB;
 733
 734         ENABLE_REGWRITE_BUFFER(ah);
 735
 736         REG_WRITE(ah, AR_IMR, imr_reg);
 737         ah->imrs2_reg |= AR_IMR_S2_GTT;
 738         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 739
 740         if (!AR_SREV_9100(ah)) {
 741                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 742                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 743                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 744         }
 745
 746         REGWRITE_BUFFER_FLUSH(ah);
 747         DISABLE_REGWRITE_BUFFER(ah);
 748
 749         if (AR_SREV_9300_20_OR_LATER(ah)) {
 750                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 751                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 752                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 753                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 754         }
 755 }
 756
 757 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 758 {
 759         u32 val = ath9k_hw_mac_to_clks(ah, us);
 760         val = min(val, (u32) 0xFFFF);
 761         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 762 }
 763
 764 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 765 {
 766         u32 val = ath9k_hw_mac_to_clks(ah, us);
 767         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 768         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 769 }
 770
 771 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 772 {
 773         u32 val = ath9k_hw_mac_to_clks(ah, us);
 774         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 775         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 776 }
 777
 778 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 779 {
 780         if (tu > 0xFFFF) {
 781                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 782                           "bad global tx timeout %u\n", tu);
 783                 ah->globaltxtimeout = (u32) -1;
 784                 return false;
 785         } else {
 786                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 787                 ah->globaltxtimeout = tu;
 788                 return true;
 789         }
 790 }
 791
 792 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 793 {
 794         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 795         int acktimeout;
 796         int slottime;
 797         int sifstime;
 798
 799         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 800                   ah->misc_mode);
 801
 802         if (ah->misc_mode != 0)
 803                 REG_WRITE(ah, AR_PCU_MISC,
 804                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 805
 806         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 807                 sifstime = 16;
 808         else
 809                 sifstime = 10;
 810
 811         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 812         slottime = ah->slottime + 3 * ah->coverage_class;
 813         acktimeout = slottime + sifstime;
 814
 815         /*
 816          * Workaround for early ACK timeouts, add an offset to match the
 817          * initval's 64us ack timeout value.
 818          * This was initially only meant to work around an issue with delayed
 819          * BA frames in some implementations, but it has been found to fix ACK
 820          * timeout issues in other cases as well.
 821          */
 822         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 823                 acktimeout += 64 - sifstime - ah->slottime;
 824
 825         ath9k_hw_setslottime(ah, slottime);
 826         ath9k_hw_set_ack_timeout(ah, acktimeout);
 827         ath9k_hw_set_cts_timeout(ah, acktimeout);
 828         if (ah->globaltxtimeout != (u32) -1)
 829                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 830 }
 831 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 832
 833 void ath9k_hw_deinit(struct ath_hw *ah)
 834 {
 835         struct ath_common *common = ath9k_hw_common(ah);
 836
 837         if (common->state < ATH_HW_INITIALIZED)
 838                 goto free_hw;
 839
 840         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 841
 842 free_hw:
 843         ath9k_hw_rf_free_ext_banks(ah);
 844 }
 845 EXPORT_SYMBOL(ath9k_hw_deinit);
 846
 847 /*******/
 848 /* INI */
 849 /*******/
 850
 851 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 852 {
 853         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 854
 855         if (IS_CHAN_B(chan))
 856                 ctl |= CTL_11B;
 857         else if (IS_CHAN_G(chan))
 858                 ctl |= CTL_11G;
 859         else
 860                 ctl |= CTL_11A;
 861
 862         return ctl;
 863 }
 864
 865 /****************************************/
 866 /* Reset and Channel Switching Routines */
 867 /****************************************/
 868
 869 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 870 {
 871         struct ath_common *common = ath9k_hw_common(ah);
 872         u32 regval;
 873
 874         ENABLE_REGWRITE_BUFFER(ah);
 875
 876         /*
 877          * set AHB_MODE not to do cacheline prefetches
 878         */
 879         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 880                 regval = REG_READ(ah, AR_AHB_MODE);
 881                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 882         }
 883
 884         /*
 885          * let mac dma reads be in 128 byte chunks
 886          */
 887         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 888         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 889
 890         REGWRITE_BUFFER_FLUSH(ah);
 891         DISABLE_REGWRITE_BUFFER(ah);
 892
 893         /*
 894          * Restore TX Trigger Level to its pre-reset value.
 895          * The initial value depends on whether aggregation is enabled, and is
 896          * adjusted whenever underruns are detected.
 897          */
 898         if (!AR_SREV_9300_20_OR_LATER(ah))
 899                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 900
 901         ENABLE_REGWRITE_BUFFER(ah);
 902
 903         /*
 904          * let mac dma writes be in 128 byte chunks
 905          */
 906         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 907         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 908
 909         /*
 910          * Setup receive FIFO threshold to hold off TX activities
 911          */
 912         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 913
 914         if (AR_SREV_9300_20_OR_LATER(ah)) {
 915                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 916                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 917
 918                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 919                         ah->caps.rx_status_len);
 920         }
 921
 922         /*
 923          * reduce the number of usable entries in PCU TXBUF to avoid
 924          * wrap around issues.
 925          */
 926         if (AR_SREV_9285(ah)) {
 927                 /* For AR9285 the number of Fifos are reduced to half.
 928                  * So set the usable tx buf size also to half to
 929                  * avoid data/delimiter underruns
 930                  */
 931                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 932                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 933         } else if (!AR_SREV_9271(ah)) {
 934                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 935                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 936         }
 937
 938         REGWRITE_BUFFER_FLUSH(ah);
 939         DISABLE_REGWRITE_BUFFER(ah);
 940
 941         if (AR_SREV_9300_20_OR_LATER(ah))
 942                 ath9k_hw_reset_txstatus_ring(ah);
 943 }
 944
 945 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 946 {
 947         u32 val;
 948
 949         val = REG_READ(ah, AR_STA_ID1);
 950         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 951         switch (opmode) {
 952         case NL80211_IFTYPE_AP:
 953                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 954                           | AR_STA_ID1_KSRCH_MODE);
 955                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 956                 break;
 957         case NL80211_IFTYPE_ADHOC:
 958         case NL80211_IFTYPE_MESH_POINT:
 959                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 960                           | AR_STA_ID1_KSRCH_MODE);
 961                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 962                 break;
 963         case NL80211_IFTYPE_STATION:
 964         case NL80211_IFTYPE_MONITOR:
 965                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 966                 break;
 967         }
 968 }
 969
 970 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 971                                    u32 *coef_mantissa, u32 *coef_exponent)
 972 {
 973         u32 coef_exp, coef_man;
 974
 975         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 976                 if ((coef_scaled >> coef_exp) & 0x1)
 977                         break;
 978
 979         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 980
 981         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 982
 983         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 984         *coef_exponent = coef_exp - 16;
 985 }
 986
 987 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 988 {
 989         u32 rst_flags;
 990         u32 tmpReg;
 991
 992         if (AR_SREV_9100(ah)) {
 993                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
 994                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
 995                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
 996                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
 997                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
 998         }
 999
1000         ENABLE_REGWRITE_BUFFER(ah);
1001
1002         if (AR_SREV_9300_20_OR_LATER(ah)) {
1003                 REG_WRITE(ah, AR_WA, ah->WARegVal);
1004                 udelay(10);
1005         }
1006
1007         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1008                   AR_RTC_FORCE_WAKE_ON_INT);
1009
1010         if (AR_SREV_9100(ah)) {
1011                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1012                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1013         } else {
1014                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1015                 if (tmpReg &
1016                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1017                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1018                         u32 val;
1019                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1020
1021                         val = AR_RC_HOSTIF;
1022                         if (!AR_SREV_9300_20_OR_LATER(ah))
1023                                 val |= AR_RC_AHB;
1024                         REG_WRITE(ah, AR_RC, val);
1025
1026                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1027                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1028
1029                 rst_flags = AR_RTC_RC_MAC_WARM;
1030                 if (type == ATH9K_RESET_COLD)
1031                         rst_flags |= AR_RTC_RC_MAC_COLD;
1032         }
1033
1034         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1035
1036         REGWRITE_BUFFER_FLUSH(ah);
1037         DISABLE_REGWRITE_BUFFER(ah);
1038
1039         udelay(50);
1040
1041         REG_WRITE(ah, AR_RTC_RC, 0);
1042         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1043                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1044                           "RTC stuck in MAC reset\n");
1045                 return false;
1046         }
1047
1048         if (!AR_SREV_9100(ah))
1049                 REG_WRITE(ah, AR_RC, 0);
1050
1051         if (AR_SREV_9100(ah))
1052                 udelay(50);
1053
1054         return true;
1055 }
1056
1057 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1058 {
1059         ENABLE_REGWRITE_BUFFER(ah);
1060
1061         if (AR_SREV_9300_20_OR_LATER(ah)) {
1062                 REG_WRITE(ah, AR_WA, ah->WARegVal);
1063                 udelay(10);
1064         }
1065
1066         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1067                   AR_RTC_FORCE_WAKE_ON_INT);
1068
1069         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1070                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1071
1072         REG_WRITE(ah, AR_RTC_RESET, 0);
1073         udelay(2);
1074
1075         REGWRITE_BUFFER_FLUSH(ah);
1076         DISABLE_REGWRITE_BUFFER(ah);
1077
1078         if (!AR_SREV_9300_20_OR_LATER(ah))
1079                 udelay(2);
1080
1081         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1082                 REG_WRITE(ah, AR_RC, 0);
1083
1084         REG_WRITE(ah, AR_RTC_RESET, 1);
1085
1086         if (!ath9k_hw_wait(ah,
1087                            AR_RTC_STATUS,
1088                            AR_RTC_STATUS_M,
1089                            AR_RTC_STATUS_ON,
1090                            AH_WAIT_TIMEOUT)) {
1091                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1092                           "RTC not waking up\n");
1093                 return false;
1094         }
1095
1096         ath9k_hw_read_revisions(ah);
1097
1098         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1099 }
1100
1101 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1102 {
1103         if (AR_SREV_9300_20_OR_LATER(ah)) {
1104                 REG_WRITE(ah, AR_WA, ah->WARegVal);
1105                 udelay(10);
1106         }
1107
1108         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1109                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1110
1111         switch (type) {
1112         case ATH9K_RESET_POWER_ON:
1113                 return ath9k_hw_set_reset_power_on(ah);
1114         case ATH9K_RESET_WARM:
1115         case ATH9K_RESET_COLD:
1116                 return ath9k_hw_set_reset(ah, type);
1117         default:
1118                 return false;
1119         }
1120 }
1121
1122 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1123                                 struct ath9k_channel *chan)
1124 {
1125         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1126                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1127                         return false;
1128         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1129                 return false;
1130
1131         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1132                 return false;
1133
1134         ah->chip_fullsleep = false;
1135         ath9k_hw_init_pll(ah, chan);
1136         ath9k_hw_set_rfmode(ah, chan);
1137
1138         return true;
1139 }
1140
1141 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1142                                     struct ath9k_channel *chan)
1143 {
1144         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1145         struct ath_common *common = ath9k_hw_common(ah);
1146         struct ieee80211_channel *channel = chan->chan;
1147         u32 qnum;
1148         int r;
1149
1150         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1151                 if (ath9k_hw_numtxpending(ah, qnum)) {
1152                         ath_print(common, ATH_DBG_QUEUE,
1153                                   "Transmit frames pending on "
1154                                   "queue %d\n", qnum);
1155                         return false;
1156                 }
1157         }
1158
1159         if (!ath9k_hw_rfbus_req(ah)) {
1160                 ath_print(common, ATH_DBG_FATAL,
1161                           "Could not kill baseband RX\n");
1162                 return false;
1163         }
1164
1165         ath9k_hw_set_channel_regs(ah, chan);
1166
1167         r = ath9k_hw_rf_set_freq(ah, chan);
1168         if (r) {
1169                 ath_print(common, ATH_DBG_FATAL,
1170                           "Failed to set channel\n");
1171                 return false;
1172         }
1173
1174         ah->eep_ops->set_txpower(ah, chan,
1175                              ath9k_regd_get_ctl(regulatory, chan),
1176                              channel->max_antenna_gain * 2,
1177                              channel->max_power * 2,
1178                              min((u32) MAX_RATE_POWER,
1179                              (u32) regulatory->power_limit));
1180
1181         ath9k_hw_rfbus_done(ah);
1182
1183         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1184                 ath9k_hw_set_delta_slope(ah, chan);
1185
1186         ath9k_hw_spur_mitigate_freq(ah, chan);
1187
1188         if (!chan->oneTimeCalsDone)
1189                 chan->oneTimeCalsDone = true;
1190
1191         return true;
1192 }
1193
1194 bool ath9k_hw_check_alive(struct ath_hw *ah)
1195 {
1196         int count = 50;
1197         u32 reg;
1198
1199         if (AR_SREV_9285_10_OR_LATER(ah))
1200                 return true;
1201
1202         do {
1203                 reg = REG_READ(ah, AR_OBS_BUS_1);
1204
1205                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1206                         continue;
1207
1208                 switch (reg & 0x7E000B00) {
1209                 case 0x1E000000:
1210                 case 0x52000B00:
1211                 case 0x18000B00:
1212                         continue;
1213                 default:
1214                         return true;
1215                 }
1216         } while (count-- > 0);
1217
1218         return false;
1219 }
1220 EXPORT_SYMBOL(ath9k_hw_check_alive);
1221
1222 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1223                     bool bChannelChange)
1224 {
1225         struct ath_common *common = ath9k_hw_common(ah);
1226         u32 saveLedState;
1227         struct ath9k_channel *curchan = ah->curchan;
1228         u32 saveDefAntenna;
1229         u32 macStaId1;
1230         u64 tsf = 0;
1231         int i, r;
1232
1233         ah->txchainmask = common->tx_chainmask;
1234         ah->rxchainmask = common->rx_chainmask;
1235
1236         if (!ah->chip_fullsleep) {
1237                 ath9k_hw_abortpcurecv(ah);
1238                 if (!ath9k_hw_stopdmarecv(ah))
1239                         ath_print(common, ATH_DBG_XMIT,
1240                                 "Failed to stop receive dma\n");
1241         }
1242
1243         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1244                 return -EIO;
1245
1246         if (curchan && !ah->chip_fullsleep)
1247                 ath9k_hw_getnf(ah, curchan);
1248
1249         if (bChannelChange &&
1250             (ah->chip_fullsleep != true) &&
1251             (ah->curchan != NULL) &&
1252             (chan->channel != ah->curchan->channel) &&
1253             ((chan->channelFlags & CHANNEL_ALL) ==
1254              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1255             !AR_SREV_9280(ah)) {
1256
1257                 if (ath9k_hw_channel_change(ah, chan)) {
1258                         ath9k_hw_loadnf(ah, ah->curchan);
1259                         ath9k_hw_start_nfcal(ah);
1260                         return 0;
1261                 }
1262         }
1263
1264         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1265         if (saveDefAntenna == 0)
1266                 saveDefAntenna = 1;
1267
1268         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1269
1270         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1271         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1272                 tsf = ath9k_hw_gettsf64(ah);
1273
1274         saveLedState = REG_READ(ah, AR_CFG_LED) &
1275                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1276                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1277
1278         ath9k_hw_mark_phy_inactive(ah);
1279
1280         /* Only required on the first reset */
1281         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1282                 REG_WRITE(ah,
1283                           AR9271_RESET_POWER_DOWN_CONTROL,
1284                           AR9271_RADIO_RF_RST);
1285                 udelay(50);
1286         }
1287
1288         if (!ath9k_hw_chip_reset(ah, chan)) {
1289                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1290                 return -EINVAL;
1291         }
1292
1293         /* Only required on the first reset */
1294         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1295                 ah->htc_reset_init = false;
1296                 REG_WRITE(ah,
1297                           AR9271_RESET_POWER_DOWN_CONTROL,
1298                           AR9271_GATE_MAC_CTL);
1299                 udelay(50);
1300         }
1301
1302         /* Restore TSF */
1303         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1304                 ath9k_hw_settsf64(ah, tsf);
1305
1306         if (AR_SREV_9280_10_OR_LATER(ah))
1307                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1308
1309         if (!AR_SREV_9300_20_OR_LATER(ah))
1310                 ar9002_hw_enable_async_fifo(ah);
1311
1312         r = ath9k_hw_process_ini(ah, chan);
1313         if (r)
1314                 return r;
1315
1316         /* Setup MFP options for CCMP */
1317         if (AR_SREV_9280_20_OR_LATER(ah)) {
1318                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1319                  * frames when constructing CCMP AAD. */
1320                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1321                               0xc7ff);
1322                 ah->sw_mgmt_crypto = false;
1323         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1324                 /* Disable hardware crypto for management frames */
1325                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1326                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1327                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1328                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1329                 ah->sw_mgmt_crypto = true;
1330         } else
1331                 ah->sw_mgmt_crypto = true;
1332
1333         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1334                 ath9k_hw_set_delta_slope(ah, chan);
1335
1336         ath9k_hw_spur_mitigate_freq(ah, chan);
1337         ah->eep_ops->set_board_values(ah, chan);
1338
1339         ath9k_hw_set_operating_mode(ah, ah->opmode);
1340
1341         ENABLE_REGWRITE_BUFFER(ah);
1342
1343         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1344         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1345                   | macStaId1
1346                   | AR_STA_ID1_RTS_USE_DEF
1347                   | (ah->config.
1348                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1349                   | ah->sta_id1_defaults);
1350         ath_hw_setbssidmask(common);
1351         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1352         ath9k_hw_write_associd(ah);
1353         REG_WRITE(ah, AR_ISR, ~0);
1354         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1355
1356         REGWRITE_BUFFER_FLUSH(ah);
1357         DISABLE_REGWRITE_BUFFER(ah);
1358
1359         r = ath9k_hw_rf_set_freq(ah, chan);
1360         if (r)
1361                 return r;
1362
1363         ENABLE_REGWRITE_BUFFER(ah);
1364
1365         for (i = 0; i < AR_NUM_DCU; i++)
1366                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1367
1368         REGWRITE_BUFFER_FLUSH(ah);
1369         DISABLE_REGWRITE_BUFFER(ah);
1370
1371         ah->intr_txqs = 0;
1372         for (i = 0; i < ah->caps.total_queues; i++)
1373                 ath9k_hw_resettxqueue(ah, i);
1374
1375         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1376         ath9k_hw_ani_cache_ini_regs(ah);
1377         ath9k_hw_init_qos(ah);
1378
1379         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1380                 ath9k_enable_rfkill(ah);
1381
1382         ath9k_hw_init_global_settings(ah);
1383
1384         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1385                 ar9002_hw_update_async_fifo(ah);
1386                 ar9002_hw_enable_wep_aggregation(ah);
1387         }
1388
1389         REG_WRITE(ah, AR_STA_ID1,
1390                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1391
1392         ath9k_hw_set_dma(ah);
1393
1394         REG_WRITE(ah, AR_OBS, 8);
1395
1396         if (ah->config.rx_intr_mitigation) {
1397                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1398                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1399         }
1400
1401         if (ah->config.tx_intr_mitigation) {
1402                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1403                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1404         }
1405
1406         ath9k_hw_init_bb(ah, chan);
1407
1408         if (!ath9k_hw_init_cal(ah, chan))
1409                 return -EIO;
1410
1411         ENABLE_REGWRITE_BUFFER(ah);
1412
1413         ath9k_hw_restore_chainmask(ah);
1414         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1415
1416         REGWRITE_BUFFER_FLUSH(ah);
1417         DISABLE_REGWRITE_BUFFER(ah);
1418
1419         /*
1420          * For big endian systems turn on swapping for descriptors
1421          */
1422         if (AR_SREV_9100(ah)) {
1423                 u32 mask;
1424                 mask = REG_READ(ah, AR_CFG);
1425                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1426                         ath_print(common, ATH_DBG_RESET,
1427                                 "CFG Byte Swap Set 0x%x\n", mask);
1428                 } else {
1429                         mask =
1430                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1431                         REG_WRITE(ah, AR_CFG, mask);
1432                         ath_print(common, ATH_DBG_RESET,
1433                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1434                 }
1435         } else {
1436                 if (common->bus_ops->ath_bus_type == ATH_USB) {
1437                         /* Configure AR9271 target WLAN */
1438                         if (AR_SREV_9271(ah))
1439                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1440                         else
1441                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1442                 }
1443 #ifdef __BIG_ENDIAN
1444                 else
1445                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1446 #endif
1447         }
1448
1449         if (ah->btcoex_hw.enabled)
1450                 ath9k_hw_btcoex_enable(ah);
1451
1452         if (AR_SREV_9300_20_OR_LATER(ah)) {
1453                 ath9k_hw_loadnf(ah, curchan);
1454                 ath9k_hw_start_nfcal(ah);
1455                 ar9003_hw_bb_watchdog_config(ah);
1456         }
1457
1458         return 0;
1459 }
1460 EXPORT_SYMBOL(ath9k_hw_reset);
1461
1462 /************************/
1463 /* Key Cache Management */
1464 /************************/
1465
1466 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1467 {
1468         u32 keyType;
1469
1470         if (entry >= ah->caps.keycache_size) {
1471                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1472                           "keychache entry %u out of range\n", entry);
1473                 return false;
1474         }
1475
1476         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1477
1478         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1479         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1480         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1481         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1482         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1483         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1484         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1485         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1486
1487         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1488                 u16 micentry = entry + 64;
1489
1490                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1491                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1492                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1493                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1494
1495         }
1496
1497         return true;
1498 }
1499 EXPORT_SYMBOL(ath9k_hw_keyreset);
1500
1501 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1502 {
1503         u32 macHi, macLo;
1504         u32 unicast_flag = AR_KEYTABLE_VALID;
1505
1506         if (entry >= ah->caps.keycache_size) {
1507                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1508                           "keychache entry %u out of range\n", entry);
1509                 return false;
1510         }
1511
1512         if (mac != NULL) {
1513                 /*
1514                  * AR_KEYTABLE_VALID indicates that the address is a unicast
1515                  * address, which must match the transmitter address for
1516                  * decrypting frames.
1517                  * Not setting this bit allows the hardware to use the key
1518                  * for multicast frame decryption.
1519                  */
1520                 if (mac[0] & 0x01)
1521                         unicast_flag = 0;
1522
1523                 macHi = (mac[5] << 8) | mac[4];
1524                 macLo = (mac[3] << 24) |
1525                         (mac[2] << 16) |
1526                         (mac[1] << 8) |
1527                         mac[0];
1528                 macLo >>= 1;
1529                 macLo |= (macHi & 1) << 31;
1530                 macHi >>= 1;
1531         } else {
1532                 macLo = macHi = 0;
1533         }
1534         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1535         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
1536
1537         return true;
1538 }
1539 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1540
1541 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1542                                  const struct ath9k_keyval *k,
1543                                  const u8 *mac)
1544 {
1545         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1546         struct ath_common *common = ath9k_hw_common(ah);
1547         u32 key0, key1, key2, key3, key4;
1548         u32 keyType;
1549
1550         if (entry >= pCap->keycache_size) {
1551                 ath_print(common, ATH_DBG_FATAL,
1552                           "keycache entry %u out of range\n", entry);
1553                 return false;
1554         }
1555
1556         switch (k->kv_type) {
1557         case ATH9K_CIPHER_AES_OCB:
1558                 keyType = AR_KEYTABLE_TYPE_AES;
1559                 break;
1560         case ATH9K_CIPHER_AES_CCM:
1561                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1562                         ath_print(common, ATH_DBG_ANY,
1563                                   "AES-CCM not supported by mac rev 0x%x\n",
1564                                   ah->hw_version.macRev);
1565                         return false;
1566                 }
1567                 keyType = AR_KEYTABLE_TYPE_CCM;
1568                 break;
1569         case ATH9K_CIPHER_TKIP:
1570                 keyType = AR_KEYTABLE_TYPE_TKIP;
1571                 if (ATH9K_IS_MIC_ENABLED(ah)
1572                     && entry + 64 >= pCap->keycache_size) {
1573                         ath_print(common, ATH_DBG_ANY,
1574                                   "entry %u inappropriate for TKIP\n", entry);
1575                         return false;
1576                 }
1577                 break;
1578         case ATH9K_CIPHER_WEP:
1579                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1580                         ath_print(common, ATH_DBG_ANY,
1581                                   "WEP key length %u too small\n", k->kv_len);
1582                         return false;
1583                 }
1584                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1585                         keyType = AR_KEYTABLE_TYPE_40;
1586                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1587                         keyType = AR_KEYTABLE_TYPE_104;
1588                 else
1589                         keyType = AR_KEYTABLE_TYPE_128;
1590                 break;
1591         case ATH9K_CIPHER_CLR:
1592                 keyType = AR_KEYTABLE_TYPE_CLR;
1593                 break;
1594         default:
1595                 ath_print(common, ATH_DBG_FATAL,
1596                           "cipher %u not supported\n", k->kv_type);
1597                 return false;
1598         }
1599
1600         key0 = get_unaligned_le32(k->kv_val + 0);
1601         key1 = get_unaligned_le16(k->kv_val + 4);
1602         key2 = get_unaligned_le32(k->kv_val + 6);
1603         key3 = get_unaligned_le16(k->kv_val + 10);
1604         key4 = get_unaligned_le32(k->kv_val + 12);
1605         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1606                 key4 &= 0xff;
1607
1608         /*
1609          * Note: Key cache registers access special memory area that requires
1610          * two 32-bit writes to actually update the values in the internal
1611          * memory. Consequently, the exact order and pairs used here must be
1612          * maintained.
1613          */
1614
1615         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1616                 u16 micentry = entry + 64;
1617
1618                 /*
1619                  * Write inverted key[47:0] first to avoid Michael MIC errors
1620                  * on frames that could be sent or received at the same time.
1621                  * The correct key will be written in the end once everything
1622                  * else is ready.
1623                  */
1624                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1625                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1626
1627                 /* Write key[95:48] */
1628                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1629                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1630
1631                 /* Write key[127:96] and key type */
1632                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1633                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1634
1635                 /* Write MAC address for the entry */
1636                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1637
1638                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1639                         /*
1640                          * TKIP uses two key cache entries:
1641                          * Michael MIC TX/RX keys in the same key cache entry
1642                          * (idx = main index + 64):
1643                          * key0 [31:0] = RX key [31:0]
1644                          * key1 [15:0] = TX key [31:16]
1645                          * key1 [31:16] = reserved
1646                          * key2 [31:0] = RX key [63:32]
1647                          * key3 [15:0] = TX key [15:0]
1648                          * key3 [31:16] = reserved
1649                          * key4 [31:0] = TX key [63:32]
1650                          */
1651                         u32 mic0, mic1, mic2, mic3, mic4;
1652
1653                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1654                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1655                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1656                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1657                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1658
1659                         /* Write RX[31:0] and TX[31:16] */
1660                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1661                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1662
1663                         /* Write RX[63:32] and TX[15:0] */
1664                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1665                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1666
1667                         /* Write TX[63:32] and keyType(reserved) */
1668                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1669                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1670                                   AR_KEYTABLE_TYPE_CLR);
1671
1672                 } else {
1673                         /*
1674                          * TKIP uses four key cache entries (two for group
1675                          * keys):
1676                          * Michael MIC TX/RX keys are in different key cache
1677                          * entries (idx = main index + 64 for TX and
1678                          * main index + 32 + 96 for RX):
1679                          * key0 [31:0] = TX/RX MIC key [31:0]
1680                          * key1 [31:0] = reserved
1681                          * key2 [31:0] = TX/RX MIC key [63:32]
1682                          * key3 [31:0] = reserved
1683                          * key4 [31:0] = reserved
1684                          *
1685                          * Upper layer code will call this function separately
1686                          * for TX and RX keys when these registers offsets are
1687                          * used.
1688                          */
1689                         u32 mic0, mic2;
1690
1691                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1692                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1693
1694                         /* Write MIC key[31:0] */
1695                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1696                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1697
1698                         /* Write MIC key[63:32] */
1699                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1700                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1701
1702                         /* Write TX[63:32] and keyType(reserved) */
1703                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1704                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1705                                   AR_KEYTABLE_TYPE_CLR);
1706                 }
1707
1708                 /* MAC address registers are reserved for the MIC entry */
1709                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1710                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1711
1712                 /*
1713                  * Write the correct (un-inverted) key[47:0] last to enable
1714                  * TKIP now that all other registers are set with correct
1715                  * values.
1716                  */
1717                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1718                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1719         } else {
1720                 /* Write key[47:0] */
1721                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1722                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1723
1724                 /* Write key[95:48] */
1725                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1726                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1727
1728                 /* Write key[127:96] and key type */
1729                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1730                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1731
1732                 /* Write MAC address for the entry */
1733                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1734         }
1735
1736         return true;
1737 }
1738 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1739
1740 /******************************/
1741 /* Power Management (Chipset) */
1742 /******************************/
1743
1744 /*
1745  * Notify Power Mgt is disabled in self-generated frames.
1746  * If requested, force chip to sleep.
1747  */
1748 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1749 {
1750         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1751         if (setChip) {
1752                 /*
1753                  * Clear the RTC force wake bit to allow the
1754                  * mac to go to sleep.
1755                  */
1756                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1757                             AR_RTC_FORCE_WAKE_EN);
1758                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1759                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1760
1761                 /* Shutdown chip. Active low */
1762                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1763                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1764                                     AR_RTC_RESET_EN);
1765         }
1766
1767         /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1768         if (AR_SREV_9300_20_OR_LATER(ah))
1769                 REG_WRITE(ah, AR_WA,
1770                           ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1771 }
1772
1773 /*
1774  * Notify Power Management is enabled in self-generating
1775  * frames. If request, set power mode of chip to
1776  * auto/normal.  Duration in units of 128us (1/8 TU).
1777  */
1778 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1779 {
1780         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1781         if (setChip) {
1782                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1783
1784                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1785                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1786                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1787                                   AR_RTC_FORCE_WAKE_ON_INT);
1788                 } else {
1789                         /*
1790                          * Clear the RTC force wake bit to allow the
1791                          * mac to go to sleep.
1792                          */
1793                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1794                                     AR_RTC_FORCE_WAKE_EN);
1795                 }
1796         }
1797
1798         /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1799         if (AR_SREV_9300_20_OR_LATER(ah))
1800                 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1801 }
1802
1803 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1804 {
1805         u32 val;
1806         int i;
1807
1808         /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1809         if (AR_SREV_9300_20_OR_LATER(ah)) {
1810                 REG_WRITE(ah, AR_WA, ah->WARegVal);
1811                 udelay(10);
1812         }
1813
1814         if (setChip) {
1815                 if ((REG_READ(ah, AR_RTC_STATUS) &
1816                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1817                         if (ath9k_hw_set_reset_reg(ah,
1818                                            ATH9K_RESET_POWER_ON) != true) {
1819                                 return false;
1820                         }
1821                         if (!AR_SREV_9300_20_OR_LATER(ah))
1822                                 ath9k_hw_init_pll(ah, NULL);
1823                 }
1824                 if (AR_SREV_9100(ah))
1825                         REG_SET_BIT(ah, AR_RTC_RESET,
1826                                     AR_RTC_RESET_EN);
1827
1828                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1829                             AR_RTC_FORCE_WAKE_EN);
1830                 udelay(50);
1831
1832                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1833                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1834                         if (val == AR_RTC_STATUS_ON)
1835                                 break;
1836                         udelay(50);
1837                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1838                                     AR_RTC_FORCE_WAKE_EN);
1839                 }
1840                 if (i == 0) {
1841                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1842                                   "Failed to wakeup in %uus\n",
1843                                   POWER_UP_TIME / 20);
1844                         return false;
1845                 }
1846         }
1847
1848         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1849
1850         return true;
1851 }
1852
1853 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1854 {
1855         struct ath_common *common = ath9k_hw_common(ah);
1856         int status = true, setChip = true;
1857         static const char *modes[] = {
1858                 "AWAKE",
1859                 "FULL-SLEEP",
1860                 "NETWORK SLEEP",
1861                 "UNDEFINED"
1862         };
1863
1864         if (ah->power_mode == mode)
1865                 return status;
1866
1867         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1868                   modes[ah->power_mode], modes[mode]);
1869
1870         switch (mode) {
1871         case ATH9K_PM_AWAKE:
1872                 status = ath9k_hw_set_power_awake(ah, setChip);
1873                 break;
1874         case ATH9K_PM_FULL_SLEEP:
1875                 ath9k_set_power_sleep(ah, setChip);
1876                 ah->chip_fullsleep = true;
1877                 break;
1878         case ATH9K_PM_NETWORK_SLEEP:
1879                 ath9k_set_power_network_sleep(ah, setChip);
1880                 break;
1881         default:
1882                 ath_print(common, ATH_DBG_FATAL,
1883                           "Unknown power mode %u\n", mode);
1884                 return false;
1885         }
1886         ah->power_mode = mode;
1887
1888         return status;
1889 }
1890 EXPORT_SYMBOL(ath9k_hw_setpower);
1891
1892 /*******************/
1893 /* Beacon Handling */
1894 /*******************/
1895
1896 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1897 {
1898         int flags = 0;
1899
1900         ah->beacon_interval = beacon_period;
1901
1902         ENABLE_REGWRITE_BUFFER(ah);
1903
1904         switch (ah->opmode) {
1905         case NL80211_IFTYPE_STATION:
1906         case NL80211_IFTYPE_MONITOR:
1907                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1908                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1909                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1910                 flags |= AR_TBTT_TIMER_EN;
1911                 break;
1912         case NL80211_IFTYPE_ADHOC:
1913         case NL80211_IFTYPE_MESH_POINT:
1914                 REG_SET_BIT(ah, AR_TXCFG,
1915                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1916                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1917                           TU_TO_USEC(next_beacon +
1918                                      (ah->atim_window ? ah->
1919                                       atim_window : 1)));
1920                 flags |= AR_NDP_TIMER_EN;
1921         case NL80211_IFTYPE_AP:
1922                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1923                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1924                           TU_TO_USEC(next_beacon -
1925                                      ah->config.
1926                                      dma_beacon_response_time));
1927                 REG_WRITE(ah, AR_NEXT_SWBA,
1928                           TU_TO_USEC(next_beacon -
1929                                      ah->config.
1930                                      sw_beacon_response_time));
1931                 flags |=
1932                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1933                 break;
1934         default:
1935                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1936                           "%s: unsupported opmode: %d\n",
1937                           __func__, ah->opmode);
1938                 return;
1939                 break;
1940         }
1941
1942         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1943         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1944         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1945         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1946
1947         REGWRITE_BUFFER_FLUSH(ah);
1948         DISABLE_REGWRITE_BUFFER(ah);
1949
1950         beacon_period &= ~ATH9K_BEACON_ENA;
1951         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1952                 ath9k_hw_reset_tsf(ah);
1953         }
1954
1955         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1956 }
1957 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1958
1959 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1960                                     const struct ath9k_beacon_state *bs)
1961 {
1962         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1963         struct ath9k_hw_capabilities *pCap = &ah->caps;
1964         struct ath_common *common = ath9k_hw_common(ah);
1965
1966         ENABLE_REGWRITE_BUFFER(ah);
1967
1968         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1969
1970         REG_WRITE(ah, AR_BEACON_PERIOD,
1971                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1972         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1973                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1974
1975         REGWRITE_BUFFER_FLUSH(ah);
1976         DISABLE_REGWRITE_BUFFER(ah);
1977
1978         REG_RMW_FIELD(ah, AR_RSSI_THR,
1979                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1980
1981         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1982
1983         if (bs->bs_sleepduration > beaconintval)
1984                 beaconintval = bs->bs_sleepduration;
1985
1986         dtimperiod = bs->bs_dtimperiod;
1987         if (bs->bs_sleepduration > dtimperiod)
1988                 dtimperiod = bs->bs_sleepduration;
1989
1990         if (beaconintval == dtimperiod)
1991                 nextTbtt = bs->bs_nextdtim;
1992         else
1993                 nextTbtt = bs->bs_nexttbtt;
1994
1995         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1996         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1997         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1998         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1999
2000         ENABLE_REGWRITE_BUFFER(ah);
2001
2002         REG_WRITE(ah, AR_NEXT_DTIM,
2003                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2004         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2005
2006         REG_WRITE(ah, AR_SLEEP1,
2007                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2008                   | AR_SLEEP1_ASSUME_DTIM);
2009
2010         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2011                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2012         else
2013                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2014
2015         REG_WRITE(ah, AR_SLEEP2,
2016                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2017
2018         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2019         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2020
2021         REGWRITE_BUFFER_FLUSH(ah);
2022         DISABLE_REGWRITE_BUFFER(ah);
2023
2024         REG_SET_BIT(ah, AR_TIMER_MODE,
2025                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2026                     AR_DTIM_TIMER_EN);
2027
2028         /* TSF Out of Range Threshold */
2029         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2030 }
2031 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2032
2033 /*******************/
2034 /* HW Capabilities */
2035 /*******************/
2036
2037 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2038 {
2039         struct ath9k_hw_capabilities *pCap = &ah->caps;
2040         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2041         struct ath_common *common = ath9k_hw_common(ah);
2042         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2043
2044         u16 capField = 0, eeval;
2045
2046         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2047         regulatory->current_rd = eeval;
2048
2049         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2050         if (AR_SREV_9285_10_OR_LATER(ah))
2051                 eeval |= AR9285_RDEXT_DEFAULT;
2052         regulatory->current_rd_ext = eeval;
2053
2054         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2055
2056         if (ah->opmode != NL80211_IFTYPE_AP &&
2057             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2058                 if (regulatory->current_rd == 0x64 ||
2059                     regulatory->current_rd == 0x65)
2060                         regulatory->current_rd += 5;
2061                 else if (regulatory->current_rd == 0x41)
2062                         regulatory->current_rd = 0x43;
2063                 ath_print(common, ATH_DBG_REGULATORY,
2064                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2065         }
2066
2067         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2068         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2069                 ath_print(common, ATH_DBG_FATAL,
2070                           "no band has been marked as supported in EEPROM.\n");
2071                 return -EINVAL;
2072         }
2073
2074         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2075
2076         if (eeval & AR5416_OPFLAGS_11A) {
2077                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2078                 if (ah->config.ht_enable) {
2079                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2080                                 set_bit(ATH9K_MODE_11NA_HT20,
2081                                         pCap->wireless_modes);
2082                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2083                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2084                                         pCap->wireless_modes);
2085                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2086                                         pCap->wireless_modes);
2087                         }
2088                 }
2089         }
2090
2091         if (eeval & AR5416_OPFLAGS_11G) {
2092                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2093                 if (ah->config.ht_enable) {
2094                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2095                                 set_bit(ATH9K_MODE_11NG_HT20,
2096                                         pCap->wireless_modes);
2097                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2098                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2099                                         pCap->wireless_modes);
2100                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2101                                         pCap->wireless_modes);
2102                         }
2103                 }
2104         }
2105
2106         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2107         /*
2108          * For AR9271 we will temporarilly uses the rx chainmax as read from
2109          * the EEPROM.
2110          */
2111         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2112             !(eeval & AR5416_OPFLAGS_11A) &&
2113             !(AR_SREV_9271(ah)))
2114                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2115                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2116         else
2117                 /* Use rx_chainmask from EEPROM. */
2118                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2119
2120         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2121                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2122
2123         pCap->low_2ghz_chan = 2312;
2124         pCap->high_2ghz_chan = 2732;
2125
2126         pCap->low_5ghz_chan = 4920;
2127         pCap->high_5ghz_chan = 6100;
2128
2129         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2130         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2131         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2132
2133         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2134         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2135         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2136
2137         if (ah->config.ht_enable)
2138                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2139         else
2140                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2141
2142         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2143         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2144         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2145         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2146
2147         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2148                 pCap->total_queues =
2149                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2150         else
2151                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2152
2153         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2154                 pCap->keycache_size =
2155                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2156         else
2157                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2158
2159         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2160
2161         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2162                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2163         else
2164                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2165
2166         if (AR_SREV_9271(ah))
2167                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2168         else if (AR_SREV_9285_10_OR_LATER(ah))
2169                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2170         else if (AR_SREV_9280_10_OR_LATER(ah))
2171                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2172         else
2173                 pCap->num_gpio_pins = AR_NUM_GPIO;
2174
2175         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2176                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2177                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2178         } else {
2179                 pCap->rts_aggr_limit = (8 * 1024);
2180         }
2181
2182         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2183
2184 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2185         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2186         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2187                 ah->rfkill_gpio =
2188                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2189                 ah->rfkill_polarity =
2190                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2191
2192                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2193         }
2194 #endif
2195         if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2196                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2197         else
2198                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2199
2200         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2201                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2202         else
2203                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2204
2205         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2206                 pCap->reg_cap =
2207                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2208                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2209                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2210                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2211         } else {
2212                 pCap->reg_cap =
2213                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2214                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2215         }
2216
2217         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2218         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2219             AR_SREV_5416(ah))
2220                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2221
2222         pCap->num_antcfg_5ghz =
2223                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2224         pCap->num_antcfg_2ghz =
2225                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2226
2227         if (AR_SREV_9280_10_OR_LATER(ah) &&
2228             ath9k_hw_btcoex_supported(ah)) {
2229                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2230                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2231
2232                 if (AR_SREV_9285(ah)) {
2233                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2234                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2235                 } else {
2236                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2237                 }
2238         } else {
2239                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2240         }
2241
2242         if (AR_SREV_9300_20_OR_LATER(ah)) {
2243                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2244                                  ATH9K_HW_CAP_FASTCLOCK;
2245                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2246                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2247                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2248                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2249                 pCap->txs_len = sizeof(struct ar9003_txs);
2250                 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2251                         pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2252         } else {
2253                 pCap->tx_desc_len = sizeof(struct ath_desc);
2254                 if (AR_SREV_9280_20(ah) &&
2255                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2256                       AR5416_EEP_MINOR_VER_16) ||
2257                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2258                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2259         }
2260
2261         if (AR_SREV_9300_20_OR_LATER(ah))
2262                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2263
2264         if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
2265                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2266
2267         return 0;
2268 }
2269
2270 /****************************/
2271 /* GPIO / RFKILL / Antennae */
2272 /****************************/
2273
2274 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2275                                          u32 gpio, u32 type)
2276 {
2277         int addr;
2278         u32 gpio_shift, tmp;
2279
2280         if (gpio > 11)
2281                 addr = AR_GPIO_OUTPUT_MUX3;
2282         else if (gpio > 5)
2283                 addr = AR_GPIO_OUTPUT_MUX2;
2284         else
2285                 addr = AR_GPIO_OUTPUT_MUX1;
2286
2287         gpio_shift = (gpio % 6) * 5;
2288
2289         if (AR_SREV_9280_20_OR_LATER(ah)
2290             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2291                 REG_RMW(ah, addr, (type << gpio_shift),
2292                         (0x1f << gpio_shift));
2293         } else {
2294                 tmp = REG_READ(ah, addr);
2295                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2296                 tmp &= ~(0x1f << gpio_shift);
2297                 tmp |= (type << gpio_shift);
2298                 REG_WRITE(ah, addr, tmp);
2299         }
2300 }
2301
2302 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2303 {
2304         u32 gpio_shift;
2305
2306         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2307
2308         gpio_shift = gpio << 1;
2309
2310         REG_RMW(ah,
2311                 AR_GPIO_OE_OUT,
2312                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2313                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2314 }
2315 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2316
2317 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2318 {
2319 #define MS_REG_READ(x, y) \
2320         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2321
2322         if (gpio >= ah->caps.num_gpio_pins)
2323                 return 0xffffffff;
2324
2325         if (AR_SREV_9300_20_OR_LATER(ah))
2326                 return MS_REG_READ(AR9300, gpio) != 0;
2327         else if (AR_SREV_9271(ah))
2328                 return MS_REG_READ(AR9271, gpio) != 0;
2329         else if (AR_SREV_9287_10_OR_LATER(ah))
2330                 return MS_REG_READ(AR9287, gpio) != 0;
2331         else if (AR_SREV_9285_10_OR_LATER(ah))
2332                 return MS_REG_READ(AR9285, gpio) != 0;
2333         else if (AR_SREV_9280_10_OR_LATER(ah))
2334                 return MS_REG_READ(AR928X, gpio) != 0;
2335         else
2336                 return MS_REG_READ(AR, gpio) != 0;
2337 }
2338 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2339
2340 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2341                          u32 ah_signal_type)
2342 {
2343         u32 gpio_shift;
2344
2345         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2346
2347         gpio_shift = 2 * gpio;
2348
2349         REG_RMW(ah,
2350                 AR_GPIO_OE_OUT,
2351                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2352                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2353 }
2354 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2355
2356 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2357 {
2358         if (AR_SREV_9271(ah))
2359                 val = ~val;
2360
2361         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2362                 AR_GPIO_BIT(gpio));
2363 }
2364 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2365
2366 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2367 {
2368         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2369 }
2370 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2371
2372 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2373 {
2374         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2375 }
2376 EXPORT_SYMBOL(ath9k_hw_setantenna);
2377
2378 /*********************/
2379 /* General Operation */
2380 /*********************/
2381
2382 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2383 {
2384         u32 bits = REG_READ(ah, AR_RX_FILTER);
2385         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2386
2387         if (phybits & AR_PHY_ERR_RADAR)
2388                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2389         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2390                 bits |= ATH9K_RX_FILTER_PHYERR;
2391
2392         return bits;
2393 }
2394 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2395
2396 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2397 {
2398         u32 phybits;
2399
2400         ENABLE_REGWRITE_BUFFER(ah);
2401
2402         REG_WRITE(ah, AR_RX_FILTER, bits);
2403
2404         phybits = 0;
2405         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2406                 phybits |= AR_PHY_ERR_RADAR;
2407         if (bits & ATH9K_RX_FILTER_PHYERR)
2408                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2409         REG_WRITE(ah, AR_PHY_ERR, phybits);
2410
2411         if (phybits)
2412                 REG_WRITE(ah, AR_RXCFG,
2413                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2414         else
2415                 REG_WRITE(ah, AR_RXCFG,
2416                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2417
2418         REGWRITE_BUFFER_FLUSH(ah);
2419         DISABLE_REGWRITE_BUFFER(ah);
2420 }
2421 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2422
2423 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2424 {
2425         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2426                 return false;
2427
2428         ath9k_hw_init_pll(ah, NULL);
2429         return true;
2430 }
2431 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2432
2433 bool ath9k_hw_disable(struct ath_hw *ah)
2434 {
2435         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2436                 return false;
2437
2438         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2439                 return false;
2440
2441         ath9k_hw_init_pll(ah, NULL);
2442         return true;
2443 }
2444 EXPORT_SYMBOL(ath9k_hw_disable);
2445
2446 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2447 {
2448         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2449         struct ath9k_channel *chan = ah->curchan;
2450         struct ieee80211_channel *channel = chan->chan;
2451
2452         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2453
2454         ah->eep_ops->set_txpower(ah, chan,
2455                                  ath9k_regd_get_ctl(regulatory, chan),
2456                                  channel->max_antenna_gain * 2,
2457                                  channel->max_power * 2,
2458                                  min((u32) MAX_RATE_POWER,
2459                                  (u32) regulatory->power_limit));
2460 }
2461 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2462
2463 void ath9k_hw_setopmode(struct ath_hw *ah)
2464 {
2465         ath9k_hw_set_operating_mode(ah, ah->opmode);
2466 }
2467 EXPORT_SYMBOL(ath9k_hw_setopmode);
2468
2469 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2470 {
2471         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2472         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2473 }
2474 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2475
2476 void ath9k_hw_write_associd(struct ath_hw *ah)
2477 {
2478         struct ath_common *common = ath9k_hw_common(ah);
2479
2480         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2481         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2482                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2483 }
2484 EXPORT_SYMBOL(ath9k_hw_write_associd);
2485
2486 #define ATH9K_MAX_TSF_READ 10
2487
2488 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2489 {
2490         u32 tsf_lower, tsf_upper1, tsf_upper2;
2491         int i;
2492
2493         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2494         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2495                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2496                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2497                 if (tsf_upper2 == tsf_upper1)
2498                         break;
2499                 tsf_upper1 = tsf_upper2;
2500         }
2501
2502         WARN_ON( i == ATH9K_MAX_TSF_READ );
2503
2504         return (((u64)tsf_upper1 << 32) | tsf_lower);
2505 }
2506 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2507
2508 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2509 {
2510         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2511         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2512 }
2513 EXPORT_SYMBOL(ath9k_hw_settsf64);
2514
2515 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2516 {
2517         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2518                            AH_TSF_WRITE_TIMEOUT))
2519                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2520                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2521
2522         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2523 }
2524 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2525
2526 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2527 {
2528         if (setting)
2529                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2530         else
2531                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2532 }
2533 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2534
2535 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2536 {
2537         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2538         u32 macmode;
2539
2540         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2541                 macmode = AR_2040_JOINED_RX_CLEAR;
2542         else
2543                 macmode = 0;
2544
2545         REG_WRITE(ah, AR_2040_MODE, macmode);
2546 }
2547
2548 /* HW Generic timers configuration */
2549
2550 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2551 {
2552         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2553         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2554         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2555         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2556         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2557         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2558         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2559         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2560         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2561         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2562                                 AR_NDP2_TIMER_MODE, 0x0002},
2563         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2564                                 AR_NDP2_TIMER_MODE, 0x0004},
2565         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2566                                 AR_NDP2_TIMER_MODE, 0x0008},
2567         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2568                                 AR_NDP2_TIMER_MODE, 0x0010},
2569         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2570                                 AR_NDP2_TIMER_MODE, 0x0020},
2571         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2572                                 AR_NDP2_TIMER_MODE, 0x0040},
2573         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2574                                 AR_NDP2_TIMER_MODE, 0x0080}
2575 };
2576
2577 /* HW generic timer primitives */
2578
2579 /* compute and clear index of rightmost 1 */
2580 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2581 {
2582         u32 b;
2583
2584         b = *mask;
2585         b &= (0-b);
2586         *mask &= ~b;
2587         b *= debruijn32;
2588         b >>= 27;
2589
2590         return timer_table->gen_timer_index[b];
2591 }
2592
2593 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2594 {
2595         return REG_READ(ah, AR_TSF_L32);
2596 }
2597 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2598
2599 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2600                                           void (*trigger)(void *),
2601                                           void (*overflow)(void *),
2602                                           void *arg,
2603                                           u8 timer_index)
2604 {
2605         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2606         struct ath_gen_timer *timer;
2607
2608         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2609
2610         if (timer == NULL) {
2611                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2612                           "Failed to allocate memory"
2613                           "for hw timer[%d]\n", timer_index);
2614                 return NULL;
2615         }
2616
2617         /* allocate a hardware generic timer slot */
2618         timer_table->timers[timer_index] = timer;
2619         timer->index = timer_index;
2620         timer->trigger = trigger;
2621         timer->overflow = overflow;
2622         timer->arg = arg;
2623
2624         return timer;
2625 }
2626 EXPORT_SYMBOL(ath_gen_timer_alloc);
2627
2628 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2629                               struct ath_gen_timer *timer,
2630                               u32 timer_next,
2631                               u32 timer_period)
2632 {
2633         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2634         u32 tsf;
2635
2636         BUG_ON(!timer_period);
2637
2638         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2639
2640         tsf = ath9k_hw_gettsf32(ah);
2641
2642         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2643                   "curent tsf %x period %x"
2644                   "timer_next %x\n", tsf, timer_period, timer_next);
2645
2646         /*
2647          * Pull timer_next forward if the current TSF already passed it
2648          * because of software latency
2649          */
2650         if (timer_next < tsf)
2651                 timer_next = tsf + timer_period;
2652
2653         /*
2654          * Program generic timer registers
2655          */
2656         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2657                  timer_next);
2658         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2659                   timer_period);
2660         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2661                     gen_tmr_configuration[timer->index].mode_mask);
2662
2663         /* Enable both trigger and thresh interrupt masks */
2664         REG_SET_BIT(ah, AR_IMR_S5,
2665                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2666                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2667 }
2668 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2669
2670 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2671 {
2672         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2673
2674         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2675                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2676                 return;
2677         }
2678
2679         /* Clear generic timer enable bits. */
2680         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2681                         gen_tmr_configuration[timer->index].mode_mask);
2682
2683         /* Disable both trigger and thresh interrupt masks */
2684         REG_CLR_BIT(ah, AR_IMR_S5,
2685                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2686                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2687
2688         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2689 }
2690 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2691
2692 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2693 {
2694         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2695
2696         /* free the hardware generic timer slot */
2697         timer_table->timers[timer->index] = NULL;
2698         kfree(timer);
2699 }
2700 EXPORT_SYMBOL(ath_gen_timer_free);
2701
2702 /*
2703  * Generic Timer Interrupts handling
2704  */
2705 void ath_gen_timer_isr(struct ath_hw *ah)
2706 {
2707         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2708         struct ath_gen_timer *timer;
2709         struct ath_common *common = ath9k_hw_common(ah);
2710         u32 trigger_mask, thresh_mask, index;
2711
2712         /* get hardware generic timer interrupt status */
2713         trigger_mask = ah->intr_gen_timer_trigger;
2714         thresh_mask = ah->intr_gen_timer_thresh;
2715         trigger_mask &= timer_table->timer_mask.val;
2716         thresh_mask &= timer_table->timer_mask.val;
2717
2718         trigger_mask &= ~thresh_mask;
2719
2720         while (thresh_mask) {
2721                 index = rightmost_index(timer_table, &thresh_mask);
2722                 timer = timer_table->timers[index];
2723                 BUG_ON(!timer);
2724                 ath_print(common, ATH_DBG_HWTIMER,
2725                           "TSF overflow for Gen timer %d\n", index);
2726                 timer->overflow(timer->arg);
2727         }
2728
2729         while (trigger_mask) {
2730                 index = rightmost_index(timer_table, &trigger_mask);
2731                 timer = timer_table->timers[index];
2732                 BUG_ON(!timer);
2733                 ath_print(common, ATH_DBG_HWTIMER,
2734                           "Gen timer[%d] trigger\n", index);
2735                 timer->trigger(timer->arg);
2736         }
2737 }
2738 EXPORT_SYMBOL(ath_gen_timer_isr);
2739
2740 /********/
2741 /* HTC  */
2742 /********/
2743
2744 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2745 {
2746         ah->htc_reset_init = true;
2747 }
2748 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2749
2750 static struct {
2751         u32 version;
2752         const char * name;
2753 } ath_mac_bb_names[] = {
2754         /* Devices with external radios */
2755         { AR_SREV_VERSION_5416_PCI,     "5416" },
2756         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2757         { AR_SREV_VERSION_9100,         "9100" },
2758         { AR_SREV_VERSION_9160,         "9160" },
2759         /* Single-chip solutions */
2760         { AR_SREV_VERSION_9280,         "9280" },
2761         { AR_SREV_VERSION_9285,         "9285" },
2762         { AR_SREV_VERSION_9287,         "9287" },
2763         { AR_SREV_VERSION_9271,         "9271" },
2764         { AR_SREV_VERSION_9300,         "9300" },
2765 };
2766
2767 /* For devices with external radios */
2768 static struct {
2769         u16 version;
2770         const char * name;
2771 } ath_rf_names[] = {
2772         { 0,                            "5133" },
2773         { AR_RAD5133_SREV_MAJOR,        "5133" },
2774         { AR_RAD5122_SREV_MAJOR,        "5122" },
2775         { AR_RAD2133_SREV_MAJOR,        "2133" },
2776         { AR_RAD2122_SREV_MAJOR,        "2122" }
2777 };
2778
2779 /*
2780  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2781  */
2782 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2783 {
2784         int i;
2785
2786         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2787                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2788                         return ath_mac_bb_names[i].name;
2789                 }
2790         }
2791
2792         return "????";
2793 }
2794
2795 /*
2796  * Return the RF name. "????" is returned if the RF is unknown.
2797  * Used for devices with external radios.
2798  */
2799 static const char *ath9k_hw_rf_name(u16 rf_version)
2800 {
2801         int i;
2802
2803         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2804                 if (ath_rf_names[i].version == rf_version) {
2805                         return ath_rf_names[i].name;
2806                 }
2807         }
2808
2809         return "????";
2810 }
2811
2812 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2813 {
2814         int used;
2815
2816         /* chipsets >= AR9280 are single-chip */
2817         if (AR_SREV_9280_10_OR_LATER(ah)) {
2818                 used = snprintf(hw_name, len,
2819                                "Atheros AR%s Rev:%x",
2820                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2821                                ah->hw_version.macRev);
2822         }
2823         else {
2824                 used = snprintf(hw_name, len,
2825                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2826                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2827                                ah->hw_version.macRev,
2828                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2829                                                 AR_RADIO_SREV_MAJOR)),
2830                                ah->hw_version.phyRev);
2831         }
2832
2833         hw_name[used] = '\0';
2834 }
2835 EXPORT_SYMBOL(ath9k_hw_name);