2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 MODULE_AUTHOR("Atheros Communications");
20 MODULE_LICENSE("Dual BSD/GPL");
21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24 module_param_named(debug, ath9k_debug, uint, 0);
25 MODULE_PARM_DESC(debug, "Debugging mask");
27 int htc_modparam_nohwcrypt;
28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
46 static struct ieee80211_channel ath9k_2ghz_channels[] = {
47 CHAN2G(2412, 0), /* Channel 1 */
48 CHAN2G(2417, 1), /* Channel 2 */
49 CHAN2G(2422, 2), /* Channel 3 */
50 CHAN2G(2427, 3), /* Channel 4 */
51 CHAN2G(2432, 4), /* Channel 5 */
52 CHAN2G(2437, 5), /* Channel 6 */
53 CHAN2G(2442, 6), /* Channel 7 */
54 CHAN2G(2447, 7), /* Channel 8 */
55 CHAN2G(2452, 8), /* Channel 9 */
56 CHAN2G(2457, 9), /* Channel 10 */
57 CHAN2G(2462, 10), /* Channel 11 */
58 CHAN2G(2467, 11), /* Channel 12 */
59 CHAN2G(2472, 12), /* Channel 13 */
60 CHAN2G(2484, 13), /* Channel 14 */
63 static struct ieee80211_channel ath9k_5ghz_channels[] = {
64 /* _We_ call this UNII 1 */
65 CHAN5G(5180, 14), /* Channel 36 */
66 CHAN5G(5200, 15), /* Channel 40 */
67 CHAN5G(5220, 16), /* Channel 44 */
68 CHAN5G(5240, 17), /* Channel 48 */
69 /* _We_ call this UNII 2 */
70 CHAN5G(5260, 18), /* Channel 52 */
71 CHAN5G(5280, 19), /* Channel 56 */
72 CHAN5G(5300, 20), /* Channel 60 */
73 CHAN5G(5320, 21), /* Channel 64 */
74 /* _We_ call this "Middle band" */
75 CHAN5G(5500, 22), /* Channel 100 */
76 CHAN5G(5520, 23), /* Channel 104 */
77 CHAN5G(5540, 24), /* Channel 108 */
78 CHAN5G(5560, 25), /* Channel 112 */
79 CHAN5G(5580, 26), /* Channel 116 */
80 CHAN5G(5600, 27), /* Channel 120 */
81 CHAN5G(5620, 28), /* Channel 124 */
82 CHAN5G(5640, 29), /* Channel 128 */
83 CHAN5G(5660, 30), /* Channel 132 */
84 CHAN5G(5680, 31), /* Channel 136 */
85 CHAN5G(5700, 32), /* Channel 140 */
86 /* _We_ call this UNII 3 */
87 CHAN5G(5745, 33), /* Channel 149 */
88 CHAN5G(5765, 34), /* Channel 153 */
89 CHAN5G(5785, 35), /* Channel 157 */
90 CHAN5G(5805, 36), /* Channel 161 */
91 CHAN5G(5825, 37), /* Channel 165 */
94 /* Atheros hardware rate code addition for short premble */
95 #define SHPCHECK(__hw_rate, __flags) \
96 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
98 #define RATE(_bitrate, _hw_rate, _flags) { \
99 .bitrate = (_bitrate), \
101 .hw_value = (_hw_rate), \
102 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
105 static struct ieee80211_rate ath9k_legacy_rates[] = {
107 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
108 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
109 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
120 #ifdef CONFIG_MAC80211_LEDS
121 static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
122 { .throughput = 0 * 1024, .blink_time = 334 },
123 { .throughput = 1 * 1024, .blink_time = 260 },
124 { .throughput = 5 * 1024, .blink_time = 220 },
125 { .throughput = 10 * 1024, .blink_time = 190 },
126 { .throughput = 20 * 1024, .blink_time = 170 },
127 { .throughput = 50 * 1024, .blink_time = 150 },
128 { .throughput = 70 * 1024, .blink_time = 130 },
129 { .throughput = 100 * 1024, .blink_time = 110 },
130 { .throughput = 200 * 1024, .blink_time = 80 },
131 { .throughput = 300 * 1024, .blink_time = 50 },
135 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
139 if (atomic_read(&priv->htc->tgt_ready) > 0) {
140 atomic_dec(&priv->htc->tgt_ready);
144 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
145 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
147 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
151 atomic_dec(&priv->htc->tgt_ready);
156 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
158 ath9k_hw_deinit(priv->ah);
163 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
165 struct ieee80211_hw *hw = priv->hw;
167 wiphy_rfkill_stop_polling(hw->wiphy);
168 ath9k_deinit_leds(priv);
169 ieee80211_unregister_hw(hw);
170 ath9k_rx_cleanup(priv);
171 ath9k_tx_cleanup(priv);
172 ath9k_deinit_priv(priv);
175 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
179 enum htc_endpoint_id,
181 enum htc_endpoint_id *ep_id)
183 struct htc_service_connreq req;
185 memset(&req, 0, sizeof(struct htc_service_connreq));
187 req.service_id = service_id;
188 req.ep_callbacks.priv = priv;
189 req.ep_callbacks.rx = ath9k_htc_rxep;
190 req.ep_callbacks.tx = tx;
192 return htc_connect_service(priv->htc, &req, ep_id);
195 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
201 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
206 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
212 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
219 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
225 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
231 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
237 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
243 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
249 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
255 * Setup required credits before initializing HTC.
256 * This is a bit hacky, but, since queuing is done in
257 * the HIF layer, shouldn't matter much.
260 if (IS_AR7010_DEVICE(drv_info))
261 priv->htc->credits = 45;
263 priv->htc->credits = 33;
265 ret = htc_init(priv->htc);
269 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
275 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
279 static int ath9k_reg_notifier(struct wiphy *wiphy,
280 struct regulatory_request *request)
282 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
283 struct ath9k_htc_priv *priv = hw->priv;
285 return ath_reg_notifier_apply(wiphy, request,
286 ath9k_hw_regulatory(priv->ah));
289 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
291 struct ath_hw *ah = (struct ath_hw *) hw_priv;
292 struct ath_common *common = ath9k_hw_common(ah);
293 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
294 __be32 val, reg = cpu_to_be32(reg_offset);
297 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
298 (u8 *) ®, sizeof(reg),
299 (u8 *) &val, sizeof(val),
302 ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
307 return be32_to_cpu(val);
310 static void ath9k_multi_regread(void *hw_priv, u32 *addr,
313 struct ath_hw *ah = (struct ath_hw *) hw_priv;
314 struct ath_common *common = ath9k_hw_common(ah);
315 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
320 for (i = 0; i < count; i++) {
321 tmpaddr[i] = cpu_to_be32(addr[i]);
324 ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
325 (u8 *)tmpaddr , sizeof(u32) * count,
326 (u8 *)tmpval, sizeof(u32) * count,
330 "Multiple REGISTER READ FAILED (count: %d)\n", count);
333 for (i = 0; i < count; i++) {
334 val[i] = be32_to_cpu(tmpval[i]);
338 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
340 struct ath_hw *ah = (struct ath_hw *) hw_priv;
341 struct ath_common *common = ath9k_hw_common(ah);
342 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
343 const __be32 buf[2] = {
344 cpu_to_be32(reg_offset),
349 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
350 (u8 *) &buf, sizeof(buf),
351 (u8 *) &val, sizeof(val),
354 ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
359 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
361 struct ath_hw *ah = (struct ath_hw *) hw_priv;
362 struct ath_common *common = ath9k_hw_common(ah);
363 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
367 mutex_lock(&priv->wmi->multi_write_mutex);
369 /* Store the register/value */
370 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
371 cpu_to_be32(reg_offset);
372 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
375 priv->wmi->multi_write_idx++;
377 /* If the buffer is full, send it out. */
378 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
379 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
380 (u8 *) &priv->wmi->multi_write,
381 sizeof(struct register_write) * priv->wmi->multi_write_idx,
382 (u8 *) &rsp_status, sizeof(rsp_status),
386 "REGISTER WRITE FAILED, multi len: %d\n",
387 priv->wmi->multi_write_idx);
389 priv->wmi->multi_write_idx = 0;
392 mutex_unlock(&priv->wmi->multi_write_mutex);
395 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
397 struct ath_hw *ah = (struct ath_hw *) hw_priv;
398 struct ath_common *common = ath9k_hw_common(ah);
399 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
401 if (atomic_read(&priv->wmi->mwrite_cnt))
402 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
404 ath9k_regwrite_single(hw_priv, val, reg_offset);
407 static void ath9k_enable_regwrite_buffer(void *hw_priv)
409 struct ath_hw *ah = (struct ath_hw *) hw_priv;
410 struct ath_common *common = ath9k_hw_common(ah);
411 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
413 atomic_inc(&priv->wmi->mwrite_cnt);
416 static void ath9k_regwrite_flush(void *hw_priv)
418 struct ath_hw *ah = (struct ath_hw *) hw_priv;
419 struct ath_common *common = ath9k_hw_common(ah);
420 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
424 atomic_dec(&priv->wmi->mwrite_cnt);
426 mutex_lock(&priv->wmi->multi_write_mutex);
428 if (priv->wmi->multi_write_idx) {
429 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
430 (u8 *) &priv->wmi->multi_write,
431 sizeof(struct register_write) * priv->wmi->multi_write_idx,
432 (u8 *) &rsp_status, sizeof(rsp_status),
436 "REGISTER WRITE FAILED, multi len: %d\n",
437 priv->wmi->multi_write_idx);
439 priv->wmi->multi_write_idx = 0;
442 mutex_unlock(&priv->wmi->multi_write_mutex);
445 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
449 val = ath9k_regread(hw_priv, reg_offset);
452 ath9k_regwrite(hw_priv, val, reg_offset);
456 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
458 *csz = L1_CACHE_BYTES >> 2;
461 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
463 struct ath_hw *ah = (struct ath_hw *) common->ah;
465 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
467 if (!ath9k_hw_wait(ah,
468 AR_EEPROM_STATUS_DATA,
469 AR_EEPROM_STATUS_DATA_BUSY |
470 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
474 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
475 AR_EEPROM_STATUS_DATA_VAL);
480 static const struct ath_bus_ops ath9k_usb_bus_ops = {
481 .ath_bus_type = ATH_USB,
482 .read_cachesize = ath_usb_read_cachesize,
483 .eeprom_read = ath_usb_eeprom_read,
486 static void setup_ht_cap(struct ath9k_htc_priv *priv,
487 struct ieee80211_sta_ht_cap *ht_info)
489 struct ath_common *common = ath9k_hw_common(priv->ah);
490 u8 tx_streams, rx_streams;
493 ht_info->ht_supported = true;
494 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
495 IEEE80211_HT_CAP_SM_PS |
496 IEEE80211_HT_CAP_SGI_40 |
497 IEEE80211_HT_CAP_DSSSCCK40;
499 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
500 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
502 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
504 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
505 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
507 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
509 /* ath9k_htc supports only 1 or 2 stream devices */
510 tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2);
511 rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2);
513 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
514 tx_streams, rx_streams);
516 if (tx_streams != rx_streams) {
517 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
518 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
519 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
522 for (i = 0; i < rx_streams; i++)
523 ht_info->mcs.rx_mask[i] = 0xff;
525 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
528 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
530 struct ath_common *common = ath9k_hw_common(priv->ah);
533 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
534 priv->hwq_map[i] = -1;
536 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
537 if (priv->beaconq == -1) {
538 ath_err(common, "Unable to setup BEACON xmit queue\n");
542 priv->cabq = ath9k_htc_cabq_setup(priv);
543 if (priv->cabq == -1) {
544 ath_err(common, "Unable to setup CAB xmit queue\n");
548 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
549 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
553 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
554 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
557 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
558 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
561 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
562 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
572 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
574 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
575 priv->sbands[IEEE80211_BAND_2GHZ].channels =
577 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
578 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
579 ARRAY_SIZE(ath9k_2ghz_channels);
580 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
581 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
582 ARRAY_SIZE(ath9k_legacy_rates);
585 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
586 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
587 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
588 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
589 ARRAY_SIZE(ath9k_5ghz_channels);
590 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
591 ath9k_legacy_rates + 4;
592 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
593 ARRAY_SIZE(ath9k_legacy_rates) - 4;
597 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
599 struct ath_common *common = ath9k_hw_common(priv->ah);
601 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
603 priv->ah->opmode = NL80211_IFTYPE_STATION;
606 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
610 switch (ath9k_hw_get_btcoex_scheme(priv->ah)) {
611 case ATH_BTCOEX_CFG_NONE:
613 case ATH_BTCOEX_CFG_3WIRE:
614 priv->ah->btcoex_hw.btactive_gpio = 7;
615 priv->ah->btcoex_hw.btpriority_gpio = 6;
616 priv->ah->btcoex_hw.wlanactive_gpio = 8;
617 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
618 ath9k_hw_btcoex_init_3wire(priv->ah);
619 ath_htc_init_btcoex_work(priv);
620 qnum = priv->hwq_map[WME_AC_BE];
621 ath9k_hw_init_btcoex_hw(priv->ah, qnum);
629 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
630 u16 devid, char *product,
633 struct ath_hw *ah = NULL;
634 struct ath_common *common;
635 int i, ret = 0, csz = 0;
637 priv->op_flags |= OP_INVALID;
639 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
643 ah->hw_version.devid = devid;
644 ah->hw_version.usbdev = drv_info;
645 ah->ah_flags |= AH_USE_EEPROM;
646 ah->reg_ops.read = ath9k_regread;
647 ah->reg_ops.multi_read = ath9k_multi_regread;
648 ah->reg_ops.write = ath9k_regwrite;
649 ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
650 ah->reg_ops.write_flush = ath9k_regwrite_flush;
651 ah->reg_ops.rmw = ath9k_reg_rmw;
654 common = ath9k_hw_common(ah);
655 common->ops = &ah->reg_ops;
656 common->bus_ops = &ath9k_usb_bus_ops;
658 common->hw = priv->hw;
660 common->debug_mask = ath9k_debug;
662 spin_lock_init(&priv->beacon_lock);
663 spin_lock_init(&priv->tx.tx_lock);
664 mutex_init(&priv->mutex);
665 mutex_init(&priv->htc_pm_lock);
666 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
667 (unsigned long)priv);
668 tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
669 (unsigned long)priv);
670 INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
671 INIT_WORK(&priv->ps_work, ath9k_ps_work);
672 INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
673 setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
674 (unsigned long)priv);
677 * Cache line size is used to size and align various
678 * structures used to communicate with the hardware.
680 ath_read_cachesize(common, &csz);
681 common->cachelsz = csz << 2; /* convert to bytes */
683 ret = ath9k_hw_init(ah);
686 "Unable to initialize hardware; initialization status: %d\n",
691 ret = ath9k_init_queues(priv);
695 for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
696 priv->cur_beacon_conf.bslot[i] = NULL;
698 ath9k_cmn_init_crypto(ah);
699 ath9k_init_channels_rates(priv);
700 ath9k_init_misc(priv);
702 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
703 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
704 if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE)
705 ath9k_init_btcoex(priv);
720 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
721 struct ieee80211_hw *hw)
723 struct ath_common *common = ath9k_hw_common(priv->ah);
725 hw->flags = IEEE80211_HW_SIGNAL_DBM |
726 IEEE80211_HW_AMPDU_AGGREGATION |
727 IEEE80211_HW_SPECTRUM_MGMT |
728 IEEE80211_HW_HAS_RATE_CONTROL |
729 IEEE80211_HW_RX_INCLUDES_FCS |
730 IEEE80211_HW_SUPPORTS_PS |
731 IEEE80211_HW_PS_NULLFUNC_STACK |
732 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
733 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
735 hw->wiphy->interface_modes =
736 BIT(NL80211_IFTYPE_STATION) |
737 BIT(NL80211_IFTYPE_ADHOC) |
738 BIT(NL80211_IFTYPE_AP) |
739 BIT(NL80211_IFTYPE_P2P_GO) |
740 BIT(NL80211_IFTYPE_P2P_CLIENT);
742 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
745 hw->channel_change_time = 5000;
746 hw->max_listen_interval = 10;
748 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
749 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
751 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
752 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
753 sizeof(struct htc_frame_hdr) + 4;
755 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
756 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
757 &priv->sbands[IEEE80211_BAND_2GHZ];
758 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
759 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
760 &priv->sbands[IEEE80211_BAND_5GHZ];
762 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
763 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
765 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
766 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
768 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
771 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
774 static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
776 struct ieee80211_hw *hw = priv->hw;
777 struct wmi_fw_version cmd_rsp;
780 memset(&cmd_rsp, 0, sizeof(cmd_rsp));
782 WMI_CMD(WMI_GET_FW_VERSION);
786 priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
787 priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
789 snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
790 priv->fw_version_major,
791 priv->fw_version_minor);
793 dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
794 priv->fw_version_major,
795 priv->fw_version_minor);
798 * Check if the available FW matches the driver's
801 if (priv->fw_version_major != MAJOR_VERSION_REQ ||
802 priv->fw_version_minor != MINOR_VERSION_REQ) {
803 dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
804 MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
811 static int ath9k_init_device(struct ath9k_htc_priv *priv,
812 u16 devid, char *product, u32 drv_info)
814 struct ieee80211_hw *hw = priv->hw;
815 struct ath_common *common;
818 struct ath_regulatory *reg;
821 /* Bring up device */
822 error = ath9k_init_priv(priv, devid, product, drv_info);
827 common = ath9k_hw_common(ah);
828 ath9k_set_hw_capab(priv, hw);
830 error = ath9k_init_firmware_version(priv);
834 /* Initialize regulatory */
835 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
840 reg = &common->regulatory;
843 error = ath9k_tx_init(priv);
848 error = ath9k_rx_init(priv);
852 #ifdef CONFIG_MAC80211_LEDS
853 /* must be initialized before ieee80211_register_hw */
854 priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
855 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
856 ARRAY_SIZE(ath9k_htc_tpt_blink));
859 /* Register with mac80211 */
860 error = ieee80211_register_hw(hw);
864 /* Handle world regulatory */
865 if (!ath_is_world_regd(reg)) {
866 error = regulatory_hint(hw->wiphy, reg->alpha2);
871 error = ath9k_htc_init_debug(priv->ah);
873 ath_err(common, "Unable to create debugfs files\n");
877 ath_dbg(common, CONFIG,
878 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
889 ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
890 wiphy_info(hw->wiphy, "%s\n", hw_name);
892 ath9k_init_leds(priv);
893 ath9k_start_rfkill_poll(priv);
898 ieee80211_unregister_hw(hw);
900 ath9k_rx_cleanup(priv);
902 ath9k_tx_cleanup(priv);
908 ath9k_deinit_priv(priv);
913 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
914 u16 devid, char *product, u32 drv_info)
916 struct ieee80211_hw *hw;
917 struct ath9k_htc_priv *priv;
920 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
926 priv->htc = htc_handle;
928 htc_handle->drv_priv = priv;
929 SET_IEEE80211_DEV(hw, priv->dev);
931 ret = ath9k_htc_wait_for_target(priv);
935 priv->wmi = ath9k_init_wmi(priv);
941 ret = ath9k_init_htc_services(priv, devid, drv_info);
945 ret = ath9k_init_device(priv, devid, product, drv_info);
952 ath9k_deinit_wmi(priv);
954 ieee80211_free_hw(hw);
958 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
960 if (htc_handle->drv_priv) {
962 /* Check if the device has been yanked out. */
964 htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
966 ath9k_deinit_device(htc_handle->drv_priv);
967 ath9k_deinit_wmi(htc_handle->drv_priv);
968 ieee80211_free_hw(htc_handle->drv_priv->hw);
974 void ath9k_htc_suspend(struct htc_target *htc_handle)
976 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
979 int ath9k_htc_resume(struct htc_target *htc_handle)
981 struct ath9k_htc_priv *priv = htc_handle->drv_priv;
984 ret = ath9k_htc_wait_for_target(priv);
988 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
989 priv->ah->hw_version.usbdev);
994 static int __init ath9k_htc_init(void)
996 if (ath9k_hif_usb_init() < 0) {
998 "ath9k_htc: No USB devices found,"
999 " driver not installed.\n");
1005 module_init(ath9k_htc_init);
1007 static void __exit ath9k_htc_exit(void)
1009 ath9k_hif_usb_exit();
1010 printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
1012 module_exit(ath9k_htc_exit);