drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 static const int firstep_table[] =
  22 /* level:  0   1   2   3   4   5   6   7   8  */
  23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  24
  25 static const int cycpwrThr1_table[] =
  26 /* level:  0   1   2   3   4   5   6   7   8  */
  27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  28
  29 /*
  30  * register values to turn OFDM weak signal detection OFF
  31  */
  32 static const int m1ThreshLow_off = 127;
  33 static const int m2ThreshLow_off = 127;
  34 static const int m1Thresh_off = 127;
  35 static const int m2Thresh_off = 127;
  36 static const int m2CountThr_off =  31;
  37 static const int m2CountThrLow_off =  63;
  38 static const int m1ThreshLowExt_off = 127;
  39 static const int m2ThreshLowExt_off = 127;
  40 static const int m1ThreshExt_off = 127;
  41 static const int m2ThreshExt_off = 127;
  42
  43 /**
  44  * ar9003_hw_set_channel - set channel on single-chip device
  45  * @ah: atheros hardware structure
  46  * @chan:
  47  *
  48  * This is the function to change channel on single-chip devices, that is
  49  * all devices after ar9280.
  50  *
  51  * This function takes the channel value in MHz and sets
  52  * hardware channel value. Assumes writes have been enabled to analog bus.
  53  *
  54  * Actual Expression,
  55  *
  56  * For 2GHz channel,
  57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  58  * (freq_ref = 40MHz)
  59  *
  60  * For 5GHz channel,
  61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  62  * (freq_ref = 40MHz/(24>>amodeRefSel))
  63  *
  64  * For 5GHz channels which are 5MHz spaced,
  65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  66  * (freq_ref = 40MHz)
  67  */
  68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  69 {
  70         u16 bMode, fracMode = 0, aModeRefSel = 0;
  71         u32 freq, channelSel = 0, reg32 = 0;
  72         struct chan_centers centers;
  73         int loadSynthChannel;
  74
  75         ath9k_hw_get_channel_centers(ah, chan, &centers);
  76         freq = centers.synth_center;
  77
  78         if (freq < 4800) {     /* 2 GHz, fractional mode */
  79                 if (AR_SREV_9330(ah)) {
  80                         u32 chan_frac;
  81                         u32 div;
  82
  83                         if (ah->is_clk_25mhz)
  84                                 div = 75;
  85                         else
  86                                 div = 120;
  87
  88                         channelSel = (freq * 4) / div;
  89                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  90                         channelSel = (channelSel << 17) | chan_frac;
  91                 } else if (AR_SREV_9485(ah)) {
  92                         u32 chan_frac;
  93
  94                         /*
  95                          * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
  96                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  97                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  98                          */
  99                         channelSel = (freq * 4) / 120;
 100                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
 101                         channelSel = (channelSel << 17) | chan_frac;
 102                 } else if (AR_SREV_9340(ah)) {
 103                         if (ah->is_clk_25mhz) {
 104                                 u32 chan_frac;
 105
 106                                 channelSel = (freq * 2) / 75;
 107                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 108                                 channelSel = (channelSel << 17) | chan_frac;
 109                         } else
 110                                 channelSel = CHANSEL_2G(freq) >> 1;
 111                 } else
 112                         channelSel = CHANSEL_2G(freq);
 113                 /* Set to 2G mode */
 114                 bMode = 1;
 115         } else {
 116                 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
 117                         u32 chan_frac;
 118
 119                         channelSel = (freq * 2) / 75;
 120                         chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 121                         channelSel = (channelSel << 17) | chan_frac;
 122                 } else {
 123                         channelSel = CHANSEL_5G(freq);
 124                         /* Doubler is ON, so, divide channelSel by 2. */
 125                         channelSel >>= 1;
 126                 }
 127                 /* Set to 5G mode */
 128                 bMode = 0;
 129         }
 130
 131         /* Enable fractional mode for all channels */
 132         fracMode = 1;
 133         aModeRefSel = 0;
 134         loadSynthChannel = 0;
 135
 136         reg32 = (bMode << 29);
 137         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 138
 139         /* Enable Long shift Select for Synthesizer */
 140         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 141                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 142
 143         /* Program Synth. setting */
 144         reg32 = (channelSel << 2) | (fracMode << 30) |
 145                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 146         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 147
 148         /* Toggle Load Synth channel bit */
 149         loadSynthChannel = 1;
 150         reg32 = (channelSel << 2) | (fracMode << 30) |
 151                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 152         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 153
 154         ah->curchan = chan;
 155         ah->curchan_rad_index = -1;
 156
 157         return 0;
 158 }
 159
 160 /**
 161  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 162  * @ah: atheros hardware structure
 163  * @chan:
 164  *
 165  * For single-chip solutions. Converts to baseband spur frequency given the
 166  * input channel frequency and compute register settings below.
 167  *
 168  * Spur mitigation for MRC CCK
 169  */
 170 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 171                                             struct ath9k_channel *chan)
 172 {
 173         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 174         int cur_bb_spur, negative = 0, cck_spur_freq;
 175         int i;
 176         int range, max_spur_cnts, synth_freq;
 177         u8 *spur_fbin_ptr = NULL;
 178
 179         /*
 180          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 181          * is out-of-band and can be ignored.
 182          */
 183
 184         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
 185                 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
 186                                                          IS_CHAN_2GHZ(chan));
 187                 if (spur_fbin_ptr[0] == 0) /* No spur */
 188                         return;
 189                 max_spur_cnts = 5;
 190                 if (IS_CHAN_HT40(chan)) {
 191                         range = 19;
 192                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 193                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 194                                 synth_freq = chan->channel + 10;
 195                         else
 196                                 synth_freq = chan->channel - 10;
 197                 } else {
 198                         range = 10;
 199                         synth_freq = chan->channel;
 200                 }
 201         } else {
 202                 range = 10;
 203                 max_spur_cnts = 4;
 204                 synth_freq = chan->channel;
 205         }
 206
 207         for (i = 0; i < max_spur_cnts; i++) {
 208                 negative = 0;
 209                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
 210                         cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
 211                                         IS_CHAN_2GHZ(chan)) - synth_freq;
 212                 else
 213                         cur_bb_spur = spur_freq[i] - synth_freq;
 214
 215                 if (cur_bb_spur < 0) {
 216                         negative = 1;
 217                         cur_bb_spur = -cur_bb_spur;
 218                 }
 219                 if (cur_bb_spur < range) {
 220                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 221
 222                         if (negative == 1)
 223                                 cck_spur_freq = -cck_spur_freq;
 224
 225                         cck_spur_freq = cck_spur_freq & 0xfffff;
 226
 227                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 228                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 229                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 230                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 231                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 232                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 233                                       0x2);
 234                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 235                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 236                                       0x1);
 237                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 238                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 239                                       cck_spur_freq);
 240
 241                         return;
 242                 }
 243         }
 244
 245         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 246                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 247         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 248                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 249         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 250                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 251 }
 252
 253 /* Clean all spur register fields */
 254 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 255 {
 256         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 257                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 258         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 259                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 260         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 261                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 262         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 263                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 264         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 265                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 266         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 267                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 268         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 269                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 270         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 271                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 272         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 273                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 274
 275         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 276                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 277         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 278                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 279         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 280                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 281         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 282                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 283         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 284                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 285         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 286                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 287         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 288                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 289         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 290                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 291         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 292                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 293         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 294                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 295 }
 296
 297 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 298                                 int freq_offset,
 299                                 int spur_freq_sd,
 300                                 int spur_delta_phase,
 301                                 int spur_subchannel_sd)
 302 {
 303         int mask_index = 0;
 304
 305         /* OFDM Spur mitigation */
 306         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 307                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 308         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 309                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 310         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 311                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 312         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 313                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 314         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 315                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 316         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 317                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 318         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 319                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 320         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 321                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 322         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 323                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 324
 325         if (REG_READ_FIELD(ah, AR_PHY_MODE,
 326                            AR_PHY_MODE_DYNAMIC) == 0x1)
 327                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 328                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 329
 330         mask_index = (freq_offset << 4) / 5;
 331         if (mask_index < 0)
 332                 mask_index = mask_index - 1;
 333
 334         mask_index = mask_index & 0x7f;
 335
 336         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 337                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 338         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 339                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 340         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 341                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 342         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 343                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 344         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 345                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 346         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 347                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 348         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 349                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 350         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 351                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 352         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 353                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 354         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 355                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 356 }
 357
 358 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 359                                      struct ath9k_channel *chan,
 360                                      int freq_offset)
 361 {
 362         int spur_freq_sd = 0;
 363         int spur_subchannel_sd = 0;
 364         int spur_delta_phase = 0;
 365
 366         if (IS_CHAN_HT40(chan)) {
 367                 if (freq_offset < 0) {
 368                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 369                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 370                                 spur_subchannel_sd = 1;
 371                         else
 372                                 spur_subchannel_sd = 0;
 373
 374                         spur_freq_sd = (freq_offset << 9) / 11;
 375
 376                 } else {
 377                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 378                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 379                                 spur_subchannel_sd = 0;
 380                         else
 381                                 spur_subchannel_sd = 1;
 382
 383                         spur_freq_sd = (freq_offset << 9) / 11;
 384
 385                 }
 386
 387                 spur_delta_phase = (freq_offset << 17) / 5;
 388
 389         } else {
 390                 spur_subchannel_sd = 0;
 391                 spur_freq_sd = (freq_offset << 9) /11;
 392                 spur_delta_phase = (freq_offset << 18) / 5;
 393         }
 394
 395         spur_freq_sd = spur_freq_sd & 0x3ff;
 396         spur_delta_phase = spur_delta_phase & 0xfffff;
 397
 398         ar9003_hw_spur_ofdm(ah,
 399                             freq_offset,
 400                             spur_freq_sd,
 401                             spur_delta_phase,
 402                             spur_subchannel_sd);
 403 }
 404
 405 /* Spur mitigation for OFDM */
 406 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 407                                          struct ath9k_channel *chan)
 408 {
 409         int synth_freq;
 410         int range = 10;
 411         int freq_offset = 0;
 412         int mode;
 413         u8* spurChansPtr;
 414         unsigned int i;
 415         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 416
 417         if (IS_CHAN_5GHZ(chan)) {
 418                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 419                 mode = 0;
 420         }
 421         else {
 422                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 423                 mode = 1;
 424         }
 425
 426         if (spurChansPtr[0] == 0)
 427                 return; /* No spur in the mode */
 428
 429         if (IS_CHAN_HT40(chan)) {
 430                 range = 19;
 431                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 432                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 433                         synth_freq = chan->channel - 10;
 434                 else
 435                         synth_freq = chan->channel + 10;
 436         } else {
 437                 range = 10;
 438                 synth_freq = chan->channel;
 439         }
 440
 441         ar9003_hw_spur_ofdm_clear(ah);
 442
 443         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 444                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
 445                 if (abs(freq_offset) < range) {
 446                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
 447                         break;
 448                 }
 449         }
 450 }
 451
 452 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 453                                     struct ath9k_channel *chan)
 454 {
 455         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 456         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 457 }
 458
 459 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 460                                          struct ath9k_channel *chan)
 461 {
 462         u32 pll;
 463
 464         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 465
 466         if (chan && IS_CHAN_HALF_RATE(chan))
 467                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 468         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 469                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 470
 471         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 472
 473         return pll;
 474 }
 475
 476 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 477                                        struct ath9k_channel *chan)
 478 {
 479         u32 phymode;
 480         u32 enableDacFifo = 0;
 481
 482         enableDacFifo =
 483                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 484
 485         /* Enable 11n HT, 20 MHz */
 486         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 487                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 488
 489         /* Configure baseband for dynamic 20/40 operation */
 490         if (IS_CHAN_HT40(chan)) {
 491                 phymode |= AR_PHY_GC_DYN2040_EN;
 492                 /* Configure control (primary) channel at +-10MHz */
 493                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 494                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 495                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 496
 497         }
 498
 499         /* make sure we preserve INI settings */
 500         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 501         /* turn off Green Field detection for STA for now */
 502         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 503
 504         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 505
 506         /* Configure MAC for 20/40 operation */
 507         ath9k_hw_set11nmac2040(ah);
 508
 509         /* global transmit timeout (25 TUs default)*/
 510         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 511         /* carrier sense timeout */
 512         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 513 }
 514
 515 static void ar9003_hw_init_bb(struct ath_hw *ah,
 516                               struct ath9k_channel *chan)
 517 {
 518         u32 synthDelay;
 519
 520         /*
 521          * Wait for the frequency synth to settle (synth goes on
 522          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 523          * Value is in 100ns increments.
 524          */
 525         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 526         if (IS_CHAN_B(chan))
 527                 synthDelay = (4 * synthDelay) / 22;
 528         else
 529                 synthDelay /= 10;
 530
 531         /* Activate the PHY (includes baseband activate + synthesizer on) */
 532         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 533
 534         /*
 535          * There is an issue if the AP starts the calibration before
 536          * the base band timeout completes.  This could result in the
 537          * rx_clear false triggering.  As a workaround we add delay an
 538          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 539          * does not happen.
 540          */
 541         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 542 }
 543
 544 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 545 {
 546         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 547                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 548                             AR_PHY_SWAP_ALT_CHAIN);
 549
 550         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 551         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 552
 553         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 554                 tx = 3;
 555         else if (AR_SREV_9462(ah))
 556                 /* xxx only when MCI support is enabled */
 557                 tx = 3;
 558
 559         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 560 }
 561
 562 /*
 563  * Override INI values with chip specific configuration.
 564  */
 565 static void ar9003_hw_override_ini(struct ath_hw *ah)
 566 {
 567         u32 val;
 568
 569         /*
 570          * Set the RX_ABORT and RX_DIS and clear it only after
 571          * RXE is set for MAC. This prevents frames with
 572          * corrupted descriptor status.
 573          */
 574         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 575
 576         /*
 577          * For AR9280 and above, there is a new feature that allows
 578          * Multicast search based on both MAC Address and Key ID. By default,
 579          * this feature is enabled. But since the driver is not using this
 580          * feature, we switch it off; otherwise multicast search based on
 581          * MAC addr only will fail.
 582          */
 583         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 584         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 585                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 586
 587         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
 588                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 589 }
 590
 591 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 592                                struct ar5416IniArray *iniArr,
 593                                int column)
 594 {
 595         unsigned int i, regWrites = 0;
 596
 597         /* New INI format: Array may be undefined (pre, core, post arrays) */
 598         if (!iniArr->ia_array)
 599                 return;
 600
 601         /*
 602          * New INI format: Pre, core, and post arrays for a given subsystem
 603          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 604          * the array is non-modal and force the column to 1.
 605          */
 606         if (column >= iniArr->ia_columns)
 607                 column = 1;
 608
 609         for (i = 0; i < iniArr->ia_rows; i++) {
 610                 u32 reg = INI_RA(iniArr, i, 0);
 611                 u32 val = INI_RA(iniArr, i, column);
 612
 613                 REG_WRITE(ah, reg, val);
 614
 615                 DO_DELAY(regWrites);
 616         }
 617 }
 618
 619 static int ar9003_hw_process_ini(struct ath_hw *ah,
 620                                  struct ath9k_channel *chan)
 621 {
 622         unsigned int regWrites = 0, i;
 623         u32 modesIndex;
 624
 625         switch (chan->chanmode) {
 626         case CHANNEL_A:
 627         case CHANNEL_A_HT20:
 628                 modesIndex = 1;
 629                 break;
 630         case CHANNEL_A_HT40PLUS:
 631         case CHANNEL_A_HT40MINUS:
 632                 modesIndex = 2;
 633                 break;
 634         case CHANNEL_G:
 635         case CHANNEL_G_HT20:
 636         case CHANNEL_B:
 637                 modesIndex = 4;
 638                 break;
 639         case CHANNEL_G_HT40PLUS:
 640         case CHANNEL_G_HT40MINUS:
 641                 modesIndex = 3;
 642                 break;
 643
 644         default:
 645                 return -EINVAL;
 646         }
 647
 648         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 649                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 650                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 651                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 652                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 653                 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
 654                         ar9003_hw_prog_ini(ah,
 655                                            &ah->ini_radio_post_sys2ant,
 656                                            modesIndex);
 657         }
 658
 659         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 660         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 661
 662         /*
 663          * For 5GHz channels requiring Fast Clock, apply
 664          * different modal values.
 665          */
 666         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 667                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
 668                                 modesIndex, regWrites);
 669
 670         if (AR_SREV_9330(ah))
 671                 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
 672
 673         if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
 674                 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
 675
 676         if (AR_SREV_9462(ah))
 677                 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
 678
 679         ah->modes_index = modesIndex;
 680         ar9003_hw_override_ini(ah);
 681         ar9003_hw_set_channel_regs(ah, chan);
 682         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 683         ath9k_hw_apply_txpower(ah, chan);
 684
 685         if (AR_SREV_9462(ah)) {
 686                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 687                                 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 688                         ah->enabled_cals |= TX_IQ_CAL;
 689                 else
 690                         ah->enabled_cals &= ~TX_IQ_CAL;
 691
 692                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 693                         ah->enabled_cals |= TX_CL_CAL;
 694                 else
 695                         ah->enabled_cals &= ~TX_CL_CAL;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 702                                  struct ath9k_channel *chan)
 703 {
 704         u32 rfMode = 0;
 705
 706         if (chan == NULL)
 707                 return;
 708
 709         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 710                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 711
 712         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 713                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 714
 715         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 716 }
 717
 718 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 719 {
 720         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 721 }
 722
 723 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 724                                       struct ath9k_channel *chan)
 725 {
 726         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 727         u32 clockMhzScaled = 0x64000000;
 728         struct chan_centers centers;
 729
 730         /*
 731          * half and quarter rate can divide the scaled clock by 2 or 4
 732          * scale for selected channel bandwidth
 733          */
 734         if (IS_CHAN_HALF_RATE(chan))
 735                 clockMhzScaled = clockMhzScaled >> 1;
 736         else if (IS_CHAN_QUARTER_RATE(chan))
 737                 clockMhzScaled = clockMhzScaled >> 2;
 738
 739         /*
 740          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 741          * scaled coef to provide precision for this floating calculation
 742          */
 743         ath9k_hw_get_channel_centers(ah, chan, &centers);
 744         coef_scaled = clockMhzScaled / centers.synth_center;
 745
 746         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 747                                       &ds_coef_exp);
 748
 749         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 750                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 751         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 752                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 753
 754         /*
 755          * For Short GI,
 756          * scaled coeff is 9/10 that of normal coeff
 757          */
 758         coef_scaled = (9 * coef_scaled) / 10;
 759
 760         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 761                                       &ds_coef_exp);
 762
 763         /* for short gi */
 764         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 765                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 766         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 767                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 768 }
 769
 770 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 771 {
 772         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 773         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 774                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 775 }
 776
 777 /*
 778  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 779  * Read the phy active delay register. Value is in 100ns increments.
 780  */
 781 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 782 {
 783         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 784         if (IS_CHAN_B(ah->curchan))
 785                 synthDelay = (4 * synthDelay) / 22;
 786         else
 787                 synthDelay /= 10;
 788
 789         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 790
 791         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 792 }
 793
 794 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 795                                   enum ath9k_ani_cmd cmd, int param)
 796 {
 797         struct ath_common *common = ath9k_hw_common(ah);
 798         struct ath9k_channel *chan = ah->curchan;
 799         struct ar5416AniState *aniState = &chan->ani;
 800         s32 value, value2;
 801
 802         switch (cmd & ah->ani_function) {
 803         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 804                 /*
 805                  * on == 1 means ofdm weak signal detection is ON
 806                  * on == 1 is the default, for less noise immunity
 807                  *
 808                  * on == 0 means ofdm weak signal detection is OFF
 809                  * on == 0 means more noise imm
 810                  */
 811                 u32 on = param ? 1 : 0;
 812                 /*
 813                  * make register setting for default
 814                  * (weak sig detect ON) come from INI file
 815                  */
 816                 int m1ThreshLow = on ?
 817                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 818                 int m2ThreshLow = on ?
 819                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 820                 int m1Thresh = on ?
 821                         aniState->iniDef.m1Thresh : m1Thresh_off;
 822                 int m2Thresh = on ?
 823                         aniState->iniDef.m2Thresh : m2Thresh_off;
 824                 int m2CountThr = on ?
 825                         aniState->iniDef.m2CountThr : m2CountThr_off;
 826                 int m2CountThrLow = on ?
 827                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 828                 int m1ThreshLowExt = on ?
 829                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 830                 int m2ThreshLowExt = on ?
 831                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 832                 int m1ThreshExt = on ?
 833                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 834                 int m2ThreshExt = on ?
 835                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 836
 837                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 838                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 839                               m1ThreshLow);
 840                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 841                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 842                               m2ThreshLow);
 843                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 844                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
 845                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 846                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
 847                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 848                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
 849                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 850                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 851                               m2CountThrLow);
 852
 853                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 854                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
 855                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 856                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
 857                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 858                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
 859                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 860                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
 861
 862                 if (on)
 863                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 864                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 865                 else
 866                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 867                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 868
 869                 if (!on != aniState->ofdmWeakSigDetectOff) {
 870                         ath_dbg(common, ATH_DBG_ANI,
 871                                 "** ch %d: ofdm weak signal: %s=>%s\n",
 872                                 chan->channel,
 873                                 !aniState->ofdmWeakSigDetectOff ?
 874                                 "on" : "off",
 875                                 on ? "on" : "off");
 876                         if (on)
 877                                 ah->stats.ast_ani_ofdmon++;
 878                         else
 879                                 ah->stats.ast_ani_ofdmoff++;
 880                         aniState->ofdmWeakSigDetectOff = !on;
 881                 }
 882                 break;
 883         }
 884         case ATH9K_ANI_FIRSTEP_LEVEL:{
 885                 u32 level = param;
 886
 887                 if (level >= ARRAY_SIZE(firstep_table)) {
 888                         ath_dbg(common, ATH_DBG_ANI,
 889                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
 890                                 level, ARRAY_SIZE(firstep_table));
 891                         return false;
 892                 }
 893
 894                 /*
 895                  * make register setting relative to default
 896                  * from INI file & cap value
 897                  */
 898                 value = firstep_table[level] -
 899                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 900                         aniState->iniDef.firstep;
 901                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 902                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 903                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 904                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 905                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 906                               AR_PHY_FIND_SIG_FIRSTEP,
 907                               value);
 908                 /*
 909                  * we need to set first step low register too
 910                  * make register setting relative to default
 911                  * from INI file & cap value
 912                  */
 913                 value2 = firstep_table[level] -
 914                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 915                          aniState->iniDef.firstepLow;
 916                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 917                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 918                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 919                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 920
 921                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
 922                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 923
 924                 if (level != aniState->firstepLevel) {
 925                         ath_dbg(common, ATH_DBG_ANI,
 926                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
 927                                 chan->channel,
 928                                 aniState->firstepLevel,
 929                                 level,
 930                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
 931                                 value,
 932                                 aniState->iniDef.firstep);
 933                         ath_dbg(common, ATH_DBG_ANI,
 934                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
 935                                 chan->channel,
 936                                 aniState->firstepLevel,
 937                                 level,
 938                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
 939                                 value2,
 940                                 aniState->iniDef.firstepLow);
 941                         if (level > aniState->firstepLevel)
 942                                 ah->stats.ast_ani_stepup++;
 943                         else if (level < aniState->firstepLevel)
 944                                 ah->stats.ast_ani_stepdown++;
 945                         aniState->firstepLevel = level;
 946                 }
 947                 break;
 948         }
 949         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 950                 u32 level = param;
 951
 952                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
 953                         ath_dbg(common, ATH_DBG_ANI,
 954                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
 955                                 level, ARRAY_SIZE(cycpwrThr1_table));
 956                         return false;
 957                 }
 958                 /*
 959                  * make register setting relative to default
 960                  * from INI file & cap value
 961                  */
 962                 value = cycpwrThr1_table[level] -
 963                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 964                         aniState->iniDef.cycpwrThr1;
 965                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 966                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 967                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 968                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 969                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
 970                               AR_PHY_TIMING5_CYCPWR_THR1,
 971                               value);
 972
 973                 /*
 974                  * set AR_PHY_EXT_CCA for extension channel
 975                  * make register setting relative to default
 976                  * from INI file & cap value
 977                  */
 978                 value2 = cycpwrThr1_table[level] -
 979                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 980                          aniState->iniDef.cycpwrThr1Ext;
 981                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 982                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 983                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 984                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 985                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 986                               AR_PHY_EXT_CYCPWR_THR1, value2);
 987
 988                 if (level != aniState->spurImmunityLevel) {
 989                         ath_dbg(common, ATH_DBG_ANI,
 990                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
 991                                 chan->channel,
 992                                 aniState->spurImmunityLevel,
 993                                 level,
 994                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
 995                                 value,
 996                                 aniState->iniDef.cycpwrThr1);
 997                         ath_dbg(common, ATH_DBG_ANI,
 998                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
 999                                 chan->channel,
1000                                 aniState->spurImmunityLevel,
1001                                 level,
1002                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1003                                 value2,
1004                                 aniState->iniDef.cycpwrThr1Ext);
1005                         if (level > aniState->spurImmunityLevel)
1006                                 ah->stats.ast_ani_spurup++;
1007                         else if (level < aniState->spurImmunityLevel)
1008                                 ah->stats.ast_ani_spurdown++;
1009                         aniState->spurImmunityLevel = level;
1010                 }
1011                 break;
1012         }
1013         case ATH9K_ANI_MRC_CCK:{
1014                 /*
1015                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1016                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1017                  */
1018                 bool is_on = param ? 1 : 0;
1019                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1020                               AR_PHY_MRC_CCK_ENABLE, is_on);
1021                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1022                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1023                 if (!is_on != aniState->mrcCCKOff) {
1024                         ath_dbg(common, ATH_DBG_ANI,
1025                                 "** ch %d: MRC CCK: %s=>%s\n",
1026                                 chan->channel,
1027                                 !aniState->mrcCCKOff ? "on" : "off",
1028                                 is_on ? "on" : "off");
1029                 if (is_on)
1030                         ah->stats.ast_ani_ccklow++;
1031                 else
1032                         ah->stats.ast_ani_cckhigh++;
1033                 aniState->mrcCCKOff = !is_on;
1034                 }
1035         break;
1036         }
1037         case ATH9K_ANI_PRESENT:
1038                 break;
1039         default:
1040                 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1041                 return false;
1042         }
1043
1044         ath_dbg(common, ATH_DBG_ANI,
1045                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1046                 aniState->spurImmunityLevel,
1047                 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1048                 aniState->firstepLevel,
1049                 !aniState->mrcCCKOff ? "on" : "off",
1050                 aniState->listenTime,
1051                 aniState->ofdmPhyErrCount,
1052                 aniState->cckPhyErrCount);
1053         return true;
1054 }
1055
1056 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1057                               int16_t nfarray[NUM_NF_READINGS])
1058 {
1059 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1060 #define AR_PHY_CH_MINCCA_PWR_S  20
1061 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1062 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1063
1064         int16_t nf;
1065         int i;
1066
1067         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1068                 if (ah->rxchainmask & BIT(i)) {
1069                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1070                                          AR_PHY_CH_MINCCA_PWR);
1071                         nfarray[i] = sign_extend32(nf, 8);
1072
1073                         if (IS_CHAN_HT40(ah->curchan)) {
1074                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1075
1076                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1077                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1078                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1079                         }
1080                 }
1081         }
1082 }
1083
1084 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1085 {
1086         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1087         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1088         if (AR_SREV_9330(ah))
1089                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1090         else
1091                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1092         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1093         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1094         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1095 }
1096
1097 /*
1098  * Initialize the ANI register values with default (ini) values.
1099  * This routine is called during a (full) hardware reset after
1100  * all the registers are initialised from the INI.
1101  */
1102 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1103 {
1104         struct ar5416AniState *aniState;
1105         struct ath_common *common = ath9k_hw_common(ah);
1106         struct ath9k_channel *chan = ah->curchan;
1107         struct ath9k_ani_default *iniDef;
1108         u32 val;
1109
1110         aniState = &ah->curchan->ani;
1111         iniDef = &aniState->iniDef;
1112
1113         ath_dbg(common, ATH_DBG_ANI,
1114                 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1115                 ah->hw_version.macVersion,
1116                 ah->hw_version.macRev,
1117                 ah->opmode,
1118                 chan->channel,
1119                 chan->channelFlags);
1120
1121         val = REG_READ(ah, AR_PHY_SFCORR);
1122         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1123         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1124         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1125
1126         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1127         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1128         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1129         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1130
1131         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1132         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1133         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1134         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1135         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1136         iniDef->firstep = REG_READ_FIELD(ah,
1137                                          AR_PHY_FIND_SIG,
1138                                          AR_PHY_FIND_SIG_FIRSTEP);
1139         iniDef->firstepLow = REG_READ_FIELD(ah,
1140                                             AR_PHY_FIND_SIG_LOW,
1141                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1142         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1143                                             AR_PHY_TIMING5,
1144                                             AR_PHY_TIMING5_CYCPWR_THR1);
1145         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1146                                                AR_PHY_EXT_CCA,
1147                                                AR_PHY_EXT_CYCPWR_THR1);
1148
1149         /* these levels just got reset to defaults by the INI */
1150         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1151         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1152         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1153         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1154 }
1155
1156 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1157                                        struct ath_hw_radar_conf *conf)
1158 {
1159         u32 radar_0 = 0, radar_1 = 0;
1160
1161         if (!conf) {
1162                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1163                 return;
1164         }
1165
1166         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1167         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1168         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1169         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1170         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1171         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1172
1173         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1174         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1175         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1176         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1177         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1178
1179         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1180         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1181         if (conf->ext_channel)
1182                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1183         else
1184                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1185 }
1186
1187 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1188 {
1189         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1190
1191         conf->fir_power = -28;
1192         conf->radar_rssi = 0;
1193         conf->pulse_height = 10;
1194         conf->pulse_rssi = 24;
1195         conf->pulse_inband = 8;
1196         conf->pulse_maxlen = 255;
1197         conf->pulse_inband_step = 12;
1198         conf->radar_inband = 8;
1199 }
1200
1201 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1202                                    struct ath_hw_antcomb_conf *antconf)
1203 {
1204         u32 regval;
1205
1206         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1207         antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1208                                   AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1209         antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1210                                  AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1211         antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1212                                   AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1213
1214         if (AR_SREV_9330_11(ah)) {
1215                 antconf->lna1_lna2_delta = -9;
1216                 antconf->div_group = 1;
1217         } else if (AR_SREV_9485(ah)) {
1218                 antconf->lna1_lna2_delta = -9;
1219                 antconf->div_group = 2;
1220         } else {
1221                 antconf->lna1_lna2_delta = -3;
1222                 antconf->div_group = 0;
1223         }
1224 }
1225
1226 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1227                                    struct ath_hw_antcomb_conf *antconf)
1228 {
1229         u32 regval;
1230
1231         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1232         regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1233                     AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1234                     AR_PHY_9485_ANT_FAST_DIV_BIAS |
1235                     AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1236                     AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1237         regval |= ((antconf->main_lna_conf <<
1238                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1239                    & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1240         regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1241                    & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1242         regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1243                    & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1244         regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1245                    & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1246         regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1247                    & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1248
1249         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1250 }
1251
1252 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1253                                       struct ath9k_channel *chan,
1254                                       u8 *ini_reloaded)
1255 {
1256         unsigned int regWrites = 0;
1257         u32 modesIndex;
1258
1259         switch (chan->chanmode) {
1260         case CHANNEL_A:
1261         case CHANNEL_A_HT20:
1262                 modesIndex = 1;
1263                 break;
1264         case CHANNEL_A_HT40PLUS:
1265         case CHANNEL_A_HT40MINUS:
1266                 modesIndex = 2;
1267                 break;
1268         case CHANNEL_G:
1269         case CHANNEL_G_HT20:
1270         case CHANNEL_B:
1271                 modesIndex = 4;
1272                 break;
1273         case CHANNEL_G_HT40PLUS:
1274         case CHANNEL_G_HT40MINUS:
1275                 modesIndex = 3;
1276                 break;
1277
1278         default:
1279                 return -EINVAL;
1280         }
1281
1282         if (modesIndex == ah->modes_index) {
1283                 *ini_reloaded = false;
1284                 goto set_rfmode;
1285         }
1286
1287         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1288         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1289         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1290         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1291         if (AR_SREV_9462_20(ah))
1292                 ar9003_hw_prog_ini(ah,
1293                                 &ah->ini_radio_post_sys2ant,
1294                                 modesIndex);
1295
1296         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1297
1298         /*
1299          * For 5GHz channels requiring Fast Clock, apply
1300          * different modal values.
1301          */
1302         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1303                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites);
1304
1305         if (AR_SREV_9330(ah))
1306                 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
1307
1308         if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
1309                 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
1310
1311         ah->modes_index = modesIndex;
1312         *ini_reloaded = true;
1313
1314 set_rfmode:
1315         ar9003_hw_set_rfmode(ah, chan);
1316         return 0;
1317 }
1318
1319 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1320 {
1321         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1322         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1323         static const u32 ar9300_cca_regs[6] = {
1324                 AR_PHY_CCA_0,
1325                 AR_PHY_CCA_1,
1326                 AR_PHY_CCA_2,
1327                 AR_PHY_EXT_CCA,
1328                 AR_PHY_EXT_CCA_1,
1329                 AR_PHY_EXT_CCA_2,
1330         };
1331
1332         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1333         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1334         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1335         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1336         priv_ops->init_bb = ar9003_hw_init_bb;
1337         priv_ops->process_ini = ar9003_hw_process_ini;
1338         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1339         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1340         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1341         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1342         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1343         priv_ops->ani_control = ar9003_hw_ani_control;
1344         priv_ops->do_getnf = ar9003_hw_do_getnf;
1345         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1346         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1347         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1348
1349         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1350         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1351
1352         ar9003_hw_set_nf_limits(ah);
1353         ar9003_hw_set_radar_conf(ah);
1354         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1355 }
1356
1357 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1358 {
1359         struct ath_common *common = ath9k_hw_common(ah);
1360         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1361         u32 val, idle_count;
1362
1363         if (!idle_tmo_ms) {
1364                 /* disable IRQ, disable chip-reset for BB panic */
1365                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1366                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1367                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1368                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1369
1370                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1371                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1372                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1373                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1374                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1375
1376                 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1377                 return;
1378         }
1379
1380         /* enable IRQ, disable chip-reset for BB watchdog */
1381         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1382         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1383                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1384                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1385
1386         /* bound limit to 10 secs */
1387         if (idle_tmo_ms > 10000)
1388                 idle_tmo_ms = 10000;
1389
1390         /*
1391          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1392          *
1393          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1394          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1395          *
1396          * Given we use fast clock now in 5 GHz, these time units should
1397          * be common for both 2 GHz and 5 GHz.
1398          */
1399         idle_count = (100 * idle_tmo_ms) / 74;
1400         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1401                 idle_count = (100 * idle_tmo_ms) / 37;
1402
1403         /*
1404          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1405          * set idle time-out.
1406          */
1407         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1408                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1409                   AR_PHY_WATCHDOG_IDLE_MASK |
1410                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1411
1412         ath_dbg(common, ATH_DBG_RESET,
1413                 "Enabled BB Watchdog timeout (%u ms)\n",
1414                 idle_tmo_ms);
1415 }
1416
1417 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1418 {
1419         /*
1420          * we want to avoid printing in ISR context so we save the
1421          * watchdog status to be printed later in bottom half context.
1422          */
1423         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1424
1425         /*
1426          * the watchdog timer should reset on status read but to be sure
1427          * sure we write 0 to the watchdog status bit.
1428          */
1429         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1430                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1431 }
1432
1433 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1434 {
1435         struct ath_common *common = ath9k_hw_common(ah);
1436         u32 status;
1437
1438         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1439                 return;
1440
1441         status = ah->bb_watchdog_last_status;
1442         ath_dbg(common, ATH_DBG_RESET,
1443                 "\n==== BB update: BB status=0x%08x ====\n", status);
1444         ath_dbg(common, ATH_DBG_RESET,
1445                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1446                 MS(status, AR_PHY_WATCHDOG_INFO),
1447                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1448                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1449                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1450                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1451                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1452                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1453                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1454                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1455
1456         ath_dbg(common, ATH_DBG_RESET,
1457                 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1458                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1459                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1460         ath_dbg(common, ATH_DBG_RESET,
1461                 "** BB mode: BB_gen_controls=0x%08x **\n",
1462                 REG_READ(ah, AR_PHY_GEN_CTRL));
1463
1464 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1465         if (common->cc_survey.cycles)
1466                 ath_dbg(common, ATH_DBG_RESET,
1467                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1468                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1469
1470         ath_dbg(common, ATH_DBG_RESET,
1471                 "==== BB update: done ====\n\n");
1472 }
1473 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1474
1475 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1476 {
1477         u32 val;
1478
1479         /* While receiving unsupported rate frame rx state machine
1480          * gets into a state 0xb and if phy_restart happens in that
1481          * state, BB would go hang. If RXSM is in 0xb state after
1482          * first bb panic, ensure to disable the phy_restart.
1483          */
1484         if (!((MS(ah->bb_watchdog_last_status,
1485                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1486             ah->bb_hang_rx_ofdm))
1487                 return;
1488
1489         ah->bb_hang_rx_ofdm = true;
1490         val = REG_READ(ah, AR_PHY_RESTART);
1491         val &= ~AR_PHY_RESTART_ENA;
1492
1493         REG_WRITE(ah, AR_PHY_RESTART, val);
1494 }
1495 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);