drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_eeprom.h"
  21
  22 #define COMP_HDR_LEN 4
  23 #define COMP_CKSUM_LEN 2
  24
  25 #define AR_CH0_TOP (0x00016288)
  26 #define AR_CH0_TOP_XPABIASLVL (0x300)
  27 #define AR_CH0_TOP_XPABIASLVL_S (8)
  28
  29 #define AR_CH0_THERM (0x00016290)
  30 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
  31 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
  32 #define AR_CH0_THERM_XPASHORT2GND 0x4
  33 #define AR_CH0_THERM_XPASHORT2GND_S 2
  34
  35 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
  36 #define AR_SWITCH_TABLE_COM_ALL_S (0)
  37
  38 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
  39 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
  40
  41 #define AR_SWITCH_TABLE_ALL (0xfff)
  42 #define AR_SWITCH_TABLE_ALL_S (0)
  43
  44 #define LE16(x) __constant_cpu_to_le16(x)
  45 #define LE32(x) __constant_cpu_to_le32(x)
  46
  47 /* Local defines to distinguish between extension and control CTL's */
  48 #define EXT_ADDITIVE (0x8000)
  49 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  50 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  51 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  52 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  53 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9  /* 10*log10(3)*2 */
  54 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
  55 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
  56 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
  57
  58 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  59 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  60
  61 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  62
  63 #define EEPROM_DATA_LEN_9485    1088
  64
  65 static int ar9003_hw_power_interpolate(int32_t x,
  66                                        int32_t *px, int32_t *py, u_int16_t np);
  67
  68
  69 static const struct ar9300_eeprom ar9300_default = {
  70         .eepromVersion = 2,
  71         .templateVersion = 2,
  72         .macAddr = {1, 2, 3, 4, 5, 6},
  73         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  74                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  75         .baseEepHeader = {
  76                 .regDmn = { LE16(0), LE16(0x1f) },
  77                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  78                 .opCapFlags = {
  79                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  80                         .eepMisc = 0,
  81                 },
  82                 .rfSilent = 0,
  83                 .blueToothOptions = 0,
  84                 .deviceCap = 0,
  85                 .deviceType = 5, /* takes lower byte in eeprom location */
  86                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  87                 .params_for_tuning_caps = {0, 0},
  88                 .featureEnable = 0x0c,
  89                  /*
  90                   * bit0 - enable tx temp comp - disabled
  91                   * bit1 - enable tx volt comp - disabled
  92                   * bit2 - enable fastClock - enabled
  93                   * bit3 - enable doubling - enabled
  94                   * bit4 - enable internal regulator - disabled
  95                   * bit5 - enable pa predistortion - disabled
  96                   */
  97                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  98                 .eepromWriteEnableGpio = 3,
  99                 .wlanDisableGpio = 0,
 100                 .wlanLedGpio = 8,
 101                 .rxBandSelectGpio = 0xff,
 102                 .txrxgain = 0,
 103                 .swreg = 0,
 104          },
 105         .modalHeader2G = {
 106         /* ar9300_modal_eep_header  2g */
 107                 /* 4 idle,t1,t2,b(4 bits per setting) */
 108                 .antCtrlCommon = LE32(0x110),
 109                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 110                 .antCtrlCommon2 = LE32(0x22222),
 111
 112                 /*
 113                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 114                  * rx1, rx12, b (2 bits each)
 115                  */
 116                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 117
 118                 /*
 119                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 120                  * for ar9280 (0xa20c/b20c 5:0)
 121                  */
 122                 .xatten1DB = {0, 0, 0},
 123
 124                 /*
 125                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 126                  * for ar9280 (0xa20c/b20c 16:12
 127                  */
 128                 .xatten1Margin = {0, 0, 0},
 129                 .tempSlope = 36,
 130                 .voltSlope = 0,
 131
 132                 /*
 133                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 134                  * channels in usual fbin coding format
 135                  */
 136                 .spurChans = {0, 0, 0, 0, 0},
 137
 138                 /*
 139                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 140                  * if the register is per chain
 141                  */
 142                 .noiseFloorThreshCh = {-1, 0, 0},
 143                 .ob = {1, 1, 1},/* 3 chain */
 144                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 145                 .db_stage3 = {0, 0, 0},
 146                 .db_stage4 = {0, 0, 0},
 147                 .xpaBiasLvl = 0,
 148                 .txFrameToDataStart = 0x0e,
 149                 .txFrameToPaOn = 0x0e,
 150                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 151                 .antennaGain = 0,
 152                 .switchSettling = 0x2c,
 153                 .adcDesiredSize = -30,
 154                 .txEndToXpaOff = 0,
 155                 .txEndToRxOn = 0x2,
 156                 .txFrameToXpaOn = 0xe,
 157                 .thresh62 = 28,
 158                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 159                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 160                 .futureModal = {
 161                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 162                 },
 163          },
 164         .base_ext1 = {
 165                 .ant_div_control = 0,
 166                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 167         },
 168         .calFreqPier2G = {
 169                 FREQ2FBIN(2412, 1),
 170                 FREQ2FBIN(2437, 1),
 171                 FREQ2FBIN(2472, 1),
 172          },
 173         /* ar9300_cal_data_per_freq_op_loop 2g */
 174         .calPierData2G = {
 175                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 176                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 177                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 178          },
 179         .calTarget_freqbin_Cck = {
 180                 FREQ2FBIN(2412, 1),
 181                 FREQ2FBIN(2484, 1),
 182          },
 183         .calTarget_freqbin_2G = {
 184                 FREQ2FBIN(2412, 1),
 185                 FREQ2FBIN(2437, 1),
 186                 FREQ2FBIN(2472, 1)
 187          },
 188         .calTarget_freqbin_2GHT20 = {
 189                 FREQ2FBIN(2412, 1),
 190                 FREQ2FBIN(2437, 1),
 191                 FREQ2FBIN(2472, 1)
 192          },
 193         .calTarget_freqbin_2GHT40 = {
 194                 FREQ2FBIN(2412, 1),
 195                 FREQ2FBIN(2437, 1),
 196                 FREQ2FBIN(2472, 1)
 197          },
 198         .calTargetPowerCck = {
 199                  /* 1L-5L,5S,11L,11S */
 200                  { {36, 36, 36, 36} },
 201                  { {36, 36, 36, 36} },
 202         },
 203         .calTargetPower2G = {
 204                  /* 6-24,36,48,54 */
 205                  { {32, 32, 28, 24} },
 206                  { {32, 32, 28, 24} },
 207                  { {32, 32, 28, 24} },
 208         },
 209         .calTargetPower2GHT20 = {
 210                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 211                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 212                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 213         },
 214         .calTargetPower2GHT40 = {
 215                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 216                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 217                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 218         },
 219         .ctlIndex_2G =  {
 220                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 221                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 222         },
 223         .ctl_freqbin_2G = {
 224                 {
 225                         FREQ2FBIN(2412, 1),
 226                         FREQ2FBIN(2417, 1),
 227                         FREQ2FBIN(2457, 1),
 228                         FREQ2FBIN(2462, 1)
 229                 },
 230                 {
 231                         FREQ2FBIN(2412, 1),
 232                         FREQ2FBIN(2417, 1),
 233                         FREQ2FBIN(2462, 1),
 234                         0xFF,
 235                 },
 236
 237                 {
 238                         FREQ2FBIN(2412, 1),
 239                         FREQ2FBIN(2417, 1),
 240                         FREQ2FBIN(2462, 1),
 241                         0xFF,
 242                 },
 243                 {
 244                         FREQ2FBIN(2422, 1),
 245                         FREQ2FBIN(2427, 1),
 246                         FREQ2FBIN(2447, 1),
 247                         FREQ2FBIN(2452, 1)
 248                 },
 249
 250                 {
 251                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 252                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 253                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 254                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 255                 },
 256
 257                 {
 258                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 259                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 260                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 261                         0,
 262                 },
 263
 264                 {
 265                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 266                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 267                         FREQ2FBIN(2472, 1),
 268                         0,
 269                 },
 270
 271                 {
 272                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 273                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 274                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 275                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 276                 },
 277
 278                 {
 279                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 280                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 281                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 282                 },
 283
 284                 {
 285                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 286                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 287                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 288                         0
 289                 },
 290
 291                 {
 292                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 293                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 294                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 295                         0
 296                 },
 297
 298                 {
 299                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 300                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 301                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 302                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 303                 }
 304          },
 305         .ctlPowerData_2G = {
 306                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 307                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 308                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 309
 310                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 311                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 312                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 313
 314                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 315                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 316                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 317
 318                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 319                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 320                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 321          },
 322         .modalHeader5G = {
 323                 /* 4 idle,t1,t2,b (4 bits per setting) */
 324                 .antCtrlCommon = LE32(0x110),
 325                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 326                 .antCtrlCommon2 = LE32(0x22222),
 327                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 328                 .antCtrlChain = {
 329                         LE16(0x000), LE16(0x000), LE16(0x000),
 330                 },
 331                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 332                 .xatten1DB = {0, 0, 0},
 333
 334                 /*
 335                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 336                  * for merlin (0xa20c/b20c 16:12
 337                  */
 338                 .xatten1Margin = {0, 0, 0},
 339                 .tempSlope = 68,
 340                 .voltSlope = 0,
 341                 /* spurChans spur channels in usual fbin coding format */
 342                 .spurChans = {0, 0, 0, 0, 0},
 343                 /* noiseFloorThreshCh Check if the register is per chain */
 344                 .noiseFloorThreshCh = {-1, 0, 0},
 345                 .ob = {3, 3, 3}, /* 3 chain */
 346                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 347                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 348                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 349                 .xpaBiasLvl = 0,
 350                 .txFrameToDataStart = 0x0e,
 351                 .txFrameToPaOn = 0x0e,
 352                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 353                 .antennaGain = 0,
 354                 .switchSettling = 0x2d,
 355                 .adcDesiredSize = -30,
 356                 .txEndToXpaOff = 0,
 357                 .txEndToRxOn = 0x2,
 358                 .txFrameToXpaOn = 0xe,
 359                 .thresh62 = 28,
 360                 .papdRateMaskHt20 = LE32(0x0c80c080),
 361                 .papdRateMaskHt40 = LE32(0x0080c080),
 362                 .futureModal = {
 363                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 364                 },
 365          },
 366         .base_ext2 = {
 367                 .tempSlopeLow = 0,
 368                 .tempSlopeHigh = 0,
 369                 .xatten1DBLow = {0, 0, 0},
 370                 .xatten1MarginLow = {0, 0, 0},
 371                 .xatten1DBHigh = {0, 0, 0},
 372                 .xatten1MarginHigh = {0, 0, 0}
 373         },
 374         .calFreqPier5G = {
 375                 FREQ2FBIN(5180, 0),
 376                 FREQ2FBIN(5220, 0),
 377                 FREQ2FBIN(5320, 0),
 378                 FREQ2FBIN(5400, 0),
 379                 FREQ2FBIN(5500, 0),
 380                 FREQ2FBIN(5600, 0),
 381                 FREQ2FBIN(5725, 0),
 382                 FREQ2FBIN(5825, 0)
 383         },
 384         .calPierData5G = {
 385                         {
 386                                 {0, 0, 0, 0, 0},
 387                                 {0, 0, 0, 0, 0},
 388                                 {0, 0, 0, 0, 0},
 389                                 {0, 0, 0, 0, 0},
 390                                 {0, 0, 0, 0, 0},
 391                                 {0, 0, 0, 0, 0},
 392                                 {0, 0, 0, 0, 0},
 393                                 {0, 0, 0, 0, 0},
 394                         },
 395                         {
 396                                 {0, 0, 0, 0, 0},
 397                                 {0, 0, 0, 0, 0},
 398                                 {0, 0, 0, 0, 0},
 399                                 {0, 0, 0, 0, 0},
 400                                 {0, 0, 0, 0, 0},
 401                                 {0, 0, 0, 0, 0},
 402                                 {0, 0, 0, 0, 0},
 403                                 {0, 0, 0, 0, 0},
 404                         },
 405                         {
 406                                 {0, 0, 0, 0, 0},
 407                                 {0, 0, 0, 0, 0},
 408                                 {0, 0, 0, 0, 0},
 409                                 {0, 0, 0, 0, 0},
 410                                 {0, 0, 0, 0, 0},
 411                                 {0, 0, 0, 0, 0},
 412                                 {0, 0, 0, 0, 0},
 413                                 {0, 0, 0, 0, 0},
 414                         },
 415
 416         },
 417         .calTarget_freqbin_5G = {
 418                 FREQ2FBIN(5180, 0),
 419                 FREQ2FBIN(5220, 0),
 420                 FREQ2FBIN(5320, 0),
 421                 FREQ2FBIN(5400, 0),
 422                 FREQ2FBIN(5500, 0),
 423                 FREQ2FBIN(5600, 0),
 424                 FREQ2FBIN(5725, 0),
 425                 FREQ2FBIN(5825, 0)
 426         },
 427         .calTarget_freqbin_5GHT20 = {
 428                 FREQ2FBIN(5180, 0),
 429                 FREQ2FBIN(5240, 0),
 430                 FREQ2FBIN(5320, 0),
 431                 FREQ2FBIN(5500, 0),
 432                 FREQ2FBIN(5700, 0),
 433                 FREQ2FBIN(5745, 0),
 434                 FREQ2FBIN(5725, 0),
 435                 FREQ2FBIN(5825, 0)
 436         },
 437         .calTarget_freqbin_5GHT40 = {
 438                 FREQ2FBIN(5180, 0),
 439                 FREQ2FBIN(5240, 0),
 440                 FREQ2FBIN(5320, 0),
 441                 FREQ2FBIN(5500, 0),
 442                 FREQ2FBIN(5700, 0),
 443                 FREQ2FBIN(5745, 0),
 444                 FREQ2FBIN(5725, 0),
 445                 FREQ2FBIN(5825, 0)
 446          },
 447         .calTargetPower5G = {
 448                 /* 6-24,36,48,54 */
 449                 { {20, 20, 20, 10} },
 450                 { {20, 20, 20, 10} },
 451                 { {20, 20, 20, 10} },
 452                 { {20, 20, 20, 10} },
 453                 { {20, 20, 20, 10} },
 454                 { {20, 20, 20, 10} },
 455                 { {20, 20, 20, 10} },
 456                 { {20, 20, 20, 10} },
 457          },
 458         .calTargetPower5GHT20 = {
 459                 /*
 460                  * 0_8_16,1-3_9-11_17-19,
 461                  * 4,5,6,7,12,13,14,15,20,21,22,23
 462                  */
 463                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 464                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 465                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 466                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 467                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 468                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 469                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 470                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 471          },
 472         .calTargetPower5GHT40 =  {
 473                 /*
 474                  * 0_8_16,1-3_9-11_17-19,
 475                  * 4,5,6,7,12,13,14,15,20,21,22,23
 476                  */
 477                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 478                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 479                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 480                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 481                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 482                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 483                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 484                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 485          },
 486         .ctlIndex_5G =  {
 487                 0x10, 0x16, 0x18, 0x40, 0x46,
 488                 0x48, 0x30, 0x36, 0x38
 489         },
 490         .ctl_freqbin_5G =  {
 491                 {
 492                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 493                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 494                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 495                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 496                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 497                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 498                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 499                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 500                 },
 501                 {
 502                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 503                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 504                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 505                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 506                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 507                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 508                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 509                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 510                 },
 511
 512                 {
 513                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 514                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 515                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 516                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 517                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 518                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 519                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 520                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 521                 },
 522
 523                 {
 524                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 525                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 526                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 527                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 528                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 529                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 530                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 531                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 532                 },
 533
 534                 {
 535                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 536                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 537                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 538                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 539                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 540                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 541                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 542                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 543                 },
 544
 545                 {
 546                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 547                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 548                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 549                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 550                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 551                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 552                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 553                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 554                 },
 555
 556                 {
 557                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 558                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 559                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 560                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 561                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 562                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 563                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 564                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 565                 },
 566
 567                 {
 568                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 569                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 570                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 571                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 572                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 573                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 574                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 575                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 576                 },
 577
 578                 {
 579                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 580                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 581                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 582                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 583                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 584                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 585                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 586                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 587                 }
 588          },
 589         .ctlPowerData_5G = {
 590                 {
 591                         {
 592                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 593                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 594                         }
 595                 },
 596                 {
 597                         {
 598                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 599                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 600                         }
 601                 },
 602                 {
 603                         {
 604                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 605                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 606                         }
 607                 },
 608                 {
 609                         {
 610                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 611                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 612                         }
 613                 },
 614                 {
 615                         {
 616                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 617                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 618                         }
 619                 },
 620                 {
 621                         {
 622                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 623                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 624                         }
 625                 },
 626                 {
 627                         {
 628                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 629                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 630                         }
 631                 },
 632                 {
 633                         {
 634                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 635                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 636                         }
 637                 },
 638                 {
 639                         {
 640                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 641                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 642                         }
 643                 },
 644          }
 645 };
 646
 647 static const struct ar9300_eeprom ar9300_x113 = {
 648         .eepromVersion = 2,
 649         .templateVersion = 6,
 650         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 651         .custData = {"x113-023-f0000"},
 652         .baseEepHeader = {
 653                 .regDmn = { LE16(0), LE16(0x1f) },
 654                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 655                 .opCapFlags = {
 656                         .opFlags = AR5416_OPFLAGS_11A,
 657                         .eepMisc = 0,
 658                 },
 659                 .rfSilent = 0,
 660                 .blueToothOptions = 0,
 661                 .deviceCap = 0,
 662                 .deviceType = 5, /* takes lower byte in eeprom location */
 663                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 664                 .params_for_tuning_caps = {0, 0},
 665                 .featureEnable = 0x0d,
 666                  /*
 667                   * bit0 - enable tx temp comp - disabled
 668                   * bit1 - enable tx volt comp - disabled
 669                   * bit2 - enable fastClock - enabled
 670                   * bit3 - enable doubling - enabled
 671                   * bit4 - enable internal regulator - disabled
 672                   * bit5 - enable pa predistortion - disabled
 673                   */
 674                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 675                 .eepromWriteEnableGpio = 6,
 676                 .wlanDisableGpio = 0,
 677                 .wlanLedGpio = 8,
 678                 .rxBandSelectGpio = 0xff,
 679                 .txrxgain = 0x21,
 680                 .swreg = 0,
 681          },
 682         .modalHeader2G = {
 683         /* ar9300_modal_eep_header  2g */
 684                 /* 4 idle,t1,t2,b(4 bits per setting) */
 685                 .antCtrlCommon = LE32(0x110),
 686                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 687                 .antCtrlCommon2 = LE32(0x44444),
 688
 689                 /*
 690                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 691                  * rx1, rx12, b (2 bits each)
 692                  */
 693                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 694
 695                 /*
 696                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 697                  * for ar9280 (0xa20c/b20c 5:0)
 698                  */
 699                 .xatten1DB = {0, 0, 0},
 700
 701                 /*
 702                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 703                  * for ar9280 (0xa20c/b20c 16:12
 704                  */
 705                 .xatten1Margin = {0, 0, 0},
 706                 .tempSlope = 25,
 707                 .voltSlope = 0,
 708
 709                 /*
 710                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 711                  * channels in usual fbin coding format
 712                  */
 713                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 714
 715                 /*
 716                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 717                  * if the register is per chain
 718                  */
 719                 .noiseFloorThreshCh = {-1, 0, 0},
 720                 .ob = {1, 1, 1},/* 3 chain */
 721                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 722                 .db_stage3 = {0, 0, 0},
 723                 .db_stage4 = {0, 0, 0},
 724                 .xpaBiasLvl = 0,
 725                 .txFrameToDataStart = 0x0e,
 726                 .txFrameToPaOn = 0x0e,
 727                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 728                 .antennaGain = 0,
 729                 .switchSettling = 0x2c,
 730                 .adcDesiredSize = -30,
 731                 .txEndToXpaOff = 0,
 732                 .txEndToRxOn = 0x2,
 733                 .txFrameToXpaOn = 0xe,
 734                 .thresh62 = 28,
 735                 .papdRateMaskHt20 = LE32(0x0c80c080),
 736                 .papdRateMaskHt40 = LE32(0x0080c080),
 737                 .futureModal = {
 738                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 739                 },
 740          },
 741          .base_ext1 = {
 742                 .ant_div_control = 0,
 743                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 744          },
 745         .calFreqPier2G = {
 746                 FREQ2FBIN(2412, 1),
 747                 FREQ2FBIN(2437, 1),
 748                 FREQ2FBIN(2472, 1),
 749          },
 750         /* ar9300_cal_data_per_freq_op_loop 2g */
 751         .calPierData2G = {
 752                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 753                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 754                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 755          },
 756         .calTarget_freqbin_Cck = {
 757                 FREQ2FBIN(2412, 1),
 758                 FREQ2FBIN(2472, 1),
 759          },
 760         .calTarget_freqbin_2G = {
 761                 FREQ2FBIN(2412, 1),
 762                 FREQ2FBIN(2437, 1),
 763                 FREQ2FBIN(2472, 1)
 764          },
 765         .calTarget_freqbin_2GHT20 = {
 766                 FREQ2FBIN(2412, 1),
 767                 FREQ2FBIN(2437, 1),
 768                 FREQ2FBIN(2472, 1)
 769          },
 770         .calTarget_freqbin_2GHT40 = {
 771                 FREQ2FBIN(2412, 1),
 772                 FREQ2FBIN(2437, 1),
 773                 FREQ2FBIN(2472, 1)
 774          },
 775         .calTargetPowerCck = {
 776                  /* 1L-5L,5S,11L,11S */
 777                  { {34, 34, 34, 34} },
 778                  { {34, 34, 34, 34} },
 779         },
 780         .calTargetPower2G = {
 781                  /* 6-24,36,48,54 */
 782                  { {34, 34, 32, 32} },
 783                  { {34, 34, 32, 32} },
 784                  { {34, 34, 32, 32} },
 785         },
 786         .calTargetPower2GHT20 = {
 787                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 788                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 789                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 790         },
 791         .calTargetPower2GHT40 = {
 792                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 793                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 794                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 795         },
 796         .ctlIndex_2G =  {
 797                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 798                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 799         },
 800         .ctl_freqbin_2G = {
 801                 {
 802                         FREQ2FBIN(2412, 1),
 803                         FREQ2FBIN(2417, 1),
 804                         FREQ2FBIN(2457, 1),
 805                         FREQ2FBIN(2462, 1)
 806                 },
 807                 {
 808                         FREQ2FBIN(2412, 1),
 809                         FREQ2FBIN(2417, 1),
 810                         FREQ2FBIN(2462, 1),
 811                         0xFF,
 812                 },
 813
 814                 {
 815                         FREQ2FBIN(2412, 1),
 816                         FREQ2FBIN(2417, 1),
 817                         FREQ2FBIN(2462, 1),
 818                         0xFF,
 819                 },
 820                 {
 821                         FREQ2FBIN(2422, 1),
 822                         FREQ2FBIN(2427, 1),
 823                         FREQ2FBIN(2447, 1),
 824                         FREQ2FBIN(2452, 1)
 825                 },
 826
 827                 {
 828                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 829                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 830                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 831                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 832                 },
 833
 834                 {
 835                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 836                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 837                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 838                         0,
 839                 },
 840
 841                 {
 842                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 843                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 844                         FREQ2FBIN(2472, 1),
 845                         0,
 846                 },
 847
 848                 {
 849                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 850                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 851                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 852                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 853                 },
 854
 855                 {
 856                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 857                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 858                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 859                 },
 860
 861                 {
 862                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 863                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 864                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 865                         0
 866                 },
 867
 868                 {
 869                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 870                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 871                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 872                         0
 873                 },
 874
 875                 {
 876                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 877                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 878                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 879                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 880                 }
 881          },
 882         .ctlPowerData_2G = {
 883                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 884                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 885                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 886
 887                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
 888                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 889                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 890
 891                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 892                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 893                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 894
 895                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 896                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 897                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 898          },
 899         .modalHeader5G = {
 900                 /* 4 idle,t1,t2,b (4 bits per setting) */
 901                 .antCtrlCommon = LE32(0x220),
 902                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 903                 .antCtrlCommon2 = LE32(0x11111),
 904                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 905                 .antCtrlChain = {
 906                         LE16(0x150), LE16(0x150), LE16(0x150),
 907                 },
 908                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 909                 .xatten1DB = {0, 0, 0},
 910
 911                 /*
 912                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 913                  * for merlin (0xa20c/b20c 16:12
 914                  */
 915                 .xatten1Margin = {0, 0, 0},
 916                 .tempSlope = 68,
 917                 .voltSlope = 0,
 918                 /* spurChans spur channels in usual fbin coding format */
 919                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 920                 /* noiseFloorThreshCh Check if the register is per chain */
 921                 .noiseFloorThreshCh = {-1, 0, 0},
 922                 .ob = {3, 3, 3}, /* 3 chain */
 923                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 924                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 925                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 926                 .xpaBiasLvl = 0xf,
 927                 .txFrameToDataStart = 0x0e,
 928                 .txFrameToPaOn = 0x0e,
 929                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 930                 .antennaGain = 0,
 931                 .switchSettling = 0x2d,
 932                 .adcDesiredSize = -30,
 933                 .txEndToXpaOff = 0,
 934                 .txEndToRxOn = 0x2,
 935                 .txFrameToXpaOn = 0xe,
 936                 .thresh62 = 28,
 937                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 938                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 939                 .futureModal = {
 940                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 941                 },
 942          },
 943         .base_ext2 = {
 944                 .tempSlopeLow = 72,
 945                 .tempSlopeHigh = 105,
 946                 .xatten1DBLow = {0, 0, 0},
 947                 .xatten1MarginLow = {0, 0, 0},
 948                 .xatten1DBHigh = {0, 0, 0},
 949                 .xatten1MarginHigh = {0, 0, 0}
 950          },
 951         .calFreqPier5G = {
 952                 FREQ2FBIN(5180, 0),
 953                 FREQ2FBIN(5240, 0),
 954                 FREQ2FBIN(5320, 0),
 955                 FREQ2FBIN(5400, 0),
 956                 FREQ2FBIN(5500, 0),
 957                 FREQ2FBIN(5600, 0),
 958                 FREQ2FBIN(5745, 0),
 959                 FREQ2FBIN(5785, 0)
 960         },
 961         .calPierData5G = {
 962                         {
 963                                 {0, 0, 0, 0, 0},
 964                                 {0, 0, 0, 0, 0},
 965                                 {0, 0, 0, 0, 0},
 966                                 {0, 0, 0, 0, 0},
 967                                 {0, 0, 0, 0, 0},
 968                                 {0, 0, 0, 0, 0},
 969                                 {0, 0, 0, 0, 0},
 970                                 {0, 0, 0, 0, 0},
 971                         },
 972                         {
 973                                 {0, 0, 0, 0, 0},
 974                                 {0, 0, 0, 0, 0},
 975                                 {0, 0, 0, 0, 0},
 976                                 {0, 0, 0, 0, 0},
 977                                 {0, 0, 0, 0, 0},
 978                                 {0, 0, 0, 0, 0},
 979                                 {0, 0, 0, 0, 0},
 980                                 {0, 0, 0, 0, 0},
 981                         },
 982                         {
 983                                 {0, 0, 0, 0, 0},
 984                                 {0, 0, 0, 0, 0},
 985                                 {0, 0, 0, 0, 0},
 986                                 {0, 0, 0, 0, 0},
 987                                 {0, 0, 0, 0, 0},
 988                                 {0, 0, 0, 0, 0},
 989                                 {0, 0, 0, 0, 0},
 990                                 {0, 0, 0, 0, 0},
 991                         },
 992
 993         },
 994         .calTarget_freqbin_5G = {
 995                 FREQ2FBIN(5180, 0),
 996                 FREQ2FBIN(5220, 0),
 997                 FREQ2FBIN(5320, 0),
 998                 FREQ2FBIN(5400, 0),
 999                 FREQ2FBIN(5500, 0),
1000                 FREQ2FBIN(5600, 0),
1001                 FREQ2FBIN(5745, 0),
1002                 FREQ2FBIN(5785, 0)
1003         },
1004         .calTarget_freqbin_5GHT20 = {
1005                 FREQ2FBIN(5180, 0),
1006                 FREQ2FBIN(5240, 0),
1007                 FREQ2FBIN(5320, 0),
1008                 FREQ2FBIN(5400, 0),
1009                 FREQ2FBIN(5500, 0),
1010                 FREQ2FBIN(5700, 0),
1011                 FREQ2FBIN(5745, 0),
1012                 FREQ2FBIN(5825, 0)
1013         },
1014         .calTarget_freqbin_5GHT40 = {
1015                 FREQ2FBIN(5190, 0),
1016                 FREQ2FBIN(5230, 0),
1017                 FREQ2FBIN(5320, 0),
1018                 FREQ2FBIN(5410, 0),
1019                 FREQ2FBIN(5510, 0),
1020                 FREQ2FBIN(5670, 0),
1021                 FREQ2FBIN(5755, 0),
1022                 FREQ2FBIN(5825, 0)
1023          },
1024         .calTargetPower5G = {
1025                 /* 6-24,36,48,54 */
1026                 { {42, 40, 40, 34} },
1027                 { {42, 40, 40, 34} },
1028                 { {42, 40, 40, 34} },
1029                 { {42, 40, 40, 34} },
1030                 { {42, 40, 40, 34} },
1031                 { {42, 40, 40, 34} },
1032                 { {42, 40, 40, 34} },
1033                 { {42, 40, 40, 34} },
1034          },
1035         .calTargetPower5GHT20 = {
1036                 /*
1037                  * 0_8_16,1-3_9-11_17-19,
1038                  * 4,5,6,7,12,13,14,15,20,21,22,23
1039                  */
1040                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1041                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1042                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1043                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1044                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1045                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1046                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1047                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1048          },
1049         .calTargetPower5GHT40 =  {
1050                 /*
1051                  * 0_8_16,1-3_9-11_17-19,
1052                  * 4,5,6,7,12,13,14,15,20,21,22,23
1053                  */
1054                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1055                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1056                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1057                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1058                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1059                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1060                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1061                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1062          },
1063         .ctlIndex_5G =  {
1064                 0x10, 0x16, 0x18, 0x40, 0x46,
1065                 0x48, 0x30, 0x36, 0x38
1066         },
1067         .ctl_freqbin_5G =  {
1068                 {
1069                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1071                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1072                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1073                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1074                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1076                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1077                 },
1078                 {
1079                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1080                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1081                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1082                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1083                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1084                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1085                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1086                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1087                 },
1088
1089                 {
1090                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1091                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1092                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1093                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1094                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1095                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1096                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1097                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1098                 },
1099
1100                 {
1101                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1102                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1103                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1104                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1105                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1106                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1107                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1108                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1109                 },
1110
1111                 {
1112                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1113                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1114                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1115                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1116                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1117                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1118                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1119                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1120                 },
1121
1122                 {
1123                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1124                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1125                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1126                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1127                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1128                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1129                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1130                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1131                 },
1132
1133                 {
1134                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1135                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1136                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1137                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1138                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1139                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1140                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1141                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1142                 },
1143
1144                 {
1145                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1146                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1147                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1148                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1149                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1150                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1151                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1152                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1153                 },
1154
1155                 {
1156                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1157                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1158                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1159                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1160                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1161                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1162                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1163                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1164                 }
1165          },
1166         .ctlPowerData_5G = {
1167                 {
1168                         {
1169                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1170                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1171                         }
1172                 },
1173                 {
1174                         {
1175                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1176                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1177                         }
1178                 },
1179                 {
1180                         {
1181                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1182                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1183                         }
1184                 },
1185                 {
1186                         {
1187                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1188                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1189                         }
1190                 },
1191                 {
1192                         {
1193                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1194                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1195                         }
1196                 },
1197                 {
1198                         {
1199                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1200                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1201                         }
1202                 },
1203                 {
1204                         {
1205                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1206                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1207                         }
1208                 },
1209                 {
1210                         {
1211                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1212                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1213                         }
1214                 },
1215                 {
1216                         {
1217                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1218                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1219                         }
1220                 },
1221          }
1222 };
1223
1224
1225 static const struct ar9300_eeprom ar9300_h112 = {
1226         .eepromVersion = 2,
1227         .templateVersion = 3,
1228         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1229         .custData = {"h112-241-f0000"},
1230         .baseEepHeader = {
1231                 .regDmn = { LE16(0), LE16(0x1f) },
1232                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1233                 .opCapFlags = {
1234                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1235                         .eepMisc = 0,
1236                 },
1237                 .rfSilent = 0,
1238                 .blueToothOptions = 0,
1239                 .deviceCap = 0,
1240                 .deviceType = 5, /* takes lower byte in eeprom location */
1241                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1242                 .params_for_tuning_caps = {0, 0},
1243                 .featureEnable = 0x0d,
1244                 /*
1245                  * bit0 - enable tx temp comp - disabled
1246                  * bit1 - enable tx volt comp - disabled
1247                  * bit2 - enable fastClock - enabled
1248                  * bit3 - enable doubling - enabled
1249                  * bit4 - enable internal regulator - disabled
1250                  * bit5 - enable pa predistortion - disabled
1251                  */
1252                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1253                 .eepromWriteEnableGpio = 6,
1254                 .wlanDisableGpio = 0,
1255                 .wlanLedGpio = 8,
1256                 .rxBandSelectGpio = 0xff,
1257                 .txrxgain = 0x10,
1258                 .swreg = 0,
1259         },
1260         .modalHeader2G = {
1261                 /* ar9300_modal_eep_header  2g */
1262                 /* 4 idle,t1,t2,b(4 bits per setting) */
1263                 .antCtrlCommon = LE32(0x110),
1264                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1265                 .antCtrlCommon2 = LE32(0x44444),
1266
1267                 /*
1268                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1269                  * rx1, rx12, b (2 bits each)
1270                  */
1271                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1272
1273                 /*
1274                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1275                  * for ar9280 (0xa20c/b20c 5:0)
1276                  */
1277                 .xatten1DB = {0, 0, 0},
1278
1279                 /*
1280                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1281                  * for ar9280 (0xa20c/b20c 16:12
1282                  */
1283                 .xatten1Margin = {0, 0, 0},
1284                 .tempSlope = 25,
1285                 .voltSlope = 0,
1286
1287                 /*
1288                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1289                  * channels in usual fbin coding format
1290                  */
1291                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1292
1293                 /*
1294                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1295                  * if the register is per chain
1296                  */
1297                 .noiseFloorThreshCh = {-1, 0, 0},
1298                 .ob = {1, 1, 1},/* 3 chain */
1299                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1300                 .db_stage3 = {0, 0, 0},
1301                 .db_stage4 = {0, 0, 0},
1302                 .xpaBiasLvl = 0,
1303                 .txFrameToDataStart = 0x0e,
1304                 .txFrameToPaOn = 0x0e,
1305                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1306                 .antennaGain = 0,
1307                 .switchSettling = 0x2c,
1308                 .adcDesiredSize = -30,
1309                 .txEndToXpaOff = 0,
1310                 .txEndToRxOn = 0x2,
1311                 .txFrameToXpaOn = 0xe,
1312                 .thresh62 = 28,
1313                 .papdRateMaskHt20 = LE32(0x80c080),
1314                 .papdRateMaskHt40 = LE32(0x80c080),
1315                 .futureModal = {
1316                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1317                 },
1318         },
1319         .base_ext1 = {
1320                 .ant_div_control = 0,
1321                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1322         },
1323         .calFreqPier2G = {
1324                 FREQ2FBIN(2412, 1),
1325                 FREQ2FBIN(2437, 1),
1326                 FREQ2FBIN(2472, 1),
1327         },
1328         /* ar9300_cal_data_per_freq_op_loop 2g */
1329         .calPierData2G = {
1330                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1331                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1332                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1333         },
1334         .calTarget_freqbin_Cck = {
1335                 FREQ2FBIN(2412, 1),
1336                 FREQ2FBIN(2484, 1),
1337         },
1338         .calTarget_freqbin_2G = {
1339                 FREQ2FBIN(2412, 1),
1340                 FREQ2FBIN(2437, 1),
1341                 FREQ2FBIN(2472, 1)
1342         },
1343         .calTarget_freqbin_2GHT20 = {
1344                 FREQ2FBIN(2412, 1),
1345                 FREQ2FBIN(2437, 1),
1346                 FREQ2FBIN(2472, 1)
1347         },
1348         .calTarget_freqbin_2GHT40 = {
1349                 FREQ2FBIN(2412, 1),
1350                 FREQ2FBIN(2437, 1),
1351                 FREQ2FBIN(2472, 1)
1352         },
1353         .calTargetPowerCck = {
1354                 /* 1L-5L,5S,11L,11S */
1355                 { {34, 34, 34, 34} },
1356                 { {34, 34, 34, 34} },
1357         },
1358         .calTargetPower2G = {
1359                 /* 6-24,36,48,54 */
1360                 { {34, 34, 32, 32} },
1361                 { {34, 34, 32, 32} },
1362                 { {34, 34, 32, 32} },
1363         },
1364         .calTargetPower2GHT20 = {
1365                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1366                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1367                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1368         },
1369         .calTargetPower2GHT40 = {
1370                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1371                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1372                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1373         },
1374         .ctlIndex_2G =  {
1375                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1376                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1377         },
1378         .ctl_freqbin_2G = {
1379                 {
1380                         FREQ2FBIN(2412, 1),
1381                         FREQ2FBIN(2417, 1),
1382                         FREQ2FBIN(2457, 1),
1383                         FREQ2FBIN(2462, 1)
1384                 },
1385                 {
1386                         FREQ2FBIN(2412, 1),
1387                         FREQ2FBIN(2417, 1),
1388                         FREQ2FBIN(2462, 1),
1389                         0xFF,
1390                 },
1391
1392                 {
1393                         FREQ2FBIN(2412, 1),
1394                         FREQ2FBIN(2417, 1),
1395                         FREQ2FBIN(2462, 1),
1396                         0xFF,
1397                 },
1398                 {
1399                         FREQ2FBIN(2422, 1),
1400                         FREQ2FBIN(2427, 1),
1401                         FREQ2FBIN(2447, 1),
1402                         FREQ2FBIN(2452, 1)
1403                 },
1404
1405                 {
1406                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1410                 },
1411
1412                 {
1413                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416                         0,
1417                 },
1418
1419                 {
1420                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1421                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1422                         FREQ2FBIN(2472, 1),
1423                         0,
1424                 },
1425
1426                 {
1427                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1428                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1429                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1430                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1431                 },
1432
1433                 {
1434                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1435                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1436                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1437                 },
1438
1439                 {
1440                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1443                         0
1444                 },
1445
1446                 {
1447                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1448                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1449                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1450                         0
1451                 },
1452
1453                 {
1454                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1455                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1456                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1457                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1458                 }
1459         },
1460         .ctlPowerData_2G = {
1461                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1462                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1463                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1464
1465                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1466                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1467                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1468
1469                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1470                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1471                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1472
1473                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1474                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1475                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1476         },
1477         .modalHeader5G = {
1478                 /* 4 idle,t1,t2,b (4 bits per setting) */
1479                 .antCtrlCommon = LE32(0x220),
1480                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1481                 .antCtrlCommon2 = LE32(0x44444),
1482                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1483                 .antCtrlChain = {
1484                         LE16(0x150), LE16(0x150), LE16(0x150),
1485                 },
1486                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1487                 .xatten1DB = {0, 0, 0},
1488
1489                 /*
1490                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1491                  * for merlin (0xa20c/b20c 16:12
1492                  */
1493                 .xatten1Margin = {0, 0, 0},
1494                 .tempSlope = 45,
1495                 .voltSlope = 0,
1496                 /* spurChans spur channels in usual fbin coding format */
1497                 .spurChans = {0, 0, 0, 0, 0},
1498                 /* noiseFloorThreshCh Check if the register is per chain */
1499                 .noiseFloorThreshCh = {-1, 0, 0},
1500                 .ob = {3, 3, 3}, /* 3 chain */
1501                 .db_stage2 = {3, 3, 3}, /* 3 chain */
1502                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1503                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
1504                 .xpaBiasLvl = 0,
1505                 .txFrameToDataStart = 0x0e,
1506                 .txFrameToPaOn = 0x0e,
1507                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1508                 .antennaGain = 0,
1509                 .switchSettling = 0x2d,
1510                 .adcDesiredSize = -30,
1511                 .txEndToXpaOff = 0,
1512                 .txEndToRxOn = 0x2,
1513                 .txFrameToXpaOn = 0xe,
1514                 .thresh62 = 28,
1515                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1516                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1517                 .futureModal = {
1518                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1519                 },
1520         },
1521         .base_ext2 = {
1522                 .tempSlopeLow = 40,
1523                 .tempSlopeHigh = 50,
1524                 .xatten1DBLow = {0, 0, 0},
1525                 .xatten1MarginLow = {0, 0, 0},
1526                 .xatten1DBHigh = {0, 0, 0},
1527                 .xatten1MarginHigh = {0, 0, 0}
1528         },
1529         .calFreqPier5G = {
1530                 FREQ2FBIN(5180, 0),
1531                 FREQ2FBIN(5220, 0),
1532                 FREQ2FBIN(5320, 0),
1533                 FREQ2FBIN(5400, 0),
1534                 FREQ2FBIN(5500, 0),
1535                 FREQ2FBIN(5600, 0),
1536                 FREQ2FBIN(5700, 0),
1537                 FREQ2FBIN(5825, 0)
1538         },
1539         .calPierData5G = {
1540                 {
1541                         {0, 0, 0, 0, 0},
1542                         {0, 0, 0, 0, 0},
1543                         {0, 0, 0, 0, 0},
1544                         {0, 0, 0, 0, 0},
1545                         {0, 0, 0, 0, 0},
1546                         {0, 0, 0, 0, 0},
1547                         {0, 0, 0, 0, 0},
1548                         {0, 0, 0, 0, 0},
1549                 },
1550                 {
1551                         {0, 0, 0, 0, 0},
1552                         {0, 0, 0, 0, 0},
1553                         {0, 0, 0, 0, 0},
1554                         {0, 0, 0, 0, 0},
1555                         {0, 0, 0, 0, 0},
1556                         {0, 0, 0, 0, 0},
1557                         {0, 0, 0, 0, 0},
1558                         {0, 0, 0, 0, 0},
1559                 },
1560                 {
1561                         {0, 0, 0, 0, 0},
1562                         {0, 0, 0, 0, 0},
1563                         {0, 0, 0, 0, 0},
1564                         {0, 0, 0, 0, 0},
1565                         {0, 0, 0, 0, 0},
1566                         {0, 0, 0, 0, 0},
1567                         {0, 0, 0, 0, 0},
1568                         {0, 0, 0, 0, 0},
1569                 },
1570
1571         },
1572         .calTarget_freqbin_5G = {
1573                 FREQ2FBIN(5180, 0),
1574                 FREQ2FBIN(5240, 0),
1575                 FREQ2FBIN(5320, 0),
1576                 FREQ2FBIN(5400, 0),
1577                 FREQ2FBIN(5500, 0),
1578                 FREQ2FBIN(5600, 0),
1579                 FREQ2FBIN(5700, 0),
1580                 FREQ2FBIN(5825, 0)
1581         },
1582         .calTarget_freqbin_5GHT20 = {
1583                 FREQ2FBIN(5180, 0),
1584                 FREQ2FBIN(5240, 0),
1585                 FREQ2FBIN(5320, 0),
1586                 FREQ2FBIN(5400, 0),
1587                 FREQ2FBIN(5500, 0),
1588                 FREQ2FBIN(5700, 0),
1589                 FREQ2FBIN(5745, 0),
1590                 FREQ2FBIN(5825, 0)
1591         },
1592         .calTarget_freqbin_5GHT40 = {
1593                 FREQ2FBIN(5180, 0),
1594                 FREQ2FBIN(5240, 0),
1595                 FREQ2FBIN(5320, 0),
1596                 FREQ2FBIN(5400, 0),
1597                 FREQ2FBIN(5500, 0),
1598                 FREQ2FBIN(5700, 0),
1599                 FREQ2FBIN(5745, 0),
1600                 FREQ2FBIN(5825, 0)
1601         },
1602         .calTargetPower5G = {
1603                 /* 6-24,36,48,54 */
1604                 { {30, 30, 28, 24} },
1605                 { {30, 30, 28, 24} },
1606                 { {30, 30, 28, 24} },
1607                 { {30, 30, 28, 24} },
1608                 { {30, 30, 28, 24} },
1609                 { {30, 30, 28, 24} },
1610                 { {30, 30, 28, 24} },
1611                 { {30, 30, 28, 24} },
1612         },
1613         .calTargetPower5GHT20 = {
1614                 /*
1615                  * 0_8_16,1-3_9-11_17-19,
1616                  * 4,5,6,7,12,13,14,15,20,21,22,23
1617                  */
1618                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1619                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1620                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1621                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1622                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1623                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1624                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1625                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1626         },
1627         .calTargetPower5GHT40 =  {
1628                 /*
1629                  * 0_8_16,1-3_9-11_17-19,
1630                  * 4,5,6,7,12,13,14,15,20,21,22,23
1631                  */
1632                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1633                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1634                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1635                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1636                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1637                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1638                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1639                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1640         },
1641         .ctlIndex_5G =  {
1642                 0x10, 0x16, 0x18, 0x40, 0x46,
1643                 0x48, 0x30, 0x36, 0x38
1644         },
1645         .ctl_freqbin_5G =  {
1646                 {
1647                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1648                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1649                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1650                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1651                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1652                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1653                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1654                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1655                 },
1656                 {
1657                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1658                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1659                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1660                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1661                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1662                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1663                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1664                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1665                 },
1666
1667                 {
1668                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1669                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1670                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1671                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1672                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1673                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1674                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1675                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1676                 },
1677
1678                 {
1679                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1680                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1681                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1682                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1683                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1684                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1685                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1686                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1687                 },
1688
1689                 {
1690                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1691                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1692                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1693                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1694                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1695                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1696                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1697                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1698                 },
1699
1700                 {
1701                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1702                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1703                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1704                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1705                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1706                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1707                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1708                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1709                 },
1710
1711                 {
1712                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1713                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1714                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1715                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1716                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1717                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1718                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1719                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1720                 },
1721
1722                 {
1723                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1724                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1725                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1726                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1727                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1728                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1729                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1730                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1731                 },
1732
1733                 {
1734                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1735                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1736                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1737                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1738                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1739                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1740                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1741                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1742                 }
1743         },
1744         .ctlPowerData_5G = {
1745                 {
1746                         {
1747                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1749                         }
1750                 },
1751                 {
1752                         {
1753                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1754                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1755                         }
1756                 },
1757                 {
1758                         {
1759                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1760                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1761                         }
1762                 },
1763                 {
1764                         {
1765                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1766                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1767                         }
1768                 },
1769                 {
1770                         {
1771                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1772                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1773                         }
1774                 },
1775                 {
1776                         {
1777                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1778                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1779                         }
1780                 },
1781                 {
1782                         {
1783                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1784                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1785                         }
1786                 },
1787                 {
1788                         {
1789                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1790                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1791                         }
1792                 },
1793                 {
1794                         {
1795                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1796                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1797                         }
1798                 },
1799         }
1800 };
1801
1802
1803 static const struct ar9300_eeprom ar9300_x112 = {
1804         .eepromVersion = 2,
1805         .templateVersion = 5,
1806         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1807         .custData = {"x112-041-f0000"},
1808         .baseEepHeader = {
1809                 .regDmn = { LE16(0), LE16(0x1f) },
1810                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1811                 .opCapFlags = {
1812                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1813                         .eepMisc = 0,
1814                 },
1815                 .rfSilent = 0,
1816                 .blueToothOptions = 0,
1817                 .deviceCap = 0,
1818                 .deviceType = 5, /* takes lower byte in eeprom location */
1819                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1820                 .params_for_tuning_caps = {0, 0},
1821                 .featureEnable = 0x0d,
1822                 /*
1823                  * bit0 - enable tx temp comp - disabled
1824                  * bit1 - enable tx volt comp - disabled
1825                  * bit2 - enable fastclock - enabled
1826                  * bit3 - enable doubling - enabled
1827                  * bit4 - enable internal regulator - disabled
1828                  * bit5 - enable pa predistortion - disabled
1829                  */
1830                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1831                 .eepromWriteEnableGpio = 6,
1832                 .wlanDisableGpio = 0,
1833                 .wlanLedGpio = 8,
1834                 .rxBandSelectGpio = 0xff,
1835                 .txrxgain = 0x0,
1836                 .swreg = 0,
1837         },
1838         .modalHeader2G = {
1839                 /* ar9300_modal_eep_header  2g */
1840                 /* 4 idle,t1,t2,b(4 bits per setting) */
1841                 .antCtrlCommon = LE32(0x110),
1842                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1843                 .antCtrlCommon2 = LE32(0x22222),
1844
1845                 /*
1846                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1847                  * rx1, rx12, b (2 bits each)
1848                  */
1849                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1850
1851                 /*
1852                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1853                  * for ar9280 (0xa20c/b20c 5:0)
1854                  */
1855                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1856
1857                 /*
1858                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1859                  * for ar9280 (0xa20c/b20c 16:12
1860                  */
1861                 .xatten1Margin = {0x15, 0x15, 0x15},
1862                 .tempSlope = 50,
1863                 .voltSlope = 0,
1864
1865                 /*
1866                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1867                  * channels in usual fbin coding format
1868                  */
1869                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1870
1871                 /*
1872                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1873                  * if the register is per chain
1874                  */
1875                 .noiseFloorThreshCh = {-1, 0, 0},
1876                 .ob = {1, 1, 1},/* 3 chain */
1877                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1878                 .db_stage3 = {0, 0, 0},
1879                 .db_stage4 = {0, 0, 0},
1880                 .xpaBiasLvl = 0,
1881                 .txFrameToDataStart = 0x0e,
1882                 .txFrameToPaOn = 0x0e,
1883                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1884                 .antennaGain = 0,
1885                 .switchSettling = 0x2c,
1886                 .adcDesiredSize = -30,
1887                 .txEndToXpaOff = 0,
1888                 .txEndToRxOn = 0x2,
1889                 .txFrameToXpaOn = 0xe,
1890                 .thresh62 = 28,
1891                 .papdRateMaskHt20 = LE32(0x0c80c080),
1892                 .papdRateMaskHt40 = LE32(0x0080c080),
1893                 .futureModal = {
1894                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1895                 },
1896         },
1897         .base_ext1 = {
1898                 .ant_div_control = 0,
1899                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1900         },
1901         .calFreqPier2G = {
1902                 FREQ2FBIN(2412, 1),
1903                 FREQ2FBIN(2437, 1),
1904                 FREQ2FBIN(2472, 1),
1905         },
1906         /* ar9300_cal_data_per_freq_op_loop 2g */
1907         .calPierData2G = {
1908                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1909                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1910                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1911         },
1912         .calTarget_freqbin_Cck = {
1913                 FREQ2FBIN(2412, 1),
1914                 FREQ2FBIN(2472, 1),
1915         },
1916         .calTarget_freqbin_2G = {
1917                 FREQ2FBIN(2412, 1),
1918                 FREQ2FBIN(2437, 1),
1919                 FREQ2FBIN(2472, 1)
1920         },
1921         .calTarget_freqbin_2GHT20 = {
1922                 FREQ2FBIN(2412, 1),
1923                 FREQ2FBIN(2437, 1),
1924                 FREQ2FBIN(2472, 1)
1925         },
1926         .calTarget_freqbin_2GHT40 = {
1927                 FREQ2FBIN(2412, 1),
1928                 FREQ2FBIN(2437, 1),
1929                 FREQ2FBIN(2472, 1)
1930         },
1931         .calTargetPowerCck = {
1932                 /* 1L-5L,5S,11L,11s */
1933                 { {38, 38, 38, 38} },
1934                 { {38, 38, 38, 38} },
1935         },
1936         .calTargetPower2G = {
1937                 /* 6-24,36,48,54 */
1938                 { {38, 38, 36, 34} },
1939                 { {38, 38, 36, 34} },
1940                 { {38, 38, 34, 32} },
1941         },
1942         .calTargetPower2GHT20 = {
1943                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1944                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1945                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1946         },
1947         .calTargetPower2GHT40 = {
1948                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1949                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1950                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1951         },
1952         .ctlIndex_2G =  {
1953                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1954                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1955         },
1956         .ctl_freqbin_2G = {
1957                 {
1958                         FREQ2FBIN(2412, 1),
1959                         FREQ2FBIN(2417, 1),
1960                         FREQ2FBIN(2457, 1),
1961                         FREQ2FBIN(2462, 1)
1962                 },
1963                 {
1964                         FREQ2FBIN(2412, 1),
1965                         FREQ2FBIN(2417, 1),
1966                         FREQ2FBIN(2462, 1),
1967                         0xFF,
1968                 },
1969
1970                 {
1971                         FREQ2FBIN(2412, 1),
1972                         FREQ2FBIN(2417, 1),
1973                         FREQ2FBIN(2462, 1),
1974                         0xFF,
1975                 },
1976                 {
1977                         FREQ2FBIN(2422, 1),
1978                         FREQ2FBIN(2427, 1),
1979                         FREQ2FBIN(2447, 1),
1980                         FREQ2FBIN(2452, 1)
1981                 },
1982
1983                 {
1984                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1988                 },
1989
1990                 {
1991                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994                         0,
1995                 },
1996
1997                 {
1998                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000                         FREQ2FBIN(2472, 1),
2001                         0,
2002                 },
2003
2004                 {
2005                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2006                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2007                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2008                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2009                 },
2010
2011                 {
2012                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2013                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2014                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2015                 },
2016
2017                 {
2018                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2021                         0
2022                 },
2023
2024                 {
2025                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2026                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2027                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2028                         0
2029                 },
2030
2031                 {
2032                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2033                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2034                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2035                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2036                 }
2037         },
2038         .ctlPowerData_2G = {
2039                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2040                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2041                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2042
2043                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2044                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2045                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2046
2047                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2048                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2049                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2050
2051                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2052                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2053                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2054         },
2055         .modalHeader5G = {
2056                 /* 4 idle,t1,t2,b (4 bits per setting) */
2057                 .antCtrlCommon = LE32(0x110),
2058                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2059                 .antCtrlCommon2 = LE32(0x22222),
2060                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2061                 .antCtrlChain = {
2062                         LE16(0x0), LE16(0x0), LE16(0x0),
2063                 },
2064                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2065                 .xatten1DB = {0x13, 0x19, 0x17},
2066
2067                 /*
2068                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2069                  * for merlin (0xa20c/b20c 16:12
2070                  */
2071                 .xatten1Margin = {0x19, 0x19, 0x19},
2072                 .tempSlope = 70,
2073                 .voltSlope = 15,
2074                 /* spurChans spur channels in usual fbin coding format */
2075                 .spurChans = {0, 0, 0, 0, 0},
2076                 /* noiseFloorThreshch check if the register is per chain */
2077                 .noiseFloorThreshCh = {-1, 0, 0},
2078                 .ob = {3, 3, 3}, /* 3 chain */
2079                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2080                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2081                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2082                 .xpaBiasLvl = 0,
2083                 .txFrameToDataStart = 0x0e,
2084                 .txFrameToPaOn = 0x0e,
2085                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2086                 .antennaGain = 0,
2087                 .switchSettling = 0x2d,
2088                 .adcDesiredSize = -30,
2089                 .txEndToXpaOff = 0,
2090                 .txEndToRxOn = 0x2,
2091                 .txFrameToXpaOn = 0xe,
2092                 .thresh62 = 28,
2093                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2094                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2095                 .futureModal = {
2096                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2097                 },
2098         },
2099         .base_ext2 = {
2100                 .tempSlopeLow = 72,
2101                 .tempSlopeHigh = 105,
2102                 .xatten1DBLow = {0x10, 0x14, 0x10},
2103                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2104                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2105                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2106         },
2107         .calFreqPier5G = {
2108                 FREQ2FBIN(5180, 0),
2109                 FREQ2FBIN(5220, 0),
2110                 FREQ2FBIN(5320, 0),
2111                 FREQ2FBIN(5400, 0),
2112                 FREQ2FBIN(5500, 0),
2113                 FREQ2FBIN(5600, 0),
2114                 FREQ2FBIN(5700, 0),
2115                 FREQ2FBIN(5785, 0)
2116         },
2117         .calPierData5G = {
2118                 {
2119                         {0, 0, 0, 0, 0},
2120                         {0, 0, 0, 0, 0},
2121                         {0, 0, 0, 0, 0},
2122                         {0, 0, 0, 0, 0},
2123                         {0, 0, 0, 0, 0},
2124                         {0, 0, 0, 0, 0},
2125                         {0, 0, 0, 0, 0},
2126                         {0, 0, 0, 0, 0},
2127                 },
2128                 {
2129                         {0, 0, 0, 0, 0},
2130                         {0, 0, 0, 0, 0},
2131                         {0, 0, 0, 0, 0},
2132                         {0, 0, 0, 0, 0},
2133                         {0, 0, 0, 0, 0},
2134                         {0, 0, 0, 0, 0},
2135                         {0, 0, 0, 0, 0},
2136                         {0, 0, 0, 0, 0},
2137                 },
2138                 {
2139                         {0, 0, 0, 0, 0},
2140                         {0, 0, 0, 0, 0},
2141                         {0, 0, 0, 0, 0},
2142                         {0, 0, 0, 0, 0},
2143                         {0, 0, 0, 0, 0},
2144                         {0, 0, 0, 0, 0},
2145                         {0, 0, 0, 0, 0},
2146                         {0, 0, 0, 0, 0},
2147                 },
2148
2149         },
2150         .calTarget_freqbin_5G = {
2151                 FREQ2FBIN(5180, 0),
2152                 FREQ2FBIN(5220, 0),
2153                 FREQ2FBIN(5320, 0),
2154                 FREQ2FBIN(5400, 0),
2155                 FREQ2FBIN(5500, 0),
2156                 FREQ2FBIN(5600, 0),
2157                 FREQ2FBIN(5725, 0),
2158                 FREQ2FBIN(5825, 0)
2159         },
2160         .calTarget_freqbin_5GHT20 = {
2161                 FREQ2FBIN(5180, 0),
2162                 FREQ2FBIN(5220, 0),
2163                 FREQ2FBIN(5320, 0),
2164                 FREQ2FBIN(5400, 0),
2165                 FREQ2FBIN(5500, 0),
2166                 FREQ2FBIN(5600, 0),
2167                 FREQ2FBIN(5725, 0),
2168                 FREQ2FBIN(5825, 0)
2169         },
2170         .calTarget_freqbin_5GHT40 = {
2171                 FREQ2FBIN(5180, 0),
2172                 FREQ2FBIN(5220, 0),
2173                 FREQ2FBIN(5320, 0),
2174                 FREQ2FBIN(5400, 0),
2175                 FREQ2FBIN(5500, 0),
2176                 FREQ2FBIN(5600, 0),
2177                 FREQ2FBIN(5725, 0),
2178                 FREQ2FBIN(5825, 0)
2179         },
2180         .calTargetPower5G = {
2181                 /* 6-24,36,48,54 */
2182                 { {32, 32, 28, 26} },
2183                 { {32, 32, 28, 26} },
2184                 { {32, 32, 28, 26} },
2185                 { {32, 32, 26, 24} },
2186                 { {32, 32, 26, 24} },
2187                 { {32, 32, 24, 22} },
2188                 { {30, 30, 24, 22} },
2189                 { {30, 30, 24, 22} },
2190         },
2191         .calTargetPower5GHT20 = {
2192                 /*
2193                  * 0_8_16,1-3_9-11_17-19,
2194                  * 4,5,6,7,12,13,14,15,20,21,22,23
2195                  */
2196                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2197                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2198                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2199                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2200                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2201                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2202                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2203                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2204         },
2205         .calTargetPower5GHT40 =  {
2206                 /*
2207                  * 0_8_16,1-3_9-11_17-19,
2208                  * 4,5,6,7,12,13,14,15,20,21,22,23
2209                  */
2210                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2211                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2212                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2213                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2214                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2215                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2216                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2217                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2218         },
2219         .ctlIndex_5G =  {
2220                 0x10, 0x16, 0x18, 0x40, 0x46,
2221                 0x48, 0x30, 0x36, 0x38
2222         },
2223         .ctl_freqbin_5G =  {
2224                 {
2225                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2226                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2227                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2228                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2229                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2230                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2231                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2232                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2233                 },
2234                 {
2235                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2236                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2237                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2238                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2239                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2240                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2241                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2242                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2243                 },
2244
2245                 {
2246                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2247                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2248                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2249                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2250                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2251                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2252                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2253                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2254                 },
2255
2256                 {
2257                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2258                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2259                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2260                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2261                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2262                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2263                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2264                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2265                 },
2266
2267                 {
2268                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2269                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2270                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2271                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2272                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2273                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2274                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2275                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2276                 },
2277
2278                 {
2279                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2280                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2281                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2282                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2283                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2284                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2285                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2286                         /* Data[5].ctledges[7].bchannel */ 0xFF
2287                 },
2288
2289                 {
2290                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2291                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2292                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2293                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2294                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2295                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2296                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2297                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2298                 },
2299
2300                 {
2301                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2302                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2303                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2304                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2305                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2306                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2307                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2308                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2309                 },
2310
2311                 {
2312                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2313                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2314                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2315                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2316                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2317                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2318                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2319                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2320                 }
2321         },
2322         .ctlPowerData_5G = {
2323                 {
2324                         {
2325                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2326                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2327                         }
2328                 },
2329                 {
2330                         {
2331                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2332                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2333                         }
2334                 },
2335                 {
2336                         {
2337                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2338                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2339                         }
2340                 },
2341                 {
2342                         {
2343                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2344                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2345                         }
2346                 },
2347                 {
2348                         {
2349                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2350                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2351                         }
2352                 },
2353                 {
2354                         {
2355                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2356                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2357                         }
2358                 },
2359                 {
2360                         {
2361                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2362                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2363                         }
2364                 },
2365                 {
2366                         {
2367                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2368                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2369                         }
2370                 },
2371                 {
2372                         {
2373                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2374                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2375                         }
2376                 },
2377         }
2378 };
2379
2380 static const struct ar9300_eeprom ar9300_h116 = {
2381         .eepromVersion = 2,
2382         .templateVersion = 4,
2383         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2384         .custData = {"h116-041-f0000"},
2385         .baseEepHeader = {
2386                 .regDmn = { LE16(0), LE16(0x1f) },
2387                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2388                 .opCapFlags = {
2389                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2390                         .eepMisc = 0,
2391                 },
2392                 .rfSilent = 0,
2393                 .blueToothOptions = 0,
2394                 .deviceCap = 0,
2395                 .deviceType = 5, /* takes lower byte in eeprom location */
2396                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2397                 .params_for_tuning_caps = {0, 0},
2398                 .featureEnable = 0x0d,
2399                  /*
2400                   * bit0 - enable tx temp comp - disabled
2401                   * bit1 - enable tx volt comp - disabled
2402                   * bit2 - enable fastClock - enabled
2403                   * bit3 - enable doubling - enabled
2404                   * bit4 - enable internal regulator - disabled
2405                   * bit5 - enable pa predistortion - disabled
2406                   */
2407                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2408                 .eepromWriteEnableGpio = 6,
2409                 .wlanDisableGpio = 0,
2410                 .wlanLedGpio = 8,
2411                 .rxBandSelectGpio = 0xff,
2412                 .txrxgain = 0x10,
2413                 .swreg = 0,
2414          },
2415         .modalHeader2G = {
2416         /* ar9300_modal_eep_header  2g */
2417                 /* 4 idle,t1,t2,b(4 bits per setting) */
2418                 .antCtrlCommon = LE32(0x110),
2419                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2420                 .antCtrlCommon2 = LE32(0x44444),
2421
2422                 /*
2423                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2424                  * rx1, rx12, b (2 bits each)
2425                  */
2426                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2427
2428                 /*
2429                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2430                  * for ar9280 (0xa20c/b20c 5:0)
2431                  */
2432                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2433
2434                 /*
2435                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2436                  * for ar9280 (0xa20c/b20c 16:12
2437                  */
2438                 .xatten1Margin = {0x12, 0x12, 0x12},
2439                 .tempSlope = 25,
2440                 .voltSlope = 0,
2441
2442                 /*
2443                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2444                  * channels in usual fbin coding format
2445                  */
2446                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2447
2448                 /*
2449                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2450                  * if the register is per chain
2451                  */
2452                 .noiseFloorThreshCh = {-1, 0, 0},
2453                 .ob = {1, 1, 1},/* 3 chain */
2454                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
2455                 .db_stage3 = {0, 0, 0},
2456                 .db_stage4 = {0, 0, 0},
2457                 .xpaBiasLvl = 0,
2458                 .txFrameToDataStart = 0x0e,
2459                 .txFrameToPaOn = 0x0e,
2460                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2461                 .antennaGain = 0,
2462                 .switchSettling = 0x2c,
2463                 .adcDesiredSize = -30,
2464                 .txEndToXpaOff = 0,
2465                 .txEndToRxOn = 0x2,
2466                 .txFrameToXpaOn = 0xe,
2467                 .thresh62 = 28,
2468                 .papdRateMaskHt20 = LE32(0x0c80C080),
2469                 .papdRateMaskHt40 = LE32(0x0080C080),
2470                 .futureModal = {
2471                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2472                 },
2473          },
2474          .base_ext1 = {
2475                 .ant_div_control = 0,
2476                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2477          },
2478         .calFreqPier2G = {
2479                 FREQ2FBIN(2412, 1),
2480                 FREQ2FBIN(2437, 1),
2481                 FREQ2FBIN(2472, 1),
2482          },
2483         /* ar9300_cal_data_per_freq_op_loop 2g */
2484         .calPierData2G = {
2485                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2486                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2487                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2488          },
2489         .calTarget_freqbin_Cck = {
2490                 FREQ2FBIN(2412, 1),
2491                 FREQ2FBIN(2472, 1),
2492          },
2493         .calTarget_freqbin_2G = {
2494                 FREQ2FBIN(2412, 1),
2495                 FREQ2FBIN(2437, 1),
2496                 FREQ2FBIN(2472, 1)
2497          },
2498         .calTarget_freqbin_2GHT20 = {
2499                 FREQ2FBIN(2412, 1),
2500                 FREQ2FBIN(2437, 1),
2501                 FREQ2FBIN(2472, 1)
2502          },
2503         .calTarget_freqbin_2GHT40 = {
2504                 FREQ2FBIN(2412, 1),
2505                 FREQ2FBIN(2437, 1),
2506                 FREQ2FBIN(2472, 1)
2507          },
2508         .calTargetPowerCck = {
2509                  /* 1L-5L,5S,11L,11S */
2510                  { {34, 34, 34, 34} },
2511                  { {34, 34, 34, 34} },
2512         },
2513         .calTargetPower2G = {
2514                  /* 6-24,36,48,54 */
2515                  { {34, 34, 32, 32} },
2516                  { {34, 34, 32, 32} },
2517                  { {34, 34, 32, 32} },
2518         },
2519         .calTargetPower2GHT20 = {
2520                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2521                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2522                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2523         },
2524         .calTargetPower2GHT40 = {
2525                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2526                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2527                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2528         },
2529         .ctlIndex_2G =  {
2530                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2531                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2532         },
2533         .ctl_freqbin_2G = {
2534                 {
2535                         FREQ2FBIN(2412, 1),
2536                         FREQ2FBIN(2417, 1),
2537                         FREQ2FBIN(2457, 1),
2538                         FREQ2FBIN(2462, 1)
2539                 },
2540                 {
2541                         FREQ2FBIN(2412, 1),
2542                         FREQ2FBIN(2417, 1),
2543                         FREQ2FBIN(2462, 1),
2544                         0xFF,
2545                 },
2546
2547                 {
2548                         FREQ2FBIN(2412, 1),
2549                         FREQ2FBIN(2417, 1),
2550                         FREQ2FBIN(2462, 1),
2551                         0xFF,
2552                 },
2553                 {
2554                         FREQ2FBIN(2422, 1),
2555                         FREQ2FBIN(2427, 1),
2556                         FREQ2FBIN(2447, 1),
2557                         FREQ2FBIN(2452, 1)
2558                 },
2559
2560                 {
2561                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2565                 },
2566
2567                 {
2568                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2571                         0,
2572                 },
2573
2574                 {
2575                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2576                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2577                         FREQ2FBIN(2472, 1),
2578                         0,
2579                 },
2580
2581                 {
2582                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2583                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2584                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2585                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2586                 },
2587
2588                 {
2589                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2590                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2591                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2592                 },
2593
2594                 {
2595                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2598                         0
2599                 },
2600
2601                 {
2602                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2603                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2604                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2605                         0
2606                 },
2607
2608                 {
2609                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2610                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2611                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2612                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2613                 }
2614          },
2615         .ctlPowerData_2G = {
2616                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2617                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2618                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2619
2620                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2621                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2622                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2623
2624                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2625                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2626                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2627
2628                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2629                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2630                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2631          },
2632         .modalHeader5G = {
2633                 /* 4 idle,t1,t2,b (4 bits per setting) */
2634                 .antCtrlCommon = LE32(0x220),
2635                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2636                 .antCtrlCommon2 = LE32(0x44444),
2637                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2638                 .antCtrlChain = {
2639                         LE16(0x150), LE16(0x150), LE16(0x150),
2640                 },
2641                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2642                 .xatten1DB = {0x19, 0x19, 0x19},
2643
2644                 /*
2645                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2646                  * for merlin (0xa20c/b20c 16:12
2647                  */
2648                 .xatten1Margin = {0x14, 0x14, 0x14},
2649                 .tempSlope = 70,
2650                 .voltSlope = 0,
2651                 /* spurChans spur channels in usual fbin coding format */
2652                 .spurChans = {0, 0, 0, 0, 0},
2653                 /* noiseFloorThreshCh Check if the register is per chain */
2654                 .noiseFloorThreshCh = {-1, 0, 0},
2655                 .ob = {3, 3, 3}, /* 3 chain */
2656                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2657                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2658                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2659                 .xpaBiasLvl = 0,
2660                 .txFrameToDataStart = 0x0e,
2661                 .txFrameToPaOn = 0x0e,
2662                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2663                 .antennaGain = 0,
2664                 .switchSettling = 0x2d,
2665                 .adcDesiredSize = -30,
2666                 .txEndToXpaOff = 0,
2667                 .txEndToRxOn = 0x2,
2668                 .txFrameToXpaOn = 0xe,
2669                 .thresh62 = 28,
2670                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2671                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2672                 .futureModal = {
2673                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2674                 },
2675          },
2676         .base_ext2 = {
2677                 .tempSlopeLow = 35,
2678                 .tempSlopeHigh = 50,
2679                 .xatten1DBLow = {0, 0, 0},
2680                 .xatten1MarginLow = {0, 0, 0},
2681                 .xatten1DBHigh = {0, 0, 0},
2682                 .xatten1MarginHigh = {0, 0, 0}
2683          },
2684         .calFreqPier5G = {
2685                 FREQ2FBIN(5180, 0),
2686                 FREQ2FBIN(5220, 0),
2687                 FREQ2FBIN(5320, 0),
2688                 FREQ2FBIN(5400, 0),
2689                 FREQ2FBIN(5500, 0),
2690                 FREQ2FBIN(5600, 0),
2691                 FREQ2FBIN(5700, 0),
2692                 FREQ2FBIN(5785, 0)
2693         },
2694         .calPierData5G = {
2695                         {
2696                                 {0, 0, 0, 0, 0},
2697                                 {0, 0, 0, 0, 0},
2698                                 {0, 0, 0, 0, 0},
2699                                 {0, 0, 0, 0, 0},
2700                                 {0, 0, 0, 0, 0},
2701                                 {0, 0, 0, 0, 0},
2702                                 {0, 0, 0, 0, 0},
2703                                 {0, 0, 0, 0, 0},
2704                         },
2705                         {
2706                                 {0, 0, 0, 0, 0},
2707                                 {0, 0, 0, 0, 0},
2708                                 {0, 0, 0, 0, 0},
2709                                 {0, 0, 0, 0, 0},
2710                                 {0, 0, 0, 0, 0},
2711                                 {0, 0, 0, 0, 0},
2712                                 {0, 0, 0, 0, 0},
2713                                 {0, 0, 0, 0, 0},
2714                         },
2715                         {
2716                                 {0, 0, 0, 0, 0},
2717                                 {0, 0, 0, 0, 0},
2718                                 {0, 0, 0, 0, 0},
2719                                 {0, 0, 0, 0, 0},
2720                                 {0, 0, 0, 0, 0},
2721                                 {0, 0, 0, 0, 0},
2722                                 {0, 0, 0, 0, 0},
2723                                 {0, 0, 0, 0, 0},
2724                         },
2725
2726         },
2727         .calTarget_freqbin_5G = {
2728                 FREQ2FBIN(5180, 0),
2729                 FREQ2FBIN(5240, 0),
2730                 FREQ2FBIN(5320, 0),
2731                 FREQ2FBIN(5400, 0),
2732                 FREQ2FBIN(5500, 0),
2733                 FREQ2FBIN(5600, 0),
2734                 FREQ2FBIN(5700, 0),
2735                 FREQ2FBIN(5825, 0)
2736         },
2737         .calTarget_freqbin_5GHT20 = {
2738                 FREQ2FBIN(5180, 0),
2739                 FREQ2FBIN(5240, 0),
2740                 FREQ2FBIN(5320, 0),
2741                 FREQ2FBIN(5400, 0),
2742                 FREQ2FBIN(5500, 0),
2743                 FREQ2FBIN(5700, 0),
2744                 FREQ2FBIN(5745, 0),
2745                 FREQ2FBIN(5825, 0)
2746         },
2747         .calTarget_freqbin_5GHT40 = {
2748                 FREQ2FBIN(5180, 0),
2749                 FREQ2FBIN(5240, 0),
2750                 FREQ2FBIN(5320, 0),
2751                 FREQ2FBIN(5400, 0),
2752                 FREQ2FBIN(5500, 0),
2753                 FREQ2FBIN(5700, 0),
2754                 FREQ2FBIN(5745, 0),
2755                 FREQ2FBIN(5825, 0)
2756          },
2757         .calTargetPower5G = {
2758                 /* 6-24,36,48,54 */
2759                 { {30, 30, 28, 24} },
2760                 { {30, 30, 28, 24} },
2761                 { {30, 30, 28, 24} },
2762                 { {30, 30, 28, 24} },
2763                 { {30, 30, 28, 24} },
2764                 { {30, 30, 28, 24} },
2765                 { {30, 30, 28, 24} },
2766                 { {30, 30, 28, 24} },
2767          },
2768         .calTargetPower5GHT20 = {
2769                 /*
2770                  * 0_8_16,1-3_9-11_17-19,
2771                  * 4,5,6,7,12,13,14,15,20,21,22,23
2772                  */
2773                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2774                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2775                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2776                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2777                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2778                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2779                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2780                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2781          },
2782         .calTargetPower5GHT40 =  {
2783                 /*
2784                  * 0_8_16,1-3_9-11_17-19,
2785                  * 4,5,6,7,12,13,14,15,20,21,22,23
2786                  */
2787                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2788                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2789                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2790                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2791                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2792                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2793                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2794                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2795          },
2796         .ctlIndex_5G =  {
2797                 0x10, 0x16, 0x18, 0x40, 0x46,
2798                 0x48, 0x30, 0x36, 0x38
2799         },
2800         .ctl_freqbin_5G =  {
2801                 {
2802                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2803                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2804                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2805                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2806                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2807                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2808                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2809                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2810                 },
2811                 {
2812                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2813                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2814                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2815                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2816                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2817                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2818                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2819                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2820                 },
2821
2822                 {
2823                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2824                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2825                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2826                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2827                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2828                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2829                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2830                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2831                 },
2832
2833                 {
2834                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2836                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2837                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2838                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2839                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2841                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2842                 },
2843
2844                 {
2845                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2846                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2847                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2848                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2849                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2850                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2851                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2852                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2853                 },
2854
2855                 {
2856                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2857                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2858                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2859                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2860                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2861                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2862                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2863                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2864                 },
2865
2866                 {
2867                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2868                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2869                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2870                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2871                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2872                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2873                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2874                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2875                 },
2876
2877                 {
2878                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2879                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2880                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2881                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2882                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2883                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2884                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2885                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2886                 },
2887
2888                 {
2889                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2890                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2891                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2892                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2893                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2894                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2895                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2896                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2897                 }
2898          },
2899         .ctlPowerData_5G = {
2900                 {
2901                         {
2902                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2903                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2904                         }
2905                 },
2906                 {
2907                         {
2908                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2909                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2910                         }
2911                 },
2912                 {
2913                         {
2914                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2915                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2916                         }
2917                 },
2918                 {
2919                         {
2920                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2921                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2922                         }
2923                 },
2924                 {
2925                         {
2926                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2927                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2928                         }
2929                 },
2930                 {
2931                         {
2932                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2933                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2934                         }
2935                 },
2936                 {
2937                         {
2938                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2939                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2940                         }
2941                 },
2942                 {
2943                         {
2944                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2945                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2946                         }
2947                 },
2948                 {
2949                         {
2950                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2951                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2952                         }
2953                 },
2954          }
2955 };
2956
2957
2958 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2959         &ar9300_default,
2960         &ar9300_x112,
2961         &ar9300_h116,
2962         &ar9300_h112,
2963         &ar9300_x113,
2964 };
2965
2966 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2967 {
2968 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2969         int it;
2970
2971         for (it = 0; it < N_LOOP; it++)
2972                 if (ar9300_eep_templates[it]->templateVersion == id)
2973                         return ar9300_eep_templates[it];
2974         return NULL;
2975 #undef N_LOOP
2976 }
2977
2978
2979 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2980 {
2981         if (fbin == AR5416_BCHAN_UNUSED)
2982                 return fbin;
2983
2984         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2985 }
2986
2987 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2988 {
2989         return 0;
2990 }
2991
2992 static int interpolate(int x, int xa, int xb, int ya, int yb)
2993 {
2994         int bf, factor, plus;
2995
2996         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2997         factor = bf / 2;
2998         plus = bf % 2;
2999         return ya + factor + plus;
3000 }
3001
3002 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3003                                       enum eeprom_param param)
3004 {
3005         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3006         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3007
3008         switch (param) {
3009         case EEP_MAC_LSW:
3010                 return get_unaligned_be16(eep->macAddr);
3011         case EEP_MAC_MID:
3012                 return get_unaligned_be16(eep->macAddr + 2);
3013         case EEP_MAC_MSW:
3014                 return get_unaligned_be16(eep->macAddr + 4);
3015         case EEP_REG_0:
3016                 return le16_to_cpu(pBase->regDmn[0]);
3017         case EEP_REG_1:
3018                 return le16_to_cpu(pBase->regDmn[1]);
3019         case EEP_OP_CAP:
3020                 return pBase->deviceCap;
3021         case EEP_OP_MODE:
3022                 return pBase->opCapFlags.opFlags;
3023         case EEP_RF_SILENT:
3024                 return pBase->rfSilent;
3025         case EEP_TX_MASK:
3026                 return (pBase->txrxMask >> 4) & 0xf;
3027         case EEP_RX_MASK:
3028                 return pBase->txrxMask & 0xf;
3029         case EEP_DRIVE_STRENGTH:
3030 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
3031                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3032         case EEP_INTERNAL_REGULATOR:
3033                 /* Bit 4 is internal regulator flag */
3034                 return (pBase->featureEnable & 0x10) >> 4;
3035         case EEP_SWREG:
3036                 return le32_to_cpu(pBase->swreg);
3037         case EEP_PAPRD:
3038                 return !!(pBase->featureEnable & BIT(5));
3039         case EEP_CHAIN_MASK_REDUCE:
3040                 return (pBase->miscConfiguration >> 0x3) & 0x1;
3041         case EEP_ANT_DIV_CTL1:
3042                 return eep->base_ext1.ant_div_control;
3043         default:
3044                 return 0;
3045         }
3046 }
3047
3048 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3049                                     u8 *buffer)
3050 {
3051         u16 val;
3052
3053         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3054                 return false;
3055
3056         *buffer = (val >> (8 * (address % 2))) & 0xff;
3057         return true;
3058 }
3059
3060 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3061                                     u8 *buffer)
3062 {
3063         u16 val;
3064
3065         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3066                 return false;
3067
3068         buffer[0] = val >> 8;
3069         buffer[1] = val & 0xff;
3070
3071         return true;
3072 }
3073
3074 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3075                                int count)
3076 {
3077         struct ath_common *common = ath9k_hw_common(ah);
3078         int i;
3079
3080         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3081                 ath_dbg(common, ATH_DBG_EEPROM,
3082                         "eeprom address not in range\n");
3083                 return false;
3084         }
3085
3086         /*
3087          * Since we're reading the bytes in reverse order from a little-endian
3088          * word stream, an even address means we only use the lower half of
3089          * the 16-bit word at that address
3090          */
3091         if (address % 2 == 0) {
3092                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3093                         goto error;
3094
3095                 count--;
3096         }
3097
3098         for (i = 0; i < count / 2; i++) {
3099                 if (!ar9300_eeprom_read_word(common, address, buffer))
3100                         goto error;
3101
3102                 address -= 2;
3103                 buffer += 2;
3104         }
3105
3106         if (count % 2)
3107                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3108                         goto error;
3109
3110         return true;
3111
3112 error:
3113         ath_dbg(common, ATH_DBG_EEPROM,
3114                 "unable to read eeprom region at offset %d\n", address);
3115         return false;
3116 }
3117
3118 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3119 {
3120         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3121
3122         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3123                            AR9300_OTP_STATUS_VALID, 1000))
3124                 return false;
3125
3126         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3127         return true;
3128 }
3129
3130 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3131                             int count)
3132 {
3133         u32 data;
3134         int i;
3135
3136         for (i = 0; i < count; i++) {
3137                 int offset = 8 * ((address - i) % 4);
3138                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3139                         return false;
3140
3141                 buffer[i] = (data >> offset) & 0xff;
3142         }
3143
3144         return true;
3145 }
3146
3147
3148 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3149                                    int *length, int *major, int *minor)
3150 {
3151         unsigned long value[4];
3152
3153         value[0] = best[0];
3154         value[1] = best[1];
3155         value[2] = best[2];
3156         value[3] = best[3];
3157         *code = ((value[0] >> 5) & 0x0007);
3158         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3159         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3160         *major = (value[2] & 0x000f);
3161         *minor = (value[3] & 0x00ff);
3162 }
3163
3164 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3165 {
3166         int it, checksum = 0;
3167
3168         for (it = 0; it < dsize; it++) {
3169                 checksum += data[it];
3170                 checksum &= 0xffff;
3171         }
3172
3173         return checksum;
3174 }
3175
3176 static bool ar9300_uncompress_block(struct ath_hw *ah,
3177                                     u8 *mptr,
3178                                     int mdataSize,
3179                                     u8 *block,
3180                                     int size)
3181 {
3182         int it;
3183         int spot;
3184         int offset;
3185         int length;
3186         struct ath_common *common = ath9k_hw_common(ah);
3187
3188         spot = 0;
3189
3190         for (it = 0; it < size; it += (length+2)) {
3191                 offset = block[it];
3192                 offset &= 0xff;
3193                 spot += offset;
3194                 length = block[it+1];
3195                 length &= 0xff;
3196
3197                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3198                         ath_dbg(common, ATH_DBG_EEPROM,
3199                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3200                                 it, spot, offset, length);
3201                         memcpy(&mptr[spot], &block[it+2], length);
3202                         spot += length;
3203                 } else if (length > 0) {
3204                         ath_dbg(common, ATH_DBG_EEPROM,
3205                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3206                                 it, spot, offset, length);
3207                         return false;
3208                 }
3209         }
3210         return true;
3211 }
3212
3213 static int ar9300_compress_decision(struct ath_hw *ah,
3214                                     int it,
3215                                     int code,
3216                                     int reference,
3217                                     u8 *mptr,
3218                                     u8 *word, int length, int mdata_size)
3219 {
3220         struct ath_common *common = ath9k_hw_common(ah);
3221         const struct ar9300_eeprom *eep = NULL;
3222
3223         switch (code) {
3224         case _CompressNone:
3225                 if (length != mdata_size) {
3226                         ath_dbg(common, ATH_DBG_EEPROM,
3227                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3228                                 mdata_size, length);
3229                         return -1;
3230                 }
3231                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3232                 ath_dbg(common, ATH_DBG_EEPROM,
3233                         "restored eeprom %d: uncompressed, length %d\n",
3234                         it, length);
3235                 break;
3236         case _CompressBlock:
3237                 if (reference == 0) {
3238                 } else {
3239                         eep = ar9003_eeprom_struct_find_by_id(reference);
3240                         if (eep == NULL) {
3241                                 ath_dbg(common, ATH_DBG_EEPROM,
3242                                         "can't find reference eeprom struct %d\n",
3243                                         reference);
3244                                 return -1;
3245                         }
3246                         memcpy(mptr, eep, mdata_size);
3247                 }
3248                 ath_dbg(common, ATH_DBG_EEPROM,
3249                         "restore eeprom %d: block, reference %d, length %d\n",
3250                         it, reference, length);
3251                 ar9300_uncompress_block(ah, mptr, mdata_size,
3252                                         (u8 *) (word + COMP_HDR_LEN), length);
3253                 break;
3254         default:
3255                 ath_dbg(common, ATH_DBG_EEPROM,
3256                         "unknown compression code %d\n", code);
3257                 return -1;
3258         }
3259         return 0;
3260 }
3261
3262 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3263                                int count);
3264
3265 static bool ar9300_check_header(void *data)
3266 {
3267         u32 *word = data;
3268         return !(*word == 0 || *word == ~0);
3269 }
3270
3271 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3272                                        int base_addr)
3273 {
3274         u8 header[4];
3275
3276         if (!read(ah, base_addr, header, 4))
3277                 return false;
3278
3279         return ar9300_check_header(header);
3280 }
3281
3282 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3283                                        int mdata_size)
3284 {
3285         struct ath_common *common = ath9k_hw_common(ah);
3286         u16 *data = (u16 *) mptr;
3287         int i;
3288
3289         for (i = 0; i < mdata_size / 2; i++, data++)
3290                 ath9k_hw_nvram_read(common, i, data);
3291
3292         return 0;
3293 }
3294 /*
3295  * Read the configuration data from the eeprom.
3296  * The data can be put in any specified memory buffer.
3297  *
3298  * Returns -1 on error.
3299  * Returns address of next memory location on success.
3300  */
3301 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3302                                           u8 *mptr, int mdata_size)
3303 {
3304 #define MDEFAULT 15
3305 #define MSTATE 100
3306         int cptr;
3307         u8 *word;
3308         int code;
3309         int reference, length, major, minor;
3310         int osize;
3311         int it;
3312         u16 checksum, mchecksum;
3313         struct ath_common *common = ath9k_hw_common(ah);
3314         eeprom_read_op read;
3315
3316         if (ath9k_hw_use_flash(ah))
3317                 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3318
3319         word = kzalloc(2048, GFP_KERNEL);
3320         if (!word)
3321                 return -ENOMEM;
3322
3323         memcpy(mptr, &ar9300_default, mdata_size);
3324
3325         read = ar9300_read_eeprom;
3326         if (AR_SREV_9485(ah))
3327                 cptr = AR9300_BASE_ADDR_4K;
3328         else if (AR_SREV_9330(ah))
3329                 cptr = AR9300_BASE_ADDR_512;
3330         else
3331                 cptr = AR9300_BASE_ADDR;
3332         ath_dbg(common, ATH_DBG_EEPROM,
3333                 "Trying EEPROM access at Address 0x%04x\n", cptr);
3334         if (ar9300_check_eeprom_header(ah, read, cptr))
3335                 goto found;
3336
3337         cptr = AR9300_BASE_ADDR_512;
3338         ath_dbg(common, ATH_DBG_EEPROM,
3339                 "Trying EEPROM access at Address 0x%04x\n", cptr);
3340         if (ar9300_check_eeprom_header(ah, read, cptr))
3341                 goto found;
3342
3343         read = ar9300_read_otp;
3344         cptr = AR9300_BASE_ADDR;
3345         ath_dbg(common, ATH_DBG_EEPROM,
3346                 "Trying OTP access at Address 0x%04x\n", cptr);
3347         if (ar9300_check_eeprom_header(ah, read, cptr))
3348                 goto found;
3349
3350         cptr = AR9300_BASE_ADDR_512;
3351         ath_dbg(common, ATH_DBG_EEPROM,
3352                 "Trying OTP access at Address 0x%04x\n", cptr);
3353         if (ar9300_check_eeprom_header(ah, read, cptr))
3354                 goto found;
3355
3356         goto fail;
3357
3358 found:
3359         ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
3360
3361         for (it = 0; it < MSTATE; it++) {
3362                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3363                         goto fail;
3364
3365                 if (!ar9300_check_header(word))
3366                         break;
3367
3368                 ar9300_comp_hdr_unpack(word, &code, &reference,
3369                                        &length, &major, &minor);
3370                 ath_dbg(common, ATH_DBG_EEPROM,
3371                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3372                         cptr, code, reference, length, major, minor);
3373                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3374                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3375                         ath_dbg(common, ATH_DBG_EEPROM,
3376                                 "Skipping bad header\n");
3377                         cptr -= COMP_HDR_LEN;
3378                         continue;
3379                 }
3380
3381                 osize = length;
3382                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3383                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3384                 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3385                 ath_dbg(common, ATH_DBG_EEPROM,
3386                         "checksum %x %x\n", checksum, mchecksum);
3387                 if (checksum == mchecksum) {
3388                         ar9300_compress_decision(ah, it, code, reference, mptr,
3389                                                  word, length, mdata_size);
3390                 } else {
3391                         ath_dbg(common, ATH_DBG_EEPROM,
3392                                 "skipping block with bad checksum\n");
3393                 }
3394                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3395         }
3396
3397         kfree(word);
3398         return cptr;
3399
3400 fail:
3401         kfree(word);
3402         return -1;
3403 }
3404
3405 /*
3406  * Restore the configuration structure by reading the eeprom.
3407  * This function destroys any existing in-memory structure
3408  * content.
3409  */
3410 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3411 {
3412         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3413
3414         if (ar9300_eeprom_restore_internal(ah, mptr,
3415                         sizeof(struct ar9300_eeprom)) < 0)
3416                 return false;
3417
3418         return true;
3419 }
3420
3421 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3422 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3423                                     struct ar9300_modal_eep_header *modal_hdr)
3424 {
3425         PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3426         PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3427         PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3428         PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3429         PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3430         PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3431         PR_EEP("Switch Settle", modal_hdr->switchSettling);
3432         PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3433         PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3434         PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3435         PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3436         PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3437         PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3438         PR_EEP("Temp Slope", modal_hdr->tempSlope);
3439         PR_EEP("Volt Slope", modal_hdr->voltSlope);
3440         PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3441         PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3442         PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3443         PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3444         PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3445         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3446         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3447         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3448         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3449         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3450         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3451         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3452         PR_EEP("txClip", modal_hdr->txClip);
3453         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3454         PR_EEP("Chain0 ob", modal_hdr->ob[0]);
3455         PR_EEP("Chain1 ob", modal_hdr->ob[1]);
3456         PR_EEP("Chain2 ob", modal_hdr->ob[2]);
3457
3458         PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]);
3459         PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]);
3460         PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]);
3461         PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]);
3462         PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]);
3463         PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]);
3464         PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]);
3465         PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]);
3466         PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]);
3467
3468         return len;
3469 }
3470
3471 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3472                                        u8 *buf, u32 len, u32 size)
3473 {
3474         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3475         struct ar9300_base_eep_hdr *pBase;
3476
3477         if (!dump_base_hdr) {
3478                 len += snprintf(buf + len, size - len,
3479                                 "%20s :\n", "2GHz modal Header");
3480                 len += ar9003_dump_modal_eeprom(buf, len, size,
3481                                                 &eep->modalHeader2G);
3482                 len += snprintf(buf + len, size - len,
3483                                 "%20s :\n", "5GHz modal Header");
3484                 len += ar9003_dump_modal_eeprom(buf, len, size,
3485                                                 &eep->modalHeader5G);
3486                 goto out;
3487         }
3488
3489         pBase = &eep->baseEepHeader;
3490
3491         PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3492         PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3493         PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3494         PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3495         PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3496         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3497                                 AR5416_OPFLAGS_11A));
3498         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3499                                 AR5416_OPFLAGS_11G));
3500         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3501                                         AR5416_OPFLAGS_N_2G_HT20));
3502         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3503                                         AR5416_OPFLAGS_N_2G_HT40));
3504         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3505                                         AR5416_OPFLAGS_N_5G_HT20));
3506         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3507                                         AR5416_OPFLAGS_N_5G_HT40));
3508         PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3509         PR_EEP("RF Silent", pBase->rfSilent);
3510         PR_EEP("BT option", pBase->blueToothOptions);
3511         PR_EEP("Device Cap", pBase->deviceCap);
3512         PR_EEP("Device Type", pBase->deviceType);
3513         PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3514         PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3515         PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3516         PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3517         PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3518         PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3519         PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3520         PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3521         PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3522         PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3523         PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3524         PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3525         PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3526         PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3527         PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3528         PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3529         PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3530         PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3531
3532         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3533                         ah->eeprom.ar9300_eep.macAddr);
3534 out:
3535         if (len > size)
3536                 len = size;
3537
3538         return len;
3539 }
3540 #else
3541 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3542                                        u8 *buf, u32 len, u32 size)
3543 {
3544         return 0;
3545 }
3546 #endif
3547
3548 /* XXX: review hardware docs */
3549 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3550 {
3551         return ah->eeprom.ar9300_eep.eepromVersion;
3552 }
3553
3554 /* XXX: could be read from the eepromVersion, not sure yet */
3555 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3556 {
3557         return 0;
3558 }
3559
3560 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3561 {
3562         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3563
3564         if (is2ghz)
3565                 return eep->modalHeader2G.xpaBiasLvl;
3566         else
3567                 return eep->modalHeader5G.xpaBiasLvl;
3568 }
3569
3570 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3571 {
3572         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3573
3574         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3575                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3576         else {
3577                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3578                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3579                                 AR_CH0_THERM_XPABIASLVL_MSB,
3580                                 bias >> 2);
3581                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3582                                 AR_CH0_THERM_XPASHORT2GND, 1);
3583         }
3584 }
3585
3586 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3587 {
3588         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3589         __le32 val;
3590
3591         if (is2ghz)
3592                 val = eep->modalHeader2G.antCtrlCommon;
3593         else
3594                 val = eep->modalHeader5G.antCtrlCommon;
3595         return le32_to_cpu(val);
3596 }
3597
3598 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3599 {
3600         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3601         __le32 val;
3602
3603         if (is2ghz)
3604                 val = eep->modalHeader2G.antCtrlCommon2;
3605         else
3606                 val = eep->modalHeader5G.antCtrlCommon2;
3607         return le32_to_cpu(val);
3608 }
3609
3610 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3611                                         int chain,
3612                                         bool is2ghz)
3613 {
3614         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3615         __le16 val = 0;
3616
3617         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3618                 if (is2ghz)
3619                         val = eep->modalHeader2G.antCtrlChain[chain];
3620                 else
3621                         val = eep->modalHeader5G.antCtrlChain[chain];
3622         }
3623
3624         return le16_to_cpu(val);
3625 }
3626
3627 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3628 {
3629         int chain;
3630         u32 regval;
3631         u32 ant_div_ctl1;
3632         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3633                         AR_PHY_SWITCH_CHAIN_0,
3634                         AR_PHY_SWITCH_CHAIN_1,
3635                         AR_PHY_SWITCH_CHAIN_2,
3636         };
3637
3638         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3639
3640         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3641
3642         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3643         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3644
3645         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3646                 if ((ah->rxchainmask & BIT(chain)) ||
3647                     (ah->txchainmask & BIT(chain))) {
3648                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3649                                                              is2ghz);
3650                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3651                                       AR_SWITCH_TABLE_ALL, value);
3652                 }
3653         }
3654
3655         if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3656                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3657                 /*
3658                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3659                  * are the fields present
3660                  */
3661                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3662                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3663                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3664                 /* enable_lnadiv */
3665                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3666                 regval |= ((value >> 6) & 0x1) <<
3667                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3668                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3669
3670                 /*enable fast_div */
3671                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3672                 regval &= (~AR_FAST_DIV_ENABLE);
3673                 regval |= ((value >> 7) & 0x1) <<
3674                                 AR_FAST_DIV_ENABLE_S;
3675                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3676                 ant_div_ctl1 =
3677                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3678                 /* check whether antenna diversity is enabled */
3679                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3680                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3681                         /*
3682                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3683                          * main_tb, alt_tb
3684                          */
3685                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3686                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3687                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3688                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3689                         /* by default use LNA1 for the main antenna */
3690                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3691                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3692                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3693                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3694                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3695                 }
3696
3697
3698         }
3699
3700 }
3701
3702 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3703 {
3704         int drive_strength;
3705         unsigned long reg;
3706
3707         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3708
3709         if (!drive_strength)
3710                 return;
3711
3712         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3713         reg &= ~0x00ffffc0;
3714         reg |= 0x5 << 21;
3715         reg |= 0x5 << 18;
3716         reg |= 0x5 << 15;
3717         reg |= 0x5 << 12;
3718         reg |= 0x5 << 9;
3719         reg |= 0x5 << 6;
3720         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3721
3722         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3723         reg &= ~0xffffffe0;
3724         reg |= 0x5 << 29;
3725         reg |= 0x5 << 26;
3726         reg |= 0x5 << 23;
3727         reg |= 0x5 << 20;
3728         reg |= 0x5 << 17;
3729         reg |= 0x5 << 14;
3730         reg |= 0x5 << 11;
3731         reg |= 0x5 << 8;
3732         reg |= 0x5 << 5;
3733         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3734
3735         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3736         reg &= ~0xff800000;
3737         reg |= 0x5 << 29;
3738         reg |= 0x5 << 26;
3739         reg |= 0x5 << 23;
3740         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3741 }
3742
3743 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3744                                      struct ath9k_channel *chan)
3745 {
3746         int f[3], t[3];
3747         u16 value;
3748         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3749
3750         if (chain >= 0 && chain < 3) {
3751                 if (IS_CHAN_2GHZ(chan))
3752                         return eep->modalHeader2G.xatten1DB[chain];
3753                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3754                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3755                         f[0] = 5180;
3756                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3757                         f[1] = 5500;
3758                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3759                         f[2] = 5785;
3760                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3761                                                             f, t, 3);
3762                         return value;
3763                 } else
3764                         return eep->modalHeader5G.xatten1DB[chain];
3765         }
3766
3767         return 0;
3768 }
3769
3770
3771 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3772                                             struct ath9k_channel *chan)
3773 {
3774         int f[3], t[3];
3775         u16 value;
3776         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3777
3778         if (chain >= 0 && chain < 3) {
3779                 if (IS_CHAN_2GHZ(chan))
3780                         return eep->modalHeader2G.xatten1Margin[chain];
3781                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3782                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3783                         f[0] = 5180;
3784                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3785                         f[1] = 5500;
3786                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3787                         f[2] = 5785;
3788                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3789                                                             f, t, 3);
3790                         return value;
3791                 } else
3792                         return eep->modalHeader5G.xatten1Margin[chain];
3793         }
3794
3795         return 0;
3796 }
3797
3798 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3799 {
3800         int i;
3801         u16 value;
3802         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3803                                           AR_PHY_EXT_ATTEN_CTL_1,
3804                                           AR_PHY_EXT_ATTEN_CTL_2,
3805                                          };
3806
3807         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3808         for (i = 0; i < 3; i++) {
3809                 if (ah->txchainmask & BIT(i)) {
3810                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3811                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3812                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3813
3814                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3815                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3816                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3817                                       value);
3818                 }
3819         }
3820 }
3821
3822 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3823 {
3824         int timeout = 100;
3825
3826         while (pmu_set != REG_READ(ah, pmu_reg)) {
3827                 if (timeout-- == 0)
3828                         return false;
3829                 REG_WRITE(ah, pmu_reg, pmu_set);
3830                 udelay(10);
3831         }
3832
3833         return true;
3834 }
3835
3836 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3837 {
3838         int internal_regulator =
3839                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3840
3841         if (internal_regulator) {
3842                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3843                         int reg_pmu_set;
3844
3845                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3846                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3847                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3848                                 return;
3849
3850                         if (AR_SREV_9330(ah)) {
3851                                 if (ah->is_clk_25mhz) {
3852                                         reg_pmu_set = (3 << 1) | (8 << 4) |
3853                                                       (3 << 8) | (1 << 14) |
3854                                                       (6 << 17) | (1 << 20) |
3855                                                       (3 << 24);
3856                                 } else {
3857                                         reg_pmu_set = (4 << 1)  | (7 << 4) |
3858                                                       (3 << 8)  | (1 << 14) |
3859                                                       (6 << 17) | (1 << 20) |
3860                                                       (3 << 24);
3861                                 }
3862                         } else {
3863                                 reg_pmu_set = (5 << 1) | (7 << 4) |
3864                                               (2 << 8) | (2 << 14) |
3865                                               (6 << 17) | (1 << 20) |
3866                                               (3 << 24) | (1 << 28);
3867                         }
3868
3869                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3870                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3871                                 return;
3872
3873                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3874                                         | (4 << 26);
3875                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3876                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3877                                 return;
3878
3879                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3880                                         | (1 << 21);
3881                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3882                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3883                                 return;
3884                 } else {
3885                         /* Internal regulator is ON. Write swreg register. */
3886                         int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3887                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3888                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3889                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3890                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3891                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3892                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3893                                   REG_READ(ah,
3894                                            AR_RTC_REG_CONTROL1) |
3895                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3896                 }
3897         } else {
3898                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3899                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3900                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3901                                               AR_PHY_PMU2_PGM))
3902                                 udelay(10);
3903
3904                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3905                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3906                                                AR_PHY_PMU1_PWD))
3907                                 udelay(10);
3908                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3909                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3910                                               AR_PHY_PMU2_PGM))
3911                                 udelay(10);
3912                 } else
3913                         REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3914                                   (REG_READ(ah,
3915                                    AR_RTC_SLEEP_CLK) |
3916                                    AR_RTC_FORCE_SWREG_PRD));
3917         }
3918
3919 }
3920
3921 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3922 {
3923         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3924         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3925
3926         if (eep->baseEepHeader.featureEnable & 0x40) {
3927                 tuning_caps_param &= 0x7f;
3928                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3929                               tuning_caps_param);
3930                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3931                               tuning_caps_param);
3932         }
3933 }
3934
3935 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3936                                              struct ath9k_channel *chan)
3937 {
3938         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3939         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3940         ar9003_hw_drive_strength_apply(ah);
3941         ar9003_hw_atten_apply(ah, chan);
3942         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3943                 ar9003_hw_internal_regulator_apply(ah);
3944         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3945                 ar9003_hw_apply_tuning_caps(ah);
3946 }
3947
3948 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3949                                       struct ath9k_channel *chan)
3950 {
3951 }
3952
3953 /*
3954  * Returns the interpolated y value corresponding to the specified x value
3955  * from the np ordered pairs of data (px,py).
3956  * The pairs do not have to be in any order.
3957  * If the specified x value is less than any of the px,
3958  * the returned y value is equal to the py for the lowest px.
3959  * If the specified x value is greater than any of the px,
3960  * the returned y value is equal to the py for the highest px.
3961  */
3962 static int ar9003_hw_power_interpolate(int32_t x,
3963                                        int32_t *px, int32_t *py, u_int16_t np)
3964 {
3965         int ip = 0;
3966         int lx = 0, ly = 0, lhave = 0;
3967         int hx = 0, hy = 0, hhave = 0;
3968         int dx = 0;
3969         int y = 0;
3970
3971         lhave = 0;
3972         hhave = 0;
3973
3974         /* identify best lower and higher x calibration measurement */
3975         for (ip = 0; ip < np; ip++) {
3976                 dx = x - px[ip];
3977
3978                 /* this measurement is higher than our desired x */
3979                 if (dx <= 0) {
3980                         if (!hhave || dx > (x - hx)) {
3981                                 /* new best higher x measurement */
3982                                 hx = px[ip];
3983                                 hy = py[ip];
3984                                 hhave = 1;
3985                         }
3986                 }
3987                 /* this measurement is lower than our desired x */
3988                 if (dx >= 0) {
3989                         if (!lhave || dx < (x - lx)) {
3990                                 /* new best lower x measurement */
3991                                 lx = px[ip];
3992                                 ly = py[ip];
3993                                 lhave = 1;
3994                         }
3995                 }
3996         }
3997
3998         /* the low x is good */
3999         if (lhave) {
4000                 /* so is the high x */
4001                 if (hhave) {
4002                         /* they're the same, so just pick one */
4003                         if (hx == lx)
4004                                 y = ly;
4005                         else    /* interpolate  */
4006                                 y = interpolate(x, lx, hx, ly, hy);
4007                 } else          /* only low is good, use it */
4008                         y = ly;
4009         } else if (hhave)       /* only high is good, use it */
4010                 y = hy;
4011         else /* nothing is good,this should never happen unless np=0, ???? */
4012                 y = -(1 << 30);
4013         return y;
4014 }
4015
4016 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4017                                        u16 rateIndex, u16 freq, bool is2GHz)
4018 {
4019         u16 numPiers, i;
4020         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4021         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4022         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4023         struct cal_tgt_pow_legacy *pEepromTargetPwr;
4024         u8 *pFreqBin;
4025
4026         if (is2GHz) {
4027                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4028                 pEepromTargetPwr = eep->calTargetPower2G;
4029                 pFreqBin = eep->calTarget_freqbin_2G;
4030         } else {
4031                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4032                 pEepromTargetPwr = eep->calTargetPower5G;
4033                 pFreqBin = eep->calTarget_freqbin_5G;
4034         }
4035
4036         /*
4037          * create array of channels and targetpower from
4038          * targetpower piers stored on eeprom
4039          */
4040         for (i = 0; i < numPiers; i++) {
4041                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4042                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4043         }
4044
4045         /* interpolate to get target power for given frequency */
4046         return (u8) ar9003_hw_power_interpolate((s32) freq,
4047                                                  freqArray,
4048                                                  targetPowerArray, numPiers);
4049 }
4050
4051 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4052                                             u16 rateIndex,
4053                                             u16 freq, bool is2GHz)
4054 {
4055         u16 numPiers, i;
4056         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4057         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4058         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4059         struct cal_tgt_pow_ht *pEepromTargetPwr;
4060         u8 *pFreqBin;
4061
4062         if (is2GHz) {
4063                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4064                 pEepromTargetPwr = eep->calTargetPower2GHT20;
4065                 pFreqBin = eep->calTarget_freqbin_2GHT20;
4066         } else {
4067                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4068                 pEepromTargetPwr = eep->calTargetPower5GHT20;
4069                 pFreqBin = eep->calTarget_freqbin_5GHT20;
4070         }
4071
4072         /*
4073          * create array of channels and targetpower
4074          * from targetpower piers stored on eeprom
4075          */
4076         for (i = 0; i < numPiers; i++) {
4077                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4078                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4079         }
4080
4081         /* interpolate to get target power for given frequency */
4082         return (u8) ar9003_hw_power_interpolate((s32) freq,
4083                                                  freqArray,
4084                                                  targetPowerArray, numPiers);
4085 }
4086
4087 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4088                                             u16 rateIndex,
4089                                             u16 freq, bool is2GHz)
4090 {
4091         u16 numPiers, i;
4092         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4093         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4094         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4095         struct cal_tgt_pow_ht *pEepromTargetPwr;
4096         u8 *pFreqBin;
4097
4098         if (is2GHz) {
4099                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4100                 pEepromTargetPwr = eep->calTargetPower2GHT40;
4101                 pFreqBin = eep->calTarget_freqbin_2GHT40;
4102         } else {
4103                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4104                 pEepromTargetPwr = eep->calTargetPower5GHT40;
4105                 pFreqBin = eep->calTarget_freqbin_5GHT40;
4106         }
4107
4108         /*
4109          * create array of channels and targetpower from
4110          * targetpower piers stored on eeprom
4111          */
4112         for (i = 0; i < numPiers; i++) {
4113                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4114                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4115         }
4116
4117         /* interpolate to get target power for given frequency */
4118         return (u8) ar9003_hw_power_interpolate((s32) freq,
4119                                                  freqArray,
4120                                                  targetPowerArray, numPiers);
4121 }
4122
4123 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4124                                            u16 rateIndex, u16 freq)
4125 {
4126         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4127         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4128         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4129         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4130         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4131         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4132
4133         /*
4134          * create array of channels and targetpower from
4135          * targetpower piers stored on eeprom
4136          */
4137         for (i = 0; i < numPiers; i++) {
4138                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4139                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4140         }
4141
4142         /* interpolate to get target power for given frequency */
4143         return (u8) ar9003_hw_power_interpolate((s32) freq,
4144                                                  freqArray,
4145                                                  targetPowerArray, numPiers);
4146 }
4147
4148 /* Set tx power registers to array of values passed in */
4149 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4150 {
4151 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4152         /* make sure forced gain is not set */
4153         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4154
4155         /* Write the OFDM power per rate set */
4156
4157         /* 6 (LSB), 9, 12, 18 (MSB) */
4158         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4159                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4160                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4161                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4162                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4163
4164         /* 24 (LSB), 36, 48, 54 (MSB) */
4165         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4166                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4167                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4168                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4169                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4170
4171         /* Write the CCK power per rate set */
4172
4173         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4174         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4175                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4176                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4177                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4178                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4179
4180         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4181         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4182                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4183                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4184                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4185                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4186             );
4187
4188         /* Write the power for duplicated frames - HT40 */
4189
4190         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4191         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4192                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4193                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4194                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4195                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4196             );
4197
4198         /* Write the HT20 power per rate set */
4199
4200         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4201         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4202                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4203                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4204                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4205                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4206             );
4207
4208         /* 6 (LSB), 7, 12, 13 (MSB) */
4209         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4210                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4211                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4212                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4213                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4214             );
4215
4216         /* 14 (LSB), 15, 20, 21 */
4217         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4218                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4219                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4220                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4221                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4222             );
4223
4224         /* Mixed HT20 and HT40 rates */
4225
4226         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4227         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4228                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4229                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4230                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4231                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4232             );
4233
4234         /*
4235          * Write the HT40 power per rate set
4236          * correct PAR difference between HT40 and HT20/LEGACY
4237          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4238          */
4239         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4240                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4241                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4242                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4243                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4244             );
4245
4246         /* 6 (LSB), 7, 12, 13 (MSB) */
4247         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4248                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4249                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4250                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4251                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4252             );
4253
4254         /* 14 (LSB), 15, 20, 21 */
4255         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4256                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4257                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4258                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4259                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4260             );
4261
4262         return 0;
4263 #undef POW_SM
4264 }
4265
4266 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4267                                               u8 *targetPowerValT2)
4268 {
4269         /* XXX: hard code for now, need to get from eeprom struct */
4270         u8 ht40PowerIncForPdadc = 0;
4271         bool is2GHz = false;
4272         unsigned int i = 0;
4273         struct ath_common *common = ath9k_hw_common(ah);
4274
4275         if (freq < 4000)
4276                 is2GHz = true;
4277
4278         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4279             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4280                                          is2GHz);
4281         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4282             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4283                                          is2GHz);
4284         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4285             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4286                                          is2GHz);
4287         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4288             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4289                                          is2GHz);
4290         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4291             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4292                                              freq);
4293         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4294             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4295         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4296             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4297         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4298             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4299         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4300             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4301                                               is2GHz);
4302         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4303             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4304                                               freq, is2GHz);
4305         targetPowerValT2[ALL_TARGET_HT20_4] =
4306             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4307                                               is2GHz);
4308         targetPowerValT2[ALL_TARGET_HT20_5] =
4309             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4310                                               is2GHz);
4311         targetPowerValT2[ALL_TARGET_HT20_6] =
4312             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4313                                               is2GHz);
4314         targetPowerValT2[ALL_TARGET_HT20_7] =
4315             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4316                                               is2GHz);
4317         targetPowerValT2[ALL_TARGET_HT20_12] =
4318             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4319                                               is2GHz);
4320         targetPowerValT2[ALL_TARGET_HT20_13] =
4321             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4322                                               is2GHz);
4323         targetPowerValT2[ALL_TARGET_HT20_14] =
4324             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4325                                               is2GHz);
4326         targetPowerValT2[ALL_TARGET_HT20_15] =
4327             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4328                                               is2GHz);
4329         targetPowerValT2[ALL_TARGET_HT20_20] =
4330             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4331                                               is2GHz);
4332         targetPowerValT2[ALL_TARGET_HT20_21] =
4333             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4334                                               is2GHz);
4335         targetPowerValT2[ALL_TARGET_HT20_22] =
4336             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4337                                               is2GHz);
4338         targetPowerValT2[ALL_TARGET_HT20_23] =
4339             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4340                                               is2GHz);
4341         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4342             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4343                                               is2GHz) + ht40PowerIncForPdadc;
4344         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4345             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4346                                               freq,
4347                                               is2GHz) + ht40PowerIncForPdadc;
4348         targetPowerValT2[ALL_TARGET_HT40_4] =
4349             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4350                                               is2GHz) + ht40PowerIncForPdadc;
4351         targetPowerValT2[ALL_TARGET_HT40_5] =
4352             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4353                                               is2GHz) + ht40PowerIncForPdadc;
4354         targetPowerValT2[ALL_TARGET_HT40_6] =
4355             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4356                                               is2GHz) + ht40PowerIncForPdadc;
4357         targetPowerValT2[ALL_TARGET_HT40_7] =
4358             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4359                                               is2GHz) + ht40PowerIncForPdadc;
4360         targetPowerValT2[ALL_TARGET_HT40_12] =
4361             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4362                                               is2GHz) + ht40PowerIncForPdadc;
4363         targetPowerValT2[ALL_TARGET_HT40_13] =
4364             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4365                                               is2GHz) + ht40PowerIncForPdadc;
4366         targetPowerValT2[ALL_TARGET_HT40_14] =
4367             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4368                                               is2GHz) + ht40PowerIncForPdadc;
4369         targetPowerValT2[ALL_TARGET_HT40_15] =
4370             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4371                                               is2GHz) + ht40PowerIncForPdadc;
4372         targetPowerValT2[ALL_TARGET_HT40_20] =
4373             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4374                                               is2GHz) + ht40PowerIncForPdadc;
4375         targetPowerValT2[ALL_TARGET_HT40_21] =
4376             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4377                                               is2GHz) + ht40PowerIncForPdadc;
4378         targetPowerValT2[ALL_TARGET_HT40_22] =
4379             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4380                                               is2GHz) + ht40PowerIncForPdadc;
4381         targetPowerValT2[ALL_TARGET_HT40_23] =
4382             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4383                                               is2GHz) + ht40PowerIncForPdadc;
4384
4385         for (i = 0; i < ar9300RateSize; i++) {
4386                 ath_dbg(common, ATH_DBG_EEPROM,
4387                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4388         }
4389 }
4390
4391 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4392                                   int mode,
4393                                   int ipier,
4394                                   int ichain,
4395                                   int *pfrequency,
4396                                   int *pcorrection,
4397                                   int *ptemperature, int *pvoltage)
4398 {
4399         u8 *pCalPier;
4400         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4401         int is2GHz;
4402         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4403         struct ath_common *common = ath9k_hw_common(ah);
4404
4405         if (ichain >= AR9300_MAX_CHAINS) {
4406                 ath_dbg(common, ATH_DBG_EEPROM,
4407                         "Invalid chain index, must be less than %d\n",
4408                         AR9300_MAX_CHAINS);
4409                 return -1;
4410         }
4411
4412         if (mode) {             /* 5GHz */
4413                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4414                         ath_dbg(common, ATH_DBG_EEPROM,
4415                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4416                                 AR9300_NUM_5G_CAL_PIERS);
4417                         return -1;
4418                 }
4419                 pCalPier = &(eep->calFreqPier5G[ipier]);
4420                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4421                 is2GHz = 0;
4422         } else {
4423                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4424                         ath_dbg(common, ATH_DBG_EEPROM,
4425                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4426                                 AR9300_NUM_2G_CAL_PIERS);
4427                         return -1;
4428                 }
4429
4430                 pCalPier = &(eep->calFreqPier2G[ipier]);
4431                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4432                 is2GHz = 1;
4433         }
4434
4435         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4436         *pcorrection = pCalPierStruct->refPower;
4437         *ptemperature = pCalPierStruct->tempMeas;
4438         *pvoltage = pCalPierStruct->voltMeas;
4439
4440         return 0;
4441 }
4442
4443 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4444                                             int frequency,
4445                                             int *correction,
4446                                             int *voltage, int *temperature)
4447 {
4448         int tempSlope = 0;
4449         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4450         int f[3], t[3];
4451
4452         REG_RMW(ah, AR_PHY_TPC_11_B0,
4453                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4454                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4455         if (ah->caps.tx_chainmask & BIT(1))
4456                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4457                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4458                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4459         if (ah->caps.tx_chainmask & BIT(2))
4460                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4461                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4462                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4463
4464         /* enable open loop power control on chip */
4465         REG_RMW(ah, AR_PHY_TPC_6_B0,
4466                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4467                 AR_PHY_TPC_6_ERROR_EST_MODE);
4468         if (ah->caps.tx_chainmask & BIT(1))
4469                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4470                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4471                         AR_PHY_TPC_6_ERROR_EST_MODE);
4472         if (ah->caps.tx_chainmask & BIT(2))
4473                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4474                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4475                         AR_PHY_TPC_6_ERROR_EST_MODE);
4476
4477         /*
4478          * enable temperature compensation
4479          * Need to use register names
4480          */
4481         if (frequency < 4000)
4482                 tempSlope = eep->modalHeader2G.tempSlope;
4483         else if (eep->base_ext2.tempSlopeLow != 0) {
4484                 t[0] = eep->base_ext2.tempSlopeLow;
4485                 f[0] = 5180;
4486                 t[1] = eep->modalHeader5G.tempSlope;
4487                 f[1] = 5500;
4488                 t[2] = eep->base_ext2.tempSlopeHigh;
4489                 f[2] = 5785;
4490                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4491                                                         f, t, 3);
4492         } else
4493                 tempSlope = eep->modalHeader5G.tempSlope;
4494
4495         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4496         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4497                       temperature[0]);
4498
4499         return 0;
4500 }
4501
4502 /* Apply the recorded correction values. */
4503 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4504 {
4505         int ichain, ipier, npier;
4506         int mode;
4507         int lfrequency[AR9300_MAX_CHAINS],
4508             lcorrection[AR9300_MAX_CHAINS],
4509             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4510         int hfrequency[AR9300_MAX_CHAINS],
4511             hcorrection[AR9300_MAX_CHAINS],
4512             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4513         int fdiff;
4514         int correction[AR9300_MAX_CHAINS],
4515             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4516         int pfrequency, pcorrection, ptemperature, pvoltage;
4517         struct ath_common *common = ath9k_hw_common(ah);
4518
4519         mode = (frequency >= 4000);
4520         if (mode)
4521                 npier = AR9300_NUM_5G_CAL_PIERS;
4522         else
4523                 npier = AR9300_NUM_2G_CAL_PIERS;
4524
4525         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4526                 lfrequency[ichain] = 0;
4527                 hfrequency[ichain] = 100000;
4528         }
4529         /* identify best lower and higher frequency calibration measurement */
4530         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4531                 for (ipier = 0; ipier < npier; ipier++) {
4532                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4533                                                     &pfrequency, &pcorrection,
4534                                                     &ptemperature, &pvoltage)) {
4535                                 fdiff = frequency - pfrequency;
4536
4537                                 /*
4538                                  * this measurement is higher than
4539                                  * our desired frequency
4540                                  */
4541                                 if (fdiff <= 0) {
4542                                         if (hfrequency[ichain] <= 0 ||
4543                                             hfrequency[ichain] >= 100000 ||
4544                                             fdiff >
4545                                             (frequency - hfrequency[ichain])) {
4546                                                 /*
4547                                                  * new best higher
4548                                                  * frequency measurement
4549                                                  */
4550                                                 hfrequency[ichain] = pfrequency;
4551                                                 hcorrection[ichain] =
4552                                                     pcorrection;
4553                                                 htemperature[ichain] =
4554                                                     ptemperature;
4555                                                 hvoltage[ichain] = pvoltage;
4556                                         }
4557                                 }
4558                                 if (fdiff >= 0) {
4559                                         if (lfrequency[ichain] <= 0
4560                                             || fdiff <
4561                                             (frequency - lfrequency[ichain])) {
4562                                                 /*
4563                                                  * new best lower
4564                                                  * frequency measurement
4565                                                  */
4566                                                 lfrequency[ichain] = pfrequency;
4567                                                 lcorrection[ichain] =
4568                                                     pcorrection;
4569                                                 ltemperature[ichain] =
4570                                                     ptemperature;
4571                                                 lvoltage[ichain] = pvoltage;
4572                                         }
4573                                 }
4574                         }
4575                 }
4576         }
4577
4578         /* interpolate  */
4579         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4580                 ath_dbg(common, ATH_DBG_EEPROM,
4581                         "ch=%d f=%d low=%d %d h=%d %d\n",
4582                         ichain, frequency, lfrequency[ichain],
4583                         lcorrection[ichain], hfrequency[ichain],
4584                         hcorrection[ichain]);
4585                 /* they're the same, so just pick one */
4586                 if (hfrequency[ichain] == lfrequency[ichain]) {
4587                         correction[ichain] = lcorrection[ichain];
4588                         voltage[ichain] = lvoltage[ichain];
4589                         temperature[ichain] = ltemperature[ichain];
4590                 }
4591                 /* the low frequency is good */
4592                 else if (frequency - lfrequency[ichain] < 1000) {
4593                         /* so is the high frequency, interpolate */
4594                         if (hfrequency[ichain] - frequency < 1000) {
4595
4596                                 correction[ichain] = interpolate(frequency,
4597                                                 lfrequency[ichain],
4598                                                 hfrequency[ichain],
4599                                                 lcorrection[ichain],
4600                                                 hcorrection[ichain]);
4601
4602                                 temperature[ichain] = interpolate(frequency,
4603                                                 lfrequency[ichain],
4604                                                 hfrequency[ichain],
4605                                                 ltemperature[ichain],
4606                                                 htemperature[ichain]);
4607
4608                                 voltage[ichain] = interpolate(frequency,
4609                                                 lfrequency[ichain],
4610                                                 hfrequency[ichain],
4611                                                 lvoltage[ichain],
4612                                                 hvoltage[ichain]);
4613                         }
4614                         /* only low is good, use it */
4615                         else {
4616                                 correction[ichain] = lcorrection[ichain];
4617                                 temperature[ichain] = ltemperature[ichain];
4618                                 voltage[ichain] = lvoltage[ichain];
4619                         }
4620                 }
4621                 /* only high is good, use it */
4622                 else if (hfrequency[ichain] - frequency < 1000) {
4623                         correction[ichain] = hcorrection[ichain];
4624                         temperature[ichain] = htemperature[ichain];
4625                         voltage[ichain] = hvoltage[ichain];
4626                 } else {        /* nothing is good, presume 0???? */
4627                         correction[ichain] = 0;
4628                         temperature[ichain] = 0;
4629                         voltage[ichain] = 0;
4630                 }
4631         }
4632
4633         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4634                                          temperature);
4635
4636         ath_dbg(common, ATH_DBG_EEPROM,
4637                 "for frequency=%d, calibration correction = %d %d %d\n",
4638                 frequency, correction[0], correction[1], correction[2]);
4639
4640         return 0;
4641 }
4642
4643 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4644                                            int idx,
4645                                            int edge,
4646                                            bool is2GHz)
4647 {
4648         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4649         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4650
4651         if (is2GHz)
4652                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4653         else
4654                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4655 }
4656
4657 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4658                                              int idx,
4659                                              unsigned int edge,
4660                                              u16 freq,
4661                                              bool is2GHz)
4662 {
4663         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4664         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4665
4666         u8 *ctl_freqbin = is2GHz ?
4667                 &eep->ctl_freqbin_2G[idx][0] :
4668                 &eep->ctl_freqbin_5G[idx][0];
4669
4670         if (is2GHz) {
4671                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4672                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4673                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4674         } else {
4675                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4676                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4677                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4678         }
4679
4680         return MAX_RATE_POWER;
4681 }
4682
4683 /*
4684  * Find the maximum conformance test limit for the given channel and CTL info
4685  */
4686 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4687                                         u16 freq, int idx, bool is2GHz)
4688 {
4689         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4690         u8 *ctl_freqbin = is2GHz ?
4691                 &eep->ctl_freqbin_2G[idx][0] :
4692                 &eep->ctl_freqbin_5G[idx][0];
4693         u16 num_edges = is2GHz ?
4694                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4695         unsigned int edge;
4696
4697         /* Get the edge power */
4698         for (edge = 0;
4699              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4700              edge++) {
4701                 /*
4702                  * If there's an exact channel match or an inband flag set
4703                  * on the lower channel use the given rdEdgePower
4704                  */
4705                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4706                         twiceMaxEdgePower =
4707                                 ar9003_hw_get_direct_edge_power(eep, idx,
4708                                                                 edge, is2GHz);
4709                         break;
4710                 } else if ((edge > 0) &&
4711                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4712                                                       is2GHz))) {
4713                         twiceMaxEdgePower =
4714                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4715                                                                   edge, freq,
4716                                                                   is2GHz);
4717                         /*
4718                          * Leave loop - no more affecting edges possible in
4719                          * this monotonic increasing list
4720                          */
4721                         break;
4722                 }
4723         }
4724         return twiceMaxEdgePower;
4725 }
4726
4727 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4728                                                struct ath9k_channel *chan,
4729                                                u8 *pPwrArray, u16 cfgCtl,
4730                                                u8 twiceAntennaReduction,
4731                                                u8 twiceMaxRegulatoryPower,
4732                                                u16 powerLimit)
4733 {
4734         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4735         struct ath_common *common = ath9k_hw_common(ah);
4736         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4737         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4738         static const u16 tpScaleReductionTable[5] = {
4739                 0, 3, 6, 9, MAX_RATE_POWER
4740         };
4741         int i;
4742         int16_t  twiceLargestAntenna;
4743         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4744         static const u16 ctlModesFor11a[] = {
4745                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4746         };
4747         static const u16 ctlModesFor11g[] = {
4748                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4749                 CTL_11G_EXT, CTL_2GHT40
4750         };
4751         u16 numCtlModes;
4752         const u16 *pCtlMode;
4753         u16 ctlMode, freq;
4754         struct chan_centers centers;
4755         u8 *ctlIndex;
4756         u8 ctlNum;
4757         u16 twiceMinEdgePower;
4758         bool is2ghz = IS_CHAN_2GHZ(chan);
4759
4760         ath9k_hw_get_channel_centers(ah, chan, &centers);
4761
4762         /* Compute TxPower reduction due to Antenna Gain */
4763         if (is2ghz)
4764                 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4765         else
4766                 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4767
4768         twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4769                                 twiceLargestAntenna, 0);
4770
4771         /*
4772          * scaledPower is the minimum of the user input power level
4773          * and the regulatory allowed power level
4774          */
4775         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4776
4777         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4778                 maxRegAllowedPower -=
4779                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4780         }
4781
4782         scaledPower = min(powerLimit, maxRegAllowedPower);
4783
4784         /*
4785          * Reduce scaled Power by number of chains active to get
4786          * to per chain tx power level
4787          */
4788         switch (ar5416_get_ntxchains(ah->txchainmask)) {
4789         case 1:
4790                 break;
4791         case 2:
4792                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4793                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4794                 else
4795                         scaledPower = 0;
4796                 break;
4797         case 3:
4798                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4799                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4800                 else
4801                         scaledPower = 0;
4802                 break;
4803         }
4804
4805         scaledPower = max((u16)0, scaledPower);
4806
4807         /*
4808          * Get target powers from EEPROM - our baseline for TX Power
4809          */
4810         if (is2ghz) {
4811                 /* Setup for CTL modes */
4812                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4813                 numCtlModes =
4814                         ARRAY_SIZE(ctlModesFor11g) -
4815                                    SUB_NUM_CTL_MODES_AT_2G_40;
4816                 pCtlMode = ctlModesFor11g;
4817                 if (IS_CHAN_HT40(chan))
4818                         /* All 2G CTL's */
4819                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4820         } else {
4821                 /* Setup for CTL modes */
4822                 /* CTL_11A, CTL_5GHT20 */
4823                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4824                                          SUB_NUM_CTL_MODES_AT_5G_40;
4825                 pCtlMode = ctlModesFor11a;
4826                 if (IS_CHAN_HT40(chan))
4827                         /* All 5G CTL's */
4828                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4829         }
4830
4831         /*
4832          * For MIMO, need to apply regulatory caps individually across
4833          * dynamically running modes: CCK, OFDM, HT20, HT40
4834          *
4835          * The outer loop walks through each possible applicable runtime mode.
4836          * The inner loop walks through each ctlIndex entry in EEPROM.
4837          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4838          */
4839         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4840                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4841                         (pCtlMode[ctlMode] == CTL_2GHT40);
4842                 if (isHt40CtlMode)
4843                         freq = centers.synth_center;
4844                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4845                         freq = centers.ext_center;
4846                 else
4847                         freq = centers.ctl_center;
4848
4849                 ath_dbg(common, ATH_DBG_REGULATORY,
4850                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4851                         ctlMode, numCtlModes, isHt40CtlMode,
4852                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4853
4854                 /* walk through each CTL index stored in EEPROM */
4855                 if (is2ghz) {
4856                         ctlIndex = pEepData->ctlIndex_2G;
4857                         ctlNum = AR9300_NUM_CTLS_2G;
4858                 } else {
4859                         ctlIndex = pEepData->ctlIndex_5G;
4860                         ctlNum = AR9300_NUM_CTLS_5G;
4861                 }
4862
4863                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4864                         ath_dbg(common, ATH_DBG_REGULATORY,
4865                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4866                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4867                                 chan->channel);
4868
4869                                 /*
4870                                  * compare test group from regulatory
4871                                  * channel list with test mode from pCtlMode
4872                                  * list
4873                                  */
4874                                 if ((((cfgCtl & ~CTL_MODE_M) |
4875                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4876                                         ctlIndex[i]) ||
4877                                     (((cfgCtl & ~CTL_MODE_M) |
4878                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4879                                      ((ctlIndex[i] & CTL_MODE_M) |
4880                                        SD_NO_CTL))) {
4881                                         twiceMinEdgePower =
4882                                           ar9003_hw_get_max_edge_power(pEepData,
4883                                                                        freq, i,
4884                                                                        is2ghz);
4885
4886                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4887                                                 /*
4888                                                  * Find the minimum of all CTL
4889                                                  * edge powers that apply to
4890                                                  * this channel
4891                                                  */
4892                                                 twiceMaxEdgePower =
4893                                                         min(twiceMaxEdgePower,
4894                                                             twiceMinEdgePower);
4895                                                 else {
4896                                                         /* specific */
4897                                                         twiceMaxEdgePower =
4898                                                           twiceMinEdgePower;
4899                                                         break;
4900                                                 }
4901                                 }
4902                         }
4903
4904                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4905
4906                         ath_dbg(common, ATH_DBG_REGULATORY,
4907                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4908                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4909                                 scaledPower, minCtlPower);
4910
4911                         /* Apply ctl mode to correct target power set */
4912                         switch (pCtlMode[ctlMode]) {
4913                         case CTL_11B:
4914                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4915                                      i <= ALL_TARGET_LEGACY_11S; i++)
4916                                         pPwrArray[i] =
4917                                           (u8)min((u16)pPwrArray[i],
4918                                                   minCtlPower);
4919                                 break;
4920                         case CTL_11A:
4921                         case CTL_11G:
4922                                 for (i = ALL_TARGET_LEGACY_6_24;
4923                                      i <= ALL_TARGET_LEGACY_54; i++)
4924                                         pPwrArray[i] =
4925                                           (u8)min((u16)pPwrArray[i],
4926                                                   minCtlPower);
4927                                 break;
4928                         case CTL_5GHT20:
4929                         case CTL_2GHT20:
4930                                 for (i = ALL_TARGET_HT20_0_8_16;
4931                                      i <= ALL_TARGET_HT20_21; i++)
4932                                         pPwrArray[i] =
4933                                           (u8)min((u16)pPwrArray[i],
4934                                                   minCtlPower);
4935                                 pPwrArray[ALL_TARGET_HT20_22] =
4936                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4937                                           minCtlPower);
4938                                 pPwrArray[ALL_TARGET_HT20_23] =
4939                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4940                                            minCtlPower);
4941                                 break;
4942                         case CTL_5GHT40:
4943                         case CTL_2GHT40:
4944                                 for (i = ALL_TARGET_HT40_0_8_16;
4945                                      i <= ALL_TARGET_HT40_23; i++)
4946                                         pPwrArray[i] =
4947                                           (u8)min((u16)pPwrArray[i],
4948                                                   minCtlPower);
4949                                 break;
4950                         default:
4951                             break;
4952                         }
4953         } /* end ctl mode checking */
4954 }
4955
4956 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4957 {
4958         u8 mod_idx = mcs_idx % 8;
4959
4960         if (mod_idx <= 3)
4961                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4962         else
4963                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4964 }
4965
4966 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4967                                         struct ath9k_channel *chan, u16 cfgCtl,
4968                                         u8 twiceAntennaReduction,
4969                                         u8 twiceMaxRegulatoryPower,
4970                                         u8 powerLimit, bool test)
4971 {
4972         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4973         struct ath_common *common = ath9k_hw_common(ah);
4974         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4975         struct ar9300_modal_eep_header *modal_hdr;
4976         u8 targetPowerValT2[ar9300RateSize];
4977         u8 target_power_val_t2_eep[ar9300RateSize];
4978         unsigned int i = 0, paprd_scale_factor = 0;
4979         u8 pwr_idx, min_pwridx = 0;
4980
4981         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4982
4983         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4984                 if (IS_CHAN_2GHZ(chan))
4985                         modal_hdr = &eep->modalHeader2G;
4986                 else
4987                         modal_hdr = &eep->modalHeader5G;
4988
4989                 ah->paprd_ratemask =
4990                         le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4991                         AR9300_PAPRD_RATE_MASK;
4992
4993                 ah->paprd_ratemask_ht40 =
4994                         le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4995                         AR9300_PAPRD_RATE_MASK;
4996
4997                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4998                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4999                                                   ALL_TARGET_HT20_0_8_16;
5000
5001                 if (!ah->paprd_table_write_done) {
5002                         memcpy(target_power_val_t2_eep, targetPowerValT2,
5003                                sizeof(targetPowerValT2));
5004                         for (i = 0; i < 24; i++) {
5005                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5006                                 if (ah->paprd_ratemask & (1 << i)) {
5007                                         if (targetPowerValT2[pwr_idx] &&
5008                                             targetPowerValT2[pwr_idx] ==
5009                                             target_power_val_t2_eep[pwr_idx])
5010                                                 targetPowerValT2[pwr_idx] -=
5011                                                         paprd_scale_factor;
5012                                 }
5013                         }
5014                 }
5015                 memcpy(target_power_val_t2_eep, targetPowerValT2,
5016                        sizeof(targetPowerValT2));
5017         }
5018
5019         ar9003_hw_set_power_per_rate_table(ah, chan,
5020                                            targetPowerValT2, cfgCtl,
5021                                            twiceAntennaReduction,
5022                                            twiceMaxRegulatoryPower,
5023                                            powerLimit);
5024
5025         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5026                 for (i = 0; i < ar9300RateSize; i++) {
5027                         if ((ah->paprd_ratemask & (1 << i)) &&
5028                             (abs(targetPowerValT2[i] -
5029                                 target_power_val_t2_eep[i]) >
5030                             paprd_scale_factor)) {
5031                                 ah->paprd_ratemask &= ~(1 << i);
5032                                 ath_dbg(common, ATH_DBG_EEPROM,
5033                                         "paprd disabled for mcs %d\n", i);
5034                         }
5035                 }
5036         }
5037
5038         regulatory->max_power_level = 0;
5039         for (i = 0; i < ar9300RateSize; i++) {
5040                 if (targetPowerValT2[i] > regulatory->max_power_level)
5041                         regulatory->max_power_level = targetPowerValT2[i];
5042         }
5043
5044         if (test)
5045                 return;
5046
5047         for (i = 0; i < ar9300RateSize; i++) {
5048                 ath_dbg(common, ATH_DBG_EEPROM,
5049                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
5050         }
5051
5052         ah->txpower_limit = regulatory->max_power_level;
5053
5054         /* Write target power array to registers */
5055         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5056         ar9003_hw_calibration_apply(ah, chan->channel);
5057
5058         if (IS_CHAN_2GHZ(chan)) {
5059                 if (IS_CHAN_HT40(chan))
5060                         i = ALL_TARGET_HT40_0_8_16;
5061                 else
5062                         i = ALL_TARGET_HT20_0_8_16;
5063         } else {
5064                 if (IS_CHAN_HT40(chan))
5065                         i = ALL_TARGET_HT40_7;
5066                 else
5067                         i = ALL_TARGET_HT20_7;
5068         }
5069         ah->paprd_target_power = targetPowerValT2[i];
5070 }
5071
5072 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5073                                             u16 i, bool is2GHz)
5074 {
5075         return AR_NO_SPUR;
5076 }
5077
5078 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5079 {
5080         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5081
5082         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5083 }
5084
5085 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5086 {
5087         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5088
5089         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5090 }
5091
5092 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5093 {
5094         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5095
5096         if (is_2ghz)
5097                 return eep->modalHeader2G.spurChans;
5098         else
5099                 return eep->modalHeader5G.spurChans;
5100 }
5101
5102 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5103                                            struct ath9k_channel *chan)
5104 {
5105         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5106
5107         if (IS_CHAN_2GHZ(chan))
5108                 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5109                           AR9300_PAPRD_SCALE_1);
5110         else {
5111                 if (chan->channel >= 5700)
5112                 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5113                           AR9300_PAPRD_SCALE_1);
5114                 else if (chan->channel >= 5400)
5115                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5116                                    AR9300_PAPRD_SCALE_2);
5117                 else
5118                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5119                                   AR9300_PAPRD_SCALE_1);
5120         }
5121 }
5122
5123 const struct eeprom_ops eep_ar9300_ops = {
5124         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5125         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5126         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5127         .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5128         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5129         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5130         .set_board_values = ath9k_hw_ar9300_set_board_values,
5131         .set_addac = ath9k_hw_ar9300_set_addac,
5132         .set_txpower = ath9k_hw_ar9300_set_txpower,
5133         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5134 };