2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include "ar9003_phy.h"
20 #include "ar9003_rtt.h"
21 #include "ar9003_mci.h"
23 #define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
24 #define MAX_MAG_DELTA 11
25 #define MAX_PHS_DELTA 10
28 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
29 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
33 enum ar9003_cal_types {
34 IQ_MISMATCH_CAL = BIT(0),
37 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
38 struct ath9k_cal_list *currCal)
40 struct ath_common *common = ath9k_hw_common(ah);
42 /* Select calibration to run */
43 switch (currCal->calData->calType) {
46 * Start calibration with
47 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
49 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
50 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
51 currCal->calData->calCountMax);
52 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
54 ath_dbg(common, CALIBRATE,
55 "starting IQ Mismatch Calibration\n");
58 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
61 ath_err(common, "Invalid calibration type\n");
67 * Generic calibration routine.
68 * Recalibrate the lower PHY chips to account for temperature/environment
71 static bool ar9003_hw_per_calibration(struct ath_hw *ah,
72 struct ath9k_channel *ichan,
74 struct ath9k_cal_list *currCal)
76 struct ath9k_hw_cal_data *caldata = ah->caldata;
77 /* Cal is assumed not done until explicitly set below */
78 bool iscaldone = false;
80 /* Calibration in progress. */
81 if (currCal->calState == CAL_RUNNING) {
82 /* Check to see if it has finished. */
83 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
85 * Accumulate cal measures for active chains
87 currCal->calData->calCollect(ah);
90 if (ah->cal_samples >=
91 currCal->calData->calNumSamples) {
92 unsigned int i, numChains = 0;
93 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
94 if (rxchainmask & (1 << i))
99 * Process accumulated data
101 currCal->calData->calPostProc(ah, numChains);
103 /* Calibration has finished. */
104 caldata->CalValid |= currCal->calData->calType;
105 currCal->calState = CAL_DONE;
109 * Set-up collection of another sub-sample until we
112 ar9003_hw_setup_calibration(ah, currCal);
115 } else if (!(caldata->CalValid & currCal->calData->calType)) {
116 /* If current cal is marked invalid in channel, kick it off */
117 ath9k_hw_reset_calibration(ah, currCal);
123 static bool ar9003_hw_calibrate(struct ath_hw *ah,
124 struct ath9k_channel *chan,
128 bool iscaldone = true;
129 struct ath9k_cal_list *currCal = ah->cal_list_curr;
132 * For given calibration:
133 * 1. Call generic cal routine
134 * 2. When this cal is done (isCalDone) if we have more cals waiting
135 * (eg after reset), mask this to upper layers by not propagating
136 * isCalDone if it is set to TRUE.
137 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
141 (currCal->calState == CAL_RUNNING ||
142 currCal->calState == CAL_WAITING)) {
143 iscaldone = ar9003_hw_per_calibration(ah, chan,
144 rxchainmask, currCal);
146 ah->cal_list_curr = currCal = currCal->calNext;
148 if (currCal->calState == CAL_WAITING) {
150 ath9k_hw_reset_calibration(ah, currCal);
156 * Do NF cal only at longer intervals. Get the value from
157 * the previous NF cal and update history buffer.
159 if (longcal && ath9k_hw_getnf(ah, chan)) {
161 * Load the NF from history buffer of the current channel.
162 * NF is slow time-variant, so it is OK to use a historical
165 ath9k_hw_loadnf(ah, ah->curchan);
167 /* start NF calibration, without updating BB NF register */
168 ath9k_hw_start_nfcal(ah, false);
174 static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
178 /* Accumulate IQ cal measures for active chains */
179 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
180 if (ah->txchainmask & BIT(i)) {
181 ah->totalPowerMeasI[i] +=
182 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
183 ah->totalPowerMeasQ[i] +=
184 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
185 ah->totalIqCorrMeas[i] +=
186 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
187 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
188 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
189 ah->cal_samples, i, ah->totalPowerMeasI[i],
190 ah->totalPowerMeasQ[i],
191 ah->totalIqCorrMeas[i]);
196 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
198 struct ath_common *common = ath9k_hw_common(ah);
199 u32 powerMeasQ, powerMeasI, iqCorrMeas;
200 u32 qCoffDenom, iCoffDenom;
201 int32_t qCoff, iCoff;
203 static const u_int32_t offset_array[3] = {
204 AR_PHY_RX_IQCAL_CORR_B0,
205 AR_PHY_RX_IQCAL_CORR_B1,
206 AR_PHY_RX_IQCAL_CORR_B2,
209 for (i = 0; i < numChains; i++) {
210 powerMeasI = ah->totalPowerMeasI[i];
211 powerMeasQ = ah->totalPowerMeasQ[i];
212 iqCorrMeas = ah->totalIqCorrMeas[i];
214 ath_dbg(common, CALIBRATE,
215 "Starting IQ Cal and Correction for Chain %d\n", i);
217 ath_dbg(common, CALIBRATE,
218 "Original: Chn %d iq_corr_meas = 0x%08x\n",
219 i, ah->totalIqCorrMeas[i]);
223 if (iqCorrMeas > 0x80000000) {
224 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
228 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",
230 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",
232 ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);
234 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
235 qCoffDenom = powerMeasQ / 64;
237 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
238 iCoff = iqCorrMeas / iCoffDenom;
239 qCoff = powerMeasI / qCoffDenom - 64;
240 ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",
242 ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",
245 /* Force bounds on iCoff */
248 else if (iCoff <= -63)
251 /* Negate iCoff if iqCorrNeg == 0 */
252 if (iqCorrNeg == 0x0)
255 /* Force bounds on qCoff */
258 else if (qCoff <= -63)
261 iCoff = iCoff & 0x7f;
262 qCoff = qCoff & 0x7f;
264 ath_dbg(common, CALIBRATE,
265 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
267 ath_dbg(common, CALIBRATE,
268 "Register offset (0x%04x) before update = 0x%x\n",
270 REG_READ(ah, offset_array[i]));
272 if (AR_SREV_9565(ah) &&
273 (iCoff == 63 || qCoff == 63 ||
274 iCoff == -63 || qCoff == -63))
277 REG_RMW_FIELD(ah, offset_array[i],
278 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
280 REG_RMW_FIELD(ah, offset_array[i],
281 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
283 ath_dbg(common, CALIBRATE,
284 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
286 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
287 REG_READ(ah, offset_array[i]));
288 ath_dbg(common, CALIBRATE,
289 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
291 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
292 REG_READ(ah, offset_array[i]));
294 ath_dbg(common, CALIBRATE,
295 "IQ Cal and Correction done for Chain %d\n", i);
299 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
300 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
301 ath_dbg(common, CALIBRATE,
302 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
303 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
304 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
305 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
308 static const struct ath9k_percal_data iq_cal_single_sample = {
312 ar9003_hw_iqcal_collect,
313 ar9003_hw_iqcalibrate
316 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
318 ah->iq_caldata.calData = &iq_cal_single_sample;
320 if (AR_SREV_9300_20_OR_LATER(ah)) {
321 ah->enabled_cals |= TX_IQ_CAL;
322 if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah))
323 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
326 ah->supp_cals = IQ_MISMATCH_CAL;
329 #define OFF_UPPER_LT 24
330 #define OFF_LOWER_LT 7
332 static bool ar9003_hw_dynamic_osdac_selection(struct ath_hw *ah,
335 struct ath_common *common = ath9k_hw_common(ah);
336 int ch0_done, osdac_ch0, dc_off_ch0_i1, dc_off_ch0_q1, dc_off_ch0_i2,
337 dc_off_ch0_q2, dc_off_ch0_i3, dc_off_ch0_q3;
338 int ch1_done, osdac_ch1, dc_off_ch1_i1, dc_off_ch1_q1, dc_off_ch1_i2,
339 dc_off_ch1_q2, dc_off_ch1_i3, dc_off_ch1_q3;
340 int ch2_done, osdac_ch2, dc_off_ch2_i1, dc_off_ch2_q1, dc_off_ch2_i2,
341 dc_off_ch2_q2, dc_off_ch2_i3, dc_off_ch2_q3;
346 * Clear offset and IQ calibration, run AGC cal.
348 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
349 AR_PHY_AGC_CONTROL_OFFSET_CAL);
350 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
351 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
352 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
353 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
355 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
356 AR_PHY_AGC_CONTROL_CAL,
359 ath_dbg(common, CALIBRATE,
360 "AGC cal without offset cal failed to complete in 1ms");
365 * Allow only offset calibration and disable the others
366 * (Carrier Leak calibration, TX Filter calibration and
367 * Peak Detector offset calibration).
369 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
370 AR_PHY_AGC_CONTROL_OFFSET_CAL);
371 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
372 AR_PHY_CL_CAL_ENABLE);
373 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
374 AR_PHY_AGC_CONTROL_FLTR_CAL);
375 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
376 AR_PHY_AGC_CONTROL_PKDET_CAL);
382 while ((ch0_done == 0) || (ch1_done == 0) || (ch2_done == 0)) {
383 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3;
384 osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3;
385 osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3;
387 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
389 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
390 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
392 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
393 AR_PHY_AGC_CONTROL_CAL,
396 ath_dbg(common, CALIBRATE,
397 "DC offset cal failed to complete in 1ms");
401 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
406 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
407 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8)));
408 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
409 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8)));
410 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
411 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8)));
413 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
414 dc_off_ch0_i1 = (temp >> 26) & 0x1f;
415 dc_off_ch0_q1 = (temp >> 21) & 0x1f;
417 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
418 dc_off_ch1_i1 = (temp >> 26) & 0x1f;
419 dc_off_ch1_q1 = (temp >> 21) & 0x1f;
421 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
422 dc_off_ch2_i1 = (temp >> 26) & 0x1f;
423 dc_off_ch2_q1 = (temp >> 21) & 0x1f;
428 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
429 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8)));
430 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
431 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8)));
432 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
433 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8)));
435 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
436 dc_off_ch0_i2 = (temp >> 26) & 0x1f;
437 dc_off_ch0_q2 = (temp >> 21) & 0x1f;
439 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
440 dc_off_ch1_i2 = (temp >> 26) & 0x1f;
441 dc_off_ch1_q2 = (temp >> 21) & 0x1f;
443 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
444 dc_off_ch2_i2 = (temp >> 26) & 0x1f;
445 dc_off_ch2_q2 = (temp >> 21) & 0x1f;
450 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
451 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8)));
452 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
453 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8)));
454 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
455 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8)));
457 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
458 dc_off_ch0_i3 = (temp >> 26) & 0x1f;
459 dc_off_ch0_q3 = (temp >> 21) & 0x1f;
461 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
462 dc_off_ch1_i3 = (temp >> 26) & 0x1f;
463 dc_off_ch1_q3 = (temp >> 21) & 0x1f;
465 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
466 dc_off_ch2_i3 = (temp >> 26) & 0x1f;
467 dc_off_ch2_q3 = (temp >> 21) & 0x1f;
469 if ((dc_off_ch0_i1 > OFF_UPPER_LT) || (dc_off_ch0_i1 < OFF_LOWER_LT) ||
470 (dc_off_ch0_i2 > OFF_UPPER_LT) || (dc_off_ch0_i2 < OFF_LOWER_LT) ||
471 (dc_off_ch0_i3 > OFF_UPPER_LT) || (dc_off_ch0_i3 < OFF_LOWER_LT) ||
472 (dc_off_ch0_q1 > OFF_UPPER_LT) || (dc_off_ch0_q1 < OFF_LOWER_LT) ||
473 (dc_off_ch0_q2 > OFF_UPPER_LT) || (dc_off_ch0_q2 < OFF_LOWER_LT) ||
474 (dc_off_ch0_q3 > OFF_UPPER_LT) || (dc_off_ch0_q3 < OFF_LOWER_LT)) {
475 if (osdac_ch0 == 3) {
480 val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff;
481 val |= (osdac_ch0 << 30);
482 REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val);
490 if ((dc_off_ch1_i1 > OFF_UPPER_LT) || (dc_off_ch1_i1 < OFF_LOWER_LT) ||
491 (dc_off_ch1_i2 > OFF_UPPER_LT) || (dc_off_ch1_i2 < OFF_LOWER_LT) ||
492 (dc_off_ch1_i3 > OFF_UPPER_LT) || (dc_off_ch1_i3 < OFF_LOWER_LT) ||
493 (dc_off_ch1_q1 > OFF_UPPER_LT) || (dc_off_ch1_q1 < OFF_LOWER_LT) ||
494 (dc_off_ch1_q2 > OFF_UPPER_LT) || (dc_off_ch1_q2 < OFF_LOWER_LT) ||
495 (dc_off_ch1_q3 > OFF_UPPER_LT) || (dc_off_ch1_q3 < OFF_LOWER_LT)) {
496 if (osdac_ch1 == 3) {
501 val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff;
502 val |= (osdac_ch1 << 30);
503 REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val);
511 if ((dc_off_ch2_i1 > OFF_UPPER_LT) || (dc_off_ch2_i1 < OFF_LOWER_LT) ||
512 (dc_off_ch2_i2 > OFF_UPPER_LT) || (dc_off_ch2_i2 < OFF_LOWER_LT) ||
513 (dc_off_ch2_i3 > OFF_UPPER_LT) || (dc_off_ch2_i3 < OFF_LOWER_LT) ||
514 (dc_off_ch2_q1 > OFF_UPPER_LT) || (dc_off_ch2_q1 < OFF_LOWER_LT) ||
515 (dc_off_ch2_q2 > OFF_UPPER_LT) || (dc_off_ch2_q2 < OFF_LOWER_LT) ||
516 (dc_off_ch2_q3 > OFF_UPPER_LT) || (dc_off_ch2_q3 < OFF_LOWER_LT)) {
517 if (osdac_ch2 == 3) {
522 val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff;
523 val |= (osdac_ch2 << 30);
524 REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val);
533 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
534 AR_PHY_AGC_CONTROL_OFFSET_CAL);
535 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
538 * We don't need to check txiqcal_done here since it is always
541 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
542 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
548 * solve 4x4 linear equation used in loopback iq cal.
550 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
561 s32 f1 = cos_2phi_1 - cos_2phi_2,
562 f3 = sin_2phi_1 - sin_2phi_2,
564 s32 mag_tx, phs_tx, mag_rx, phs_rx;
565 const s32 result_shift = 1 << 15;
566 struct ath_common *common = ath9k_hw_common(ah);
568 f2 = ((f1 >> 3) * (f1 >> 3) + (f3 >> 3) * (f3 >> 3)) >> 9;
571 ath_dbg(common, CALIBRATE, "Divide by 0\n");
575 /* mag mismatch, tx */
576 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
577 /* phs mismatch, tx */
578 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
580 mag_tx = (mag_tx / f2);
581 phs_tx = (phs_tx / f2);
583 /* mag mismatch, rx */
584 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
586 /* phs mismatch, rx */
587 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
590 solved_eq[0] = mag_tx;
591 solved_eq[1] = phs_tx;
592 solved_eq[2] = mag_rx;
593 solved_eq[3] = phs_rx;
598 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
600 s32 abs_i = abs(in_re),
612 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
617 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
622 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
623 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
624 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
625 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
626 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
627 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
628 sin_2phi_1, cos_2phi_1,
629 sin_2phi_2, cos_2phi_2;
630 s32 mag_tx, phs_tx, mag_rx, phs_rx;
631 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
633 const s32 res_scale = 1 << 15;
634 const s32 delpt_shift = 1 << 8;
636 struct ath_common *common = ath9k_hw_common(ah);
638 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
639 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
640 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
642 if (i2_m_q2_a0_d0 > 0x800)
643 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
645 if (i2_p_q2_a0_d0 > 0x800)
646 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
648 if (iq_corr_a0_d0 > 0x800)
649 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
651 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
652 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
653 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
655 if (i2_m_q2_a0_d1 > 0x800)
656 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
658 if (iq_corr_a0_d1 > 0x800)
659 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
661 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
662 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
663 iq_corr_a1_d0 = iq_res[4] & 0xfff;
665 if (i2_m_q2_a1_d0 > 0x800)
666 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
668 if (i2_p_q2_a1_d0 > 0x800)
669 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
671 if (iq_corr_a1_d0 > 0x800)
672 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
674 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
675 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
676 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
678 if (i2_m_q2_a1_d1 > 0x800)
679 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
681 if (i2_p_q2_a1_d1 > 0x800)
682 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
684 if (iq_corr_a1_d1 > 0x800)
685 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
687 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
688 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
689 ath_dbg(common, CALIBRATE,
695 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
696 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
700 if ((i2_p_q2_a0_d0 < 1024) || (i2_p_q2_a0_d0 > 2047) ||
701 (i2_p_q2_a1_d0 < 0) || (i2_p_q2_a1_d1 < 0) ||
702 (i2_p_q2_a0_d0 <= i2_m_q2_a0_d0) ||
703 (i2_p_q2_a0_d0 <= iq_corr_a0_d0) ||
704 (i2_p_q2_a0_d1 <= i2_m_q2_a0_d1) ||
705 (i2_p_q2_a0_d1 <= iq_corr_a0_d1) ||
706 (i2_p_q2_a1_d0 <= i2_m_q2_a1_d0) ||
707 (i2_p_q2_a1_d0 <= iq_corr_a1_d0) ||
708 (i2_p_q2_a1_d1 <= i2_m_q2_a1_d1) ||
709 (i2_p_q2_a1_d1 <= iq_corr_a1_d1)) {
713 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
714 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
716 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
717 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
719 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
720 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
722 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
723 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
725 /* w/o analog phase shift */
726 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
727 /* w/o analog phase shift */
728 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
729 /* w/ analog phase shift */
730 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
731 /* w/ analog phase shift */
732 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
735 * force sin^2 + cos^2 = 1;
736 * find magnitude by approximation
738 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
739 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
741 if ((mag1 == 0) || (mag2 == 0)) {
742 ath_dbg(common, CALIBRATE, "Divide by 0: mag1=%d, mag2=%d\n",
747 /* normalization sin and cos by mag */
748 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
749 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
750 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
751 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
753 /* calculate IQ mismatch */
754 if (!ar9003_hw_solve_iq_cal(ah,
755 sin_2phi_1, cos_2phi_1,
756 sin_2phi_2, cos_2phi_2,
757 mag_a0_d0, phs_a0_d0,
759 phs_a1_d0, solved_eq)) {
760 ath_dbg(common, CALIBRATE,
761 "Call to ar9003_hw_solve_iq_cal() failed\n");
765 mag_tx = solved_eq[0];
766 phs_tx = solved_eq[1];
767 mag_rx = solved_eq[2];
768 phs_rx = solved_eq[3];
770 ath_dbg(common, CALIBRATE,
771 "chain %d: mag mismatch=%d phase mismatch=%d\n",
772 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
774 if (res_scale == mag_tx) {
775 ath_dbg(common, CALIBRATE,
776 "Divide by 0: mag_tx=%d, res_scale=%d\n",
781 /* calculate and quantize Tx IQ correction factor */
782 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
783 phs_corr_tx = -phs_tx;
785 q_q_coff = (mag_corr_tx * 128 / res_scale);
786 q_i_coff = (phs_corr_tx * 256 / res_scale);
788 ath_dbg(common, CALIBRATE, "tx chain %d: mag corr=%d phase corr=%d\n",
789 chain_idx, q_q_coff, q_i_coff);
800 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
802 ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n",
803 chain_idx, iqc_coeff[0]);
805 if (-mag_rx == res_scale) {
806 ath_dbg(common, CALIBRATE,
807 "Divide by 0: mag_rx=%d, res_scale=%d\n",
812 /* calculate and quantize Rx IQ correction factors */
813 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
814 phs_corr_rx = -phs_rx;
816 q_q_coff = (mag_corr_rx * 128 / res_scale);
817 q_i_coff = (phs_corr_rx * 256 / res_scale);
819 ath_dbg(common, CALIBRATE, "rx chain %d: mag corr=%d phase corr=%d\n",
820 chain_idx, q_q_coff, q_i_coff);
831 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
833 ath_dbg(common, CALIBRATE, "rx chain %d: iq corr coeff=%x\n",
834 chain_idx, iqc_coeff[1]);
839 static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
842 int mp_max = -64, max_idx = 0;
843 int mp_min = 63, min_idx = 0;
844 int mp_avg = 0, i, outlier_idx = 0, mp_count = 0;
846 /* find min/max mismatch across all calibrated gains */
847 for (i = 0; i < nmeasurement; i++) {
848 if (mp_coeff[i] > mp_max) {
849 mp_max = mp_coeff[i];
851 } else if (mp_coeff[i] < mp_min) {
852 mp_min = mp_coeff[i];
857 /* find average (exclude max abs value) */
858 for (i = 0; i < nmeasurement; i++) {
859 if ((abs(mp_coeff[i]) < abs(mp_max)) ||
860 (abs(mp_coeff[i]) < abs(mp_min))) {
861 mp_avg += mp_coeff[i];
867 * finding mean magnitude/phase if possible, otherwise
868 * just use the last value as the mean
873 mp_avg = mp_coeff[nmeasurement - 1];
876 if (abs(mp_max - mp_min) > max_delta) {
877 if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
878 outlier_idx = max_idx;
880 outlier_idx = min_idx;
882 mp_coeff[outlier_idx] = mp_avg;
886 static void ar9003_hw_tx_iq_cal_outlier_detection(struct ath_hw *ah,
890 int i, im, nmeasurement;
891 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
892 struct ath9k_hw_cal_data *caldata = ah->caldata;
894 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
895 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
896 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
897 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
898 if (!AR_SREV_9485(ah)) {
899 tx_corr_coeff[i * 2][1] =
900 tx_corr_coeff[(i * 2) + 1][1] =
901 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
903 tx_corr_coeff[i * 2][2] =
904 tx_corr_coeff[(i * 2) + 1][2] =
905 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
909 /* Load the average of 2 passes */
910 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
911 if (!(ah->txchainmask & (1 << i)))
913 nmeasurement = REG_READ_FIELD(ah,
914 AR_PHY_TX_IQCAL_STATUS_B0,
915 AR_PHY_CALIBRATED_GAINS_0);
917 if (nmeasurement > MAX_MEASUREMENT)
918 nmeasurement = MAX_MEASUREMENT;
920 /* detect outlier only if nmeasurement > 1 */
921 if (nmeasurement > 1) {
922 /* Detect magnitude outlier */
923 ar9003_hw_detect_outlier(coeff->mag_coeff[i],
924 nmeasurement, MAX_MAG_DELTA);
926 /* Detect phase outlier */
927 ar9003_hw_detect_outlier(coeff->phs_coeff[i],
928 nmeasurement, MAX_PHS_DELTA);
931 for (im = 0; im < nmeasurement; im++) {
933 coeff->iqc_coeff[0] = (coeff->mag_coeff[i][im] & 0x7f) |
934 ((coeff->phs_coeff[i][im] & 0x7f) << 7);
937 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
938 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
939 coeff->iqc_coeff[0]);
941 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
942 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
943 coeff->iqc_coeff[0]);
946 caldata->tx_corr_coeff[im][i] =
950 caldata->num_measures[i] = nmeasurement;
953 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
954 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
955 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
956 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
960 set_bit(TXIQCAL_DONE, &caldata->cal_flags);
962 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
968 static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
970 struct ath_common *common = ath9k_hw_common(ah);
973 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
974 AR_PHY_TXGAIN_FORCE);
976 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
977 AR_PHY_TXGAIN_FORCE, 0);
979 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
980 AR_PHY_TX_IQCAL_START_DO_CAL, 1);
982 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
983 AR_PHY_TX_IQCAL_START_DO_CAL, 0,
985 ath_dbg(common, CALIBRATE, "Tx IQ Cal is not completed\n");
991 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
993 struct ath_common *common = ath9k_hw_common(ah);
994 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
995 AR_PHY_TX_IQCAL_STATUS_B0,
996 AR_PHY_TX_IQCAL_STATUS_B1,
997 AR_PHY_TX_IQCAL_STATUS_B2,
999 const u_int32_t chan_info_tab[] = {
1000 AR_PHY_CHAN_INFO_TAB_0,
1001 AR_PHY_CHAN_INFO_TAB_1,
1002 AR_PHY_CHAN_INFO_TAB_2,
1009 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1010 if (!(ah->txchainmask & (1 << i)))
1013 nmeasurement = REG_READ_FIELD(ah,
1014 AR_PHY_TX_IQCAL_STATUS_B0,
1015 AR_PHY_CALIBRATED_GAINS_0);
1016 if (nmeasurement > MAX_MEASUREMENT)
1017 nmeasurement = MAX_MEASUREMENT;
1019 for (im = 0; im < nmeasurement; im++) {
1020 ath_dbg(common, CALIBRATE,
1021 "Doing Tx IQ Cal for chain %d\n", i);
1023 if (REG_READ(ah, txiqcal_status[i]) &
1024 AR_PHY_TX_IQCAL_STATUS_FAILED) {
1025 ath_dbg(common, CALIBRATE,
1026 "Tx IQ Cal failed for chain %d\n", i);
1030 for (j = 0; j < 3; j++) {
1031 u32 idx = 2 * j, offset = 4 * (3 * im + j);
1034 AR_PHY_CHAN_INFO_MEMORY,
1035 AR_PHY_CHAN_INFO_TAB_S2_READ,
1039 iq_res[idx] = REG_READ(ah,
1044 AR_PHY_CHAN_INFO_MEMORY,
1045 AR_PHY_CHAN_INFO_TAB_S2_READ,
1049 iq_res[idx + 1] = 0xffff & REG_READ(ah,
1050 chan_info_tab[i] + offset);
1052 ath_dbg(common, CALIBRATE,
1053 "IQ_RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
1054 idx, iq_res[idx], idx + 1,
1058 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
1060 ath_dbg(common, CALIBRATE,
1061 "Failed in calculation of IQ correction\n");
1065 coeff.mag_coeff[i][im] = coeff.iqc_coeff[0] & 0x7f;
1066 coeff.phs_coeff[i][im] =
1067 (coeff.iqc_coeff[0] >> 7) & 0x7f;
1069 if (coeff.mag_coeff[i][im] > 63)
1070 coeff.mag_coeff[i][im] -= 128;
1071 if (coeff.phs_coeff[i][im] > 63)
1072 coeff.phs_coeff[i][im] -= 128;
1075 ar9003_hw_tx_iq_cal_outlier_detection(ah, &coeff, is_reusable);
1080 ath_dbg(common, CALIBRATE, "Tx IQ Cal failed\n");
1084 static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
1086 struct ath9k_hw_cal_data *caldata = ah->caldata;
1087 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
1090 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
1091 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
1092 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
1093 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
1094 if (!AR_SREV_9485(ah)) {
1095 tx_corr_coeff[i * 2][1] =
1096 tx_corr_coeff[(i * 2) + 1][1] =
1097 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
1099 tx_corr_coeff[i * 2][2] =
1100 tx_corr_coeff[(i * 2) + 1][2] =
1101 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
1105 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1106 if (!(ah->txchainmask & (1 << i)))
1109 for (im = 0; im < caldata->num_measures[i]; im++) {
1111 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1112 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
1113 caldata->tx_corr_coeff[im][i]);
1115 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1116 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
1117 caldata->tx_corr_coeff[im][i]);
1121 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
1122 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
1123 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
1124 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
1127 static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
1129 int offset[8] = {0}, total = 0, test;
1132 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1133 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0x1);
1134 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1135 AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC, 0x0);
1137 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1138 AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR, 0x0);
1140 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1141 AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR, 0x0);
1143 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1144 AR_PHY_65NM_RXTX2_RXON_OVR, 0x1);
1145 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1146 AR_PHY_65NM_RXTX2_RXON, 0x0);
1148 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1149 AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE, 0x1);
1150 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1151 AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
1152 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1153 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
1155 if (AR_SREV_9330_11(ah)) {
1156 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1157 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
1160 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1161 AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
1163 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1164 AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
1167 for (i = 6; i > 0; i--) {
1168 offset[i] = BIT(i - 1);
1169 test = total + offset[i];
1172 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1173 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR,
1176 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1177 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR,
1180 agc_out = REG_READ_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1181 AR_PHY_65NM_RXRF_AGC_AGC_OUT);
1182 offset[i] = (agc_out) ? 0 : 1;
1183 total += (offset[i] << (i - 1));
1187 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1188 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, total);
1190 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1191 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR, total);
1193 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1194 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0);
1195 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1196 AR_PHY_65NM_RXTX2_RXON_OVR, 0);
1197 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1198 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
1201 static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
1202 struct ath9k_channel *chan,
1205 struct ath9k_hw_cal_data *caldata = ah->caldata;
1208 if (!AR_SREV_9462(ah) && !AR_SREV_9565(ah) && !AR_SREV_9485(ah))
1211 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && !run_rtt_cal)
1214 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1215 if (!(ah->rxchainmask & (1 << i)))
1217 ar9003_hw_manual_peak_cal(ah, i, IS_CHAN_2GHZ(chan));
1221 set_bit(SW_PKDET_DONE, &caldata->cal_flags);
1223 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && caldata) {
1224 if (IS_CHAN_2GHZ(chan)){
1225 caldata->caldac[0] = REG_READ_FIELD(ah,
1226 AR_PHY_65NM_RXRF_AGC(0),
1227 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1228 caldata->caldac[1] = REG_READ_FIELD(ah,
1229 AR_PHY_65NM_RXRF_AGC(1),
1230 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1232 caldata->caldac[0] = REG_READ_FIELD(ah,
1233 AR_PHY_65NM_RXRF_AGC(0),
1234 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1235 caldata->caldac[1] = REG_READ_FIELD(ah,
1236 AR_PHY_65NM_RXRF_AGC(1),
1237 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1242 static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
1244 u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
1247 struct ath9k_hw_cal_data *caldata = ah->caldata;
1248 bool txclcal_done = false;
1251 if (!caldata || !(ah->enabled_cals & TX_CL_CAL))
1254 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
1255 AR_PHY_AGC_CONTROL_CLC_SUCCESS);
1257 if (test_bit(TXCLCAL_DONE, &caldata->cal_flags)) {
1258 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1259 if (!(ah->txchainmask & (1 << i)))
1261 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1262 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
1263 caldata->tx_clcal[i][j]);
1265 } else if (is_reusable && txclcal_done) {
1266 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1267 if (!(ah->txchainmask & (1 << i)))
1269 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1270 caldata->tx_clcal[i][j] =
1271 REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));
1273 set_bit(TXCLCAL_DONE, &caldata->cal_flags);
1277 static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
1278 struct ath9k_channel *chan)
1280 struct ath_common *common = ath9k_hw_common(ah);
1281 struct ath9k_hw_cal_data *caldata = ah->caldata;
1282 bool txiqcal_done = false;
1283 bool is_reusable = true, status = true;
1284 bool run_rtt_cal = false, run_agc_cal;
1285 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
1287 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
1288 AR_PHY_AGC_CONTROL_FLTR_CAL |
1289 AR_PHY_AGC_CONTROL_PKDET_CAL;
1291 /* Use chip chainmask only for calibration */
1292 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1295 if (!ar9003_hw_rtt_restore(ah, chan))
1299 ath_dbg(common, CALIBRATE, "RTT calibration to be done\n");
1302 run_agc_cal = run_rtt_cal;
1305 ar9003_hw_rtt_enable(ah);
1306 ar9003_hw_rtt_set_mask(ah, 0x00);
1307 ar9003_hw_rtt_clear_hist(ah);
1312 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
1313 agc_supp_cals &= agc_ctrl;
1314 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
1315 AR_PHY_AGC_CONTROL_FLTR_CAL |
1316 AR_PHY_AGC_CONTROL_PKDET_CAL);
1317 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1319 if (ah->ah_flags & AH_FASTCC)
1324 if (ah->enabled_cals & TX_CL_CAL) {
1325 if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
1326 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
1327 AR_PHY_CL_CAL_ENABLE);
1329 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
1330 AR_PHY_CL_CAL_ENABLE);
1335 if ((IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) ||
1336 !(ah->enabled_cals & TX_IQ_CAL))
1339 /* Do Tx IQ Calibration */
1340 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1341 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1345 * For AR9485 or later chips, TxIQ cal runs as part of
1348 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1349 if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1350 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1351 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1353 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1354 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1355 txiqcal_done = run_agc_cal = true;
1359 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1360 ar9003_mci_init_cal_req(ah, &is_reusable);
1362 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1363 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
1364 /* Disable BB_active */
1365 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1367 REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
1368 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1371 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1372 /* Calibrate the AGC */
1373 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1374 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1375 AR_PHY_AGC_CONTROL_CAL);
1377 /* Poll for offset calibration complete */
1378 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1379 AR_PHY_AGC_CONTROL_CAL,
1380 0, AH_WAIT_TIMEOUT);
1382 ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
1385 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1386 REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
1390 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1391 ar9003_mci_init_cal_done(ah);
1393 if (rtt && !run_rtt_cal) {
1394 agc_ctrl |= agc_supp_cals;
1395 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1400 ar9003_hw_rtt_disable(ah);
1402 ath_dbg(common, CALIBRATE,
1403 "offset calibration failed to complete in %d ms; noisy environment?\n",
1404 AH_WAIT_TIMEOUT / 1000);
1409 ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
1410 else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1411 ar9003_hw_tx_iq_cal_reload(ah);
1413 ar9003_hw_cl_cal_post_proc(ah, is_reusable);
1415 if (run_rtt_cal && caldata) {
1417 if (!ath9k_hw_rfbus_req(ah)) {
1418 ath_err(ath9k_hw_common(ah),
1419 "Could not stop baseband\n");
1421 ar9003_hw_rtt_fill_hist(ah);
1423 if (test_bit(SW_PKDET_DONE, &caldata->cal_flags))
1424 ar9003_hw_rtt_load_hist(ah);
1427 ath9k_hw_rfbus_done(ah);
1430 ar9003_hw_rtt_disable(ah);
1433 /* Revert chainmask to runtime parameters */
1434 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1436 /* Initialize list pointers */
1437 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1439 INIT_CAL(&ah->iq_caldata);
1440 INSERT_CAL(ah, &ah->iq_caldata);
1441 ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
1443 /* Initialize current pointer to first element in list */
1444 ah->cal_list_curr = ah->cal_list;
1446 if (ah->cal_list_curr)
1447 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1450 caldata->CalValid = 0;
1455 static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
1456 struct ath9k_channel *chan)
1458 struct ath_common *common = ath9k_hw_common(ah);
1459 struct ath9k_hw_cal_data *caldata = ah->caldata;
1460 bool txiqcal_done = false;
1462 bool run_agc_cal = false, sep_iq_cal = false;
1464 /* Use chip chainmask only for calibration */
1465 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1467 if (ah->enabled_cals & TX_CL_CAL) {
1468 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1472 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1475 /* Do Tx IQ Calibration */
1476 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1477 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1481 * For AR9485 or later chips, TxIQ cal runs as part of
1482 * AGC calibration. Specifically, AR9550 in SoC chips.
1484 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1485 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1486 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) {
1487 txiqcal_done = true;
1489 txiqcal_done = false;
1498 * In the SoC family, this will run for AR9300, AR9331 and AR9340.
1501 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
1502 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1504 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1507 if (AR_SREV_9550(ah) && IS_CHAN_2GHZ(chan)) {
1508 if (!ar9003_hw_dynamic_osdac_selection(ah, txiqcal_done))
1513 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1514 if (AR_SREV_9330_11(ah))
1515 ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
1517 /* Calibrate the AGC */
1518 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1519 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1520 AR_PHY_AGC_CONTROL_CAL);
1522 /* Poll for offset calibration complete */
1523 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1524 AR_PHY_AGC_CONTROL_CAL,
1525 0, AH_WAIT_TIMEOUT);
1529 ath_dbg(common, CALIBRATE,
1530 "offset calibration failed to complete in %d ms; noisy environment?\n",
1531 AH_WAIT_TIMEOUT / 1000);
1536 ar9003_hw_tx_iq_cal_post_proc(ah, false);
1538 /* Revert chainmask to runtime parameters */
1539 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1541 /* Initialize list pointers */
1542 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1544 INIT_CAL(&ah->iq_caldata);
1545 INSERT_CAL(ah, &ah->iq_caldata);
1546 ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
1548 /* Initialize current pointer to first element in list */
1549 ah->cal_list_curr = ah->cal_list;
1551 if (ah->cal_list_curr)
1552 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1555 caldata->CalValid = 0;
1560 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
1562 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1563 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1565 if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
1566 priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
1568 priv_ops->init_cal = ar9003_hw_init_cal_soc;
1570 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
1571 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
1573 ops->calibrate = ar9003_hw_calibrate;