drivers/net/wireless/ath/ath5k/reset.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
   5  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
   6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  */
  21
  22 /*****************************\
  23   Reset functions and helpers
  24 \*****************************/
  25
  26 #include <asm/unaligned.h>
  27
  28 #include <linux/pci.h>          /* To determine if a card is pci-e */
  29 #include <linux/log2.h>
  30 #include "ath5k.h"
  31 #include "reg.h"
  32 #include "base.h"
  33 #include "debug.h"
  34
  35
  36 /******************\
  37 * Helper functions *
  38 \******************/
  39
  40 /*
  41  * Check if a register write has been completed
  42  */
  43 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
  44                               bool is_set)
  45 {
  46         int i;
  47         u32 data;
  48
  49         for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
  50                 data = ath5k_hw_reg_read(ah, reg);
  51                 if (is_set && (data & flag))
  52                         break;
  53                 else if ((data & flag) == val)
  54                         break;
  55                 udelay(15);
  56         }
  57
  58         return (i <= 0) ? -EAGAIN : 0;
  59 }
  60
  61
  62 /*************************\
  63 * Clock related functions *
  64 \*************************/
  65
  66 /**
  67  * ath5k_hw_htoclock - Translate usec to hw clock units
  68  *
  69  * @ah: The &struct ath5k_hw
  70  * @usec: value in microseconds
  71  */
  72 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
  73 {
  74         struct ath_common *common = ath5k_hw_common(ah);
  75         return usec * common->clockrate;
  76 }
  77
  78 /**
  79  * ath5k_hw_clocktoh - Translate hw clock units to usec
  80  * @clock: value in hw clock units
  81  */
  82 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
  83 {
  84         struct ath_common *common = ath5k_hw_common(ah);
  85         return clock / common->clockrate;
  86 }
  87
  88 /**
  89  * ath5k_hw_set_clockrate - Set common->clockrate for the current channel
  90  *
  91  * @ah: The &struct ath5k_hw
  92  */
  93 void ath5k_hw_set_clockrate(struct ath5k_hw *ah)
  94 {
  95         struct ieee80211_channel *channel = ah->ah_current_channel;
  96         struct ath_common *common = ath5k_hw_common(ah);
  97         int clock;
  98
  99         if (channel->hw_value & CHANNEL_5GHZ)
 100                 clock = 40; /* 802.11a */
 101         else if (channel->hw_value & CHANNEL_CCK)
 102                 clock = 22; /* 802.11b */
 103         else
 104                 clock = 44; /* 802.11g */
 105
 106         /* Clock rate in turbo modes is twice the normal rate */
 107         if (channel->hw_value & CHANNEL_TURBO)
 108                 clock *= 2;
 109
 110         common->clockrate = clock;
 111 }
 112
 113 /*
 114  * If there is an external 32KHz crystal available, use it
 115  * as ref. clock instead of 32/40MHz clock and baseband clocks
 116  * to save power during sleep or restore normal 32/40MHz
 117  * operation.
 118  *
 119  * XXX: When operating on 32KHz certain PHY registers (27 - 31,
 120  *      123 - 127) require delay on access.
 121  */
 122 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 123 {
 124         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 125         u32 scal, spending, usec32;
 126
 127         /* Only set 32KHz settings if we have an external
 128          * 32KHz crystal present */
 129         if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
 130         AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
 131         enable) {
 132
 133                 /* 1 usec/cycle */
 134                 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
 135                 /* Set up tsf increment on each cycle */
 136                 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
 137
 138                 /* Set baseband sleep control registers
 139                  * and sleep control rate */
 140                 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 141
 142                 if ((ah->ah_radio == AR5K_RF5112) ||
 143                 (ah->ah_radio == AR5K_RF5413) ||
 144                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
 145                         spending = 0x14;
 146                 else
 147                         spending = 0x18;
 148                 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 149
 150                 if ((ah->ah_radio == AR5K_RF5112) ||
 151                 (ah->ah_radio == AR5K_RF5413) ||
 152                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
 153                         ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
 154                         ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
 155                         ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
 156                         ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
 157                         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 158                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
 159                 } else {
 160                         ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
 161                         ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
 162                         ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
 163                         ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
 164                         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 165                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
 166                 }
 167
 168                 /* Enable sleep clock operation */
 169                 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
 170                                 AR5K_PCICFG_SLEEP_CLOCK_EN);
 171
 172         } else {
 173
 174                 /* Disable sleep clock operation and
 175                  * restore default parameters */
 176                 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
 177                                 AR5K_PCICFG_SLEEP_CLOCK_EN);
 178
 179                 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 180                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
 181
 182                 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 183                 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
 184
 185                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
 186                         scal = AR5K_PHY_SCAL_32MHZ_2417;
 187                 else if (ee->ee_is_hb63)
 188                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
 189                 else
 190                         scal = AR5K_PHY_SCAL_32MHZ;
 191                 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
 192
 193                 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
 194                 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
 195
 196                 if ((ah->ah_radio == AR5K_RF5112) ||
 197                 (ah->ah_radio == AR5K_RF5413) ||
 198                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
 199                         spending = 0x14;
 200                 else
 201                         spending = 0x18;
 202                 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 203
 204                 if ((ah->ah_radio == AR5K_RF5112) ||
 205                 (ah->ah_radio == AR5K_RF5413))
 206                         usec32 = 39;
 207                 else
 208                         usec32 = 31;
 209                 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
 210
 211                 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
 212         }
 213 }
 214
 215
 216 /*********************\
 217 * Reset/Sleep control *
 218 \*********************/
 219
 220 /*
 221  * Reset chipset
 222  */
 223 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 224 {
 225         int ret;
 226         u32 mask = val ? val : ~0U;
 227
 228         /* Read-and-clear RX Descriptor Pointer*/
 229         ath5k_hw_reg_read(ah, AR5K_RXDP);
 230
 231         /*
 232          * Reset the device and wait until success
 233          */
 234         ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
 235
 236         /* Wait at least 128 PCI clocks */
 237         udelay(15);
 238
 239         if (ah->ah_version == AR5K_AR5210) {
 240                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
 241                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
 242                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
 243                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
 244         } else {
 245                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 246                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 247         }
 248
 249         ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
 250
 251         /*
 252          * Reset configuration register (for hw byte-swap). Note that this
 253          * is only set for big endian. We do the necessary magic in
 254          * AR5K_INIT_CFG.
 255          */
 256         if ((val & AR5K_RESET_CTL_PCU) == 0)
 257                 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
 258
 259         return ret;
 260 }
 261
 262 /*
 263  * Sleep control
 264  */
 265 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
 266                               bool set_chip, u16 sleep_duration)
 267 {
 268         unsigned int i;
 269         u32 staid, data;
 270
 271         staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
 272
 273         switch (mode) {
 274         case AR5K_PM_AUTO:
 275                 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
 276                 /* fallthrough */
 277         case AR5K_PM_NETWORK_SLEEP:
 278                 if (set_chip)
 279                         ath5k_hw_reg_write(ah,
 280                                 AR5K_SLEEP_CTL_SLE_ALLOW |
 281                                 sleep_duration,
 282                                 AR5K_SLEEP_CTL);
 283
 284                 staid |= AR5K_STA_ID1_PWR_SV;
 285                 break;
 286
 287         case AR5K_PM_FULL_SLEEP:
 288                 if (set_chip)
 289                         ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
 290                                 AR5K_SLEEP_CTL);
 291
 292                 staid |= AR5K_STA_ID1_PWR_SV;
 293                 break;
 294
 295         case AR5K_PM_AWAKE:
 296
 297                 staid &= ~AR5K_STA_ID1_PWR_SV;
 298
 299                 if (!set_chip)
 300                         goto commit;
 301
 302                 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
 303
 304                 /* If card is down we 'll get 0xffff... so we
 305                  * need to clean this up before we write the register
 306                  */
 307                 if (data & 0xffc00000)
 308                         data = 0;
 309                 else
 310                         /* Preserve sleep duration etc */
 311                         data = data & ~AR5K_SLEEP_CTL_SLE;
 312
 313                 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
 314                                                         AR5K_SLEEP_CTL);
 315                 udelay(15);
 316
 317                 for (i = 200; i > 0; i--) {
 318                         /* Check if the chip did wake up */
 319                         if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
 320                                         AR5K_PCICFG_SPWR_DN) == 0)
 321                                 break;
 322
 323                         /* Wait a bit and retry */
 324                         udelay(50);
 325                         ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
 326                                                         AR5K_SLEEP_CTL);
 327                 }
 328
 329                 /* Fail if the chip didn't wake up */
 330                 if (i == 0)
 331                         return -EIO;
 332
 333                 break;
 334
 335         default:
 336                 return -EINVAL;
 337         }
 338
 339 commit:
 340         ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
 341
 342         return 0;
 343 }
 344
 345 /*
 346  * Put device on hold
 347  *
 348  * Put MAC and Baseband on warm reset and
 349  * keep that state (don't clean sleep control
 350  * register). After this MAC and Baseband are
 351  * disabled and a full reset is needed to come
 352  * back. This way we save as much power as possible
 353  * without putting the card on full sleep.
 354  */
 355 int ath5k_hw_on_hold(struct ath5k_hw *ah)
 356 {
 357         struct pci_dev *pdev = ah->ah_sc->pdev;
 358         u32 bus_flags;
 359         int ret;
 360
 361         /* Make sure device is awake */
 362         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 363         if (ret) {
 364                 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
 365                 return ret;
 366         }
 367
 368         /*
 369          * Put chipset on warm reset...
 370          *
 371          * Note: putting PCI core on warm reset on PCI-E cards
 372          * results card to hang and always return 0xffff... so
 373          * we ingore that flag for PCI-E cards. On PCI cards
 374          * this flag gets cleared after 64 PCI clocks.
 375          */
 376         bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
 377
 378         if (ah->ah_version == AR5K_AR5210) {
 379                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 380                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
 381                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
 382                         mdelay(2);
 383         } else {
 384                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 385                         AR5K_RESET_CTL_BASEBAND | bus_flags);
 386         }
 387
 388         if (ret) {
 389                 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
 390                 return -EIO;
 391         }
 392
 393         /* ...wakeup again!*/
 394         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 395         if (ret) {
 396                 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
 397                 return ret;
 398         }
 399
 400         return ret;
 401 }
 402
 403 /*
 404  * Bring up MAC + PHY Chips and program PLL
 405  * TODO: Half/Quarter rate support
 406  */
 407 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 408 {
 409         struct pci_dev *pdev = ah->ah_sc->pdev;
 410         u32 turbo, mode, clock, bus_flags;
 411         int ret;
 412
 413         turbo = 0;
 414         mode = 0;
 415         clock = 0;
 416
 417         /* Wakeup the device */
 418         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 419         if (ret) {
 420                 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
 421                 return ret;
 422         }
 423
 424         /*
 425          * Put chipset on warm reset...
 426          *
 427          * Note: putting PCI core on warm reset on PCI-E cards
 428          * results card to hang and always return 0xffff... so
 429          * we ingore that flag for PCI-E cards. On PCI cards
 430          * this flag gets cleared after 64 PCI clocks.
 431          */
 432         bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
 433
 434         if (ah->ah_version == AR5K_AR5210) {
 435                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 436                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
 437                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
 438                         mdelay(2);
 439         } else {
 440                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 441                         AR5K_RESET_CTL_BASEBAND | bus_flags);
 442         }
 443
 444         if (ret) {
 445                 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
 446                 return -EIO;
 447         }
 448
 449         /* ...wakeup again!...*/
 450         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 451         if (ret) {
 452                 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
 453                 return ret;
 454         }
 455
 456         /* ...clear reset control register and pull device out of
 457          * warm reset */
 458         if (ath5k_hw_nic_reset(ah, 0)) {
 459                 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
 460                 return -EIO;
 461         }
 462
 463         /* On initialization skip PLL programming since we don't have
 464          * a channel / mode set yet */
 465         if (initial)
 466                 return 0;
 467
 468         if (ah->ah_version != AR5K_AR5210) {
 469                 /*
 470                  * Get channel mode flags
 471                  */
 472
 473                 if (ah->ah_radio >= AR5K_RF5112) {
 474                         mode = AR5K_PHY_MODE_RAD_RF5112;
 475                         clock = AR5K_PHY_PLL_RF5112;
 476                 } else {
 477                         mode = AR5K_PHY_MODE_RAD_RF5111;        /*Zero*/
 478                         clock = AR5K_PHY_PLL_RF5111;            /*Zero*/
 479                 }
 480
 481                 if (flags & CHANNEL_2GHZ) {
 482                         mode |= AR5K_PHY_MODE_FREQ_2GHZ;
 483                         clock |= AR5K_PHY_PLL_44MHZ;
 484
 485                         if (flags & CHANNEL_CCK) {
 486                                 mode |= AR5K_PHY_MODE_MOD_CCK;
 487                         } else if (flags & CHANNEL_OFDM) {
 488                                 /* XXX Dynamic OFDM/CCK is not supported by the
 489                                  * AR5211 so we set MOD_OFDM for plain g (no
 490                                  * CCK headers) operation. We need to test
 491                                  * this, 5211 might support ofdm-only g after
 492                                  * all, there are also initial register values
 493                                  * in the code for g mode (see initvals.c). */
 494                                 if (ah->ah_version == AR5K_AR5211)
 495                                         mode |= AR5K_PHY_MODE_MOD_OFDM;
 496                                 else
 497                                         mode |= AR5K_PHY_MODE_MOD_DYN;
 498                         } else {
 499                                 ATH5K_ERR(ah->ah_sc,
 500                                         "invalid radio modulation mode\n");
 501                                 return -EINVAL;
 502                         }
 503                 } else if (flags & CHANNEL_5GHZ) {
 504                         mode |= AR5K_PHY_MODE_FREQ_5GHZ;
 505
 506                         if (ah->ah_radio == AR5K_RF5413)
 507                                 clock = AR5K_PHY_PLL_40MHZ_5413;
 508                         else
 509                                 clock |= AR5K_PHY_PLL_40MHZ;
 510
 511                         if (flags & CHANNEL_OFDM)
 512                                 mode |= AR5K_PHY_MODE_MOD_OFDM;
 513                         else {
 514                                 ATH5K_ERR(ah->ah_sc,
 515                                         "invalid radio modulation mode\n");
 516                                 return -EINVAL;
 517                         }
 518                 } else {
 519                         ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
 520                         return -EINVAL;
 521                 }
 522
 523                 if (flags & CHANNEL_TURBO)
 524                         turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
 525         } else { /* Reset the device */
 526
 527                 /* ...enable Atheros turbo mode if requested */
 528                 if (flags & CHANNEL_TURBO)
 529                         ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
 530                                         AR5K_PHY_TURBO);
 531         }
 532
 533         if (ah->ah_version != AR5K_AR5210) {
 534
 535                 /* ...update PLL if needed */
 536                 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
 537                         ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
 538                         udelay(300);
 539                 }
 540
 541                 /* ...set the PHY operating mode */
 542                 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
 543                 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
 544         }
 545
 546         return 0;
 547 }
 548
 549
 550 /**************************************\
 551 * Post-initvals register modifications *
 552 \**************************************/
 553
 554 /* TODO: Half/Quarter rate */
 555 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
 556                                 struct ieee80211_channel *channel)
 557 {
 558         if (ah->ah_version == AR5K_AR5212 &&
 559             ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 560
 561                 /* Setup ADC control */
 562                 ath5k_hw_reg_write(ah,
 563                                 (AR5K_REG_SM(2,
 564                                 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
 565                                 AR5K_REG_SM(2,
 566                                 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
 567                                 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
 568                                 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
 569                                 AR5K_PHY_ADC_CTL);
 570
 571
 572
 573                 /* Disable barker RSSI threshold */
 574                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
 575                                 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
 576
 577                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
 578                         AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
 579
 580                 /* Set the mute mask */
 581                 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
 582         }
 583
 584         /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
 585         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
 586                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
 587
 588         /* Enable DCU double buffering */
 589         if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
 590                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
 591                                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
 592
 593         /* Set DAC/ADC delays */
 594         if (ah->ah_version == AR5K_AR5212) {
 595                 u32 scal;
 596                 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 597                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
 598                         scal = AR5K_PHY_SCAL_32MHZ_2417;
 599                 else if (ee->ee_is_hb63)
 600                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
 601                 else
 602                         scal = AR5K_PHY_SCAL_32MHZ;
 603                 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
 604         }
 605
 606         /* Set fast ADC */
 607         if ((ah->ah_radio == AR5K_RF5413) ||
 608         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
 609                 u32 fast_adc = true;
 610
 611                 if (channel->center_freq == 2462 ||
 612                 channel->center_freq == 2467)
 613                         fast_adc = 0;
 614
 615                 /* Only update if needed */
 616                 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
 617                                 ath5k_hw_reg_write(ah, fast_adc,
 618                                                 AR5K_PHY_FAST_ADC);
 619         }
 620
 621         /* Fix for first revision of the RF5112 RF chipset */
 622         if (ah->ah_radio == AR5K_RF5112 &&
 623                         ah->ah_radio_5ghz_revision <
 624                         AR5K_SREV_RAD_5112A) {
 625                 u32 data;
 626                 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
 627                                 AR5K_PHY_CCKTXCTL);
 628                 if (channel->hw_value & CHANNEL_5GHZ)
 629                         data = 0xffb81020;
 630                 else
 631                         data = 0xffb80d20;
 632                 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
 633         }
 634
 635         if ((ah->ah_radio == AR5K_RF5112) &&
 636         (ah->ah_mac_srev < AR5K_SREV_AR5211)) {
 637                 u32 usec_reg;
 638                 /* 5311 has different tx/rx latency masks
 639                  * from 5211, since we deal 5311 the same
 640                  * as 5211 when setting initvals, shift
 641                  * values here to their proper locations */
 642                 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
 643                 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
 644                                 AR5K_USEC_32 |
 645                                 AR5K_USEC_TX_LATENCY_5211 |
 646                                 AR5K_REG_SM(29,
 647                                 AR5K_USEC_RX_LATENCY_5210)),
 648                                 AR5K_USEC_5211);
 649                 /* Clear QCU/DCU clock gating register */
 650                 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
 651                 /* Set DAC/ADC delays */
 652                 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
 653                 /* Enable PCU FIFO corruption ECO */
 654                 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
 655                                         AR5K_DIAG_SW_ECO_ENABLE);
 656         }
 657 }
 658
 659 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
 660                 struct ieee80211_channel *channel, u8 ee_mode)
 661 {
 662         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 663         s16 cck_ofdm_pwr_delta;
 664
 665         /* TODO: Add support for AR5210 EEPROM */
 666         if (ah->ah_version == AR5K_AR5210)
 667                 return;
 668
 669         /* Adjust power delta for channel 14 */
 670         if (channel->center_freq == 2484)
 671                 cck_ofdm_pwr_delta =
 672                         ((ee->ee_cck_ofdm_power_delta -
 673                         ee->ee_scaled_cck_delta) * 2) / 10;
 674         else
 675                 cck_ofdm_pwr_delta =
 676                         (ee->ee_cck_ofdm_power_delta * 2) / 10;
 677
 678         /* Set CCK to OFDM power delta on tx power
 679          * adjustment register */
 680         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 681                 if (channel->hw_value == CHANNEL_G)
 682                         ath5k_hw_reg_write(ah,
 683                         AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
 684                                 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
 685                         AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
 686                                 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
 687                                 AR5K_PHY_TX_PWR_ADJ);
 688                 else
 689                         ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
 690         } else {
 691                 /* For older revs we scale power on sw during tx power
 692                  * setup */
 693                 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
 694                 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
 695                                                 ee->ee_cck_ofdm_gain_delta;
 696         }
 697
 698         /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
 699          * too */
 700         ath5k_hw_set_antenna_switch(ah, ee_mode);
 701
 702         /* Noise floor threshold */
 703         ath5k_hw_reg_write(ah,
 704                 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
 705                 AR5K_PHY_NFTHRES);
 706
 707         if ((channel->hw_value & CHANNEL_TURBO) &&
 708         (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
 709                 /* Switch settling time (Turbo) */
 710                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 711                                 AR5K_PHY_SETTLING_SWITCH,
 712                                 ee->ee_switch_settling_turbo[ee_mode]);
 713
 714                 /* Tx/Rx attenuation (Turbo) */
 715                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
 716                                 AR5K_PHY_GAIN_TXRX_ATTEN,
 717                                 ee->ee_atn_tx_rx_turbo[ee_mode]);
 718
 719                 /* ADC/PGA desired size (Turbo) */
 720                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 721                                 AR5K_PHY_DESIRED_SIZE_ADC,
 722                                 ee->ee_adc_desired_size_turbo[ee_mode]);
 723
 724                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 725                                 AR5K_PHY_DESIRED_SIZE_PGA,
 726                                 ee->ee_pga_desired_size_turbo[ee_mode]);
 727
 728                 /* Tx/Rx margin (Turbo) */
 729                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
 730                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 731                                 ee->ee_margin_tx_rx_turbo[ee_mode]);
 732
 733         } else {
 734                 /* Switch settling time */
 735                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 736                                 AR5K_PHY_SETTLING_SWITCH,
 737                                 ee->ee_switch_settling[ee_mode]);
 738
 739                 /* Tx/Rx attenuation */
 740                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
 741                                 AR5K_PHY_GAIN_TXRX_ATTEN,
 742                                 ee->ee_atn_tx_rx[ee_mode]);
 743
 744                 /* ADC/PGA desired size */
 745                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 746                                 AR5K_PHY_DESIRED_SIZE_ADC,
 747                                 ee->ee_adc_desired_size[ee_mode]);
 748
 749                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 750                                 AR5K_PHY_DESIRED_SIZE_PGA,
 751                                 ee->ee_pga_desired_size[ee_mode]);
 752
 753                 /* Tx/Rx margin */
 754                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 755                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
 756                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 757                                 ee->ee_margin_tx_rx[ee_mode]);
 758         }
 759
 760         /* XPA delays */
 761         ath5k_hw_reg_write(ah,
 762                 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
 763                 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
 764                 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
 765                 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
 766
 767         /* XLNA delay */
 768         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
 769                         AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
 770                         ee->ee_tx_end2xlna_enable[ee_mode]);
 771
 772         /* Thresh64 (ANI) */
 773         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
 774                         AR5K_PHY_NF_THRESH62,
 775                         ee->ee_thr_62[ee_mode]);
 776
 777         /* False detect backoff for channels
 778          * that have spur noise. Write the new
 779          * cyclic power RSSI threshold. */
 780         if (ath5k_hw_chan_has_spur_noise(ah, channel))
 781                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
 782                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
 783                                 AR5K_INIT_CYCRSSI_THR1 +
 784                                 ee->ee_false_detect[ee_mode]);
 785         else
 786                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
 787                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
 788                                 AR5K_INIT_CYCRSSI_THR1);
 789
 790         /* I/Q correction (set enable bit last to match HAL sources) */
 791         /* TODO: Per channel i/q infos ? */
 792         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
 793                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
 794                             ee->ee_i_cal[ee_mode]);
 795                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
 796                             ee->ee_q_cal[ee_mode]);
 797                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
 798         }
 799
 800         /* Heavy clipping -disable for now */
 801         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
 802                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
 803 }
 804
 805
 806 /*********************\
 807 * Main reset function *
 808 \*********************/
 809
 810 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
 811         struct ieee80211_channel *channel, bool change_channel)
 812 {
 813         struct ath_common *common = ath5k_hw_common(ah);
 814         u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
 815         u8 mode, freq, ee_mode;
 816         int i, ret;
 817
 818         ee_mode = 0;
 819         staid1_flags = 0;
 820         tsf_up = 0;
 821         tsf_lo = 0;
 822         freq = 0;
 823         mode = 0;
 824
 825         /*
 826          * Save some registers before a reset
 827          */
 828         /*DCU/Antenna selection not available on 5210*/
 829         if (ah->ah_version != AR5K_AR5210) {
 830
 831                 switch (channel->hw_value & CHANNEL_MODES) {
 832                 case CHANNEL_A:
 833                         mode = AR5K_MODE_11A;
 834                         freq = AR5K_INI_RFGAIN_5GHZ;
 835                         ee_mode = AR5K_EEPROM_MODE_11A;
 836                         break;
 837                 case CHANNEL_G:
 838                         mode = AR5K_MODE_11G;
 839                         freq = AR5K_INI_RFGAIN_2GHZ;
 840                         ee_mode = AR5K_EEPROM_MODE_11G;
 841                         break;
 842                 case CHANNEL_B:
 843                         mode = AR5K_MODE_11B;
 844                         freq = AR5K_INI_RFGAIN_2GHZ;
 845                         ee_mode = AR5K_EEPROM_MODE_11B;
 846                         break;
 847                 case CHANNEL_T:
 848                         mode = AR5K_MODE_11A_TURBO;
 849                         freq = AR5K_INI_RFGAIN_5GHZ;
 850                         ee_mode = AR5K_EEPROM_MODE_11A;
 851                         break;
 852                 case CHANNEL_TG:
 853                         if (ah->ah_version == AR5K_AR5211) {
 854                                 ATH5K_ERR(ah->ah_sc,
 855                                         "TurboG mode not available on 5211");
 856                                 return -EINVAL;
 857                         }
 858                         mode = AR5K_MODE_11G_TURBO;
 859                         freq = AR5K_INI_RFGAIN_2GHZ;
 860                         ee_mode = AR5K_EEPROM_MODE_11G;
 861                         break;
 862                 case CHANNEL_XR:
 863                         if (ah->ah_version == AR5K_AR5211) {
 864                                 ATH5K_ERR(ah->ah_sc,
 865                                         "XR mode not available on 5211");
 866                                 return -EINVAL;
 867                         }
 868                         mode = AR5K_MODE_XR;
 869                         freq = AR5K_INI_RFGAIN_5GHZ;
 870                         ee_mode = AR5K_EEPROM_MODE_11A;
 871                         break;
 872                 default:
 873                         ATH5K_ERR(ah->ah_sc,
 874                                 "invalid channel: %d\n", channel->center_freq);
 875                         return -EINVAL;
 876                 }
 877
 878                 if (change_channel) {
 879                         /*
 880                          * Save frame sequence count
 881                          * For revs. after Oahu, only save
 882                          * seq num for DCU 0 (Global seq num)
 883                          */
 884                         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 885
 886                                 for (i = 0; i < 10; i++)
 887                                         s_seq[i] = ath5k_hw_reg_read(ah,
 888                                                 AR5K_QUEUE_DCU_SEQNUM(i));
 889
 890                         } else {
 891                                 s_seq[0] = ath5k_hw_reg_read(ah,
 892                                                 AR5K_QUEUE_DCU_SEQNUM(0));
 893                         }
 894
 895                         /* TSF accelerates on AR5211 during reset
 896                          * As a workaround save it here and restore
 897                          * it later so that it's back in time after
 898                          * reset. This way it'll get re-synced on the
 899                          * next beacon without breaking ad-hoc.
 900                          *
 901                          * On AR5212 TSF is almost preserved across a
 902                          * reset so it stays back in time anyway and
 903                          * we don't have to save/restore it.
 904                          *
 905                          * XXX: Since this breaks power saving we have
 906                          * to disable power saving until we receive the
 907                          * next beacon, so we can resync beacon timers */
 908                         if (ah->ah_version == AR5K_AR5211) {
 909                                 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
 910                                 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
 911                         }
 912                 }
 913
 914                 if (ah->ah_version == AR5K_AR5212) {
 915                         /* Restore normal 32/40MHz clock operation
 916                          * to avoid register access delay on certain
 917                          * PHY registers */
 918                         ath5k_hw_set_sleep_clock(ah, false);
 919
 920                         /* Since we are going to write rf buffer
 921                          * check if we have any pending gain_F
 922                          * optimization settings */
 923                         if (change_channel && ah->ah_rf_banks != NULL)
 924                                 ath5k_hw_gainf_calibrate(ah);
 925                 }
 926         }
 927
 928         /*GPIOs*/
 929         s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
 930                                         AR5K_PCICFG_LEDSTATE;
 931         s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
 932         s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
 933
 934         /* AR5K_STA_ID1 flags, only preserve antenna
 935          * settings and ack/cts rate mode */
 936         staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
 937                         (AR5K_STA_ID1_DEFAULT_ANTENNA |
 938                         AR5K_STA_ID1_DESC_ANTENNA |
 939                         AR5K_STA_ID1_RTS_DEF_ANTENNA |
 940                         AR5K_STA_ID1_ACKCTS_6MB |
 941                         AR5K_STA_ID1_BASE_RATE_11B |
 942                         AR5K_STA_ID1_SELFGEN_DEF_ANT);
 943
 944         /* Wakeup the device */
 945         ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
 946         if (ret)
 947                 return ret;
 948
 949         /* PHY access enable */
 950         if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
 951                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
 952         else
 953                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
 954                                                         AR5K_PHY(0));
 955
 956         /* Write initial settings */
 957         ret = ath5k_hw_write_initvals(ah, mode, change_channel);
 958         if (ret)
 959                 return ret;
 960
 961         /*
 962          * Tweak initval settings for revised
 963          * chipsets and add some more config
 964          * bits
 965          */
 966         ath5k_hw_tweak_initval_settings(ah, channel);
 967
 968         /* Commit values from EEPROM */
 969         ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
 970
 971
 972         /*
 973          * Restore saved values
 974          */
 975
 976         /*DCU/Antenna selection not available on 5210*/
 977         if (ah->ah_version != AR5K_AR5210) {
 978
 979                 if (change_channel) {
 980                         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 981                                 for (i = 0; i < 10; i++)
 982                                         ath5k_hw_reg_write(ah, s_seq[i],
 983                                                 AR5K_QUEUE_DCU_SEQNUM(i));
 984                         } else {
 985                                 ath5k_hw_reg_write(ah, s_seq[0],
 986                                         AR5K_QUEUE_DCU_SEQNUM(0));
 987                         }
 988
 989
 990                         if (ah->ah_version == AR5K_AR5211) {
 991                                 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
 992                                 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
 993                         }
 994                 }
 995         }
 996
 997         /* Ledstate */
 998         AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
 999
1000         /* Gpio settings */
1001         ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1002         ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1003
1004         /* Restore sta_id flags and preserve our mac address*/
1005         ath5k_hw_reg_write(ah,
1006                            get_unaligned_le32(common->macaddr),
1007                            AR5K_STA_ID0);
1008         ath5k_hw_reg_write(ah,
1009                            staid1_flags | get_unaligned_le16(common->macaddr + 4),
1010                            AR5K_STA_ID1);
1011
1012
1013         /*
1014          * Initialize PCU
1015          */
1016         ath5k_hw_pcu_init(ah, op_mode, mode);
1017
1018         /* Clear any pending interrupts
1019          * PISR/SISR Not available on 5210 */
1020         if (ah->ah_version != AR5K_AR5210)
1021                 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1022
1023         /*
1024          * Initialize PHY
1025          */
1026         ret = ath5k_hw_phy_init(ah, channel, mode, ee_mode, freq);
1027         if (ret) {
1028                 ATH5K_ERR(ah->ah_sc,
1029                         "failed to initialize PHY (%i) !\n", ret);
1030                 return ret;
1031         }
1032
1033         /*
1034          * Configure QCUs/DCUs
1035          */
1036         ret = ath5k_hw_init_queues(ah);
1037         if (ret)
1038                 return ret;
1039
1040
1041         /*
1042          * Initialize DMA/Interrupts
1043          */
1044         ath5k_hw_dma_init(ah);
1045
1046
1047         /* Enable 32KHz clock function for AR5212+ chips
1048          * Set clocks to 32KHz operation and use an
1049          * external 32KHz crystal when sleeping if one
1050          * exists */
1051         if (ah->ah_version == AR5K_AR5212 &&
1052             op_mode != NL80211_IFTYPE_AP)
1053                 ath5k_hw_set_sleep_clock(ah, true);
1054
1055         /*
1056          * Disable beacons and reset the TSF
1057          */
1058         AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1059         ath5k_hw_reset_tsf(ah);
1060         return 0;
1061 }