2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
19 #include <linux/pci-aspm.h>
27 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
28 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
29 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
30 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
31 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
32 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
33 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
34 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
35 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
36 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
37 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
38 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
39 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
40 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
41 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
42 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
43 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
44 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
45 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
49 /* return bus cachesize in 4B word units */
50 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
52 struct ath5k_softc *sc = (struct ath5k_softc *) common->priv;
55 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
59 * This check was put in to avoid "unplesant" consequences if
60 * the bootrom has not fully initialized all PCI devices.
61 * Sometimes the cache line size register is not set
65 *csz = L1_CACHE_BYTES >> 2; /* Use the default size */
68 /* Common ath_bus_opts structure */
69 static const struct ath_bus_ops ath_pci_bus_ops = {
70 .ath_bus_type = ATH_PCI,
71 .read_cachesize = ath5k_pci_read_cachesize,
74 /********************\
75 * PCI Initialization *
76 \********************/
79 ath5k_pci_probe(struct pci_dev *pdev,
80 const struct pci_device_id *id)
83 struct ath5k_softc *sc;
84 struct ieee80211_hw *hw;
89 * L0s needs to be disabled on all ath5k cards.
91 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
92 * by default in the future in 2.6.36) this will also mean both L1 and
93 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
94 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
95 * though but cannot currently undue the effect of a blacklist, for
96 * details you can read pcie_aspm_sanity_check() and see how it adjusts
97 * the device link capability.
99 * It may be possible in the future to implement some PCI API to allow
100 * drivers to override blacklists for pre 1.1 PCIe but for now it is
101 * best to accept that both L0s and L1 will be disabled completely for
102 * distributions shipping with CONFIG_PCIEASPM rather than having this
103 * issue present. Motivation for adding this new API will be to help
104 * with power consumption for some of these devices.
106 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
108 ret = pci_enable_device(pdev);
110 dev_err(&pdev->dev, "can't enable device\n");
114 /* XXX 32-bit addressing only */
115 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
117 dev_err(&pdev->dev, "32-bit DMA not available\n");
122 * Cache line size is used to size and align various
123 * structures used to communicate with the hardware.
125 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
128 * Linux 2.4.18 (at least) writes the cache line size
129 * register as a 16-bit wide register which is wrong.
130 * We must have this setup properly for rx buffer
131 * DMA to work so force a reasonable value here if it
134 csz = L1_CACHE_BYTES >> 2;
135 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
138 * The default setting of latency timer yields poor results,
139 * set it to the value used by other systems. It may be worth
140 * tweaking this setting more.
142 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
144 /* Enable bus mastering */
145 pci_set_master(pdev);
148 * Disable the RETRY_TIMEOUT register (0x41) to keep
149 * PCI Tx retries from interfering with C3 CPU state.
151 pci_write_config_byte(pdev, 0x41, 0);
153 ret = pci_request_region(pdev, 0, "ath5k");
155 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
159 mem = pci_iomap(pdev, 0, 0);
161 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
167 * Allocate hw (mac80211 main struct)
168 * and hw->priv (driver private data)
170 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
172 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
177 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
182 sc->dev = &pdev->dev;
184 sc->devid = id->device;
185 sc->iobase = mem; /* So we can unmap it on detach */
188 ret = ath5k_init_softc(sc, &ath_pci_bus_ops);
192 /* Set private data */
193 pci_set_drvdata(pdev, hw);
197 ieee80211_free_hw(hw);
199 pci_iounmap(pdev, mem);
201 pci_release_region(pdev, 0);
203 pci_disable_device(pdev);
208 static void __devexit
209 ath5k_pci_remove(struct pci_dev *pdev)
211 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
212 struct ath5k_softc *sc = hw->priv;
214 ath5k_deinit_softc(sc);
215 pci_iounmap(pdev, sc->iobase);
216 pci_release_region(pdev, 0);
217 pci_disable_device(pdev);
218 ieee80211_free_hw(hw);
221 #ifdef CONFIG_PM_SLEEP
222 static int ath5k_pci_suspend(struct device *dev)
224 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
230 static int ath5k_pci_resume(struct device *dev)
232 struct pci_dev *pdev = to_pci_dev(dev);
233 struct ath5k_softc *sc = pci_get_drvdata(pdev);
236 * Suspend/Resume resets the PCI configuration space, so we have to
237 * re-disable the RETRY_TIMEOUT register (0x41) to keep
238 * PCI Tx retries from interfering with C3 CPU state
240 pci_write_config_byte(pdev, 0x41, 0);
242 ath5k_led_enable(sc);
246 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
247 #define ATH5K_PM_OPS (&ath5k_pm_ops)
249 #define ATH5K_PM_OPS NULL
250 #endif /* CONFIG_PM_SLEEP */
252 static struct pci_driver ath5k_pci_driver = {
253 .name = KBUILD_MODNAME,
254 .id_table = ath5k_pci_id_table,
255 .probe = ath5k_pci_probe,
256 .remove = __devexit_p(ath5k_pci_remove),
257 .driver.pm = ATH5K_PM_OPS,
261 * Module init/exit functions
268 ret = pci_register_driver(&ath5k_pci_driver);
270 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
280 pci_unregister_driver(&ath5k_pci_driver);
283 module_init(init_ath5k_pci);
284 module_exit(exit_ath5k_pci);