2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
64 static int modparam_nohwcrypt;
65 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
68 static int modparam_all_channels;
69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
108 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
111 static const struct ath5k_srev_name srev_names[] = {
112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150 static const struct ieee80211_rate ath5k_rates[] = {
152 .hw_value = ATH5K_RATE_CODE_1M, },
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 .hw_value = ATH5K_RATE_CODE_6M,
169 .hw_value = ATH5K_RATE_CODE_9M,
172 .hw_value = ATH5K_RATE_CODE_12M,
175 .hw_value = ATH5K_RATE_CODE_18M,
178 .hw_value = ATH5K_RATE_CODE_24M,
181 .hw_value = ATH5K_RATE_CODE_36M,
184 .hw_value = ATH5K_RATE_CODE_48M,
187 .hw_value = ATH5K_RATE_CODE_54M,
193 * Prototypes - PCI stack related functions
195 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
199 static int ath5k_pci_suspend(struct device *dev);
200 static int ath5k_pci_resume(struct device *dev);
202 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
203 #define ATH5K_PM_OPS (&ath5k_pm_ops)
205 #define ATH5K_PM_OPS NULL
206 #endif /* CONFIG_PM */
208 static struct pci_driver ath5k_pci_driver = {
209 .name = KBUILD_MODNAME,
210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
213 .driver.pm = ATH5K_PM_OPS,
219 * Prototypes - MAC 802.11 stack related functions
221 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
222 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
224 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
225 static int ath5k_reset_wake(struct ath5k_softc *sc);
226 static int ath5k_start(struct ieee80211_hw *hw);
227 static void ath5k_stop(struct ieee80211_hw *hw);
228 static int ath5k_add_interface(struct ieee80211_hw *hw,
229 struct ieee80211_vif *vif);
230 static void ath5k_remove_interface(struct ieee80211_hw *hw,
231 struct ieee80211_vif *vif);
232 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
233 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
234 struct netdev_hw_addr_list *mc_list);
235 static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 unsigned int changed_flags,
237 unsigned int *new_flags,
239 static int ath5k_set_key(struct ieee80211_hw *hw,
240 enum set_key_cmd cmd,
241 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
242 struct ieee80211_key_conf *key);
243 static int ath5k_get_stats(struct ieee80211_hw *hw,
244 struct ieee80211_low_level_stats *stats);
245 static int ath5k_get_survey(struct ieee80211_hw *hw,
246 int idx, struct survey_info *survey);
247 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
248 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
249 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
250 static int ath5k_beacon_update(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif);
252 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
253 struct ieee80211_vif *vif,
254 struct ieee80211_bss_conf *bss_conf,
256 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
257 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
261 static const struct ieee80211_ops ath5k_hw_ops = {
263 .start = ath5k_start,
265 .add_interface = ath5k_add_interface,
266 .remove_interface = ath5k_remove_interface,
267 .config = ath5k_config,
268 .prepare_multicast = ath5k_prepare_multicast,
269 .configure_filter = ath5k_configure_filter,
270 .set_key = ath5k_set_key,
271 .get_stats = ath5k_get_stats,
272 .get_survey = ath5k_get_survey,
274 .get_tsf = ath5k_get_tsf,
275 .set_tsf = ath5k_set_tsf,
276 .reset_tsf = ath5k_reset_tsf,
277 .bss_info_changed = ath5k_bss_info_changed,
278 .sw_scan_start = ath5k_sw_scan_start,
279 .sw_scan_complete = ath5k_sw_scan_complete,
280 .set_coverage_class = ath5k_set_coverage_class,
284 * Prototypes - Internal functions
287 static int ath5k_attach(struct pci_dev *pdev,
288 struct ieee80211_hw *hw);
289 static void ath5k_detach(struct pci_dev *pdev,
290 struct ieee80211_hw *hw);
291 /* Channel/mode setup */
292 static inline short ath5k_ieee2mhz(short chan);
293 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
294 struct ieee80211_channel *channels,
297 static int ath5k_setup_bands(struct ieee80211_hw *hw);
298 static int ath5k_chan_set(struct ath5k_softc *sc,
299 struct ieee80211_channel *chan);
300 static void ath5k_setcurmode(struct ath5k_softc *sc,
302 static void ath5k_mode_setup(struct ath5k_softc *sc);
304 /* Descriptor setup */
305 static int ath5k_desc_alloc(struct ath5k_softc *sc,
306 struct pci_dev *pdev);
307 static void ath5k_desc_free(struct ath5k_softc *sc,
308 struct pci_dev *pdev);
310 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
311 struct ath5k_buf *bf);
312 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
313 struct ath5k_buf *bf,
314 struct ath5k_txq *txq, int padsize);
315 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
316 struct ath5k_buf *bf)
321 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
323 dev_kfree_skb_any(bf->skb);
327 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
328 struct ath5k_buf *bf)
330 struct ath5k_hw *ah = sc->ah;
331 struct ath_common *common = ath5k_hw_common(ah);
336 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
338 dev_kfree_skb_any(bf->skb);
344 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
345 int qtype, int subtype);
346 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
347 static int ath5k_beaconq_config(struct ath5k_softc *sc);
348 static void ath5k_txq_drainq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
351 static void ath5k_txq_release(struct ath5k_softc *sc);
353 static int ath5k_rx_start(struct ath5k_softc *sc);
354 static void ath5k_rx_stop(struct ath5k_softc *sc);
355 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
356 struct ath5k_desc *ds,
358 struct ath5k_rx_status *rs);
359 static void ath5k_tasklet_rx(unsigned long data);
361 static void ath5k_tx_processq(struct ath5k_softc *sc,
362 struct ath5k_txq *txq);
363 static void ath5k_tasklet_tx(unsigned long data);
364 /* Beacon handling */
365 static int ath5k_beacon_setup(struct ath5k_softc *sc,
366 struct ath5k_buf *bf);
367 static void ath5k_beacon_send(struct ath5k_softc *sc);
368 static void ath5k_beacon_config(struct ath5k_softc *sc);
369 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
370 static void ath5k_tasklet_beacon(unsigned long data);
371 static void ath5k_tasklet_ani(unsigned long data);
373 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
375 u64 tsf = ath5k_hw_get_tsf64(ah);
377 if ((tsf & 0x7fff) < rstamp)
380 return (tsf & ~0x7fff) | rstamp;
383 /* Interrupt handling */
384 static int ath5k_init(struct ath5k_softc *sc);
385 static int ath5k_stop_locked(struct ath5k_softc *sc);
386 static int ath5k_stop_hw(struct ath5k_softc *sc);
387 static irqreturn_t ath5k_intr(int irq, void *dev_id);
388 static void ath5k_tasklet_reset(unsigned long data);
390 static void ath5k_tasklet_calibrate(unsigned long data);
393 * Module init/exit functions
402 ret = pci_register_driver(&ath5k_pci_driver);
404 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
414 pci_unregister_driver(&ath5k_pci_driver);
416 ath5k_debug_finish();
419 module_init(init_ath5k_pci);
420 module_exit(exit_ath5k_pci);
423 /********************\
424 * PCI Initialization *
425 \********************/
428 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
430 const char *name = "xxxxx";
433 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
434 if (srev_names[i].sr_type != type)
437 if ((val & 0xf0) == srev_names[i].sr_val)
438 name = srev_names[i].sr_name;
440 if ((val & 0xff) == srev_names[i].sr_val) {
441 name = srev_names[i].sr_name;
448 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
450 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
451 return ath5k_hw_reg_read(ah, reg_offset);
454 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
456 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
457 ath5k_hw_reg_write(ah, val, reg_offset);
460 static const struct ath_ops ath5k_common_ops = {
461 .read = ath5k_ioread32,
462 .write = ath5k_iowrite32,
466 ath5k_pci_probe(struct pci_dev *pdev,
467 const struct pci_device_id *id)
470 struct ath5k_softc *sc;
471 struct ath_common *common;
472 struct ieee80211_hw *hw;
476 ret = pci_enable_device(pdev);
478 dev_err(&pdev->dev, "can't enable device\n");
482 /* XXX 32-bit addressing only */
483 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
485 dev_err(&pdev->dev, "32-bit DMA not available\n");
490 * Cache line size is used to size and align various
491 * structures used to communicate with the hardware.
493 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
496 * Linux 2.4.18 (at least) writes the cache line size
497 * register as a 16-bit wide register which is wrong.
498 * We must have this setup properly for rx buffer
499 * DMA to work so force a reasonable value here if it
502 csz = L1_CACHE_BYTES >> 2;
503 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
506 * The default setting of latency timer yields poor results,
507 * set it to the value used by other systems. It may be worth
508 * tweaking this setting more.
510 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
512 /* Enable bus mastering */
513 pci_set_master(pdev);
516 * Disable the RETRY_TIMEOUT register (0x41) to keep
517 * PCI Tx retries from interfering with C3 CPU state.
519 pci_write_config_byte(pdev, 0x41, 0);
521 ret = pci_request_region(pdev, 0, "ath5k");
523 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
527 mem = pci_iomap(pdev, 0, 0);
529 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
535 * Allocate hw (mac80211 main struct)
536 * and hw->priv (driver private data)
538 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
540 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
545 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
547 /* Initialize driver private data */
548 SET_IEEE80211_DEV(hw, &pdev->dev);
549 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
550 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
551 IEEE80211_HW_SIGNAL_DBM;
553 hw->wiphy->interface_modes =
554 BIT(NL80211_IFTYPE_AP) |
555 BIT(NL80211_IFTYPE_STATION) |
556 BIT(NL80211_IFTYPE_ADHOC) |
557 BIT(NL80211_IFTYPE_MESH_POINT);
559 hw->extra_tx_headroom = 2;
560 hw->channel_change_time = 5000;
565 ath5k_debug_init_device(sc);
568 * Mark the device as detached to avoid processing
569 * interrupts until setup is complete.
571 __set_bit(ATH_STAT_INVALID, sc->status);
573 sc->iobase = mem; /* So we can unmap it on detach */
574 sc->opmode = NL80211_IFTYPE_STATION;
576 mutex_init(&sc->lock);
577 spin_lock_init(&sc->rxbuflock);
578 spin_lock_init(&sc->txbuflock);
579 spin_lock_init(&sc->block);
581 /* Set private data */
582 pci_set_drvdata(pdev, hw);
584 /* Setup interrupt handler */
585 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
587 ATH5K_ERR(sc, "request_irq failed\n");
591 /*If we passed the test malloc a ath5k_hw struct*/
592 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
595 ATH5K_ERR(sc, "out of memory\n");
600 sc->ah->ah_iobase = sc->iobase;
601 common = ath5k_hw_common(sc->ah);
602 common->ops = &ath5k_common_ops;
605 common->cachelsz = csz << 2; /* convert to bytes */
607 /* Initialize device */
608 ret = ath5k_hw_attach(sc);
613 /* set up multi-rate retry capabilities */
614 if (sc->ah->ah_version == AR5K_AR5212) {
616 hw->max_rate_tries = 11;
619 /* Finish private driver data initialization */
620 ret = ath5k_attach(pdev, hw);
624 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
625 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
627 sc->ah->ah_phy_revision);
629 if (!sc->ah->ah_single_chip) {
630 /* Single chip radio (!RF5111) */
631 if (sc->ah->ah_radio_5ghz_revision &&
632 !sc->ah->ah_radio_2ghz_revision) {
633 /* No 5GHz support -> report 2GHz radio */
634 if (!test_bit(AR5K_MODE_11A,
635 sc->ah->ah_capabilities.cap_mode)) {
636 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
637 ath5k_chip_name(AR5K_VERSION_RAD,
638 sc->ah->ah_radio_5ghz_revision),
639 sc->ah->ah_radio_5ghz_revision);
640 /* No 2GHz support (5110 and some
641 * 5Ghz only cards) -> report 5Ghz radio */
642 } else if (!test_bit(AR5K_MODE_11B,
643 sc->ah->ah_capabilities.cap_mode)) {
644 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
645 ath5k_chip_name(AR5K_VERSION_RAD,
646 sc->ah->ah_radio_5ghz_revision),
647 sc->ah->ah_radio_5ghz_revision);
648 /* Multiband radio */
650 ATH5K_INFO(sc, "RF%s multiband radio found"
652 ath5k_chip_name(AR5K_VERSION_RAD,
653 sc->ah->ah_radio_5ghz_revision),
654 sc->ah->ah_radio_5ghz_revision);
657 /* Multi chip radio (RF5111 - RF2111) ->
658 * report both 2GHz/5GHz radios */
659 else if (sc->ah->ah_radio_5ghz_revision &&
660 sc->ah->ah_radio_2ghz_revision){
661 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_5ghz_revision),
664 sc->ah->ah_radio_5ghz_revision);
665 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
666 ath5k_chip_name(AR5K_VERSION_RAD,
667 sc->ah->ah_radio_2ghz_revision),
668 sc->ah->ah_radio_2ghz_revision);
673 /* ready to process interrupts */
674 __clear_bit(ATH_STAT_INVALID, sc->status);
678 ath5k_hw_detach(sc->ah);
680 free_irq(pdev->irq, sc);
684 ieee80211_free_hw(hw);
686 pci_iounmap(pdev, mem);
688 pci_release_region(pdev, 0);
690 pci_disable_device(pdev);
695 static void __devexit
696 ath5k_pci_remove(struct pci_dev *pdev)
698 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
699 struct ath5k_softc *sc = hw->priv;
701 ath5k_debug_finish_device(sc);
702 ath5k_detach(pdev, hw);
703 ath5k_hw_detach(sc->ah);
705 free_irq(pdev->irq, sc);
706 pci_iounmap(pdev, sc->iobase);
707 pci_release_region(pdev, 0);
708 pci_disable_device(pdev);
709 ieee80211_free_hw(hw);
713 static int ath5k_pci_suspend(struct device *dev)
715 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
716 struct ath5k_softc *sc = hw->priv;
722 static int ath5k_pci_resume(struct device *dev)
724 struct pci_dev *pdev = to_pci_dev(dev);
725 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
726 struct ath5k_softc *sc = hw->priv;
729 * Suspend/Resume resets the PCI configuration space, so we have to
730 * re-disable the RETRY_TIMEOUT register (0x41) to keep
731 * PCI Tx retries from interfering with C3 CPU state
733 pci_write_config_byte(pdev, 0x41, 0);
735 ath5k_led_enable(sc);
738 #endif /* CONFIG_PM */
741 /***********************\
742 * Driver Initialization *
743 \***********************/
745 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
747 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
748 struct ath5k_softc *sc = hw->priv;
749 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
751 return ath_reg_notifier_apply(wiphy, request, regulatory);
755 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
757 struct ath5k_softc *sc = hw->priv;
758 struct ath5k_hw *ah = sc->ah;
759 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
760 u8 mac[ETH_ALEN] = {};
763 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
766 * Check if the MAC has multi-rate retry support.
767 * We do this by trying to setup a fake extended
768 * descriptor. MAC's that don't have support will
769 * return false w/o doing anything. MAC's that do
770 * support it will return true w/o doing anything.
772 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
776 __set_bit(ATH_STAT_MRRETRY, sc->status);
779 * Collect the channel list. The 802.11 layer
780 * is resposible for filtering this list based
781 * on settings like the phy mode and regulatory
782 * domain restrictions.
784 ret = ath5k_setup_bands(hw);
786 ATH5K_ERR(sc, "can't get channels\n");
790 /* NB: setup here so ath5k_rate_update is happy */
791 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
792 ath5k_setcurmode(sc, AR5K_MODE_11A);
794 ath5k_setcurmode(sc, AR5K_MODE_11B);
797 * Allocate tx+rx descriptors and populate the lists.
799 ret = ath5k_desc_alloc(sc, pdev);
801 ATH5K_ERR(sc, "can't allocate descriptors\n");
806 * Allocate hardware transmit queues: one queue for
807 * beacon frames and one data queue for each QoS
808 * priority. Note that hw functions handle reseting
809 * these queues at the needed time.
811 ret = ath5k_beaconq_setup(ah);
813 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
817 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
818 if (IS_ERR(sc->cabq)) {
819 ATH5K_ERR(sc, "can't setup cab queue\n");
820 ret = PTR_ERR(sc->cabq);
824 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
825 if (IS_ERR(sc->txq)) {
826 ATH5K_ERR(sc, "can't setup xmit queue\n");
827 ret = PTR_ERR(sc->txq);
831 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
832 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
833 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
834 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
835 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
836 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
838 ret = ath5k_eeprom_read_mac(ah, mac);
840 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
845 SET_IEEE80211_PERM_ADDR(hw, mac);
846 /* All MAC address bits matter for ACKs */
847 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
848 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
850 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
851 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
853 ATH5K_ERR(sc, "can't initialize regulatory system\n");
857 ret = ieee80211_register_hw(hw);
859 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
863 if (!ath_is_world_regd(regulatory))
864 regulatory_hint(hw->wiphy, regulatory->alpha2);
870 ath5k_txq_release(sc);
872 ath5k_hw_release_tx_queue(ah, sc->bhalq);
874 ath5k_desc_free(sc, pdev);
880 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
882 struct ath5k_softc *sc = hw->priv;
885 * NB: the order of these is important:
886 * o call the 802.11 layer before detaching ath5k_hw to
887 * insure callbacks into the driver to delete global
888 * key cache entries can be handled
889 * o reclaim the tx queue data structures after calling
890 * the 802.11 layer as we'll get called back to reclaim
891 * node state and potentially want to use them
892 * o to cleanup the tx queues the hal is called, so detach
894 * XXX: ??? detach ath5k_hw ???
895 * Other than that, it's straightforward...
897 ieee80211_unregister_hw(hw);
898 ath5k_desc_free(sc, pdev);
899 ath5k_txq_release(sc);
900 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
901 ath5k_unregister_leds(sc);
904 * NB: can't reclaim these until after ieee80211_ifdetach
905 * returns because we'll get called back to reclaim node
906 * state and potentially want to use them.
913 /********************\
914 * Channel/mode setup *
915 \********************/
918 * Convert IEEE channel number to MHz frequency.
921 ath5k_ieee2mhz(short chan)
923 if (chan <= 14 || chan >= 27)
924 return ieee80211chan2mhz(chan);
926 return 2212 + chan * 20;
930 * Returns true for the channel numbers used without all_channels modparam.
932 static bool ath5k_is_standard_channel(short chan)
934 return ((chan <= 14) ||
936 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
938 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
940 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
944 ath5k_copy_channels(struct ath5k_hw *ah,
945 struct ieee80211_channel *channels,
949 unsigned int i, count, size, chfreq, freq, ch;
951 if (!test_bit(mode, ah->ah_modes))
956 case AR5K_MODE_11A_TURBO:
957 /* 1..220, but 2GHz frequencies are filtered by check_channel */
959 chfreq = CHANNEL_5GHZ;
963 case AR5K_MODE_11G_TURBO:
965 chfreq = CHANNEL_2GHZ;
968 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
972 for (i = 0, count = 0; i < size && max > 0; i++) {
974 freq = ath5k_ieee2mhz(ch);
976 /* Check if channel is supported by the chipset */
977 if (!ath5k_channel_ok(ah, freq, chfreq))
980 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
983 /* Write channel info and increment counter */
984 channels[count].center_freq = freq;
985 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
986 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
990 channels[count].hw_value = chfreq | CHANNEL_OFDM;
992 case AR5K_MODE_11A_TURBO:
993 case AR5K_MODE_11G_TURBO:
994 channels[count].hw_value = chfreq |
995 CHANNEL_OFDM | CHANNEL_TURBO;
998 channels[count].hw_value = CHANNEL_B;
1009 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1013 for (i = 0; i < AR5K_MAX_RATES; i++)
1014 sc->rate_idx[b->band][i] = -1;
1016 for (i = 0; i < b->n_bitrates; i++) {
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1018 if (b->bitrates[i].hw_value_short)
1019 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1024 ath5k_setup_bands(struct ieee80211_hw *hw)
1026 struct ath5k_softc *sc = hw->priv;
1027 struct ath5k_hw *ah = sc->ah;
1028 struct ieee80211_supported_band *sband;
1029 int max_c, count_c = 0;
1032 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1033 max_c = ARRAY_SIZE(sc->channels);
1036 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1037 sband->band = IEEE80211_BAND_2GHZ;
1038 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1040 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1042 memcpy(sband->bitrates, &ath5k_rates[0],
1043 sizeof(struct ieee80211_rate) * 12);
1044 sband->n_bitrates = 12;
1046 sband->channels = sc->channels;
1047 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1048 AR5K_MODE_11G, max_c);
1050 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1051 count_c = sband->n_channels;
1053 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1055 memcpy(sband->bitrates, &ath5k_rates[0],
1056 sizeof(struct ieee80211_rate) * 4);
1057 sband->n_bitrates = 4;
1059 /* 5211 only supports B rates and uses 4bit rate codes
1060 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1063 if (ah->ah_version == AR5K_AR5211) {
1064 for (i = 0; i < 4; i++) {
1065 sband->bitrates[i].hw_value =
1066 sband->bitrates[i].hw_value & 0xF;
1067 sband->bitrates[i].hw_value_short =
1068 sband->bitrates[i].hw_value_short & 0xF;
1072 sband->channels = sc->channels;
1073 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1074 AR5K_MODE_11B, max_c);
1076 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1077 count_c = sband->n_channels;
1080 ath5k_setup_rate_idx(sc, sband);
1082 /* 5GHz band, A mode */
1083 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1084 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1085 sband->band = IEEE80211_BAND_5GHZ;
1086 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1088 memcpy(sband->bitrates, &ath5k_rates[4],
1089 sizeof(struct ieee80211_rate) * 8);
1090 sband->n_bitrates = 8;
1092 sband->channels = &sc->channels[count_c];
1093 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1094 AR5K_MODE_11A, max_c);
1096 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1098 ath5k_setup_rate_idx(sc, sband);
1100 ath5k_debug_dump_bands(sc);
1106 * Set/change channels. We always reset the chip.
1107 * To accomplish this we must first cleanup any pending DMA,
1108 * then restart stuff after a la ath5k_init.
1110 * Called with sc->lock.
1113 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1115 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1116 sc->curchan->center_freq, chan->center_freq);
1119 * To switch channels clear any pending DMA operations;
1120 * wait long enough for the RX fifo to drain, reset the
1121 * hardware at the new frequency, and then re-enable
1122 * the relevant bits of the h/w.
1124 return ath5k_reset(sc, chan);
1128 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1132 if (mode == AR5K_MODE_11A) {
1133 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1135 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1140 ath5k_mode_setup(struct ath5k_softc *sc)
1142 struct ath5k_hw *ah = sc->ah;
1145 /* configure rx filter */
1146 rfilt = sc->filter_flags;
1147 ath5k_hw_set_rx_filter(ah, rfilt);
1149 if (ath5k_hw_hasbssidmask(ah))
1150 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1152 /* configure operational mode */
1153 ath5k_hw_set_opmode(ah, sc->opmode);
1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1156 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1160 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1164 /* return base rate on errors */
1165 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1166 "hw_rix out of bounds: %x\n", hw_rix))
1169 rix = sc->rate_idx[sc->curband->band][hw_rix];
1170 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1181 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1183 struct ath_common *common = ath5k_hw_common(sc->ah);
1184 struct sk_buff *skb;
1187 * Allocate buffer with headroom_needed space for the
1188 * fake physical layer header at the start.
1190 skb = ath_rxbuf_alloc(common,
1195 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1196 common->rx_bufsize);
1200 *skb_addr = pci_map_single(sc->pdev,
1201 skb->data, common->rx_bufsize,
1202 PCI_DMA_FROMDEVICE);
1203 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1204 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1212 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1214 struct ath5k_hw *ah = sc->ah;
1215 struct sk_buff *skb = bf->skb;
1216 struct ath5k_desc *ds;
1219 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1226 * Setup descriptors. For receive we always terminate
1227 * the descriptor list with a self-linked entry so we'll
1228 * not get overrun under high load (as can happen with a
1229 * 5212 when ANI processing enables PHY error frames).
1231 * To insure the last descriptor is self-linked we create
1232 * each descriptor as self-linked and add it to the end. As
1233 * each additional descriptor is added the previous self-linked
1234 * entry is ``fixed'' naturally. This should be safe even
1235 * if DMA is happening. When processing RX interrupts we
1236 * never remove/process the last, self-linked, entry on the
1237 * descriptor list. This insures the hardware always has
1238 * someplace to write a new frame.
1241 ds->ds_link = bf->daddr; /* link to self */
1242 ds->ds_data = bf->skbaddr;
1243 ah->ah_setup_rx_desc(ah, ds,
1244 skb_tailroom(skb), /* buffer size */
1247 if (sc->rxlink != NULL)
1248 *sc->rxlink = bf->daddr;
1249 sc->rxlink = &ds->ds_link;
1253 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1255 struct ieee80211_hdr *hdr;
1256 enum ath5k_pkt_type htype;
1259 hdr = (struct ieee80211_hdr *)skb->data;
1260 fc = hdr->frame_control;
1262 if (ieee80211_is_beacon(fc))
1263 htype = AR5K_PKT_TYPE_BEACON;
1264 else if (ieee80211_is_probe_resp(fc))
1265 htype = AR5K_PKT_TYPE_PROBE_RESP;
1266 else if (ieee80211_is_atim(fc))
1267 htype = AR5K_PKT_TYPE_ATIM;
1268 else if (ieee80211_is_pspoll(fc))
1269 htype = AR5K_PKT_TYPE_PSPOLL;
1271 htype = AR5K_PKT_TYPE_NORMAL;
1277 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1278 struct ath5k_txq *txq, int padsize)
1280 struct ath5k_hw *ah = sc->ah;
1281 struct ath5k_desc *ds = bf->desc;
1282 struct sk_buff *skb = bf->skb;
1283 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1284 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1285 struct ieee80211_rate *rate;
1286 unsigned int mrr_rate[3], mrr_tries[3];
1293 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1295 /* XXX endianness */
1296 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1299 rate = ieee80211_get_tx_rate(sc->hw, info);
1301 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1302 flags |= AR5K_TXDESC_NOACK;
1304 rc_flags = info->control.rates[0].flags;
1305 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1306 rate->hw_value_short : rate->hw_value;
1310 /* FIXME: If we are in g mode and rate is a CCK rate
1311 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1312 * from tx power (value is in dB units already) */
1313 if (info->control.hw_key) {
1314 keyidx = info->control.hw_key->hw_key_idx;
1315 pktlen += info->control.hw_key->icv_len;
1317 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1318 flags |= AR5K_TXDESC_RTSENA;
1319 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1320 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1321 sc->vif, pktlen, info));
1323 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1324 flags |= AR5K_TXDESC_CTSENA;
1325 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1326 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1327 sc->vif, pktlen, info));
1329 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1330 ieee80211_get_hdrlen_from_skb(skb), padsize,
1331 get_hw_packet_type(skb),
1332 (sc->power_level * 2),
1334 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1335 cts_rate, duration);
1339 memset(mrr_rate, 0, sizeof(mrr_rate));
1340 memset(mrr_tries, 0, sizeof(mrr_tries));
1341 for (i = 0; i < 3; i++) {
1342 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1346 mrr_rate[i] = rate->hw_value;
1347 mrr_tries[i] = info->control.rates[i + 1].count;
1350 ah->ah_setup_mrr_tx_desc(ah, ds,
1351 mrr_rate[0], mrr_tries[0],
1352 mrr_rate[1], mrr_tries[1],
1353 mrr_rate[2], mrr_tries[2]);
1356 ds->ds_data = bf->skbaddr;
1358 spin_lock_bh(&txq->lock);
1359 list_add_tail(&bf->list, &txq->q);
1360 if (txq->link == NULL) /* is this first packet? */
1361 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1362 else /* no, so only link it */
1363 *txq->link = bf->daddr;
1365 txq->link = &ds->ds_link;
1366 ath5k_hw_start_tx_dma(ah, txq->qnum);
1368 spin_unlock_bh(&txq->lock);
1372 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1376 /*******************\
1377 * Descriptors setup *
1378 \*******************/
1381 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1383 struct ath5k_desc *ds;
1384 struct ath5k_buf *bf;
1389 /* allocate descriptors */
1390 sc->desc_len = sizeof(struct ath5k_desc) *
1391 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1392 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1393 if (sc->desc == NULL) {
1394 ATH5K_ERR(sc, "can't allocate descriptors\n");
1399 da = sc->desc_daddr;
1400 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1401 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1403 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1404 sizeof(struct ath5k_buf), GFP_KERNEL);
1406 ATH5K_ERR(sc, "can't allocate bufptr\n");
1412 INIT_LIST_HEAD(&sc->rxbuf);
1413 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1416 list_add_tail(&bf->list, &sc->rxbuf);
1419 INIT_LIST_HEAD(&sc->txbuf);
1420 sc->txbuf_len = ATH_TXBUF;
1421 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1422 da += sizeof(*ds)) {
1425 list_add_tail(&bf->list, &sc->txbuf);
1435 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1442 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1444 struct ath5k_buf *bf;
1446 ath5k_txbuf_free(sc, sc->bbuf);
1447 list_for_each_entry(bf, &sc->txbuf, list)
1448 ath5k_txbuf_free(sc, bf);
1449 list_for_each_entry(bf, &sc->rxbuf, list)
1450 ath5k_rxbuf_free(sc, bf);
1452 /* Free memory associated with all descriptors */
1453 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1467 static struct ath5k_txq *
1468 ath5k_txq_setup(struct ath5k_softc *sc,
1469 int qtype, int subtype)
1471 struct ath5k_hw *ah = sc->ah;
1472 struct ath5k_txq *txq;
1473 struct ath5k_txq_info qi = {
1474 .tqi_subtype = subtype,
1475 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1476 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1477 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1482 * Enable interrupts only for EOL and DESC conditions.
1483 * We mark tx descriptors to receive a DESC interrupt
1484 * when a tx queue gets deep; otherwise waiting for the
1485 * EOL to reap descriptors. Note that this is done to
1486 * reduce interrupt load and this only defers reaping
1487 * descriptors, never transmitting frames. Aside from
1488 * reducing interrupts this also permits more concurrency.
1489 * The only potential downside is if the tx queue backs
1490 * up in which case the top half of the kernel may backup
1491 * due to a lack of tx descriptors.
1493 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1494 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1495 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1498 * NB: don't print a message, this happens
1499 * normally on parts with too few tx queues
1501 return ERR_PTR(qnum);
1503 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1504 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1505 qnum, ARRAY_SIZE(sc->txqs));
1506 ath5k_hw_release_tx_queue(ah, qnum);
1507 return ERR_PTR(-EINVAL);
1509 txq = &sc->txqs[qnum];
1513 INIT_LIST_HEAD(&txq->q);
1514 spin_lock_init(&txq->lock);
1517 return &sc->txqs[qnum];
1521 ath5k_beaconq_setup(struct ath5k_hw *ah)
1523 struct ath5k_txq_info qi = {
1524 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1525 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1526 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1527 /* NB: for dynamic turbo, don't enable any other interrupts */
1528 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1531 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1535 ath5k_beaconq_config(struct ath5k_softc *sc)
1537 struct ath5k_hw *ah = sc->ah;
1538 struct ath5k_txq_info qi;
1541 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1545 if (sc->opmode == NL80211_IFTYPE_AP ||
1546 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1548 * Always burst out beacon and CAB traffic
1549 * (aifs = cwmin = cwmax = 0)
1554 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1556 * Adhoc mode; backoff between 0 and (2 * cw_min).
1560 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1563 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1564 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1565 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1567 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1569 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1570 "hardware queue!\n", __func__);
1573 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1577 /* reconfigure cabq with ready time to 80% of beacon_interval */
1578 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1582 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1583 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1587 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1593 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1595 struct ath5k_buf *bf, *bf0;
1598 * NB: this assumes output has been stopped and
1599 * we do not need to block ath5k_tx_tasklet
1601 spin_lock_bh(&txq->lock);
1602 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1603 ath5k_debug_printtxbuf(sc, bf);
1605 ath5k_txbuf_free(sc, bf);
1607 spin_lock_bh(&sc->txbuflock);
1608 list_move_tail(&bf->list, &sc->txbuf);
1610 spin_unlock_bh(&sc->txbuflock);
1613 spin_unlock_bh(&txq->lock);
1617 * Drain the transmit queues and reclaim resources.
1620 ath5k_txq_cleanup(struct ath5k_softc *sc)
1622 struct ath5k_hw *ah = sc->ah;
1625 /* XXX return value */
1626 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1627 /* don't touch the hardware if marked invalid */
1628 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1629 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1630 ath5k_hw_get_txdp(ah, sc->bhalq));
1631 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1632 if (sc->txqs[i].setup) {
1633 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1634 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1637 ath5k_hw_get_txdp(ah,
1643 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1644 if (sc->txqs[i].setup)
1645 ath5k_txq_drainq(sc, &sc->txqs[i]);
1649 ath5k_txq_release(struct ath5k_softc *sc)
1651 struct ath5k_txq *txq = sc->txqs;
1654 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1656 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1669 * Enable the receive h/w following a reset.
1672 ath5k_rx_start(struct ath5k_softc *sc)
1674 struct ath5k_hw *ah = sc->ah;
1675 struct ath_common *common = ath5k_hw_common(ah);
1676 struct ath5k_buf *bf;
1679 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1681 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1682 common->cachelsz, common->rx_bufsize);
1684 spin_lock_bh(&sc->rxbuflock);
1686 list_for_each_entry(bf, &sc->rxbuf, list) {
1687 ret = ath5k_rxbuf_setup(sc, bf);
1689 spin_unlock_bh(&sc->rxbuflock);
1693 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1694 ath5k_hw_set_rxdp(ah, bf->daddr);
1695 spin_unlock_bh(&sc->rxbuflock);
1697 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1698 ath5k_mode_setup(sc); /* set filters, etc. */
1699 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1707 * Disable the receive h/w in preparation for a reset.
1710 ath5k_rx_stop(struct ath5k_softc *sc)
1712 struct ath5k_hw *ah = sc->ah;
1714 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1715 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1716 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1718 ath5k_debug_printrxbuffs(sc, ah);
1720 sc->rxlink = NULL; /* just in case */
1724 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1725 struct sk_buff *skb, struct ath5k_rx_status *rs)
1727 struct ath5k_hw *ah = sc->ah;
1728 struct ath_common *common = ath5k_hw_common(ah);
1729 struct ieee80211_hdr *hdr = (void *)skb->data;
1730 unsigned int keyix, hlen;
1732 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1733 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1734 return RX_FLAG_DECRYPTED;
1736 /* Apparently when a default key is used to decrypt the packet
1737 the hw does not set the index used to decrypt. In such cases
1738 get the index from the packet. */
1739 hlen = ieee80211_hdrlen(hdr->frame_control);
1740 if (ieee80211_has_protected(hdr->frame_control) &&
1741 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1742 skb->len >= hlen + 4) {
1743 keyix = skb->data[hlen + 3] >> 6;
1745 if (test_bit(keyix, common->keymap))
1746 return RX_FLAG_DECRYPTED;
1754 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1755 struct ieee80211_rx_status *rxs)
1757 struct ath_common *common = ath5k_hw_common(sc->ah);
1760 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1762 if (ieee80211_is_beacon(mgmt->frame_control) &&
1763 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1764 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1766 * Received an IBSS beacon with the same BSSID. Hardware *must*
1767 * have updated the local TSF. We have to work around various
1768 * hardware bugs, though...
1770 tsf = ath5k_hw_get_tsf64(sc->ah);
1771 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1772 hw_tu = TSF_TO_TU(tsf);
1774 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1775 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1776 (unsigned long long)bc_tstamp,
1777 (unsigned long long)rxs->mactime,
1778 (unsigned long long)(rxs->mactime - bc_tstamp),
1779 (unsigned long long)tsf);
1782 * Sometimes the HW will give us a wrong tstamp in the rx
1783 * status, causing the timestamp extension to go wrong.
1784 * (This seems to happen especially with beacon frames bigger
1785 * than 78 byte (incl. FCS))
1786 * But we know that the receive timestamp must be later than the
1787 * timestamp of the beacon since HW must have synced to that.
1789 * NOTE: here we assume mactime to be after the frame was
1790 * received, not like mac80211 which defines it at the start.
1792 if (bc_tstamp > rxs->mactime) {
1793 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1794 "fixing mactime from %llx to %llx\n",
1795 (unsigned long long)rxs->mactime,
1796 (unsigned long long)tsf);
1801 * Local TSF might have moved higher than our beacon timers,
1802 * in that case we have to update them to continue sending
1803 * beacons. This also takes care of synchronizing beacon sending
1804 * times with other stations.
1806 if (hw_tu >= sc->nexttbtt)
1807 ath5k_beacon_update_timers(sc, bc_tstamp);
1812 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1814 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1815 struct ath5k_hw *ah = sc->ah;
1816 struct ath_common *common = ath5k_hw_common(ah);
1818 /* only beacons from our BSSID */
1819 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1820 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1823 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1826 /* in IBSS mode we should keep RSSI statistics per neighbour */
1827 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1831 * Compute padding position. skb must contains an IEEE 802.11 frame
1833 static int ath5k_common_padpos(struct sk_buff *skb)
1835 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1836 __le16 frame_control = hdr->frame_control;
1839 if (ieee80211_has_a4(frame_control)) {
1842 if (ieee80211_is_data_qos(frame_control)) {
1843 padpos += IEEE80211_QOS_CTL_LEN;
1850 * This function expects a 802.11 frame and returns the number of
1851 * bytes added, or -1 if we don't have enought header room.
1854 static int ath5k_add_padding(struct sk_buff *skb)
1856 int padpos = ath5k_common_padpos(skb);
1857 int padsize = padpos & 3;
1859 if (padsize && skb->len>padpos) {
1861 if (skb_headroom(skb) < padsize)
1864 skb_push(skb, padsize);
1865 memmove(skb->data, skb->data+padsize, padpos);
1873 * This function expects a 802.11 frame and returns the number of
1877 static int ath5k_remove_padding(struct sk_buff *skb)
1879 int padpos = ath5k_common_padpos(skb);
1880 int padsize = padpos & 3;
1882 if (padsize && skb->len>=padpos+padsize) {
1883 memmove(skb->data + padsize, skb->data, padpos);
1884 skb_pull(skb, padsize);
1892 ath5k_tasklet_rx(unsigned long data)
1894 struct ieee80211_rx_status *rxs;
1895 struct ath5k_rx_status rs = {};
1896 struct sk_buff *skb, *next_skb;
1897 dma_addr_t next_skb_addr;
1898 struct ath5k_softc *sc = (void *)data;
1899 struct ath5k_hw *ah = sc->ah;
1900 struct ath_common *common = ath5k_hw_common(ah);
1901 struct ath5k_buf *bf;
1902 struct ath5k_desc *ds;
1906 spin_lock(&sc->rxbuflock);
1907 if (list_empty(&sc->rxbuf)) {
1908 ATH5K_WARN(sc, "empty rx buf pool\n");
1914 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1915 BUG_ON(bf->skb == NULL);
1919 /* bail if HW is still using self-linked descriptor */
1920 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1923 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1924 if (unlikely(ret == -EINPROGRESS))
1926 else if (unlikely(ret)) {
1927 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1928 sc->stats.rxerr_proc++;
1929 spin_unlock(&sc->rxbuflock);
1933 sc->stats.rx_all_count++;
1935 if (unlikely(rs.rs_more)) {
1936 ATH5K_WARN(sc, "unsupported jumbo\n");
1937 sc->stats.rxerr_jumbo++;
1941 if (unlikely(rs.rs_status)) {
1942 if (rs.rs_status & AR5K_RXERR_CRC)
1943 sc->stats.rxerr_crc++;
1944 if (rs.rs_status & AR5K_RXERR_FIFO)
1945 sc->stats.rxerr_fifo++;
1946 if (rs.rs_status & AR5K_RXERR_PHY) {
1947 sc->stats.rxerr_phy++;
1948 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1949 sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
1952 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1954 * Decrypt error. If the error occurred
1955 * because there was no hardware key, then
1956 * let the frame through so the upper layers
1957 * can process it. This is necessary for 5210
1958 * parts which have no way to setup a ``clear''
1961 * XXX do key cache faulting
1963 sc->stats.rxerr_decrypt++;
1964 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1965 !(rs.rs_status & AR5K_RXERR_CRC))
1968 if (rs.rs_status & AR5K_RXERR_MIC) {
1969 rx_flag |= RX_FLAG_MMIC_ERROR;
1970 sc->stats.rxerr_mic++;
1974 /* let crypto-error packets fall through in MNTR */
1976 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1977 sc->opmode != NL80211_IFTYPE_MONITOR)
1981 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1984 * If we can't replace bf->skb with a new skb under memory
1985 * pressure, just skip this packet
1990 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1991 PCI_DMA_FROMDEVICE);
1992 skb_put(skb, rs.rs_datalen);
1994 /* The MAC header is padded to have 32-bit boundary if the
1995 * packet payload is non-zero. The general calculation for
1996 * padsize would take into account odd header lengths:
1997 * padsize = (4 - hdrlen % 4) % 4; However, since only
1998 * even-length headers are used, padding can only be 0 or 2
1999 * bytes and we can optimize this a bit. In addition, we must
2000 * not try to remove padding from short control frames that do
2001 * not have payload. */
2002 ath5k_remove_padding(skb);
2004 rxs = IEEE80211_SKB_RXCB(skb);
2007 * always extend the mac timestamp, since this information is
2008 * also needed for proper IBSS merging.
2010 * XXX: it might be too late to do it here, since rs_tstamp is
2011 * 15bit only. that means TSF extension has to be done within
2012 * 32768usec (about 32ms). it might be necessary to move this to
2013 * the interrupt handler, like it is done in madwifi.
2015 * Unfortunately we don't know when the hardware takes the rx
2016 * timestamp (beginning of phy frame, data frame, end of rx?).
2017 * The only thing we know is that it is hardware specific...
2018 * On AR5213 it seems the rx timestamp is at the end of the
2019 * frame, but i'm not sure.
2021 * NOTE: mac80211 defines mactime at the beginning of the first
2022 * data symbol. Since we don't have any time references it's
2023 * impossible to comply to that. This affects IBSS merge only
2024 * right now, so it's not too bad...
2026 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2027 rxs->flag = rx_flag | RX_FLAG_TSFT;
2029 rxs->freq = sc->curchan->center_freq;
2030 rxs->band = sc->curband->band;
2032 rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
2034 rxs->antenna = rs.rs_antenna;
2036 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2037 sc->stats.antenna_rx[rs.rs_antenna]++;
2039 sc->stats.antenna_rx[0]++; /* invalid */
2041 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2042 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
2044 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2045 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2046 rxs->flag |= RX_FLAG_SHORTPRE;
2048 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2050 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2052 /* check beacons in IBSS mode */
2053 if (sc->opmode == NL80211_IFTYPE_ADHOC)
2054 ath5k_check_ibss_tsf(sc, skb, rxs);
2056 ieee80211_rx(sc->hw, skb);
2059 bf->skbaddr = next_skb_addr;
2061 list_move_tail(&bf->list, &sc->rxbuf);
2062 } while (ath5k_rxbuf_setup(sc, bf) == 0);
2064 spin_unlock(&sc->rxbuflock);
2075 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2077 struct ath5k_tx_status ts = {};
2078 struct ath5k_buf *bf, *bf0;
2079 struct ath5k_desc *ds;
2080 struct sk_buff *skb;
2081 struct ieee80211_tx_info *info;
2084 spin_lock(&txq->lock);
2085 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2089 * It's possible that the hardware can say the buffer is
2090 * completed when it hasn't yet loaded the ds_link from
2091 * host memory and moved on. If there are more TX
2092 * descriptors in the queue, wait for TXDP to change
2093 * before processing this one.
2095 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2096 !list_is_last(&bf->list, &txq->q))
2099 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2100 if (unlikely(ret == -EINPROGRESS))
2102 else if (unlikely(ret)) {
2103 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2108 sc->stats.tx_all_count++;
2110 info = IEEE80211_SKB_CB(skb);
2113 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2116 ieee80211_tx_info_clear_status(info);
2117 for (i = 0; i < 4; i++) {
2118 struct ieee80211_tx_rate *r =
2119 &info->status.rates[i];
2121 if (ts.ts_rate[i]) {
2122 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2123 r->count = ts.ts_retry[i];
2130 /* count the successful attempt as well */
2131 info->status.rates[ts.ts_final_idx].count++;
2133 if (unlikely(ts.ts_status)) {
2134 sc->stats.ack_fail++;
2135 if (ts.ts_status & AR5K_TXERR_FILT) {
2136 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2137 sc->stats.txerr_filt++;
2139 if (ts.ts_status & AR5K_TXERR_XRETRY)
2140 sc->stats.txerr_retry++;
2141 if (ts.ts_status & AR5K_TXERR_FIFO)
2142 sc->stats.txerr_fifo++;
2144 info->flags |= IEEE80211_TX_STAT_ACK;
2145 info->status.ack_signal = ts.ts_rssi;
2149 * Remove MAC header padding before giving the frame
2152 ath5k_remove_padding(skb);
2154 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2155 sc->stats.antenna_tx[ts.ts_antenna]++;
2157 sc->stats.antenna_tx[0]++; /* invalid */
2159 ieee80211_tx_status(sc->hw, skb);
2161 spin_lock(&sc->txbuflock);
2162 list_move_tail(&bf->list, &sc->txbuf);
2164 spin_unlock(&sc->txbuflock);
2166 if (likely(list_empty(&txq->q)))
2168 spin_unlock(&txq->lock);
2169 if (sc->txbuf_len > ATH_TXBUF / 5)
2170 ieee80211_wake_queues(sc->hw);
2174 ath5k_tasklet_tx(unsigned long data)
2177 struct ath5k_softc *sc = (void *)data;
2179 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2180 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2181 ath5k_tx_processq(sc, &sc->txqs[i]);
2190 * Setup the beacon frame for transmit.
2193 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2195 struct sk_buff *skb = bf->skb;
2196 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2197 struct ath5k_hw *ah = sc->ah;
2198 struct ath5k_desc *ds;
2202 const int padsize = 0;
2204 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2206 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2207 "skbaddr %llx\n", skb, skb->data, skb->len,
2208 (unsigned long long)bf->skbaddr);
2209 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2210 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2215 antenna = ah->ah_tx_ant;
2217 flags = AR5K_TXDESC_NOACK;
2218 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2219 ds->ds_link = bf->daddr; /* self-linked */
2220 flags |= AR5K_TXDESC_VEOL;
2225 * If we use multiple antennas on AP and use
2226 * the Sectored AP scenario, switch antenna every
2227 * 4 beacons to make sure everybody hears our AP.
2228 * When a client tries to associate, hw will keep
2229 * track of the tx antenna to be used for this client
2230 * automaticaly, based on ACKed packets.
2232 * Note: AP still listens and transmits RTS on the
2233 * default antenna which is supposed to be an omni.
2235 * Note2: On sectored scenarios it's possible to have
2236 * multiple antennas (1omni -the default- and 14 sectors)
2237 * so if we choose to actually support this mode we need
2238 * to allow user to set how many antennas we have and tweak
2239 * the code below to send beacons on all of them.
2241 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2242 antenna = sc->bsent & 4 ? 2 : 1;
2245 /* FIXME: If we are in g mode and rate is a CCK rate
2246 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2247 * from tx power (value is in dB units already) */
2248 ds->ds_data = bf->skbaddr;
2249 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2250 ieee80211_get_hdrlen_from_skb(skb), padsize,
2251 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2252 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2253 1, AR5K_TXKEYIX_INVALID,
2254 antenna, flags, 0, 0);
2260 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2265 * Transmit a beacon frame at SWBA. Dynamic updates to the
2266 * frame contents are done as needed and the slot time is
2267 * also adjusted based on current state.
2269 * This is called from software irq context (beacontq or restq
2270 * tasklets) or user context from ath5k_beacon_config.
2273 ath5k_beacon_send(struct ath5k_softc *sc)
2275 struct ath5k_buf *bf = sc->bbuf;
2276 struct ath5k_hw *ah = sc->ah;
2277 struct sk_buff *skb;
2279 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2281 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2282 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2283 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2287 * Check if the previous beacon has gone out. If
2288 * not don't don't try to post another, skip this
2289 * period and wait for the next. Missed beacons
2290 * indicate a problem and should not occur. If we
2291 * miss too many consecutive beacons reset the device.
2293 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2295 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2296 "missed %u consecutive beacons\n", sc->bmisscount);
2297 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2298 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2299 "stuck beacon time (%u missed)\n",
2301 tasklet_schedule(&sc->restq);
2305 if (unlikely(sc->bmisscount != 0)) {
2306 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2307 "resume beacon xmit after %u misses\n",
2313 * Stop any current dma and put the new frame on the queue.
2314 * This should never fail since we check above that no frames
2315 * are still pending on the queue.
2317 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2318 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2319 /* NB: hw still stops DMA, so proceed */
2322 /* refresh the beacon for AP mode */
2323 if (sc->opmode == NL80211_IFTYPE_AP)
2324 ath5k_beacon_update(sc->hw, sc->vif);
2326 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2327 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2328 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2329 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2331 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2333 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2334 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2342 * ath5k_beacon_update_timers - update beacon timers
2344 * @sc: struct ath5k_softc pointer we are operating on
2345 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2346 * beacon timer update based on the current HW TSF.
2348 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2349 * of a received beacon or the current local hardware TSF and write it to the
2350 * beacon timer registers.
2352 * This is called in a variety of situations, e.g. when a beacon is received,
2353 * when a TSF update has been detected, but also when an new IBSS is created or
2354 * when we otherwise know we have to update the timers, but we keep it in this
2355 * function to have it all together in one place.
2358 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2360 struct ath5k_hw *ah = sc->ah;
2361 u32 nexttbtt, intval, hw_tu, bc_tu;
2364 intval = sc->bintval & AR5K_BEACON_PERIOD;
2365 if (WARN_ON(!intval))
2368 /* beacon TSF converted to TU */
2369 bc_tu = TSF_TO_TU(bc_tsf);
2371 /* current TSF converted to TU */
2372 hw_tsf = ath5k_hw_get_tsf64(ah);
2373 hw_tu = TSF_TO_TU(hw_tsf);
2376 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2379 * no beacons received, called internally.
2380 * just need to refresh timers based on HW TSF.
2382 nexttbtt = roundup(hw_tu + FUDGE, intval);
2383 } else if (bc_tsf == 0) {
2385 * no beacon received, probably called by ath5k_reset_tsf().
2386 * reset TSF to start with 0.
2389 intval |= AR5K_BEACON_RESET_TSF;
2390 } else if (bc_tsf > hw_tsf) {
2392 * beacon received, SW merge happend but HW TSF not yet updated.
2393 * not possible to reconfigure timers yet, but next time we
2394 * receive a beacon with the same BSSID, the hardware will
2395 * automatically update the TSF and then we need to reconfigure
2398 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2399 "need to wait for HW TSF sync\n");
2403 * most important case for beacon synchronization between STA.
2405 * beacon received and HW TSF has been already updated by HW.
2406 * update next TBTT based on the TSF of the beacon, but make
2407 * sure it is ahead of our local TSF timer.
2409 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2413 sc->nexttbtt = nexttbtt;
2415 intval |= AR5K_BEACON_ENA;
2416 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2419 * debugging output last in order to preserve the time critical aspect
2423 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2424 "reconfigured timers based on HW TSF\n");
2425 else if (bc_tsf == 0)
2426 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2427 "reset HW TSF and timers\n");
2429 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2430 "updated timers based on beacon TSF\n");
2432 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2433 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2434 (unsigned long long) bc_tsf,
2435 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2436 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2437 intval & AR5K_BEACON_PERIOD,
2438 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2439 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2444 * ath5k_beacon_config - Configure the beacon queues and interrupts
2446 * @sc: struct ath5k_softc pointer we are operating on
2448 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2449 * interrupts to detect TSF updates only.
2452 ath5k_beacon_config(struct ath5k_softc *sc)
2454 struct ath5k_hw *ah = sc->ah;
2455 unsigned long flags;
2457 spin_lock_irqsave(&sc->block, flags);
2459 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2461 if (sc->enable_beacon) {
2463 * In IBSS mode we use a self-linked tx descriptor and let the
2464 * hardware send the beacons automatically. We have to load it
2466 * We use the SWBA interrupt only to keep track of the beacon
2467 * timers in order to detect automatic TSF updates.
2469 ath5k_beaconq_config(sc);
2471 sc->imask |= AR5K_INT_SWBA;
2473 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2474 if (ath5k_hw_hasveol(ah))
2475 ath5k_beacon_send(sc);
2477 ath5k_beacon_update_timers(sc, -1);
2479 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2482 ath5k_hw_set_imr(ah, sc->imask);
2484 spin_unlock_irqrestore(&sc->block, flags);
2487 static void ath5k_tasklet_beacon(unsigned long data)
2489 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2492 * Software beacon alert--time to send a beacon.
2494 * In IBSS mode we use this interrupt just to
2495 * keep track of the next TBTT (target beacon
2496 * transmission time) in order to detect wether
2497 * automatic TSF updates happened.
2499 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2500 /* XXX: only if VEOL suppported */
2501 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2502 sc->nexttbtt += sc->bintval;
2503 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2504 "SWBA nexttbtt: %x hw_tu: %x "
2508 (unsigned long long) tsf);
2510 spin_lock(&sc->block);
2511 ath5k_beacon_send(sc);
2512 spin_unlock(&sc->block);
2517 /********************\
2518 * Interrupt handling *
2519 \********************/
2522 ath5k_init(struct ath5k_softc *sc)
2524 struct ath5k_hw *ah = sc->ah;
2527 mutex_lock(&sc->lock);
2529 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2532 * Stop anything previously setup. This is safe
2533 * no matter this is the first time through or not.
2535 ath5k_stop_locked(sc);
2538 * The basic interface to setting the hardware in a good
2539 * state is ``reset''. On return the hardware is known to
2540 * be powered up and with interrupts disabled. This must
2541 * be followed by initialization of the appropriate bits
2542 * and then setup of the interrupt mask.
2544 sc->curchan = sc->hw->conf.channel;
2545 sc->curband = &sc->sbands[sc->curchan->band];
2546 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2547 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2548 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2550 ret = ath5k_reset(sc, NULL);
2554 ath5k_rfkill_hw_start(ah);
2557 * Reset the key cache since some parts do not reset the
2558 * contents on initial power up or resume from suspend.
2560 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2561 ath5k_hw_reset_key(ah, i);
2563 ath5k_hw_set_ack_bitrate_high(ah, true);
2567 mutex_unlock(&sc->lock);
2572 ath5k_stop_locked(struct ath5k_softc *sc)
2574 struct ath5k_hw *ah = sc->ah;
2576 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2577 test_bit(ATH_STAT_INVALID, sc->status));
2580 * Shutdown the hardware and driver:
2581 * stop output from above
2582 * disable interrupts
2584 * turn off the radio
2585 * clear transmit machinery
2586 * clear receive machinery
2587 * drain and release tx queues
2588 * reclaim beacon resources
2589 * power down hardware
2591 * Note that some of this work is not possible if the
2592 * hardware is gone (invalid).
2594 ieee80211_stop_queues(sc->hw);
2596 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2598 ath5k_hw_set_imr(ah, 0);
2599 synchronize_irq(sc->pdev->irq);
2601 ath5k_txq_cleanup(sc);
2602 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2604 ath5k_hw_phy_disable(ah);
2612 * Stop the device, grabbing the top-level lock to protect
2613 * against concurrent entry through ath5k_init (which can happen
2614 * if another thread does a system call and the thread doing the
2615 * stop is preempted).
2618 ath5k_stop_hw(struct ath5k_softc *sc)
2622 mutex_lock(&sc->lock);
2623 ret = ath5k_stop_locked(sc);
2624 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2626 * Don't set the card in full sleep mode!
2628 * a) When the device is in this state it must be carefully
2629 * woken up or references to registers in the PCI clock
2630 * domain may freeze the bus (and system). This varies
2631 * by chip and is mostly an issue with newer parts
2632 * (madwifi sources mentioned srev >= 0x78) that go to
2633 * sleep more quickly.
2635 * b) On older chips full sleep results a weird behaviour
2636 * during wakeup. I tested various cards with srev < 0x78
2637 * and they don't wake up after module reload, a second
2638 * module reload is needed to bring the card up again.
2640 * Until we figure out what's going on don't enable
2641 * full chip reset on any chip (this is what Legacy HAL
2642 * and Sam's HAL do anyway). Instead Perform a full reset
2643 * on the device (same as initial state after attach) and
2644 * leave it idle (keep MAC/BB on warm reset) */
2645 ret = ath5k_hw_on_hold(sc->ah);
2647 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2648 "putting device to sleep\n");
2650 ath5k_txbuf_free(sc, sc->bbuf);
2653 mutex_unlock(&sc->lock);
2655 tasklet_kill(&sc->rxtq);
2656 tasklet_kill(&sc->txtq);
2657 tasklet_kill(&sc->restq);
2658 tasklet_kill(&sc->calib);
2659 tasklet_kill(&sc->beacontq);
2660 tasklet_kill(&sc->ani_tasklet);
2662 ath5k_rfkill_hw_stop(sc->ah);
2668 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2670 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2671 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2672 /* run ANI only when full calibration is not active */
2673 ah->ah_cal_next_ani = jiffies +
2674 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2675 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2677 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2678 ah->ah_cal_next_full = jiffies +
2679 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2680 tasklet_schedule(&ah->ah_sc->calib);
2682 /* we could use SWI to generate enough interrupts to meet our
2683 * calibration interval requirements, if necessary:
2684 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2688 ath5k_intr(int irq, void *dev_id)
2690 struct ath5k_softc *sc = dev_id;
2691 struct ath5k_hw *ah = sc->ah;
2692 enum ath5k_int status;
2693 unsigned int counter = 1000;
2695 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2696 !ath5k_hw_is_intr_pending(ah)))
2700 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2701 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2703 if (unlikely(status & AR5K_INT_FATAL)) {
2705 * Fatal errors are unrecoverable.
2706 * Typically these are caused by DMA errors.
2708 tasklet_schedule(&sc->restq);
2709 } else if (unlikely(status & AR5K_INT_RXORN)) {
2711 * Receive buffers are full. Either the bus is busy or
2712 * the CPU is not fast enough to process all received
2714 * Older chipsets need a reset to come out of this
2715 * condition, but we treat it as RX for newer chips.
2716 * We don't know exactly which versions need a reset -
2717 * this guess is copied from the HAL.
2719 sc->stats.rxorn_intr++;
2720 if (ah->ah_mac_srev < AR5K_SREV_AR5212)
2721 tasklet_schedule(&sc->restq);
2723 tasklet_schedule(&sc->rxtq);
2725 if (status & AR5K_INT_SWBA) {
2726 tasklet_hi_schedule(&sc->beacontq);
2728 if (status & AR5K_INT_RXEOL) {
2730 * NB: the hardware should re-read the link when
2731 * RXE bit is written, but it doesn't work at
2732 * least on older hardware revs.
2736 if (status & AR5K_INT_TXURN) {
2737 /* bump tx trigger level */
2738 ath5k_hw_update_tx_triglevel(ah, true);
2740 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2741 tasklet_schedule(&sc->rxtq);
2742 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2743 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2744 tasklet_schedule(&sc->txtq);
2745 if (status & AR5K_INT_BMISS) {
2748 if (status & AR5K_INT_MIB) {
2749 sc->stats.mib_intr++;
2750 ath5k_hw_update_mib_counters(ah);
2751 ath5k_ani_mib_intr(ah);
2753 if (status & AR5K_INT_GPIO)
2754 tasklet_schedule(&sc->rf_kill.toggleq);
2757 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2759 if (unlikely(!counter))
2760 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2762 ath5k_intr_calibration_poll(ah);
2768 ath5k_tasklet_reset(unsigned long data)
2770 struct ath5k_softc *sc = (void *)data;
2772 ath5k_reset_wake(sc);
2776 * Periodically recalibrate the PHY to account
2777 * for temperature/environment changes.
2780 ath5k_tasklet_calibrate(unsigned long data)
2782 struct ath5k_softc *sc = (void *)data;
2783 struct ath5k_hw *ah = sc->ah;
2785 /* Only full calibration for now */
2786 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2788 /* Stop queues so that calibration
2789 * doesn't interfere with tx */
2790 ieee80211_stop_queues(sc->hw);
2792 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2793 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2794 sc->curchan->hw_value);
2796 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2798 * Rfgain is out of bounds, reset the chip
2799 * to load new gain values.
2801 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2802 ath5k_reset(sc, sc->curchan);
2804 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2805 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2806 ieee80211_frequency_to_channel(
2807 sc->curchan->center_freq));
2810 ieee80211_wake_queues(sc->hw);
2812 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2817 ath5k_tasklet_ani(unsigned long data)
2819 struct ath5k_softc *sc = (void *)data;
2820 struct ath5k_hw *ah = sc->ah;
2822 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2823 ath5k_ani_calibration(ah);
2824 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2828 /********************\
2829 * Mac80211 functions *
2830 \********************/
2833 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2835 struct ath5k_softc *sc = hw->priv;
2837 return ath5k_tx_queue(hw, skb, sc->txq);
2840 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2841 struct ath5k_txq *txq)
2843 struct ath5k_softc *sc = hw->priv;
2844 struct ath5k_buf *bf;
2845 unsigned long flags;
2848 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2850 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2851 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2854 * the hardware expects the header padded to 4 byte boundaries
2855 * if this is not the case we add the padding after the header
2857 padsize = ath5k_add_padding(skb);
2859 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2860 " headroom to pad");
2864 spin_lock_irqsave(&sc->txbuflock, flags);
2865 if (list_empty(&sc->txbuf)) {
2866 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2867 spin_unlock_irqrestore(&sc->txbuflock, flags);
2868 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2871 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2872 list_del(&bf->list);
2874 if (list_empty(&sc->txbuf))
2875 ieee80211_stop_queues(hw);
2876 spin_unlock_irqrestore(&sc->txbuflock, flags);
2880 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2882 spin_lock_irqsave(&sc->txbuflock, flags);
2883 list_add_tail(&bf->list, &sc->txbuf);
2885 spin_unlock_irqrestore(&sc->txbuflock, flags);
2888 return NETDEV_TX_OK;
2891 dev_kfree_skb_any(skb);
2892 return NETDEV_TX_OK;
2896 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2897 * and change to the given channel.
2900 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2902 struct ath5k_hw *ah = sc->ah;
2905 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2908 ath5k_hw_set_imr(ah, 0);
2909 ath5k_txq_cleanup(sc);
2913 sc->curband = &sc->sbands[chan->band];
2915 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2917 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2921 ret = ath5k_rx_start(sc);
2923 ATH5K_ERR(sc, "can't start recv logic\n");
2927 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2930 * Change channels and update the h/w rate map if we're switching;
2931 * e.g. 11a to 11b/g.
2933 * We may be doing a reset in response to an ioctl that changes the
2934 * channel so update any state that might change as a result.
2938 /* ath5k_chan_change(sc, c); */
2940 ath5k_beacon_config(sc);
2941 /* intrs are enabled by ath5k_beacon_config */
2949 ath5k_reset_wake(struct ath5k_softc *sc)
2953 ret = ath5k_reset(sc, sc->curchan);
2955 ieee80211_wake_queues(sc->hw);
2960 static int ath5k_start(struct ieee80211_hw *hw)
2962 return ath5k_init(hw->priv);
2965 static void ath5k_stop(struct ieee80211_hw *hw)
2967 ath5k_stop_hw(hw->priv);
2970 static int ath5k_add_interface(struct ieee80211_hw *hw,
2971 struct ieee80211_vif *vif)
2973 struct ath5k_softc *sc = hw->priv;
2976 mutex_lock(&sc->lock);
2984 switch (vif->type) {
2985 case NL80211_IFTYPE_AP:
2986 case NL80211_IFTYPE_STATION:
2987 case NL80211_IFTYPE_ADHOC:
2988 case NL80211_IFTYPE_MESH_POINT:
2989 case NL80211_IFTYPE_MONITOR:
2990 sc->opmode = vif->type;
2997 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2999 ath5k_hw_set_lladdr(sc->ah, vif->addr);
3000 ath5k_mode_setup(sc);
3004 mutex_unlock(&sc->lock);
3009 ath5k_remove_interface(struct ieee80211_hw *hw,
3010 struct ieee80211_vif *vif)
3012 struct ath5k_softc *sc = hw->priv;
3013 u8 mac[ETH_ALEN] = {};
3015 mutex_lock(&sc->lock);
3019 ath5k_hw_set_lladdr(sc->ah, mac);
3022 mutex_unlock(&sc->lock);
3026 * TODO: Phy disable/diversity etc
3029 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3031 struct ath5k_softc *sc = hw->priv;
3032 struct ath5k_hw *ah = sc->ah;
3033 struct ieee80211_conf *conf = &hw->conf;
3036 mutex_lock(&sc->lock);
3038 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3039 ret = ath5k_chan_set(sc, conf->channel);
3044 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3045 (sc->power_level != conf->power_level)) {
3046 sc->power_level = conf->power_level;
3049 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3053 * 1) Move this on config_interface and handle each case
3054 * separately eg. when we have only one STA vif, use
3055 * AR5K_ANTMODE_SINGLE_AP
3057 * 2) Allow the user to change antenna mode eg. when only
3058 * one antenna is present
3060 * 3) Allow the user to set default/tx antenna when possible
3062 * 4) Default mode should handle 90% of the cases, together
3063 * with fixed a/b and single AP modes we should be able to
3064 * handle 99%. Sectored modes are extreme cases and i still
3065 * haven't found a usage for them. If we decide to support them,
3066 * then we must allow the user to set how many tx antennas we
3069 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3072 mutex_unlock(&sc->lock);
3076 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3077 struct netdev_hw_addr_list *mc_list)
3081 struct netdev_hw_addr *ha;
3086 netdev_hw_addr_list_for_each(ha, mc_list) {
3087 /* calculate XOR of eight 6-bit values */
3088 val = get_unaligned_le32(ha->addr + 0);
3089 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3090 val = get_unaligned_le32(ha->addr + 3);
3091 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3093 mfilt[pos / 32] |= (1 << (pos % 32));
3094 /* XXX: we might be able to just do this instead,
3095 * but not sure, needs testing, if we do use this we'd
3096 * neet to inform below to not reset the mcast */
3097 /* ath5k_hw_set_mcast_filterindex(ah,
3101 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3104 #define SUPPORTED_FIF_FLAGS \
3105 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3106 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3107 FIF_BCN_PRBRESP_PROMISC
3109 * o always accept unicast, broadcast, and multicast traffic
3110 * o multicast traffic for all BSSIDs will be enabled if mac80211
3112 * o maintain current state of phy ofdm or phy cck error reception.
3113 * If the hardware detects any of these type of errors then
3114 * ath5k_hw_get_rx_filter() will pass to us the respective
3115 * hardware filters to be able to receive these type of frames.
3116 * o probe request frames are accepted only when operating in
3117 * hostap, adhoc, or monitor modes
3118 * o enable promiscuous mode according to the interface state
3120 * - when operating in adhoc mode so the 802.11 layer creates
3121 * node table entries for peers,
3122 * - when operating in station mode for collecting rssi data when
3123 * the station is otherwise quiet, or
3126 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3127 unsigned int changed_flags,
3128 unsigned int *new_flags,
3131 struct ath5k_softc *sc = hw->priv;
3132 struct ath5k_hw *ah = sc->ah;
3133 u32 mfilt[2], rfilt;
3135 mutex_lock(&sc->lock);
3137 mfilt[0] = multicast;
3138 mfilt[1] = multicast >> 32;
3140 /* Only deal with supported flags */
3141 changed_flags &= SUPPORTED_FIF_FLAGS;
3142 *new_flags &= SUPPORTED_FIF_FLAGS;
3144 /* If HW detects any phy or radar errors, leave those filters on.
3145 * Also, always enable Unicast, Broadcasts and Multicast
3146 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3147 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3148 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3149 AR5K_RX_FILTER_MCAST);
3151 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3152 if (*new_flags & FIF_PROMISC_IN_BSS) {
3153 rfilt |= AR5K_RX_FILTER_PROM;
3154 __set_bit(ATH_STAT_PROMISC, sc->status);
3156 __clear_bit(ATH_STAT_PROMISC, sc->status);
3160 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3161 if (*new_flags & FIF_ALLMULTI) {
3166 /* This is the best we can do */
3167 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3168 rfilt |= AR5K_RX_FILTER_PHYERR;
3170 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3171 * and probes for any BSSID, this needs testing */
3172 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3173 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3175 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3176 * set we should only pass on control frames for this
3177 * station. This needs testing. I believe right now this
3178 * enables *all* control frames, which is OK.. but
3179 * but we should see if we can improve on granularity */
3180 if (*new_flags & FIF_CONTROL)
3181 rfilt |= AR5K_RX_FILTER_CONTROL;
3183 /* Additional settings per mode -- this is per ath5k */
3185 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3187 switch (sc->opmode) {
3188 case NL80211_IFTYPE_MESH_POINT:
3189 case NL80211_IFTYPE_MONITOR:
3190 rfilt |= AR5K_RX_FILTER_CONTROL |
3191 AR5K_RX_FILTER_BEACON |
3192 AR5K_RX_FILTER_PROBEREQ |
3193 AR5K_RX_FILTER_PROM;
3195 case NL80211_IFTYPE_AP:
3196 case NL80211_IFTYPE_ADHOC:
3197 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3198 AR5K_RX_FILTER_BEACON;
3200 case NL80211_IFTYPE_STATION:
3202 rfilt |= AR5K_RX_FILTER_BEACON;
3208 ath5k_hw_set_rx_filter(ah, rfilt);
3210 /* Set multicast bits */
3211 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3212 /* Set the cached hw filter flags, this will alter actually
3214 sc->filter_flags = rfilt;
3216 mutex_unlock(&sc->lock);
3220 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3221 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3222 struct ieee80211_key_conf *key)
3224 struct ath5k_softc *sc = hw->priv;
3225 struct ath5k_hw *ah = sc->ah;
3226 struct ath_common *common = ath5k_hw_common(ah);
3229 if (modparam_nohwcrypt)
3232 if (sc->opmode == NL80211_IFTYPE_AP)
3240 if (sc->ah->ah_aes_support)
3249 mutex_lock(&sc->lock);
3253 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3254 sta ? sta->addr : NULL);
3256 ATH5K_ERR(sc, "can't set the key\n");
3259 __set_bit(key->keyidx, common->keymap);
3260 key->hw_key_idx = key->keyidx;
3261 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3262 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3265 ath5k_hw_reset_key(sc->ah, key->keyidx);
3266 __clear_bit(key->keyidx, common->keymap);
3275 mutex_unlock(&sc->lock);
3280 ath5k_get_stats(struct ieee80211_hw *hw,
3281 struct ieee80211_low_level_stats *stats)
3283 struct ath5k_softc *sc = hw->priv;
3286 ath5k_hw_update_mib_counters(sc->ah);
3288 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3289 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3290 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3291 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3296 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3297 struct survey_info *survey)
3299 struct ath5k_softc *sc = hw->priv;
3300 struct ieee80211_conf *conf = &hw->conf;
3305 survey->channel = conf->channel;
3306 survey->filled = SURVEY_INFO_NOISE_DBM;
3307 survey->noise = sc->ah->ah_noise_floor;
3313 ath5k_get_tsf(struct ieee80211_hw *hw)
3315 struct ath5k_softc *sc = hw->priv;
3317 return ath5k_hw_get_tsf64(sc->ah);
3321 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3323 struct ath5k_softc *sc = hw->priv;
3325 ath5k_hw_set_tsf64(sc->ah, tsf);
3329 ath5k_reset_tsf(struct ieee80211_hw *hw)
3331 struct ath5k_softc *sc = hw->priv;
3334 * in IBSS mode we need to update the beacon timers too.
3335 * this will also reset the TSF if we call it with 0
3337 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3338 ath5k_beacon_update_timers(sc, 0);
3340 ath5k_hw_reset_tsf(sc->ah);
3344 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3345 * this is called only once at config_bss time, for AP we do it every
3346 * SWBA interrupt so that the TIM will reflect buffered frames.
3348 * Called with the beacon lock.
3351 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3354 struct ath5k_softc *sc = hw->priv;
3355 struct sk_buff *skb;
3357 if (WARN_ON(!vif)) {
3362 skb = ieee80211_beacon_get(hw, vif);
3369 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3371 ath5k_txbuf_free(sc, sc->bbuf);
3372 sc->bbuf->skb = skb;
3373 ret = ath5k_beacon_setup(sc, sc->bbuf);
3375 sc->bbuf->skb = NULL;
3381 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3383 struct ath5k_softc *sc = hw->priv;
3384 struct ath5k_hw *ah = sc->ah;
3386 rfilt = ath5k_hw_get_rx_filter(ah);
3388 rfilt |= AR5K_RX_FILTER_BEACON;
3390 rfilt &= ~AR5K_RX_FILTER_BEACON;
3391 ath5k_hw_set_rx_filter(ah, rfilt);
3392 sc->filter_flags = rfilt;
3395 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3396 struct ieee80211_vif *vif,
3397 struct ieee80211_bss_conf *bss_conf,
3400 struct ath5k_softc *sc = hw->priv;
3401 struct ath5k_hw *ah = sc->ah;
3402 struct ath_common *common = ath5k_hw_common(ah);
3403 unsigned long flags;
3405 mutex_lock(&sc->lock);
3406 if (WARN_ON(sc->vif != vif))
3409 if (changes & BSS_CHANGED_BSSID) {
3410 /* Cache for later use during resets */
3411 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3413 ath5k_hw_set_associd(ah);
3417 if (changes & BSS_CHANGED_BEACON_INT)
3418 sc->bintval = bss_conf->beacon_int;
3420 if (changes & BSS_CHANGED_ASSOC) {
3421 sc->assoc = bss_conf->assoc;
3422 if (sc->opmode == NL80211_IFTYPE_STATION)
3423 set_beacon_filter(hw, sc->assoc);
3424 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3425 AR5K_LED_ASSOC : AR5K_LED_INIT);
3426 if (bss_conf->assoc) {
3427 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3428 "Bss Info ASSOC %d, bssid: %pM\n",
3429 bss_conf->aid, common->curbssid);
3430 common->curaid = bss_conf->aid;
3431 ath5k_hw_set_associd(ah);
3432 /* Once ANI is available you would start it here */
3436 if (changes & BSS_CHANGED_BEACON) {
3437 spin_lock_irqsave(&sc->block, flags);
3438 ath5k_beacon_update(hw, vif);
3439 spin_unlock_irqrestore(&sc->block, flags);
3442 if (changes & BSS_CHANGED_BEACON_ENABLED)
3443 sc->enable_beacon = bss_conf->enable_beacon;
3445 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3446 BSS_CHANGED_BEACON_INT))
3447 ath5k_beacon_config(sc);
3450 mutex_unlock(&sc->lock);
3453 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3455 struct ath5k_softc *sc = hw->priv;
3457 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3460 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3462 struct ath5k_softc *sc = hw->priv;
3463 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3464 AR5K_LED_ASSOC : AR5K_LED_INIT);
3468 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3470 * @hw: struct ieee80211_hw pointer
3471 * @coverage_class: IEEE 802.11 coverage class number
3473 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3474 * coverage class. The values are persistent, they are restored after device
3477 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3479 struct ath5k_softc *sc = hw->priv;
3481 mutex_lock(&sc->lock);
3482 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3483 mutex_unlock(&sc->lock);
git.openpandora.org / pandora-kernel.git / blob