2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
56 #include <net/ieee80211_radiotap.h>
58 #include <asm/unaligned.h>
65 static int modparam_nohwcrypt;
66 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
67 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
69 static int modparam_all_channels;
70 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
71 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74 MODULE_AUTHOR("Jiri Slaby");
75 MODULE_AUTHOR("Nick Kossifidis");
76 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78 MODULE_LICENSE("Dual BSD/GPL");
79 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
81 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
82 static int ath5k_beacon_update(struct ieee80211_hw *hw,
83 struct ieee80211_vif *vif);
84 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
108 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
111 static const struct ath5k_srev_name srev_names[] = {
112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150 static const struct ieee80211_rate ath5k_rates[] = {
152 .hw_value = ATH5K_RATE_CODE_1M, },
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 .hw_value = ATH5K_RATE_CODE_6M,
169 .hw_value = ATH5K_RATE_CODE_9M,
172 .hw_value = ATH5K_RATE_CODE_12M,
175 .hw_value = ATH5K_RATE_CODE_18M,
178 .hw_value = ATH5K_RATE_CODE_24M,
181 .hw_value = ATH5K_RATE_CODE_36M,
184 .hw_value = ATH5K_RATE_CODE_48M,
187 .hw_value = ATH5K_RATE_CODE_54M,
192 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
193 struct ath5k_buf *bf)
198 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
200 dev_kfree_skb_any(bf->skb);
203 bf->desc->ds_data = 0;
206 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
207 struct ath5k_buf *bf)
209 struct ath5k_hw *ah = sc->ah;
210 struct ath_common *common = ath5k_hw_common(ah);
215 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
217 dev_kfree_skb_any(bf->skb);
220 bf->desc->ds_data = 0;
224 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
226 u64 tsf = ath5k_hw_get_tsf64(ah);
228 if ((tsf & 0x7fff) < rstamp)
231 return (tsf & ~0x7fff) | rstamp;
235 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
237 const char *name = "xxxxx";
240 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
241 if (srev_names[i].sr_type != type)
244 if ((val & 0xf0) == srev_names[i].sr_val)
245 name = srev_names[i].sr_name;
247 if ((val & 0xff) == srev_names[i].sr_val) {
248 name = srev_names[i].sr_name;
255 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
257 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
258 return ath5k_hw_reg_read(ah, reg_offset);
261 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
263 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
264 ath5k_hw_reg_write(ah, val, reg_offset);
267 static const struct ath_ops ath5k_common_ops = {
268 .read = ath5k_ioread32,
269 .write = ath5k_iowrite32,
272 /***********************\
273 * Driver Initialization *
274 \***********************/
276 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
278 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
279 struct ath5k_softc *sc = hw->priv;
280 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
282 return ath_reg_notifier_apply(wiphy, request, regulatory);
285 /********************\
286 * Channel/mode setup *
287 \********************/
290 * Convert IEEE channel number to MHz frequency.
293 ath5k_ieee2mhz(short chan)
295 if (chan <= 14 || chan >= 27)
296 return ieee80211chan2mhz(chan);
298 return 2212 + chan * 20;
302 * Returns true for the channel numbers used without all_channels modparam.
304 static bool ath5k_is_standard_channel(short chan)
306 return ((chan <= 14) ||
308 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
310 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
312 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
316 ath5k_copy_channels(struct ath5k_hw *ah,
317 struct ieee80211_channel *channels,
321 unsigned int i, count, size, chfreq, freq, ch;
323 if (!test_bit(mode, ah->ah_modes))
328 case AR5K_MODE_11A_TURBO:
329 /* 1..220, but 2GHz frequencies are filtered by check_channel */
331 chfreq = CHANNEL_5GHZ;
335 case AR5K_MODE_11G_TURBO:
337 chfreq = CHANNEL_2GHZ;
340 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
344 for (i = 0, count = 0; i < size && max > 0; i++) {
346 freq = ath5k_ieee2mhz(ch);
348 /* Check if channel is supported by the chipset */
349 if (!ath5k_channel_ok(ah, freq, chfreq))
352 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
355 /* Write channel info and increment counter */
356 channels[count].center_freq = freq;
357 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
358 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
362 channels[count].hw_value = chfreq | CHANNEL_OFDM;
364 case AR5K_MODE_11A_TURBO:
365 case AR5K_MODE_11G_TURBO:
366 channels[count].hw_value = chfreq |
367 CHANNEL_OFDM | CHANNEL_TURBO;
370 channels[count].hw_value = CHANNEL_B;
381 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
385 for (i = 0; i < AR5K_MAX_RATES; i++)
386 sc->rate_idx[b->band][i] = -1;
388 for (i = 0; i < b->n_bitrates; i++) {
389 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
390 if (b->bitrates[i].hw_value_short)
391 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
396 ath5k_setup_bands(struct ieee80211_hw *hw)
398 struct ath5k_softc *sc = hw->priv;
399 struct ath5k_hw *ah = sc->ah;
400 struct ieee80211_supported_band *sband;
401 int max_c, count_c = 0;
404 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
405 max_c = ARRAY_SIZE(sc->channels);
408 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
409 sband->band = IEEE80211_BAND_2GHZ;
410 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
412 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
414 memcpy(sband->bitrates, &ath5k_rates[0],
415 sizeof(struct ieee80211_rate) * 12);
416 sband->n_bitrates = 12;
418 sband->channels = sc->channels;
419 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
420 AR5K_MODE_11G, max_c);
422 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
423 count_c = sband->n_channels;
425 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
427 memcpy(sband->bitrates, &ath5k_rates[0],
428 sizeof(struct ieee80211_rate) * 4);
429 sband->n_bitrates = 4;
431 /* 5211 only supports B rates and uses 4bit rate codes
432 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
435 if (ah->ah_version == AR5K_AR5211) {
436 for (i = 0; i < 4; i++) {
437 sband->bitrates[i].hw_value =
438 sband->bitrates[i].hw_value & 0xF;
439 sband->bitrates[i].hw_value_short =
440 sband->bitrates[i].hw_value_short & 0xF;
444 sband->channels = sc->channels;
445 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
446 AR5K_MODE_11B, max_c);
448 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
449 count_c = sband->n_channels;
452 ath5k_setup_rate_idx(sc, sband);
454 /* 5GHz band, A mode */
455 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
456 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
457 sband->band = IEEE80211_BAND_5GHZ;
458 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
460 memcpy(sband->bitrates, &ath5k_rates[4],
461 sizeof(struct ieee80211_rate) * 8);
462 sband->n_bitrates = 8;
464 sband->channels = &sc->channels[count_c];
465 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
466 AR5K_MODE_11A, max_c);
468 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
470 ath5k_setup_rate_idx(sc, sband);
472 ath5k_debug_dump_bands(sc);
478 * Set/change channels. We always reset the chip.
479 * To accomplish this we must first cleanup any pending DMA,
480 * then restart stuff after a la ath5k_init.
482 * Called with sc->lock.
485 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
488 "channel set, resetting (%u -> %u MHz)\n",
489 sc->curchan->center_freq, chan->center_freq);
492 * To switch channels clear any pending DMA operations;
493 * wait long enough for the RX fifo to drain, reset the
494 * hardware at the new frequency, and then re-enable
495 * the relevant bits of the h/w.
497 return ath5k_reset(sc, chan);
501 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
505 if (mode == AR5K_MODE_11A) {
506 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
508 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
513 ath5k_mode_setup(struct ath5k_softc *sc)
515 struct ath5k_hw *ah = sc->ah;
518 /* configure rx filter */
519 rfilt = sc->filter_flags;
520 ath5k_hw_set_rx_filter(ah, rfilt);
522 if (ath5k_hw_hasbssidmask(ah))
523 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
525 /* configure operational mode */
526 ath5k_hw_set_opmode(ah, sc->opmode);
528 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
529 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
533 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
537 /* return base rate on errors */
538 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
539 "hw_rix out of bounds: %x\n", hw_rix))
542 rix = sc->rate_idx[sc->curband->band][hw_rix];
543 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
554 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
556 struct ath_common *common = ath5k_hw_common(sc->ah);
560 * Allocate buffer with headroom_needed space for the
561 * fake physical layer header at the start.
563 skb = ath_rxbuf_alloc(common,
568 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
573 *skb_addr = pci_map_single(sc->pdev,
574 skb->data, common->rx_bufsize,
576 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
577 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
585 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
587 struct ath5k_hw *ah = sc->ah;
588 struct sk_buff *skb = bf->skb;
589 struct ath5k_desc *ds;
593 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
600 * Setup descriptors. For receive we always terminate
601 * the descriptor list with a self-linked entry so we'll
602 * not get overrun under high load (as can happen with a
603 * 5212 when ANI processing enables PHY error frames).
605 * To ensure the last descriptor is self-linked we create
606 * each descriptor as self-linked and add it to the end. As
607 * each additional descriptor is added the previous self-linked
608 * entry is "fixed" naturally. This should be safe even
609 * if DMA is happening. When processing RX interrupts we
610 * never remove/process the last, self-linked, entry on the
611 * descriptor list. This ensures the hardware always has
612 * someplace to write a new frame.
615 ds->ds_link = bf->daddr; /* link to self */
616 ds->ds_data = bf->skbaddr;
617 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
619 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
623 if (sc->rxlink != NULL)
624 *sc->rxlink = bf->daddr;
625 sc->rxlink = &ds->ds_link;
629 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
631 struct ieee80211_hdr *hdr;
632 enum ath5k_pkt_type htype;
635 hdr = (struct ieee80211_hdr *)skb->data;
636 fc = hdr->frame_control;
638 if (ieee80211_is_beacon(fc))
639 htype = AR5K_PKT_TYPE_BEACON;
640 else if (ieee80211_is_probe_resp(fc))
641 htype = AR5K_PKT_TYPE_PROBE_RESP;
642 else if (ieee80211_is_atim(fc))
643 htype = AR5K_PKT_TYPE_ATIM;
644 else if (ieee80211_is_pspoll(fc))
645 htype = AR5K_PKT_TYPE_PSPOLL;
647 htype = AR5K_PKT_TYPE_NORMAL;
653 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
654 struct ath5k_txq *txq, int padsize)
656 struct ath5k_hw *ah = sc->ah;
657 struct ath5k_desc *ds = bf->desc;
658 struct sk_buff *skb = bf->skb;
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
660 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
661 struct ieee80211_rate *rate;
662 unsigned int mrr_rate[3], mrr_tries[3];
669 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
672 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
675 rate = ieee80211_get_tx_rate(sc->hw, info);
677 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
678 flags |= AR5K_TXDESC_NOACK;
680 rc_flags = info->control.rates[0].flags;
681 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
682 rate->hw_value_short : rate->hw_value;
686 /* FIXME: If we are in g mode and rate is a CCK rate
687 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
688 * from tx power (value is in dB units already) */
689 if (info->control.hw_key) {
690 keyidx = info->control.hw_key->hw_key_idx;
691 pktlen += info->control.hw_key->icv_len;
693 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
694 flags |= AR5K_TXDESC_RTSENA;
695 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
696 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
697 sc->vif, pktlen, info));
699 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
700 flags |= AR5K_TXDESC_CTSENA;
701 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
702 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
703 sc->vif, pktlen, info));
705 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
706 ieee80211_get_hdrlen_from_skb(skb), padsize,
707 get_hw_packet_type(skb),
708 (sc->power_level * 2),
710 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
715 memset(mrr_rate, 0, sizeof(mrr_rate));
716 memset(mrr_tries, 0, sizeof(mrr_tries));
717 for (i = 0; i < 3; i++) {
718 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
722 mrr_rate[i] = rate->hw_value;
723 mrr_tries[i] = info->control.rates[i + 1].count;
726 ath5k_hw_setup_mrr_tx_desc(ah, ds,
727 mrr_rate[0], mrr_tries[0],
728 mrr_rate[1], mrr_tries[1],
729 mrr_rate[2], mrr_tries[2]);
732 ds->ds_data = bf->skbaddr;
734 spin_lock_bh(&txq->lock);
735 list_add_tail(&bf->list, &txq->q);
737 if (txq->link == NULL) /* is this first packet? */
738 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
739 else /* no, so only link it */
740 *txq->link = bf->daddr;
742 txq->link = &ds->ds_link;
743 ath5k_hw_start_tx_dma(ah, txq->qnum);
745 spin_unlock_bh(&txq->lock);
749 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
753 /*******************\
754 * Descriptors setup *
755 \*******************/
758 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
760 struct ath5k_desc *ds;
761 struct ath5k_buf *bf;
766 /* allocate descriptors */
767 sc->desc_len = sizeof(struct ath5k_desc) *
768 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
769 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
770 if (sc->desc == NULL) {
771 ATH5K_ERR(sc, "can't allocate descriptors\n");
777 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
778 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
780 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
781 sizeof(struct ath5k_buf), GFP_KERNEL);
783 ATH5K_ERR(sc, "can't allocate bufptr\n");
789 INIT_LIST_HEAD(&sc->rxbuf);
790 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
793 list_add_tail(&bf->list, &sc->rxbuf);
796 INIT_LIST_HEAD(&sc->txbuf);
797 sc->txbuf_len = ATH_TXBUF;
798 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
802 list_add_tail(&bf->list, &sc->txbuf);
812 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
819 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
821 struct ath5k_buf *bf;
823 ath5k_txbuf_free_skb(sc, sc->bbuf);
824 list_for_each_entry(bf, &sc->txbuf, list)
825 ath5k_txbuf_free_skb(sc, bf);
826 list_for_each_entry(bf, &sc->rxbuf, list)
827 ath5k_rxbuf_free_skb(sc, bf);
829 /* Free memory associated with all descriptors */
830 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
844 static struct ath5k_txq *
845 ath5k_txq_setup(struct ath5k_softc *sc,
846 int qtype, int subtype)
848 struct ath5k_hw *ah = sc->ah;
849 struct ath5k_txq *txq;
850 struct ath5k_txq_info qi = {
851 .tqi_subtype = subtype,
852 /* XXX: default values not correct for B and XR channels,
854 .tqi_aifs = AR5K_TUNE_AIFS,
855 .tqi_cw_min = AR5K_TUNE_CWMIN,
856 .tqi_cw_max = AR5K_TUNE_CWMAX
861 * Enable interrupts only for EOL and DESC conditions.
862 * We mark tx descriptors to receive a DESC interrupt
863 * when a tx queue gets deep; otherwise we wait for the
864 * EOL to reap descriptors. Note that this is done to
865 * reduce interrupt load and this only defers reaping
866 * descriptors, never transmitting frames. Aside from
867 * reducing interrupts this also permits more concurrency.
868 * The only potential downside is if the tx queue backs
869 * up in which case the top half of the kernel may backup
870 * due to a lack of tx descriptors.
872 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
873 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
874 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
877 * NB: don't print a message, this happens
878 * normally on parts with too few tx queues
880 return ERR_PTR(qnum);
882 if (qnum >= ARRAY_SIZE(sc->txqs)) {
883 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
884 qnum, ARRAY_SIZE(sc->txqs));
885 ath5k_hw_release_tx_queue(ah, qnum);
886 return ERR_PTR(-EINVAL);
888 txq = &sc->txqs[qnum];
892 INIT_LIST_HEAD(&txq->q);
893 spin_lock_init(&txq->lock);
896 txq->txq_poll_mark = false;
899 return &sc->txqs[qnum];
903 ath5k_beaconq_setup(struct ath5k_hw *ah)
905 struct ath5k_txq_info qi = {
906 /* XXX: default values not correct for B and XR channels,
908 .tqi_aifs = AR5K_TUNE_AIFS,
909 .tqi_cw_min = AR5K_TUNE_CWMIN,
910 .tqi_cw_max = AR5K_TUNE_CWMAX,
911 /* NB: for dynamic turbo, don't enable any other interrupts */
912 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
915 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
919 ath5k_beaconq_config(struct ath5k_softc *sc)
921 struct ath5k_hw *ah = sc->ah;
922 struct ath5k_txq_info qi;
925 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
929 if (sc->opmode == NL80211_IFTYPE_AP ||
930 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
932 * Always burst out beacon and CAB traffic
933 * (aifs = cwmin = cwmax = 0)
938 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
940 * Adhoc mode; backoff between 0 and (2 * cw_min).
944 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
947 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
948 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
949 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
951 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
953 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
954 "hardware queue!\n", __func__);
957 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
961 /* reconfigure cabq with ready time to 80% of beacon_interval */
962 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
966 qi.tqi_ready_time = (sc->bintval * 80) / 100;
967 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
971 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
977 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
979 struct ath5k_buf *bf, *bf0;
982 * NB: this assumes output has been stopped and
983 * we do not need to block ath5k_tx_tasklet
985 spin_lock_bh(&txq->lock);
986 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
987 ath5k_debug_printtxbuf(sc, bf);
989 ath5k_txbuf_free_skb(sc, bf);
991 spin_lock_bh(&sc->txbuflock);
992 list_move_tail(&bf->list, &sc->txbuf);
995 spin_unlock_bh(&sc->txbuflock);
998 txq->txq_poll_mark = false;
999 spin_unlock_bh(&txq->lock);
1003 * Drain the transmit queues and reclaim resources.
1006 ath5k_txq_cleanup(struct ath5k_softc *sc)
1008 struct ath5k_hw *ah = sc->ah;
1011 /* XXX return value */
1012 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1013 /* don't touch the hardware if marked invalid */
1014 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1015 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1016 ath5k_hw_get_txdp(ah, sc->bhalq));
1017 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1018 if (sc->txqs[i].setup) {
1019 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1020 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1023 ath5k_hw_get_txdp(ah,
1029 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1030 if (sc->txqs[i].setup)
1031 ath5k_txq_drainq(sc, &sc->txqs[i]);
1035 ath5k_txq_release(struct ath5k_softc *sc)
1037 struct ath5k_txq *txq = sc->txqs;
1040 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1042 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1053 * Enable the receive h/w following a reset.
1056 ath5k_rx_start(struct ath5k_softc *sc)
1058 struct ath5k_hw *ah = sc->ah;
1059 struct ath_common *common = ath5k_hw_common(ah);
1060 struct ath5k_buf *bf;
1063 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1065 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1066 common->cachelsz, common->rx_bufsize);
1068 spin_lock_bh(&sc->rxbuflock);
1070 list_for_each_entry(bf, &sc->rxbuf, list) {
1071 ret = ath5k_rxbuf_setup(sc, bf);
1073 spin_unlock_bh(&sc->rxbuflock);
1077 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1078 ath5k_hw_set_rxdp(ah, bf->daddr);
1079 spin_unlock_bh(&sc->rxbuflock);
1081 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1082 ath5k_mode_setup(sc); /* set filters, etc. */
1083 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1091 * Disable the receive h/w in preparation for a reset.
1094 ath5k_rx_stop(struct ath5k_softc *sc)
1096 struct ath5k_hw *ah = sc->ah;
1098 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1099 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1100 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1102 ath5k_debug_printrxbuffs(sc, ah);
1106 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1107 struct ath5k_rx_status *rs)
1109 struct ath5k_hw *ah = sc->ah;
1110 struct ath_common *common = ath5k_hw_common(ah);
1111 struct ieee80211_hdr *hdr = (void *)skb->data;
1112 unsigned int keyix, hlen;
1114 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1115 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1116 return RX_FLAG_DECRYPTED;
1118 /* Apparently when a default key is used to decrypt the packet
1119 the hw does not set the index used to decrypt. In such cases
1120 get the index from the packet. */
1121 hlen = ieee80211_hdrlen(hdr->frame_control);
1122 if (ieee80211_has_protected(hdr->frame_control) &&
1123 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1124 skb->len >= hlen + 4) {
1125 keyix = skb->data[hlen + 3] >> 6;
1127 if (test_bit(keyix, common->keymap))
1128 return RX_FLAG_DECRYPTED;
1136 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1137 struct ieee80211_rx_status *rxs)
1139 struct ath_common *common = ath5k_hw_common(sc->ah);
1142 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1144 if (ieee80211_is_beacon(mgmt->frame_control) &&
1145 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1146 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1148 * Received an IBSS beacon with the same BSSID. Hardware *must*
1149 * have updated the local TSF. We have to work around various
1150 * hardware bugs, though...
1152 tsf = ath5k_hw_get_tsf64(sc->ah);
1153 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1154 hw_tu = TSF_TO_TU(tsf);
1156 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1157 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1158 (unsigned long long)bc_tstamp,
1159 (unsigned long long)rxs->mactime,
1160 (unsigned long long)(rxs->mactime - bc_tstamp),
1161 (unsigned long long)tsf);
1164 * Sometimes the HW will give us a wrong tstamp in the rx
1165 * status, causing the timestamp extension to go wrong.
1166 * (This seems to happen especially with beacon frames bigger
1167 * than 78 byte (incl. FCS))
1168 * But we know that the receive timestamp must be later than the
1169 * timestamp of the beacon since HW must have synced to that.
1171 * NOTE: here we assume mactime to be after the frame was
1172 * received, not like mac80211 which defines it at the start.
1174 if (bc_tstamp > rxs->mactime) {
1175 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1176 "fixing mactime from %llx to %llx\n",
1177 (unsigned long long)rxs->mactime,
1178 (unsigned long long)tsf);
1183 * Local TSF might have moved higher than our beacon timers,
1184 * in that case we have to update them to continue sending
1185 * beacons. This also takes care of synchronizing beacon sending
1186 * times with other stations.
1188 if (hw_tu >= sc->nexttbtt)
1189 ath5k_beacon_update_timers(sc, bc_tstamp);
1194 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1196 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1197 struct ath5k_hw *ah = sc->ah;
1198 struct ath_common *common = ath5k_hw_common(ah);
1200 /* only beacons from our BSSID */
1201 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1202 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1205 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1208 /* in IBSS mode we should keep RSSI statistics per neighbour */
1209 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1213 * Compute padding position. skb must contain an IEEE 802.11 frame
1215 static int ath5k_common_padpos(struct sk_buff *skb)
1217 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1218 __le16 frame_control = hdr->frame_control;
1221 if (ieee80211_has_a4(frame_control)) {
1224 if (ieee80211_is_data_qos(frame_control)) {
1225 padpos += IEEE80211_QOS_CTL_LEN;
1232 * This function expects an 802.11 frame and returns the number of
1233 * bytes added, or -1 if we don't have enough header room.
1235 static int ath5k_add_padding(struct sk_buff *skb)
1237 int padpos = ath5k_common_padpos(skb);
1238 int padsize = padpos & 3;
1240 if (padsize && skb->len>padpos) {
1242 if (skb_headroom(skb) < padsize)
1245 skb_push(skb, padsize);
1246 memmove(skb->data, skb->data+padsize, padpos);
1254 * The MAC header is padded to have 32-bit boundary if the
1255 * packet payload is non-zero. The general calculation for
1256 * padsize would take into account odd header lengths:
1257 * padsize = 4 - (hdrlen & 3); however, since only
1258 * even-length headers are used, padding can only be 0 or 2
1259 * bytes and we can optimize this a bit. We must not try to
1260 * remove padding from short control frames that do not have a
1263 * This function expects an 802.11 frame and returns the number of
1266 static int ath5k_remove_padding(struct sk_buff *skb)
1268 int padpos = ath5k_common_padpos(skb);
1269 int padsize = padpos & 3;
1271 if (padsize && skb->len>=padpos+padsize) {
1272 memmove(skb->data + padsize, skb->data, padpos);
1273 skb_pull(skb, padsize);
1281 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1282 struct ath5k_rx_status *rs)
1284 struct ieee80211_rx_status *rxs;
1286 ath5k_remove_padding(skb);
1288 rxs = IEEE80211_SKB_RXCB(skb);
1291 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1292 rxs->flag |= RX_FLAG_MMIC_ERROR;
1295 * always extend the mac timestamp, since this information is
1296 * also needed for proper IBSS merging.
1298 * XXX: it might be too late to do it here, since rs_tstamp is
1299 * 15bit only. that means TSF extension has to be done within
1300 * 32768usec (about 32ms). it might be necessary to move this to
1301 * the interrupt handler, like it is done in madwifi.
1303 * Unfortunately we don't know when the hardware takes the rx
1304 * timestamp (beginning of phy frame, data frame, end of rx?).
1305 * The only thing we know is that it is hardware specific...
1306 * On AR5213 it seems the rx timestamp is at the end of the
1307 * frame, but i'm not sure.
1309 * NOTE: mac80211 defines mactime at the beginning of the first
1310 * data symbol. Since we don't have any time references it's
1311 * impossible to comply to that. This affects IBSS merge only
1312 * right now, so it's not too bad...
1314 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1315 rxs->flag |= RX_FLAG_TSFT;
1317 rxs->freq = sc->curchan->center_freq;
1318 rxs->band = sc->curband->band;
1320 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1322 rxs->antenna = rs->rs_antenna;
1324 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1325 sc->stats.antenna_rx[rs->rs_antenna]++;
1327 sc->stats.antenna_rx[0]++; /* invalid */
1329 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1330 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1332 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1333 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1334 rxs->flag |= RX_FLAG_SHORTPRE;
1336 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1338 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1340 /* check beacons in IBSS mode */
1341 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1342 ath5k_check_ibss_tsf(sc, skb, rxs);
1344 ieee80211_rx(sc->hw, skb);
1347 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1349 * Check if we want to further process this frame or not. Also update
1350 * statistics. Return true if we want this frame, false if not.
1353 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1355 sc->stats.rx_all_count++;
1357 if (unlikely(rs->rs_status)) {
1358 if (rs->rs_status & AR5K_RXERR_CRC)
1359 sc->stats.rxerr_crc++;
1360 if (rs->rs_status & AR5K_RXERR_FIFO)
1361 sc->stats.rxerr_fifo++;
1362 if (rs->rs_status & AR5K_RXERR_PHY) {
1363 sc->stats.rxerr_phy++;
1364 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1365 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1368 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1370 * Decrypt error. If the error occurred
1371 * because there was no hardware key, then
1372 * let the frame through so the upper layers
1373 * can process it. This is necessary for 5210
1374 * parts which have no way to setup a ``clear''
1377 * XXX do key cache faulting
1379 sc->stats.rxerr_decrypt++;
1380 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1381 !(rs->rs_status & AR5K_RXERR_CRC))
1384 if (rs->rs_status & AR5K_RXERR_MIC) {
1385 sc->stats.rxerr_mic++;
1389 /* reject any frames with non-crypto errors */
1390 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1394 if (unlikely(rs->rs_more)) {
1395 sc->stats.rxerr_jumbo++;
1402 ath5k_tasklet_rx(unsigned long data)
1404 struct ath5k_rx_status rs = {};
1405 struct sk_buff *skb, *next_skb;
1406 dma_addr_t next_skb_addr;
1407 struct ath5k_softc *sc = (void *)data;
1408 struct ath5k_hw *ah = sc->ah;
1409 struct ath_common *common = ath5k_hw_common(ah);
1410 struct ath5k_buf *bf;
1411 struct ath5k_desc *ds;
1414 spin_lock(&sc->rxbuflock);
1415 if (list_empty(&sc->rxbuf)) {
1416 ATH5K_WARN(sc, "empty rx buf pool\n");
1420 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1421 BUG_ON(bf->skb == NULL);
1425 /* bail if HW is still using self-linked descriptor */
1426 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1429 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1430 if (unlikely(ret == -EINPROGRESS))
1432 else if (unlikely(ret)) {
1433 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1434 sc->stats.rxerr_proc++;
1438 if (ath5k_receive_frame_ok(sc, &rs)) {
1439 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1442 * If we can't replace bf->skb with a new skb under
1443 * memory pressure, just skip this packet
1448 pci_unmap_single(sc->pdev, bf->skbaddr,
1450 PCI_DMA_FROMDEVICE);
1452 skb_put(skb, rs.rs_datalen);
1454 ath5k_receive_frame(sc, skb, &rs);
1457 bf->skbaddr = next_skb_addr;
1460 list_move_tail(&bf->list, &sc->rxbuf);
1461 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1463 spin_unlock(&sc->rxbuflock);
1471 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1472 struct ath5k_txq *txq)
1474 struct ath5k_softc *sc = hw->priv;
1475 struct ath5k_buf *bf;
1476 unsigned long flags;
1479 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1482 * The hardware expects the header padded to 4 byte boundaries.
1483 * If this is not the case, we add the padding after the header.
1485 padsize = ath5k_add_padding(skb);
1487 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1488 " headroom to pad");
1492 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1493 ieee80211_stop_queue(hw, txq->qnum);
1495 spin_lock_irqsave(&sc->txbuflock, flags);
1496 if (list_empty(&sc->txbuf)) {
1497 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1498 spin_unlock_irqrestore(&sc->txbuflock, flags);
1499 ieee80211_stop_queues(hw);
1502 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1503 list_del(&bf->list);
1505 if (list_empty(&sc->txbuf))
1506 ieee80211_stop_queues(hw);
1507 spin_unlock_irqrestore(&sc->txbuflock, flags);
1511 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1513 spin_lock_irqsave(&sc->txbuflock, flags);
1514 list_add_tail(&bf->list, &sc->txbuf);
1516 spin_unlock_irqrestore(&sc->txbuflock, flags);
1519 return NETDEV_TX_OK;
1522 dev_kfree_skb_any(skb);
1523 return NETDEV_TX_OK;
1527 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1528 struct ath5k_tx_status *ts)
1530 struct ieee80211_tx_info *info;
1533 sc->stats.tx_all_count++;
1534 info = IEEE80211_SKB_CB(skb);
1536 ieee80211_tx_info_clear_status(info);
1537 for (i = 0; i < 4; i++) {
1538 struct ieee80211_tx_rate *r =
1539 &info->status.rates[i];
1541 if (ts->ts_rate[i]) {
1542 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1543 r->count = ts->ts_retry[i];
1550 /* count the successful attempt as well */
1551 info->status.rates[ts->ts_final_idx].count++;
1553 if (unlikely(ts->ts_status)) {
1554 sc->stats.ack_fail++;
1555 if (ts->ts_status & AR5K_TXERR_FILT) {
1556 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1557 sc->stats.txerr_filt++;
1559 if (ts->ts_status & AR5K_TXERR_XRETRY)
1560 sc->stats.txerr_retry++;
1561 if (ts->ts_status & AR5K_TXERR_FIFO)
1562 sc->stats.txerr_fifo++;
1564 info->flags |= IEEE80211_TX_STAT_ACK;
1565 info->status.ack_signal = ts->ts_rssi;
1569 * Remove MAC header padding before giving the frame
1572 ath5k_remove_padding(skb);
1574 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1575 sc->stats.antenna_tx[ts->ts_antenna]++;
1577 sc->stats.antenna_tx[0]++; /* invalid */
1579 ieee80211_tx_status(sc->hw, skb);
1583 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1585 struct ath5k_tx_status ts = {};
1586 struct ath5k_buf *bf, *bf0;
1587 struct ath5k_desc *ds;
1588 struct sk_buff *skb;
1591 spin_lock(&txq->lock);
1592 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1594 txq->txq_poll_mark = false;
1596 /* skb might already have been processed last time. */
1597 if (bf->skb != NULL) {
1600 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1601 if (unlikely(ret == -EINPROGRESS))
1603 else if (unlikely(ret)) {
1605 "error %d while processing "
1606 "queue %u\n", ret, txq->qnum);
1612 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1614 ath5k_tx_frame_completed(sc, skb, &ts);
1618 * It's possible that the hardware can say the buffer is
1619 * completed when it hasn't yet loaded the ds_link from
1620 * host memory and moved on.
1621 * Always keep the last descriptor to avoid HW races...
1623 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1624 spin_lock(&sc->txbuflock);
1625 list_move_tail(&bf->list, &sc->txbuf);
1628 spin_unlock(&sc->txbuflock);
1631 spin_unlock(&txq->lock);
1632 if (txq->txq_len < ATH5K_TXQ_LEN_LOW)
1633 ieee80211_wake_queue(sc->hw, txq->qnum);
1637 ath5k_tasklet_tx(unsigned long data)
1640 struct ath5k_softc *sc = (void *)data;
1642 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1643 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1644 ath5k_tx_processq(sc, &sc->txqs[i]);
1653 * Setup the beacon frame for transmit.
1656 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1658 struct sk_buff *skb = bf->skb;
1659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1660 struct ath5k_hw *ah = sc->ah;
1661 struct ath5k_desc *ds;
1665 const int padsize = 0;
1667 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1669 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1670 "skbaddr %llx\n", skb, skb->data, skb->len,
1671 (unsigned long long)bf->skbaddr);
1672 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1673 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1678 antenna = ah->ah_tx_ant;
1680 flags = AR5K_TXDESC_NOACK;
1681 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1682 ds->ds_link = bf->daddr; /* self-linked */
1683 flags |= AR5K_TXDESC_VEOL;
1688 * If we use multiple antennas on AP and use
1689 * the Sectored AP scenario, switch antenna every
1690 * 4 beacons to make sure everybody hears our AP.
1691 * When a client tries to associate, hw will keep
1692 * track of the tx antenna to be used for this client
1693 * automaticaly, based on ACKed packets.
1695 * Note: AP still listens and transmits RTS on the
1696 * default antenna which is supposed to be an omni.
1698 * Note2: On sectored scenarios it's possible to have
1699 * multiple antennas (1 omni -- the default -- and 14
1700 * sectors), so if we choose to actually support this
1701 * mode, we need to allow the user to set how many antennas
1702 * we have and tweak the code below to send beacons
1705 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1706 antenna = sc->bsent & 4 ? 2 : 1;
1709 /* FIXME: If we are in g mode and rate is a CCK rate
1710 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1711 * from tx power (value is in dB units already) */
1712 ds->ds_data = bf->skbaddr;
1713 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1714 ieee80211_get_hdrlen_from_skb(skb), padsize,
1715 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1716 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1717 1, AR5K_TXKEYIX_INVALID,
1718 antenna, flags, 0, 0);
1724 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1729 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1730 * this is called only once at config_bss time, for AP we do it every
1731 * SWBA interrupt so that the TIM will reflect buffered frames.
1733 * Called with the beacon lock.
1736 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1739 struct ath5k_softc *sc = hw->priv;
1740 struct sk_buff *skb;
1742 if (WARN_ON(!vif)) {
1747 skb = ieee80211_beacon_get(hw, vif);
1754 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1756 ath5k_txbuf_free_skb(sc, sc->bbuf);
1757 sc->bbuf->skb = skb;
1758 ret = ath5k_beacon_setup(sc, sc->bbuf);
1760 sc->bbuf->skb = NULL;
1766 * Transmit a beacon frame at SWBA. Dynamic updates to the
1767 * frame contents are done as needed and the slot time is
1768 * also adjusted based on current state.
1770 * This is called from software irq context (beacontq tasklets)
1771 * or user context from ath5k_beacon_config.
1774 ath5k_beacon_send(struct ath5k_softc *sc)
1776 struct ath5k_buf *bf = sc->bbuf;
1777 struct ath5k_hw *ah = sc->ah;
1778 struct sk_buff *skb;
1780 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1782 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION)) {
1783 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1787 * Check if the previous beacon has gone out. If
1788 * not, don't don't try to post another: skip this
1789 * period and wait for the next. Missed beacons
1790 * indicate a problem and should not occur. If we
1791 * miss too many consecutive beacons reset the device.
1793 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1795 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1796 "missed %u consecutive beacons\n", sc->bmisscount);
1797 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1798 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1799 "stuck beacon time (%u missed)\n",
1801 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1802 "stuck beacon, resetting\n");
1803 ieee80211_queue_work(sc->hw, &sc->reset_work);
1807 if (unlikely(sc->bmisscount != 0)) {
1808 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1809 "resume beacon xmit after %u misses\n",
1815 * Stop any current dma and put the new frame on the queue.
1816 * This should never fail since we check above that no frames
1817 * are still pending on the queue.
1819 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1820 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1821 /* NB: hw still stops DMA, so proceed */
1824 /* refresh the beacon for AP mode */
1825 if (sc->opmode == NL80211_IFTYPE_AP)
1826 ath5k_beacon_update(sc->hw, sc->vif);
1828 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1829 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1830 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1831 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1833 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1835 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1836 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1843 * ath5k_beacon_update_timers - update beacon timers
1845 * @sc: struct ath5k_softc pointer we are operating on
1846 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1847 * beacon timer update based on the current HW TSF.
1849 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1850 * of a received beacon or the current local hardware TSF and write it to the
1851 * beacon timer registers.
1853 * This is called in a variety of situations, e.g. when a beacon is received,
1854 * when a TSF update has been detected, but also when an new IBSS is created or
1855 * when we otherwise know we have to update the timers, but we keep it in this
1856 * function to have it all together in one place.
1859 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1861 struct ath5k_hw *ah = sc->ah;
1862 u32 nexttbtt, intval, hw_tu, bc_tu;
1865 intval = sc->bintval & AR5K_BEACON_PERIOD;
1866 if (WARN_ON(!intval))
1869 /* beacon TSF converted to TU */
1870 bc_tu = TSF_TO_TU(bc_tsf);
1872 /* current TSF converted to TU */
1873 hw_tsf = ath5k_hw_get_tsf64(ah);
1874 hw_tu = TSF_TO_TU(hw_tsf);
1877 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
1880 * no beacons received, called internally.
1881 * just need to refresh timers based on HW TSF.
1883 nexttbtt = roundup(hw_tu + FUDGE, intval);
1884 } else if (bc_tsf == 0) {
1886 * no beacon received, probably called by ath5k_reset_tsf().
1887 * reset TSF to start with 0.
1890 intval |= AR5K_BEACON_RESET_TSF;
1891 } else if (bc_tsf > hw_tsf) {
1893 * beacon received, SW merge happend but HW TSF not yet updated.
1894 * not possible to reconfigure timers yet, but next time we
1895 * receive a beacon with the same BSSID, the hardware will
1896 * automatically update the TSF and then we need to reconfigure
1899 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1900 "need to wait for HW TSF sync\n");
1904 * most important case for beacon synchronization between STA.
1906 * beacon received and HW TSF has been already updated by HW.
1907 * update next TBTT based on the TSF of the beacon, but make
1908 * sure it is ahead of our local TSF timer.
1910 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1914 sc->nexttbtt = nexttbtt;
1916 intval |= AR5K_BEACON_ENA;
1917 ath5k_hw_init_beacon(ah, nexttbtt, intval);
1920 * debugging output last in order to preserve the time critical aspect
1924 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1925 "reconfigured timers based on HW TSF\n");
1926 else if (bc_tsf == 0)
1927 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1928 "reset HW TSF and timers\n");
1930 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1931 "updated timers based on beacon TSF\n");
1933 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1934 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
1935 (unsigned long long) bc_tsf,
1936 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
1937 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
1938 intval & AR5K_BEACON_PERIOD,
1939 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
1940 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
1944 * ath5k_beacon_config - Configure the beacon queues and interrupts
1946 * @sc: struct ath5k_softc pointer we are operating on
1948 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
1949 * interrupts to detect TSF updates only.
1952 ath5k_beacon_config(struct ath5k_softc *sc)
1954 struct ath5k_hw *ah = sc->ah;
1955 unsigned long flags;
1957 spin_lock_irqsave(&sc->block, flags);
1959 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
1961 if (sc->enable_beacon) {
1963 * In IBSS mode we use a self-linked tx descriptor and let the
1964 * hardware send the beacons automatically. We have to load it
1966 * We use the SWBA interrupt only to keep track of the beacon
1967 * timers in order to detect automatic TSF updates.
1969 ath5k_beaconq_config(sc);
1971 sc->imask |= AR5K_INT_SWBA;
1973 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1974 if (ath5k_hw_hasveol(ah))
1975 ath5k_beacon_send(sc);
1977 ath5k_beacon_update_timers(sc, -1);
1979 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
1982 ath5k_hw_set_imr(ah, sc->imask);
1984 spin_unlock_irqrestore(&sc->block, flags);
1987 static void ath5k_tasklet_beacon(unsigned long data)
1989 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1992 * Software beacon alert--time to send a beacon.
1994 * In IBSS mode we use this interrupt just to
1995 * keep track of the next TBTT (target beacon
1996 * transmission time) in order to detect wether
1997 * automatic TSF updates happened.
1999 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2000 /* XXX: only if VEOL suppported */
2001 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2002 sc->nexttbtt += sc->bintval;
2003 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2004 "SWBA nexttbtt: %x hw_tu: %x "
2008 (unsigned long long) tsf);
2010 spin_lock(&sc->block);
2011 ath5k_beacon_send(sc);
2012 spin_unlock(&sc->block);
2017 /********************\
2018 * Interrupt handling *
2019 \********************/
2022 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2024 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2025 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2026 /* run ANI only when full calibration is not active */
2027 ah->ah_cal_next_ani = jiffies +
2028 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2029 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2031 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2032 ah->ah_cal_next_full = jiffies +
2033 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2034 tasklet_schedule(&ah->ah_sc->calib);
2036 /* we could use SWI to generate enough interrupts to meet our
2037 * calibration interval requirements, if necessary:
2038 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2042 ath5k_intr(int irq, void *dev_id)
2044 struct ath5k_softc *sc = dev_id;
2045 struct ath5k_hw *ah = sc->ah;
2046 enum ath5k_int status;
2047 unsigned int counter = 1000;
2049 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2050 !ath5k_hw_is_intr_pending(ah)))
2054 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2055 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2057 if (unlikely(status & AR5K_INT_FATAL)) {
2059 * Fatal errors are unrecoverable.
2060 * Typically these are caused by DMA errors.
2062 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2063 "fatal int, resetting\n");
2064 ieee80211_queue_work(sc->hw, &sc->reset_work);
2065 } else if (unlikely(status & AR5K_INT_RXORN)) {
2067 * Receive buffers are full. Either the bus is busy or
2068 * the CPU is not fast enough to process all received
2070 * Older chipsets need a reset to come out of this
2071 * condition, but we treat it as RX for newer chips.
2072 * We don't know exactly which versions need a reset -
2073 * this guess is copied from the HAL.
2075 sc->stats.rxorn_intr++;
2076 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2077 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2078 "rx overrun, resetting\n");
2079 ieee80211_queue_work(sc->hw, &sc->reset_work);
2082 tasklet_schedule(&sc->rxtq);
2084 if (status & AR5K_INT_SWBA) {
2085 tasklet_hi_schedule(&sc->beacontq);
2087 if (status & AR5K_INT_RXEOL) {
2089 * NB: the hardware should re-read the link when
2090 * RXE bit is written, but it doesn't work at
2091 * least on older hardware revs.
2093 sc->stats.rxeol_intr++;
2095 if (status & AR5K_INT_TXURN) {
2096 /* bump tx trigger level */
2097 ath5k_hw_update_tx_triglevel(ah, true);
2099 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2100 tasklet_schedule(&sc->rxtq);
2101 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2102 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2103 tasklet_schedule(&sc->txtq);
2104 if (status & AR5K_INT_BMISS) {
2107 if (status & AR5K_INT_MIB) {
2108 sc->stats.mib_intr++;
2109 ath5k_hw_update_mib_counters(ah);
2110 ath5k_ani_mib_intr(ah);
2112 if (status & AR5K_INT_GPIO)
2113 tasklet_schedule(&sc->rf_kill.toggleq);
2116 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2118 if (unlikely(!counter))
2119 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2121 ath5k_intr_calibration_poll(ah);
2127 * Periodically recalibrate the PHY to account
2128 * for temperature/environment changes.
2131 ath5k_tasklet_calibrate(unsigned long data)
2133 struct ath5k_softc *sc = (void *)data;
2134 struct ath5k_hw *ah = sc->ah;
2136 /* Only full calibration for now */
2137 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2139 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2140 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2141 sc->curchan->hw_value);
2143 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2145 * Rfgain is out of bounds, reset the chip
2146 * to load new gain values.
2148 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2149 ieee80211_queue_work(sc->hw, &sc->reset_work);
2151 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2152 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2153 ieee80211_frequency_to_channel(
2154 sc->curchan->center_freq));
2156 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2158 * TODO: We should stop TX here, so that it doesn't interfere.
2159 * Note that stopping the queues is not enough to stop TX! */
2160 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2161 ah->ah_cal_next_nf = jiffies +
2162 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2163 ath5k_hw_update_noise_floor(ah);
2166 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2171 ath5k_tasklet_ani(unsigned long data)
2173 struct ath5k_softc *sc = (void *)data;
2174 struct ath5k_hw *ah = sc->ah;
2176 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2177 ath5k_ani_calibration(ah);
2178 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2183 ath5k_tx_complete_poll_work(struct work_struct *work)
2185 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2186 tx_complete_work.work);
2187 struct ath5k_txq *txq;
2189 bool needreset = false;
2191 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2192 if (sc->txqs[i].setup) {
2194 spin_lock_bh(&txq->lock);
2195 if (txq->txq_len > 1) {
2196 if (txq->txq_poll_mark) {
2197 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2198 "TX queue stuck %d\n",
2202 spin_unlock_bh(&txq->lock);
2205 txq->txq_poll_mark = true;
2208 spin_unlock_bh(&txq->lock);
2213 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2214 "TX queues stuck, resetting\n");
2215 ath5k_reset(sc, sc->curchan);
2218 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2219 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2223 /*************************\
2224 * Initialization routines *
2225 \*************************/
2228 ath5k_stop_locked(struct ath5k_softc *sc)
2230 struct ath5k_hw *ah = sc->ah;
2232 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2233 test_bit(ATH_STAT_INVALID, sc->status));
2236 * Shutdown the hardware and driver:
2237 * stop output from above
2238 * disable interrupts
2240 * turn off the radio
2241 * clear transmit machinery
2242 * clear receive machinery
2243 * drain and release tx queues
2244 * reclaim beacon resources
2245 * power down hardware
2247 * Note that some of this work is not possible if the
2248 * hardware is gone (invalid).
2250 ieee80211_stop_queues(sc->hw);
2252 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2254 ath5k_hw_set_imr(ah, 0);
2255 synchronize_irq(sc->pdev->irq);
2257 ath5k_txq_cleanup(sc);
2258 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2260 ath5k_hw_phy_disable(ah);
2267 ath5k_init(struct ath5k_softc *sc)
2269 struct ath5k_hw *ah = sc->ah;
2270 struct ath_common *common = ath5k_hw_common(ah);
2273 mutex_lock(&sc->lock);
2275 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2278 * Stop anything previously setup. This is safe
2279 * no matter this is the first time through or not.
2281 ath5k_stop_locked(sc);
2284 * The basic interface to setting the hardware in a good
2285 * state is ``reset''. On return the hardware is known to
2286 * be powered up and with interrupts disabled. This must
2287 * be followed by initialization of the appropriate bits
2288 * and then setup of the interrupt mask.
2290 sc->curchan = sc->hw->conf.channel;
2291 sc->curband = &sc->sbands[sc->curchan->band];
2292 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2293 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2294 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2296 ret = ath5k_reset(sc, NULL);
2300 ath5k_rfkill_hw_start(ah);
2303 * Reset the key cache since some parts do not reset the
2304 * contents on initial power up or resume from suspend.
2306 for (i = 0; i < common->keymax; i++)
2307 ath_hw_keyreset(common, (u16) i);
2309 ath5k_hw_set_ack_bitrate_high(ah, true);
2313 mutex_unlock(&sc->lock);
2315 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2316 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2321 static void stop_tasklets(struct ath5k_softc *sc)
2323 tasklet_kill(&sc->rxtq);
2324 tasklet_kill(&sc->txtq);
2325 tasklet_kill(&sc->calib);
2326 tasklet_kill(&sc->beacontq);
2327 tasklet_kill(&sc->ani_tasklet);
2331 * Stop the device, grabbing the top-level lock to protect
2332 * against concurrent entry through ath5k_init (which can happen
2333 * if another thread does a system call and the thread doing the
2334 * stop is preempted).
2337 ath5k_stop_hw(struct ath5k_softc *sc)
2341 mutex_lock(&sc->lock);
2342 ret = ath5k_stop_locked(sc);
2343 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2345 * Don't set the card in full sleep mode!
2347 * a) When the device is in this state it must be carefully
2348 * woken up or references to registers in the PCI clock
2349 * domain may freeze the bus (and system). This varies
2350 * by chip and is mostly an issue with newer parts
2351 * (madwifi sources mentioned srev >= 0x78) that go to
2352 * sleep more quickly.
2354 * b) On older chips full sleep results a weird behaviour
2355 * during wakeup. I tested various cards with srev < 0x78
2356 * and they don't wake up after module reload, a second
2357 * module reload is needed to bring the card up again.
2359 * Until we figure out what's going on don't enable
2360 * full chip reset on any chip (this is what Legacy HAL
2361 * and Sam's HAL do anyway). Instead Perform a full reset
2362 * on the device (same as initial state after attach) and
2363 * leave it idle (keep MAC/BB on warm reset) */
2364 ret = ath5k_hw_on_hold(sc->ah);
2366 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2367 "putting device to sleep\n");
2369 ath5k_txbuf_free_skb(sc, sc->bbuf);
2372 mutex_unlock(&sc->lock);
2376 cancel_delayed_work_sync(&sc->tx_complete_work);
2378 ath5k_rfkill_hw_stop(sc->ah);
2384 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2385 * and change to the given channel.
2387 * This should be called with sc->lock.
2390 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2392 struct ath5k_hw *ah = sc->ah;
2395 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2397 ath5k_hw_set_imr(ah, 0);
2398 synchronize_irq(sc->pdev->irq);
2402 ath5k_txq_cleanup(sc);
2406 sc->curband = &sc->sbands[chan->band];
2408 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2410 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2414 ret = ath5k_rx_start(sc);
2416 ATH5K_ERR(sc, "can't start recv logic\n");
2420 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2422 ah->ah_cal_next_full = jiffies;
2423 ah->ah_cal_next_ani = jiffies;
2424 ah->ah_cal_next_nf = jiffies;
2427 * Change channels and update the h/w rate map if we're switching;
2428 * e.g. 11a to 11b/g.
2430 * We may be doing a reset in response to an ioctl that changes the
2431 * channel so update any state that might change as a result.
2435 /* ath5k_chan_change(sc, c); */
2437 ath5k_beacon_config(sc);
2438 /* intrs are enabled by ath5k_beacon_config */
2440 ieee80211_wake_queues(sc->hw);
2447 static void ath5k_reset_work(struct work_struct *work)
2449 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2452 mutex_lock(&sc->lock);
2453 ath5k_reset(sc, sc->curchan);
2454 mutex_unlock(&sc->lock);
2458 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2460 struct ath5k_softc *sc = hw->priv;
2461 struct ath5k_hw *ah = sc->ah;
2462 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2463 struct ath5k_txq *txq;
2464 u8 mac[ETH_ALEN] = {};
2467 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
2470 * Check if the MAC has multi-rate retry support.
2471 * We do this by trying to setup a fake extended
2472 * descriptor. MACs that don't have support will
2473 * return false w/o doing anything. MACs that do
2474 * support it will return true w/o doing anything.
2476 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2481 __set_bit(ATH_STAT_MRRETRY, sc->status);
2484 * Collect the channel list. The 802.11 layer
2485 * is resposible for filtering this list based
2486 * on settings like the phy mode and regulatory
2487 * domain restrictions.
2489 ret = ath5k_setup_bands(hw);
2491 ATH5K_ERR(sc, "can't get channels\n");
2495 /* NB: setup here so ath5k_rate_update is happy */
2496 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2497 ath5k_setcurmode(sc, AR5K_MODE_11A);
2499 ath5k_setcurmode(sc, AR5K_MODE_11B);
2502 * Allocate tx+rx descriptors and populate the lists.
2504 ret = ath5k_desc_alloc(sc, pdev);
2506 ATH5K_ERR(sc, "can't allocate descriptors\n");
2511 * Allocate hardware transmit queues: one queue for
2512 * beacon frames and one data queue for each QoS
2513 * priority. Note that hw functions handle resetting
2514 * these queues at the needed time.
2516 ret = ath5k_beaconq_setup(ah);
2518 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2522 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2523 if (IS_ERR(sc->cabq)) {
2524 ATH5K_ERR(sc, "can't setup cab queue\n");
2525 ret = PTR_ERR(sc->cabq);
2529 /* This order matches mac80211's queue priority, so we can
2530 * directly use the mac80211 queue number without any mapping */
2531 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2533 ATH5K_ERR(sc, "can't setup xmit queue\n");
2537 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2539 ATH5K_ERR(sc, "can't setup xmit queue\n");
2543 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2545 ATH5K_ERR(sc, "can't setup xmit queue\n");
2549 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2551 ATH5K_ERR(sc, "can't setup xmit queue\n");
2557 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2558 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2559 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2560 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2561 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2563 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2564 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2566 ret = ath5k_eeprom_read_mac(ah, mac);
2568 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2573 SET_IEEE80211_PERM_ADDR(hw, mac);
2574 /* All MAC address bits matter for ACKs */
2575 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
2576 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
2578 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2579 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2581 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2585 ret = ieee80211_register_hw(hw);
2587 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2591 if (!ath_is_world_regd(regulatory))
2592 regulatory_hint(hw->wiphy, regulatory->alpha2);
2594 ath5k_init_leds(sc);
2596 ath5k_sysfs_register(sc);
2600 ath5k_txq_release(sc);
2602 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2604 ath5k_desc_free(sc, pdev);
2610 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2612 struct ath5k_softc *sc = hw->priv;
2615 * NB: the order of these is important:
2616 * o call the 802.11 layer before detaching ath5k_hw to
2617 * ensure callbacks into the driver to delete global
2618 * key cache entries can be handled
2619 * o reclaim the tx queue data structures after calling
2620 * the 802.11 layer as we'll get called back to reclaim
2621 * node state and potentially want to use them
2622 * o to cleanup the tx queues the hal is called, so detach
2624 * XXX: ??? detach ath5k_hw ???
2625 * Other than that, it's straightforward...
2627 ieee80211_unregister_hw(hw);
2628 ath5k_desc_free(sc, pdev);
2629 ath5k_txq_release(sc);
2630 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2631 ath5k_unregister_leds(sc);
2633 ath5k_sysfs_unregister(sc);
2635 * NB: can't reclaim these until after ieee80211_ifdetach
2636 * returns because we'll get called back to reclaim node
2637 * state and potentially want to use them.
2641 /********************\
2642 * Mac80211 functions *
2643 \********************/
2646 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2648 struct ath5k_softc *sc = hw->priv;
2649 u16 qnum = skb_get_queue_mapping(skb);
2651 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2652 dev_kfree_skb_any(skb);
2656 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
2659 static int ath5k_start(struct ieee80211_hw *hw)
2661 return ath5k_init(hw->priv);
2664 static void ath5k_stop(struct ieee80211_hw *hw)
2666 ath5k_stop_hw(hw->priv);
2669 static int ath5k_add_interface(struct ieee80211_hw *hw,
2670 struct ieee80211_vif *vif)
2672 struct ath5k_softc *sc = hw->priv;
2675 mutex_lock(&sc->lock);
2683 switch (vif->type) {
2684 case NL80211_IFTYPE_AP:
2685 case NL80211_IFTYPE_STATION:
2686 case NL80211_IFTYPE_ADHOC:
2687 case NL80211_IFTYPE_MESH_POINT:
2688 sc->opmode = vif->type;
2695 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2697 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2698 ath5k_mode_setup(sc);
2702 mutex_unlock(&sc->lock);
2707 ath5k_remove_interface(struct ieee80211_hw *hw,
2708 struct ieee80211_vif *vif)
2710 struct ath5k_softc *sc = hw->priv;
2711 u8 mac[ETH_ALEN] = {};
2713 mutex_lock(&sc->lock);
2717 ath5k_hw_set_lladdr(sc->ah, mac);
2720 mutex_unlock(&sc->lock);
2724 * TODO: Phy disable/diversity etc
2727 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2729 struct ath5k_softc *sc = hw->priv;
2730 struct ath5k_hw *ah = sc->ah;
2731 struct ieee80211_conf *conf = &hw->conf;
2734 mutex_lock(&sc->lock);
2736 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2737 ret = ath5k_chan_set(sc, conf->channel);
2742 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2743 (sc->power_level != conf->power_level)) {
2744 sc->power_level = conf->power_level;
2747 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2751 * 1) Move this on config_interface and handle each case
2752 * separately eg. when we have only one STA vif, use
2753 * AR5K_ANTMODE_SINGLE_AP
2755 * 2) Allow the user to change antenna mode eg. when only
2756 * one antenna is present
2758 * 3) Allow the user to set default/tx antenna when possible
2760 * 4) Default mode should handle 90% of the cases, together
2761 * with fixed a/b and single AP modes we should be able to
2762 * handle 99%. Sectored modes are extreme cases and i still
2763 * haven't found a usage for them. If we decide to support them,
2764 * then we must allow the user to set how many tx antennas we
2767 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
2770 mutex_unlock(&sc->lock);
2774 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2775 struct netdev_hw_addr_list *mc_list)
2779 struct netdev_hw_addr *ha;
2784 netdev_hw_addr_list_for_each(ha, mc_list) {
2785 /* calculate XOR of eight 6-bit values */
2786 val = get_unaligned_le32(ha->addr + 0);
2787 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2788 val = get_unaligned_le32(ha->addr + 3);
2789 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2791 mfilt[pos / 32] |= (1 << (pos % 32));
2792 /* XXX: we might be able to just do this instead,
2793 * but not sure, needs testing, if we do use this we'd
2794 * neet to inform below to not reset the mcast */
2795 /* ath5k_hw_set_mcast_filterindex(ah,
2799 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2802 #define SUPPORTED_FIF_FLAGS \
2803 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2804 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2805 FIF_BCN_PRBRESP_PROMISC
2807 * o always accept unicast, broadcast, and multicast traffic
2808 * o multicast traffic for all BSSIDs will be enabled if mac80211
2810 * o maintain current state of phy ofdm or phy cck error reception.
2811 * If the hardware detects any of these type of errors then
2812 * ath5k_hw_get_rx_filter() will pass to us the respective
2813 * hardware filters to be able to receive these type of frames.
2814 * o probe request frames are accepted only when operating in
2815 * hostap, adhoc, or monitor modes
2816 * o enable promiscuous mode according to the interface state
2818 * - when operating in adhoc mode so the 802.11 layer creates
2819 * node table entries for peers,
2820 * - when operating in station mode for collecting rssi data when
2821 * the station is otherwise quiet, or
2824 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2825 unsigned int changed_flags,
2826 unsigned int *new_flags,
2829 struct ath5k_softc *sc = hw->priv;
2830 struct ath5k_hw *ah = sc->ah;
2831 u32 mfilt[2], rfilt;
2833 mutex_lock(&sc->lock);
2835 mfilt[0] = multicast;
2836 mfilt[1] = multicast >> 32;
2838 /* Only deal with supported flags */
2839 changed_flags &= SUPPORTED_FIF_FLAGS;
2840 *new_flags &= SUPPORTED_FIF_FLAGS;
2842 /* If HW detects any phy or radar errors, leave those filters on.
2843 * Also, always enable Unicast, Broadcasts and Multicast
2844 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2845 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2846 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2847 AR5K_RX_FILTER_MCAST);
2849 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2850 if (*new_flags & FIF_PROMISC_IN_BSS) {
2851 __set_bit(ATH_STAT_PROMISC, sc->status);
2853 __clear_bit(ATH_STAT_PROMISC, sc->status);
2857 if (test_bit(ATH_STAT_PROMISC, sc->status))
2858 rfilt |= AR5K_RX_FILTER_PROM;
2860 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2861 if (*new_flags & FIF_ALLMULTI) {
2866 /* This is the best we can do */
2867 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2868 rfilt |= AR5K_RX_FILTER_PHYERR;
2870 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2871 * and probes for any BSSID */
2872 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2873 rfilt |= AR5K_RX_FILTER_BEACON;
2875 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2876 * set we should only pass on control frames for this
2877 * station. This needs testing. I believe right now this
2878 * enables *all* control frames, which is OK.. but
2879 * but we should see if we can improve on granularity */
2880 if (*new_flags & FIF_CONTROL)
2881 rfilt |= AR5K_RX_FILTER_CONTROL;
2883 /* Additional settings per mode -- this is per ath5k */
2885 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2887 switch (sc->opmode) {
2888 case NL80211_IFTYPE_MESH_POINT:
2889 rfilt |= AR5K_RX_FILTER_CONTROL |
2890 AR5K_RX_FILTER_BEACON |
2891 AR5K_RX_FILTER_PROBEREQ |
2892 AR5K_RX_FILTER_PROM;
2894 case NL80211_IFTYPE_AP:
2895 case NL80211_IFTYPE_ADHOC:
2896 rfilt |= AR5K_RX_FILTER_PROBEREQ |
2897 AR5K_RX_FILTER_BEACON;
2899 case NL80211_IFTYPE_STATION:
2901 rfilt |= AR5K_RX_FILTER_BEACON;
2907 ath5k_hw_set_rx_filter(ah, rfilt);
2909 /* Set multicast bits */
2910 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2911 /* Set the cached hw filter flags, this will later actually
2913 sc->filter_flags = rfilt;
2915 mutex_unlock(&sc->lock);
2919 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2920 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2921 struct ieee80211_key_conf *key)
2923 struct ath5k_softc *sc = hw->priv;
2924 struct ath5k_hw *ah = sc->ah;
2925 struct ath_common *common = ath5k_hw_common(ah);
2928 if (modparam_nohwcrypt)
2931 switch (key->cipher) {
2932 case WLAN_CIPHER_SUITE_WEP40:
2933 case WLAN_CIPHER_SUITE_WEP104:
2934 case WLAN_CIPHER_SUITE_TKIP:
2936 case WLAN_CIPHER_SUITE_CCMP:
2937 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
2945 mutex_lock(&sc->lock);
2949 ret = ath_key_config(common, vif, sta, key);
2951 key->hw_key_idx = ret;
2952 /* push IV and Michael MIC generation to stack */
2953 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2954 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
2955 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2956 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
2957 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2962 ath_key_delete(common, key);
2969 mutex_unlock(&sc->lock);
2974 ath5k_get_stats(struct ieee80211_hw *hw,
2975 struct ieee80211_low_level_stats *stats)
2977 struct ath5k_softc *sc = hw->priv;
2980 ath5k_hw_update_mib_counters(sc->ah);
2982 stats->dot11ACKFailureCount = sc->stats.ack_fail;
2983 stats->dot11RTSFailureCount = sc->stats.rts_fail;
2984 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
2985 stats->dot11FCSErrorCount = sc->stats.fcs_error;
2990 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
2991 struct survey_info *survey)
2993 struct ath5k_softc *sc = hw->priv;
2994 struct ieee80211_conf *conf = &hw->conf;
2999 survey->channel = conf->channel;
3000 survey->filled = SURVEY_INFO_NOISE_DBM;
3001 survey->noise = sc->ah->ah_noise_floor;
3007 ath5k_get_tsf(struct ieee80211_hw *hw)
3009 struct ath5k_softc *sc = hw->priv;
3011 return ath5k_hw_get_tsf64(sc->ah);
3015 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3017 struct ath5k_softc *sc = hw->priv;
3019 ath5k_hw_set_tsf64(sc->ah, tsf);
3023 ath5k_reset_tsf(struct ieee80211_hw *hw)
3025 struct ath5k_softc *sc = hw->priv;
3028 * in IBSS mode we need to update the beacon timers too.
3029 * this will also reset the TSF if we call it with 0
3031 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3032 ath5k_beacon_update_timers(sc, 0);
3034 ath5k_hw_reset_tsf(sc->ah);
3038 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3040 struct ath5k_softc *sc = hw->priv;
3041 struct ath5k_hw *ah = sc->ah;
3043 rfilt = ath5k_hw_get_rx_filter(ah);
3045 rfilt |= AR5K_RX_FILTER_BEACON;
3047 rfilt &= ~AR5K_RX_FILTER_BEACON;
3048 ath5k_hw_set_rx_filter(ah, rfilt);
3049 sc->filter_flags = rfilt;
3052 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3053 struct ieee80211_vif *vif,
3054 struct ieee80211_bss_conf *bss_conf,
3057 struct ath5k_softc *sc = hw->priv;
3058 struct ath5k_hw *ah = sc->ah;
3059 struct ath_common *common = ath5k_hw_common(ah);
3060 unsigned long flags;
3062 mutex_lock(&sc->lock);
3063 if (WARN_ON(sc->vif != vif))
3066 if (changes & BSS_CHANGED_BSSID) {
3067 /* Cache for later use during resets */
3068 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3070 ath5k_hw_set_bssid(ah);
3074 if (changes & BSS_CHANGED_BEACON_INT)
3075 sc->bintval = bss_conf->beacon_int;
3077 if (changes & BSS_CHANGED_ASSOC) {
3078 sc->assoc = bss_conf->assoc;
3079 if (sc->opmode == NL80211_IFTYPE_STATION)
3080 set_beacon_filter(hw, sc->assoc);
3081 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3082 AR5K_LED_ASSOC : AR5K_LED_INIT);
3083 if (bss_conf->assoc) {
3084 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3085 "Bss Info ASSOC %d, bssid: %pM\n",
3086 bss_conf->aid, common->curbssid);
3087 common->curaid = bss_conf->aid;
3088 ath5k_hw_set_bssid(ah);
3089 /* Once ANI is available you would start it here */
3093 if (changes & BSS_CHANGED_BEACON) {
3094 spin_lock_irqsave(&sc->block, flags);
3095 ath5k_beacon_update(hw, vif);
3096 spin_unlock_irqrestore(&sc->block, flags);
3099 if (changes & BSS_CHANGED_BEACON_ENABLED)
3100 sc->enable_beacon = bss_conf->enable_beacon;
3102 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3103 BSS_CHANGED_BEACON_INT))
3104 ath5k_beacon_config(sc);
3107 mutex_unlock(&sc->lock);
3110 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3112 struct ath5k_softc *sc = hw->priv;
3114 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3117 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3119 struct ath5k_softc *sc = hw->priv;
3120 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3121 AR5K_LED_ASSOC : AR5K_LED_INIT);
3125 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3127 * @hw: struct ieee80211_hw pointer
3128 * @coverage_class: IEEE 802.11 coverage class number
3130 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3131 * coverage class. The values are persistent, they are restored after device
3134 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3136 struct ath5k_softc *sc = hw->priv;
3138 mutex_lock(&sc->lock);
3139 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3140 mutex_unlock(&sc->lock);
3143 static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3144 const struct ieee80211_tx_queue_params *params)
3146 struct ath5k_softc *sc = hw->priv;
3147 struct ath5k_hw *ah = sc->ah;
3148 struct ath5k_txq_info qi;
3151 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3154 mutex_lock(&sc->lock);
3156 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3158 qi.tqi_aifs = params->aifs;
3159 qi.tqi_cw_min = params->cw_min;
3160 qi.tqi_cw_max = params->cw_max;
3161 qi.tqi_burst_time = params->txop;
3163 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3164 "Configure tx [queue %d], "
3165 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3166 queue, params->aifs, params->cw_min,
3167 params->cw_max, params->txop);
3169 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3171 "Unable to update hardware queue %u!\n", queue);
3174 ath5k_hw_reset_tx_queue(ah, queue);
3176 mutex_unlock(&sc->lock);
3181 static const struct ieee80211_ops ath5k_hw_ops = {
3183 .start = ath5k_start,
3185 .add_interface = ath5k_add_interface,
3186 .remove_interface = ath5k_remove_interface,
3187 .config = ath5k_config,
3188 .prepare_multicast = ath5k_prepare_multicast,
3189 .configure_filter = ath5k_configure_filter,
3190 .set_key = ath5k_set_key,
3191 .get_stats = ath5k_get_stats,
3192 .get_survey = ath5k_get_survey,
3193 .conf_tx = ath5k_conf_tx,
3194 .get_tsf = ath5k_get_tsf,
3195 .set_tsf = ath5k_set_tsf,
3196 .reset_tsf = ath5k_reset_tsf,
3197 .bss_info_changed = ath5k_bss_info_changed,
3198 .sw_scan_start = ath5k_sw_scan_start,
3199 .sw_scan_complete = ath5k_sw_scan_complete,
3200 .set_coverage_class = ath5k_set_coverage_class,
3203 /********************\
3204 * PCI Initialization *
3205 \********************/
3207 static int __devinit
3208 ath5k_pci_probe(struct pci_dev *pdev,
3209 const struct pci_device_id *id)
3212 struct ath5k_softc *sc;
3213 struct ath_common *common;
3214 struct ieee80211_hw *hw;
3219 * L0s needs to be disabled on all ath5k cards.
3221 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3222 * by default in the future in 2.6.36) this will also mean both L1 and
3223 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3224 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3225 * though but cannot currently undue the effect of a blacklist, for
3226 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3227 * the device link capability.
3229 * It may be possible in the future to implement some PCI API to allow
3230 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3231 * best to accept that both L0s and L1 will be disabled completely for
3232 * distributions shipping with CONFIG_PCIEASPM rather than having this
3233 * issue present. Motivation for adding this new API will be to help
3234 * with power consumption for some of these devices.
3236 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3238 ret = pci_enable_device(pdev);
3240 dev_err(&pdev->dev, "can't enable device\n");
3244 /* XXX 32-bit addressing only */
3245 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3247 dev_err(&pdev->dev, "32-bit DMA not available\n");
3252 * Cache line size is used to size and align various
3253 * structures used to communicate with the hardware.
3255 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3258 * Linux 2.4.18 (at least) writes the cache line size
3259 * register as a 16-bit wide register which is wrong.
3260 * We must have this setup properly for rx buffer
3261 * DMA to work so force a reasonable value here if it
3264 csz = L1_CACHE_BYTES >> 2;
3265 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3268 * The default setting of latency timer yields poor results,
3269 * set it to the value used by other systems. It may be worth
3270 * tweaking this setting more.
3272 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3274 /* Enable bus mastering */
3275 pci_set_master(pdev);
3278 * Disable the RETRY_TIMEOUT register (0x41) to keep
3279 * PCI Tx retries from interfering with C3 CPU state.
3281 pci_write_config_byte(pdev, 0x41, 0);
3283 ret = pci_request_region(pdev, 0, "ath5k");
3285 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3289 mem = pci_iomap(pdev, 0, 0);
3291 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3297 * Allocate hw (mac80211 main struct)
3298 * and hw->priv (driver private data)
3300 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3302 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3307 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3309 /* Initialize driver private data */
3310 SET_IEEE80211_DEV(hw, &pdev->dev);
3311 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3312 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3313 IEEE80211_HW_SIGNAL_DBM;
3315 hw->wiphy->interface_modes =
3316 BIT(NL80211_IFTYPE_AP) |
3317 BIT(NL80211_IFTYPE_STATION) |
3318 BIT(NL80211_IFTYPE_ADHOC) |
3319 BIT(NL80211_IFTYPE_MESH_POINT);
3321 hw->extra_tx_headroom = 2;
3322 hw->channel_change_time = 5000;
3327 ath5k_debug_init_device(sc);
3330 * Mark the device as detached to avoid processing
3331 * interrupts until setup is complete.
3333 __set_bit(ATH_STAT_INVALID, sc->status);
3335 sc->iobase = mem; /* So we can unmap it on detach */
3336 sc->opmode = NL80211_IFTYPE_STATION;
3338 mutex_init(&sc->lock);
3339 spin_lock_init(&sc->rxbuflock);
3340 spin_lock_init(&sc->txbuflock);
3341 spin_lock_init(&sc->block);
3343 /* Set private data */
3344 pci_set_drvdata(pdev, sc);
3346 /* Setup interrupt handler */
3347 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3349 ATH5K_ERR(sc, "request_irq failed\n");
3353 /* If we passed the test, malloc an ath5k_hw struct */
3354 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3357 ATH5K_ERR(sc, "out of memory\n");
3362 sc->ah->ah_iobase = sc->iobase;
3363 common = ath5k_hw_common(sc->ah);
3364 common->ops = &ath5k_common_ops;
3365 common->ah = sc->ah;
3367 common->cachelsz = csz << 2; /* convert to bytes */
3369 /* Initialize device */
3370 ret = ath5k_hw_attach(sc);
3375 /* set up multi-rate retry capabilities */
3376 if (sc->ah->ah_version == AR5K_AR5212) {
3378 hw->max_rate_tries = 11;
3381 /* Finish private driver data initialization */
3382 ret = ath5k_attach(pdev, hw);
3386 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3387 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3388 sc->ah->ah_mac_srev,
3389 sc->ah->ah_phy_revision);
3391 if (!sc->ah->ah_single_chip) {
3392 /* Single chip radio (!RF5111) */
3393 if (sc->ah->ah_radio_5ghz_revision &&
3394 !sc->ah->ah_radio_2ghz_revision) {
3395 /* No 5GHz support -> report 2GHz radio */
3396 if (!test_bit(AR5K_MODE_11A,
3397 sc->ah->ah_capabilities.cap_mode)) {
3398 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3399 ath5k_chip_name(AR5K_VERSION_RAD,
3400 sc->ah->ah_radio_5ghz_revision),
3401 sc->ah->ah_radio_5ghz_revision);
3402 /* No 2GHz support (5110 and some
3403 * 5Ghz only cards) -> report 5Ghz radio */
3404 } else if (!test_bit(AR5K_MODE_11B,
3405 sc->ah->ah_capabilities.cap_mode)) {
3406 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3407 ath5k_chip_name(AR5K_VERSION_RAD,
3408 sc->ah->ah_radio_5ghz_revision),
3409 sc->ah->ah_radio_5ghz_revision);
3410 /* Multiband radio */
3412 ATH5K_INFO(sc, "RF%s multiband radio found"
3414 ath5k_chip_name(AR5K_VERSION_RAD,
3415 sc->ah->ah_radio_5ghz_revision),
3416 sc->ah->ah_radio_5ghz_revision);
3419 /* Multi chip radio (RF5111 - RF2111) ->
3420 * report both 2GHz/5GHz radios */
3421 else if (sc->ah->ah_radio_5ghz_revision &&
3422 sc->ah->ah_radio_2ghz_revision){
3423 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3424 ath5k_chip_name(AR5K_VERSION_RAD,
3425 sc->ah->ah_radio_5ghz_revision),
3426 sc->ah->ah_radio_5ghz_revision);
3427 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3428 ath5k_chip_name(AR5K_VERSION_RAD,
3429 sc->ah->ah_radio_2ghz_revision),
3430 sc->ah->ah_radio_2ghz_revision);
3435 /* ready to process interrupts */
3436 __clear_bit(ATH_STAT_INVALID, sc->status);
3440 ath5k_hw_detach(sc->ah);
3444 free_irq(pdev->irq, sc);
3446 ieee80211_free_hw(hw);
3448 pci_iounmap(pdev, mem);
3450 pci_release_region(pdev, 0);
3452 pci_disable_device(pdev);
3457 static void __devexit
3458 ath5k_pci_remove(struct pci_dev *pdev)
3460 struct ath5k_softc *sc = pci_get_drvdata(pdev);
3462 ath5k_debug_finish_device(sc);
3463 ath5k_detach(pdev, sc->hw);
3464 ath5k_hw_detach(sc->ah);
3466 free_irq(pdev->irq, sc);
3467 pci_iounmap(pdev, sc->iobase);
3468 pci_release_region(pdev, 0);
3469 pci_disable_device(pdev);
3470 ieee80211_free_hw(sc->hw);
3473 #ifdef CONFIG_PM_SLEEP
3474 static int ath5k_pci_suspend(struct device *dev)
3476 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3482 static int ath5k_pci_resume(struct device *dev)
3484 struct pci_dev *pdev = to_pci_dev(dev);
3485 struct ath5k_softc *sc = pci_get_drvdata(pdev);
3488 * Suspend/Resume resets the PCI configuration space, so we have to
3489 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3490 * PCI Tx retries from interfering with C3 CPU state
3492 pci_write_config_byte(pdev, 0x41, 0);
3494 ath5k_led_enable(sc);
3498 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3499 #define ATH5K_PM_OPS (&ath5k_pm_ops)
3501 #define ATH5K_PM_OPS NULL
3502 #endif /* CONFIG_PM_SLEEP */
3504 static struct pci_driver ath5k_pci_driver = {
3505 .name = KBUILD_MODNAME,
3506 .id_table = ath5k_pci_id_table,
3507 .probe = ath5k_pci_probe,
3508 .remove = __devexit_p(ath5k_pci_remove),
3509 .driver.pm = ATH5K_PM_OPS,
3513 * Module init/exit functions
3516 init_ath5k_pci(void)
3522 ret = pci_register_driver(&ath5k_pci_driver);
3524 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3532 exit_ath5k_pci(void)
3534 pci_unregister_driver(&ath5k_pci_driver);
3536 ath5k_debug_finish();
3539 module_init(init_ath5k_pci);
3540 module_exit(exit_ath5k_pci);