drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
  43         /* ADMtek ADM8211 */
  44         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  45         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  46         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  47         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  48         { 0 }
  49 };
  50
  51 static struct ieee80211_rate adm8211_rates[] = {
  52         { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  53         { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  54         { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  55         { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  56         { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  57 };
  58
  59 static const struct ieee80211_channel adm8211_channels[] = {
  60         { .center_freq = 2412},
  61         { .center_freq = 2417},
  62         { .center_freq = 2422},
  63         { .center_freq = 2427},
  64         { .center_freq = 2432},
  65         { .center_freq = 2437},
  66         { .center_freq = 2442},
  67         { .center_freq = 2447},
  68         { .center_freq = 2452},
  69         { .center_freq = 2457},
  70         { .center_freq = 2462},
  71         { .center_freq = 2467},
  72         { .center_freq = 2472},
  73         { .center_freq = 2484},
  74 };
  75
  76
  77 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  78 {
  79         struct adm8211_priv *priv = eeprom->data;
  80         u32 reg = ADM8211_CSR_READ(SPR);
  81
  82         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  83         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  84         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  85         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  86 }
  87
  88 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  89 {
  90         struct adm8211_priv *priv = eeprom->data;
  91         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  92
  93         if (eeprom->reg_data_in)
  94                 reg |= ADM8211_SPR_SDI;
  95         if (eeprom->reg_data_out)
  96                 reg |= ADM8211_SPR_SDO;
  97         if (eeprom->reg_data_clock)
  98                 reg |= ADM8211_SPR_SCLK;
  99         if (eeprom->reg_chip_select)
 100                 reg |= ADM8211_SPR_SCS;
 101
 102         ADM8211_CSR_WRITE(SPR, reg);
 103         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
 104 }
 105
 106 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
 107 {
 108         struct adm8211_priv *priv = dev->priv;
 109         unsigned int words, i;
 110         struct ieee80211_chan_range chan_range;
 111         u16 cr49;
 112         struct eeprom_93cx6 eeprom = {
 113                 .data           = priv,
 114                 .register_read  = adm8211_eeprom_register_read,
 115                 .register_write = adm8211_eeprom_register_write
 116         };
 117
 118         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
 119                 /* 256 * 16-bit = 512 bytes */
 120                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 121                 words = 256;
 122         } else {
 123                 /* 64 * 16-bit = 128 bytes */
 124                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 125                 words = 64;
 126         }
 127
 128         priv->eeprom_len = words * 2;
 129         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 130         if (!priv->eeprom)
 131                 return -ENOMEM;
 132
 133         eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
 134
 135         cr49 = le16_to_cpu(priv->eeprom->cr49);
 136         priv->rf_type = (cr49 >> 3) & 0x7;
 137         switch (priv->rf_type) {
 138         case ADM8211_TYPE_INTERSIL:
 139         case ADM8211_TYPE_RFMD:
 140         case ADM8211_TYPE_MARVEL:
 141         case ADM8211_TYPE_AIROHA:
 142         case ADM8211_TYPE_ADMTEK:
 143                 break;
 144
 145         default:
 146                 if (priv->pdev->revision < ADM8211_REV_CA)
 147                         priv->rf_type = ADM8211_TYPE_RFMD;
 148                 else
 149                         priv->rf_type = ADM8211_TYPE_AIROHA;
 150
 151                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 152                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 153         }
 154
 155         priv->bbp_type = cr49 & 0x7;
 156         switch (priv->bbp_type) {
 157         case ADM8211_TYPE_INTERSIL:
 158         case ADM8211_TYPE_RFMD:
 159         case ADM8211_TYPE_MARVEL:
 160         case ADM8211_TYPE_AIROHA:
 161         case ADM8211_TYPE_ADMTEK:
 162                 break;
 163         default:
 164                 if (priv->pdev->revision < ADM8211_REV_CA)
 165                         priv->bbp_type = ADM8211_TYPE_RFMD;
 166                 else
 167                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 168
 169                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 170                        pci_name(priv->pdev), cr49 >> 3);
 171         }
 172
 173         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 174                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 175                        pci_name(priv->pdev), priv->eeprom->country_code);
 176
 177                 chan_range = cranges[2];
 178         } else
 179                 chan_range = cranges[priv->eeprom->country_code];
 180
 181         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 182                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 183
 184         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
 185
 186         memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
 187         priv->band.channels = priv->channels;
 188         priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
 189         priv->band.bitrates = adm8211_rates;
 190         priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
 191
 192         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 193                 if (i < chan_range.min || i > chan_range.max)
 194                         priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
 195
 196         switch (priv->eeprom->specific_bbptype) {
 197         case ADM8211_BBP_RFMD3000:
 198         case ADM8211_BBP_RFMD3002:
 199         case ADM8211_BBP_ADM8011:
 200                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 201                 break;
 202
 203         default:
 204                 if (priv->pdev->revision < ADM8211_REV_CA)
 205                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 206                 else
 207                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 208
 209                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 210                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 211         }
 212
 213         switch (priv->eeprom->specific_rftype) {
 214         case ADM8211_RFMD2948:
 215         case ADM8211_RFMD2958:
 216         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 217         case ADM8211_MAX2820:
 218         case ADM8211_AL2210L:
 219                 priv->transceiver_type = priv->eeprom->specific_rftype;
 220                 break;
 221
 222         default:
 223                 if (priv->pdev->revision == ADM8211_REV_BA)
 224                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 225                 else if (priv->pdev->revision == ADM8211_REV_CA)
 226                         priv->transceiver_type = ADM8211_AL2210L;
 227                 else if (priv->pdev->revision == ADM8211_REV_AB)
 228                         priv->transceiver_type = ADM8211_RFMD2948;
 229
 230                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 231                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 232
 233                 break;
 234         }
 235
 236         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 237                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 238                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 239
 240         return 0;
 241 }
 242
 243 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 244                                       u32 addr, u32 data)
 245 {
 246         struct adm8211_priv *priv = dev->priv;
 247
 248         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 249                           (priv->pdev->revision < ADM8211_REV_BA ?
 250                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 251         ADM8211_CSR_READ(WEPCTL);
 252         msleep(1);
 253
 254         ADM8211_CSR_WRITE(WESK, data);
 255         ADM8211_CSR_READ(WESK);
 256         msleep(1);
 257 }
 258
 259 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 260                                      unsigned int addr, u8 *buf,
 261                                      unsigned int len)
 262 {
 263         struct adm8211_priv *priv = dev->priv;
 264         u32 reg = ADM8211_CSR_READ(WEPCTL);
 265         unsigned int i;
 266
 267         if (priv->pdev->revision < ADM8211_REV_BA) {
 268                 for (i = 0; i < len; i += 2) {
 269                         u16 val = buf[i] | (buf[i + 1] << 8);
 270                         adm8211_write_sram(dev, addr + i / 2, val);
 271                 }
 272         } else {
 273                 for (i = 0; i < len; i += 4) {
 274                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 275                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 276                         adm8211_write_sram(dev, addr + i / 4, val);
 277                 }
 278         }
 279
 280         ADM8211_CSR_WRITE(WEPCTL, reg);
 281 }
 282
 283 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 284 {
 285         struct adm8211_priv *priv = dev->priv;
 286         u32 reg = ADM8211_CSR_READ(WEPCTL);
 287         unsigned int addr;
 288
 289         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 290                 adm8211_write_sram(dev, addr, 0);
 291
 292         ADM8211_CSR_WRITE(WEPCTL, reg);
 293 }
 294
 295 static int adm8211_get_stats(struct ieee80211_hw *dev,
 296                              struct ieee80211_low_level_stats *stats)
 297 {
 298         struct adm8211_priv *priv = dev->priv;
 299
 300         memcpy(stats, &priv->stats, sizeof(*stats));
 301
 302         return 0;
 303 }
 304
 305 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 306 {
 307         struct adm8211_priv *priv = dev->priv;
 308         unsigned int dirty_tx;
 309
 310         spin_lock(&priv->lock);
 311
 312         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 313                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 314                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 315                 struct ieee80211_tx_info *txi;
 316                 struct adm8211_tx_ring_info *info;
 317                 struct sk_buff *skb;
 318
 319                 if (status & TDES0_CONTROL_OWN ||
 320                     !(status & TDES0_CONTROL_DONE))
 321                         break;
 322
 323                 info = &priv->tx_buffers[entry];
 324                 skb = info->skb;
 325                 txi = IEEE80211_SKB_CB(skb);
 326
 327                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 328
 329                 pci_unmap_single(priv->pdev, info->mapping,
 330                                  info->skb->len, PCI_DMA_TODEVICE);
 331
 332                 ieee80211_tx_info_clear_status(txi);
 333
 334                 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 335                 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 336                 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
 337                     !(status & TDES0_STATUS_ES))
 338                         txi->flags |= IEEE80211_TX_STAT_ACK;
 339
 340                 ieee80211_tx_status_irqsafe(dev, skb);
 341
 342                 info->skb = NULL;
 343         }
 344
 345         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 346                 ieee80211_wake_queue(dev, 0);
 347
 348         priv->dirty_tx = dirty_tx;
 349         spin_unlock(&priv->lock);
 350 }
 351
 352
 353 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 354 {
 355         struct adm8211_priv *priv = dev->priv;
 356         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 357         u32 status;
 358         unsigned int pktlen;
 359         struct sk_buff *skb, *newskb;
 360         unsigned int limit = priv->rx_ring_size;
 361         u8 rssi, rate;
 362
 363         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 364                 if (!limit--)
 365                         break;
 366
 367                 status = le32_to_cpu(priv->rx_ring[entry].status);
 368                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 369                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 370                         RDES1_STATUS_RSSI;
 371
 372                 pktlen = status & RDES0_STATUS_FL;
 373                 if (pktlen > RX_PKT_SIZE) {
 374                         if (net_ratelimit())
 375                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 376                                        wiphy_name(dev->wiphy), pktlen);
 377                         pktlen = RX_PKT_SIZE;
 378                 }
 379
 380                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 381                         skb = NULL; /* old buffer will be reused */
 382                         /* TODO: update RX error stats */
 383                         /* TODO: check RDES0_STATUS_CRC*E */
 384                 } else if (pktlen < RX_COPY_BREAK) {
 385                         skb = dev_alloc_skb(pktlen);
 386                         if (skb) {
 387                                 pci_dma_sync_single_for_cpu(
 388                                         priv->pdev,
 389                                         priv->rx_buffers[entry].mapping,
 390                                         pktlen, PCI_DMA_FROMDEVICE);
 391                                 memcpy(skb_put(skb, pktlen),
 392                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 393                                        pktlen);
 394                                 pci_dma_sync_single_for_device(
 395                                         priv->pdev,
 396                                         priv->rx_buffers[entry].mapping,
 397                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 398                         }
 399                 } else {
 400                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 401                         if (newskb) {
 402                                 skb = priv->rx_buffers[entry].skb;
 403                                 skb_put(skb, pktlen);
 404                                 pci_unmap_single(
 405                                         priv->pdev,
 406                                         priv->rx_buffers[entry].mapping,
 407                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 408                                 priv->rx_buffers[entry].skb = newskb;
 409                                 priv->rx_buffers[entry].mapping =
 410                                         pci_map_single(priv->pdev,
 411                                                        skb_tail_pointer(newskb),
 412                                                        RX_PKT_SIZE,
 413                                                        PCI_DMA_FROMDEVICE);
 414                         } else {
 415                                 skb = NULL;
 416                                 /* TODO: update rx dropped stats */
 417                         }
 418
 419                         priv->rx_ring[entry].buffer1 =
 420                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 421                 }
 422
 423                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 424                                                           RDES0_STATUS_SQL);
 425                 priv->rx_ring[entry].length =
 426                         cpu_to_le32(RX_PKT_SIZE |
 427                                     (entry == priv->rx_ring_size - 1 ?
 428                                      RDES1_CONTROL_RER : 0));
 429
 430                 if (skb) {
 431                         struct ieee80211_rx_status rx_status = {0};
 432
 433                         if (priv->pdev->revision < ADM8211_REV_CA)
 434                                 rx_status.signal = rssi;
 435                         else
 436                                 rx_status.signal = 100 - rssi;
 437
 438                         rx_status.rate_idx = rate;
 439
 440                         rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
 441                         rx_status.band = IEEE80211_BAND_2GHZ;
 442
 443                         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 444                         ieee80211_rx_irqsafe(dev, skb);
 445                 }
 446
 447                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 448         }
 449
 450         /* TODO: check LPC and update stats? */
 451 }
 452
 453
 454 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 455 {
 456 #define ADM8211_INT(x)                                                     \
 457 do {                                                                       \
 458         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 459                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 460 } while (0)
 461
 462         struct ieee80211_hw *dev = dev_id;
 463         struct adm8211_priv *priv = dev->priv;
 464         u32 stsr = ADM8211_CSR_READ(STSR);
 465         ADM8211_CSR_WRITE(STSR, stsr);
 466         if (stsr == 0xffffffff)
 467                 return IRQ_HANDLED;
 468
 469         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 470                 return IRQ_HANDLED;
 471
 472         if (stsr & ADM8211_STSR_RCI)
 473                 adm8211_interrupt_rci(dev);
 474         if (stsr & ADM8211_STSR_TCI)
 475                 adm8211_interrupt_tci(dev);
 476
 477         ADM8211_INT(PCF);
 478         ADM8211_INT(BCNTC);
 479         ADM8211_INT(GPINT);
 480         ADM8211_INT(ATIMTC);
 481         ADM8211_INT(TSFTF);
 482         ADM8211_INT(TSCZ);
 483         ADM8211_INT(SQL);
 484         ADM8211_INT(WEPTD);
 485         ADM8211_INT(ATIME);
 486         ADM8211_INT(TEIS);
 487         ADM8211_INT(FBE);
 488         ADM8211_INT(REIS);
 489         ADM8211_INT(GPTT);
 490         ADM8211_INT(RPS);
 491         ADM8211_INT(RDU);
 492         ADM8211_INT(TUF);
 493         ADM8211_INT(TPS);
 494
 495         return IRQ_HANDLED;
 496
 497 #undef ADM8211_INT
 498 }
 499
 500 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 501 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 502                                            u16 addr, u32 value) {            \
 503         struct adm8211_priv *priv = dev->priv;                               \
 504         unsigned int i;                                                      \
 505         u32 reg, bitbuf;                                                     \
 506                                                                              \
 507         value &= v_mask;                                                     \
 508         addr &= a_mask;                                                      \
 509         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 510                                                                              \
 511         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 512         ADM8211_CSR_READ(SYNRF);                                             \
 513         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 514         ADM8211_CSR_READ(SYNRF);                                             \
 515                                                                              \
 516         if (prewrite) {                                                      \
 517                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 518                 ADM8211_CSR_READ(SYNRF);                                     \
 519         }                                                                    \
 520                                                                              \
 521         for (i = 0; i <= bits; i++) {                                        \
 522                 if (bitbuf & (1 << (bits - i)))                              \
 523                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 524                 else                                                         \
 525                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 526                                                                              \
 527                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 528                 ADM8211_CSR_READ(SYNRF);                                     \
 529                                                                              \
 530                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 531                 ADM8211_CSR_READ(SYNRF);                                     \
 532                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 533                 ADM8211_CSR_READ(SYNRF);                                     \
 534         }                                                                    \
 535                                                                              \
 536         if (postwrite == 1) {                                                \
 537                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 538                 ADM8211_CSR_READ(SYNRF);                                     \
 539         }                                                                    \
 540         if (postwrite == 2) {                                                \
 541                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 542                 ADM8211_CSR_READ(SYNRF);                                     \
 543         }                                                                    \
 544                                                                              \
 545         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 546         ADM8211_CSR_READ(SYNRF);                                             \
 547 }
 548
 549 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 550 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 551 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 552 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 553
 554 #undef WRITE_SYN
 555
 556 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 557 {
 558         struct adm8211_priv *priv = dev->priv;
 559         unsigned int timeout;
 560         u32 reg;
 561
 562         timeout = 10;
 563         while (timeout > 0) {
 564                 reg = ADM8211_CSR_READ(BBPCTL);
 565                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 566                         break;
 567                 timeout--;
 568                 msleep(2);
 569         }
 570
 571         if (timeout == 0) {
 572                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 573                        " prewrite (reg=0x%08x)\n",
 574                        wiphy_name(dev->wiphy), addr, data, reg);
 575                 return -ETIMEDOUT;
 576         }
 577
 578         switch (priv->bbp_type) {
 579         case ADM8211_TYPE_INTERSIL:
 580                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 581                 break;
 582         case ADM8211_TYPE_RFMD:
 583                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 584                       (0x01 << 18);
 585                 break;
 586         case ADM8211_TYPE_ADMTEK:
 587                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 588                       (0x05 << 18);
 589                 break;
 590         }
 591         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 592
 593         ADM8211_CSR_WRITE(BBPCTL, reg);
 594
 595         timeout = 10;
 596         while (timeout > 0) {
 597                 reg = ADM8211_CSR_READ(BBPCTL);
 598                 if (!(reg & ADM8211_BBPCTL_WR))
 599                         break;
 600                 timeout--;
 601                 msleep(2);
 602         }
 603
 604         if (timeout == 0) {
 605                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 606                                   ~ADM8211_BBPCTL_WR);
 607                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 608                        " postwrite (reg=0x%08x)\n",
 609                        wiphy_name(dev->wiphy), addr, data, reg);
 610                 return -ETIMEDOUT;
 611         }
 612
 613         return 0;
 614 }
 615
 616 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 617 {
 618         static const u32 adm8211_rfmd2958_reg5[] =
 619                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 620                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 621         static const u32 adm8211_rfmd2958_reg6[] =
 622                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 623                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 624
 625         struct adm8211_priv *priv = dev->priv;
 626         u8 ant_power = priv->ant_power > 0x3F ?
 627                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 628         u8 tx_power = priv->tx_power > 0x3F ?
 629                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 630         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 631                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 632         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 633                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 634         u32 reg;
 635
 636         ADM8211_IDLE();
 637
 638         /* Program synthesizer to new channel */
 639         switch (priv->transceiver_type) {
 640         case ADM8211_RFMD2958:
 641         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 642                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 643                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 644
 645                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 646                         adm8211_rfmd2958_reg5[chan - 1]);
 647                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 648                         adm8211_rfmd2958_reg6[chan - 1]);
 649                 break;
 650
 651         case ADM8211_RFMD2948:
 652                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 653                                               SI4126_MAIN_XINDIV2);
 654                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 655                                               SI4126_POWERDOWN_PDIB |
 656                                               SI4126_POWERDOWN_PDRB);
 657                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 658                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 659                                               (chan == 14 ?
 660                                                2110 : (2033 + (chan * 5))));
 661                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 662                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 663                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 664                 break;
 665
 666         case ADM8211_MAX2820:
 667                 adm8211_rf_write_syn_max2820(dev, 0x3,
 668                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 669                 break;
 670
 671         case ADM8211_AL2210L:
 672                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 673                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 674                 break;
 675
 676         default:
 677                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 678                        wiphy_name(dev->wiphy), priv->transceiver_type);
 679                 break;
 680         }
 681
 682         /* write BBP regs */
 683         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 684
 685         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 686         /* TODO: remove if SMC 2635W doesn't need this */
 687         if (priv->transceiver_type == ADM8211_RFMD2948) {
 688                 reg = ADM8211_CSR_READ(GPIO);
 689                 reg &= 0xfffc0000;
 690                 reg |= ADM8211_CSR_GPIO_EN0;
 691                 if (chan != 14)
 692                         reg |= ADM8211_CSR_GPIO_O0;
 693                 ADM8211_CSR_WRITE(GPIO, reg);
 694         }
 695
 696         if (priv->transceiver_type == ADM8211_RFMD2958) {
 697                 /* set PCNT2 */
 698                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 699                 /* set PCNT1 P_DESIRED/MID_BIAS */
 700                 reg = le16_to_cpu(priv->eeprom->cr49);
 701                 reg >>= 13;
 702                 reg <<= 15;
 703                 reg |= ant_power << 9;
 704                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 705                 /* set TXRX TX_GAIN */
 706                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 707                         (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 708         } else {
 709                 reg = ADM8211_CSR_READ(PLCPHD);
 710                 reg &= 0xff00ffff;
 711                 reg |= tx_power << 18;
 712                 ADM8211_CSR_WRITE(PLCPHD, reg);
 713         }
 714
 715         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 716                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 717         ADM8211_CSR_READ(SYNRF);
 718         msleep(30);
 719
 720         /* RF3000 BBP */
 721         if (priv->transceiver_type != ADM8211_RFMD2958)
 722                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 723                                   tx_power<<2);
 724         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 725         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 726         adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 727                                      priv->eeprom->cr28 : 0);
 728         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 729
 730         ADM8211_CSR_WRITE(SYNRF, 0);
 731
 732         /* Nothing to do for ADMtek BBP */
 733         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 734                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 735                        wiphy_name(dev->wiphy), priv->bbp_type);
 736
 737         ADM8211_RESTORE();
 738
 739         /* update current channel for adhoc (and maybe AP mode) */
 740         reg = ADM8211_CSR_READ(CAP0);
 741         reg &= ~0xF;
 742         reg |= chan;
 743         ADM8211_CSR_WRITE(CAP0, reg);
 744
 745         return 0;
 746 }
 747
 748 static void adm8211_update_mode(struct ieee80211_hw *dev)
 749 {
 750         struct adm8211_priv *priv = dev->priv;
 751
 752         ADM8211_IDLE();
 753
 754         priv->soft_rx_crc = 0;
 755         switch (priv->mode) {
 756         case NL80211_IFTYPE_STATION:
 757                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 758                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 759                 break;
 760         case NL80211_IFTYPE_ADHOC:
 761                 priv->nar &= ~ADM8211_NAR_PR;
 762                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 763
 764                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 765                 if (priv->pdev->revision >= ADM8211_REV_BA)
 766                         priv->soft_rx_crc = 1;
 767                 break;
 768         case NL80211_IFTYPE_MONITOR:
 769                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 770                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 771                 break;
 772         }
 773
 774         ADM8211_RESTORE();
 775 }
 776
 777 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 778 {
 779         struct adm8211_priv *priv = dev->priv;
 780
 781         switch (priv->transceiver_type) {
 782         case ADM8211_RFMD2958:
 783         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 784                 /* comments taken from ADMtek vendor driver */
 785
 786                 /* Reset RF2958 after power on */
 787                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 788                 /* Initialize RF VCO Core Bias to maximum */
 789                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 790                 /* Initialize IF PLL */
 791                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 792                 /* Initialize IF PLL Coarse Tuning */
 793                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 794                 /* Initialize RF PLL */
 795                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 796                 /* Initialize RF PLL Coarse Tuning */
 797                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 798                 /* Initialize TX gain and filter BW (R9) */
 799                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 800                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 801                          0x10050 : 0x00050));
 802                 /* Initialize CAL register */
 803                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 804                 break;
 805
 806         case ADM8211_MAX2820:
 807                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 808                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 809                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 810                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 811                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 812                 break;
 813
 814         case ADM8211_AL2210L:
 815                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 816                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 817                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 818                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 819                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 820                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 821                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 822                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 823                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 824                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 825                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 826                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 827                 break;
 828
 829         case ADM8211_RFMD2948:
 830         default:
 831                 break;
 832         }
 833 }
 834
 835 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 836 {
 837         struct adm8211_priv *priv = dev->priv;
 838         u32 reg;
 839
 840         /* write addresses */
 841         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 842                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 843                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 844                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 845         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 846                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 847                 /* check specific BBP type */
 848                 switch (priv->specific_bbptype) {
 849                 case ADM8211_BBP_RFMD3000:
 850                 case ADM8211_BBP_RFMD3002:
 851                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 852                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 853                         break;
 854
 855                 case ADM8211_BBP_ADM8011:
 856                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 857                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 858
 859                         reg = ADM8211_CSR_READ(BBPCTL);
 860                         reg &= ~ADM8211_BBPCTL_TYPE;
 861                         reg |= 0x5 << 18;
 862                         ADM8211_CSR_WRITE(BBPCTL, reg);
 863                         break;
 864                 }
 865
 866                 switch (priv->pdev->revision) {
 867                 case ADM8211_REV_CA:
 868                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 869                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 870                             priv->transceiver_type == ADM8211_RFMD2948)
 871                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 872                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 873                                  priv->transceiver_type == ADM8211_AL2210L)
 874                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 875                         break;
 876
 877                 case ADM8211_REV_BA:
 878                         reg  = ADM8211_CSR_READ(MMIRD1);
 879                         reg &= 0x0000FFFF;
 880                         reg |= 0x7e100000;
 881                         ADM8211_CSR_WRITE(MMIRD1, reg);
 882                         break;
 883
 884                 case ADM8211_REV_AB:
 885                 case ADM8211_REV_AF:
 886                 default:
 887                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 888                         break;
 889                 }
 890
 891                 /* For RFMD */
 892                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 893         }
 894
 895         adm8211_hw_init_syn(dev);
 896
 897         /* Set RF Power control IF pin to PE1+PHYRST# */
 898         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 899                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 900         ADM8211_CSR_READ(SYNRF);
 901         msleep(20);
 902
 903         /* write BBP regs */
 904         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 905                 /* RF3000 BBP */
 906                 /* another set:
 907                  * 11: c8
 908                  * 14: 14
 909                  * 15: 50 (chan 1..13; chan 14: d0)
 910                  * 1c: 00
 911                  * 1d: 84
 912                  */
 913                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 914                 /* antenna selection: diversity */
 915                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 916                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 917                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 918                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 919
 920                 if (priv->eeprom->major_version < 2) {
 921                         adm8211_write_bbp(dev, 0x1c, 0x00);
 922                         adm8211_write_bbp(dev, 0x1d, 0x80);
 923                 } else {
 924                         if (priv->pdev->revision == ADM8211_REV_BA)
 925                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 926                         else
 927                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 928
 929                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 930                 }
 931         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 932                 /* reset baseband */
 933                 adm8211_write_bbp(dev, 0x00, 0xFF);
 934                 /* antenna selection: diversity */
 935                 adm8211_write_bbp(dev, 0x07, 0x0A);
 936
 937                 /* TODO: find documentation for this */
 938                 switch (priv->transceiver_type) {
 939                 case ADM8211_RFMD2958:
 940                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 941                         adm8211_write_bbp(dev, 0x00, 0x00);
 942                         adm8211_write_bbp(dev, 0x01, 0x00);
 943                         adm8211_write_bbp(dev, 0x02, 0x00);
 944                         adm8211_write_bbp(dev, 0x03, 0x00);
 945                         adm8211_write_bbp(dev, 0x06, 0x0f);
 946                         adm8211_write_bbp(dev, 0x09, 0x00);
 947                         adm8211_write_bbp(dev, 0x0a, 0x00);
 948                         adm8211_write_bbp(dev, 0x0b, 0x00);
 949                         adm8211_write_bbp(dev, 0x0c, 0x00);
 950                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 951                         adm8211_write_bbp(dev, 0x10, 0x8c);
 952                         adm8211_write_bbp(dev, 0x11, 0x43);
 953                         adm8211_write_bbp(dev, 0x18, 0x40);
 954                         adm8211_write_bbp(dev, 0x20, 0x23);
 955                         adm8211_write_bbp(dev, 0x21, 0x02);
 956                         adm8211_write_bbp(dev, 0x22, 0x28);
 957                         adm8211_write_bbp(dev, 0x23, 0x30);
 958                         adm8211_write_bbp(dev, 0x24, 0x2d);
 959                         adm8211_write_bbp(dev, 0x28, 0x35);
 960                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 961                         adm8211_write_bbp(dev, 0x2b, 0x81);
 962                         adm8211_write_bbp(dev, 0x2c, 0x44);
 963                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 964                         adm8211_write_bbp(dev, 0x29, 0x40);
 965                         adm8211_write_bbp(dev, 0x60, 0x08);
 966                         adm8211_write_bbp(dev, 0x64, 0x01);
 967                         break;
 968
 969                 case ADM8211_MAX2820:
 970                         adm8211_write_bbp(dev, 0x00, 0x00);
 971                         adm8211_write_bbp(dev, 0x01, 0x00);
 972                         adm8211_write_bbp(dev, 0x02, 0x00);
 973                         adm8211_write_bbp(dev, 0x03, 0x00);
 974                         adm8211_write_bbp(dev, 0x06, 0x0f);
 975                         adm8211_write_bbp(dev, 0x09, 0x05);
 976                         adm8211_write_bbp(dev, 0x0a, 0x02);
 977                         adm8211_write_bbp(dev, 0x0b, 0x00);
 978                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 979                         adm8211_write_bbp(dev, 0x0f, 0x55);
 980                         adm8211_write_bbp(dev, 0x10, 0x8d);
 981                         adm8211_write_bbp(dev, 0x11, 0x43);
 982                         adm8211_write_bbp(dev, 0x18, 0x4a);
 983                         adm8211_write_bbp(dev, 0x20, 0x20);
 984                         adm8211_write_bbp(dev, 0x21, 0x02);
 985                         adm8211_write_bbp(dev, 0x22, 0x23);
 986                         adm8211_write_bbp(dev, 0x23, 0x30);
 987                         adm8211_write_bbp(dev, 0x24, 0x2d);
 988                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 989                         adm8211_write_bbp(dev, 0x2b, 0x81);
 990                         adm8211_write_bbp(dev, 0x2c, 0x44);
 991                         adm8211_write_bbp(dev, 0x29, 0x4a);
 992                         adm8211_write_bbp(dev, 0x60, 0x2b);
 993                         adm8211_write_bbp(dev, 0x64, 0x01);
 994                         break;
 995
 996                 case ADM8211_AL2210L:
 997                         adm8211_write_bbp(dev, 0x00, 0x00);
 998                         adm8211_write_bbp(dev, 0x01, 0x00);
 999                         adm8211_write_bbp(dev, 0x02, 0x00);
1000                         adm8211_write_bbp(dev, 0x03, 0x00);
1001                         adm8211_write_bbp(dev, 0x06, 0x0f);
1002                         adm8211_write_bbp(dev, 0x07, 0x05);
1003                         adm8211_write_bbp(dev, 0x08, 0x03);
1004                         adm8211_write_bbp(dev, 0x09, 0x00);
1005                         adm8211_write_bbp(dev, 0x0a, 0x00);
1006                         adm8211_write_bbp(dev, 0x0b, 0x00);
1007                         adm8211_write_bbp(dev, 0x0c, 0x10);
1008                         adm8211_write_bbp(dev, 0x0f, 0x55);
1009                         adm8211_write_bbp(dev, 0x10, 0x8d);
1010                         adm8211_write_bbp(dev, 0x11, 0x43);
1011                         adm8211_write_bbp(dev, 0x18, 0x4a);
1012                         adm8211_write_bbp(dev, 0x20, 0x20);
1013                         adm8211_write_bbp(dev, 0x21, 0x02);
1014                         adm8211_write_bbp(dev, 0x22, 0x23);
1015                         adm8211_write_bbp(dev, 0x23, 0x30);
1016                         adm8211_write_bbp(dev, 0x24, 0x2d);
1017                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1018                         adm8211_write_bbp(dev, 0x2b, 0x81);
1019                         adm8211_write_bbp(dev, 0x2c, 0x44);
1020                         adm8211_write_bbp(dev, 0x29, 0xfa);
1021                         adm8211_write_bbp(dev, 0x60, 0x2d);
1022                         adm8211_write_bbp(dev, 0x64, 0x01);
1023                         break;
1024
1025                 case ADM8211_RFMD2948:
1026                         break;
1027
1028                 default:
1029                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1030                                wiphy_name(dev->wiphy), priv->transceiver_type);
1031                         break;
1032                 }
1033         } else
1034                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1035                        wiphy_name(dev->wiphy), priv->bbp_type);
1036
1037         ADM8211_CSR_WRITE(SYNRF, 0);
1038
1039         /* Set RF CAL control source to MAC control */
1040         reg = ADM8211_CSR_READ(SYNCTL);
1041         reg |= ADM8211_SYNCTL_SELCAL;
1042         ADM8211_CSR_WRITE(SYNCTL, reg);
1043
1044         return 0;
1045 }
1046
1047 /* configures hw beacons/probe responses */
1048 static int adm8211_set_rate(struct ieee80211_hw *dev)
1049 {
1050         struct adm8211_priv *priv = dev->priv;
1051         u32 reg;
1052         int i = 0;
1053         u8 rate_buf[12] = {0};
1054
1055         /* write supported rates */
1056         if (priv->pdev->revision != ADM8211_REV_BA) {
1057                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1058                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1059                         rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1060         } else {
1061                 /* workaround for rev BA specific bug */
1062                 rate_buf[0] = 0x04;
1063                 rate_buf[1] = 0x82;
1064                 rate_buf[2] = 0x04;
1065                 rate_buf[3] = 0x0b;
1066                 rate_buf[4] = 0x16;
1067         }
1068
1069         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1070                                  ARRAY_SIZE(adm8211_rates) + 1);
1071
1072         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1073         reg |= 1 << 15; /* short preamble */
1074         reg |= 110 << 24;
1075         ADM8211_CSR_WRITE(PLCPHD, reg);
1076
1077         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1078          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1079          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1080         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1081
1082         return 0;
1083 }
1084
1085 static void adm8211_hw_init(struct ieee80211_hw *dev)
1086 {
1087         struct adm8211_priv *priv = dev->priv;
1088         u32 reg;
1089         u8 cline;
1090
1091         reg = ADM8211_CSR_READ(PAR);
1092         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1093         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1094
1095         if (!pci_set_mwi(priv->pdev)) {
1096                 reg |= 0x1 << 24;
1097                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1098
1099                 switch (cline) {
1100                 case  0x8: reg |= (0x1 << 14);
1101                            break;
1102                 case 0x16: reg |= (0x2 << 14);
1103                            break;
1104                 case 0x32: reg |= (0x3 << 14);
1105                            break;
1106                   default: reg |= (0x0 << 14);
1107                            break;
1108                 }
1109         }
1110
1111         ADM8211_CSR_WRITE(PAR, reg);
1112
1113         reg = ADM8211_CSR_READ(CSR_TEST1);
1114         reg &= ~(0xF << 28);
1115         reg |= (1 << 28) | (1 << 31);
1116         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1117
1118         /* lose link after 4 lost beacons */
1119         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1120         ADM8211_CSR_WRITE(WCSR, reg);
1121
1122         /* Disable APM, enable receive FIFO threshold, and set drain receive
1123          * threshold to store-and-forward */
1124         reg = ADM8211_CSR_READ(CMDR);
1125         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1126         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1127         ADM8211_CSR_WRITE(CMDR, reg);
1128
1129         adm8211_set_rate(dev);
1130
1131         /* 4-bit values:
1132          * PWR1UP   = 8 * 2 ms
1133          * PWR0PAPE = 8 us or 5 us
1134          * PWR1PAPE = 1 us or 3 us
1135          * PWR0TRSW = 5 us
1136          * PWR1TRSW = 12 us
1137          * PWR0PE2  = 13 us
1138          * PWR1PE2  = 1 us
1139          * PWR0TXPE = 8 or 6 */
1140         if (priv->pdev->revision < ADM8211_REV_CA)
1141                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1142         else
1143                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1144
1145         /* Enable store and forward for transmit */
1146         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1147         ADM8211_CSR_WRITE(NAR, priv->nar);
1148
1149         /* Reset RF */
1150         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1151         ADM8211_CSR_READ(SYNRF);
1152         msleep(10);
1153         ADM8211_CSR_WRITE(SYNRF, 0);
1154         ADM8211_CSR_READ(SYNRF);
1155         msleep(5);
1156
1157         /* Set CFP Max Duration to 0x10 TU */
1158         reg = ADM8211_CSR_READ(CFPP);
1159         reg &= ~(0xffff << 8);
1160         reg |= 0x0010 << 8;
1161         ADM8211_CSR_WRITE(CFPP, reg);
1162
1163         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1164          * TUCNT = 0x3ff - Tu counter 1024 us  */
1165         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1166
1167         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1168          * DIFS=50 us, EIFS=100 us */
1169         if (priv->pdev->revision < ADM8211_REV_CA)
1170                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1171                                         (50 << 9)  | 100);
1172         else
1173                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1174                                         (50 << 9)  | 100);
1175
1176         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1177          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1178         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1179
1180         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1181         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1182
1183         /* Initialize BBP (and SYN) */
1184         adm8211_hw_init_bbp(dev);
1185
1186         /* make sure interrupts are off */
1187         ADM8211_CSR_WRITE(IER, 0);
1188
1189         /* ACK interrupts */
1190         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1191
1192         /* Setup WEP (turns it off for now) */
1193         reg = ADM8211_CSR_READ(MACTEST);
1194         reg &= ~(7 << 20);
1195         ADM8211_CSR_WRITE(MACTEST, reg);
1196
1197         reg = ADM8211_CSR_READ(WEPCTL);
1198         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1199         reg |= ADM8211_WEPCTL_WEPRXBYP;
1200         ADM8211_CSR_WRITE(WEPCTL, reg);
1201
1202         /* Clear the missed-packet counter. */
1203         ADM8211_CSR_READ(LPC);
1204 }
1205
1206 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1207 {
1208         struct adm8211_priv *priv = dev->priv;
1209         u32 reg, tmp;
1210         int timeout = 100;
1211
1212         /* Power-on issue */
1213         /* TODO: check if this is necessary */
1214         ADM8211_CSR_WRITE(FRCTL, 0);
1215
1216         /* Reset the chip */
1217         tmp = ADM8211_CSR_READ(PAR);
1218         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1219
1220         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1221                 msleep(50);
1222
1223         if (timeout <= 0)
1224                 return -ETIMEDOUT;
1225
1226         ADM8211_CSR_WRITE(PAR, tmp);
1227
1228         if (priv->pdev->revision == ADM8211_REV_BA &&
1229             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1230              priv->transceiver_type == ADM8211_RFMD2958)) {
1231                 reg = ADM8211_CSR_READ(CSR_TEST1);
1232                 reg |= (1 << 4) | (1 << 5);
1233                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1234         } else if (priv->pdev->revision == ADM8211_REV_CA) {
1235                 reg = ADM8211_CSR_READ(CSR_TEST1);
1236                 reg &= ~((1 << 4) | (1 << 5));
1237                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1238         }
1239
1240         ADM8211_CSR_WRITE(FRCTL, 0);
1241
1242         reg = ADM8211_CSR_READ(CSR_TEST0);
1243         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1244         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1245
1246         adm8211_clear_sram(dev);
1247
1248         return 0;
1249 }
1250
1251 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1252 {
1253         struct adm8211_priv *priv = dev->priv;
1254         u32 tsftl;
1255         u64 tsft;
1256
1257         tsftl = ADM8211_CSR_READ(TSFTL);
1258         tsft = ADM8211_CSR_READ(TSFTH);
1259         tsft <<= 32;
1260         tsft |= tsftl;
1261
1262         return tsft;
1263 }
1264
1265 static void adm8211_set_interval(struct ieee80211_hw *dev,
1266                                  unsigned short bi, unsigned short li)
1267 {
1268         struct adm8211_priv *priv = dev->priv;
1269         u32 reg;
1270
1271         /* BP (beacon interval) = data->beacon_interval
1272          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1273         reg = (bi << 16) | li;
1274         ADM8211_CSR_WRITE(BPLI, reg);
1275 }
1276
1277 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1278 {
1279         struct adm8211_priv *priv = dev->priv;
1280         u32 reg;
1281
1282         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1283         reg = ADM8211_CSR_READ(ABDA1);
1284         reg &= 0x0000ffff;
1285         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1286         ADM8211_CSR_WRITE(ABDA1, reg);
1287 }
1288
1289 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1290 {
1291         struct adm8211_priv *priv = dev->priv;
1292         struct ieee80211_conf *conf = &dev->conf;
1293         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1294
1295         if (channel != priv->channel) {
1296                 priv->channel = channel;
1297                 adm8211_rf_set_channel(dev, priv->channel);
1298         }
1299
1300         return 0;
1301 }
1302
1303 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1304                                      struct ieee80211_vif *vif,
1305                                      struct ieee80211_bss_conf *conf,
1306                                      u32 changes)
1307 {
1308         struct adm8211_priv *priv = dev->priv;
1309
1310         if (!(changes & BSS_CHANGED_BSSID))
1311                 return;
1312
1313         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1314                 adm8211_set_bssid(dev, conf->bssid);
1315                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1316         }
1317 }
1318
1319 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1320                                      int mc_count, struct dev_addr_list *mclist)
1321 {
1322         unsigned int bit_nr, i;
1323         u32 mc_filter[2];
1324
1325         mc_filter[1] = mc_filter[0] = 0;
1326
1327         for (i = 0; i < mc_count; i++) {
1328                 if (!mclist)
1329                         break;
1330                 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1331
1332                 bit_nr &= 0x3F;
1333                 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1334                 mclist = mclist->next;
1335         }
1336
1337         return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1338 }
1339
1340 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1341                                      unsigned int changed_flags,
1342                                      unsigned int *total_flags,
1343                                      u64 multicast)
1344 {
1345         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1346         struct adm8211_priv *priv = dev->priv;
1347         unsigned int new_flags;
1348         u32 mc_filter[2];
1349
1350         mc_filter[0] = multicast;
1351         mc_filter[1] = multicast >> 32;
1352
1353         new_flags = 0;
1354
1355         if (*total_flags & FIF_PROMISC_IN_BSS) {
1356                 new_flags |= FIF_PROMISC_IN_BSS;
1357                 priv->nar |= ADM8211_NAR_PR;
1358                 priv->nar &= ~ADM8211_NAR_MM;
1359                 mc_filter[1] = mc_filter[0] = ~0;
1360         } else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1361                 new_flags |= FIF_ALLMULTI;
1362                 priv->nar &= ~ADM8211_NAR_PR;
1363                 priv->nar |= ADM8211_NAR_MM;
1364                 mc_filter[1] = mc_filter[0] = ~0;
1365         } else {
1366                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1367         }
1368
1369         ADM8211_IDLE_RX();
1370
1371         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1372         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1373         ADM8211_CSR_READ(NAR);
1374
1375         if (priv->nar & ADM8211_NAR_PR)
1376                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1377         else
1378                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1379
1380         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1381                 adm8211_set_bssid(dev, bcast);
1382         else
1383                 adm8211_set_bssid(dev, priv->bssid);
1384
1385         ADM8211_RESTORE();
1386
1387         *total_flags = new_flags;
1388 }
1389
1390 static int adm8211_add_interface(struct ieee80211_hw *dev,
1391                                  struct ieee80211_vif *vif)
1392 {
1393         struct adm8211_priv *priv = dev->priv;
1394         if (priv->mode != NL80211_IFTYPE_MONITOR)
1395                 return -EOPNOTSUPP;
1396
1397         switch (vif->type) {
1398         case NL80211_IFTYPE_STATION:
1399                 priv->mode = vif->type;
1400                 break;
1401         default:
1402                 return -EOPNOTSUPP;
1403         }
1404
1405         ADM8211_IDLE();
1406
1407         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1408         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1409
1410         adm8211_update_mode(dev);
1411
1412         ADM8211_RESTORE();
1413
1414         return 0;
1415 }
1416
1417 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1418                                      struct ieee80211_vif *vif)
1419 {
1420         struct adm8211_priv *priv = dev->priv;
1421         priv->mode = NL80211_IFTYPE_MONITOR;
1422 }
1423
1424 static int adm8211_init_rings(struct ieee80211_hw *dev)
1425 {
1426         struct adm8211_priv *priv = dev->priv;
1427         struct adm8211_desc *desc = NULL;
1428         struct adm8211_rx_ring_info *rx_info;
1429         struct adm8211_tx_ring_info *tx_info;
1430         unsigned int i;
1431
1432         for (i = 0; i < priv->rx_ring_size; i++) {
1433                 desc = &priv->rx_ring[i];
1434                 desc->status = 0;
1435                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1436                 priv->rx_buffers[i].skb = NULL;
1437         }
1438         /* Mark the end of RX ring; hw returns to base address after this
1439          * descriptor */
1440         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1441
1442         for (i = 0; i < priv->rx_ring_size; i++) {
1443                 desc = &priv->rx_ring[i];
1444                 rx_info = &priv->rx_buffers[i];
1445
1446                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1447                 if (rx_info->skb == NULL)
1448                         break;
1449                 rx_info->mapping = pci_map_single(priv->pdev,
1450                                                   skb_tail_pointer(rx_info->skb),
1451                                                   RX_PKT_SIZE,
1452                                                   PCI_DMA_FROMDEVICE);
1453                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1454                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1455         }
1456
1457         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1458         for (i = 0; i < priv->tx_ring_size; i++) {
1459                 desc = &priv->tx_ring[i];
1460                 tx_info = &priv->tx_buffers[i];
1461
1462                 tx_info->skb = NULL;
1463                 tx_info->mapping = 0;
1464                 desc->status = 0;
1465         }
1466         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1467
1468         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1469         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1470         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1471
1472         return 0;
1473 }
1474
1475 static void adm8211_free_rings(struct ieee80211_hw *dev)
1476 {
1477         struct adm8211_priv *priv = dev->priv;
1478         unsigned int i;
1479
1480         for (i = 0; i < priv->rx_ring_size; i++) {
1481                 if (!priv->rx_buffers[i].skb)
1482                         continue;
1483
1484                 pci_unmap_single(
1485                         priv->pdev,
1486                         priv->rx_buffers[i].mapping,
1487                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1488
1489                 dev_kfree_skb(priv->rx_buffers[i].skb);
1490         }
1491
1492         for (i = 0; i < priv->tx_ring_size; i++) {
1493                 if (!priv->tx_buffers[i].skb)
1494                         continue;
1495
1496                 pci_unmap_single(priv->pdev,
1497                                  priv->tx_buffers[i].mapping,
1498                                  priv->tx_buffers[i].skb->len,
1499                                  PCI_DMA_TODEVICE);
1500
1501                 dev_kfree_skb(priv->tx_buffers[i].skb);
1502         }
1503 }
1504
1505 static int adm8211_start(struct ieee80211_hw *dev)
1506 {
1507         struct adm8211_priv *priv = dev->priv;
1508         int retval;
1509
1510         /* Power up MAC and RF chips */
1511         retval = adm8211_hw_reset(dev);
1512         if (retval) {
1513                 printk(KERN_ERR "%s: hardware reset failed\n",
1514                        wiphy_name(dev->wiphy));
1515                 goto fail;
1516         }
1517
1518         retval = adm8211_init_rings(dev);
1519         if (retval) {
1520                 printk(KERN_ERR "%s: failed to initialize rings\n",
1521                        wiphy_name(dev->wiphy));
1522                 goto fail;
1523         }
1524
1525         /* Init hardware */
1526         adm8211_hw_init(dev);
1527         adm8211_rf_set_channel(dev, priv->channel);
1528
1529         retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1530                              IRQF_SHARED, "adm8211", dev);
1531         if (retval) {
1532                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1533                        wiphy_name(dev->wiphy));
1534                 goto fail;
1535         }
1536
1537         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1538                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1539                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1540         priv->mode = NL80211_IFTYPE_MONITOR;
1541         adm8211_update_mode(dev);
1542         ADM8211_CSR_WRITE(RDR, 0);
1543
1544         adm8211_set_interval(dev, 100, 10);
1545         return 0;
1546
1547 fail:
1548         return retval;
1549 }
1550
1551 static void adm8211_stop(struct ieee80211_hw *dev)
1552 {
1553         struct adm8211_priv *priv = dev->priv;
1554
1555         priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1556         priv->nar = 0;
1557         ADM8211_CSR_WRITE(NAR, 0);
1558         ADM8211_CSR_WRITE(IER, 0);
1559         ADM8211_CSR_READ(NAR);
1560
1561         free_irq(priv->pdev->irq, dev);
1562
1563         adm8211_free_rings(dev);
1564 }
1565
1566 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1567                                    int plcp_signal, int short_preamble)
1568 {
1569         /* Alternative calculation from NetBSD: */
1570
1571 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1572 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1573 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1574 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1575 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1576 #define IEEE80211_DUR_DS_SLOW_ACK       112
1577 #define IEEE80211_DUR_DS_FAST_ACK       56
1578 #define IEEE80211_DUR_DS_SLOW_CTS       112
1579 #define IEEE80211_DUR_DS_FAST_CTS       56
1580 #define IEEE80211_DUR_DS_SLOT           20
1581 #define IEEE80211_DUR_DS_SIFS           10
1582
1583         int remainder;
1584
1585         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1586                 / plcp_signal;
1587
1588         if (plcp_signal <= PLCP_SIGNAL_2M)
1589                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1590                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1591                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1592                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1593                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1594         else
1595                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1596                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1597                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1598                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1599                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1600
1601         /* lengthen duration if long preamble */
1602         if (!short_preamble)
1603                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1604                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1605                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1606                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1607
1608
1609         *plcp = (80 * len) / plcp_signal;
1610         remainder = (80 * len) % plcp_signal;
1611         if (plcp_signal == PLCP_SIGNAL_11M &&
1612             remainder <= 30 && remainder > 0)
1613                 *plcp = (*plcp | 0x8000) + 1;
1614         else if (remainder)
1615                 (*plcp)++;
1616 }
1617
1618 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1619 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1620                            u16 plcp_signal,
1621                            size_t hdrlen)
1622 {
1623         struct adm8211_priv *priv = dev->priv;
1624         unsigned long flags;
1625         dma_addr_t mapping;
1626         unsigned int entry;
1627         u32 flag;
1628
1629         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1630                                  PCI_DMA_TODEVICE);
1631
1632         spin_lock_irqsave(&priv->lock, flags);
1633
1634         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1635                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1636         else
1637                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1638
1639         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1640                 ieee80211_stop_queue(dev, 0);
1641
1642         entry = priv->cur_tx % priv->tx_ring_size;
1643
1644         priv->tx_buffers[entry].skb = skb;
1645         priv->tx_buffers[entry].mapping = mapping;
1646         priv->tx_buffers[entry].hdrlen = hdrlen;
1647         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1648
1649         if (entry == priv->tx_ring_size - 1)
1650                 flag |= TDES1_CONTROL_TER;
1651         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1652
1653         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1654         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1655         priv->tx_ring[entry].status = cpu_to_le32(flag);
1656
1657         priv->cur_tx++;
1658
1659         spin_unlock_irqrestore(&priv->lock, flags);
1660
1661         /* Trigger transmit poll */
1662         ADM8211_CSR_WRITE(TDR, 0);
1663 }
1664
1665 /* Put adm8211_tx_hdr on skb and transmit */
1666 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
1667 {
1668         struct adm8211_tx_hdr *txhdr;
1669         size_t payload_len, hdrlen;
1670         int plcp, dur, len, plcp_signal, short_preamble;
1671         struct ieee80211_hdr *hdr;
1672         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1673         struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1674         u8 rc_flags;
1675
1676         rc_flags = info->control.rates[0].flags;
1677         short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1678         plcp_signal = txrate->bitrate;
1679
1680         hdr = (struct ieee80211_hdr *)skb->data;
1681         hdrlen = ieee80211_hdrlen(hdr->frame_control);
1682         memcpy(skb->cb, skb->data, hdrlen);
1683         hdr = (struct ieee80211_hdr *)skb->cb;
1684         skb_pull(skb, hdrlen);
1685         payload_len = skb->len;
1686
1687         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1688         memset(txhdr, 0, sizeof(*txhdr));
1689         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1690         txhdr->signal = plcp_signal;
1691         txhdr->frame_body_size = cpu_to_le16(payload_len);
1692         txhdr->frame_control = hdr->frame_control;
1693
1694         len = hdrlen + payload_len + FCS_LEN;
1695
1696         txhdr->frag = cpu_to_le16(0x0FFF);
1697         adm8211_calc_durations(&dur, &plcp, payload_len,
1698                                len, plcp_signal, short_preamble);
1699         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1700         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1701         txhdr->dur_frag_head = cpu_to_le16(dur);
1702         txhdr->dur_frag_tail = cpu_to_le16(dur);
1703
1704         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1705
1706         if (short_preamble)
1707                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1708
1709         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1710                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1711
1712         txhdr->retry_limit = info->control.rates[0].count;
1713
1714         adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1715
1716         return NETDEV_TX_OK;
1717 }
1718
1719 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1720 {
1721         struct adm8211_priv *priv = dev->priv;
1722         unsigned int ring_size;
1723
1724         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1725                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1726         if (!priv->rx_buffers)
1727                 return -ENOMEM;
1728
1729         priv->tx_buffers = (void *)priv->rx_buffers +
1730                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1731
1732         /* Allocate TX/RX descriptors */
1733         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1734                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1735         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1736                                              &priv->rx_ring_dma);
1737
1738         if (!priv->rx_ring) {
1739                 kfree(priv->rx_buffers);
1740                 priv->rx_buffers = NULL;
1741                 priv->tx_buffers = NULL;
1742                 return -ENOMEM;
1743         }
1744
1745         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1746                                                 priv->rx_ring_size);
1747         priv->tx_ring_dma = priv->rx_ring_dma +
1748                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1749
1750         return 0;
1751 }
1752
1753 static const struct ieee80211_ops adm8211_ops = {
1754         .tx                     = adm8211_tx,
1755         .start                  = adm8211_start,
1756         .stop                   = adm8211_stop,
1757         .add_interface          = adm8211_add_interface,
1758         .remove_interface       = adm8211_remove_interface,
1759         .config                 = adm8211_config,
1760         .bss_info_changed       = adm8211_bss_info_changed,
1761         .prepare_multicast      = adm8211_prepare_multicast,
1762         .configure_filter       = adm8211_configure_filter,
1763         .get_stats              = adm8211_get_stats,
1764         .get_tsf                = adm8211_get_tsft
1765 };
1766
1767 static int __devinit adm8211_probe(struct pci_dev *pdev,
1768                                    const struct pci_device_id *id)
1769 {
1770         struct ieee80211_hw *dev;
1771         struct adm8211_priv *priv;
1772         unsigned long mem_addr, mem_len;
1773         unsigned int io_addr, io_len;
1774         int err;
1775         u32 reg;
1776         u8 perm_addr[ETH_ALEN];
1777
1778         err = pci_enable_device(pdev);
1779         if (err) {
1780                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1781                        pci_name(pdev));
1782                 return err;
1783         }
1784
1785         io_addr = pci_resource_start(pdev, 0);
1786         io_len = pci_resource_len(pdev, 0);
1787         mem_addr = pci_resource_start(pdev, 1);
1788         mem_len = pci_resource_len(pdev, 1);
1789         if (io_len < 256 || mem_len < 1024) {
1790                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1791                        pci_name(pdev));
1792                 goto err_disable_pdev;
1793         }
1794
1795
1796         /* check signature */
1797         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1798         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1799                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1800                        pci_name(pdev), reg);
1801                 goto err_disable_pdev;
1802         }
1803
1804         err = pci_request_regions(pdev, "adm8211");
1805         if (err) {
1806                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1807                        pci_name(pdev));
1808                 return err; /* someone else grabbed it? don't disable it */
1809         }
1810
1811         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1812             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1813                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1814                        pci_name(pdev));
1815                 goto err_free_reg;
1816         }
1817
1818         pci_set_master(pdev);
1819
1820         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1821         if (!dev) {
1822                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1823                        pci_name(pdev));
1824                 err = -ENOMEM;
1825                 goto err_free_reg;
1826         }
1827         priv = dev->priv;
1828         priv->pdev = pdev;
1829
1830         spin_lock_init(&priv->lock);
1831
1832         SET_IEEE80211_DEV(dev, &pdev->dev);
1833
1834         pci_set_drvdata(pdev, dev);
1835
1836         priv->map = pci_iomap(pdev, 1, mem_len);
1837         if (!priv->map)
1838                 priv->map = pci_iomap(pdev, 0, io_len);
1839
1840         if (!priv->map) {
1841                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1842                        pci_name(pdev));
1843                 goto err_free_dev;
1844         }
1845
1846         priv->rx_ring_size = rx_ring_size;
1847         priv->tx_ring_size = tx_ring_size;
1848
1849         if (adm8211_alloc_rings(dev)) {
1850                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1851                        pci_name(pdev));
1852                 goto err_iounmap;
1853         }
1854
1855         *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1856         *(__le16 *)&perm_addr[4] =
1857                 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1858
1859         if (!is_valid_ether_addr(perm_addr)) {
1860                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1861                        pci_name(pdev));
1862                 random_ether_addr(perm_addr);
1863         }
1864         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1865
1866         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1867         /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1868         dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
1869         dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1870
1871         dev->channel_change_time = 1000;
1872         dev->max_signal = 100;    /* FIXME: find better value */
1873
1874         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1875
1876         priv->retry_limit = 3;
1877         priv->ant_power = 0x40;
1878         priv->tx_power = 0x40;
1879         priv->lpf_cutoff = 0xFF;
1880         priv->lnags_threshold = 0xFF;
1881         priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1882
1883         /* Power-on issue. EEPROM won't read correctly without */
1884         if (pdev->revision >= ADM8211_REV_BA) {
1885                 ADM8211_CSR_WRITE(FRCTL, 0);
1886                 ADM8211_CSR_READ(FRCTL);
1887                 ADM8211_CSR_WRITE(FRCTL, 1);
1888                 ADM8211_CSR_READ(FRCTL);
1889                 msleep(100);
1890         }
1891
1892         err = adm8211_read_eeprom(dev);
1893         if (err) {
1894                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1895                        pci_name(pdev));
1896                 goto err_free_desc;
1897         }
1898
1899         priv->channel = 1;
1900
1901         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1902
1903         err = ieee80211_register_hw(dev);
1904         if (err) {
1905                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1906                        pci_name(pdev));
1907                 goto err_free_desc;
1908         }
1909
1910         printk(KERN_INFO "%s: hwaddr %pM, Rev 0x%02x\n",
1911                wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1912                pdev->revision);
1913
1914         return 0;
1915
1916  err_free_desc:
1917         pci_free_consistent(pdev,
1918                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1919                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1920                             priv->rx_ring, priv->rx_ring_dma);
1921         kfree(priv->rx_buffers);
1922
1923  err_iounmap:
1924         pci_iounmap(pdev, priv->map);
1925
1926  err_free_dev:
1927         pci_set_drvdata(pdev, NULL);
1928         ieee80211_free_hw(dev);
1929
1930  err_free_reg:
1931         pci_release_regions(pdev);
1932
1933  err_disable_pdev:
1934         pci_disable_device(pdev);
1935         return err;
1936 }
1937
1938
1939 static void __devexit adm8211_remove(struct pci_dev *pdev)
1940 {
1941         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1942         struct adm8211_priv *priv;
1943
1944         if (!dev)
1945                 return;
1946
1947         ieee80211_unregister_hw(dev);
1948
1949         priv = dev->priv;
1950
1951         pci_free_consistent(pdev,
1952                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1953                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1954                             priv->rx_ring, priv->rx_ring_dma);
1955
1956         kfree(priv->rx_buffers);
1957         kfree(priv->eeprom);
1958         pci_iounmap(pdev, priv->map);
1959         pci_release_regions(pdev);
1960         pci_disable_device(pdev);
1961         ieee80211_free_hw(dev);
1962 }
1963
1964
1965 #ifdef CONFIG_PM
1966 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1967 {
1968         pci_save_state(pdev);
1969         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1970         return 0;
1971 }
1972
1973 static int adm8211_resume(struct pci_dev *pdev)
1974 {
1975         pci_set_power_state(pdev, PCI_D0);
1976         pci_restore_state(pdev);
1977         return 0;
1978 }
1979 #endif /* CONFIG_PM */
1980
1981
1982 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1983
1984 /* TODO: implement enable_wake */
1985 static struct pci_driver adm8211_driver = {
1986         .name           = "adm8211",
1987         .id_table       = adm8211_pci_id_table,
1988         .probe          = adm8211_probe,
1989         .remove         = __devexit_p(adm8211_remove),
1990 #ifdef CONFIG_PM
1991         .suspend        = adm8211_suspend,
1992         .resume         = adm8211_resume,
1993 #endif /* CONFIG_PM */
1994 };
1995
1996
1997
1998 static int __init adm8211_init(void)
1999 {
2000         return pci_register_driver(&adm8211_driver);
2001 }
2002
2003
2004 static void __exit adm8211_exit(void)
2005 {
2006         pci_unregister_driver(&adm8211_driver);
2007 }
2008
2009
2010 module_init(adm8211_init);
2011 module_exit(adm8211_exit);