drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
  43         /* ADMtek ADM8211 */
  44         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  45         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  46         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  47         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  48         { 0 }
  49 };
  50
  51 static struct ieee80211_rate adm8211_rates[] = {
  52         { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  53         { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  54         { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  55         { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  56         { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  57 };
  58
  59 static const struct ieee80211_channel adm8211_channels[] = {
  60         { .center_freq = 2412},
  61         { .center_freq = 2417},
  62         { .center_freq = 2422},
  63         { .center_freq = 2427},
  64         { .center_freq = 2432},
  65         { .center_freq = 2437},
  66         { .center_freq = 2442},
  67         { .center_freq = 2447},
  68         { .center_freq = 2452},
  69         { .center_freq = 2457},
  70         { .center_freq = 2462},
  71         { .center_freq = 2467},
  72         { .center_freq = 2472},
  73         { .center_freq = 2484},
  74 };
  75
  76
  77 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  78 {
  79         struct adm8211_priv *priv = eeprom->data;
  80         u32 reg = ADM8211_CSR_READ(SPR);
  81
  82         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  83         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  84         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  85         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  86 }
  87
  88 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  89 {
  90         struct adm8211_priv *priv = eeprom->data;
  91         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  92
  93         if (eeprom->reg_data_in)
  94                 reg |= ADM8211_SPR_SDI;
  95         if (eeprom->reg_data_out)
  96                 reg |= ADM8211_SPR_SDO;
  97         if (eeprom->reg_data_clock)
  98                 reg |= ADM8211_SPR_SCLK;
  99         if (eeprom->reg_chip_select)
 100                 reg |= ADM8211_SPR_SCS;
 101
 102         ADM8211_CSR_WRITE(SPR, reg);
 103         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
 104 }
 105
 106 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
 107 {
 108         struct adm8211_priv *priv = dev->priv;
 109         unsigned int words, i;
 110         struct ieee80211_chan_range chan_range;
 111         u16 cr49;
 112         struct eeprom_93cx6 eeprom = {
 113                 .data           = priv,
 114                 .register_read  = adm8211_eeprom_register_read,
 115                 .register_write = adm8211_eeprom_register_write
 116         };
 117
 118         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
 119                 /* 256 * 16-bit = 512 bytes */
 120                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 121                 words = 256;
 122         } else {
 123                 /* 64 * 16-bit = 128 bytes */
 124                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 125                 words = 64;
 126         }
 127
 128         priv->eeprom_len = words * 2;
 129         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 130         if (!priv->eeprom)
 131                 return -ENOMEM;
 132
 133         eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
 134
 135         cr49 = le16_to_cpu(priv->eeprom->cr49);
 136         priv->rf_type = (cr49 >> 3) & 0x7;
 137         switch (priv->rf_type) {
 138         case ADM8211_TYPE_INTERSIL:
 139         case ADM8211_TYPE_RFMD:
 140         case ADM8211_TYPE_MARVEL:
 141         case ADM8211_TYPE_AIROHA:
 142         case ADM8211_TYPE_ADMTEK:
 143                 break;
 144
 145         default:
 146                 if (priv->pdev->revision < ADM8211_REV_CA)
 147                         priv->rf_type = ADM8211_TYPE_RFMD;
 148                 else
 149                         priv->rf_type = ADM8211_TYPE_AIROHA;
 150
 151                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 152                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 153         }
 154
 155         priv->bbp_type = cr49 & 0x7;
 156         switch (priv->bbp_type) {
 157         case ADM8211_TYPE_INTERSIL:
 158         case ADM8211_TYPE_RFMD:
 159         case ADM8211_TYPE_MARVEL:
 160         case ADM8211_TYPE_AIROHA:
 161         case ADM8211_TYPE_ADMTEK:
 162                 break;
 163         default:
 164                 if (priv->pdev->revision < ADM8211_REV_CA)
 165                         priv->bbp_type = ADM8211_TYPE_RFMD;
 166                 else
 167                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 168
 169                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 170                        pci_name(priv->pdev), cr49 >> 3);
 171         }
 172
 173         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 174                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 175                        pci_name(priv->pdev), priv->eeprom->country_code);
 176
 177                 chan_range = cranges[2];
 178         } else
 179                 chan_range = cranges[priv->eeprom->country_code];
 180
 181         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 182                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 183
 184         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
 185
 186         memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
 187         priv->band.channels = priv->channels;
 188         priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
 189         priv->band.bitrates = adm8211_rates;
 190         priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
 191
 192         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 193                 if (i < chan_range.min || i > chan_range.max)
 194                         priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
 195
 196         switch (priv->eeprom->specific_bbptype) {
 197         case ADM8211_BBP_RFMD3000:
 198         case ADM8211_BBP_RFMD3002:
 199         case ADM8211_BBP_ADM8011:
 200                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 201                 break;
 202
 203         default:
 204                 if (priv->pdev->revision < ADM8211_REV_CA)
 205                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 206                 else
 207                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 208
 209                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 210                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 211         }
 212
 213         switch (priv->eeprom->specific_rftype) {
 214         case ADM8211_RFMD2948:
 215         case ADM8211_RFMD2958:
 216         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 217         case ADM8211_MAX2820:
 218         case ADM8211_AL2210L:
 219                 priv->transceiver_type = priv->eeprom->specific_rftype;
 220                 break;
 221
 222         default:
 223                 if (priv->pdev->revision == ADM8211_REV_BA)
 224                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 225                 else if (priv->pdev->revision == ADM8211_REV_CA)
 226                         priv->transceiver_type = ADM8211_AL2210L;
 227                 else if (priv->pdev->revision == ADM8211_REV_AB)
 228                         priv->transceiver_type = ADM8211_RFMD2948;
 229
 230                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 231                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 232
 233                 break;
 234         }
 235
 236         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 237                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 238                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 239
 240         return 0;
 241 }
 242
 243 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 244                                       u32 addr, u32 data)
 245 {
 246         struct adm8211_priv *priv = dev->priv;
 247
 248         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 249                           (priv->pdev->revision < ADM8211_REV_BA ?
 250                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 251         ADM8211_CSR_READ(WEPCTL);
 252         msleep(1);
 253
 254         ADM8211_CSR_WRITE(WESK, data);
 255         ADM8211_CSR_READ(WESK);
 256         msleep(1);
 257 }
 258
 259 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 260                                      unsigned int addr, u8 *buf,
 261                                      unsigned int len)
 262 {
 263         struct adm8211_priv *priv = dev->priv;
 264         u32 reg = ADM8211_CSR_READ(WEPCTL);
 265         unsigned int i;
 266
 267         if (priv->pdev->revision < ADM8211_REV_BA) {
 268                 for (i = 0; i < len; i += 2) {
 269                         u16 val = buf[i] | (buf[i + 1] << 8);
 270                         adm8211_write_sram(dev, addr + i / 2, val);
 271                 }
 272         } else {
 273                 for (i = 0; i < len; i += 4) {
 274                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 275                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 276                         adm8211_write_sram(dev, addr + i / 4, val);
 277                 }
 278         }
 279
 280         ADM8211_CSR_WRITE(WEPCTL, reg);
 281 }
 282
 283 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 284 {
 285         struct adm8211_priv *priv = dev->priv;
 286         u32 reg = ADM8211_CSR_READ(WEPCTL);
 287         unsigned int addr;
 288
 289         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 290                 adm8211_write_sram(dev, addr, 0);
 291
 292         ADM8211_CSR_WRITE(WEPCTL, reg);
 293 }
 294
 295 static int adm8211_get_stats(struct ieee80211_hw *dev,
 296                              struct ieee80211_low_level_stats *stats)
 297 {
 298         struct adm8211_priv *priv = dev->priv;
 299
 300         memcpy(stats, &priv->stats, sizeof(*stats));
 301
 302         return 0;
 303 }
 304
 305 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
 306                                 struct ieee80211_tx_queue_stats *stats)
 307 {
 308         struct adm8211_priv *priv = dev->priv;
 309
 310         stats[0].len = priv->cur_tx - priv->dirty_tx;
 311         stats[0].limit = priv->tx_ring_size - 2;
 312         stats[0].count = priv->dirty_tx;
 313
 314         return 0;
 315 }
 316
 317 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 318 {
 319         struct adm8211_priv *priv = dev->priv;
 320         unsigned int dirty_tx;
 321
 322         spin_lock(&priv->lock);
 323
 324         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 325                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 326                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 327                 struct ieee80211_tx_info *txi;
 328                 struct adm8211_tx_ring_info *info;
 329                 struct sk_buff *skb;
 330
 331                 if (status & TDES0_CONTROL_OWN ||
 332                     !(status & TDES0_CONTROL_DONE))
 333                         break;
 334
 335                 info = &priv->tx_buffers[entry];
 336                 skb = info->skb;
 337                 txi = IEEE80211_SKB_CB(skb);
 338
 339                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 340
 341                 pci_unmap_single(priv->pdev, info->mapping,
 342                                  info->skb->len, PCI_DMA_TODEVICE);
 343
 344                 ieee80211_tx_info_clear_status(txi);
 345
 346                 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 347                 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 348                 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
 349                     !(status & TDES0_STATUS_ES))
 350                         txi->flags |= IEEE80211_TX_STAT_ACK;
 351
 352                 ieee80211_tx_status_irqsafe(dev, skb);
 353
 354                 info->skb = NULL;
 355         }
 356
 357         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 358                 ieee80211_wake_queue(dev, 0);
 359
 360         priv->dirty_tx = dirty_tx;
 361         spin_unlock(&priv->lock);
 362 }
 363
 364
 365 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 366 {
 367         struct adm8211_priv *priv = dev->priv;
 368         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 369         u32 status;
 370         unsigned int pktlen;
 371         struct sk_buff *skb, *newskb;
 372         unsigned int limit = priv->rx_ring_size;
 373         u8 rssi, rate;
 374
 375         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 376                 if (!limit--)
 377                         break;
 378
 379                 status = le32_to_cpu(priv->rx_ring[entry].status);
 380                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 381                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 382                         RDES1_STATUS_RSSI;
 383
 384                 pktlen = status & RDES0_STATUS_FL;
 385                 if (pktlen > RX_PKT_SIZE) {
 386                         if (net_ratelimit())
 387                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 388                                        wiphy_name(dev->wiphy), pktlen);
 389                         pktlen = RX_PKT_SIZE;
 390                 }
 391
 392                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 393                         skb = NULL; /* old buffer will be reused */
 394                         /* TODO: update RX error stats */
 395                         /* TODO: check RDES0_STATUS_CRC*E */
 396                 } else if (pktlen < RX_COPY_BREAK) {
 397                         skb = dev_alloc_skb(pktlen);
 398                         if (skb) {
 399                                 pci_dma_sync_single_for_cpu(
 400                                         priv->pdev,
 401                                         priv->rx_buffers[entry].mapping,
 402                                         pktlen, PCI_DMA_FROMDEVICE);
 403                                 memcpy(skb_put(skb, pktlen),
 404                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 405                                        pktlen);
 406                                 pci_dma_sync_single_for_device(
 407                                         priv->pdev,
 408                                         priv->rx_buffers[entry].mapping,
 409                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 410                         }
 411                 } else {
 412                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 413                         if (newskb) {
 414                                 skb = priv->rx_buffers[entry].skb;
 415                                 skb_put(skb, pktlen);
 416                                 pci_unmap_single(
 417                                         priv->pdev,
 418                                         priv->rx_buffers[entry].mapping,
 419                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 420                                 priv->rx_buffers[entry].skb = newskb;
 421                                 priv->rx_buffers[entry].mapping =
 422                                         pci_map_single(priv->pdev,
 423                                                        skb_tail_pointer(newskb),
 424                                                        RX_PKT_SIZE,
 425                                                        PCI_DMA_FROMDEVICE);
 426                         } else {
 427                                 skb = NULL;
 428                                 /* TODO: update rx dropped stats */
 429                         }
 430
 431                         priv->rx_ring[entry].buffer1 =
 432                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 433                 }
 434
 435                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 436                                                           RDES0_STATUS_SQL);
 437                 priv->rx_ring[entry].length =
 438                         cpu_to_le32(RX_PKT_SIZE |
 439                                     (entry == priv->rx_ring_size - 1 ?
 440                                      RDES1_CONTROL_RER : 0));
 441
 442                 if (skb) {
 443                         struct ieee80211_rx_status rx_status = {0};
 444
 445                         if (priv->pdev->revision < ADM8211_REV_CA)
 446                                 rx_status.signal = rssi;
 447                         else
 448                                 rx_status.signal = 100 - rssi;
 449
 450                         rx_status.rate_idx = rate;
 451
 452                         rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
 453                         rx_status.band = IEEE80211_BAND_2GHZ;
 454
 455                         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 456                         ieee80211_rx_irqsafe(dev, skb);
 457                 }
 458
 459                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 460         }
 461
 462         /* TODO: check LPC and update stats? */
 463 }
 464
 465
 466 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 467 {
 468 #define ADM8211_INT(x)                                                     \
 469 do {                                                                       \
 470         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 471                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 472 } while (0)
 473
 474         struct ieee80211_hw *dev = dev_id;
 475         struct adm8211_priv *priv = dev->priv;
 476         u32 stsr = ADM8211_CSR_READ(STSR);
 477         ADM8211_CSR_WRITE(STSR, stsr);
 478         if (stsr == 0xffffffff)
 479                 return IRQ_HANDLED;
 480
 481         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 482                 return IRQ_HANDLED;
 483
 484         if (stsr & ADM8211_STSR_RCI)
 485                 adm8211_interrupt_rci(dev);
 486         if (stsr & ADM8211_STSR_TCI)
 487                 adm8211_interrupt_tci(dev);
 488
 489         ADM8211_INT(PCF);
 490         ADM8211_INT(BCNTC);
 491         ADM8211_INT(GPINT);
 492         ADM8211_INT(ATIMTC);
 493         ADM8211_INT(TSFTF);
 494         ADM8211_INT(TSCZ);
 495         ADM8211_INT(SQL);
 496         ADM8211_INT(WEPTD);
 497         ADM8211_INT(ATIME);
 498         ADM8211_INT(TEIS);
 499         ADM8211_INT(FBE);
 500         ADM8211_INT(REIS);
 501         ADM8211_INT(GPTT);
 502         ADM8211_INT(RPS);
 503         ADM8211_INT(RDU);
 504         ADM8211_INT(TUF);
 505         ADM8211_INT(TPS);
 506
 507         return IRQ_HANDLED;
 508
 509 #undef ADM8211_INT
 510 }
 511
 512 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 513 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 514                                            u16 addr, u32 value) {            \
 515         struct adm8211_priv *priv = dev->priv;                               \
 516         unsigned int i;                                                      \
 517         u32 reg, bitbuf;                                                     \
 518                                                                              \
 519         value &= v_mask;                                                     \
 520         addr &= a_mask;                                                      \
 521         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 522                                                                              \
 523         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 524         ADM8211_CSR_READ(SYNRF);                                             \
 525         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 526         ADM8211_CSR_READ(SYNRF);                                             \
 527                                                                              \
 528         if (prewrite) {                                                      \
 529                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 530                 ADM8211_CSR_READ(SYNRF);                                     \
 531         }                                                                    \
 532                                                                              \
 533         for (i = 0; i <= bits; i++) {                                        \
 534                 if (bitbuf & (1 << (bits - i)))                              \
 535                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 536                 else                                                         \
 537                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 538                                                                              \
 539                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 540                 ADM8211_CSR_READ(SYNRF);                                     \
 541                                                                              \
 542                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 543                 ADM8211_CSR_READ(SYNRF);                                     \
 544                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 545                 ADM8211_CSR_READ(SYNRF);                                     \
 546         }                                                                    \
 547                                                                              \
 548         if (postwrite == 1) {                                                \
 549                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 550                 ADM8211_CSR_READ(SYNRF);                                     \
 551         }                                                                    \
 552         if (postwrite == 2) {                                                \
 553                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 554                 ADM8211_CSR_READ(SYNRF);                                     \
 555         }                                                                    \
 556                                                                              \
 557         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 558         ADM8211_CSR_READ(SYNRF);                                             \
 559 }
 560
 561 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 562 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 563 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 564 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 565
 566 #undef WRITE_SYN
 567
 568 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 569 {
 570         struct adm8211_priv *priv = dev->priv;
 571         unsigned int timeout;
 572         u32 reg;
 573
 574         timeout = 10;
 575         while (timeout > 0) {
 576                 reg = ADM8211_CSR_READ(BBPCTL);
 577                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 578                         break;
 579                 timeout--;
 580                 msleep(2);
 581         }
 582
 583         if (timeout == 0) {
 584                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 585                        " prewrite (reg=0x%08x)\n",
 586                        wiphy_name(dev->wiphy), addr, data, reg);
 587                 return -ETIMEDOUT;
 588         }
 589
 590         switch (priv->bbp_type) {
 591         case ADM8211_TYPE_INTERSIL:
 592                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 593                 break;
 594         case ADM8211_TYPE_RFMD:
 595                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 596                       (0x01 << 18);
 597                 break;
 598         case ADM8211_TYPE_ADMTEK:
 599                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 600                       (0x05 << 18);
 601                 break;
 602         }
 603         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 604
 605         ADM8211_CSR_WRITE(BBPCTL, reg);
 606
 607         timeout = 10;
 608         while (timeout > 0) {
 609                 reg = ADM8211_CSR_READ(BBPCTL);
 610                 if (!(reg & ADM8211_BBPCTL_WR))
 611                         break;
 612                 timeout--;
 613                 msleep(2);
 614         }
 615
 616         if (timeout == 0) {
 617                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 618                                   ~ADM8211_BBPCTL_WR);
 619                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 620                        " postwrite (reg=0x%08x)\n",
 621                        wiphy_name(dev->wiphy), addr, data, reg);
 622                 return -ETIMEDOUT;
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 629 {
 630         static const u32 adm8211_rfmd2958_reg5[] =
 631                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 632                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 633         static const u32 adm8211_rfmd2958_reg6[] =
 634                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 635                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 636
 637         struct adm8211_priv *priv = dev->priv;
 638         u8 ant_power = priv->ant_power > 0x3F ?
 639                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 640         u8 tx_power = priv->tx_power > 0x3F ?
 641                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 642         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 643                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 644         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 645                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 646         u32 reg;
 647
 648         ADM8211_IDLE();
 649
 650         /* Program synthesizer to new channel */
 651         switch (priv->transceiver_type) {
 652         case ADM8211_RFMD2958:
 653         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 654                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 655                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 656
 657                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 658                         adm8211_rfmd2958_reg5[chan - 1]);
 659                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 660                         adm8211_rfmd2958_reg6[chan - 1]);
 661                 break;
 662
 663         case ADM8211_RFMD2948:
 664                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 665                                               SI4126_MAIN_XINDIV2);
 666                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 667                                               SI4126_POWERDOWN_PDIB |
 668                                               SI4126_POWERDOWN_PDRB);
 669                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 670                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 671                                               (chan == 14 ?
 672                                                2110 : (2033 + (chan * 5))));
 673                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 674                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 675                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 676                 break;
 677
 678         case ADM8211_MAX2820:
 679                 adm8211_rf_write_syn_max2820(dev, 0x3,
 680                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 681                 break;
 682
 683         case ADM8211_AL2210L:
 684                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 685                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 686                 break;
 687
 688         default:
 689                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 690                        wiphy_name(dev->wiphy), priv->transceiver_type);
 691                 break;
 692         }
 693
 694         /* write BBP regs */
 695         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 696
 697         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 698         /* TODO: remove if SMC 2635W doesn't need this */
 699         if (priv->transceiver_type == ADM8211_RFMD2948) {
 700                 reg = ADM8211_CSR_READ(GPIO);
 701                 reg &= 0xfffc0000;
 702                 reg |= ADM8211_CSR_GPIO_EN0;
 703                 if (chan != 14)
 704                         reg |= ADM8211_CSR_GPIO_O0;
 705                 ADM8211_CSR_WRITE(GPIO, reg);
 706         }
 707
 708         if (priv->transceiver_type == ADM8211_RFMD2958) {
 709                 /* set PCNT2 */
 710                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 711                 /* set PCNT1 P_DESIRED/MID_BIAS */
 712                 reg = le16_to_cpu(priv->eeprom->cr49);
 713                 reg >>= 13;
 714                 reg <<= 15;
 715                 reg |= ant_power << 9;
 716                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 717                 /* set TXRX TX_GAIN */
 718                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 719                         (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 720         } else {
 721                 reg = ADM8211_CSR_READ(PLCPHD);
 722                 reg &= 0xff00ffff;
 723                 reg |= tx_power << 18;
 724                 ADM8211_CSR_WRITE(PLCPHD, reg);
 725         }
 726
 727         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 728                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 729         ADM8211_CSR_READ(SYNRF);
 730         msleep(30);
 731
 732         /* RF3000 BBP */
 733         if (priv->transceiver_type != ADM8211_RFMD2958)
 734                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 735                                   tx_power<<2);
 736         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 737         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 738         adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 739                                      priv->eeprom->cr28 : 0);
 740         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 741
 742         ADM8211_CSR_WRITE(SYNRF, 0);
 743
 744         /* Nothing to do for ADMtek BBP */
 745         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 746                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 747                        wiphy_name(dev->wiphy), priv->bbp_type);
 748
 749         ADM8211_RESTORE();
 750
 751         /* update current channel for adhoc (and maybe AP mode) */
 752         reg = ADM8211_CSR_READ(CAP0);
 753         reg &= ~0xF;
 754         reg |= chan;
 755         ADM8211_CSR_WRITE(CAP0, reg);
 756
 757         return 0;
 758 }
 759
 760 static void adm8211_update_mode(struct ieee80211_hw *dev)
 761 {
 762         struct adm8211_priv *priv = dev->priv;
 763
 764         ADM8211_IDLE();
 765
 766         priv->soft_rx_crc = 0;
 767         switch (priv->mode) {
 768         case NL80211_IFTYPE_STATION:
 769                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 770                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 771                 break;
 772         case NL80211_IFTYPE_ADHOC:
 773                 priv->nar &= ~ADM8211_NAR_PR;
 774                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 775
 776                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 777                 if (priv->pdev->revision >= ADM8211_REV_BA)
 778                         priv->soft_rx_crc = 1;
 779                 break;
 780         case NL80211_IFTYPE_MONITOR:
 781                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 782                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 783                 break;
 784         }
 785
 786         ADM8211_RESTORE();
 787 }
 788
 789 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 790 {
 791         struct adm8211_priv *priv = dev->priv;
 792
 793         switch (priv->transceiver_type) {
 794         case ADM8211_RFMD2958:
 795         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 796                 /* comments taken from ADMtek vendor driver */
 797
 798                 /* Reset RF2958 after power on */
 799                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 800                 /* Initialize RF VCO Core Bias to maximum */
 801                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 802                 /* Initialize IF PLL */
 803                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 804                 /* Initialize IF PLL Coarse Tuning */
 805                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 806                 /* Initialize RF PLL */
 807                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 808                 /* Initialize RF PLL Coarse Tuning */
 809                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 810                 /* Initialize TX gain and filter BW (R9) */
 811                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 812                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 813                          0x10050 : 0x00050));
 814                 /* Initialize CAL register */
 815                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 816                 break;
 817
 818         case ADM8211_MAX2820:
 819                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 820                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 821                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 822                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 823                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 824                 break;
 825
 826         case ADM8211_AL2210L:
 827                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 828                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 829                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 830                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 831                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 832                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 833                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 834                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 835                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 836                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 837                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 838                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 839                 break;
 840
 841         case ADM8211_RFMD2948:
 842         default:
 843                 break;
 844         }
 845 }
 846
 847 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 848 {
 849         struct adm8211_priv *priv = dev->priv;
 850         u32 reg;
 851
 852         /* write addresses */
 853         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 854                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 855                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 856                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 857         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 858                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 859                 /* check specific BBP type */
 860                 switch (priv->specific_bbptype) {
 861                 case ADM8211_BBP_RFMD3000:
 862                 case ADM8211_BBP_RFMD3002:
 863                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 864                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 865                         break;
 866
 867                 case ADM8211_BBP_ADM8011:
 868                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 869                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 870
 871                         reg = ADM8211_CSR_READ(BBPCTL);
 872                         reg &= ~ADM8211_BBPCTL_TYPE;
 873                         reg |= 0x5 << 18;
 874                         ADM8211_CSR_WRITE(BBPCTL, reg);
 875                         break;
 876                 }
 877
 878                 switch (priv->pdev->revision) {
 879                 case ADM8211_REV_CA:
 880                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 881                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 882                             priv->transceiver_type == ADM8211_RFMD2948)
 883                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 884                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 885                                  priv->transceiver_type == ADM8211_AL2210L)
 886                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 887                         break;
 888
 889                 case ADM8211_REV_BA:
 890                         reg  = ADM8211_CSR_READ(MMIRD1);
 891                         reg &= 0x0000FFFF;
 892                         reg |= 0x7e100000;
 893                         ADM8211_CSR_WRITE(MMIRD1, reg);
 894                         break;
 895
 896                 case ADM8211_REV_AB:
 897                 case ADM8211_REV_AF:
 898                 default:
 899                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 900                         break;
 901                 }
 902
 903                 /* For RFMD */
 904                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 905         }
 906
 907         adm8211_hw_init_syn(dev);
 908
 909         /* Set RF Power control IF pin to PE1+PHYRST# */
 910         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 911                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 912         ADM8211_CSR_READ(SYNRF);
 913         msleep(20);
 914
 915         /* write BBP regs */
 916         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 917                 /* RF3000 BBP */
 918                 /* another set:
 919                  * 11: c8
 920                  * 14: 14
 921                  * 15: 50 (chan 1..13; chan 14: d0)
 922                  * 1c: 00
 923                  * 1d: 84
 924                  */
 925                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 926                 /* antenna selection: diversity */
 927                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 928                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 929                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 930                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 931
 932                 if (priv->eeprom->major_version < 2) {
 933                         adm8211_write_bbp(dev, 0x1c, 0x00);
 934                         adm8211_write_bbp(dev, 0x1d, 0x80);
 935                 } else {
 936                         if (priv->pdev->revision == ADM8211_REV_BA)
 937                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 938                         else
 939                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 940
 941                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 942                 }
 943         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 944                 /* reset baseband */
 945                 adm8211_write_bbp(dev, 0x00, 0xFF);
 946                 /* antenna selection: diversity */
 947                 adm8211_write_bbp(dev, 0x07, 0x0A);
 948
 949                 /* TODO: find documentation for this */
 950                 switch (priv->transceiver_type) {
 951                 case ADM8211_RFMD2958:
 952                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 953                         adm8211_write_bbp(dev, 0x00, 0x00);
 954                         adm8211_write_bbp(dev, 0x01, 0x00);
 955                         adm8211_write_bbp(dev, 0x02, 0x00);
 956                         adm8211_write_bbp(dev, 0x03, 0x00);
 957                         adm8211_write_bbp(dev, 0x06, 0x0f);
 958                         adm8211_write_bbp(dev, 0x09, 0x00);
 959                         adm8211_write_bbp(dev, 0x0a, 0x00);
 960                         adm8211_write_bbp(dev, 0x0b, 0x00);
 961                         adm8211_write_bbp(dev, 0x0c, 0x00);
 962                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 963                         adm8211_write_bbp(dev, 0x10, 0x8c);
 964                         adm8211_write_bbp(dev, 0x11, 0x43);
 965                         adm8211_write_bbp(dev, 0x18, 0x40);
 966                         adm8211_write_bbp(dev, 0x20, 0x23);
 967                         adm8211_write_bbp(dev, 0x21, 0x02);
 968                         adm8211_write_bbp(dev, 0x22, 0x28);
 969                         adm8211_write_bbp(dev, 0x23, 0x30);
 970                         adm8211_write_bbp(dev, 0x24, 0x2d);
 971                         adm8211_write_bbp(dev, 0x28, 0x35);
 972                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 973                         adm8211_write_bbp(dev, 0x2b, 0x81);
 974                         adm8211_write_bbp(dev, 0x2c, 0x44);
 975                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 976                         adm8211_write_bbp(dev, 0x29, 0x40);
 977                         adm8211_write_bbp(dev, 0x60, 0x08);
 978                         adm8211_write_bbp(dev, 0x64, 0x01);
 979                         break;
 980
 981                 case ADM8211_MAX2820:
 982                         adm8211_write_bbp(dev, 0x00, 0x00);
 983                         adm8211_write_bbp(dev, 0x01, 0x00);
 984                         adm8211_write_bbp(dev, 0x02, 0x00);
 985                         adm8211_write_bbp(dev, 0x03, 0x00);
 986                         adm8211_write_bbp(dev, 0x06, 0x0f);
 987                         adm8211_write_bbp(dev, 0x09, 0x05);
 988                         adm8211_write_bbp(dev, 0x0a, 0x02);
 989                         adm8211_write_bbp(dev, 0x0b, 0x00);
 990                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 991                         adm8211_write_bbp(dev, 0x0f, 0x55);
 992                         adm8211_write_bbp(dev, 0x10, 0x8d);
 993                         adm8211_write_bbp(dev, 0x11, 0x43);
 994                         adm8211_write_bbp(dev, 0x18, 0x4a);
 995                         adm8211_write_bbp(dev, 0x20, 0x20);
 996                         adm8211_write_bbp(dev, 0x21, 0x02);
 997                         adm8211_write_bbp(dev, 0x22, 0x23);
 998                         adm8211_write_bbp(dev, 0x23, 0x30);
 999                         adm8211_write_bbp(dev, 0x24, 0x2d);
1000                         adm8211_write_bbp(dev, 0x2a, 0x8c);
1001                         adm8211_write_bbp(dev, 0x2b, 0x81);
1002                         adm8211_write_bbp(dev, 0x2c, 0x44);
1003                         adm8211_write_bbp(dev, 0x29, 0x4a);
1004                         adm8211_write_bbp(dev, 0x60, 0x2b);
1005                         adm8211_write_bbp(dev, 0x64, 0x01);
1006                         break;
1007
1008                 case ADM8211_AL2210L:
1009                         adm8211_write_bbp(dev, 0x00, 0x00);
1010                         adm8211_write_bbp(dev, 0x01, 0x00);
1011                         adm8211_write_bbp(dev, 0x02, 0x00);
1012                         adm8211_write_bbp(dev, 0x03, 0x00);
1013                         adm8211_write_bbp(dev, 0x06, 0x0f);
1014                         adm8211_write_bbp(dev, 0x07, 0x05);
1015                         adm8211_write_bbp(dev, 0x08, 0x03);
1016                         adm8211_write_bbp(dev, 0x09, 0x00);
1017                         adm8211_write_bbp(dev, 0x0a, 0x00);
1018                         adm8211_write_bbp(dev, 0x0b, 0x00);
1019                         adm8211_write_bbp(dev, 0x0c, 0x10);
1020                         adm8211_write_bbp(dev, 0x0f, 0x55);
1021                         adm8211_write_bbp(dev, 0x10, 0x8d);
1022                         adm8211_write_bbp(dev, 0x11, 0x43);
1023                         adm8211_write_bbp(dev, 0x18, 0x4a);
1024                         adm8211_write_bbp(dev, 0x20, 0x20);
1025                         adm8211_write_bbp(dev, 0x21, 0x02);
1026                         adm8211_write_bbp(dev, 0x22, 0x23);
1027                         adm8211_write_bbp(dev, 0x23, 0x30);
1028                         adm8211_write_bbp(dev, 0x24, 0x2d);
1029                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1030                         adm8211_write_bbp(dev, 0x2b, 0x81);
1031                         adm8211_write_bbp(dev, 0x2c, 0x44);
1032                         adm8211_write_bbp(dev, 0x29, 0xfa);
1033                         adm8211_write_bbp(dev, 0x60, 0x2d);
1034                         adm8211_write_bbp(dev, 0x64, 0x01);
1035                         break;
1036
1037                 case ADM8211_RFMD2948:
1038                         break;
1039
1040                 default:
1041                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1042                                wiphy_name(dev->wiphy), priv->transceiver_type);
1043                         break;
1044                 }
1045         } else
1046                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1047                        wiphy_name(dev->wiphy), priv->bbp_type);
1048
1049         ADM8211_CSR_WRITE(SYNRF, 0);
1050
1051         /* Set RF CAL control source to MAC control */
1052         reg = ADM8211_CSR_READ(SYNCTL);
1053         reg |= ADM8211_SYNCTL_SELCAL;
1054         ADM8211_CSR_WRITE(SYNCTL, reg);
1055
1056         return 0;
1057 }
1058
1059 /* configures hw beacons/probe responses */
1060 static int adm8211_set_rate(struct ieee80211_hw *dev)
1061 {
1062         struct adm8211_priv *priv = dev->priv;
1063         u32 reg;
1064         int i = 0;
1065         u8 rate_buf[12] = {0};
1066
1067         /* write supported rates */
1068         if (priv->pdev->revision != ADM8211_REV_BA) {
1069                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1070                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1071                         rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1072         } else {
1073                 /* workaround for rev BA specific bug */
1074                 rate_buf[0] = 0x04;
1075                 rate_buf[1] = 0x82;
1076                 rate_buf[2] = 0x04;
1077                 rate_buf[3] = 0x0b;
1078                 rate_buf[4] = 0x16;
1079         }
1080
1081         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1082                                  ARRAY_SIZE(adm8211_rates) + 1);
1083
1084         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1085         reg |= 1 << 15; /* short preamble */
1086         reg |= 110 << 24;
1087         ADM8211_CSR_WRITE(PLCPHD, reg);
1088
1089         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1090          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1091          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1092         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1093
1094         return 0;
1095 }
1096
1097 static void adm8211_hw_init(struct ieee80211_hw *dev)
1098 {
1099         struct adm8211_priv *priv = dev->priv;
1100         u32 reg;
1101         u8 cline;
1102
1103         reg = ADM8211_CSR_READ(PAR);
1104         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1105         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1106
1107         if (!pci_set_mwi(priv->pdev)) {
1108                 reg |= 0x1 << 24;
1109                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1110
1111                 switch (cline) {
1112                 case  0x8: reg |= (0x1 << 14);
1113                            break;
1114                 case 0x16: reg |= (0x2 << 14);
1115                            break;
1116                 case 0x32: reg |= (0x3 << 14);
1117                            break;
1118                   default: reg |= (0x0 << 14);
1119                            break;
1120                 }
1121         }
1122
1123         ADM8211_CSR_WRITE(PAR, reg);
1124
1125         reg = ADM8211_CSR_READ(CSR_TEST1);
1126         reg &= ~(0xF << 28);
1127         reg |= (1 << 28) | (1 << 31);
1128         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1129
1130         /* lose link after 4 lost beacons */
1131         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1132         ADM8211_CSR_WRITE(WCSR, reg);
1133
1134         /* Disable APM, enable receive FIFO threshold, and set drain receive
1135          * threshold to store-and-forward */
1136         reg = ADM8211_CSR_READ(CMDR);
1137         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1138         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1139         ADM8211_CSR_WRITE(CMDR, reg);
1140
1141         adm8211_set_rate(dev);
1142
1143         /* 4-bit values:
1144          * PWR1UP   = 8 * 2 ms
1145          * PWR0PAPE = 8 us or 5 us
1146          * PWR1PAPE = 1 us or 3 us
1147          * PWR0TRSW = 5 us
1148          * PWR1TRSW = 12 us
1149          * PWR0PE2  = 13 us
1150          * PWR1PE2  = 1 us
1151          * PWR0TXPE = 8 or 6 */
1152         if (priv->pdev->revision < ADM8211_REV_CA)
1153                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1154         else
1155                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1156
1157         /* Enable store and forward for transmit */
1158         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1159         ADM8211_CSR_WRITE(NAR, priv->nar);
1160
1161         /* Reset RF */
1162         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1163         ADM8211_CSR_READ(SYNRF);
1164         msleep(10);
1165         ADM8211_CSR_WRITE(SYNRF, 0);
1166         ADM8211_CSR_READ(SYNRF);
1167         msleep(5);
1168
1169         /* Set CFP Max Duration to 0x10 TU */
1170         reg = ADM8211_CSR_READ(CFPP);
1171         reg &= ~(0xffff << 8);
1172         reg |= 0x0010 << 8;
1173         ADM8211_CSR_WRITE(CFPP, reg);
1174
1175         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1176          * TUCNT = 0x3ff - Tu counter 1024 us  */
1177         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1178
1179         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1180          * DIFS=50 us, EIFS=100 us */
1181         if (priv->pdev->revision < ADM8211_REV_CA)
1182                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1183                                         (50 << 9)  | 100);
1184         else
1185                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1186                                         (50 << 9)  | 100);
1187
1188         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1189          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1190         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1191
1192         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1193         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1194
1195         /* Initialize BBP (and SYN) */
1196         adm8211_hw_init_bbp(dev);
1197
1198         /* make sure interrupts are off */
1199         ADM8211_CSR_WRITE(IER, 0);
1200
1201         /* ACK interrupts */
1202         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1203
1204         /* Setup WEP (turns it off for now) */
1205         reg = ADM8211_CSR_READ(MACTEST);
1206         reg &= ~(7 << 20);
1207         ADM8211_CSR_WRITE(MACTEST, reg);
1208
1209         reg = ADM8211_CSR_READ(WEPCTL);
1210         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1211         reg |= ADM8211_WEPCTL_WEPRXBYP;
1212         ADM8211_CSR_WRITE(WEPCTL, reg);
1213
1214         /* Clear the missed-packet counter. */
1215         ADM8211_CSR_READ(LPC);
1216 }
1217
1218 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1219 {
1220         struct adm8211_priv *priv = dev->priv;
1221         u32 reg, tmp;
1222         int timeout = 100;
1223
1224         /* Power-on issue */
1225         /* TODO: check if this is necessary */
1226         ADM8211_CSR_WRITE(FRCTL, 0);
1227
1228         /* Reset the chip */
1229         tmp = ADM8211_CSR_READ(PAR);
1230         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1231
1232         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1233                 msleep(50);
1234
1235         if (timeout <= 0)
1236                 return -ETIMEDOUT;
1237
1238         ADM8211_CSR_WRITE(PAR, tmp);
1239
1240         if (priv->pdev->revision == ADM8211_REV_BA &&
1241             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1242              priv->transceiver_type == ADM8211_RFMD2958)) {
1243                 reg = ADM8211_CSR_READ(CSR_TEST1);
1244                 reg |= (1 << 4) | (1 << 5);
1245                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1246         } else if (priv->pdev->revision == ADM8211_REV_CA) {
1247                 reg = ADM8211_CSR_READ(CSR_TEST1);
1248                 reg &= ~((1 << 4) | (1 << 5));
1249                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1250         }
1251
1252         ADM8211_CSR_WRITE(FRCTL, 0);
1253
1254         reg = ADM8211_CSR_READ(CSR_TEST0);
1255         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1256         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1257
1258         adm8211_clear_sram(dev);
1259
1260         return 0;
1261 }
1262
1263 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1264 {
1265         struct adm8211_priv *priv = dev->priv;
1266         u32 tsftl;
1267         u64 tsft;
1268
1269         tsftl = ADM8211_CSR_READ(TSFTL);
1270         tsft = ADM8211_CSR_READ(TSFTH);
1271         tsft <<= 32;
1272         tsft |= tsftl;
1273
1274         return tsft;
1275 }
1276
1277 static void adm8211_set_interval(struct ieee80211_hw *dev,
1278                                  unsigned short bi, unsigned short li)
1279 {
1280         struct adm8211_priv *priv = dev->priv;
1281         u32 reg;
1282
1283         /* BP (beacon interval) = data->beacon_interval
1284          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1285         reg = (bi << 16) | li;
1286         ADM8211_CSR_WRITE(BPLI, reg);
1287 }
1288
1289 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1290 {
1291         struct adm8211_priv *priv = dev->priv;
1292         u32 reg;
1293
1294         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1295         reg = ADM8211_CSR_READ(ABDA1);
1296         reg &= 0x0000ffff;
1297         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1298         ADM8211_CSR_WRITE(ABDA1, reg);
1299 }
1300
1301 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1302 {
1303         struct adm8211_priv *priv = dev->priv;
1304         struct ieee80211_conf *conf = &dev->conf;
1305         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1306
1307         if (channel != priv->channel) {
1308                 priv->channel = channel;
1309                 adm8211_rf_set_channel(dev, priv->channel);
1310         }
1311
1312         return 0;
1313 }
1314
1315 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1316                                      struct ieee80211_vif *vif,
1317                                      struct ieee80211_bss_conf *conf,
1318                                      u32 changes)
1319 {
1320         struct adm8211_priv *priv = dev->priv;
1321
1322         if (!(changes & BSS_CHANGED_BSSID))
1323                 return;
1324
1325         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1326                 adm8211_set_bssid(dev, conf->bssid);
1327                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1328         }
1329 }
1330
1331 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1332                                      int mc_count, struct dev_addr_list *mclist)
1333 {
1334         unsigned int bit_nr, i;
1335         u32 mc_filter[2];
1336
1337         mc_filter[1] = mc_filter[0] = 0;
1338
1339         for (i = 0; i < mc_count; i++) {
1340                 if (!mclist)
1341                         break;
1342                 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1343
1344                 bit_nr &= 0x3F;
1345                 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1346                 mclist = mclist->next;
1347         }
1348
1349         return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1350 }
1351
1352 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1353                                      unsigned int changed_flags,
1354                                      unsigned int *total_flags,
1355                                      u64 multicast)
1356 {
1357         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1358         struct adm8211_priv *priv = dev->priv;
1359         unsigned int new_flags;
1360         u32 mc_filter[2];
1361
1362         mc_filter[0] = multicast;
1363         mc_filter[1] = multicast >> 32;
1364
1365         new_flags = 0;
1366
1367         if (*total_flags & FIF_PROMISC_IN_BSS) {
1368                 new_flags |= FIF_PROMISC_IN_BSS;
1369                 priv->nar |= ADM8211_NAR_PR;
1370                 priv->nar &= ~ADM8211_NAR_MM;
1371                 mc_filter[1] = mc_filter[0] = ~0;
1372         } else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1373                 new_flags |= FIF_ALLMULTI;
1374                 priv->nar &= ~ADM8211_NAR_PR;
1375                 priv->nar |= ADM8211_NAR_MM;
1376                 mc_filter[1] = mc_filter[0] = ~0;
1377         } else {
1378                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1379         }
1380
1381         ADM8211_IDLE_RX();
1382
1383         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1384         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1385         ADM8211_CSR_READ(NAR);
1386
1387         if (priv->nar & ADM8211_NAR_PR)
1388                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1389         else
1390                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1391
1392         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1393                 adm8211_set_bssid(dev, bcast);
1394         else
1395                 adm8211_set_bssid(dev, priv->bssid);
1396
1397         ADM8211_RESTORE();
1398
1399         *total_flags = new_flags;
1400 }
1401
1402 static int adm8211_add_interface(struct ieee80211_hw *dev,
1403                                  struct ieee80211_if_init_conf *conf)
1404 {
1405         struct adm8211_priv *priv = dev->priv;
1406         if (priv->mode != NL80211_IFTYPE_MONITOR)
1407                 return -EOPNOTSUPP;
1408
1409         switch (conf->type) {
1410         case NL80211_IFTYPE_STATION:
1411                 priv->mode = conf->type;
1412                 break;
1413         default:
1414                 return -EOPNOTSUPP;
1415         }
1416
1417         ADM8211_IDLE();
1418
1419         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1420         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
1421
1422         adm8211_update_mode(dev);
1423
1424         ADM8211_RESTORE();
1425
1426         return 0;
1427 }
1428
1429 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1430                                      struct ieee80211_if_init_conf *conf)
1431 {
1432         struct adm8211_priv *priv = dev->priv;
1433         priv->mode = NL80211_IFTYPE_MONITOR;
1434 }
1435
1436 static int adm8211_init_rings(struct ieee80211_hw *dev)
1437 {
1438         struct adm8211_priv *priv = dev->priv;
1439         struct adm8211_desc *desc = NULL;
1440         struct adm8211_rx_ring_info *rx_info;
1441         struct adm8211_tx_ring_info *tx_info;
1442         unsigned int i;
1443
1444         for (i = 0; i < priv->rx_ring_size; i++) {
1445                 desc = &priv->rx_ring[i];
1446                 desc->status = 0;
1447                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1448                 priv->rx_buffers[i].skb = NULL;
1449         }
1450         /* Mark the end of RX ring; hw returns to base address after this
1451          * descriptor */
1452         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1453
1454         for (i = 0; i < priv->rx_ring_size; i++) {
1455                 desc = &priv->rx_ring[i];
1456                 rx_info = &priv->rx_buffers[i];
1457
1458                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1459                 if (rx_info->skb == NULL)
1460                         break;
1461                 rx_info->mapping = pci_map_single(priv->pdev,
1462                                                   skb_tail_pointer(rx_info->skb),
1463                                                   RX_PKT_SIZE,
1464                                                   PCI_DMA_FROMDEVICE);
1465                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1466                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1467         }
1468
1469         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1470         for (i = 0; i < priv->tx_ring_size; i++) {
1471                 desc = &priv->tx_ring[i];
1472                 tx_info = &priv->tx_buffers[i];
1473
1474                 tx_info->skb = NULL;
1475                 tx_info->mapping = 0;
1476                 desc->status = 0;
1477         }
1478         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1479
1480         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1481         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1482         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1483
1484         return 0;
1485 }
1486
1487 static void adm8211_free_rings(struct ieee80211_hw *dev)
1488 {
1489         struct adm8211_priv *priv = dev->priv;
1490         unsigned int i;
1491
1492         for (i = 0; i < priv->rx_ring_size; i++) {
1493                 if (!priv->rx_buffers[i].skb)
1494                         continue;
1495
1496                 pci_unmap_single(
1497                         priv->pdev,
1498                         priv->rx_buffers[i].mapping,
1499                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1500
1501                 dev_kfree_skb(priv->rx_buffers[i].skb);
1502         }
1503
1504         for (i = 0; i < priv->tx_ring_size; i++) {
1505                 if (!priv->tx_buffers[i].skb)
1506                         continue;
1507
1508                 pci_unmap_single(priv->pdev,
1509                                  priv->tx_buffers[i].mapping,
1510                                  priv->tx_buffers[i].skb->len,
1511                                  PCI_DMA_TODEVICE);
1512
1513                 dev_kfree_skb(priv->tx_buffers[i].skb);
1514         }
1515 }
1516
1517 static int adm8211_start(struct ieee80211_hw *dev)
1518 {
1519         struct adm8211_priv *priv = dev->priv;
1520         int retval;
1521
1522         /* Power up MAC and RF chips */
1523         retval = adm8211_hw_reset(dev);
1524         if (retval) {
1525                 printk(KERN_ERR "%s: hardware reset failed\n",
1526                        wiphy_name(dev->wiphy));
1527                 goto fail;
1528         }
1529
1530         retval = adm8211_init_rings(dev);
1531         if (retval) {
1532                 printk(KERN_ERR "%s: failed to initialize rings\n",
1533                        wiphy_name(dev->wiphy));
1534                 goto fail;
1535         }
1536
1537         /* Init hardware */
1538         adm8211_hw_init(dev);
1539         adm8211_rf_set_channel(dev, priv->channel);
1540
1541         retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1542                              IRQF_SHARED, "adm8211", dev);
1543         if (retval) {
1544                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1545                        wiphy_name(dev->wiphy));
1546                 goto fail;
1547         }
1548
1549         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1550                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1551                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1552         priv->mode = NL80211_IFTYPE_MONITOR;
1553         adm8211_update_mode(dev);
1554         ADM8211_CSR_WRITE(RDR, 0);
1555
1556         adm8211_set_interval(dev, 100, 10);
1557         return 0;
1558
1559 fail:
1560         return retval;
1561 }
1562
1563 static void adm8211_stop(struct ieee80211_hw *dev)
1564 {
1565         struct adm8211_priv *priv = dev->priv;
1566
1567         priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1568         priv->nar = 0;
1569         ADM8211_CSR_WRITE(NAR, 0);
1570         ADM8211_CSR_WRITE(IER, 0);
1571         ADM8211_CSR_READ(NAR);
1572
1573         free_irq(priv->pdev->irq, dev);
1574
1575         adm8211_free_rings(dev);
1576 }
1577
1578 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1579                                    int plcp_signal, int short_preamble)
1580 {
1581         /* Alternative calculation from NetBSD: */
1582
1583 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1584 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1585 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1586 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1587 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1588 #define IEEE80211_DUR_DS_SLOW_ACK       112
1589 #define IEEE80211_DUR_DS_FAST_ACK       56
1590 #define IEEE80211_DUR_DS_SLOW_CTS       112
1591 #define IEEE80211_DUR_DS_FAST_CTS       56
1592 #define IEEE80211_DUR_DS_SLOT           20
1593 #define IEEE80211_DUR_DS_SIFS           10
1594
1595         int remainder;
1596
1597         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1598                 / plcp_signal;
1599
1600         if (plcp_signal <= PLCP_SIGNAL_2M)
1601                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1602                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1603                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1604                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1605                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1606         else
1607                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1608                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1609                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1610                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1611                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1612
1613         /* lengthen duration if long preamble */
1614         if (!short_preamble)
1615                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1616                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1617                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1618                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1619
1620
1621         *plcp = (80 * len) / plcp_signal;
1622         remainder = (80 * len) % plcp_signal;
1623         if (plcp_signal == PLCP_SIGNAL_11M &&
1624             remainder <= 30 && remainder > 0)
1625                 *plcp = (*plcp | 0x8000) + 1;
1626         else if (remainder)
1627                 (*plcp)++;
1628 }
1629
1630 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1631 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1632                            u16 plcp_signal,
1633                            size_t hdrlen)
1634 {
1635         struct adm8211_priv *priv = dev->priv;
1636         unsigned long flags;
1637         dma_addr_t mapping;
1638         unsigned int entry;
1639         u32 flag;
1640
1641         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1642                                  PCI_DMA_TODEVICE);
1643
1644         spin_lock_irqsave(&priv->lock, flags);
1645
1646         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1647                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1648         else
1649                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1650
1651         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1652                 ieee80211_stop_queue(dev, 0);
1653
1654         entry = priv->cur_tx % priv->tx_ring_size;
1655
1656         priv->tx_buffers[entry].skb = skb;
1657         priv->tx_buffers[entry].mapping = mapping;
1658         priv->tx_buffers[entry].hdrlen = hdrlen;
1659         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1660
1661         if (entry == priv->tx_ring_size - 1)
1662                 flag |= TDES1_CONTROL_TER;
1663         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1664
1665         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1666         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1667         priv->tx_ring[entry].status = cpu_to_le32(flag);
1668
1669         priv->cur_tx++;
1670
1671         spin_unlock_irqrestore(&priv->lock, flags);
1672
1673         /* Trigger transmit poll */
1674         ADM8211_CSR_WRITE(TDR, 0);
1675 }
1676
1677 /* Put adm8211_tx_hdr on skb and transmit */
1678 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
1679 {
1680         struct adm8211_tx_hdr *txhdr;
1681         size_t payload_len, hdrlen;
1682         int plcp, dur, len, plcp_signal, short_preamble;
1683         struct ieee80211_hdr *hdr;
1684         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1685         struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1686         u8 rc_flags;
1687
1688         rc_flags = info->control.rates[0].flags;
1689         short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1690         plcp_signal = txrate->bitrate;
1691
1692         hdr = (struct ieee80211_hdr *)skb->data;
1693         hdrlen = ieee80211_hdrlen(hdr->frame_control);
1694         memcpy(skb->cb, skb->data, hdrlen);
1695         hdr = (struct ieee80211_hdr *)skb->cb;
1696         skb_pull(skb, hdrlen);
1697         payload_len = skb->len;
1698
1699         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1700         memset(txhdr, 0, sizeof(*txhdr));
1701         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1702         txhdr->signal = plcp_signal;
1703         txhdr->frame_body_size = cpu_to_le16(payload_len);
1704         txhdr->frame_control = hdr->frame_control;
1705
1706         len = hdrlen + payload_len + FCS_LEN;
1707
1708         txhdr->frag = cpu_to_le16(0x0FFF);
1709         adm8211_calc_durations(&dur, &plcp, payload_len,
1710                                len, plcp_signal, short_preamble);
1711         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1712         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1713         txhdr->dur_frag_head = cpu_to_le16(dur);
1714         txhdr->dur_frag_tail = cpu_to_le16(dur);
1715
1716         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1717
1718         if (short_preamble)
1719                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1720
1721         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1722                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1723
1724         txhdr->retry_limit = info->control.rates[0].count;
1725
1726         adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1727
1728         return NETDEV_TX_OK;
1729 }
1730
1731 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1732 {
1733         struct adm8211_priv *priv = dev->priv;
1734         unsigned int ring_size;
1735
1736         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1737                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1738         if (!priv->rx_buffers)
1739                 return -ENOMEM;
1740
1741         priv->tx_buffers = (void *)priv->rx_buffers +
1742                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1743
1744         /* Allocate TX/RX descriptors */
1745         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1746                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1747         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1748                                              &priv->rx_ring_dma);
1749
1750         if (!priv->rx_ring) {
1751                 kfree(priv->rx_buffers);
1752                 priv->rx_buffers = NULL;
1753                 priv->tx_buffers = NULL;
1754                 return -ENOMEM;
1755         }
1756
1757         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1758                                                 priv->rx_ring_size);
1759         priv->tx_ring_dma = priv->rx_ring_dma +
1760                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1761
1762         return 0;
1763 }
1764
1765 static const struct ieee80211_ops adm8211_ops = {
1766         .tx                     = adm8211_tx,
1767         .start                  = adm8211_start,
1768         .stop                   = adm8211_stop,
1769         .add_interface          = adm8211_add_interface,
1770         .remove_interface       = adm8211_remove_interface,
1771         .config                 = adm8211_config,
1772         .bss_info_changed       = adm8211_bss_info_changed,
1773         .prepare_multicast      = adm8211_prepare_multicast,
1774         .configure_filter       = adm8211_configure_filter,
1775         .get_stats              = adm8211_get_stats,
1776         .get_tx_stats           = adm8211_get_tx_stats,
1777         .get_tsf                = adm8211_get_tsft
1778 };
1779
1780 static int __devinit adm8211_probe(struct pci_dev *pdev,
1781                                    const struct pci_device_id *id)
1782 {
1783         struct ieee80211_hw *dev;
1784         struct adm8211_priv *priv;
1785         unsigned long mem_addr, mem_len;
1786         unsigned int io_addr, io_len;
1787         int err;
1788         u32 reg;
1789         u8 perm_addr[ETH_ALEN];
1790
1791         err = pci_enable_device(pdev);
1792         if (err) {
1793                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1794                        pci_name(pdev));
1795                 return err;
1796         }
1797
1798         io_addr = pci_resource_start(pdev, 0);
1799         io_len = pci_resource_len(pdev, 0);
1800         mem_addr = pci_resource_start(pdev, 1);
1801         mem_len = pci_resource_len(pdev, 1);
1802         if (io_len < 256 || mem_len < 1024) {
1803                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1804                        pci_name(pdev));
1805                 goto err_disable_pdev;
1806         }
1807
1808
1809         /* check signature */
1810         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1811         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1812                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1813                        pci_name(pdev), reg);
1814                 goto err_disable_pdev;
1815         }
1816
1817         err = pci_request_regions(pdev, "adm8211");
1818         if (err) {
1819                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1820                        pci_name(pdev));
1821                 return err; /* someone else grabbed it? don't disable it */
1822         }
1823
1824         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1825             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1826                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1827                        pci_name(pdev));
1828                 goto err_free_reg;
1829         }
1830
1831         pci_set_master(pdev);
1832
1833         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1834         if (!dev) {
1835                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1836                        pci_name(pdev));
1837                 err = -ENOMEM;
1838                 goto err_free_reg;
1839         }
1840         priv = dev->priv;
1841         priv->pdev = pdev;
1842
1843         spin_lock_init(&priv->lock);
1844
1845         SET_IEEE80211_DEV(dev, &pdev->dev);
1846
1847         pci_set_drvdata(pdev, dev);
1848
1849         priv->map = pci_iomap(pdev, 1, mem_len);
1850         if (!priv->map)
1851                 priv->map = pci_iomap(pdev, 0, io_len);
1852
1853         if (!priv->map) {
1854                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1855                        pci_name(pdev));
1856                 goto err_free_dev;
1857         }
1858
1859         priv->rx_ring_size = rx_ring_size;
1860         priv->tx_ring_size = tx_ring_size;
1861
1862         if (adm8211_alloc_rings(dev)) {
1863                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1864                        pci_name(pdev));
1865                 goto err_iounmap;
1866         }
1867
1868         *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1869         *(__le16 *)&perm_addr[4] =
1870                 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1871
1872         if (!is_valid_ether_addr(perm_addr)) {
1873                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1874                        pci_name(pdev));
1875                 random_ether_addr(perm_addr);
1876         }
1877         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1878
1879         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1880         /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1881         dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
1882         dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1883
1884         dev->channel_change_time = 1000;
1885         dev->max_signal = 100;    /* FIXME: find better value */
1886
1887         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1888
1889         priv->retry_limit = 3;
1890         priv->ant_power = 0x40;
1891         priv->tx_power = 0x40;
1892         priv->lpf_cutoff = 0xFF;
1893         priv->lnags_threshold = 0xFF;
1894         priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1895
1896         /* Power-on issue. EEPROM won't read correctly without */
1897         if (pdev->revision >= ADM8211_REV_BA) {
1898                 ADM8211_CSR_WRITE(FRCTL, 0);
1899                 ADM8211_CSR_READ(FRCTL);
1900                 ADM8211_CSR_WRITE(FRCTL, 1);
1901                 ADM8211_CSR_READ(FRCTL);
1902                 msleep(100);
1903         }
1904
1905         err = adm8211_read_eeprom(dev);
1906         if (err) {
1907                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1908                        pci_name(pdev));
1909                 goto err_free_desc;
1910         }
1911
1912         priv->channel = 1;
1913
1914         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1915
1916         err = ieee80211_register_hw(dev);
1917         if (err) {
1918                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1919                        pci_name(pdev));
1920                 goto err_free_desc;
1921         }
1922
1923         printk(KERN_INFO "%s: hwaddr %pM, Rev 0x%02x\n",
1924                wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1925                pdev->revision);
1926
1927         return 0;
1928
1929  err_free_desc:
1930         pci_free_consistent(pdev,
1931                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1932                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1933                             priv->rx_ring, priv->rx_ring_dma);
1934         kfree(priv->rx_buffers);
1935
1936  err_iounmap:
1937         pci_iounmap(pdev, priv->map);
1938
1939  err_free_dev:
1940         pci_set_drvdata(pdev, NULL);
1941         ieee80211_free_hw(dev);
1942
1943  err_free_reg:
1944         pci_release_regions(pdev);
1945
1946  err_disable_pdev:
1947         pci_disable_device(pdev);
1948         return err;
1949 }
1950
1951
1952 static void __devexit adm8211_remove(struct pci_dev *pdev)
1953 {
1954         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1955         struct adm8211_priv *priv;
1956
1957         if (!dev)
1958                 return;
1959
1960         ieee80211_unregister_hw(dev);
1961
1962         priv = dev->priv;
1963
1964         pci_free_consistent(pdev,
1965                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1966                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1967                             priv->rx_ring, priv->rx_ring_dma);
1968
1969         kfree(priv->rx_buffers);
1970         kfree(priv->eeprom);
1971         pci_iounmap(pdev, priv->map);
1972         pci_release_regions(pdev);
1973         pci_disable_device(pdev);
1974         ieee80211_free_hw(dev);
1975 }
1976
1977
1978 #ifdef CONFIG_PM
1979 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1980 {
1981         pci_save_state(pdev);
1982         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1983         return 0;
1984 }
1985
1986 static int adm8211_resume(struct pci_dev *pdev)
1987 {
1988         pci_set_power_state(pdev, PCI_D0);
1989         pci_restore_state(pdev);
1990         return 0;
1991 }
1992 #endif /* CONFIG_PM */
1993
1994
1995 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1996
1997 /* TODO: implement enable_wake */
1998 static struct pci_driver adm8211_driver = {
1999         .name           = "adm8211",
2000         .id_table       = adm8211_pci_id_table,
2001         .probe          = adm8211_probe,
2002         .remove         = __devexit_p(adm8211_remove),
2003 #ifdef CONFIG_PM
2004         .suspend        = adm8211_suspend,
2005         .resume         = adm8211_resume,
2006 #endif /* CONFIG_PM */
2007 };
2008
2009
2010
2011 static int __init adm8211_init(void)
2012 {
2013         return pci_register_driver(&adm8211_driver);
2014 }
2015
2016
2017 static void __exit adm8211_exit(void)
2018 {
2019         pci_unregister_driver(&adm8211_driver);
2020 }
2021
2022
2023 module_init(adm8211_init);
2024 module_exit(adm8211_exit);