drivers/net/wan/pc300_drv.c

   1 #define USE_PCI_CLOCK
   2 static const char rcsid[] =
   3 "Revision: 3.4.5 Date: 2002/03/07 ";
   4
   5 /*
   6  * pc300.c      Cyclades-PC300(tm) Driver.
   7  *
   8  * Author:      Ivan Passos <ivan@cyclades.com>
   9  * Maintainer:  PC300 Maintainer <pc300@cyclades.com>
  10  *
  11  * Copyright:   (c) 1999-2003 Cyclades Corp.
  12  *
  13  *      This program is free software; you can redistribute it and/or
  14  *      modify it under the terms of the GNU General Public License
  15  *      as published by the Free Software Foundation; either version
  16  *      2 of the License, or (at your option) any later version.
  17  *
  18  *      Using tabstop = 4.
  19  *
  20  * $Log: pc300_drv.c,v $
  21  * Revision 3.23  2002/03/20 13:58:40  henrique
  22  * Fixed ortographic mistakes
  23  *
  24  * Revision 3.22  2002/03/13 16:56:56  henrique
  25  * Take out the debug messages
  26  *
  27  * Revision 3.21  2002/03/07 14:17:09  henrique
  28  * License data fixed
  29  *
  30  * Revision 3.20  2002/01/17 17:58:52  ivan
  31  * Support for PC300-TE/M (PMC).
  32  *
  33  * Revision 3.19  2002/01/03 17:08:47  daniela
  34  * Enables DMA reception when the SCA-II disables it improperly.
  35  *
  36  * Revision 3.18  2001/12/03 18:47:50  daniela
  37  * Esthetic changes.
  38  *
  39  * Revision 3.17  2001/10/19 16:50:13  henrique
  40  * Patch to kernel 2.4.12 and new generic hdlc.
  41  *
  42  * Revision 3.16  2001/10/16 15:12:31  regina
  43  * clear statistics
  44  *
  45  * Revision 3.11 to 3.15  2001/10/11 20:26:04  daniela
  46  * More DMA fixes for noisy lines.
  47  * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
  48  * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
  49  * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
  50  * Fixed BOF interrupt treatment. Created dma_start routine.
  51  * Changed min and max to cpc_min and cpc_max.
  52  *
  53  * Revision 3.10  2001/08/06 12:01:51  regina
  54  * Fixed problem in DSR_DE bit.
  55  *
  56  * Revision 3.9  2001/07/18 19:27:26  daniela
  57  * Added some history comments.
  58  *
  59  * Revision 3.8  2001/07/12 13:11:19  regina
  60  * bug fix - DCD-OFF in pc300 tty driver
  61  *
  62  * Revision 3.3 to 3.7  2001/07/06 15:00:20  daniela
  63  * Removing kernel 2.4.3 and previous support.
  64  * DMA transmission bug fix.
  65  * MTU check in cpc_net_rx fixed.
  66  * Boot messages reviewed.
  67  * New configuration parameters (line code, CRC calculation and clock).
  68  *
  69  * Revision 3.2 2001/06/22 13:13:02  regina
  70  * MLPPP implementation. Changed the header of message trace to include
  71  * the device name. New format : "hdlcX[R/T]: ".
  72  * Default configuration changed.
  73  *
  74  * Revision 3.1 2001/06/15 regina
  75  * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
  76  * upping major version number
  77  *
  78  * Revision 1.1.1.1  2001/06/13 20:25:04  daniela
  79  * PC300 initial CVS version (3.4.0-pre1)
  80  *
  81  * Revision 3.0.1.2 2001/06/08 daniela
  82  * Did some changes in the DMA programming implementation to avoid the
  83  * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
  84  *
  85  * Revision 3.0.1.1 2001/05/02 daniela
  86  * Added kernel 2.4.3 support.
  87  *
  88  * Revision 3.0.1.0 2001/03/13 daniela, henrique
  89  * Added Frame Relay Support.
  90  * Driver now uses HDLC generic driver to provide protocol support.
  91  *
  92  * Revision 3.0.0.8 2001/03/02 daniela
  93  * Fixed ram size detection.
  94  * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
  95  *
  96  * Revision 3.0.0.7 2001/02/23 daniela
  97  * netif_stop_queue called before the SCA-II transmition commands in
  98  * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
  99  * transmition interrupts.
 100  * Fixed falc_check_status for Unframed E1.
 101  *
 102  * Revision 3.0.0.6 2000/12/13 daniela
 103  * Implemented pc300util support: trace, statistics, status and loopback
 104  * tests for the PC300 TE boards.
 105  *
 106  * Revision 3.0.0.5 2000/12/12 ivan
 107  * Added support for Unframed E1.
 108  * Implemented monitor mode.
 109  * Fixed DCD sensitivity on the second channel.
 110  * Driver now complies with new PCI kernel architecture.
 111  *
 112  * Revision 3.0.0.4 2000/09/28 ivan
 113  * Implemented DCD sensitivity.
 114  * Moved hardware-specific open to the end of cpc_open, to avoid race
 115  * conditions with early reception interrupts.
 116  * Included code for [request|release]_mem_region().
 117  * Changed location of pc300.h .
 118  * Minor code revision (contrib. of Jeff Garzik).
 119  *
 120  * Revision 3.0.0.3 2000/07/03 ivan
 121  * Previous bugfix for the framing errors with external clock made X21
 122  * boards stop working. This version fixes it.
 123  *
 124  * Revision 3.0.0.2 2000/06/23 ivan
 125  * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
 126  * handling when Tx timeouts occur.
 127  * Revisited Rx statistics.
 128  * Fixed a bug in the SCA-II programming that would cause framing errors
 129  * when external clock was configured.
 130  *
 131  * Revision 3.0.0.1 2000/05/26 ivan
 132  * Added logic in the SCA interrupt handler so that no board can monopolize
 133  * the driver.
 134  * Request PLX I/O region, although driver doesn't use it, to avoid
 135  * problems with other drivers accessing it.
 136  *
 137  * Revision 3.0.0.0 2000/05/15 ivan
 138  * Did some changes in the DMA programming implementation to avoid the
 139  * occurrence of a SCA-II bug in the second channel.
 140  * Implemented workaround for PLX9050 bug that would cause a system lockup
 141  * in certain systems, depending on the MMIO addresses allocated to the
 142  * board.
 143  * Fixed the FALC chip programming to avoid synchronization problems in the
 144  * second channel (TE only).
 145  * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
 146  * cpc_queue_xmit().
 147  * Changed the built-in driver implementation so that the driver can use the
 148  * general 'hdlcN' naming convention instead of proprietary device names.
 149  * Driver load messages are now device-centric, instead of board-centric.
 150  * Dynamic allocation of net_device structures.
 151  * Code is now compliant with the new module interface (module_[init|exit]).
 152  * Make use of the PCI helper functions to access PCI resources.
 153  *
 154  * Revision 2.0.0.0 2000/04/15 ivan
 155  * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
 156  *
 157  * Revision 1.1.0.0 2000/02/28 ivan
 158  * Major changes in the driver architecture.
 159  * Softnet compliancy implemented.
 160  * Driver now reports physical instead of virtual memory addresses.
 161  * Added cpc_change_mtu function.
 162  *
 163  * Revision 1.0.0.0 1999/12/16 ivan
 164  * First official release.
 165  * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
 166  * Support for monolythic installation (i.e., drv built into the kernel).
 167  * X.25 additional checking when lapb_[dis]connect_request returns an error.
 168  * SCA programming now covers X.21 as well.
 169  *
 170  * Revision 0.3.1.0 1999/11/18 ivan
 171  * Made X.25 support configuration-dependent (as it depends on external
 172  * modules to work).
 173  * Changed X.25-specific function names to comply with adopted convention.
 174  * Fixed typos in X.25 functions that would cause compile errors (Daniela).
 175  * Fixed bug in ch_config that would disable interrupts on a previously
 176  * enabled channel if the other channel on the same board was enabled later.
 177  *
 178  * Revision 0.3.0.0 1999/11/16 daniela
 179  * X.25 support.
 180  *
 181  * Revision 0.2.3.0 1999/11/15 ivan
 182  * Function cpc_ch_status now provides more detailed information.
 183  * Added support for X.21 clock configuration.
 184  * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
 185  * Now using PCI clock instead of internal oscillator clock for the SCA.
 186  *
 187  * Revision 0.2.2.0 1999/11/10 ivan
 188  * Changed the *_dma_buf_check functions so that they would print only
 189  * the useful info instead of the whole buffer descriptor bank.
 190  * Fixed bug in cpc_queue_xmit that would eventually crash the system
 191  * in case of a packet drop.
 192  * Implemented TX underrun handling.
 193  * Improved SCA fine tuning to boost up its performance.
 194  *
 195  * Revision 0.2.1.0 1999/11/03 ivan
 196  * Added functions *dma_buf_pt_init to allow independent initialization
 197  * of the next-descr. and DMA buffer pointers on the DMA descriptors.
 198  * Kernel buffer release and tbusy clearing is now done in the interrupt
 199  * handler.
 200  * Fixed bug in cpc_open that would cause an interface reopen to fail.
 201  * Added a protocol-specific code section in cpc_net_rx.
 202  * Removed printk level defs (they might be added back after the beta phase).
 203  *
 204  * Revision 0.2.0.0 1999/10/28 ivan
 205  * Revisited the code so that new protocols can be easily added / supported.
 206  *
 207  * Revision 0.1.0.1 1999/10/20 ivan
 208  * Mostly "esthetic" changes.
 209  *
 210  * Revision 0.1.0.0 1999/10/11 ivan
 211  * Initial version.
 212  *
 213  */
 214
 215 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 216
 217 #include <linux/module.h>
 218 #include <linux/kernel.h>
 219 #include <linux/mm.h>
 220 #include <linux/ioport.h>
 221 #include <linux/pci.h>
 222 #include <linux/errno.h>
 223 #include <linux/string.h>
 224 #include <linux/init.h>
 225 #include <linux/delay.h>
 226 #include <linux/net.h>
 227 #include <linux/skbuff.h>
 228 #include <linux/if_arp.h>
 229 #include <linux/netdevice.h>
 230 #include <linux/etherdevice.h>
 231 #include <linux/spinlock.h>
 232 #include <linux/if.h>
 233 #include <linux/slab.h>
 234 #include <net/arp.h>
 235
 236 #include <asm/io.h>
 237 #include <asm/uaccess.h>
 238
 239 #include "pc300.h"
 240
 241 #define CPC_LOCK(card,flags)            \
 242                 do {                                            \
 243                 spin_lock_irqsave(&card->card_lock, flags);     \
 244                 } while (0)
 245
 246 #define CPC_UNLOCK(card,flags)                  \
 247                 do {                                                    \
 248                 spin_unlock_irqrestore(&card->card_lock, flags);        \
 249                 } while (0)
 250
 251 #undef  PC300_DEBUG_PCI
 252 #undef  PC300_DEBUG_INTR
 253 #undef  PC300_DEBUG_TX
 254 #undef  PC300_DEBUG_RX
 255 #undef  PC300_DEBUG_OTHER
 256
 257 static DEFINE_PCI_DEVICE_TABLE(cpc_pci_dev_id) = {
 258         /* PC300/RSV or PC300/X21, 2 chan */
 259         {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
 260         /* PC300/RSV or PC300/X21, 1 chan */
 261         {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
 262         /* PC300/TE, 2 chan */
 263         {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
 264         /* PC300/TE, 1 chan */
 265         {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
 266         /* PC300/TE-M, 2 chan */
 267         {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
 268         /* PC300/TE-M, 1 chan */
 269         {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
 270         /* End of table */
 271         {0,},
 272 };
 273 MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
 274
 275 #ifndef cpc_min
 276 #define cpc_min(a,b)    (((a)<(b))?(a):(b))
 277 #endif
 278 #ifndef cpc_max
 279 #define cpc_max(a,b)    (((a)>(b))?(a):(b))
 280 #endif
 281
 282 /* prototypes */
 283 static void tx_dma_buf_pt_init(pc300_t *, int);
 284 static void tx_dma_buf_init(pc300_t *, int);
 285 static void rx_dma_buf_pt_init(pc300_t *, int);
 286 static void rx_dma_buf_init(pc300_t *, int);
 287 static void tx_dma_buf_check(pc300_t *, int);
 288 static void rx_dma_buf_check(pc300_t *, int);
 289 static irqreturn_t cpc_intr(int, void *);
 290 static int clock_rate_calc(u32, u32, int *);
 291 static u32 detect_ram(pc300_t *);
 292 static void plx_init(pc300_t *);
 293 static void cpc_trace(struct net_device *, struct sk_buff *, char);
 294 static int cpc_attach(struct net_device *, unsigned short, unsigned short);
 295 static int cpc_close(struct net_device *dev);
 296
 297 #ifdef CONFIG_PC300_MLPPP
 298 void cpc_tty_init(pc300dev_t * dev);
 299 void cpc_tty_unregister_service(pc300dev_t * pc300dev);
 300 void cpc_tty_receive(pc300dev_t * pc300dev);
 301 void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
 302 void cpc_tty_reset_var(void);
 303 #endif
 304
 305 /************************/
 306 /***   DMA Routines   ***/
 307 /************************/
 308 static void tx_dma_buf_pt_init(pc300_t * card, int ch)
 309 {
 310         int i;
 311         int ch_factor = ch * N_DMA_TX_BUF;
 312         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 313                                        + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 314
 315         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
 316                 cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
 317                         (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
 318                 cpc_writel(&ptdescr->ptbuf,
 319                            (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
 320         }
 321 }
 322
 323 static void tx_dma_buf_init(pc300_t * card, int ch)
 324 {
 325         int i;
 326         int ch_factor = ch * N_DMA_TX_BUF;
 327         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 328                                + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 329
 330         for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
 331                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
 332                 cpc_writew(&ptdescr->len, 0);
 333                 cpc_writeb(&ptdescr->status, DST_OSB);
 334         }
 335         tx_dma_buf_pt_init(card, ch);
 336 }
 337
 338 static void rx_dma_buf_pt_init(pc300_t * card, int ch)
 339 {
 340         int i;
 341         int ch_factor = ch * N_DMA_RX_BUF;
 342         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 343                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 344
 345         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
 346                 cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
 347                         (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
 348                 cpc_writel(&ptdescr->ptbuf,
 349                            (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
 350         }
 351 }
 352
 353 static void rx_dma_buf_init(pc300_t * card, int ch)
 354 {
 355         int i;
 356         int ch_factor = ch * N_DMA_RX_BUF;
 357         volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
 358                                        + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 359
 360         for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
 361                 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
 362                 cpc_writew(&ptdescr->len, 0);
 363                 cpc_writeb(&ptdescr->status, 0);
 364         }
 365         rx_dma_buf_pt_init(card, ch);
 366 }
 367
 368 static void tx_dma_buf_check(pc300_t * card, int ch)
 369 {
 370         volatile pcsca_bd_t __iomem *ptdescr;
 371         int i;
 372         u16 first_bd = card->chan[ch].tx_first_bd;
 373         u16 next_bd = card->chan[ch].tx_next_bd;
 374
 375         printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
 376                first_bd, TX_BD_ADDR(ch, first_bd),
 377                next_bd, TX_BD_ADDR(ch, next_bd));
 378         for (i = first_bd,
 379              ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
 380              i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
 381              i = (i + 1) & (N_DMA_TX_BUF - 1),
 382                  ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
 383                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 384                        ch, i, cpc_readl(&ptdescr->next),
 385                        cpc_readl(&ptdescr->ptbuf),
 386                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
 387         }
 388         printk("\n");
 389 }
 390
 391 #ifdef  PC300_DEBUG_OTHER
 392 /* Show all TX buffer descriptors */
 393 static void tx1_dma_buf_check(pc300_t * card, int ch)
 394 {
 395         volatile pcsca_bd_t __iomem *ptdescr;
 396         int i;
 397         u16 first_bd = card->chan[ch].tx_first_bd;
 398         u16 next_bd = card->chan[ch].tx_next_bd;
 399         u32 scabase = card->hw.scabase;
 400
 401         printk ("\nnfree_tx_bd = %d\n", card->chan[ch].nfree_tx_bd);
 402         printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
 403                first_bd, TX_BD_ADDR(ch, first_bd),
 404                next_bd, TX_BD_ADDR(ch, next_bd));
 405         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
 406                cpc_readl(scabase + DTX_REG(CDAL, ch)),
 407                cpc_readl(scabase + DTX_REG(EDAL, ch)));
 408         for (i = 0; i < N_DMA_TX_BUF; i++) {
 409                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
 410                 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 411                        ch, i, cpc_readl(&ptdescr->next),
 412                        cpc_readl(&ptdescr->ptbuf),
 413                        cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
 414         }
 415         printk("\n");
 416 }
 417 #endif
 418
 419 static void rx_dma_buf_check(pc300_t * card, int ch)
 420 {
 421         volatile pcsca_bd_t __iomem *ptdescr;
 422         int i;
 423         u16 first_bd = card->chan[ch].rx_first_bd;
 424         u16 last_bd = card->chan[ch].rx_last_bd;
 425         int ch_factor;
 426
 427         ch_factor = ch * N_DMA_RX_BUF;
 428         printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
 429         for (i = 0, ptdescr = (card->hw.rambase +
 430                                               DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
 431              i < N_DMA_RX_BUF; i++, ptdescr++) {
 432                 if (cpc_readb(&ptdescr->status) & DST_OSB)
 433                         printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
 434                                  ch, i, cpc_readl(&ptdescr->next),
 435                                  cpc_readl(&ptdescr->ptbuf),
 436                                  cpc_readb(&ptdescr->status),
 437                                  cpc_readw(&ptdescr->len));
 438         }
 439         printk("\n");
 440 }
 441
 442 static int dma_get_rx_frame_size(pc300_t * card, int ch)
 443 {
 444         volatile pcsca_bd_t __iomem *ptdescr;
 445         u16 first_bd = card->chan[ch].rx_first_bd;
 446         int rcvd = 0;
 447         volatile u8 status;
 448
 449         ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
 450         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
 451                 rcvd += cpc_readw(&ptdescr->len);
 452                 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
 453                 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
 454                         /* Return the size of a good frame or incomplete bad frame
 455                         * (dma_buf_read will clean the buffer descriptors in this case). */
 456                         return rcvd;
 457                 }
 458                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
 459         }
 460         return -1;
 461 }
 462
 463 /*
 464  * dma_buf_write: writes a frame to the Tx DMA buffers
 465  * NOTE: this function writes one frame at a time.
 466  */
 467 static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
 468 {
 469         int i, nchar;
 470         volatile pcsca_bd_t __iomem *ptdescr;
 471         int tosend = len;
 472         u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
 473
 474         if (nbuf >= card->chan[ch].nfree_tx_bd) {
 475                 return -ENOMEM;
 476         }
 477
 478         for (i = 0; i < nbuf; i++) {
 479                 ptdescr = (card->hw.rambase +
 480                                           TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
 481                 nchar = cpc_min(BD_DEF_LEN, tosend);
 482                 if (cpc_readb(&ptdescr->status) & DST_OSB) {
 483                         memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
 484                                     &ptdata[len - tosend], nchar);
 485                         cpc_writew(&ptdescr->len, nchar);
 486                         card->chan[ch].nfree_tx_bd--;
 487                         if ((i + 1) == nbuf) {
 488                                 /* This must be the last BD to be used */
 489                                 cpc_writeb(&ptdescr->status, DST_EOM);
 490                         } else {
 491                                 cpc_writeb(&ptdescr->status, 0);
 492                         }
 493                 } else {
 494                         return -ENOMEM;
 495                 }
 496                 tosend -= nchar;
 497                 card->chan[ch].tx_next_bd =
 498                         (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
 499         }
 500         /* If it gets to here, it means we have sent the whole frame */
 501         return 0;
 502 }
 503
 504 /*
 505  * dma_buf_read: reads a frame from the Rx DMA buffers
 506  * NOTE: this function reads one frame at a time.
 507  */
 508 static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
 509 {
 510         int nchar;
 511         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 512         volatile pcsca_bd_t __iomem *ptdescr;
 513         int rcvd = 0;
 514         volatile u8 status;
 515
 516         ptdescr = (card->hw.rambase +
 517                                   RX_BD_ADDR(ch, chan->rx_first_bd));
 518         while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
 519                 nchar = cpc_readw(&ptdescr->len);
 520                 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT)) ||
 521                     (nchar > BD_DEF_LEN)) {
 522
 523                         if (nchar > BD_DEF_LEN)
 524                                 status |= DST_RBIT;
 525                         rcvd = -status;
 526                         /* Discard remaining descriptors used by the bad frame */
 527                         while (chan->rx_first_bd != chan->rx_last_bd) {
 528                                 cpc_writeb(&ptdescr->status, 0);
 529                                 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
 530                                 if (status & DST_EOM)
 531                                         break;
 532                                 ptdescr = (card->hw.rambase +
 533                                                           cpc_readl(&ptdescr->next));
 534                                 status = cpc_readb(&ptdescr->status);
 535                         }
 536                         break;
 537                 }
 538                 if (nchar != 0) {
 539                         if (skb) {
 540                                 memcpy_fromio(skb_put(skb, nchar),
 541                                  (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
 542                         }
 543                         rcvd += nchar;
 544                 }
 545                 cpc_writeb(&ptdescr->status, 0);
 546                 cpc_writeb(&ptdescr->len, 0);
 547                 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
 548
 549                 if (status & DST_EOM)
 550                         break;
 551
 552                 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
 553         }
 554
 555         if (rcvd != 0) {
 556                 /* Update pointer */
 557                 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
 558                 /* Update EDA */
 559                 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
 560                            RX_BD_ADDR(ch, chan->rx_last_bd));
 561         }
 562         return rcvd;
 563 }
 564
 565 static void tx_dma_stop(pc300_t * card, int ch)
 566 {
 567         void __iomem *scabase = card->hw.scabase;
 568         u8 drr_ena_bit = 1 << (5 + 2 * ch);
 569         u8 drr_rst_bit = 1 << (1 + 2 * ch);
 570
 571         /* Disable DMA */
 572         cpc_writeb(scabase + DRR, drr_ena_bit);
 573         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
 574 }
 575
 576 static void rx_dma_stop(pc300_t * card, int ch)
 577 {
 578         void __iomem *scabase = card->hw.scabase;
 579         u8 drr_ena_bit = 1 << (4 + 2 * ch);
 580         u8 drr_rst_bit = 1 << (2 * ch);
 581
 582         /* Disable DMA */
 583         cpc_writeb(scabase + DRR, drr_ena_bit);
 584         cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
 585 }
 586
 587 static void rx_dma_start(pc300_t * card, int ch)
 588 {
 589         void __iomem *scabase = card->hw.scabase;
 590         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 591
 592         /* Start DMA */
 593         cpc_writel(scabase + DRX_REG(CDAL, ch),
 594                    RX_BD_ADDR(ch, chan->rx_first_bd));
 595         if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
 596                                   RX_BD_ADDR(ch, chan->rx_first_bd)) {
 597                 cpc_writel(scabase + DRX_REG(CDAL, ch),
 598                                    RX_BD_ADDR(ch, chan->rx_first_bd));
 599         }
 600         cpc_writel(scabase + DRX_REG(EDAL, ch),
 601                    RX_BD_ADDR(ch, chan->rx_last_bd));
 602         cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
 603         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
 604         if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
 605         cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
 606         }
 607 }
 608
 609 /*************************/
 610 /***   FALC Routines   ***/
 611 /*************************/
 612 static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
 613 {
 614         void __iomem *falcbase = card->hw.falcbase;
 615         unsigned long i = 0;
 616
 617         while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
 618                 if (i++ >= PC300_FALC_MAXLOOP) {
 619                         printk("%s: FALC command locked(cmd=0x%x).\n",
 620                                card->chan[ch].d.name, cmd);
 621                         break;
 622                 }
 623         }
 624         cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
 625 }
 626
 627 static void falc_intr_enable(pc300_t * card, int ch)
 628 {
 629         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 630         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 631         falc_t *pfalc = (falc_t *) & chan->falc;
 632         void __iomem *falcbase = card->hw.falcbase;
 633
 634         /* Interrupt pins are open-drain */
 635         cpc_writeb(falcbase + F_REG(IPC, ch),
 636                    cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
 637         /* Conters updated each second */
 638         cpc_writeb(falcbase + F_REG(FMR1, ch),
 639                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
 640         /* Enable SEC and ES interrupts  */
 641         cpc_writeb(falcbase + F_REG(IMR3, ch),
 642                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
 643         if (conf->fr_mode == PC300_FR_UNFRAMED) {
 644                 cpc_writeb(falcbase + F_REG(IMR4, ch),
 645                            cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
 646         } else {
 647                 cpc_writeb(falcbase + F_REG(IMR4, ch),
 648                            cpc_readb(falcbase + F_REG(IMR4, ch)) &
 649                            ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
 650         }
 651         if (conf->media == IF_IFACE_T1) {
 652                 cpc_writeb(falcbase + F_REG(IMR3, ch),
 653                            cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
 654         } else {
 655                 cpc_writeb(falcbase + F_REG(IPC, ch),
 656                            cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
 657                 if (conf->fr_mode == PC300_FR_UNFRAMED) {
 658                         cpc_writeb(falcbase + F_REG(IMR2, ch),
 659                                    cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
 660                 } else {
 661                         cpc_writeb(falcbase + F_REG(IMR2, ch),
 662                                    cpc_readb(falcbase + F_REG(IMR2, ch)) &
 663                                    ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
 664                         if (pfalc->multiframe_mode) {
 665                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
 666                                            cpc_readb(falcbase + F_REG(IMR2, ch)) &
 667                                            ~(IMR2_T400MS | IMR2_MFAR));
 668                         } else {
 669                                 cpc_writeb(falcbase + F_REG(IMR2, ch),
 670                                            cpc_readb(falcbase + F_REG(IMR2, ch)) |
 671                                            IMR2_T400MS | IMR2_MFAR);
 672                         }
 673                 }
 674         }
 675 }
 676
 677 static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
 678 {
 679         void __iomem *falcbase = card->hw.falcbase;
 680         u8 tshf = card->chan[ch].falc.offset;
 681
 682         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
 683                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
 684                         ~(0x80 >> ((timeslot - tshf) & 0x07)));
 685         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
 686                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
 687                         (0x80 >> (timeslot & 0x07)));
 688         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
 689                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
 690                         (0x80 >> (timeslot & 0x07)));
 691 }
 692
 693 static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
 694 {
 695         void __iomem *falcbase = card->hw.falcbase;
 696         u8 tshf = card->chan[ch].falc.offset;
 697
 698         cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
 699                    cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
 700                    (0x80 >> ((timeslot - tshf) & 0x07)));
 701         cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
 702                    cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
 703                    ~(0x80 >> (timeslot & 0x07)));
 704         cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
 705                    cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
 706                    ~(0x80 >> (timeslot & 0x07)));
 707 }
 708
 709 static void falc_close_all_timeslots(pc300_t * card, int ch)
 710 {
 711         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 712         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 713         void __iomem *falcbase = card->hw.falcbase;
 714
 715         cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
 716         cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
 717         cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
 718         cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
 719         cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
 720         cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
 721         cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
 722         cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
 723         cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
 724         if (conf->media == IF_IFACE_E1) {
 725                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
 726                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
 727                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
 728         }
 729 }
 730
 731 static void falc_open_all_timeslots(pc300_t * card, int ch)
 732 {
 733         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 734         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 735         void __iomem *falcbase = card->hw.falcbase;
 736
 737         cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
 738         if (conf->fr_mode == PC300_FR_UNFRAMED) {
 739                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
 740                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
 741         } else {
 742                 /* Timeslot 0 is never enabled */
 743                 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
 744                 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
 745         }
 746         cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
 747         cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
 748         cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
 749         cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
 750         cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
 751         cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
 752         if (conf->media == IF_IFACE_E1) {
 753                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
 754                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
 755                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
 756         } else {
 757                 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
 758                 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
 759                 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
 760         }
 761 }
 762
 763 static void falc_init_timeslot(pc300_t * card, int ch)
 764 {
 765         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 766         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 767         falc_t *pfalc = (falc_t *) & chan->falc;
 768         int tslot;
 769
 770         for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
 771                 if (conf->tslot_bitmap & (1 << tslot)) {
 772                         // Channel enabled
 773                         falc_open_timeslot(card, ch, tslot + 1);
 774                 } else {
 775                         // Channel disabled
 776                         falc_close_timeslot(card, ch, tslot + 1);
 777                 }
 778         }
 779 }
 780
 781 static void falc_enable_comm(pc300_t * card, int ch)
 782 {
 783         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 784         falc_t *pfalc = (falc_t *) & chan->falc;
 785
 786         if (pfalc->full_bandwidth) {
 787                 falc_open_all_timeslots(card, ch);
 788         } else {
 789                 falc_init_timeslot(card, ch);
 790         }
 791         // CTS/DCD ON
 792         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
 793                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
 794                    ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
 795 }
 796
 797 static void falc_disable_comm(pc300_t * card, int ch)
 798 {
 799         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 800         falc_t *pfalc = (falc_t *) & chan->falc;
 801
 802         if (pfalc->loop_active != 2) {
 803                 falc_close_all_timeslots(card, ch);
 804         }
 805         // CTS/DCD OFF
 806         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
 807                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
 808                    ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
 809 }
 810
 811 static void falc_init_t1(pc300_t * card, int ch)
 812 {
 813         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 814         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 815         falc_t *pfalc = (falc_t *) & chan->falc;
 816         void __iomem *falcbase = card->hw.falcbase;
 817         u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
 818
 819         /* Switch to T1 mode (PCM 24) */
 820         cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
 821
 822         /* Wait 20 us for setup */
 823         udelay(20);
 824
 825         /* Transmit Buffer Size (1 frame) */
 826         cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
 827
 828         /* Clock mode */
 829         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
 830                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 831                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
 832         } else { /* Slave mode */
 833                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 834                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
 835                 cpc_writeb(falcbase + F_REG(LOOP, ch),
 836                            cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
 837         }
 838
 839         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
 840         cpc_writeb(falcbase + F_REG(FMR0, ch),
 841                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
 842                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
 843
 844         switch (conf->lcode) {
 845                 case PC300_LC_AMI:
 846                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 847                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
 848                                    FMR0_XC1 | FMR0_RC1);
 849                         /* Clear Channel register to ON for all channels */
 850                         cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
 851                         cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
 852                         cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
 853                         break;
 854
 855                 case PC300_LC_B8ZS:
 856                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 857                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
 858                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
 859                         break;
 860
 861                 case PC300_LC_NRZ:
 862                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 863                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
 864                         break;
 865         }
 866
 867         cpc_writeb(falcbase + F_REG(LIM0, ch),
 868                    cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
 869         cpc_writeb(falcbase + F_REG(LIM0, ch),
 870                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
 871         /* Set interface mode to 2 MBPS */
 872         cpc_writeb(falcbase + F_REG(FMR1, ch),
 873                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
 874
 875         switch (conf->fr_mode) {
 876                 case PC300_FR_ESF:
 877                         pfalc->multiframe_mode = 0;
 878                         cpc_writeb(falcbase + F_REG(FMR4, ch),
 879                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
 880                         cpc_writeb(falcbase + F_REG(FMR1, ch),
 881                                    cpc_readb(falcbase + F_REG(FMR1, ch)) |
 882                                    FMR1_CRC | FMR1_EDL);
 883                         cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
 884                         cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
 885                         cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
 886                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 887                                    cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
 888                         cpc_writeb(falcbase + F_REG(FMR2, ch),
 889                                    cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
 890                         break;
 891
 892                 case PC300_FR_D4:
 893                         pfalc->multiframe_mode = 1;
 894                         cpc_writeb(falcbase + F_REG(FMR4, ch),
 895                                    cpc_readb(falcbase + F_REG(FMR4, ch)) &
 896                                    ~(FMR4_FM1 | FMR4_FM0));
 897                         cpc_writeb(falcbase + F_REG(FMR0, ch),
 898                                    cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
 899                         cpc_writeb(falcbase + F_REG(FMR2, ch),
 900                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
 901                         break;
 902         }
 903
 904         /* Enable Automatic Resynchronization */
 905         cpc_writeb(falcbase + F_REG(FMR4, ch),
 906                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
 907
 908         /* Transmit Automatic Remote Alarm */
 909         cpc_writeb(falcbase + F_REG(FMR2, ch),
 910                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
 911
 912         /* Channel translation mode 1 : one to one */
 913         cpc_writeb(falcbase + F_REG(FMR1, ch),
 914                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
 915
 916         /* No signaling */
 917         cpc_writeb(falcbase + F_REG(FMR1, ch),
 918                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
 919         cpc_writeb(falcbase + F_REG(FMR5, ch),
 920                    cpc_readb(falcbase + F_REG(FMR5, ch)) &
 921                    ~(FMR5_EIBR | FMR5_SRS));
 922         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
 923
 924         cpc_writeb(falcbase + F_REG(LIM1, ch),
 925                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
 926
 927         switch (conf->lbo) {
 928                         /* Provides proper Line Build Out */
 929                 case PC300_LBO_0_DB:
 930                         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
 931                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
 932                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
 933                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 934                         break;
 935                 case PC300_LBO_7_5_DB:
 936                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
 937                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
 938                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
 939                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 940                         break;
 941                 case PC300_LBO_15_DB:
 942                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
 943                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
 944                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
 945                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 946                         break;
 947                 case PC300_LBO_22_5_DB:
 948                         cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
 949                         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
 950                         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
 951                         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
 952                         break;
 953         }
 954
 955         /* Transmit Clock-Slot Offset */
 956         cpc_writeb(falcbase + F_REG(XC0, ch),
 957                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
 958         /* Transmit Time-slot Offset */
 959         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
 960         /* Receive  Clock-Slot offset */
 961         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
 962         /* Receive  Time-slot offset */
 963         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
 964
 965         /* LOS Detection after 176 consecutive 0s */
 966         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
 967         /* LOS Recovery after 22 ones in the time window of PCD */
 968         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
 969
 970         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
 971
 972         if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
 973                 cpc_writeb(falcbase + F_REG(RC1, ch),
 974                            cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
 975         }
 976
 977         falc_close_all_timeslots(card, ch);
 978 }
 979
 980 static void falc_init_e1(pc300_t * card, int ch)
 981 {
 982         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
 983         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
 984         falc_t *pfalc = (falc_t *) & chan->falc;
 985         void __iomem *falcbase = card->hw.falcbase;
 986         u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
 987
 988         /* Switch to E1 mode (PCM 30) */
 989         cpc_writeb(falcbase + F_REG(FMR1, ch),
 990                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
 991
 992         /* Clock mode */
 993         if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
 994                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 995                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
 996         } else { /* Slave mode */
 997                 cpc_writeb(falcbase + F_REG(LIM0, ch),
 998                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
 999         }
1000         cpc_writeb(falcbase + F_REG(LOOP, ch),
1001                    cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1002
1003         cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1004         cpc_writeb(falcbase + F_REG(FMR0, ch),
1005                    cpc_readb(falcbase + F_REG(FMR0, ch)) &
1006                    ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1007
1008         switch (conf->lcode) {
1009                 case PC300_LC_AMI:
1010                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1011                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1012                                    FMR0_XC1 | FMR0_RC1);
1013                         break;
1014
1015                 case PC300_LC_HDB3:
1016                         cpc_writeb(falcbase + F_REG(FMR0, ch),
1017                                    cpc_readb(falcbase + F_REG(FMR0, ch)) |
1018                                    FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1019                         break;
1020
1021                 case PC300_LC_NRZ:
1022                         break;
1023         }
1024
1025         cpc_writeb(falcbase + F_REG(LIM0, ch),
1026                    cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1027         /* Set interface mode to 2 MBPS */
1028         cpc_writeb(falcbase + F_REG(FMR1, ch),
1029                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1030
1031         cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1032         cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1033         cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1034
1035         switch (conf->fr_mode) {
1036                 case PC300_FR_MF_CRC4:
1037                         pfalc->multiframe_mode = 1;
1038                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1039                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1040                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1041                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1042                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1043                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1044                         cpc_writeb(falcbase + F_REG(FMR3, ch),
1045                                    cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1046
1047                         /* MultiFrame Resynchronization */
1048                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1049                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1050
1051                         /* Automatic Loss of Multiframe > 914 CRC errors */
1052                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1053                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1054
1055                         /* S1 and SI1/SI2 spare Bits set to 1 */
1056                         cpc_writeb(falcbase + F_REG(XSP, ch),
1057                                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1058                         cpc_writeb(falcbase + F_REG(XSP, ch),
1059                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1060                         cpc_writeb(falcbase + F_REG(XSP, ch),
1061                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1062
1063                         /* Automatic Force Resynchronization */
1064                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1065                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1066
1067                         /* Transmit Automatic Remote Alarm */
1068                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1069                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1070
1071                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1072                         cpc_writeb(falcbase + F_REG(XSW, ch),
1073                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1074                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1075                         break;
1076
1077                 case PC300_FR_MF_NON_CRC4:
1078                 case PC300_FR_D4:
1079                         pfalc->multiframe_mode = 0;
1080                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1081                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1082                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1083                                    cpc_readb(falcbase + F_REG(FMR2, ch)) &
1084                                    ~(FMR2_RFS1 | FMR2_RFS0));
1085                         cpc_writeb(falcbase + F_REG(XSW, ch),
1086                                    cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1087                         cpc_writeb(falcbase + F_REG(XSP, ch),
1088                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1089
1090                         /* Automatic Force Resynchronization */
1091                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1092                                    cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1093
1094                         /* Transmit Automatic Remote Alarm */
1095                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1096                                    cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1097
1098                         /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1099                         cpc_writeb(falcbase + F_REG(XSW, ch),
1100                                    cpc_readb(falcbase + F_REG(XSW, ch)) |
1101                                    XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1102                         break;
1103
1104                 case PC300_FR_UNFRAMED:
1105                         pfalc->multiframe_mode = 0;
1106                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1107                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1108                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1109                                    cpc_readb(falcbase + F_REG(FMR2, ch)) &
1110                                    ~(FMR2_RFS1 | FMR2_RFS0));
1111                         cpc_writeb(falcbase + F_REG(XSP, ch),
1112                                    cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1113                         cpc_writeb(falcbase + F_REG(XSW, ch),
1114                                    cpc_readb(falcbase + F_REG(XSW, ch)) &
1115                                    ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1116                         cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1117                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1118                                    cpc_readb(falcbase + F_REG(FMR2, ch)) |
1119                                    (FMR2_RTM | FMR2_DAIS));
1120                         cpc_writeb(falcbase + F_REG(FMR2, ch),
1121                                    cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1122                         cpc_writeb(falcbase + F_REG(FMR1, ch),
1123                                    cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1124                         pfalc->sync = 1;
1125                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1126                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1127                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1128                         break;
1129         }
1130
1131         /* No signaling */
1132         cpc_writeb(falcbase + F_REG(XSP, ch),
1133                    cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1134         cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1135
1136         cpc_writeb(falcbase + F_REG(LIM1, ch),
1137                    cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1138         cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1139
1140         /* Transmit Clock-Slot Offset */
1141         cpc_writeb(falcbase + F_REG(XC0, ch),
1142                    cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1143         /* Transmit Time-slot Offset */
1144         cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1145         /* Receive  Clock-Slot offset */
1146         cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1147         /* Receive  Time-slot offset */
1148         cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1149
1150         /* LOS Detection after 176 consecutive 0s */
1151         cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1152         /* LOS Recovery after 22 ones in the time window of PCD */
1153         cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1154
1155         cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1156
1157         falc_close_all_timeslots(card, ch);
1158 }
1159
1160 static void falc_init_hdlc(pc300_t * card, int ch)
1161 {
1162         void __iomem *falcbase = card->hw.falcbase;
1163         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1164         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1165
1166         /* Enable transparent data transfer */
1167         if (conf->fr_mode == PC300_FR_UNFRAMED) {
1168                 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1169         } else {
1170                 cpc_writeb(falcbase + F_REG(MODE, ch),
1171                            cpc_readb(falcbase + F_REG(MODE, ch)) |
1172                            (MODE_HRAC | MODE_MDS2));
1173                 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1174                 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1175                 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1176                 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1177         }
1178
1179         /* Tx/Rx reset  */
1180         falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1181
1182         /* Enable interrupt sources */
1183         falc_intr_enable(card, ch);
1184 }
1185
1186 static void te_config(pc300_t * card, int ch)
1187 {
1188         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1189         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1190         falc_t *pfalc = (falc_t *) & chan->falc;
1191         void __iomem *falcbase = card->hw.falcbase;
1192         u8 dummy;
1193         unsigned long flags;
1194
1195         memset(pfalc, 0, sizeof(falc_t));
1196         switch (conf->media) {
1197                 case IF_IFACE_T1:
1198                         pfalc->num_channels = NUM_OF_T1_CHANNELS;
1199                         pfalc->offset = 1;
1200                         break;
1201                 case IF_IFACE_E1:
1202                         pfalc->num_channels = NUM_OF_E1_CHANNELS;
1203                         pfalc->offset = 0;
1204                         break;
1205         }
1206         if (conf->tslot_bitmap == 0xffffffffUL)
1207                 pfalc->full_bandwidth = 1;
1208         else
1209                 pfalc->full_bandwidth = 0;
1210
1211         CPC_LOCK(card, flags);
1212         /* Reset the FALC chip */
1213         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1214                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1215                    (CPLD_REG1_FALC_RESET << (2 * ch)));
1216         udelay(10000);
1217         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1218                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1219                    ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1220
1221         if (conf->media == IF_IFACE_T1) {
1222                 falc_init_t1(card, ch);
1223         } else {
1224                 falc_init_e1(card, ch);
1225         }
1226         falc_init_hdlc(card, ch);
1227         if (conf->rx_sens == PC300_RX_SENS_SH) {
1228                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1229                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1230         } else {
1231                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1232                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1233         }
1234         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1235                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1236                    ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1237
1238         /* Clear all interrupt registers */
1239         dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1240                 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1241                 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1242                 cpc_readb(falcbase + F_REG(FISR3, ch));
1243         CPC_UNLOCK(card, flags);
1244 }
1245
1246 static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1247 {
1248         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1249         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1250         falc_t *pfalc = (falc_t *) & chan->falc;
1251         void __iomem *falcbase = card->hw.falcbase;
1252
1253         /* Verify LOS */
1254         if (frs0 & FRS0_LOS) {
1255                 if (!pfalc->red_alarm) {
1256                         pfalc->red_alarm = 1;
1257                         pfalc->los++;
1258                         if (!pfalc->blue_alarm) {
1259                                 // EVENT_FALC_ABNORMAL
1260                                 if (conf->media == IF_IFACE_T1) {
1261                                         /* Disable this interrupt as it may otherwise interfere
1262                                          * with other working boards. */
1263                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1264                                                    cpc_readb(falcbase + F_REG(IMR0, ch))
1265                                                    | IMR0_PDEN);
1266                                 }
1267                                 falc_disable_comm(card, ch);
1268                                 // EVENT_FALC_ABNORMAL
1269                         }
1270                 }
1271         } else {
1272                 if (pfalc->red_alarm) {
1273                         pfalc->red_alarm = 0;
1274                         pfalc->losr++;
1275                 }
1276         }
1277
1278         if (conf->fr_mode != PC300_FR_UNFRAMED) {
1279                 /* Verify AIS alarm */
1280                 if (frs0 & FRS0_AIS) {
1281                         if (!pfalc->blue_alarm) {
1282                                 pfalc->blue_alarm = 1;
1283                                 pfalc->ais++;
1284                                 // EVENT_AIS
1285                                 if (conf->media == IF_IFACE_T1) {
1286                                         /* Disable this interrupt as it may otherwise interfere with                       other working boards. */
1287                                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1288                                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1289                                 }
1290                                 falc_disable_comm(card, ch);
1291                                 // EVENT_AIS
1292                         }
1293                 } else {
1294                         pfalc->blue_alarm = 0;
1295                 }
1296
1297                 /* Verify LFA */
1298                 if (frs0 & FRS0_LFA) {
1299                         if (!pfalc->loss_fa) {
1300                                 pfalc->loss_fa = 1;
1301                                 pfalc->lfa++;
1302                                 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1303                                         // EVENT_FALC_ABNORMAL
1304                                         if (conf->media == IF_IFACE_T1) {
1305                                                 /* Disable this interrupt as it may otherwise
1306                                                  * interfere with other working boards. */
1307                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1308                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1309                                                            | IMR0_PDEN);
1310                                         }
1311                                         falc_disable_comm(card, ch);
1312                                         // EVENT_FALC_ABNORMAL
1313                                 }
1314                         }
1315                 } else {
1316                         if (pfalc->loss_fa) {
1317                                 pfalc->loss_fa = 0;
1318                                 pfalc->farec++;
1319                         }
1320                 }
1321
1322                 /* Verify LMFA */
1323                 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1324                         /* D4 or CRC4 frame mode */
1325                         if (!pfalc->loss_mfa) {
1326                                 pfalc->loss_mfa = 1;
1327                                 pfalc->lmfa++;
1328                                 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1329                                     !pfalc->loss_fa) {
1330                                         // EVENT_FALC_ABNORMAL
1331                                         if (conf->media == IF_IFACE_T1) {
1332                                                 /* Disable this interrupt as it may otherwise
1333                                                  * interfere with other working boards. */
1334                                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1335                                                            cpc_readb(falcbase + F_REG(IMR0, ch))
1336                                                            | IMR0_PDEN);
1337                                         }
1338                                         falc_disable_comm(card, ch);
1339                                         // EVENT_FALC_ABNORMAL
1340                                 }
1341                         }
1342                 } else {
1343                         pfalc->loss_mfa = 0;
1344                 }
1345
1346                 /* Verify Remote Alarm */
1347                 if (frs0 & FRS0_RRA) {
1348                         if (!pfalc->yellow_alarm) {
1349                                 pfalc->yellow_alarm = 1;
1350                                 pfalc->rai++;
1351                                 if (pfalc->sync) {
1352                                         // EVENT_RAI
1353                                         falc_disable_comm(card, ch);
1354                                         // EVENT_RAI
1355                                 }
1356                         }
1357                 } else {
1358                         pfalc->yellow_alarm = 0;
1359                 }
1360         } /* if !PC300_UNFRAMED */
1361
1362         if (pfalc->red_alarm || pfalc->loss_fa ||
1363             pfalc->loss_mfa || pfalc->blue_alarm) {
1364                 if (pfalc->sync) {
1365                         pfalc->sync = 0;
1366                         chan->d.line_off++;
1367                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1368                                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1369                                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1370                 }
1371         } else {
1372                 if (!pfalc->sync) {
1373                         pfalc->sync = 1;
1374                         chan->d.line_on++;
1375                         cpc_writeb(falcbase + card->hw.cpld_reg2,
1376                                    cpc_readb(falcbase + card->hw.cpld_reg2) |
1377                                    (CPLD_REG2_FALC_LED2 << (2 * ch)));
1378                 }
1379         }
1380
1381         if (pfalc->sync && !pfalc->yellow_alarm) {
1382                 if (!pfalc->active) {
1383                         // EVENT_FALC_NORMAL
1384                         if (pfalc->loop_active) {
1385                                 return;
1386                         }
1387                         if (conf->media == IF_IFACE_T1) {
1388                                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1389                                            cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1390                         }
1391                         falc_enable_comm(card, ch);
1392                         // EVENT_FALC_NORMAL
1393                         pfalc->active = 1;
1394                 }
1395         } else {
1396                 if (pfalc->active) {
1397                         pfalc->active = 0;
1398                 }
1399         }
1400 }
1401
1402 static void falc_update_stats(pc300_t * card, int ch)
1403 {
1404         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1405         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1406         falc_t *pfalc = (falc_t *) & chan->falc;
1407         void __iomem *falcbase = card->hw.falcbase;
1408         u16 counter;
1409
1410         counter = cpc_readb(falcbase + F_REG(FECL, ch));
1411         counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1412         pfalc->fec += counter;
1413
1414         counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1415         counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1416         pfalc->cvc += counter;
1417
1418         counter = cpc_readb(falcbase + F_REG(CECL, ch));
1419         counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1420         pfalc->cec += counter;
1421
1422         counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1423         counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1424         pfalc->ebc += counter;
1425
1426         if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1427                 mdelay(10);
1428                 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1429                 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1430                 pfalc->bec += counter;
1431
1432                 if (((conf->media == IF_IFACE_T1) &&
1433                      (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1434                      (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN))) ||
1435                     ((conf->media == IF_IFACE_E1) &&
1436                      (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1437                         pfalc->prbs = 2;
1438                 } else {
1439                         pfalc->prbs = 1;
1440                 }
1441         }
1442 }
1443
1444 /*----------------------------------------------------------------------------
1445  * falc_remote_loop
1446  *----------------------------------------------------------------------------
1447  * Description: In the remote loopback mode the clock and data recovered
1448  *              from the line inputs RL1/2 or RDIP/RDIN are routed back
1449  *              to the line outputs XL1/2 or XDOP/XDON via the analog
1450  *              transmitter. As in normal mode they are processed by
1451  *              the synchronizer and then sent to the system interface.
1452  *----------------------------------------------------------------------------
1453  */
1454 static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1455 {
1456         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1457         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1458         falc_t *pfalc = (falc_t *) & chan->falc;
1459         void __iomem *falcbase = card->hw.falcbase;
1460
1461         if (loop_on) {
1462                 // EVENT_FALC_ABNORMAL
1463                 if (conf->media == IF_IFACE_T1) {
1464                         /* Disable this interrupt as it may otherwise interfere with
1465                          * other working boards. */
1466                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1467                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1468                 }
1469                 falc_disable_comm(card, ch);
1470                 // EVENT_FALC_ABNORMAL
1471                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1472                            cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1473                 pfalc->loop_active = 1;
1474         } else {
1475                 cpc_writeb(falcbase + F_REG(LIM1, ch),
1476                            cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1477                 pfalc->sync = 0;
1478                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1479                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1480                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1481                 pfalc->active = 0;
1482                 falc_issue_cmd(card, ch, CMDR_XRES);
1483                 pfalc->loop_active = 0;
1484         }
1485 }
1486
1487 /*----------------------------------------------------------------------------
1488  * falc_local_loop
1489  *----------------------------------------------------------------------------
1490  * Description: The local loopback mode disconnects the receive lines
1491  *              RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1492  *              signals coming from the line the data provided by system
1493  *              interface are routed through the analog receiver back to
1494  *              the system interface. The unipolar bit stream will be
1495  *              undisturbed transmitted on the line. Receiver and transmitter
1496  *              coding must be identical.
1497  *----------------------------------------------------------------------------
1498  */
1499 static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1500 {
1501         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1502         falc_t *pfalc = (falc_t *) & chan->falc;
1503         void __iomem *falcbase = card->hw.falcbase;
1504
1505         if (loop_on) {
1506                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1507                            cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1508                 pfalc->loop_active = 1;
1509         } else {
1510                 cpc_writeb(falcbase + F_REG(LIM0, ch),
1511                            cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1512                 pfalc->loop_active = 0;
1513         }
1514 }
1515
1516 /*----------------------------------------------------------------------------
1517  * falc_payload_loop
1518  *----------------------------------------------------------------------------
1519  * Description: This routine allows to enable/disable payload loopback.
1520  *              When the payload loop is activated, the received 192 bits
1521  *              of payload data will be looped back to the transmit
1522  *              direction. The framing bits, CRC6 and DL bits are not
1523  *              looped. They are originated by the FALC-LH transmitter.
1524  *----------------------------------------------------------------------------
1525  */
1526 static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1527 {
1528         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1529         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1530         falc_t *pfalc = (falc_t *) & chan->falc;
1531         void __iomem *falcbase = card->hw.falcbase;
1532
1533         if (loop_on) {
1534                 // EVENT_FALC_ABNORMAL
1535                 if (conf->media == IF_IFACE_T1) {
1536                         /* Disable this interrupt as it may otherwise interfere with
1537                          * other working boards. */
1538                         cpc_writeb(falcbase + F_REG(IMR0, ch),
1539                                    cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1540                 }
1541                 falc_disable_comm(card, ch);
1542                 // EVENT_FALC_ABNORMAL
1543                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1544                            cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1545                 if (conf->media == IF_IFACE_T1) {
1546                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1547                                    cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1548                 } else {
1549                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1550                                    cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1551                 }
1552                 falc_open_all_timeslots(card, ch);
1553                 pfalc->loop_active = 2;
1554         } else {
1555                 cpc_writeb(falcbase + F_REG(FMR2, ch),
1556                            cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1557                 if (conf->media == IF_IFACE_T1) {
1558                         cpc_writeb(falcbase + F_REG(FMR4, ch),
1559                                    cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1560                 } else {
1561                         cpc_writeb(falcbase + F_REG(FMR5, ch),
1562                                    cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1563                 }
1564                 pfalc->sync = 0;
1565                 cpc_writeb(falcbase + card->hw.cpld_reg2,
1566                            cpc_readb(falcbase + card->hw.cpld_reg2) &
1567                            ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1568                 pfalc->active = 0;
1569                 falc_issue_cmd(card, ch, CMDR_XRES);
1570                 pfalc->loop_active = 0;
1571         }
1572 }
1573
1574 /*----------------------------------------------------------------------------
1575  * turn_off_xlu
1576  *----------------------------------------------------------------------------
1577  * Description: Turns XLU bit off in the proper register
1578  *----------------------------------------------------------------------------
1579  */
1580 static void turn_off_xlu(pc300_t * card, int ch)
1581 {
1582         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1583         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1584         void __iomem *falcbase = card->hw.falcbase;
1585
1586         if (conf->media == IF_IFACE_T1) {
1587                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1588                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1589         } else {
1590                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1591                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1592         }
1593 }
1594
1595 /*----------------------------------------------------------------------------
1596  * turn_off_xld
1597  *----------------------------------------------------------------------------
1598  * Description: Turns XLD bit off in the proper register
1599  *----------------------------------------------------------------------------
1600  */
1601 static void turn_off_xld(pc300_t * card, int ch)
1602 {
1603         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1604         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1605         void __iomem *falcbase = card->hw.falcbase;
1606
1607         if (conf->media == IF_IFACE_T1) {
1608                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1609                            cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1610         } else {
1611                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1612                            cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1613         }
1614 }
1615
1616 /*----------------------------------------------------------------------------
1617  * falc_generate_loop_up_code
1618  *----------------------------------------------------------------------------
1619  * Description: This routine writes the proper FALC chip register in order
1620  *              to generate a LOOP activation code over a T1/E1 line.
1621  *----------------------------------------------------------------------------
1622  */
1623 static void falc_generate_loop_up_code(pc300_t * card, int ch)
1624 {
1625         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1626         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1627         falc_t *pfalc = (falc_t *) & chan->falc;
1628         void __iomem *falcbase = card->hw.falcbase;
1629
1630         if (conf->media == IF_IFACE_T1) {
1631                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1632                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1633         } else {
1634                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1635                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1636         }
1637         // EVENT_FALC_ABNORMAL
1638         if (conf->media == IF_IFACE_T1) {
1639                 /* Disable this interrupt as it may otherwise interfere with
1640                  * other working boards. */
1641                 cpc_writeb(falcbase + F_REG(IMR0, ch),
1642                            cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1643         }
1644         falc_disable_comm(card, ch);
1645         // EVENT_FALC_ABNORMAL
1646         pfalc->loop_gen = 1;
1647 }
1648
1649 /*----------------------------------------------------------------------------
1650  * falc_generate_loop_down_code
1651  *----------------------------------------------------------------------------
1652  * Description: This routine writes the proper FALC chip register in order
1653  *              to generate a LOOP deactivation code over a T1/E1 line.
1654  *----------------------------------------------------------------------------
1655  */
1656 static void falc_generate_loop_down_code(pc300_t * card, int ch)
1657 {
1658         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1659         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1660         falc_t *pfalc = (falc_t *) & chan->falc;
1661         void __iomem *falcbase = card->hw.falcbase;
1662
1663         if (conf->media == IF_IFACE_T1) {
1664                 cpc_writeb(falcbase + F_REG(FMR5, ch),
1665                            cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1666         } else {
1667                 cpc_writeb(falcbase + F_REG(FMR3, ch),
1668                            cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1669         }
1670         pfalc->sync = 0;
1671         cpc_writeb(falcbase + card->hw.cpld_reg2,
1672                    cpc_readb(falcbase + card->hw.cpld_reg2) &
1673                    ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1674         pfalc->active = 0;
1675 //?    falc_issue_cmd(card, ch, CMDR_XRES);
1676         pfalc->loop_gen = 0;
1677 }
1678
1679 /*----------------------------------------------------------------------------
1680  * falc_pattern_test
1681  *----------------------------------------------------------------------------
1682  * Description: This routine generates a pattern code and checks
1683  *              it on the reception side.
1684  *----------------------------------------------------------------------------
1685  */
1686 static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1687 {
1688         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1689         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1690         falc_t *pfalc = (falc_t *) & chan->falc;
1691         void __iomem *falcbase = card->hw.falcbase;
1692
1693         if (activate) {
1694                 pfalc->prbs = 1;
1695                 pfalc->bec = 0;
1696                 if (conf->media == IF_IFACE_T1) {
1697                         /* Disable local loop activation/deactivation detect */
1698                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1699                                    cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1700                 } else {
1701                         /* Disable local loop activation/deactivation detect */
1702                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1703                                    cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1704                 }
1705                 /* Activates generation and monitoring of PRBS
1706                  * (Pseudo Random Bit Sequence) */
1707                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1708                            cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1709         } else {
1710                 pfalc->prbs = 0;
1711                 /* Deactivates generation and monitoring of PRBS
1712                  * (Pseudo Random Bit Sequence) */
1713                 cpc_writeb(falcbase + F_REG(LCR1, ch),
1714                            cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1715                 if (conf->media == IF_IFACE_T1) {
1716                         /* Enable local loop activation/deactivation detect */
1717                         cpc_writeb(falcbase + F_REG(IMR3, ch),
1718                                    cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1719                 } else {
1720                         /* Enable local loop activation/deactivation detect */
1721                         cpc_writeb(falcbase + F_REG(IMR1, ch),
1722                                    cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1723                 }
1724         }
1725 }
1726
1727 /*----------------------------------------------------------------------------
1728  * falc_pattern_test_error
1729  *----------------------------------------------------------------------------
1730  * Description: This routine returns the bit error counter value
1731  *----------------------------------------------------------------------------
1732  */
1733 static u16 falc_pattern_test_error(pc300_t * card, int ch)
1734 {
1735         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1736         falc_t *pfalc = (falc_t *) & chan->falc;
1737
1738         return pfalc->bec;
1739 }
1740
1741 /**********************************/
1742 /***   Net Interface Routines   ***/
1743 /**********************************/
1744
1745 static void
1746 cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1747 {
1748         struct sk_buff *skb;
1749
1750         if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1751                 printk("%s: out of memory\n", dev->name);
1752                 return;
1753         }
1754         skb_put(skb, 10 + skb_main->len);
1755
1756         skb->dev = dev;
1757         skb->protocol = htons(ETH_P_CUST);
1758         skb_reset_mac_header(skb);
1759         skb->pkt_type = PACKET_HOST;
1760         skb->len = 10 + skb_main->len;
1761
1762         skb_copy_to_linear_data(skb, dev->name, 5);
1763         skb->data[5] = '[';
1764         skb->data[6] = rx_tx;
1765         skb->data[7] = ']';
1766         skb->data[8] = ':';
1767         skb->data[9] = ' ';
1768         skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1769
1770         netif_rx(skb);
1771 }
1772
1773 static void cpc_tx_timeout(struct net_device *dev)
1774 {
1775         pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1776         pc300ch_t *chan = (pc300ch_t *) d->chan;
1777         pc300_t *card = (pc300_t *) chan->card;
1778         int ch = chan->channel;
1779         unsigned long flags;
1780         u8 ilar;
1781
1782         dev->stats.tx_errors++;
1783         dev->stats.tx_aborted_errors++;
1784         CPC_LOCK(card, flags);
1785         if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1786                 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1787                 cpc_writeb(card->hw.scabase + ILAR, ilar);
1788                 cpc_writeb(card->hw.scabase + DMER, 0x80);
1789         }
1790         if (card->hw.type == PC300_TE) {
1791                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1792                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1793                            ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1794         }
1795         dev->trans_start = jiffies; /* prevent tx timeout */
1796         CPC_UNLOCK(card, flags);
1797         netif_wake_queue(dev);
1798 }
1799
1800 static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1801 {
1802         pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1803         pc300ch_t *chan = (pc300ch_t *) d->chan;
1804         pc300_t *card = (pc300_t *) chan->card;
1805         int ch = chan->channel;
1806         unsigned long flags;
1807 #ifdef PC300_DEBUG_TX
1808         int i;
1809 #endif
1810
1811         if (!netif_carrier_ok(dev)) {
1812                 /* DCD must be OFF: drop packet */
1813                 dev_kfree_skb(skb);
1814                 dev->stats.tx_errors++;
1815                 dev->stats.tx_carrier_errors++;
1816                 return 0;
1817         } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1818                 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1819                 dev->stats.tx_errors++;
1820                 dev->stats.tx_carrier_errors++;
1821                 dev_kfree_skb(skb);
1822                 netif_carrier_off(dev);
1823                 CPC_LOCK(card, flags);
1824                 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1825                 if (card->hw.type == PC300_TE) {
1826                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1827                                    cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1828                                                         ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1829                 }
1830                 CPC_UNLOCK(card, flags);
1831                 netif_wake_queue(dev);
1832                 return 0;
1833         }
1834
1835         /* Write buffer to DMA buffers */
1836         if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
1837 //              printk("%s: write error. Dropping TX packet.\n", dev->name);
1838                 netif_stop_queue(dev);
1839                 dev_kfree_skb(skb);
1840                 dev->stats.tx_errors++;
1841                 dev->stats.tx_dropped++;
1842                 return 0;
1843         }
1844 #ifdef PC300_DEBUG_TX
1845         printk("%s T:", dev->name);
1846         for (i = 0; i < skb->len; i++)
1847                 printk(" %02x", *(skb->data + i));
1848         printk("\n");
1849 #endif
1850
1851         if (d->trace_on) {
1852                 cpc_trace(dev, skb, 'T');
1853         }
1854
1855         /* Start transmission */
1856         CPC_LOCK(card, flags);
1857         /* verify if it has more than one free descriptor */
1858         if (card->chan[ch].nfree_tx_bd <= 1) {
1859                 /* don't have so stop the queue */
1860                 netif_stop_queue(dev);
1861         }
1862         cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1863                    TX_BD_ADDR(ch, chan->tx_next_bd));
1864         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1865         cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1866         if (card->hw.type == PC300_TE) {
1867                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1868                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1869                            (CPLD_REG2_FALC_LED1 << (2 * ch)));
1870         }
1871         CPC_UNLOCK(card, flags);
1872         dev_kfree_skb(skb);
1873
1874         return 0;
1875 }
1876
1877 static void cpc_net_rx(struct net_device *dev)
1878 {
1879         pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1880         pc300ch_t *chan = (pc300ch_t *) d->chan;
1881         pc300_t *card = (pc300_t *) chan->card;
1882         int ch = chan->channel;
1883 #ifdef PC300_DEBUG_RX
1884         int i;
1885 #endif
1886         int rxb;
1887         struct sk_buff *skb;
1888
1889         while (1) {
1890                 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1891                         return;
1892
1893                 if (!netif_carrier_ok(dev)) {
1894                         /* DCD must be OFF: drop packet */
1895                     printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1896                         skb = NULL;
1897                 } else {
1898                         if (rxb > (dev->mtu + 40)) { /* add headers */
1899                                 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1900                                 skb = NULL;
1901                         } else {
1902                                 skb = dev_alloc_skb(rxb);
1903                                 if (skb == NULL) {
1904                                         printk("%s: Memory squeeze!!\n", dev->name);
1905                                         return;
1906                                 }
1907                                 skb->dev = dev;
1908                         }
1909                 }
1910
1911                 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1912 #ifdef PC300_DEBUG_RX
1913                         printk("%s: rxb = %x\n", dev->name, rxb);
1914 #endif
1915                         if ((skb == NULL) && (rxb > 0)) {
1916                                 /* rxb > dev->mtu */
1917                                 dev->stats.rx_errors++;
1918                                 dev->stats.rx_length_errors++;
1919                                 continue;
1920                         }
1921
1922                         if (rxb < 0) {  /* Invalid frame */
1923                                 rxb = -rxb;
1924                                 if (rxb & DST_OVR) {
1925                                         dev->stats.rx_errors++;
1926                                         dev->stats.rx_fifo_errors++;
1927                                 }
1928                                 if (rxb & DST_CRC) {
1929                                         dev->stats.rx_errors++;
1930                                         dev->stats.rx_crc_errors++;
1931                                 }
1932                                 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1933                                         dev->stats.rx_errors++;
1934                                         dev->stats.rx_frame_errors++;
1935                                 }
1936                         }
1937                         if (skb) {
1938                                 dev_kfree_skb_irq(skb);
1939                         }
1940                         continue;
1941                 }
1942
1943                 dev->stats.rx_bytes += rxb;
1944
1945 #ifdef PC300_DEBUG_RX
1946                 printk("%s R:", dev->name);
1947                 for (i = 0; i < skb->len; i++)
1948                         printk(" %02x", *(skb->data + i));
1949                 printk("\n");
1950 #endif
1951                 if (d->trace_on) {
1952                         cpc_trace(dev, skb, 'R');
1953                 }
1954                 dev->stats.rx_packets++;
1955                 skb->protocol = hdlc_type_trans(skb, dev);
1956                 netif_rx(skb);
1957         }
1958 }
1959
1960 /************************************/
1961 /***   PC300 Interrupt Routines   ***/
1962 /************************************/
1963 static void sca_tx_intr(pc300dev_t *dev)
1964 {
1965         pc300ch_t *chan = (pc300ch_t *)dev->chan;
1966         pc300_t *card = (pc300_t *)chan->card;
1967         int ch = chan->channel;
1968         volatile pcsca_bd_t __iomem * ptdescr;
1969
1970     /* Clean up descriptors from previous transmission */
1971         ptdescr = (card->hw.rambase +
1972                                                 TX_BD_ADDR(ch,chan->tx_first_bd));
1973         while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1974                 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1975                (cpc_readb(&ptdescr->status) & DST_OSB)) {
1976                 dev->dev->stats.tx_packets++;
1977                 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1978                 cpc_writeb(&ptdescr->status, DST_OSB);
1979                 cpc_writew(&ptdescr->len, 0);
1980                 chan->nfree_tx_bd++;
1981                 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1982                 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1983     }
1984
1985 #ifdef CONFIG_PC300_MLPPP
1986         if (chan->conf.proto == PC300_PROTO_MLPPP) {
1987                         cpc_tty_trigger_poll(dev);
1988         } else {
1989 #endif
1990         /* Tell the upper layer we are ready to transmit more packets */
1991                 netif_wake_queue(dev->dev);
1992 #ifdef CONFIG_PC300_MLPPP
1993         }
1994 #endif
1995 }
1996
1997 static void sca_intr(pc300_t * card)
1998 {
1999         void __iomem *scabase = card->hw.scabase;
2000         volatile u32 status;
2001         int ch;
2002         int intr_count = 0;
2003         unsigned char dsr_rx;
2004
2005         while ((status = cpc_readl(scabase + ISR0)) != 0) {
2006                 for (ch = 0; ch < card->hw.nchan; ch++) {
2007                         pc300ch_t *chan = &card->chan[ch];
2008                         pc300dev_t *d = &chan->d;
2009                         struct net_device *dev = d->dev;
2010
2011                         spin_lock(&card->card_lock);
2012
2013             /**** Reception ****/
2014                         if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2015                                 u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
2016
2017                                 /* Clear RX interrupts */
2018                                 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2019
2020 #ifdef PC300_DEBUG_INTR
2021                                 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2022                                          ch, status, drx_stat);
2023 #endif
2024                                 if (status & IR0_DRX(IR0_DMIA, ch)) {
2025                                         if (drx_stat & DSR_BOF) {
2026 #ifdef CONFIG_PC300_MLPPP
2027                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2028                                                         /* verify if driver is TTY */
2029                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2030                                                                 rx_dma_stop(card, ch);
2031                                                         }
2032                                                         cpc_tty_receive(d);
2033                                                         rx_dma_start(card, ch);
2034                                                 } else
2035 #endif
2036                                                 {
2037                                                         if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2038                                                                 rx_dma_stop(card, ch);
2039                                                         }
2040                                                         cpc_net_rx(dev);
2041                                                         /* Discard invalid frames */
2042                                                         dev->stats.rx_errors++;
2043                                                         dev->stats.rx_over_errors++;
2044                                                         chan->rx_first_bd = 0;
2045                                                         chan->rx_last_bd = N_DMA_RX_BUF - 1;
2046                                                         rx_dma_start(card, ch);
2047                                                 }
2048                                         }
2049                                 }
2050                                 if (status & IR0_DRX(IR0_DMIB, ch)) {
2051                                         if (drx_stat & DSR_EOM) {
2052                                                 if (card->hw.type == PC300_TE) {
2053                                                         cpc_writeb(card->hw.falcbase +
2054                                                                    card->hw.cpld_reg2,
2055                                                                    cpc_readb (card->hw.falcbase +
2056                                                                         card->hw.cpld_reg2) |
2057                                                                    (CPLD_REG2_FALC_LED1 << (2 * ch)));
2058                                                 }
2059 #ifdef CONFIG_PC300_MLPPP
2060                                                 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2061                                                         /* verify if driver is TTY */
2062                                                         cpc_tty_receive(d);
2063                                                 } else {
2064                                                         cpc_net_rx(dev);
2065                                                 }
2066 #else
2067                                                 cpc_net_rx(dev);
2068 #endif
2069                                                 if (card->hw.type == PC300_TE) {
2070                                                         cpc_writeb(card->hw.falcbase +
2071                                                                    card->hw.cpld_reg2,
2072                                                                    cpc_readb (card->hw.falcbase +
2073                                                                                 card->hw.cpld_reg2) &
2074                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2075                                                 }
2076                                         }
2077                                 }
2078                                 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2079 #ifdef PC300_DEBUG_INTR
2080                 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2081                         dev->name, ch, status, drx_stat, dsr_rx);
2082 #endif
2083                                         cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2084                                 }
2085                         }
2086
2087             /**** Transmission ****/
2088                         if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2089                                 u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2090
2091                                 /* Clear TX interrupts */
2092                                 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2093
2094 #ifdef PC300_DEBUG_INTR
2095                                 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2096                                          ch, status, dtx_stat);
2097 #endif
2098                                 if (status & IR0_DTX(IR0_EFT, ch)) {
2099                                         if (dtx_stat & DSR_UDRF) {
2100                                                 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2101                                                         cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2102                                                 }
2103                                                 if (card->hw.type == PC300_TE) {
2104                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2105                                                                    cpc_readb (card->hw.falcbase +
2106                                                                                    card->hw.cpld_reg2) &
2107                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2108                                                 }
2109                                                 dev->stats.tx_errors++;
2110                                                 dev->stats.tx_fifo_errors++;
2111                                                 sca_tx_intr(d);
2112                                         }
2113                                 }
2114                                 if (status & IR0_DTX(IR0_DMIA, ch)) {
2115                                         if (dtx_stat & DSR_BOF) {
2116                                         }
2117                                 }
2118                                 if (status & IR0_DTX(IR0_DMIB, ch)) {
2119                                         if (dtx_stat & DSR_EOM) {
2120                                                 if (card->hw.type == PC300_TE) {
2121                                                         cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2122                                                                    cpc_readb (card->hw.falcbase +
2123                                                                                         card->hw.cpld_reg2) &
2124                                                                    ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2125                                                 }
2126                                                 sca_tx_intr(d);
2127                                         }
2128                                 }
2129                         }
2130
2131             /**** MSCI ****/
2132                         if (status & IR0_M(IR0_RXINTA, ch)) {
2133                                 u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
2134
2135                                 /* Clear MSCI interrupts */
2136                                 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2137
2138 #ifdef PC300_DEBUG_INTR
2139                                 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2140                                          ch, status, st1);
2141 #endif
2142                                 if (st1 & ST1_CDCD) {   /* DCD changed */
2143                                         if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2144                                                 printk ("%s: DCD is OFF. Going administrative down.\n",
2145                                                          dev->name);
2146 #ifdef CONFIG_PC300_MLPPP
2147                                                 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2148                                                         netif_carrier_off(dev);
2149                                                 }
2150 #else
2151                                                 netif_carrier_off(dev);
2152
2153 #endif
2154                                                 card->chan[ch].d.line_off++;
2155                                         } else {        /* DCD = 1 */
2156                                                 printk ("%s: DCD is ON. Going administrative up.\n",
2157                                                          dev->name);
2158 #ifdef CONFIG_PC300_MLPPP
2159                                                 if (chan->conf.proto != PC300_PROTO_MLPPP)
2160                                                         /* verify if driver is not TTY */
2161 #endif
2162                                                         netif_carrier_on(dev);
2163                                                 card->chan[ch].d.line_on++;
2164                                         }
2165                                 }
2166                         }
2167                         spin_unlock(&card->card_lock);
2168                 }
2169                 if (++intr_count == 10)
2170                         /* Too much work at this board. Force exit */
2171                         break;
2172         }
2173 }
2174
2175 static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
2176 {
2177         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2178         falc_t *pfalc = (falc_t *) & chan->falc;
2179         void __iomem *falcbase = card->hw.falcbase;
2180
2181         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2182             !pfalc->loop_gen) {
2183                 if (frs1 & FRS1_LLBDD) {
2184                         // A Line Loop Back Deactivation signal detected
2185                         if (pfalc->loop_active) {
2186                                 falc_remote_loop(card, ch, 0);
2187                         }
2188                 } else {
2189                         if ((frs1 & FRS1_LLBAD) &&
2190                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2191                                 // A Line Loop Back Activation signal detected
2192                                 if (!pfalc->loop_active) {
2193                                         falc_remote_loop(card, ch, 1);
2194                                 }
2195                         }
2196                 }
2197         }
2198 }
2199
2200 static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
2201 {
2202         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2203         falc_t *pfalc = (falc_t *) & chan->falc;
2204         void __iomem *falcbase = card->hw.falcbase;
2205
2206         if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2207             !pfalc->loop_gen) {
2208                 if (rsp & RSP_LLBDD) {
2209                         // A Line Loop Back Deactivation signal detected
2210                         if (pfalc->loop_active) {
2211                                 falc_remote_loop(card, ch, 0);
2212                         }
2213                 } else {
2214                         if ((rsp & RSP_LLBAD) &&
2215                             ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2216                                 // A Line Loop Back Activation signal detected
2217                                 if (!pfalc->loop_active) {
2218                                         falc_remote_loop(card, ch, 1);
2219                                 }
2220                         }
2221                 }
2222         }
2223 }
2224
2225 static void falc_t1_intr(pc300_t * card, int ch)
2226 {
2227         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2228         falc_t *pfalc = (falc_t *) & chan->falc;
2229         void __iomem *falcbase = card->hw.falcbase;
2230         u8 isr0, isr3, gis;
2231         u8 dummy;
2232
2233         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2234                 if (gis & GIS_ISR0) {
2235                         isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2236                         if (isr0 & FISR0_PDEN) {
2237                                 /* Read the bit to clear the situation */
2238                                 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2239                                     FRS1_PDEN) {
2240                                         pfalc->pden++;
2241                                 }
2242                         }
2243                 }
2244
2245                 if (gis & GIS_ISR1) {
2246                         dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2247                 }
2248
2249                 if (gis & GIS_ISR2) {
2250                         dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2251                 }
2252
2253                 if (gis & GIS_ISR3) {
2254                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2255                         if (isr3 & FISR3_SEC) {
2256                                 pfalc->sec++;
2257                                 falc_update_stats(card, ch);
2258                                 falc_check_status(card, ch,
2259                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2260                         }
2261                         if (isr3 & FISR3_ES) {
2262                                 pfalc->es++;
2263                         }
2264                         if (isr3 & FISR3_LLBSC) {
2265                                 falc_t1_loop_detection(card, ch,
2266                                                        cpc_readb(falcbase + F_REG(FRS1, ch)));
2267                         }
2268                 }
2269         }
2270 }
2271
2272 static void falc_e1_intr(pc300_t * card, int ch)
2273 {
2274         pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2275         falc_t *pfalc = (falc_t *) & chan->falc;
2276         void __iomem *falcbase = card->hw.falcbase;
2277         u8 isr1, isr2, isr3, gis, rsp;
2278         u8 dummy;
2279
2280         while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2281                 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2282
2283                 if (gis & GIS_ISR0) {
2284                         dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2285                 }
2286                 if (gis & GIS_ISR1) {
2287                         isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2288                         if (isr1 & FISR1_XMB) {
2289                                 if ((pfalc->xmb_cause & 2) &&
2290                                     pfalc->multiframe_mode) {
2291                                         if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2292                                                                         (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2293                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2294                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2295                                                            & ~XSP_AXS);
2296                                         } else {
2297                                                 cpc_writeb(falcbase + F_REG(XSP, ch),
2298                                                            cpc_readb(falcbase + F_REG(XSP, ch))
2299                                                            | XSP_AXS);
2300                                         }
2301                                 }
2302                                 pfalc->xmb_cause = 0;
2303                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2304                                            cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2305                         }
2306                         if (isr1 & FISR1_LLBSC) {
2307                                 falc_e1_loop_detection(card, ch, rsp);
2308                         }
2309                 }
2310                 if (gis & GIS_ISR2) {
2311                         isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2312                         if (isr2 & FISR2_T400MS) {
2313                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2314                                            cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2315                         }
2316                         if (isr2 & FISR2_MFAR) {
2317                                 cpc_writeb(falcbase + F_REG(XSW, ch),
2318                                            cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2319                         }
2320                         if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2321                                 pfalc->xmb_cause |= 2;
2322                                 cpc_writeb(falcbase + F_REG(IMR1, ch),
2323                                            cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2324                         }
2325                 }
2326                 if (gis & GIS_ISR3) {
2327                         isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2328                         if (isr3 & FISR3_SEC) {
2329                                 pfalc->sec++;
2330                                 falc_update_stats(card, ch);
2331                                 falc_check_status(card, ch,
2332                                                   cpc_readb(falcbase + F_REG(FRS0, ch)));
2333                         }
2334                         if (isr3 & FISR3_ES) {
2335                                 pfalc->es++;
2336                         }
2337                 }
2338         }
2339 }
2340
2341 static void falc_intr(pc300_t * card)
2342 {
2343         int ch;
2344
2345         for (ch = 0; ch < card->hw.nchan; ch++) {
2346                 pc300ch_t *chan = &card->chan[ch];
2347                 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2348
2349                 if (conf->media == IF_IFACE_T1) {
2350                         falc_t1_intr(card, ch);
2351                 } else {
2352                         falc_e1_intr(card, ch);
2353                 }
2354         }
2355 }
2356
2357 static irqreturn_t cpc_intr(int irq, void *dev_id)
2358 {
2359         pc300_t *card = dev_id;
2360         volatile u8 plx_status;
2361
2362         if (!card) {
2363 #ifdef PC300_DEBUG_INTR
2364                 printk("cpc_intr: spurious intr %d\n", irq);
2365 #endif
2366                 return IRQ_NONE;                /* spurious intr */
2367         }
2368
2369         if (!card->hw.rambase) {
2370 #ifdef PC300_DEBUG_INTR
2371                 printk("cpc_intr: spurious intr2 %d\n", irq);
2372 #endif
2373                 return IRQ_NONE;                /* spurious intr */
2374         }
2375
2376         switch (card->hw.type) {
2377                 case PC300_RSV:
2378                 case PC300_X21:
2379                         sca_intr(card);
2380                         break;
2381
2382                 case PC300_TE:
2383                         while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2384                                  (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2385                                 if (plx_status & PLX_9050_LINT1_STATUS) {       /* SCA Interrupt */
2386                                         sca_intr(card);
2387                                 }
2388                                 if (plx_status & PLX_9050_LINT2_STATUS) {       /* FALC Interrupt */
2389                                         falc_intr(card);
2390                                 }
2391                         }
2392                         break;
2393         }
2394         return IRQ_HANDLED;
2395 }
2396
2397 static void cpc_sca_status(pc300_t * card, int ch)
2398 {
2399         u8 ilar;
2400         void __iomem *scabase = card->hw.scabase;
2401         unsigned long flags;
2402
2403         tx_dma_buf_check(card, ch);
2404         rx_dma_buf_check(card, ch);
2405         ilar = cpc_readb(scabase + ILAR);
2406         printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2407                  ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2408                  cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2409         printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2410                cpc_readl(scabase + DTX_REG(CDAL, ch)),
2411                cpc_readl(scabase + DTX_REG(EDAL, ch)));
2412         printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2413                cpc_readl(scabase + DRX_REG(CDAL, ch)),
2414                cpc_readl(scabase + DRX_REG(EDAL, ch)),
2415                cpc_readw(scabase + DRX_REG(BFLL, ch)));
2416         printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2417                cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2418                cpc_readb(scabase + DSR_RX(ch)));
2419         printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2420                cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2421                cpc_readb(scabase + DIR_TX(ch)),
2422                cpc_readb(scabase + DIR_RX(ch)));
2423         printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2424                cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2425                cpc_readb(scabase + FCT_TX(ch)),
2426                cpc_readb(scabase + FCT_RX(ch)));
2427         printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2428                cpc_readb(scabase + M_REG(MD0, ch)),
2429                cpc_readb(scabase + M_REG(MD1, ch)),
2430                cpc_readb(scabase + M_REG(MD2, ch)),
2431                cpc_readb(scabase + M_REG(MD3, ch)),
2432                cpc_readb(scabase + M_REG(IDL, ch)));
2433         printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2434                cpc_readb(scabase + M_REG(CMD, ch)),
2435                cpc_readb(scabase + M_REG(SA0, ch)),
2436                cpc_readb(scabase + M_REG(SA1, ch)),
2437                cpc_readb(scabase + M_REG(TFN, ch)),
2438                cpc_readb(scabase + M_REG(CTL, ch)));
2439         printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2440                cpc_readb(scabase + M_REG(ST0, ch)),
2441                cpc_readb(scabase + M_REG(ST1, ch)),
2442                cpc_readb(scabase + M_REG(ST2, ch)),
2443                cpc_readb(scabase + M_REG(ST3, ch)),
2444                cpc_readb(scabase + M_REG(ST4, ch)));
2445         printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2446                  cpc_readb(scabase + M_REG(CST0, ch)),
2447                  cpc_readb(scabase + M_REG(CST1, ch)),
2448                  cpc_readb(scabase + M_REG(CST2, ch)),
2449                  cpc_readb(scabase + M_REG(CST3, ch)),
2450                  cpc_readb(scabase + M_REG(FST, ch)));
2451         printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2452                cpc_readb(scabase + M_REG(TRC0, ch)),
2453                cpc_readb(scabase + M_REG(TRC1, ch)),
2454                cpc_readb(scabase + M_REG(RRC, ch)),
2455                cpc_readb(scabase + M_REG(TBN, ch)),
2456                cpc_readb(scabase + M_REG(RBN, ch)));
2457         printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2458                cpc_readb(scabase + M_REG(TFS, ch)),
2459                cpc_readb(scabase + M_REG(TNR0, ch)),
2460                cpc_readb(scabase + M_REG(TNR1, ch)),
2461                cpc_readb(scabase + M_REG(RNR, ch)));
2462         printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2463                cpc_readb(scabase + M_REG(TCR, ch)),
2464                cpc_readb(scabase + M_REG(RCR, ch)),
2465                cpc_readb(scabase + M_REG(TNR1, ch)),
2466                cpc_readb(scabase + M_REG(RNR, ch)));
2467         printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2468                cpc_readb(scabase + M_REG(TXS, ch)),
2469                cpc_readb(scabase + M_REG(RXS, ch)),
2470                cpc_readb(scabase + M_REG(EXS, ch)),
2471                cpc_readb(scabase + M_REG(TMCT, ch)),
2472                cpc_readb(scabase + M_REG(TMCR, ch)));
2473         printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2474                cpc_readb(scabase + M_REG(IE0, ch)),
2475                cpc_readb(scabase + M_REG(IE1, ch)),
2476                cpc_readb(scabase + M_REG(IE2, ch)),
2477                cpc_readb(scabase + M_REG(IE4, ch)),
2478                cpc_readb(scabase + M_REG(FIE, ch)));
2479         printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2480
2481         if (ilar != 0) {
2482                 CPC_LOCK(card, flags);
2483                 cpc_writeb(scabase + ILAR, ilar);
2484                 cpc_writeb(scabase + DMER, 0x80);
2485                 CPC_UNLOCK(card, flags);
2486         }
2487 }
2488
2489 static void cpc_falc_status(pc300_t * card, int ch)
2490 {
2491         pc300ch_t *chan = &card->chan[ch];
2492         falc_t *pfalc = (falc_t *) & chan->falc;
2493         unsigned long flags;
2494
2495         CPC_LOCK(card, flags);
2496         printk("CH%d:   %s %s  %d channels\n",
2497                ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2498                pfalc->num_channels);
2499
2500         printk("        pden=%d,  los=%d,  losr=%d,  lfa=%d,  farec=%d\n",
2501                pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2502         printk("        lmfa=%d,  ais=%d,  sec=%d,  es=%d,  rai=%d\n",
2503                pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2504         printk("        bec=%d,  fec=%d,  cvc=%d,  cec=%d,  ebc=%d\n",
2505                pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2506
2507         printk("\n");
2508         printk("        STATUS: %s  %s  %s  %s  %s  %s\n",
2509                (pfalc->red_alarm ? "RED" : ""),
2510                (pfalc->blue_alarm ? "BLU" : ""),
2511                (pfalc->yellow_alarm ? "YEL" : ""),
2512                (pfalc->loss_fa ? "LFA" : ""),
2513                (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2514         CPC_UNLOCK(card, flags);
2515 }
2516
2517 static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2518 {
2519         if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2520                 return -EINVAL;
2521         dev->mtu = new_mtu;
2522         return 0;
2523 }
2524
2525 static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2526 {
2527         pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
2528         pc300ch_t *chan = (pc300ch_t *) d->chan;
2529         pc300_t *card = (pc300_t *) chan->card;
2530         pc300conf_t conf_aux;
2531         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2532         int ch = chan->channel;
2533         void __user *arg = ifr->ifr_data;
2534         struct if_settings *settings = &ifr->ifr_settings;
2535         void __iomem *scabase = card->hw.scabase;
2536
2537         if (!capable(CAP_NET_ADMIN))
2538                 return -EPERM;
2539
2540         switch (cmd) {
2541                 case SIOCGPC300CONF:
2542 #ifdef CONFIG_PC300_MLPPP
2543                         if (conf->proto != PC300_PROTO_MLPPP) {
2544                                 conf->proto = /* FIXME hdlc->proto.id */ 0;
2545                         }
2546 #else
2547                         conf->proto = /* FIXME hdlc->proto.id */ 0;
2548 #endif
2549                         memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2550                         memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2551                         if (!arg ||
2552                                 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2553                                 return -EINVAL;
2554                         return 0;
2555                 case SIOCSPC300CONF:
2556                         if (!capable(CAP_NET_ADMIN))
2557                                 return -EPERM;
2558                         if (!arg ||
2559                                 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2560                                 return -EINVAL;
2561                         if (card->hw.cpld_id < 0x02 &&
2562                             conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2563                                 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2564                                 return -EINVAL;
2565                         }
2566 #ifdef CONFIG_PC300_MLPPP
2567                         if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2568                                 if (conf->proto != PC300_PROTO_MLPPP) {
2569                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2570                                         cpc_tty_init(d);        /* init TTY driver */
2571                                 }
2572                         } else {
2573                                 if (conf_aux.conf.proto == 0xffff) {
2574                                         if (conf->proto == PC300_PROTO_MLPPP){
2575                                                 /* ifdown interface */
2576                                                 cpc_close(dev);
2577                                         }
2578                                 } else {
2579                                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2580                                         /* FIXME hdlc->proto.id = conf->proto; */
2581                                 }
2582                         }
2583 #else
2584                         memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2585                         /* FIXME hdlc->proto.id = conf->proto; */
2586 #endif
2587                         return 0;
2588                 case SIOCGPC300STATUS:
2589                         cpc_sca_status(card, ch);
2590                         return 0;
2591                 case SIOCGPC300FALCSTATUS:
2592                         cpc_falc_status(card, ch);
2593                         return 0;
2594
2595                 case SIOCGPC300UTILSTATS:
2596                         {
2597                                 if (!arg) {     /* clear statistics */
2598                                         memset(&dev->stats, 0, sizeof(dev->stats));
2599                                         if (card->hw.type == PC300_TE) {
2600                                                 memset(&chan->falc, 0, sizeof(falc_t));
2601                                         }
2602                                 } else {
2603                                         pc300stats_t pc300stats;
2604
2605                                         memset(&pc300stats, 0, sizeof(pc300stats_t));
2606                                         pc300stats.hw_type = card->hw.type;
2607                                         pc300stats.line_on = card->chan[ch].d.line_on;
2608                                         pc300stats.line_off = card->chan[ch].d.line_off;
2609                                         memcpy(&pc300stats.gen_stats, &dev->stats,
2610                                                sizeof(dev->stats));
2611                                         if (card->hw.type == PC300_TE)
2612                                                 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2613                                         if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2614                                                 return -EFAULT;
2615                                 }
2616                                 return 0;
2617                         }
2618
2619                 case SIOCGPC300UTILSTATUS:
2620                         {
2621                                 struct pc300status pc300status;
2622
2623                                 pc300status.hw_type = card->hw.type;
2624                                 if (card->hw.type == PC300_TE) {
2625                                         pc300status.te_status.sync = chan->falc.sync;
2626                                         pc300status.te_status.red_alarm = chan->falc.red_alarm;
2627                                         pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2628                                         pc300status.te_status.loss_fa = chan->falc.loss_fa;
2629                                         pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2630                                         pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2631                                         pc300status.te_status.prbs = chan->falc.prbs;
2632                                 } else {
2633                                         pc300status.gen_status.dcd =
2634                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2635                                         pc300status.gen_status.cts =
2636                                                 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2637                                         pc300status.gen_status.rts =
2638                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2639                                         pc300status.gen_status.dtr =
2640                                                 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2641                                         /* There is no DSR in HD64572 */
2642                                 }
2643                                 if (!arg ||
2644                                     copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2645                                         return -EINVAL;
2646                                 return 0;
2647                         }
2648
2649                 case SIOCSPC300TRACE:
2650                         /* Sets/resets a trace_flag for the respective device */
2651                         if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2652                                         return -EINVAL;
2653                         return 0;
2654
2655                 case SIOCSPC300LOOPBACK:
2656                         {
2657                                 struct pc300loopback pc300loop;
2658
2659                                 /* TE boards only */
2660                                 if (card->hw.type != PC300_TE)
2661                                         return -EINVAL;
2662
2663                                 if (!arg ||
2664                                         copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2665                                                 return -EINVAL;
2666                                 switch (pc300loop.loop_type) {
2667                                         case PC300LOCLOOP:      /* Turn the local loop on/off */
2668                                                 falc_local_loop(card, ch, pc300loop.loop_on);
2669                                                 return 0;
2670
2671                                         case PC300REMLOOP:      /* Turn the remote loop on/off */
2672                                                 falc_remote_loop(card, ch, pc300loop.loop_on);
2673                                                 return 0;
2674
2675                                         case PC300PAYLOADLOOP:  /* Turn the payload loop on/off */
2676                                                 falc_payload_loop(card, ch, pc300loop.loop_on);
2677                                                 return 0;
2678
2679                                         case PC300GENLOOPUP:    /* Generate loop UP */
2680                                                 if (pc300loop.loop_on) {
2681                                                         falc_generate_loop_up_code (card, ch);
2682                                                 } else {
2683                                                         turn_off_xlu(card, ch);
2684                                                 }
2685                                                 return 0;
2686
2687                                         case PC300GENLOOPDOWN:  /* Generate loop DOWN */
2688                                                 if (pc300loop.loop_on) {
2689                                                         falc_generate_loop_down_code (card, ch);
2690                                                 } else {
2691                                                         turn_off_xld(card, ch);
2692                                                 }
2693                                                 return 0;
2694
2695                                         default:
2696                                                 return -EINVAL;
2697                                 }
2698                         }
2699
2700                 case SIOCSPC300PATTERNTEST:
2701                         /* Turn the pattern test on/off and show the errors counter */
2702                         {
2703                                 struct pc300patterntst pc300patrntst;
2704
2705                                 /* TE boards only */
2706                                 if (card->hw.type != PC300_TE)
2707                                         return -EINVAL;
2708
2709                                 if (card->hw.cpld_id < 0x02) {
2710                                         /* CPLD_ID < 0x02 doesn't support pattern test */
2711                                         return -EINVAL;
2712                                 }
2713
2714                                 if (!arg ||
2715                                         copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2716                                                 return -EINVAL;
2717                                 if (pc300patrntst.patrntst_on == 2) {
2718                                         if (chan->falc.prbs == 0) {
2719                                                 falc_pattern_test(card, ch, 1);
2720                                         }
2721                                         pc300patrntst.num_errors =
2722                                                 falc_pattern_test_error(card, ch);
2723                                         if (copy_to_user(arg, &pc300patrntst,
2724                                                          sizeof(pc300patterntst_t)))
2725                                                         return -EINVAL;
2726                                 } else {
2727                                         falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2728                                 }
2729                                 return 0;
2730                         }
2731
2732                 case SIOCWANDEV:
2733                         switch (ifr->ifr_settings.type) {
2734                                 case IF_GET_IFACE:
2735                                 {
2736                                         const size_t size = sizeof(sync_serial_settings);
2737                                         ifr->ifr_settings.type = conf->media;
2738                                         if (ifr->ifr_settings.size < size) {
2739                                                 /* data size wanted */
2740                                                 ifr->ifr_settings.size = size;
2741                                                 return -ENOBUFS;
2742                                         }
2743
2744                                         if (copy_to_user(settings->ifs_ifsu.sync,
2745                                                          &conf->phys_settings, size)) {
2746                                                 return -EFAULT;
2747                                         }
2748                                         return 0;
2749                                 }
2750
2751                                 case IF_IFACE_V35:
2752                                 case IF_IFACE_V24:
2753                                 case IF_IFACE_X21:
2754                                 {
2755                                         const size_t size = sizeof(sync_serial_settings);
2756
2757                                         if (!capable(CAP_NET_ADMIN)) {
2758                                                 return -EPERM;
2759                                         }
2760                                         /* incorrect data len? */
2761                                         if (ifr->ifr_settings.size != size) {
2762                                                 return -ENOBUFS;
2763                                         }
2764
2765                                         if (copy_from_user(&conf->phys_settings,
2766                                                            settings->ifs_ifsu.sync, size)) {
2767                                                 return -EFAULT;
2768                                         }
2769
2770                                         if (conf->phys_settings.loopback) {
2771                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2772                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2773                                                         MD2_LOOP_MIR);
2774                                         }
2775                                         conf->media = ifr->ifr_settings.type;
2776                                         return 0;
2777                                 }
2778
2779                                 case IF_IFACE_T1:
2780                                 case IF_IFACE_E1:
2781                                 {
2782                                         const size_t te_size = sizeof(te1_settings);
2783                                         const size_t size = sizeof(sync_serial_settings);
2784
2785                                         if (!capable(CAP_NET_ADMIN)) {
2786                                                 return -EPERM;
2787                                         }
2788
2789                                         /* incorrect data len? */
2790                                         if (ifr->ifr_settings.size != te_size) {
2791                                                 return -ENOBUFS;
2792                                         }
2793
2794                                         if (copy_from_user(&conf->phys_settings,
2795                                                            settings->ifs_ifsu.te1, size)) {
2796                                                 return -EFAULT;
2797                                         }/* Ignoring HDLC slot_map for a while */
2798
2799                                         if (conf->phys_settings.loopback) {
2800                                                 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2801                                                         cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2802                                                         MD2_LOOP_MIR);
2803                                         }
2804                                         conf->media = ifr->ifr_settings.type;
2805                                         return 0;
2806                                 }
2807                                 default:
2808                                         return hdlc_ioctl(dev, ifr, cmd);
2809                         }
2810
2811                 default:
2812                         return hdlc_ioctl(dev, ifr, cmd);
2813         }
2814 }
2815
2816 static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
2817 {
2818         int br, tc;
2819         int br_pwr, error;
2820
2821         *br_io = 0;
2822
2823         if (rate == 0)
2824                 return 0;
2825
2826         for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2827                 if ((tc = clock / br_pwr / rate) <= 0xff) {
2828                         *br_io = br;
2829                         break;
2830                 }
2831         }
2832
2833         if (tc <= 0xff) {
2834                 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2835                 /* Errors bigger than +/- 1% won't be tolerated */
2836                 if (error < -10 || error > 10)
2837                         return -1;
2838                 else
2839                         return tc;
2840         } else {
2841                 return -1;
2842         }
2843 }
2844
2845 static int ch_config(pc300dev_t * d)
2846 {
2847         pc300ch_t *chan = (pc300ch_t *) d->chan;
2848         pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2849         pc300_t *card = (pc300_t *) chan->card;
2850         void __iomem *scabase = card->hw.scabase;
2851         void __iomem *plxbase = card->hw.plxbase;
2852         int ch = chan->channel;
2853         u32 clkrate = chan->conf.phys_settings.clock_rate;
2854         u32 clktype = chan->conf.phys_settings.clock_type;
2855         u16 encoding = chan->conf.proto_settings.encoding;
2856         u16 parity = chan->conf.proto_settings.parity;
2857         u8 md0, md2;
2858
2859         /* Reset the channel */
2860         cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2861
2862         /* Configure the SCA registers */
2863         switch (parity) {
2864                 case PARITY_NONE:
2865                         md0 = MD0_BIT_SYNC;
2866                         break;
2867                 case PARITY_CRC16_PR0:
2868                         md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2869                         break;
2870                 case PARITY_CRC16_PR1:
2871                         md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2872                         break;
2873                 case PARITY_CRC32_PR1_CCITT:
2874                         md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2875                         break;
2876                 case PARITY_CRC16_PR1_CCITT:
2877                 default:
2878                         md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2879                         break;
2880         }
2881         switch (encoding) {
2882                 case ENCODING_NRZI:
2883                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2884                         break;
2885                 case ENCODING_FM_MARK:  /* FM1 */
2886                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2887                         break;
2888                 case ENCODING_FM_SPACE: /* FM0 */
2889                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2890                         break;
2891                 case ENCODING_MANCHESTER: /* It's not working... */
2892                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2893                         break;
2894                 case ENCODING_NRZ:
2895                 default:
2896                         md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2897                         break;
2898         }
2899         cpc_writeb(scabase + M_REG(MD0, ch), md0);
2900         cpc_writeb(scabase + M_REG(MD1, ch), 0);
2901         cpc_writeb(scabase + M_REG(MD2, ch), md2);
2902         cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2903         cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2904
2905         /* Configure HW media */
2906         switch (card->hw.type) {
2907                 case PC300_RSV:
2908                         if (conf->media == IF_IFACE_V35) {
2909                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2910                                            cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2911                         } else {
2912                                 cpc_writel((plxbase + card->hw.gpioc_reg),
2913                                            cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2914                         }
2915                         break;
2916
2917                 case PC300_X21:
2918                         break;
2919
2920                 case PC300_TE:
2921                         te_config(card, ch);
2922                         break;
2923         }
2924
2925         switch (card->hw.type) {
2926                 case PC300_RSV:
2927                 case PC300_X21:
2928                         if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2929                                 int tmc, br;
2930
2931                                 /* Calculate the clkrate parameters */
2932                                 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2933                                 if (tmc < 0)
2934                                         return -EIO;
2935                                 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2936                                 cpc_writeb(scabase + M_REG(TXS, ch),
2937                                            (TXS_DTRXC | TXS_IBRG | br));
2938                                 if (clktype == CLOCK_INT) {
2939                                         cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2940                                         cpc_writeb(scabase + M_REG(RXS, ch),
2941                                                    (RXS_IBRG | br));
2942                                 } else {
2943                                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2944                                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2945                                 }
2946                                 if (card->hw.type == PC300_X21) {
2947                                         cpc_writeb(scabase + M_REG(GPO, ch), 1);
2948                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2949                                 } else {
2950                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2951                                 }
2952                         } else {
2953                                 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2954                                 if (clktype == CLOCK_EXT) {
2955                                         cpc_writeb(scabase + M_REG(TXS, ch),
2956                                                    TXS_DTRXC);
2957                                 } else {
2958                                         cpc_writeb(scabase + M_REG(TXS, ch),
2959                                                    TXS_DTRXC|TXS_RCLK);
2960                                 }
2961                                 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2962                                 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2963                                 if (card->hw.type == PC300_X21) {
2964                                         cpc_writeb(scabase + M_REG(GPO, ch), 0);
2965                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2966                                 } else {
2967                                         cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2968                                 }
2969                         }
2970                         break;
2971
2972                 case PC300_TE:
2973                         /* SCA always receives clock from the FALC chip */
2974                         cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2975                         cpc_writeb(scabase + M_REG(TXS, ch), 0);
2976                         cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2977                         cpc_writeb(scabase + M_REG(RXS, ch), 0);
2978                         cpc_writeb(scabase + M_REG(EXS, ch), 0);
2979                         break;
2980         }
2981
2982         /* Enable Interrupts */
2983         cpc_writel(scabase + IER0,
2984                    cpc_readl(scabase + IER0) |
2985                    IR0_M(IR0_RXINTA, ch) |
2986                    IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2987                    IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2988         cpc_writeb(scabase + M_REG(IE0, ch),
2989                    cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2990         cpc_writeb(scabase + M_REG(IE1, ch),
2991                    cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2992
2993         return 0;
2994 }
2995
2996 static int rx_config(pc300dev_t * d)
2997 {
2998         pc300ch_t *chan = (pc300ch_t *) d->chan;
2999         pc300_t *card = (pc300_t *) chan->card;
3000         void __iomem *scabase = card->hw.scabase;
3001         int ch = chan->channel;
3002
3003         cpc_writeb(scabase + DSR_RX(ch), 0);
3004
3005         /* General RX settings */
3006         cpc_writeb(scabase + M_REG(RRC, ch), 0);
3007         cpc_writeb(scabase + M_REG(RNR, ch), 16);
3008
3009         /* Enable reception */
3010         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3011         cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3012
3013         /* Initialize DMA stuff */
3014         chan->rx_first_bd = 0;
3015         chan->rx_last_bd = N_DMA_RX_BUF - 1;
3016         rx_dma_buf_init(card, ch);
3017         cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3018         cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3019         cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3020
3021         /* Start DMA */
3022         rx_dma_start(card, ch);
3023
3024         return 0;
3025 }
3026
3027 static int tx_config(pc300dev_t * d)
3028 {
3029         pc300ch_t *chan = (pc300ch_t *) d->chan;
3030         pc300_t *card = (pc300_t *) chan->card;
3031         void __iomem *scabase = card->hw.scabase;
3032         int ch = chan->channel;
3033
3034         cpc_writeb(scabase + DSR_TX(ch), 0);
3035
3036         /* General TX settings */
3037         cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3038         cpc_writeb(scabase + M_REG(TFS, ch), 32);
3039         cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3040         cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3041         cpc_writeb(scabase + M_REG(TCR, ch), 8);
3042
3043         /* Enable transmission */
3044         cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3045
3046         /* Initialize DMA stuff */
3047         chan->tx_first_bd = 0;
3048         chan->tx_next_bd = 0;
3049         tx_dma_buf_init(card, ch);
3050         cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3051         cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3052         cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3053         cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3054         cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3055
3056         return 0;
3057 }
3058
3059 static int cpc_attach(struct net_device *dev, unsigned short encoding,
3060                       unsigned short parity)
3061 {
3062         pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv;
3063         pc300ch_t *chan = (pc300ch_t *)d->chan;
3064         pc300_t *card = (pc300_t *)chan->card;
3065         pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3066
3067         if (card->hw.type == PC300_TE) {
3068                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3069                         return -EINVAL;
3070                 }
3071         } else {
3072                 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3073                     encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3074                         /* Driver doesn't support ENCODING_MANCHESTER yet */
3075                         return -EINVAL;
3076                 }
3077         }
3078
3079         if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3080             parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3081             parity != PARITY_CRC16_PR1_CCITT) {
3082                 return -EINVAL;
3083         }
3084
3085         conf->proto_settings.encoding = encoding;
3086         conf->proto_settings.parity = parity;
3087         return 0;
3088 }
3089
3090 static int cpc_opench(pc300dev_t * d)
3091 {
3092         pc300ch_t *chan = (pc300ch_t *) d->chan;
3093         pc300_t *card = (pc300_t *) chan->card;
3094         int ch = chan->channel, rc;
3095         void __iomem *scabase = card->hw.scabase;
3096
3097         rc = ch_config(d);
3098         if (rc)
3099                 return rc;
3100
3101         rx_config(d);
3102
3103         tx_config(d);
3104
3105         /* Assert RTS and DTR */
3106         cpc_writeb(scabase + M_REG(CTL, ch),
3107                    cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3108
3109         return 0;
3110 }
3111
3112 static void cpc_closech(pc300dev_t * d)
3113 {
3114         pc300ch_t *chan = (pc300ch_t *) d->chan;
3115         pc300_t *card = (pc300_t *) chan->card;
3116         falc_t *pfalc = (falc_t *) & chan->falc;
3117         int ch = chan->channel;
3118
3119         cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3120         rx_dma_stop(card, ch);
3121         tx_dma_stop(card, ch);
3122
3123         if (card->hw.type == PC300_TE) {
3124                 memset(pfalc, 0, sizeof(falc_t));
3125                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3126                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3127                            ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3128                               CPLD_REG2_FALC_LED2) << (2 * ch)));
3129                 /* Reset the FALC chip */
3130                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3131                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3132                            (CPLD_REG1_FALC_RESET << (2 * ch)));
3133                 udelay(10000);
3134                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3135                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3136                            ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3137         }
3138 }
3139
3140 int cpc_open(struct net_device *dev)
3141 {
3142         pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3143         struct ifreq ifr;
3144         int result;
3145
3146 #ifdef  PC300_DEBUG_OTHER
3147         printk("pc300: cpc_open");
3148 #endif
3149
3150         result = hdlc_open(dev);
3151
3152         if (result)
3153                 return result;
3154
3155         sprintf(ifr.ifr_name, "%s", dev->name);
3156         result = cpc_opench(d);
3157         if (result)
3158                 goto err_out;
3159
3160         netif_start_queue(dev);
3161         return 0;
3162
3163 err_out:
3164         hdlc_close(dev);
3165         return result;
3166 }
3167
3168 static int cpc_close(struct net_device *dev)
3169 {
3170         pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3171         pc300ch_t *chan = (pc300ch_t *) d->chan;
3172         pc300_t *card = (pc300_t *) chan->card;
3173         unsigned long flags;
3174
3175 #ifdef  PC300_DEBUG_OTHER
3176         printk("pc300: cpc_close");
3177 #endif
3178
3179         netif_stop_queue(dev);
3180
3181         CPC_LOCK(card, flags);
3182         cpc_closech(d);
3183         CPC_UNLOCK(card, flags);
3184
3185         hdlc_close(dev);
3186
3187 #ifdef CONFIG_PC300_MLPPP
3188         if (chan->conf.proto == PC300_PROTO_MLPPP) {
3189                 cpc_tty_unregister_service(d);
3190                 chan->conf.proto = 0xffff;
3191         }
3192 #endif
3193
3194         return 0;
3195 }
3196
3197 static u32 detect_ram(pc300_t * card)
3198 {
3199         u32 i;
3200         u8 data;
3201         void __iomem *rambase = card->hw.rambase;
3202
3203         card->hw.ramsize = PC300_RAMSIZE;
3204         /* Let's find out how much RAM is present on this board */
3205         for (i = 0; i < card->hw.ramsize; i++) {
3206                 data = (u8)(i & 0xff);
3207                 cpc_writeb(rambase + i, data);
3208                 if (cpc_readb(rambase + i) != data) {
3209                         break;
3210                 }
3211         }
3212         return i;
3213 }
3214
3215 static void plx_init(pc300_t * card)
3216 {
3217         struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3218
3219         /* Reset PLX */
3220         cpc_writel(&plx_ctl->init_ctrl,
3221                    cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3222         udelay(10000L);
3223         cpc_writel(&plx_ctl->init_ctrl,
3224                    cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3225
3226         /* Reload Config. Registers from EEPROM */
3227         cpc_writel(&plx_ctl->init_ctrl,
3228                    cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3229         udelay(10000L);
3230         cpc_writel(&plx_ctl->init_ctrl,
3231                    cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3232
3233 }
3234
3235 static inline void show_version(void)
3236 {
3237         char *rcsvers, *rcsdate, *tmp;
3238
3239         rcsvers = strchr(rcsid, ' ');
3240         rcsvers++;
3241         tmp = strchr(rcsvers, ' ');
3242         *tmp++ = '\0';
3243         rcsdate = strchr(tmp, ' ');
3244         rcsdate++;
3245         tmp = strrchr(rcsdate, ' ');
3246         *tmp = '\0';
3247         pr_info("Cyclades-PC300 driver %s %s\n", rcsvers, rcsdate);
3248 }                               /* show_version */
3249
3250 static const struct net_device_ops cpc_netdev_ops = {
3251         .ndo_open               = cpc_open,
3252         .ndo_stop               = cpc_close,
3253         .ndo_tx_timeout         = cpc_tx_timeout,
3254         .ndo_set_mac_address    = NULL,
3255         .ndo_change_mtu         = cpc_change_mtu,
3256         .ndo_do_ioctl           = cpc_ioctl,
3257         .ndo_validate_addr      = eth_validate_addr,
3258 };
3259
3260 static void cpc_init_card(pc300_t * card)
3261 {
3262         int i, devcount = 0;
3263         static int board_nbr = 1;
3264
3265         /* Enable interrupts on the PCI bridge */
3266         plx_init(card);
3267         cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3268                    cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3269
3270 #ifdef USE_PCI_CLOCK
3271         /* Set board clock to PCI clock */
3272         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3273                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3274         card->hw.clock = PC300_PCI_CLOCK;
3275 #else
3276         /* Set board clock to internal oscillator clock */
3277         cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3278                    cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3279         card->hw.clock = PC300_OSC_CLOCK;
3280 #endif
3281
3282         /* Detect actual on-board RAM size */
3283         card->hw.ramsize = detect_ram(card);
3284
3285         /* Set Global SCA-II registers */
3286         cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3287         cpc_writeb(card->hw.scabase + BTCR, 0x10);
3288         cpc_writeb(card->hw.scabase + WCRL, 0);
3289         cpc_writeb(card->hw.scabase + DMER, 0x80);
3290
3291         if (card->hw.type == PC300_TE) {
3292                 u8 reg1;
3293
3294                 /* Check CPLD version */
3295                 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3296                 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3297                 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3298                         /* New CPLD */
3299                         card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3300                         card->hw.cpld_reg1 = CPLD_V2_REG1;
3301                         card->hw.cpld_reg2 = CPLD_V2_REG2;
3302                 } else {
3303                         /* old CPLD */
3304                         card->hw.cpld_id = 0;
3305                         card->hw.cpld_reg1 = CPLD_REG1;
3306                         card->hw.cpld_reg2 = CPLD_REG2;
3307                         cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3308                 }
3309
3310                 /* Enable the board's global clock */
3311                 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3312                            cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3313                            CPLD_REG1_GLOBAL_CLK);
3314
3315         }
3316
3317         for (i = 0; i < card->hw.nchan; i++) {
3318                 pc300ch_t *chan = &card->chan[i];
3319                 pc300dev_t *d = &chan->d;
3320                 hdlc_device *hdlc;
3321                 struct net_device *dev;
3322
3323                 chan->card = card;
3324                 chan->channel = i;
3325                 chan->conf.phys_settings.clock_rate = 0;
3326                 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3327                 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3328                 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3329                 switch (card->hw.type) {
3330                         case PC300_TE:
3331                                 chan->conf.media = IF_IFACE_T1;
3332                                 chan->conf.lcode = PC300_LC_B8ZS;
3333                                 chan->conf.fr_mode = PC300_FR_ESF;
3334                                 chan->conf.lbo = PC300_LBO_0_DB;
3335                                 chan->conf.rx_sens = PC300_RX_SENS_SH;
3336                                 chan->conf.tslot_bitmap = 0xffffffffUL;
3337                                 break;
3338
3339                         case PC300_X21:
3340                                 chan->conf.media = IF_IFACE_X21;
3341                                 break;
3342
3343                         case PC300_RSV:
3344                         default:
3345                                 chan->conf.media = IF_IFACE_V35;
3346                                 break;
3347                 }
3348                 chan->conf.proto = IF_PROTO_PPP;
3349                 chan->tx_first_bd = 0;
3350                 chan->tx_next_bd = 0;
3351                 chan->rx_first_bd = 0;
3352                 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3353                 chan->nfree_tx_bd = N_DMA_TX_BUF;
3354
3355                 d->chan = chan;
3356                 d->trace_on = 0;
3357                 d->line_on = 0;
3358                 d->line_off = 0;
3359
3360                 dev = alloc_hdlcdev(d);
3361                 if (dev == NULL)
3362                         continue;
3363
3364                 hdlc = dev_to_hdlc(dev);
3365                 hdlc->xmit = cpc_queue_xmit;
3366                 hdlc->attach = cpc_attach;
3367                 d->dev = dev;
3368                 dev->mem_start = card->hw.ramphys;
3369                 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3370                 dev->irq = card->hw.irq;
3371                 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3372                 dev->mtu = PC300_DEF_MTU;
3373
3374                 dev->netdev_ops = &cpc_netdev_ops;
3375                 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3376
3377                 if (register_hdlc_device(dev) == 0) {
3378                         printk("%s: Cyclades-PC300/", dev->name);
3379                         switch (card->hw.type) {
3380                                 case PC300_TE:
3381                                         if (card->hw.bus == PC300_PMC) {
3382                                                 printk("TE-M");
3383                                         } else {
3384                                                 printk("TE  ");
3385                                         }
3386                                         break;
3387
3388                                 case PC300_X21:
3389                                         printk("X21 ");
3390                                         break;
3391
3392                                 case PC300_RSV:
3393                                 default:
3394                                         printk("RSV ");
3395                                         break;
3396                         }
3397                         printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3398                                  board_nbr, card->hw.ramsize / 1024,
3399                                  card->hw.ramphys, card->hw.irq, i + 1);
3400                         devcount++;
3401                 } else {
3402                         printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3403                                  i + 1, card->hw.ramphys);
3404                         free_netdev(dev);
3405                         continue;
3406                 }
3407         }
3408         spin_lock_init(&card->card_lock);
3409
3410         board_nbr++;
3411 }
3412
3413 static int __devinit
3414 cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3415 {
3416         static int first_time = 1;
3417         int err, eeprom_outdated = 0;
3418         u16 device_id;
3419         pc300_t *card;
3420
3421         if (first_time) {
3422                 first_time = 0;
3423                 show_version();
3424 #ifdef CONFIG_PC300_MLPPP
3425                 cpc_tty_reset_var();
3426 #endif
3427         }
3428
3429         if ((err = pci_enable_device(pdev)) < 0)
3430                 return err;
3431
3432         card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3433         if (card == NULL) {
3434                 printk("PC300 found at RAM 0x%016llx, "
3435                        "but could not allocate card structure.\n",
3436                        (unsigned long long)pci_resource_start(pdev, 3));
3437                 err = -ENOMEM;
3438                 goto err_disable_dev;
3439         }
3440
3441         err = -ENODEV;
3442
3443         /* read PCI configuration area */
3444         device_id = ent->device;
3445         card->hw.irq = pdev->irq;
3446         card->hw.iophys = pci_resource_start(pdev, 1);
3447         card->hw.iosize = pci_resource_len(pdev, 1);
3448         card->hw.scaphys = pci_resource_start(pdev, 2);
3449         card->hw.scasize = pci_resource_len(pdev, 2);
3450         card->hw.ramphys = pci_resource_start(pdev, 3);
3451         card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3452         card->hw.falcphys = pci_resource_start(pdev, 4);
3453         card->hw.falcsize = pci_resource_len(pdev, 4);
3454         card->hw.plxphys = pci_resource_start(pdev, 5);
3455         card->hw.plxsize = pci_resource_len(pdev, 5);
3456
3457         switch (device_id) {
3458                 case PCI_DEVICE_ID_PC300_RX_1:
3459                 case PCI_DEVICE_ID_PC300_TE_1:
3460                 case PCI_DEVICE_ID_PC300_TE_M_1:
3461                         card->hw.nchan = 1;
3462                         break;
3463
3464                 case PCI_DEVICE_ID_PC300_RX_2:
3465                 case PCI_DEVICE_ID_PC300_TE_2:
3466                 case PCI_DEVICE_ID_PC300_TE_M_2:
3467                 default:
3468                         card->hw.nchan = PC300_MAXCHAN;
3469                         break;
3470         }
3471 #ifdef PC300_DEBUG_PCI
3472         printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3473         printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3474         printk("cpc:found  ramaddr=0x%08lx plxaddr=0x%08lx "
3475                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3476                card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3477                card->hw.falcphys);
3478 #endif
3479         /* Although we don't use this I/O region, we should
3480          * request it from the kernel anyway, to avoid problems
3481          * with other drivers accessing it. */
3482         if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3483                 /* In case we can't allocate it, warn user */
3484                 printk("WARNING: couldn't allocate I/O region for PC300 board "
3485                        "at 0x%08x!\n", card->hw.ramphys);
3486         }
3487
3488         if (card->hw.plxphys) {
3489                 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3490         } else {
3491                 eeprom_outdated = 1;
3492                 card->hw.plxphys = pci_resource_start(pdev, 0);
3493                 card->hw.plxsize = pci_resource_len(pdev, 0);
3494         }
3495
3496         if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3497                                 "PLX Registers")) {
3498                 printk("PC300 found at RAM 0x%08x, "
3499                        "but could not allocate PLX mem region.\n",
3500                        card->hw.ramphys);
3501                 goto err_release_io;
3502         }
3503         if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3504                                 "On-board RAM")) {
3505                 printk("PC300 found at RAM 0x%08x, "
3506                        "but could not allocate RAM mem region.\n",
3507                        card->hw.ramphys);
3508                 goto err_release_plx;
3509         }
3510         if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3511                                 "SCA-II Registers")) {
3512                 printk("PC300 found at RAM 0x%08x, "
3513                        "but could not allocate SCA mem region.\n",
3514                        card->hw.ramphys);
3515                 goto err_release_ram;
3516         }
3517
3518         card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3519         card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3520         card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3521         switch (device_id) {
3522                 case PCI_DEVICE_ID_PC300_TE_1:
3523                 case PCI_DEVICE_ID_PC300_TE_2:
3524                 case PCI_DEVICE_ID_PC300_TE_M_1:
3525                 case PCI_DEVICE_ID_PC300_TE_M_2:
3526                         request_mem_region(card->hw.falcphys, card->hw.falcsize,
3527                                            "FALC Registers");
3528                         card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3529                         break;
3530
3531                 case PCI_DEVICE_ID_PC300_RX_1:
3532                 case PCI_DEVICE_ID_PC300_RX_2:
3533                 default:
3534                         card->hw.falcbase = NULL;
3535                         break;
3536         }
3537
3538 #ifdef PC300_DEBUG_PCI
3539         printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3540                "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3541                card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3542                card->hw.falcbase);
3543 #endif
3544
3545         /* Set PCI drv pointer to the card structure */
3546         pci_set_drvdata(pdev, card);
3547
3548         /* Set board type */
3549         switch (device_id) {
3550                 case PCI_DEVICE_ID_PC300_TE_1:
3551                 case PCI_DEVICE_ID_PC300_TE_2:
3552                 case PCI_DEVICE_ID_PC300_TE_M_1:
3553                 case PCI_DEVICE_ID_PC300_TE_M_2:
3554                         card->hw.type = PC300_TE;
3555
3556                         if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3557                             (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3558                                 card->hw.bus = PC300_PMC;
3559                                 /* Set PLX register offsets */
3560                                 card->hw.gpioc_reg = 0x54;
3561                                 card->hw.intctl_reg = 0x4c;
3562                         } else {
3563                                 card->hw.bus = PC300_PCI;
3564                                 /* Set PLX register offsets */
3565                                 card->hw.gpioc_reg = 0x50;
3566                                 card->hw.intctl_reg = 0x4c;
3567                         }
3568                         break;
3569
3570                 case PCI_DEVICE_ID_PC300_RX_1:
3571                 case PCI_DEVICE_ID_PC300_RX_2:
3572                 default:
3573                         card->hw.bus = PC300_PCI;
3574                         /* Set PLX register offsets */
3575                         card->hw.gpioc_reg = 0x50;
3576                         card->hw.intctl_reg = 0x4c;
3577
3578                         if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3579                                 card->hw.type = PC300_X21;
3580                         } else {
3581                                 card->hw.type = PC300_RSV;
3582                         }
3583                         break;
3584         }
3585
3586         /* Allocate IRQ */
3587         if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3588                 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3589                          card->hw.ramphys, card->hw.irq);
3590                 goto err_io_unmap;
3591         }
3592
3593         cpc_init_card(card);
3594
3595         if (eeprom_outdated)
3596                 printk("WARNING: PC300 with outdated EEPROM.\n");
3597         return 0;
3598
3599 err_io_unmap:
3600         iounmap(card->hw.plxbase);
3601         iounmap(card->hw.scabase);
3602         iounmap(card->hw.rambase);
3603         if (card->hw.type == PC300_TE) {
3604                 iounmap(card->hw.falcbase);
3605                 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3606         }
3607         release_mem_region(card->hw.scaphys, card->hw.scasize);
3608 err_release_ram:
3609         release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3610 err_release_plx:
3611         release_mem_region(card->hw.plxphys, card->hw.plxsize);
3612 err_release_io:
3613         release_region(card->hw.iophys, card->hw.iosize);
3614         kfree(card);
3615 err_disable_dev:
3616         pci_disable_device(pdev);
3617         return err;
3618 }
3619
3620 static void __devexit cpc_remove_one(struct pci_dev *pdev)
3621 {
3622         pc300_t *card = pci_get_drvdata(pdev);
3623
3624         if (card->hw.rambase) {
3625                 int i;
3626
3627                 /* Disable interrupts on the PCI bridge */
3628                 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3629                            cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3630
3631                 for (i = 0; i < card->hw.nchan; i++) {
3632                         unregister_hdlc_device(card->chan[i].d.dev);
3633                 }
3634                 iounmap(card->hw.plxbase);
3635                 iounmap(card->hw.scabase);
3636                 iounmap(card->hw.rambase);
3637                 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3638                 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3639                 release_mem_region(card->hw.scaphys, card->hw.scasize);
3640                 release_region(card->hw.iophys, card->hw.iosize);
3641                 if (card->hw.type == PC300_TE) {
3642                         iounmap(card->hw.falcbase);
3643                         release_mem_region(card->hw.falcphys, card->hw.falcsize);
3644                 }
3645                 for (i = 0; i < card->hw.nchan; i++)
3646                         if (card->chan[i].d.dev)
3647                                 free_netdev(card->chan[i].d.dev);
3648                 if (card->hw.irq)
3649                         free_irq(card->hw.irq, card);
3650                 kfree(card);
3651                 pci_disable_device(pdev);
3652         }
3653 }
3654
3655 static struct pci_driver cpc_driver = {
3656         .name           = "pc300",
3657         .id_table       = cpc_pci_dev_id,
3658         .probe          = cpc_init_one,
3659         .remove         = __devexit_p(cpc_remove_one),
3660 };
3661
3662 static int __init cpc_init(void)
3663 {
3664         return pci_register_driver(&cpc_driver);
3665 }
3666
3667 static void __exit cpc_cleanup_module(void)
3668 {
3669         pci_unregister_driver(&cpc_driver);
3670 }
3671
3672 module_init(cpc_init);
3673 module_exit(cpc_cleanup_module);
3674
3675 MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3676 MODULE_AUTHOR(  "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3677                 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3678 MODULE_LICENSE("GPL");
3679