2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux
4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * Source of information: HD64572 SCA-II User's Manual
12 * We use the following SCA memory map:
14 * Packet buffer descriptor rings - starting from winbase or win0base:
15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
20 * Packet data buffers - starting from winbase + buff_offset:
21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
27 #include <linux/bitops.h>
28 #include <linux/errno.h>
29 #include <linux/fcntl.h>
30 #include <linux/hdlc.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/jiffies.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/types.h>
44 #include <asm/system.h>
45 #include <asm/uaccess.h>
48 #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
49 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
50 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
52 #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
53 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
54 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
57 static inline struct net_device *port_to_dev(port_t *port)
62 static inline int sca_intr_status(card_t *card)
65 u32 isr0 = sca_inl(ISR0, card);
67 if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0);
68 if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0);
69 if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1);
70 if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1);
71 if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0);
72 if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1);
74 if (!(result & SCA_INTR_DMAC_TX(0)))
75 if (sca_in(DSR_TX(0), card) & DSR_EOM)
76 result |= SCA_INTR_DMAC_TX(0);
77 if (!(result & SCA_INTR_DMAC_TX(1)))
78 if (sca_in(DSR_TX(1), card) & DSR_EOM)
79 result |= SCA_INTR_DMAC_TX(1);
84 static inline port_t* dev_to_port(struct net_device *dev)
86 return dev_to_hdlc(dev)->priv;
89 static inline u16 next_desc(port_t *port, u16 desc, int transmit)
91 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
92 : port_to_card(port)->rx_ring_buffers);
96 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
98 u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
99 u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
101 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
102 return log_node(port) * (rx_buffs + tx_buffs) +
103 transmit * rx_buffs + desc;
107 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
109 /* Descriptor offset always fits in 16 bytes */
110 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
114 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
117 return (pkt_desc __iomem *)(winbase(port_to_card(port))
118 + desc_offset(port, desc, transmit));
122 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
124 return port_to_card(port)->buff_offset +
125 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
129 static inline void sca_set_carrier(port_t *port)
131 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
133 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
134 port_to_dev(port)->name);
136 netif_carrier_on(port_to_dev(port));
139 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
140 port_to_dev(port)->name);
142 netif_carrier_off(port_to_dev(port));
147 static void sca_init_port(port_t *port)
149 card_t *card = port_to_card(port);
156 for (transmit = 0; transmit < 2; transmit++) {
157 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
158 u16 buffs = transmit ? card->tx_ring_buffers
159 : card->rx_ring_buffers;
161 for (i = 0; i < buffs; i++) {
162 pkt_desc __iomem *desc = desc_address(port, i, transmit);
163 u16 chain_off = desc_offset(port, i + 1, transmit);
164 u32 buff_off = buffer_offset(port, i, transmit);
166 writel(chain_off, &desc->cp);
167 writel(buff_off, &desc->bp);
168 writew(0, &desc->len);
169 writeb(0, &desc->stat);
172 /* DMA disable - to halt state */
173 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
174 DSR_RX(phy_node(port)), card);
175 /* software ABORT - to initial state */
176 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
177 DCR_RX(phy_node(port)), card);
179 /* current desc addr */
180 sca_outl(desc_offset(port, 0, transmit), dmac + CDAL, card);
182 sca_outl(desc_offset(port, buffs - 1, transmit),
185 sca_outl(desc_offset(port, 0, transmit), dmac + EDAL,
188 /* clear frame end interrupt counter */
189 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
190 DCR_RX(phy_node(port)), card);
192 if (!transmit) { /* Receive */
193 /* set buffer length */
194 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
195 /* Chain mode, Multi-frame */
196 sca_out(0x14, DMR_RX(phy_node(port)), card);
197 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
200 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
201 } else { /* Transmit */
202 /* Chain mode, Multi-frame */
203 sca_out(0x14, DMR_TX(phy_node(port)), card);
204 /* enable underflow interrupts */
205 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
208 sca_set_carrier(port);
212 /* MSCI interrupt service */
213 static inline void sca_msci_intr(port_t *port)
215 u16 msci = get_msci(port);
216 card_t* card = port_to_card(port);
217 u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
219 /* Reset MSCI TX underrun and CDCD status bit */
220 sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
222 if (stat & ST1_UDRN) {
223 /* TX Underrun error detected */
224 port_to_dev(port)->stats.tx_errors++;
225 port_to_dev(port)->stats.tx_fifo_errors++;
229 sca_set_carrier(port);
233 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
236 struct net_device *dev = port_to_dev(port);
241 len = readw(&desc->len);
242 skb = dev_alloc_skb(len);
244 dev->stats.rx_dropped++;
248 buff = buffer_offset(port, rxin, 0);
249 memcpy_fromio(skb->data, winbase(card) + buff, len);
253 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
256 dev->stats.rx_packets++;
257 dev->stats.rx_bytes += skb->len;
258 skb->protocol = hdlc_type_trans(skb, dev);
263 /* Receive DMA interrupt service */
264 static inline void sca_rx_intr(port_t *port)
266 struct net_device *dev = port_to_dev(port);
267 u16 dmac = get_dmac_rx(port);
268 card_t *card = port_to_card(port);
269 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
271 /* Reset DSR status bits */
272 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
273 DSR_RX(phy_node(port)), card);
276 /* Dropped one or more frames */
277 dev->stats.rx_over_errors++;
280 u32 desc_off = desc_offset(port, port->rxin, 0);
281 pkt_desc __iomem *desc;
282 u32 cda = sca_inl(dmac + CDAL, card);
284 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
285 break; /* No frame received */
287 desc = desc_address(port, port->rxin, 0);
288 stat = readb(&desc->stat);
289 if (!(stat & ST_RX_EOM))
290 port->rxpart = 1; /* partial frame received */
291 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
292 dev->stats.rx_errors++;
293 if (stat & ST_RX_OVERRUN)
294 dev->stats.rx_fifo_errors++;
295 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
296 ST_RX_RESBIT)) || port->rxpart)
297 dev->stats.rx_frame_errors++;
298 else if (stat & ST_RX_CRC)
299 dev->stats.rx_crc_errors++;
300 if (stat & ST_RX_EOM)
301 port->rxpart = 0; /* received last fragment */
303 sca_rx(card, port, desc, port->rxin);
305 /* Set new error descriptor address */
306 sca_outl(desc_off, dmac + EDAL, card);
307 port->rxin = next_desc(port, port->rxin, 0);
310 /* make sure RX DMA is enabled */
311 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
315 /* Transmit DMA interrupt service */
316 static inline void sca_tx_intr(port_t *port)
318 struct net_device *dev = port_to_dev(port);
319 u16 dmac = get_dmac_tx(port);
320 card_t* card = port_to_card(port);
323 spin_lock(&port->lock);
325 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
327 /* Reset DSR status bits */
328 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
329 DSR_TX(phy_node(port)), card);
332 pkt_desc __iomem *desc;
334 u32 desc_off = desc_offset(port, port->txlast, 1);
335 u32 cda = sca_inl(dmac + CDAL, card);
336 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
337 break; /* Transmitter is/will_be sending this frame */
339 desc = desc_address(port, port->txlast, 1);
340 dev->stats.tx_packets++;
341 dev->stats.tx_bytes += readw(&desc->len);
342 writeb(0, &desc->stat); /* Free descriptor */
343 port->txlast = next_desc(port, port->txlast, 1);
346 netif_wake_queue(dev);
347 spin_unlock(&port->lock);
351 static irqreturn_t sca_intr(int irq, void* dev_id)
353 card_t *card = dev_id;
358 while((stat = sca_intr_status(card)) != 0) {
360 for (i = 0; i < 2; i++) {
361 port_t *port = get_port(card, i);
363 if (stat & SCA_INTR_MSCI(i))
366 if (stat & SCA_INTR_DMAC_RX(i))
369 if (stat & SCA_INTR_DMAC_TX(i))
375 return IRQ_RETVAL(handled);
379 static void sca_set_port(port_t *port)
381 card_t* card = port_to_card(port);
382 u16 msci = get_msci(port);
383 u8 md2 = sca_in(msci + MD2, card);
384 unsigned int tmc, br = 10, brv = 1024;
387 if (port->settings.clock_rate > 0) {
388 /* Try lower br for better accuracy*/
391 brv >>= 1; /* brv = 2^9 = 512 max in specs */
393 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
394 tmc = CLOCK_BASE / brv / port->settings.clock_rate;
395 }while (br > 1 && tmc <= 128);
399 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
401 } else if (tmc > 255)
402 tmc = 256; /* tmc=0 means 256 - low baud rates */
404 port->settings.clock_rate = CLOCK_BASE / brv / tmc;
406 br = 9; /* Minimum clock rate */
407 tmc = 256; /* 8bit = 0 */
408 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
411 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
412 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
415 /* baud divisor - time constant*/
416 sca_out(port->tmc, msci + TMCR, card);
417 sca_out(port->tmc, msci + TMCT, card);
420 sca_out(port->rxs, msci + RXS, card);
421 sca_out(port->txs, msci + TXS, card);
423 if (port->settings.loopback)
426 md2 &= ~MD2_LOOPBACK;
428 sca_out(md2, msci + MD2, card);
433 static void sca_open(struct net_device *dev)
435 port_t *port = dev_to_port(dev);
436 card_t* card = port_to_card(port);
437 u16 msci = get_msci(port);
440 switch(port->encoding) {
441 case ENCODING_NRZ: md2 = MD2_NRZ; break;
442 case ENCODING_NRZI: md2 = MD2_NRZI; break;
443 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
444 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
445 default: md2 = MD2_MANCHESTER;
448 if (port->settings.loopback)
451 switch(port->parity) {
452 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
453 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
454 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
455 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
456 default: md0 = MD0_HDLC | MD0_CRC_NONE;
459 sca_out(CMD_RESET, msci + CMD, card);
460 sca_out(md0, msci + MD0, card);
461 sca_out(0x00, msci + MD1, card); /* no address field check */
462 sca_out(md2, msci + MD2, card);
463 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
464 /* Skip the rest of underrun frame */
465 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
466 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
467 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
468 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
469 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
470 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
472 /* We're using the following interrupts:
473 - TXINT (DMAC completed all transmisions, underrun or DCD change)
477 sca_set_carrier(port);
479 /* MSCI TXINT and RXINTA interrupt enable */
480 sca_outl(IE0_TXINT | IE0_RXINTA | IE0_UDRN | IE0_CDCD, msci + IE0,
482 /* DMA & MSCI IRQ enable */
483 sca_outl(sca_inl(IER0, card) |
484 (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, card);
486 sca_out(port->tmc, msci + TMCR, card);
487 sca_out(port->tmc, msci + TMCT, card);
488 sca_out(port->rxs, msci + RXS, card);
489 sca_out(port->txs, msci + TXS, card);
490 sca_out(CMD_TX_ENABLE, msci + CMD, card);
491 sca_out(CMD_RX_ENABLE, msci + CMD, card);
493 netif_start_queue(dev);
497 static void sca_close(struct net_device *dev)
499 port_t *port = dev_to_port(dev);
500 card_t* card = port_to_card(port);
503 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
504 /* disable DMA & MSCI IRQ */
505 sca_outl(sca_inl(IER0, card) &
506 (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, card);
508 netif_stop_queue(dev);
512 static int sca_attach(struct net_device *dev, unsigned short encoding,
513 unsigned short parity)
515 if (encoding != ENCODING_NRZ &&
516 encoding != ENCODING_NRZI &&
517 encoding != ENCODING_FM_MARK &&
518 encoding != ENCODING_FM_SPACE &&
519 encoding != ENCODING_MANCHESTER)
522 if (parity != PARITY_NONE &&
523 parity != PARITY_CRC16_PR0 &&
524 parity != PARITY_CRC16_PR1 &&
525 parity != PARITY_CRC32_PR1_CCITT &&
526 parity != PARITY_CRC16_PR1_CCITT)
529 dev_to_port(dev)->encoding = encoding;
530 dev_to_port(dev)->parity = parity;
536 static void sca_dump_rings(struct net_device *dev)
538 port_t *port = dev_to_port(dev);
539 card_t *card = port_to_card(port);
542 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
543 sca_inl(get_dmac_rx(port) + CDAL, card),
544 sca_inl(get_dmac_rx(port) + EDAL, card),
545 sca_in(DSR_RX(phy_node(port)), card), port->rxin,
546 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
547 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
548 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
550 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
552 sca_inl(get_dmac_tx(port) + CDAL, card),
553 sca_inl(get_dmac_tx(port) + EDAL, card),
554 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
555 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
557 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
558 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
561 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x,"
562 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n",
563 sca_in(get_msci(port) + MD0, card),
564 sca_in(get_msci(port) + MD1, card),
565 sca_in(get_msci(port) + MD2, card),
566 sca_in(get_msci(port) + ST0, card),
567 sca_in(get_msci(port) + ST1, card),
568 sca_in(get_msci(port) + ST2, card),
569 sca_in(get_msci(port) + ST3, card),
570 sca_in(get_msci(port) + ST4, card),
571 sca_in(get_msci(port) + FST, card),
572 sca_in(get_msci(port) + CST0, card),
573 sca_in(get_msci(port) + CST1, card));
575 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
576 sca_inl(ISR0, card), sca_inl(ISR1, card));
578 #endif /* DEBUG_RINGS */
581 static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
583 port_t *port = dev_to_port(dev);
584 card_t *card = port_to_card(port);
585 pkt_desc __iomem *desc;
588 spin_lock_irq(&port->lock);
590 desc = desc_address(port, port->txin + 1, 1);
591 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
594 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
598 desc = desc_address(port, port->txin, 1);
599 buff = buffer_offset(port, port->txin, 1);
601 memcpy_toio(winbase(card) + buff, skb->data, len);
603 writew(len, &desc->len);
604 writeb(ST_TX_EOM, &desc->stat);
605 dev->trans_start = jiffies;
607 port->txin = next_desc(port, port->txin, 1);
608 sca_outl(desc_offset(port, port->txin, 1),
609 get_dmac_tx(port) + EDAL, card);
611 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
613 desc = desc_address(port, port->txin + 1, 1);
614 if (readb(&desc->stat)) /* allow 1 packet gap */
615 netif_stop_queue(dev);
617 spin_unlock_irq(&port->lock);
624 static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
627 /* Round RAM size to 32 bits, fill from end to start */
628 u32 i = ramsize &= ~3;
632 writel(i ^ 0x12345678, rambase + i);
635 for (i = 0; i < ramsize ; i += 4) {
636 if (readl(rambase + i) != (i ^ 0x12345678))
644 static void __devinit sca_init(card_t *card, int wait_states)
646 sca_out(wait_states, WCRL, card); /* Wait Control */
647 sca_out(wait_states, WCRM, card);
648 sca_out(wait_states, WCRH, card);
650 sca_out(0, DMER, card); /* DMA Master disable */
651 sca_out(0x03, PCR, card); /* DMA priority */
652 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
653 sca_out(0, DSR_TX(0), card);
654 sca_out(0, DSR_RX(1), card);
655 sca_out(0, DSR_TX(1), card);
656 sca_out(DMER_DME, DMER, card); /* DMA Master enable */