drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2011 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mdio.h>
  36 #include <linux/mii.h>
  37 #include <linux/phy.h>
  38 #include <linux/brcmphy.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/ip.h>
  41 #include <linux/tcp.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/firmware.h>
  46
  47 #include <net/checksum.h>
  48 #include <net/ip.h>
  49
  50 #include <asm/system.h>
  51 #include <linux/io.h>
  52 #include <asm/byteorder.h>
  53 #include <linux/uaccess.h>
  54
  55 #ifdef CONFIG_SPARC
  56 #include <asm/idprom.h>
  57 #include <asm/prom.h>
  58 #endif
  59
  60 #define BAR_0   0
  61 #define BAR_2   2
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define TG3_MAJ_NUM                     3
  67 #define TG3_MIN_NUM                     117
  68 #define DRV_MODULE_VERSION      \
  69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  70 #define DRV_MODULE_RELDATE      "January 25, 2011"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_STD_RING_SIZE(tp) \
 100         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 101          TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JMB_RING_SIZE(tp) \
 104         ((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
 105          TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 106 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 107 #define TG3_RSS_INDIR_TBL_SIZE          128
 108
 109 /* Do not place this n-ring entries value into the tp struct itself,
 110  * we really want to expose these constants to GCC so that modulo et
 111  * al.  operations are done with shifts and masks instead of with
 112  * hw multiply/modulo instructions.  Another solution would be to
 113  * replace things like '% foo' with '& (foo - 1)'.
 114  */
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_STD_RING_BYTES(tp) \
 120         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 121 #define TG3_RX_JMB_RING_BYTES(tp) \
 122         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 123 #define TG3_RX_RCB_RING_BYTES(tp) \
 124         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 140         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 141
 142 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 143         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 144
 145 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 146  * that are at least dword aligned when used in PCIX mode.  The driver
 147  * works around this bug by double copying the packet.  This workaround
 148  * is built into the normal double copy length check for efficiency.
 149  *
 150  * However, the double copy is only necessary on those architectures
 151  * where unaligned memory accesses are inefficient.  For those architectures
 152  * where unaligned memory accesses incur little penalty, we can reintegrate
 153  * the 5701 in the normal rx path.  Doing so saves a device structure
 154  * dereference by hardcoding the double copy threshold in place.
 155  */
 156 #define TG3_RX_COPY_THRESHOLD           256
 157 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 158         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 159 #else
 160         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 161 #endif
 162
 163 /* minimum number of free TX descriptors required to wake up TX process */
 164 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 165
 166 #define TG3_RAW_IP_ALIGN 2
 167
 168 /* number of ETHTOOL_GSTATS u64's */
 169 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 170
 171 #define TG3_NUM_TEST            6
 172
 173 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 174
 175 #define FIRMWARE_TG3            "tigon/tg3.bin"
 176 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 177 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 178
 179 static char version[] __devinitdata =
 180         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 181
 182 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 183 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 184 MODULE_LICENSE("GPL");
 185 MODULE_VERSION(DRV_MODULE_VERSION);
 186 MODULE_FIRMWARE(FIRMWARE_TG3);
 187 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 188 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 189
 190 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 191 module_param(tg3_debug, int, 0);
 192 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 193
 194 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 275         {}
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 279
 280 static const struct {
 281         const char string[ETH_GSTRING_LEN];
 282 } ethtool_stats_keys[TG3_NUM_STATS] = {
 283         { "rx_octets" },
 284         { "rx_fragments" },
 285         { "rx_ucast_packets" },
 286         { "rx_mcast_packets" },
 287         { "rx_bcast_packets" },
 288         { "rx_fcs_errors" },
 289         { "rx_align_errors" },
 290         { "rx_xon_pause_rcvd" },
 291         { "rx_xoff_pause_rcvd" },
 292         { "rx_mac_ctrl_rcvd" },
 293         { "rx_xoff_entered" },
 294         { "rx_frame_too_long_errors" },
 295         { "rx_jabbers" },
 296         { "rx_undersize_packets" },
 297         { "rx_in_length_errors" },
 298         { "rx_out_length_errors" },
 299         { "rx_64_or_less_octet_packets" },
 300         { "rx_65_to_127_octet_packets" },
 301         { "rx_128_to_255_octet_packets" },
 302         { "rx_256_to_511_octet_packets" },
 303         { "rx_512_to_1023_octet_packets" },
 304         { "rx_1024_to_1522_octet_packets" },
 305         { "rx_1523_to_2047_octet_packets" },
 306         { "rx_2048_to_4095_octet_packets" },
 307         { "rx_4096_to_8191_octet_packets" },
 308         { "rx_8192_to_9022_octet_packets" },
 309
 310         { "tx_octets" },
 311         { "tx_collisions" },
 312
 313         { "tx_xon_sent" },
 314         { "tx_xoff_sent" },
 315         { "tx_flow_control" },
 316         { "tx_mac_errors" },
 317         { "tx_single_collisions" },
 318         { "tx_mult_collisions" },
 319         { "tx_deferred" },
 320         { "tx_excessive_collisions" },
 321         { "tx_late_collisions" },
 322         { "tx_collide_2times" },
 323         { "tx_collide_3times" },
 324         { "tx_collide_4times" },
 325         { "tx_collide_5times" },
 326         { "tx_collide_6times" },
 327         { "tx_collide_7times" },
 328         { "tx_collide_8times" },
 329         { "tx_collide_9times" },
 330         { "tx_collide_10times" },
 331         { "tx_collide_11times" },
 332         { "tx_collide_12times" },
 333         { "tx_collide_13times" },
 334         { "tx_collide_14times" },
 335         { "tx_collide_15times" },
 336         { "tx_ucast_packets" },
 337         { "tx_mcast_packets" },
 338         { "tx_bcast_packets" },
 339         { "tx_carrier_sense_errors" },
 340         { "tx_discards" },
 341         { "tx_errors" },
 342
 343         { "dma_writeq_full" },
 344         { "dma_write_prioq_full" },
 345         { "rxbds_empty" },
 346         { "rx_discards" },
 347         { "rx_errors" },
 348         { "rx_threshold_hit" },
 349
 350         { "dma_readq_full" },
 351         { "dma_read_prioq_full" },
 352         { "tx_comp_queue_full" },
 353
 354         { "ring_set_send_prod_index" },
 355         { "ring_status_update" },
 356         { "nic_irqs" },
 357         { "nic_avoided_irqs" },
 358         { "nic_tx_threshold_hit" }
 359 };
 360
 361 static const struct {
 362         const char string[ETH_GSTRING_LEN];
 363 } ethtool_test_keys[TG3_NUM_TEST] = {
 364         { "nvram test     (online) " },
 365         { "link test      (online) " },
 366         { "register test  (offline)" },
 367         { "memory test    (offline)" },
 368         { "loopback test  (offline)" },
 369         { "interrupt test (offline)" },
 370 };
 371
 372 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         writel(val, tp->regs + off);
 375 }
 376
 377 static u32 tg3_read32(struct tg3 *tp, u32 off)
 378 {
 379         return readl(tp->regs + off);
 380 }
 381
 382 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 383 {
 384         writel(val, tp->aperegs + off);
 385 }
 386
 387 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 388 {
 389         return readl(tp->aperegs + off);
 390 }
 391
 392 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 393 {
 394         unsigned long flags;
 395
 396         spin_lock_irqsave(&tp->indirect_lock, flags);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 398         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 399         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 400 }
 401
 402 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 403 {
 404         writel(val, tp->regs + off);
 405         readl(tp->regs + off);
 406 }
 407
 408 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 409 {
 410         unsigned long flags;
 411         u32 val;
 412
 413         spin_lock_irqsave(&tp->indirect_lock, flags);
 414         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 415         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 416         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 417         return val;
 418 }
 419
 420 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 421 {
 422         unsigned long flags;
 423
 424         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 425                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 426                                        TG3_64BIT_REG_LOW, val);
 427                 return;
 428         }
 429         if (off == TG3_RX_STD_PROD_IDX_REG) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 431                                        TG3_64BIT_REG_LOW, val);
 432                 return;
 433         }
 434
 435         spin_lock_irqsave(&tp->indirect_lock, flags);
 436         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 437         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 438         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 439
 440         /* In indirect mode when disabling interrupts, we also need
 441          * to clear the interrupt bit in the GRC local ctrl register.
 442          */
 443         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 444             (val == 0x1)) {
 445                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 446                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 447         }
 448 }
 449
 450 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 451 {
 452         unsigned long flags;
 453         u32 val;
 454
 455         spin_lock_irqsave(&tp->indirect_lock, flags);
 456         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 457         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 458         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 459         return val;
 460 }
 461
 462 /* usec_wait specifies the wait time in usec when writing to certain registers
 463  * where it is unsafe to read back the register without some delay.
 464  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 465  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 466  */
 467 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 468 {
 469         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 470             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 /* Non-posted methods */
 472                 tp->write32(tp, off, val);
 473         else {
 474                 /* Posted method */
 475                 tg3_write32(tp, off, val);
 476                 if (usec_wait)
 477                         udelay(usec_wait);
 478                 tp->read32(tp, off);
 479         }
 480         /* Wait again after the read for the posted method to guarantee that
 481          * the wait time is met.
 482          */
 483         if (usec_wait)
 484                 udelay(usec_wait);
 485 }
 486
 487 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 488 {
 489         tp->write32_mbox(tp, off, val);
 490         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 491             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 492                 tp->read32_mbox(tp, off);
 493 }
 494
 495 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         void __iomem *mbox = tp->regs + off;
 498         writel(val, mbox);
 499         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 500                 writel(val, mbox);
 501         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 502                 readl(mbox);
 503 }
 504
 505 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 506 {
 507         return readl(tp->regs + off + GRCMBOX_BASE);
 508 }
 509
 510 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 511 {
 512         writel(val, tp->regs + off + GRCMBOX_BASE);
 513 }
 514
 515 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 516 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 517 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 518 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 519 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 520
 521 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 522 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 523 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 524 #define tr32(reg)                       tp->read32(tp, reg)
 525
 526 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 527 {
 528         unsigned long flags;
 529
 530         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 531             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 532                 return;
 533
 534         spin_lock_irqsave(&tp->indirect_lock, flags);
 535         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 536                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 538
 539                 /* Always leave this as zero. */
 540                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 541         } else {
 542                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         }
 548         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 549 }
 550
 551 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 552 {
 553         unsigned long flags;
 554
 555         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 556             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 557                 *val = 0;
 558                 return;
 559         }
 560
 561         spin_lock_irqsave(&tp->indirect_lock, flags);
 562         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 563                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 564                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 565
 566                 /* Always leave this as zero. */
 567                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 568         } else {
 569                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 570                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 571
 572                 /* Always leave this as zero. */
 573                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 574         }
 575         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 576 }
 577
 578 static void tg3_ape_lock_init(struct tg3 *tp)
 579 {
 580         int i;
 581         u32 regbase;
 582
 583         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 584                 regbase = TG3_APE_LOCK_GRANT;
 585         else
 586                 regbase = TG3_APE_PER_LOCK_GRANT;
 587
 588         /* Make sure the driver hasn't any stale locks. */
 589         for (i = 0; i < 8; i++)
 590                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 591 }
 592
 593 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 594 {
 595         int i, off;
 596         int ret = 0;
 597         u32 status, req, gnt;
 598
 599         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 600                 return 0;
 601
 602         switch (locknum) {
 603         case TG3_APE_LOCK_GRC:
 604         case TG3_APE_LOCK_MEM:
 605                 break;
 606         default:
 607                 return -EINVAL;
 608         }
 609
 610         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 611                 req = TG3_APE_LOCK_REQ;
 612                 gnt = TG3_APE_LOCK_GRANT;
 613         } else {
 614                 req = TG3_APE_PER_LOCK_REQ;
 615                 gnt = TG3_APE_PER_LOCK_GRANT;
 616         }
 617
 618         off = 4 * locknum;
 619
 620         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 621
 622         /* Wait for up to 1 millisecond to acquire lock. */
 623         for (i = 0; i < 100; i++) {
 624                 status = tg3_ape_read32(tp, gnt + off);
 625                 if (status == APE_LOCK_GRANT_DRIVER)
 626                         break;
 627                 udelay(10);
 628         }
 629
 630         if (status != APE_LOCK_GRANT_DRIVER) {
 631                 /* Revoke the lock request. */
 632                 tg3_ape_write32(tp, gnt + off,
 633                                 APE_LOCK_GRANT_DRIVER);
 634
 635                 ret = -EBUSY;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 642 {
 643         u32 gnt;
 644
 645         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 646                 return;
 647
 648         switch (locknum) {
 649         case TG3_APE_LOCK_GRC:
 650         case TG3_APE_LOCK_MEM:
 651                 break;
 652         default:
 653                 return;
 654         }
 655
 656         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 657                 gnt = TG3_APE_LOCK_GRANT;
 658         else
 659                 gnt = TG3_APE_PER_LOCK_GRANT;
 660
 661         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 662 }
 663
 664 static void tg3_disable_ints(struct tg3 *tp)
 665 {
 666         int i;
 667
 668         tw32(TG3PCI_MISC_HOST_CTRL,
 669              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 670         for (i = 0; i < tp->irq_max; i++)
 671                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 672 }
 673
 674 static void tg3_enable_ints(struct tg3 *tp)
 675 {
 676         int i;
 677
 678         tp->irq_sync = 0;
 679         wmb();
 680
 681         tw32(TG3PCI_MISC_HOST_CTRL,
 682              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 683
 684         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 685         for (i = 0; i < tp->irq_cnt; i++) {
 686                 struct tg3_napi *tnapi = &tp->napi[i];
 687
 688                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 689                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 690                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 691
 692                 tp->coal_now |= tnapi->coal_now;
 693         }
 694
 695         /* Force an initial interrupt */
 696         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 697             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 698                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 699         else
 700                 tw32(HOSTCC_MODE, tp->coal_now);
 701
 702         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 703 }
 704
 705 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 706 {
 707         struct tg3 *tp = tnapi->tp;
 708         struct tg3_hw_status *sblk = tnapi->hw_status;
 709         unsigned int work_exists = 0;
 710
 711         /* check for phy events */
 712         if (!(tp->tg3_flags &
 713               (TG3_FLAG_USE_LINKCHG_REG |
 714                TG3_FLAG_POLL_SERDES))) {
 715                 if (sblk->status & SD_STATUS_LINK_CHG)
 716                         work_exists = 1;
 717         }
 718         /* check for RX/TX work to do */
 719         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 720             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 721                 work_exists = 1;
 722
 723         return work_exists;
 724 }
 725
 726 /* tg3_int_reenable
 727  *  similar to tg3_enable_ints, but it accurately determines whether there
 728  *  is new work pending and can return without flushing the PIO write
 729  *  which reenables interrupts
 730  */
 731 static void tg3_int_reenable(struct tg3_napi *tnapi)
 732 {
 733         struct tg3 *tp = tnapi->tp;
 734
 735         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 736         mmiowb();
 737
 738         /* When doing tagged status, this work check is unnecessary.
 739          * The last_tag we write above tells the chip which piece of
 740          * work we've completed.
 741          */
 742         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 743             tg3_has_work(tnapi))
 744                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 745                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 746 }
 747
 748 static void tg3_switch_clocks(struct tg3 *tp)
 749 {
 750         u32 clock_ctrl;
 751         u32 orig_clock_ctrl;
 752
 753         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 754             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 755                 return;
 756
 757         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 758
 759         orig_clock_ctrl = clock_ctrl;
 760         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 761                        CLOCK_CTRL_CLKRUN_OENABLE |
 762                        0x1f);
 763         tp->pci_clock_ctrl = clock_ctrl;
 764
 765         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 766                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 767                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 768                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 769                 }
 770         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 771                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 772                             clock_ctrl |
 773                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 774                             40);
 775                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 776                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 777                             40);
 778         }
 779         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 780 }
 781
 782 #define PHY_BUSY_LOOPS  5000
 783
 784 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 785 {
 786         u32 frame_val;
 787         unsigned int loops;
 788         int ret;
 789
 790         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 791                 tw32_f(MAC_MI_MODE,
 792                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 793                 udelay(80);
 794         }
 795
 796         *val = 0x0;
 797
 798         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 799                       MI_COM_PHY_ADDR_MASK);
 800         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 801                       MI_COM_REG_ADDR_MASK);
 802         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810
 811                 if ((frame_val & MI_COM_BUSY) == 0) {
 812                         udelay(5);
 813                         frame_val = tr32(MAC_MI_COM);
 814                         break;
 815                 }
 816                 loops -= 1;
 817         }
 818
 819         ret = -EBUSY;
 820         if (loops != 0) {
 821                 *val = frame_val & MI_COM_DATA_MASK;
 822                 ret = 0;
 823         }
 824
 825         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 826                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 827                 udelay(80);
 828         }
 829
 830         return ret;
 831 }
 832
 833 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 834 {
 835         u32 frame_val;
 836         unsigned int loops;
 837         int ret;
 838
 839         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 840             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 841                 return 0;
 842
 843         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 844                 tw32_f(MAC_MI_MODE,
 845                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 846                 udelay(80);
 847         }
 848
 849         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 850                       MI_COM_PHY_ADDR_MASK);
 851         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 852                       MI_COM_REG_ADDR_MASK);
 853         frame_val |= (val & MI_COM_DATA_MASK);
 854         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 855
 856         tw32_f(MAC_MI_COM, frame_val);
 857
 858         loops = PHY_BUSY_LOOPS;
 859         while (loops != 0) {
 860                 udelay(10);
 861                 frame_val = tr32(MAC_MI_COM);
 862                 if ((frame_val & MI_COM_BUSY) == 0) {
 863                         udelay(5);
 864                         frame_val = tr32(MAC_MI_COM);
 865                         break;
 866                 }
 867                 loops -= 1;
 868         }
 869
 870         ret = -EBUSY;
 871         if (loops != 0)
 872                 ret = 0;
 873
 874         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 875                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 876                 udelay(80);
 877         }
 878
 879         return ret;
 880 }
 881
 882 static int tg3_bmcr_reset(struct tg3 *tp)
 883 {
 884         u32 phy_control;
 885         int limit, err;
 886
 887         /* OK, reset it, and poll the BMCR_RESET bit until it
 888          * clears or we time out.
 889          */
 890         phy_control = BMCR_RESET;
 891         err = tg3_writephy(tp, MII_BMCR, phy_control);
 892         if (err != 0)
 893                 return -EBUSY;
 894
 895         limit = 5000;
 896         while (limit--) {
 897                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 898                 if (err != 0)
 899                         return -EBUSY;
 900
 901                 if ((phy_control & BMCR_RESET) == 0) {
 902                         udelay(40);
 903                         break;
 904                 }
 905                 udelay(10);
 906         }
 907         if (limit < 0)
 908                 return -EBUSY;
 909
 910         return 0;
 911 }
 912
 913 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 914 {
 915         struct tg3 *tp = bp->priv;
 916         u32 val;
 917
 918         spin_lock_bh(&tp->lock);
 919
 920         if (tg3_readphy(tp, reg, &val))
 921                 val = -EIO;
 922
 923         spin_unlock_bh(&tp->lock);
 924
 925         return val;
 926 }
 927
 928 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 929 {
 930         struct tg3 *tp = bp->priv;
 931         u32 ret = 0;
 932
 933         spin_lock_bh(&tp->lock);
 934
 935         if (tg3_writephy(tp, reg, val))
 936                 ret = -EIO;
 937
 938         spin_unlock_bh(&tp->lock);
 939
 940         return ret;
 941 }
 942
 943 static int tg3_mdio_reset(struct mii_bus *bp)
 944 {
 945         return 0;
 946 }
 947
 948 static void tg3_mdio_config_5785(struct tg3 *tp)
 949 {
 950         u32 val;
 951         struct phy_device *phydev;
 952
 953         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 954         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 955         case PHY_ID_BCM50610:
 956         case PHY_ID_BCM50610M:
 957                 val = MAC_PHYCFG2_50610_LED_MODES;
 958                 break;
 959         case PHY_ID_BCMAC131:
 960                 val = MAC_PHYCFG2_AC131_LED_MODES;
 961                 break;
 962         case PHY_ID_RTL8211C:
 963                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 964                 break;
 965         case PHY_ID_RTL8201E:
 966                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 967                 break;
 968         default:
 969                 return;
 970         }
 971
 972         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 973                 tw32(MAC_PHYCFG2, val);
 974
 975                 val = tr32(MAC_PHYCFG1);
 976                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 977                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 978                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 979                 tw32(MAC_PHYCFG1, val);
 980
 981                 return;
 982         }
 983
 984         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 985                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 986                        MAC_PHYCFG2_FMODE_MASK_MASK |
 987                        MAC_PHYCFG2_GMODE_MASK_MASK |
 988                        MAC_PHYCFG2_ACT_MASK_MASK   |
 989                        MAC_PHYCFG2_QUAL_MASK_MASK |
 990                        MAC_PHYCFG2_INBAND_ENABLE;
 991
 992         tw32(MAC_PHYCFG2, val);
 993
 994         val = tr32(MAC_PHYCFG1);
 995         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 996                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 997         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
 998                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 999                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1001                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1002         }
1003         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1004                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1005         tw32(MAC_PHYCFG1, val);
1006
1007         val = tr32(MAC_EXT_RGMII_MODE);
1008         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1009                  MAC_RGMII_MODE_RX_QUALITY |
1010                  MAC_RGMII_MODE_RX_ACTIVITY |
1011                  MAC_RGMII_MODE_RX_ENG_DET |
1012                  MAC_RGMII_MODE_TX_ENABLE |
1013                  MAC_RGMII_MODE_TX_LOWPWR |
1014                  MAC_RGMII_MODE_TX_RESET);
1015         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1016                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1017                         val |= MAC_RGMII_MODE_RX_INT_B |
1018                                MAC_RGMII_MODE_RX_QUALITY |
1019                                MAC_RGMII_MODE_RX_ACTIVITY |
1020                                MAC_RGMII_MODE_RX_ENG_DET;
1021                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1022                         val |= MAC_RGMII_MODE_TX_ENABLE |
1023                                MAC_RGMII_MODE_TX_LOWPWR |
1024                                MAC_RGMII_MODE_TX_RESET;
1025         }
1026         tw32(MAC_EXT_RGMII_MODE, val);
1027 }
1028
1029 static void tg3_mdio_start(struct tg3 *tp)
1030 {
1031         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1032         tw32_f(MAC_MI_MODE, tp->mi_mode);
1033         udelay(80);
1034
1035         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1037                 tg3_mdio_config_5785(tp);
1038 }
1039
1040 static int tg3_mdio_init(struct tg3 *tp)
1041 {
1042         int i;
1043         u32 reg;
1044         struct phy_device *phydev;
1045
1046         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
1047                 u32 is_serdes;
1048
1049                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1050
1051                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1052                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1053                 else
1054                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1055                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1056                 if (is_serdes)
1057                         tp->phy_addr += 7;
1058         } else
1059                 tp->phy_addr = TG3_PHY_MII_ADDR;
1060
1061         tg3_mdio_start(tp);
1062
1063         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1064             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1065                 return 0;
1066
1067         tp->mdio_bus = mdiobus_alloc();
1068         if (tp->mdio_bus == NULL)
1069                 return -ENOMEM;
1070
1071         tp->mdio_bus->name     = "tg3 mdio bus";
1072         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1073                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1074         tp->mdio_bus->priv     = tp;
1075         tp->mdio_bus->parent   = &tp->pdev->dev;
1076         tp->mdio_bus->read     = &tg3_mdio_read;
1077         tp->mdio_bus->write    = &tg3_mdio_write;
1078         tp->mdio_bus->reset    = &tg3_mdio_reset;
1079         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1080         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1081
1082         for (i = 0; i < PHY_MAX_ADDR; i++)
1083                 tp->mdio_bus->irq[i] = PHY_POLL;
1084
1085         /* The bus registration will look for all the PHYs on the mdio bus.
1086          * Unfortunately, it does not ensure the PHY is powered up before
1087          * accessing the PHY ID registers.  A chip reset is the
1088          * quickest way to bring the device back to an operational state..
1089          */
1090         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1091                 tg3_bmcr_reset(tp);
1092
1093         i = mdiobus_register(tp->mdio_bus);
1094         if (i) {
1095                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1096                 mdiobus_free(tp->mdio_bus);
1097                 return i;
1098         }
1099
1100         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1101
1102         if (!phydev || !phydev->drv) {
1103                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1104                 mdiobus_unregister(tp->mdio_bus);
1105                 mdiobus_free(tp->mdio_bus);
1106                 return -ENODEV;
1107         }
1108
1109         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1110         case PHY_ID_BCM57780:
1111                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1112                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1113                 break;
1114         case PHY_ID_BCM50610:
1115         case PHY_ID_BCM50610M:
1116                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1117                                      PHY_BRCM_RX_REFCLK_UNUSED |
1118                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1119                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1121                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1122                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1123                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1124                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1125                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1126                 /* fallthru */
1127         case PHY_ID_RTL8211C:
1128                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1129                 break;
1130         case PHY_ID_RTL8201E:
1131         case PHY_ID_BCMAC131:
1132                 phydev->interface = PHY_INTERFACE_MODE_MII;
1133                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1134                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1135                 break;
1136         }
1137
1138         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1139
1140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1141                 tg3_mdio_config_5785(tp);
1142
1143         return 0;
1144 }
1145
1146 static void tg3_mdio_fini(struct tg3 *tp)
1147 {
1148         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1149                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1150                 mdiobus_unregister(tp->mdio_bus);
1151                 mdiobus_free(tp->mdio_bus);
1152         }
1153 }
1154
1155 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1156 {
1157         int err;
1158
1159         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1160         if (err)
1161                 goto done;
1162
1163         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1164         if (err)
1165                 goto done;
1166
1167         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1168                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1169         if (err)
1170                 goto done;
1171
1172         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1173
1174 done:
1175         return err;
1176 }
1177
1178 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1179 {
1180         int err;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1183         if (err)
1184                 goto done;
1185
1186         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1187         if (err)
1188                 goto done;
1189
1190         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1191                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1192         if (err)
1193                 goto done;
1194
1195         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1196
1197 done:
1198         return err;
1199 }
1200
1201 /* tp->lock is held. */
1202 static inline void tg3_generate_fw_event(struct tg3 *tp)
1203 {
1204         u32 val;
1205
1206         val = tr32(GRC_RX_CPU_EVENT);
1207         val |= GRC_RX_CPU_DRIVER_EVENT;
1208         tw32_f(GRC_RX_CPU_EVENT, val);
1209
1210         tp->last_event_jiffies = jiffies;
1211 }
1212
1213 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1214
1215 /* tp->lock is held. */
1216 static void tg3_wait_for_event_ack(struct tg3 *tp)
1217 {
1218         int i;
1219         unsigned int delay_cnt;
1220         long time_remain;
1221
1222         /* If enough time has passed, no wait is necessary. */
1223         time_remain = (long)(tp->last_event_jiffies + 1 +
1224                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1225                       (long)jiffies;
1226         if (time_remain < 0)
1227                 return;
1228
1229         /* Check if we can shorten the wait time. */
1230         delay_cnt = jiffies_to_usecs(time_remain);
1231         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1232                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1233         delay_cnt = (delay_cnt >> 3) + 1;
1234
1235         for (i = 0; i < delay_cnt; i++) {
1236                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1237                         break;
1238                 udelay(8);
1239         }
1240 }
1241
1242 /* tp->lock is held. */
1243 static void tg3_ump_link_report(struct tg3 *tp)
1244 {
1245         u32 reg;
1246         u32 val;
1247
1248         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1249             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1250                 return;
1251
1252         tg3_wait_for_event_ack(tp);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1255
1256         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1257
1258         val = 0;
1259         if (!tg3_readphy(tp, MII_BMCR, &reg))
1260                 val = reg << 16;
1261         if (!tg3_readphy(tp, MII_BMSR, &reg))
1262                 val |= (reg & 0xffff);
1263         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1264
1265         val = 0;
1266         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1267                 val = reg << 16;
1268         if (!tg3_readphy(tp, MII_LPA, &reg))
1269                 val |= (reg & 0xffff);
1270         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1271
1272         val = 0;
1273         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1274                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1275                         val = reg << 16;
1276                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1277                         val |= (reg & 0xffff);
1278         }
1279         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1280
1281         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1282                 val = reg << 16;
1283         else
1284                 val = 0;
1285         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1286
1287         tg3_generate_fw_event(tp);
1288 }
1289
1290 static void tg3_link_report(struct tg3 *tp)
1291 {
1292         if (!netif_carrier_ok(tp->dev)) {
1293                 netif_info(tp, link, tp->dev, "Link is down\n");
1294                 tg3_ump_link_report(tp);
1295         } else if (netif_msg_link(tp)) {
1296                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1297                             (tp->link_config.active_speed == SPEED_1000 ?
1298                              1000 :
1299                              (tp->link_config.active_speed == SPEED_100 ?
1300                               100 : 10)),
1301                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1302                              "full" : "half"));
1303
1304                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1306                             "on" : "off",
1307                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1308                             "on" : "off");
1309                 tg3_ump_link_report(tp);
1310         }
1311 }
1312
1313 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1314 {
1315         u16 miireg;
1316
1317         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1318                 miireg = ADVERTISE_PAUSE_CAP;
1319         else if (flow_ctrl & FLOW_CTRL_TX)
1320                 miireg = ADVERTISE_PAUSE_ASYM;
1321         else if (flow_ctrl & FLOW_CTRL_RX)
1322                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1323         else
1324                 miireg = 0;
1325
1326         return miireg;
1327 }
1328
1329 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1330 {
1331         u16 miireg;
1332
1333         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1334                 miireg = ADVERTISE_1000XPAUSE;
1335         else if (flow_ctrl & FLOW_CTRL_TX)
1336                 miireg = ADVERTISE_1000XPSE_ASYM;
1337         else if (flow_ctrl & FLOW_CTRL_RX)
1338                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1339         else
1340                 miireg = 0;
1341
1342         return miireg;
1343 }
1344
1345 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1346 {
1347         u8 cap = 0;
1348
1349         if (lcladv & ADVERTISE_1000XPAUSE) {
1350                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1351                         if (rmtadv & LPA_1000XPAUSE)
1352                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1353                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1354                                 cap = FLOW_CTRL_RX;
1355                 } else {
1356                         if (rmtadv & LPA_1000XPAUSE)
1357                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1358                 }
1359         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1360                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1361                         cap = FLOW_CTRL_TX;
1362         }
1363
1364         return cap;
1365 }
1366
1367 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1368 {
1369         u8 autoneg;
1370         u8 flowctrl = 0;
1371         u32 old_rx_mode = tp->rx_mode;
1372         u32 old_tx_mode = tp->tx_mode;
1373
1374         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1375                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1376         else
1377                 autoneg = tp->link_config.autoneg;
1378
1379         if (autoneg == AUTONEG_ENABLE &&
1380             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1381                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1382                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1383                 else
1384                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1385         } else
1386                 flowctrl = tp->link_config.flowctrl;
1387
1388         tp->link_config.active_flowctrl = flowctrl;
1389
1390         if (flowctrl & FLOW_CTRL_RX)
1391                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1392         else
1393                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1394
1395         if (old_rx_mode != tp->rx_mode)
1396                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1397
1398         if (flowctrl & FLOW_CTRL_TX)
1399                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1400         else
1401                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1402
1403         if (old_tx_mode != tp->tx_mode)
1404                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1405 }
1406
1407 static void tg3_adjust_link(struct net_device *dev)
1408 {
1409         u8 oldflowctrl, linkmesg = 0;
1410         u32 mac_mode, lcl_adv, rmt_adv;
1411         struct tg3 *tp = netdev_priv(dev);
1412         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1413
1414         spin_lock_bh(&tp->lock);
1415
1416         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1417                                     MAC_MODE_HALF_DUPLEX);
1418
1419         oldflowctrl = tp->link_config.active_flowctrl;
1420
1421         if (phydev->link) {
1422                 lcl_adv = 0;
1423                 rmt_adv = 0;
1424
1425                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1426                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1427                 else if (phydev->speed == SPEED_1000 ||
1428                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1429                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1430                 else
1431                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1432
1433                 if (phydev->duplex == DUPLEX_HALF)
1434                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1435                 else {
1436                         lcl_adv = tg3_advert_flowctrl_1000T(
1437                                   tp->link_config.flowctrl);
1438
1439                         if (phydev->pause)
1440                                 rmt_adv = LPA_PAUSE_CAP;
1441                         if (phydev->asym_pause)
1442                                 rmt_adv |= LPA_PAUSE_ASYM;
1443                 }
1444
1445                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1446         } else
1447                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1448
1449         if (mac_mode != tp->mac_mode) {
1450                 tp->mac_mode = mac_mode;
1451                 tw32_f(MAC_MODE, tp->mac_mode);
1452                 udelay(40);
1453         }
1454
1455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1456                 if (phydev->speed == SPEED_10)
1457                         tw32(MAC_MI_STAT,
1458                              MAC_MI_STAT_10MBPS_MODE |
1459                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460                 else
1461                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462         }
1463
1464         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1465                 tw32(MAC_TX_LENGTHS,
1466                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1467                       (6 << TX_LENGTHS_IPG_SHIFT) |
1468                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1469         else
1470                 tw32(MAC_TX_LENGTHS,
1471                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1472                       (6 << TX_LENGTHS_IPG_SHIFT) |
1473                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1474
1475         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1476             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1477             phydev->speed != tp->link_config.active_speed ||
1478             phydev->duplex != tp->link_config.active_duplex ||
1479             oldflowctrl != tp->link_config.active_flowctrl)
1480                 linkmesg = 1;
1481
1482         tp->link_config.active_speed = phydev->speed;
1483         tp->link_config.active_duplex = phydev->duplex;
1484
1485         spin_unlock_bh(&tp->lock);
1486
1487         if (linkmesg)
1488                 tg3_link_report(tp);
1489 }
1490
1491 static int tg3_phy_init(struct tg3 *tp)
1492 {
1493         struct phy_device *phydev;
1494
1495         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1496                 return 0;
1497
1498         /* Bring the PHY back to a known state. */
1499         tg3_bmcr_reset(tp);
1500
1501         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1502
1503         /* Attach the MAC to the PHY. */
1504         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1505                              phydev->dev_flags, phydev->interface);
1506         if (IS_ERR(phydev)) {
1507                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1508                 return PTR_ERR(phydev);
1509         }
1510
1511         /* Mask with MAC supported features. */
1512         switch (phydev->interface) {
1513         case PHY_INTERFACE_MODE_GMII:
1514         case PHY_INTERFACE_MODE_RGMII:
1515                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1516                         phydev->supported &= (PHY_GBIT_FEATURES |
1517                                               SUPPORTED_Pause |
1518                                               SUPPORTED_Asym_Pause);
1519                         break;
1520                 }
1521                 /* fallthru */
1522         case PHY_INTERFACE_MODE_MII:
1523                 phydev->supported &= (PHY_BASIC_FEATURES |
1524                                       SUPPORTED_Pause |
1525                                       SUPPORTED_Asym_Pause);
1526                 break;
1527         default:
1528                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529                 return -EINVAL;
1530         }
1531
1532         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1533
1534         phydev->advertising = phydev->supported;
1535
1536         return 0;
1537 }
1538
1539 static void tg3_phy_start(struct tg3 *tp)
1540 {
1541         struct phy_device *phydev;
1542
1543         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1544                 return;
1545
1546         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1547
1548         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1549                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1550                 phydev->speed = tp->link_config.orig_speed;
1551                 phydev->duplex = tp->link_config.orig_duplex;
1552                 phydev->autoneg = tp->link_config.orig_autoneg;
1553                 phydev->advertising = tp->link_config.orig_advertising;
1554         }
1555
1556         phy_start(phydev);
1557
1558         phy_start_aneg(phydev);
1559 }
1560
1561 static void tg3_phy_stop(struct tg3 *tp)
1562 {
1563         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1564                 return;
1565
1566         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1567 }
1568
1569 static void tg3_phy_fini(struct tg3 *tp)
1570 {
1571         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1572                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1573                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1574         }
1575 }
1576
1577 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1578 {
1579         int err;
1580
1581         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1582         if (!err)
1583                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1584
1585         return err;
1586 }
1587
1588 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1589 {
1590         int err;
1591
1592         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1593         if (!err)
1594                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1595
1596         return err;
1597 }
1598
1599 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1600 {
1601         u32 phytest;
1602
1603         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1604                 u32 phy;
1605
1606                 tg3_writephy(tp, MII_TG3_FET_TEST,
1607                              phytest | MII_TG3_FET_SHADOW_EN);
1608                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1609                         if (enable)
1610                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1611                         else
1612                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1614                 }
1615                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1616         }
1617 }
1618
1619 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1620 {
1621         u32 reg;
1622
1623         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1624             ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
1625              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1626                 return;
1627
1628         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1629                 tg3_phy_fet_toggle_apd(tp, enable);
1630                 return;
1631         }
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_SCR5_SEL |
1635               MII_TG3_MISC_SHDW_SCR5_LPED |
1636               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1637               MII_TG3_MISC_SHDW_SCR5_SDTL |
1638               MII_TG3_MISC_SHDW_SCR5_C125OE;
1639         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1640                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1641
1642         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1643
1644
1645         reg = MII_TG3_MISC_SHDW_WREN |
1646               MII_TG3_MISC_SHDW_APD_SEL |
1647               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1648         if (enable)
1649                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1650
1651         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1652 }
1653
1654 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1655 {
1656         u32 phy;
1657
1658         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1659             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1660                 return;
1661
1662         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1663                 u32 ephy;
1664
1665                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1666                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1667
1668                         tg3_writephy(tp, MII_TG3_FET_TEST,
1669                                      ephy | MII_TG3_FET_SHADOW_EN);
1670                         if (!tg3_readphy(tp, reg, &phy)) {
1671                                 if (enable)
1672                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1673                                 else
1674                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1675                                 tg3_writephy(tp, reg, phy);
1676                         }
1677                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1678                 }
1679         } else {
1680                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1681                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1682                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1683                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1684                         if (enable)
1685                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1686                         else
1687                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1688                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1689                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1690                 }
1691         }
1692 }
1693
1694 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1695 {
1696         u32 val;
1697
1698         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1699                 return;
1700
1701         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1702             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1703                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1704                              (val | (1 << 15) | (1 << 4)));
1705 }
1706
1707 static void tg3_phy_apply_otp(struct tg3 *tp)
1708 {
1709         u32 otp, phy;
1710
1711         if (!tp->phy_otp)
1712                 return;
1713
1714         otp = tp->phy_otp;
1715
1716         /* Enable SM_DSP clock and tx 6dB coding. */
1717         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1718               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1719               MII_TG3_AUXCTL_ACTL_TX_6DB;
1720         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1721
1722         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1723         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1724         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1725
1726         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1727               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1728         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1729
1730         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1731         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1732         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1733
1734         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1735         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1736
1737         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1739
1740         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1741               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1742         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1743
1744         /* Turn off SM_DSP clock. */
1745         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1746               MII_TG3_AUXCTL_ACTL_TX_6DB;
1747         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1748 }
1749
1750 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1751 {
1752         u32 val;
1753
1754         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1755                 return;
1756
1757         tp->setlpicnt = 0;
1758
1759         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1760             current_link_up == 1 &&
1761             tp->link_config.active_duplex == DUPLEX_FULL &&
1762             (tp->link_config.active_speed == SPEED_100 ||
1763              tp->link_config.active_speed == SPEED_1000)) {
1764                 u32 eeectl;
1765
1766                 if (tp->link_config.active_speed == SPEED_1000)
1767                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1768                 else
1769                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1770
1771                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1772
1773                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1774                                   TG3_CL45_D7_EEERES_STAT, &val);
1775
1776                 switch (val) {
1777                 case TG3_CL45_D7_EEERES_STAT_LP_1000T:
1778                         switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
1779                         case ASIC_REV_5717:
1780                         case ASIC_REV_5719:
1781                         case ASIC_REV_57765:
1782                                 /* Enable SM_DSP clock and tx 6dB coding. */
1783                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1784                                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1785                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1786                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1787
1788                                 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
1789
1790                                 /* Turn off SM_DSP clock. */
1791                                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1792                                       MII_TG3_AUXCTL_ACTL_TX_6DB;
1793                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1794                         }
1795                         /* Fallthrough */
1796                 case TG3_CL45_D7_EEERES_STAT_LP_100TX:
1797                         tp->setlpicnt = 2;
1798                 }
1799         }
1800
1801         if (!tp->setlpicnt) {
1802                 val = tr32(TG3_CPMU_EEE_MODE);
1803                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1804         }
1805 }
1806
1807 static int tg3_wait_macro_done(struct tg3 *tp)
1808 {
1809         int limit = 100;
1810
1811         while (limit--) {
1812                 u32 tmp32;
1813
1814                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1815                         if ((tmp32 & 0x1000) == 0)
1816                                 break;
1817                 }
1818         }
1819         if (limit < 0)
1820                 return -EBUSY;
1821
1822         return 0;
1823 }
1824
1825 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1826 {
1827         static const u32 test_pat[4][6] = {
1828         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1829         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1830         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1831         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1832         };
1833         int chan;
1834
1835         for (chan = 0; chan < 4; chan++) {
1836                 int i;
1837
1838                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1839                              (chan * 0x2000) | 0x0200);
1840                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1841
1842                 for (i = 0; i < 6; i++)
1843                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1844                                      test_pat[chan][i]);
1845
1846                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1847                 if (tg3_wait_macro_done(tp)) {
1848                         *resetp = 1;
1849                         return -EBUSY;
1850                 }
1851
1852                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1853                              (chan * 0x2000) | 0x0200);
1854                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1855                 if (tg3_wait_macro_done(tp)) {
1856                         *resetp = 1;
1857                         return -EBUSY;
1858                 }
1859
1860                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1861                 if (tg3_wait_macro_done(tp)) {
1862                         *resetp = 1;
1863                         return -EBUSY;
1864                 }
1865
1866                 for (i = 0; i < 6; i += 2) {
1867                         u32 low, high;
1868
1869                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1870                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1871                             tg3_wait_macro_done(tp)) {
1872                                 *resetp = 1;
1873                                 return -EBUSY;
1874                         }
1875                         low &= 0x7fff;
1876                         high &= 0x000f;
1877                         if (low != test_pat[chan][i] ||
1878                             high != test_pat[chan][i+1]) {
1879                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1880                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1881                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1882
1883                                 return -EBUSY;
1884                         }
1885                 }
1886         }
1887
1888         return 0;
1889 }
1890
1891 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1892 {
1893         int chan;
1894
1895         for (chan = 0; chan < 4; chan++) {
1896                 int i;
1897
1898                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1899                              (chan * 0x2000) | 0x0200);
1900                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1901                 for (i = 0; i < 6; i++)
1902                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1903                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1904                 if (tg3_wait_macro_done(tp))
1905                         return -EBUSY;
1906         }
1907
1908         return 0;
1909 }
1910
1911 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1912 {
1913         u32 reg32, phy9_orig;
1914         int retries, do_phy_reset, err;
1915
1916         retries = 10;
1917         do_phy_reset = 1;
1918         do {
1919                 if (do_phy_reset) {
1920                         err = tg3_bmcr_reset(tp);
1921                         if (err)
1922                                 return err;
1923                         do_phy_reset = 0;
1924                 }
1925
1926                 /* Disable transmitter and interrupt.  */
1927                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1928                         continue;
1929
1930                 reg32 |= 0x3000;
1931                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1932
1933                 /* Set full-duplex, 1000 mbps.  */
1934                 tg3_writephy(tp, MII_BMCR,
1935                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1936
1937                 /* Set to master mode.  */
1938                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1939                         continue;
1940
1941                 tg3_writephy(tp, MII_TG3_CTRL,
1942                              (MII_TG3_CTRL_AS_MASTER |
1943                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1944
1945                 /* Enable SM_DSP_CLOCK and 6dB.  */
1946                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1947
1948                 /* Block the PHY control access.  */
1949                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1950
1951                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1952                 if (!err)
1953                         break;
1954         } while (--retries);
1955
1956         err = tg3_phy_reset_chanpat(tp);
1957         if (err)
1958                 return err;
1959
1960         tg3_phydsp_write(tp, 0x8005, 0x0000);
1961
1962         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1963         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1964
1965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1966             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1967                 /* Set Extended packet length bit for jumbo frames */
1968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1969         } else {
1970                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1971         }
1972
1973         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1974
1975         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1976                 reg32 &= ~0x3000;
1977                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1978         } else if (!err)
1979                 err = -EBUSY;
1980
1981         return err;
1982 }
1983
1984 /* This will reset the tigon3 PHY if there is no valid
1985  * link unless the FORCE argument is non-zero.
1986  */
1987 static int tg3_phy_reset(struct tg3 *tp)
1988 {
1989         u32 val, cpmuctrl;
1990         int err;
1991
1992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1993                 val = tr32(GRC_MISC_CFG);
1994                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1995                 udelay(40);
1996         }
1997         err  = tg3_readphy(tp, MII_BMSR, &val);
1998         err |= tg3_readphy(tp, MII_BMSR, &val);
1999         if (err != 0)
2000                 return -EBUSY;
2001
2002         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2003                 netif_carrier_off(tp->dev);
2004                 tg3_link_report(tp);
2005         }
2006
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2010                 err = tg3_phy_reset_5703_4_5(tp);
2011                 if (err)
2012                         return err;
2013                 goto out;
2014         }
2015
2016         cpmuctrl = 0;
2017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2018             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2019                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2020                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2021                         tw32(TG3_CPMU_CTRL,
2022                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2023         }
2024
2025         err = tg3_bmcr_reset(tp);
2026         if (err)
2027                 return err;
2028
2029         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2030                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2031                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2032
2033                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2034         }
2035
2036         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2037             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2038                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2039                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2040                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2041                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2042                         udelay(40);
2043                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2044                 }
2045         }
2046
2047         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
2048             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2049                 return 0;
2050
2051         tg3_phy_apply_otp(tp);
2052
2053         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2054                 tg3_phy_toggle_apd(tp, true);
2055         else
2056                 tg3_phy_toggle_apd(tp, false);
2057
2058 out:
2059         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2060                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2061                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2062                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2063                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2064         }
2065         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2066                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2067                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2068         }
2069         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2070                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2071                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2072                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2073                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2074                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2075         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2076                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2077                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2078                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2079                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2080                         tg3_writephy(tp, MII_TG3_TEST1,
2081                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2082                 } else
2083                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2084                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2085         }
2086         /* Set Extended packet length bit (bit 14) on all chips that */
2087         /* support jumbo frames */
2088         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2089                 /* Cannot do read-modify-write on 5401 */
2090                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2091         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2092                 /* Set bit 14 with read-modify-write to preserve other bits */
2093                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2094                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2095                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2096         }
2097
2098         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2099          * jumbo frames transmission.
2100          */
2101         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2102                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2103                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2104                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2105         }
2106
2107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2108                 /* adjust output voltage */
2109                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2110         }
2111
2112         tg3_phy_toggle_automdix(tp, 1);
2113         tg3_phy_set_wirespeed(tp);
2114         return 0;
2115 }
2116
2117 static void tg3_frob_aux_power(struct tg3 *tp)
2118 {
2119         bool need_vaux = false;
2120
2121         /* The GPIOs do something completely different on 57765. */
2122         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2123             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2124             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2125                 return;
2126
2127         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2128              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2129              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2130              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2131             tp->pdev_peer != tp->pdev) {
2132                 struct net_device *dev_peer;
2133
2134                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2135
2136                 /* remove_one() may have been run on the peer. */
2137                 if (dev_peer) {
2138                         struct tg3 *tp_peer = netdev_priv(dev_peer);
2139
2140                         if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
2141                                 return;
2142
2143                         if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2144                             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
2145                                 need_vaux = true;
2146                 }
2147         }
2148
2149         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
2150             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2151                 need_vaux = true;
2152
2153         if (need_vaux) {
2154                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2155                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2157                                     (GRC_LCLCTRL_GPIO_OE0 |
2158                                      GRC_LCLCTRL_GPIO_OE1 |
2159                                      GRC_LCLCTRL_GPIO_OE2 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2161                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2162                                     100);
2163                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2164                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2165                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2166                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2167                                              GRC_LCLCTRL_GPIO_OE1 |
2168                                              GRC_LCLCTRL_GPIO_OE2 |
2169                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2170                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2171                                              tp->grc_local_ctrl;
2172                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2173
2174                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2175                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2176
2177                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2178                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2179                 } else {
2180                         u32 no_gpio2;
2181                         u32 grc_local_ctrl = 0;
2182
2183                         /* Workaround to prevent overdrawing Amps. */
2184                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2185                             ASIC_REV_5714) {
2186                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2187                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2188                                             grc_local_ctrl, 100);
2189                         }
2190
2191                         /* On 5753 and variants, GPIO2 cannot be used. */
2192                         no_gpio2 = tp->nic_sram_data_cfg &
2193                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2194
2195                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2196                                          GRC_LCLCTRL_GPIO_OE1 |
2197                                          GRC_LCLCTRL_GPIO_OE2 |
2198                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2199                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2200                         if (no_gpio2) {
2201                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2202                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2203                         }
2204                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2205                                                     grc_local_ctrl, 100);
2206
2207                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2208
2209                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2210                                                     grc_local_ctrl, 100);
2211
2212                         if (!no_gpio2) {
2213                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2214                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                             grc_local_ctrl, 100);
2216                         }
2217                 }
2218         } else {
2219                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2220                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2221                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2222                                     (GRC_LCLCTRL_GPIO_OE1 |
2223                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2224
2225                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2226                                     GRC_LCLCTRL_GPIO_OE1, 100);
2227
2228                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2229                                     (GRC_LCLCTRL_GPIO_OE1 |
2230                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2231                 }
2232         }
2233 }
2234
2235 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2236 {
2237         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2238                 return 1;
2239         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2240                 if (speed != SPEED_10)
2241                         return 1;
2242         } else if (speed == SPEED_10)
2243                 return 1;
2244
2245         return 0;
2246 }
2247
2248 static int tg3_setup_phy(struct tg3 *, int);
2249
2250 #define RESET_KIND_SHUTDOWN     0
2251 #define RESET_KIND_INIT         1
2252 #define RESET_KIND_SUSPEND      2
2253
2254 static void tg3_write_sig_post_reset(struct tg3 *, int);
2255 static int tg3_halt_cpu(struct tg3 *, u32);
2256
2257 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2258 {
2259         u32 val;
2260
2261         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2262                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2263                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2264                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2265
2266                         sg_dig_ctrl |=
2267                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2268                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2269                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2270                 }
2271                 return;
2272         }
2273
2274         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2275                 tg3_bmcr_reset(tp);
2276                 val = tr32(GRC_MISC_CFG);
2277                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2278                 udelay(40);
2279                 return;
2280         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2281                 u32 phytest;
2282                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2283                         u32 phy;
2284
2285                         tg3_writephy(tp, MII_ADVERTISE, 0);
2286                         tg3_writephy(tp, MII_BMCR,
2287                                      BMCR_ANENABLE | BMCR_ANRESTART);
2288
2289                         tg3_writephy(tp, MII_TG3_FET_TEST,
2290                                      phytest | MII_TG3_FET_SHADOW_EN);
2291                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2292                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2293                                 tg3_writephy(tp,
2294                                              MII_TG3_FET_SHDW_AUXMODE4,
2295                                              phy);
2296                         }
2297                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2298                 }
2299                 return;
2300         } else if (do_low_power) {
2301                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2302                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2303
2304                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2305                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2306                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2307                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2308                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2309         }
2310
2311         /* The PHY should not be powered down on some chips because
2312          * of bugs.
2313          */
2314         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2315             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2316             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2317              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2318                 return;
2319
2320         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2321             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2322                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2323                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2324                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2325                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2326         }
2327
2328         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2329 }
2330
2331 /* tp->lock is held. */
2332 static int tg3_nvram_lock(struct tg3 *tp)
2333 {
2334         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2335                 int i;
2336
2337                 if (tp->nvram_lock_cnt == 0) {
2338                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2339                         for (i = 0; i < 8000; i++) {
2340                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2341                                         break;
2342                                 udelay(20);
2343                         }
2344                         if (i == 8000) {
2345                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2346                                 return -ENODEV;
2347                         }
2348                 }
2349                 tp->nvram_lock_cnt++;
2350         }
2351         return 0;
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_nvram_unlock(struct tg3 *tp)
2356 {
2357         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2358                 if (tp->nvram_lock_cnt > 0)
2359                         tp->nvram_lock_cnt--;
2360                 if (tp->nvram_lock_cnt == 0)
2361                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_enable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2373         }
2374 }
2375
2376 /* tp->lock is held. */
2377 static void tg3_disable_nvram_access(struct tg3 *tp)
2378 {
2379         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2380             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2381                 u32 nvaccess = tr32(NVRAM_ACCESS);
2382
2383                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2384         }
2385 }
2386
2387 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2388                                         u32 offset, u32 *val)
2389 {
2390         u32 tmp;
2391         int i;
2392
2393         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2394                 return -EINVAL;
2395
2396         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2397                                         EEPROM_ADDR_DEVID_MASK |
2398                                         EEPROM_ADDR_READ);
2399         tw32(GRC_EEPROM_ADDR,
2400              tmp |
2401              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2402              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2403               EEPROM_ADDR_ADDR_MASK) |
2404              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2405
2406         for (i = 0; i < 1000; i++) {
2407                 tmp = tr32(GRC_EEPROM_ADDR);
2408
2409                 if (tmp & EEPROM_ADDR_COMPLETE)
2410                         break;
2411                 msleep(1);
2412         }
2413         if (!(tmp & EEPROM_ADDR_COMPLETE))
2414                 return -EBUSY;
2415
2416         tmp = tr32(GRC_EEPROM_DATA);
2417
2418         /*
2419          * The data will always be opposite the native endian
2420          * format.  Perform a blind byteswap to compensate.
2421          */
2422         *val = swab32(tmp);
2423
2424         return 0;
2425 }
2426
2427 #define NVRAM_CMD_TIMEOUT 10000
2428
2429 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2430 {
2431         int i;
2432
2433         tw32(NVRAM_CMD, nvram_cmd);
2434         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2435                 udelay(10);
2436                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2437                         udelay(10);
2438                         break;
2439                 }
2440         }
2441
2442         if (i == NVRAM_CMD_TIMEOUT)
2443                 return -EBUSY;
2444
2445         return 0;
2446 }
2447
2448 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2449 {
2450         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2451             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2452             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2453            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2454             (tp->nvram_jedecnum == JEDEC_ATMEL))
2455
2456                 addr = ((addr / tp->nvram_pagesize) <<
2457                         ATMEL_AT45DB0X1B_PAGE_POS) +
2458                        (addr % tp->nvram_pagesize);
2459
2460         return addr;
2461 }
2462
2463 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2464 {
2465         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2466             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2467             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2468            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2469             (tp->nvram_jedecnum == JEDEC_ATMEL))
2470
2471                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2472                         tp->nvram_pagesize) +
2473                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2474
2475         return addr;
2476 }
2477
2478 /* NOTE: Data read in from NVRAM is byteswapped according to
2479  * the byteswapping settings for all other register accesses.
2480  * tg3 devices are BE devices, so on a BE machine, the data
2481  * returned will be exactly as it is seen in NVRAM.  On a LE
2482  * machine, the 32-bit value will be byteswapped.
2483  */
2484 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2485 {
2486         int ret;
2487
2488         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2489                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2490
2491         offset = tg3_nvram_phys_addr(tp, offset);
2492
2493         if (offset > NVRAM_ADDR_MSK)
2494                 return -EINVAL;
2495
2496         ret = tg3_nvram_lock(tp);
2497         if (ret)
2498                 return ret;
2499
2500         tg3_enable_nvram_access(tp);
2501
2502         tw32(NVRAM_ADDR, offset);
2503         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2504                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2505
2506         if (ret == 0)
2507                 *val = tr32(NVRAM_RDDATA);
2508
2509         tg3_disable_nvram_access(tp);
2510
2511         tg3_nvram_unlock(tp);
2512
2513         return ret;
2514 }
2515
2516 /* Ensures NVRAM data is in bytestream format. */
2517 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2518 {
2519         u32 v;
2520         int res = tg3_nvram_read(tp, offset, &v);
2521         if (!res)
2522                 *val = cpu_to_be32(v);
2523         return res;
2524 }
2525
2526 /* tp->lock is held. */
2527 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2528 {
2529         u32 addr_high, addr_low;
2530         int i;
2531
2532         addr_high = ((tp->dev->dev_addr[0] << 8) |
2533                      tp->dev->dev_addr[1]);
2534         addr_low = ((tp->dev->dev_addr[2] << 24) |
2535                     (tp->dev->dev_addr[3] << 16) |
2536                     (tp->dev->dev_addr[4] <<  8) |
2537                     (tp->dev->dev_addr[5] <<  0));
2538         for (i = 0; i < 4; i++) {
2539                 if (i == 1 && skip_mac_1)
2540                         continue;
2541                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2542                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2543         }
2544
2545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2546             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2547                 for (i = 0; i < 12; i++) {
2548                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2549                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2550                 }
2551         }
2552
2553         addr_high = (tp->dev->dev_addr[0] +
2554                      tp->dev->dev_addr[1] +
2555                      tp->dev->dev_addr[2] +
2556                      tp->dev->dev_addr[3] +
2557                      tp->dev->dev_addr[4] +
2558                      tp->dev->dev_addr[5]) &
2559                 TX_BACKOFF_SEED_MASK;
2560         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2561 }
2562
2563 static void tg3_enable_register_access(struct tg3 *tp)
2564 {
2565         /*
2566          * Make sure register accesses (indirect or otherwise) will function
2567          * correctly.
2568          */
2569         pci_write_config_dword(tp->pdev,
2570                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2571 }
2572
2573 static int tg3_power_up(struct tg3 *tp)
2574 {
2575         tg3_enable_register_access(tp);
2576
2577         pci_set_power_state(tp->pdev, PCI_D0);
2578
2579         /* Switch out of Vaux if it is a NIC */
2580         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2581                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2582
2583         return 0;
2584 }
2585
2586 static int tg3_power_down_prepare(struct tg3 *tp)
2587 {
2588         u32 misc_host_ctrl;
2589         bool device_should_wake, do_low_power;
2590
2591         tg3_enable_register_access(tp);
2592
2593         /* Restore the CLKREQ setting. */
2594         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2595                 u16 lnkctl;
2596
2597                 pci_read_config_word(tp->pdev,
2598                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2599                                      &lnkctl);
2600                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2601                 pci_write_config_word(tp->pdev,
2602                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2603                                       lnkctl);
2604         }
2605
2606         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2607         tw32(TG3PCI_MISC_HOST_CTRL,
2608              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2609
2610         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2611                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2612
2613         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2614                 do_low_power = false;
2615                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2616                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2617                         struct phy_device *phydev;
2618                         u32 phyid, advertising;
2619
2620                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2621
2622                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2623
2624                         tp->link_config.orig_speed = phydev->speed;
2625                         tp->link_config.orig_duplex = phydev->duplex;
2626                         tp->link_config.orig_autoneg = phydev->autoneg;
2627                         tp->link_config.orig_advertising = phydev->advertising;
2628
2629                         advertising = ADVERTISED_TP |
2630                                       ADVERTISED_Pause |
2631                                       ADVERTISED_Autoneg |
2632                                       ADVERTISED_10baseT_Half;
2633
2634                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2635                             device_should_wake) {
2636                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2637                                         advertising |=
2638                                                 ADVERTISED_100baseT_Half |
2639                                                 ADVERTISED_100baseT_Full |
2640                                                 ADVERTISED_10baseT_Full;
2641                                 else
2642                                         advertising |= ADVERTISED_10baseT_Full;
2643                         }
2644
2645                         phydev->advertising = advertising;
2646
2647                         phy_start_aneg(phydev);
2648
2649                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2650                         if (phyid != PHY_ID_BCMAC131) {
2651                                 phyid &= PHY_BCM_OUI_MASK;
2652                                 if (phyid == PHY_BCM_OUI_1 ||
2653                                     phyid == PHY_BCM_OUI_2 ||
2654                                     phyid == PHY_BCM_OUI_3)
2655                                         do_low_power = true;
2656                         }
2657                 }
2658         } else {
2659                 do_low_power = true;
2660
2661                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2662                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2663                         tp->link_config.orig_speed = tp->link_config.speed;
2664                         tp->link_config.orig_duplex = tp->link_config.duplex;
2665                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2666                 }
2667
2668                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2669                         tp->link_config.speed = SPEED_10;
2670                         tp->link_config.duplex = DUPLEX_HALF;
2671                         tp->link_config.autoneg = AUTONEG_ENABLE;
2672                         tg3_setup_phy(tp, 0);
2673                 }
2674         }
2675
2676         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2677                 u32 val;
2678
2679                 val = tr32(GRC_VCPU_EXT_CTRL);
2680                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2681         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2682                 int i;
2683                 u32 val;
2684
2685                 for (i = 0; i < 200; i++) {
2686                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2687                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2688                                 break;
2689                         msleep(1);
2690                 }
2691         }
2692         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2693                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2694                                                      WOL_DRV_STATE_SHUTDOWN |
2695                                                      WOL_DRV_WOL |
2696                                                      WOL_SET_MAGIC_PKT);
2697
2698         if (device_should_wake) {
2699                 u32 mac_mode;
2700
2701                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2702                         if (do_low_power) {
2703                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2704                                 udelay(40);
2705                         }
2706
2707                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2708                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2709                         else
2710                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2711
2712                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2713                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2714                             ASIC_REV_5700) {
2715                                 u32 speed = (tp->tg3_flags &
2716                                              TG3_FLAG_WOL_SPEED_100MB) ?
2717                                              SPEED_100 : SPEED_10;
2718                                 if (tg3_5700_link_polarity(tp, speed))
2719                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2720                                 else
2721                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2722                         }
2723                 } else {
2724                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2725                 }
2726
2727                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2728                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2729
2730                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2731                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2732                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2733                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2734                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2735                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2736
2737                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2738                         mac_mode |= MAC_MODE_APE_TX_EN |
2739                                     MAC_MODE_APE_RX_EN |
2740                                     MAC_MODE_TDE_ENABLE;
2741
2742                 tw32_f(MAC_MODE, mac_mode);
2743                 udelay(100);
2744
2745                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2746                 udelay(10);
2747         }
2748
2749         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2750             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2751              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2752                 u32 base_val;
2753
2754                 base_val = tp->pci_clock_ctrl;
2755                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2756                              CLOCK_CTRL_TXCLK_DISABLE);
2757
2758                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2759                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2760         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2761                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2762                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2763                 /* do nothing */
2764         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2765                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2766                 u32 newbits1, newbits2;
2767
2768                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2769                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2770                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2771                                     CLOCK_CTRL_TXCLK_DISABLE |
2772                                     CLOCK_CTRL_ALTCLK);
2773                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2774                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2775                         newbits1 = CLOCK_CTRL_625_CORE;
2776                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2777                 } else {
2778                         newbits1 = CLOCK_CTRL_ALTCLK;
2779                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2780                 }
2781
2782                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2783                             40);
2784
2785                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2786                             40);
2787
2788                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2789                         u32 newbits3;
2790
2791                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2792                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2793                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2794                                             CLOCK_CTRL_TXCLK_DISABLE |
2795                                             CLOCK_CTRL_44MHZ_CORE);
2796                         } else {
2797                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2798                         }
2799
2800                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2801                                     tp->pci_clock_ctrl | newbits3, 40);
2802                 }
2803         }
2804
2805         if (!(device_should_wake) &&
2806             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2807                 tg3_power_down_phy(tp, do_low_power);
2808
2809         tg3_frob_aux_power(tp);
2810
2811         /* Workaround for unstable PLL clock */
2812         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2813             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2814                 u32 val = tr32(0x7d00);
2815
2816                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2817                 tw32(0x7d00, val);
2818                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2819                         int err;
2820
2821                         err = tg3_nvram_lock(tp);
2822                         tg3_halt_cpu(tp, RX_CPU_BASE);
2823                         if (!err)
2824                                 tg3_nvram_unlock(tp);
2825                 }
2826         }
2827
2828         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2829
2830         return 0;
2831 }
2832
2833 static void tg3_power_down(struct tg3 *tp)
2834 {
2835         tg3_power_down_prepare(tp);
2836
2837         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2838         pci_set_power_state(tp->pdev, PCI_D3hot);
2839 }
2840
2841 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2842 {
2843         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2844         case MII_TG3_AUX_STAT_10HALF:
2845                 *speed = SPEED_10;
2846                 *duplex = DUPLEX_HALF;
2847                 break;
2848
2849         case MII_TG3_AUX_STAT_10FULL:
2850                 *speed = SPEED_10;
2851                 *duplex = DUPLEX_FULL;
2852                 break;
2853
2854         case MII_TG3_AUX_STAT_100HALF:
2855                 *speed = SPEED_100;
2856                 *duplex = DUPLEX_HALF;
2857                 break;
2858
2859         case MII_TG3_AUX_STAT_100FULL:
2860                 *speed = SPEED_100;
2861                 *duplex = DUPLEX_FULL;
2862                 break;
2863
2864         case MII_TG3_AUX_STAT_1000HALF:
2865                 *speed = SPEED_1000;
2866                 *duplex = DUPLEX_HALF;
2867                 break;
2868
2869         case MII_TG3_AUX_STAT_1000FULL:
2870                 *speed = SPEED_1000;
2871                 *duplex = DUPLEX_FULL;
2872                 break;
2873
2874         default:
2875                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2876                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2877                                  SPEED_10;
2878                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2879                                   DUPLEX_HALF;
2880                         break;
2881                 }
2882                 *speed = SPEED_INVALID;
2883                 *duplex = DUPLEX_INVALID;
2884                 break;
2885         }
2886 }
2887
2888 static void tg3_phy_copper_begin(struct tg3 *tp)
2889 {
2890         u32 new_adv;
2891         int i;
2892
2893         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2894                 /* Entering low power mode.  Disable gigabit and
2895                  * 100baseT advertisements.
2896                  */
2897                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2898
2899                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2900                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2901                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2902                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2903
2904                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2905         } else if (tp->link_config.speed == SPEED_INVALID) {
2906                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2907                         tp->link_config.advertising &=
2908                                 ~(ADVERTISED_1000baseT_Half |
2909                                   ADVERTISED_1000baseT_Full);
2910
2911                 new_adv = ADVERTISE_CSMA;
2912                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2913                         new_adv |= ADVERTISE_10HALF;
2914                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2915                         new_adv |= ADVERTISE_10FULL;
2916                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2917                         new_adv |= ADVERTISE_100HALF;
2918                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2919                         new_adv |= ADVERTISE_100FULL;
2920
2921                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2922
2923                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2924
2925                 if (tp->link_config.advertising &
2926                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2927                         new_adv = 0;
2928                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2929                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2930                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2931                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2932                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2933                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2934                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2935                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2936                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2937                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2938                 } else {
2939                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2940                 }
2941         } else {
2942                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2943                 new_adv |= ADVERTISE_CSMA;
2944
2945                 /* Asking for a specific link mode. */
2946                 if (tp->link_config.speed == SPEED_1000) {
2947                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2948
2949                         if (tp->link_config.duplex == DUPLEX_FULL)
2950                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2951                         else
2952                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2953                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2954                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2955                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2956                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2957                 } else {
2958                         if (tp->link_config.speed == SPEED_100) {
2959                                 if (tp->link_config.duplex == DUPLEX_FULL)
2960                                         new_adv |= ADVERTISE_100FULL;
2961                                 else
2962                                         new_adv |= ADVERTISE_100HALF;
2963                         } else {
2964                                 if (tp->link_config.duplex == DUPLEX_FULL)
2965                                         new_adv |= ADVERTISE_10FULL;
2966                                 else
2967                                         new_adv |= ADVERTISE_10HALF;
2968                         }
2969                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2970
2971                         new_adv = 0;
2972                 }
2973
2974                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2975         }
2976
2977         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2978                 u32 val;
2979
2980                 tw32(TG3_CPMU_EEE_MODE,
2981                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2982
2983                 /* Enable SM_DSP clock and tx 6dB coding. */
2984                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2985                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2986                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2988
2989                 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2990                 case ASIC_REV_5717:
2991                 case ASIC_REV_57765:
2992                         if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2993                                 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2994                                                  MII_TG3_DSP_CH34TP2_HIBW01);
2995                         /* Fall through */
2996                 case ASIC_REV_5719:
2997                         val = MII_TG3_DSP_TAP26_ALNOKO |
2998                               MII_TG3_DSP_TAP26_RMRXSTO |
2999                               MII_TG3_DSP_TAP26_OPCSINPT;
3000                         tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3001                 }
3002
3003                 val = 0;
3004                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3005                         /* Advertise 100-BaseTX EEE ability */
3006                         if (tp->link_config.advertising &
3007                             ADVERTISED_100baseT_Full)
3008                                 val |= MDIO_AN_EEE_ADV_100TX;
3009                         /* Advertise 1000-BaseT EEE ability */
3010                         if (tp->link_config.advertising &
3011                             ADVERTISED_1000baseT_Full)
3012                                 val |= MDIO_AN_EEE_ADV_1000T;
3013                 }
3014                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3015
3016                 /* Turn off SM_DSP clock. */
3017                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3018                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3019                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3020         }
3021
3022         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3023             tp->link_config.speed != SPEED_INVALID) {
3024                 u32 bmcr, orig_bmcr;
3025
3026                 tp->link_config.active_speed = tp->link_config.speed;
3027                 tp->link_config.active_duplex = tp->link_config.duplex;
3028
3029                 bmcr = 0;
3030                 switch (tp->link_config.speed) {
3031                 default:
3032                 case SPEED_10:
3033                         break;
3034
3035                 case SPEED_100:
3036                         bmcr |= BMCR_SPEED100;
3037                         break;
3038
3039                 case SPEED_1000:
3040                         bmcr |= TG3_BMCR_SPEED1000;
3041                         break;
3042                 }
3043
3044                 if (tp->link_config.duplex == DUPLEX_FULL)
3045                         bmcr |= BMCR_FULLDPLX;
3046
3047                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3048                     (bmcr != orig_bmcr)) {
3049                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3050                         for (i = 0; i < 1500; i++) {
3051                                 u32 tmp;
3052
3053                                 udelay(10);
3054                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3055                                     tg3_readphy(tp, MII_BMSR, &tmp))
3056                                         continue;
3057                                 if (!(tmp & BMSR_LSTATUS)) {
3058                                         udelay(40);
3059                                         break;
3060                                 }
3061                         }
3062                         tg3_writephy(tp, MII_BMCR, bmcr);
3063                         udelay(40);
3064                 }
3065         } else {
3066                 tg3_writephy(tp, MII_BMCR,
3067                              BMCR_ANENABLE | BMCR_ANRESTART);
3068         }
3069 }
3070
3071 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3072 {
3073         int err;
3074
3075         /* Turn off tap power management. */
3076         /* Set Extended packet length bit */
3077         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3078
3079         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3080         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3081         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3082         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3083         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3084
3085         udelay(40);
3086
3087         return err;
3088 }
3089
3090 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3091 {
3092         u32 adv_reg, all_mask = 0;
3093
3094         if (mask & ADVERTISED_10baseT_Half)
3095                 all_mask |= ADVERTISE_10HALF;
3096         if (mask & ADVERTISED_10baseT_Full)
3097                 all_mask |= ADVERTISE_10FULL;
3098         if (mask & ADVERTISED_100baseT_Half)
3099                 all_mask |= ADVERTISE_100HALF;
3100         if (mask & ADVERTISED_100baseT_Full)
3101                 all_mask |= ADVERTISE_100FULL;
3102
3103         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3104                 return 0;
3105
3106         if ((adv_reg & all_mask) != all_mask)
3107                 return 0;
3108         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3109                 u32 tg3_ctrl;
3110
3111                 all_mask = 0;
3112                 if (mask & ADVERTISED_1000baseT_Half)
3113                         all_mask |= ADVERTISE_1000HALF;
3114                 if (mask & ADVERTISED_1000baseT_Full)
3115                         all_mask |= ADVERTISE_1000FULL;
3116
3117                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3118                         return 0;
3119
3120                 if ((tg3_ctrl & all_mask) != all_mask)
3121                         return 0;
3122         }
3123         return 1;
3124 }
3125
3126 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3127 {
3128         u32 curadv, reqadv;
3129
3130         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3131                 return 1;
3132
3133         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3134         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3135
3136         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3137                 if (curadv != reqadv)
3138                         return 0;
3139
3140                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3141                         tg3_readphy(tp, MII_LPA, rmtadv);
3142         } else {
3143                 /* Reprogram the advertisement register, even if it
3144                  * does not affect the current link.  If the link
3145                  * gets renegotiated in the future, we can save an
3146                  * additional renegotiation cycle by advertising
3147                  * it correctly in the first place.
3148                  */
3149                 if (curadv != reqadv) {
3150                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3151                                      ADVERTISE_PAUSE_ASYM);
3152                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3153                 }
3154         }
3155
3156         return 1;
3157 }
3158
3159 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3160 {
3161         int current_link_up;
3162         u32 bmsr, val;
3163         u32 lcl_adv, rmt_adv;
3164         u16 current_speed;
3165         u8 current_duplex;
3166         int i, err;
3167
3168         tw32(MAC_EVENT, 0);
3169
3170         tw32_f(MAC_STATUS,
3171              (MAC_STATUS_SYNC_CHANGED |
3172               MAC_STATUS_CFG_CHANGED |
3173               MAC_STATUS_MI_COMPLETION |
3174               MAC_STATUS_LNKSTATE_CHANGED));
3175         udelay(40);
3176
3177         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3178                 tw32_f(MAC_MI_MODE,
3179                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3180                 udelay(80);
3181         }
3182
3183         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3184
3185         /* Some third-party PHYs need to be reset on link going
3186          * down.
3187          */
3188         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3189              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3190              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3191             netif_carrier_ok(tp->dev)) {
3192                 tg3_readphy(tp, MII_BMSR, &bmsr);
3193                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3194                     !(bmsr & BMSR_LSTATUS))
3195                         force_reset = 1;
3196         }
3197         if (force_reset)
3198                 tg3_phy_reset(tp);
3199
3200         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3201                 tg3_readphy(tp, MII_BMSR, &bmsr);
3202                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3203                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3204                         bmsr = 0;
3205
3206                 if (!(bmsr & BMSR_LSTATUS)) {
3207                         err = tg3_init_5401phy_dsp(tp);
3208                         if (err)
3209                                 return err;
3210
3211                         tg3_readphy(tp, MII_BMSR, &bmsr);
3212                         for (i = 0; i < 1000; i++) {
3213                                 udelay(10);
3214                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3215                                     (bmsr & BMSR_LSTATUS)) {
3216                                         udelay(40);
3217                                         break;
3218                                 }
3219                         }
3220
3221                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3222                             TG3_PHY_REV_BCM5401_B0 &&
3223                             !(bmsr & BMSR_LSTATUS) &&
3224                             tp->link_config.active_speed == SPEED_1000) {
3225                                 err = tg3_phy_reset(tp);
3226                                 if (!err)
3227                                         err = tg3_init_5401phy_dsp(tp);
3228                                 if (err)
3229                                         return err;
3230                         }
3231                 }
3232         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3233                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3234                 /* 5701 {A0,B0} CRC bug workaround */
3235                 tg3_writephy(tp, 0x15, 0x0a75);
3236                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3237                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3238                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3239         }
3240
3241         /* Clear pending interrupts... */
3242         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3243         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3244
3245         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3246                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3247         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3248                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3249
3250         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3251             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3252                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3253                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3254                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3255                 else
3256                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3257         }
3258
3259         current_link_up = 0;
3260         current_speed = SPEED_INVALID;
3261         current_duplex = DUPLEX_INVALID;
3262
3263         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3264                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3265                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3266                 if (!(val & (1 << 10))) {
3267                         val |= (1 << 10);
3268                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3269                         goto relink;
3270                 }
3271         }
3272
3273         bmsr = 0;
3274         for (i = 0; i < 100; i++) {
3275                 tg3_readphy(tp, MII_BMSR, &bmsr);
3276                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3277                     (bmsr & BMSR_LSTATUS))
3278                         break;
3279                 udelay(40);
3280         }
3281
3282         if (bmsr & BMSR_LSTATUS) {
3283                 u32 aux_stat, bmcr;
3284
3285                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3286                 for (i = 0; i < 2000; i++) {
3287                         udelay(10);
3288                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3289                             aux_stat)
3290                                 break;
3291                 }
3292
3293                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3294                                              &current_speed,
3295                                              &current_duplex);
3296
3297                 bmcr = 0;
3298                 for (i = 0; i < 200; i++) {
3299                         tg3_readphy(tp, MII_BMCR, &bmcr);
3300                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3301                                 continue;
3302                         if (bmcr && bmcr != 0x7fff)
3303                                 break;
3304                         udelay(10);
3305                 }
3306
3307                 lcl_adv = 0;
3308                 rmt_adv = 0;
3309
3310                 tp->link_config.active_speed = current_speed;
3311                 tp->link_config.active_duplex = current_duplex;
3312
3313                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3314                         if ((bmcr & BMCR_ANENABLE) &&
3315                             tg3_copper_is_advertising_all(tp,
3316                                                 tp->link_config.advertising)) {
3317                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3318                                                                   &rmt_adv))
3319                                         current_link_up = 1;
3320                         }
3321                 } else {
3322                         if (!(bmcr & BMCR_ANENABLE) &&
3323                             tp->link_config.speed == current_speed &&
3324                             tp->link_config.duplex == current_duplex &&
3325                             tp->link_config.flowctrl ==
3326                             tp->link_config.active_flowctrl) {
3327                                 current_link_up = 1;
3328                         }
3329                 }
3330
3331                 if (current_link_up == 1 &&
3332                     tp->link_config.active_duplex == DUPLEX_FULL)
3333                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3334         }
3335
3336 relink:
3337         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3338                 tg3_phy_copper_begin(tp);
3339
3340                 tg3_readphy(tp, MII_BMSR, &bmsr);
3341                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3342                     (bmsr & BMSR_LSTATUS))
3343                         current_link_up = 1;
3344         }
3345
3346         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3347         if (current_link_up == 1) {
3348                 if (tp->link_config.active_speed == SPEED_100 ||
3349                     tp->link_config.active_speed == SPEED_10)
3350                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3351                 else
3352                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3353         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3354                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3355         else
3356                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3357
3358         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3359         if (tp->link_config.active_duplex == DUPLEX_HALF)
3360                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3361
3362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3363                 if (current_link_up == 1 &&
3364                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3365                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3366                 else
3367                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3368         }
3369
3370         /* ??? Without this setting Netgear GA302T PHY does not
3371          * ??? send/receive packets...
3372          */
3373         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3374             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3375                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3376                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3377                 udelay(80);
3378         }
3379
3380         tw32_f(MAC_MODE, tp->mac_mode);
3381         udelay(40);
3382
3383         tg3_phy_eee_adjust(tp, current_link_up);
3384
3385         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3386                 /* Polled via timer. */
3387                 tw32_f(MAC_EVENT, 0);
3388         } else {
3389                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3390         }
3391         udelay(40);
3392
3393         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3394             current_link_up == 1 &&
3395             tp->link_config.active_speed == SPEED_1000 &&
3396             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3397              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3398                 udelay(120);
3399                 tw32_f(MAC_STATUS,
3400                      (MAC_STATUS_SYNC_CHANGED |
3401                       MAC_STATUS_CFG_CHANGED));
3402                 udelay(40);
3403                 tg3_write_mem(tp,
3404                               NIC_SRAM_FIRMWARE_MBOX,
3405                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3406         }
3407
3408         /* Prevent send BD corruption. */
3409         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3410                 u16 oldlnkctl, newlnkctl;
3411
3412                 pci_read_config_word(tp->pdev,
3413                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3414                                      &oldlnkctl);
3415                 if (tp->link_config.active_speed == SPEED_100 ||
3416                     tp->link_config.active_speed == SPEED_10)
3417                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3418                 else
3419                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3420                 if (newlnkctl != oldlnkctl)
3421                         pci_write_config_word(tp->pdev,
3422                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3423                                               newlnkctl);
3424         }
3425
3426         if (current_link_up != netif_carrier_ok(tp->dev)) {
3427                 if (current_link_up)
3428                         netif_carrier_on(tp->dev);
3429                 else
3430                         netif_carrier_off(tp->dev);
3431                 tg3_link_report(tp);
3432         }
3433
3434         return 0;
3435 }
3436
3437 struct tg3_fiber_aneginfo {
3438         int state;
3439 #define ANEG_STATE_UNKNOWN              0
3440 #define ANEG_STATE_AN_ENABLE            1
3441 #define ANEG_STATE_RESTART_INIT         2
3442 #define ANEG_STATE_RESTART              3
3443 #define ANEG_STATE_DISABLE_LINK_OK      4
3444 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3445 #define ANEG_STATE_ABILITY_DETECT       6
3446 #define ANEG_STATE_ACK_DETECT_INIT      7
3447 #define ANEG_STATE_ACK_DETECT           8
3448 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3449 #define ANEG_STATE_COMPLETE_ACK         10
3450 #define ANEG_STATE_IDLE_DETECT_INIT     11
3451 #define ANEG_STATE_IDLE_DETECT          12
3452 #define ANEG_STATE_LINK_OK              13
3453 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3454 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3455
3456         u32 flags;
3457 #define MR_AN_ENABLE            0x00000001
3458 #define MR_RESTART_AN           0x00000002
3459 #define MR_AN_COMPLETE          0x00000004
3460 #define MR_PAGE_RX              0x00000008
3461 #define MR_NP_LOADED            0x00000010
3462 #define MR_TOGGLE_TX            0x00000020
3463 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3464 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3465 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3466 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3467 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3468 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3469 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3470 #define MR_TOGGLE_RX            0x00002000
3471 #define MR_NP_RX                0x00004000
3472
3473 #define MR_LINK_OK              0x80000000
3474
3475         unsigned long link_time, cur_time;
3476
3477         u32 ability_match_cfg;
3478         int ability_match_count;
3479
3480         char ability_match, idle_match, ack_match;
3481
3482         u32 txconfig, rxconfig;
3483 #define ANEG_CFG_NP             0x00000080
3484 #define ANEG_CFG_ACK            0x00000040
3485 #define ANEG_CFG_RF2            0x00000020
3486 #define ANEG_CFG_RF1            0x00000010
3487 #define ANEG_CFG_PS2            0x00000001
3488 #define ANEG_CFG_PS1            0x00008000
3489 #define ANEG_CFG_HD             0x00004000
3490 #define ANEG_CFG_FD             0x00002000
3491 #define ANEG_CFG_INVAL          0x00001f06
3492
3493 };
3494 #define ANEG_OK         0
3495 #define ANEG_DONE       1
3496 #define ANEG_TIMER_ENAB 2
3497 #define ANEG_FAILED     -1
3498
3499 #define ANEG_STATE_SETTLE_TIME  10000
3500
3501 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3502                                    struct tg3_fiber_aneginfo *ap)
3503 {
3504         u16 flowctrl;
3505         unsigned long delta;
3506         u32 rx_cfg_reg;
3507         int ret;
3508
3509         if (ap->state == ANEG_STATE_UNKNOWN) {
3510                 ap->rxconfig = 0;
3511                 ap->link_time = 0;
3512                 ap->cur_time = 0;
3513                 ap->ability_match_cfg = 0;
3514                 ap->ability_match_count = 0;
3515                 ap->ability_match = 0;
3516                 ap->idle_match = 0;
3517                 ap->ack_match = 0;
3518         }
3519         ap->cur_time++;
3520
3521         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3522                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3523
3524                 if (rx_cfg_reg != ap->ability_match_cfg) {
3525                         ap->ability_match_cfg = rx_cfg_reg;
3526                         ap->ability_match = 0;
3527                         ap->ability_match_count = 0;
3528                 } else {
3529                         if (++ap->ability_match_count > 1) {
3530                                 ap->ability_match = 1;
3531                                 ap->ability_match_cfg = rx_cfg_reg;
3532                         }
3533                 }
3534                 if (rx_cfg_reg & ANEG_CFG_ACK)
3535                         ap->ack_match = 1;
3536                 else
3537                         ap->ack_match = 0;
3538
3539                 ap->idle_match = 0;
3540         } else {
3541                 ap->idle_match = 1;
3542                 ap->ability_match_cfg = 0;
3543                 ap->ability_match_count = 0;
3544                 ap->ability_match = 0;
3545                 ap->ack_match = 0;
3546
3547                 rx_cfg_reg = 0;
3548         }
3549
3550         ap->rxconfig = rx_cfg_reg;
3551         ret = ANEG_OK;
3552
3553         switch (ap->state) {
3554         case ANEG_STATE_UNKNOWN:
3555                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3556                         ap->state = ANEG_STATE_AN_ENABLE;
3557
3558                 /* fallthru */
3559         case ANEG_STATE_AN_ENABLE:
3560                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3561                 if (ap->flags & MR_AN_ENABLE) {
3562                         ap->link_time = 0;
3563                         ap->cur_time = 0;
3564                         ap->ability_match_cfg = 0;
3565                         ap->ability_match_count = 0;
3566                         ap->ability_match = 0;
3567                         ap->idle_match = 0;
3568                         ap->ack_match = 0;
3569
3570                         ap->state = ANEG_STATE_RESTART_INIT;
3571                 } else {
3572                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3573                 }
3574                 break;
3575
3576         case ANEG_STATE_RESTART_INIT:
3577                 ap->link_time = ap->cur_time;
3578                 ap->flags &= ~(MR_NP_LOADED);
3579                 ap->txconfig = 0;
3580                 tw32(MAC_TX_AUTO_NEG, 0);
3581                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3582                 tw32_f(MAC_MODE, tp->mac_mode);
3583                 udelay(40);
3584
3585                 ret = ANEG_TIMER_ENAB;
3586                 ap->state = ANEG_STATE_RESTART;
3587
3588                 /* fallthru */
3589         case ANEG_STATE_RESTART:
3590                 delta = ap->cur_time - ap->link_time;
3591                 if (delta > ANEG_STATE_SETTLE_TIME)
3592                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3593                 else
3594                         ret = ANEG_TIMER_ENAB;
3595                 break;
3596
3597         case ANEG_STATE_DISABLE_LINK_OK:
3598                 ret = ANEG_DONE;
3599                 break;
3600
3601         case ANEG_STATE_ABILITY_DETECT_INIT:
3602                 ap->flags &= ~(MR_TOGGLE_TX);
3603                 ap->txconfig = ANEG_CFG_FD;
3604                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3605                 if (flowctrl & ADVERTISE_1000XPAUSE)
3606                         ap->txconfig |= ANEG_CFG_PS1;
3607                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3608                         ap->txconfig |= ANEG_CFG_PS2;
3609                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3610                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3611                 tw32_f(MAC_MODE, tp->mac_mode);
3612                 udelay(40);
3613
3614                 ap->state = ANEG_STATE_ABILITY_DETECT;
3615                 break;
3616
3617         case ANEG_STATE_ABILITY_DETECT:
3618                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3619                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3620                 break;
3621
3622         case ANEG_STATE_ACK_DETECT_INIT:
3623                 ap->txconfig |= ANEG_CFG_ACK;
3624                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3625                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3626                 tw32_f(MAC_MODE, tp->mac_mode);
3627                 udelay(40);
3628
3629                 ap->state = ANEG_STATE_ACK_DETECT;
3630
3631                 /* fallthru */
3632         case ANEG_STATE_ACK_DETECT:
3633                 if (ap->ack_match != 0) {
3634                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3635                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3636                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3637                         } else {
3638                                 ap->state = ANEG_STATE_AN_ENABLE;
3639                         }
3640                 } else if (ap->ability_match != 0 &&
3641                            ap->rxconfig == 0) {
3642                         ap->state = ANEG_STATE_AN_ENABLE;
3643                 }
3644                 break;
3645
3646         case ANEG_STATE_COMPLETE_ACK_INIT:
3647                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3648                         ret = ANEG_FAILED;
3649                         break;
3650                 }
3651                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3652                                MR_LP_ADV_HALF_DUPLEX |
3653                                MR_LP_ADV_SYM_PAUSE |
3654                                MR_LP_ADV_ASYM_PAUSE |
3655                                MR_LP_ADV_REMOTE_FAULT1 |
3656                                MR_LP_ADV_REMOTE_FAULT2 |
3657                                MR_LP_ADV_NEXT_PAGE |
3658                                MR_TOGGLE_RX |
3659                                MR_NP_RX);
3660                 if (ap->rxconfig & ANEG_CFG_FD)
3661                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3662                 if (ap->rxconfig & ANEG_CFG_HD)
3663                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3664                 if (ap->rxconfig & ANEG_CFG_PS1)
3665                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3666                 if (ap->rxconfig & ANEG_CFG_PS2)
3667                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3668                 if (ap->rxconfig & ANEG_CFG_RF1)
3669                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3670                 if (ap->rxconfig & ANEG_CFG_RF2)
3671                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3672                 if (ap->rxconfig & ANEG_CFG_NP)
3673                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3674
3675                 ap->link_time = ap->cur_time;
3676
3677                 ap->flags ^= (MR_TOGGLE_TX);
3678                 if (ap->rxconfig & 0x0008)
3679                         ap->flags |= MR_TOGGLE_RX;
3680                 if (ap->rxconfig & ANEG_CFG_NP)
3681                         ap->flags |= MR_NP_RX;
3682                 ap->flags |= MR_PAGE_RX;
3683
3684                 ap->state = ANEG_STATE_COMPLETE_ACK;
3685                 ret = ANEG_TIMER_ENAB;
3686                 break;
3687
3688         case ANEG_STATE_COMPLETE_ACK:
3689                 if (ap->ability_match != 0 &&
3690                     ap->rxconfig == 0) {
3691                         ap->state = ANEG_STATE_AN_ENABLE;
3692                         break;
3693                 }
3694                 delta = ap->cur_time - ap->link_time;
3695                 if (delta > ANEG_STATE_SETTLE_TIME) {
3696                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3697                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3698                         } else {
3699                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3700                                     !(ap->flags & MR_NP_RX)) {
3701                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3702                                 } else {
3703                                         ret = ANEG_FAILED;
3704                                 }
3705                         }
3706                 }
3707                 break;
3708
3709         case ANEG_STATE_IDLE_DETECT_INIT:
3710                 ap->link_time = ap->cur_time;
3711                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3712                 tw32_f(MAC_MODE, tp->mac_mode);
3713                 udelay(40);
3714
3715                 ap->state = ANEG_STATE_IDLE_DETECT;
3716                 ret = ANEG_TIMER_ENAB;
3717                 break;
3718
3719         case ANEG_STATE_IDLE_DETECT:
3720                 if (ap->ability_match != 0 &&
3721                     ap->rxconfig == 0) {
3722                         ap->state = ANEG_STATE_AN_ENABLE;
3723                         break;
3724                 }
3725                 delta = ap->cur_time - ap->link_time;
3726                 if (delta > ANEG_STATE_SETTLE_TIME) {
3727                         /* XXX another gem from the Broadcom driver :( */
3728                         ap->state = ANEG_STATE_LINK_OK;
3729                 }
3730                 break;
3731
3732         case ANEG_STATE_LINK_OK:
3733                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3734                 ret = ANEG_DONE;
3735                 break;
3736
3737         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3738                 /* ??? unimplemented */
3739                 break;
3740
3741         case ANEG_STATE_NEXT_PAGE_WAIT:
3742                 /* ??? unimplemented */
3743                 break;
3744
3745         default:
3746                 ret = ANEG_FAILED;
3747                 break;
3748         }
3749
3750         return ret;
3751 }
3752
3753 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3754 {
3755         int res = 0;
3756         struct tg3_fiber_aneginfo aninfo;
3757         int status = ANEG_FAILED;
3758         unsigned int tick;
3759         u32 tmp;
3760
3761         tw32_f(MAC_TX_AUTO_NEG, 0);
3762
3763         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3764         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3765         udelay(40);
3766
3767         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3768         udelay(40);
3769
3770         memset(&aninfo, 0, sizeof(aninfo));
3771         aninfo.flags |= MR_AN_ENABLE;
3772         aninfo.state = ANEG_STATE_UNKNOWN;
3773         aninfo.cur_time = 0;
3774         tick = 0;
3775         while (++tick < 195000) {
3776                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3777                 if (status == ANEG_DONE || status == ANEG_FAILED)
3778                         break;
3779
3780                 udelay(1);
3781         }
3782
3783         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3784         tw32_f(MAC_MODE, tp->mac_mode);
3785         udelay(40);
3786
3787         *txflags = aninfo.txconfig;
3788         *rxflags = aninfo.flags;
3789
3790         if (status == ANEG_DONE &&
3791             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3792                              MR_LP_ADV_FULL_DUPLEX)))
3793                 res = 1;
3794
3795         return res;
3796 }
3797
3798 static void tg3_init_bcm8002(struct tg3 *tp)
3799 {
3800         u32 mac_status = tr32(MAC_STATUS);
3801         int i;
3802
3803         /* Reset when initting first time or we have a link. */
3804         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3805             !(mac_status & MAC_STATUS_PCS_SYNCED))
3806                 return;
3807
3808         /* Set PLL lock range. */
3809         tg3_writephy(tp, 0x16, 0x8007);
3810
3811         /* SW reset */
3812         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3813
3814         /* Wait for reset to complete. */
3815         /* XXX schedule_timeout() ... */
3816         for (i = 0; i < 500; i++)
3817                 udelay(10);
3818
3819         /* Config mode; select PMA/Ch 1 regs. */
3820         tg3_writephy(tp, 0x10, 0x8411);
3821
3822         /* Enable auto-lock and comdet, select txclk for tx. */
3823         tg3_writephy(tp, 0x11, 0x0a10);
3824
3825         tg3_writephy(tp, 0x18, 0x00a0);
3826         tg3_writephy(tp, 0x16, 0x41ff);
3827
3828         /* Assert and deassert POR. */
3829         tg3_writephy(tp, 0x13, 0x0400);
3830         udelay(40);
3831         tg3_writephy(tp, 0x13, 0x0000);
3832
3833         tg3_writephy(tp, 0x11, 0x0a50);
3834         udelay(40);
3835         tg3_writephy(tp, 0x11, 0x0a10);
3836
3837         /* Wait for signal to stabilize */
3838         /* XXX schedule_timeout() ... */
3839         for (i = 0; i < 15000; i++)
3840                 udelay(10);
3841
3842         /* Deselect the channel register so we can read the PHYID
3843          * later.
3844          */
3845         tg3_writephy(tp, 0x10, 0x8011);
3846 }
3847
3848 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3849 {
3850         u16 flowctrl;
3851         u32 sg_dig_ctrl, sg_dig_status;
3852         u32 serdes_cfg, expected_sg_dig_ctrl;
3853         int workaround, port_a;
3854         int current_link_up;
3855
3856         serdes_cfg = 0;
3857         expected_sg_dig_ctrl = 0;
3858         workaround = 0;
3859         port_a = 1;
3860         current_link_up = 0;
3861
3862         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3863             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3864                 workaround = 1;
3865                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3866                         port_a = 0;
3867
3868                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3869                 /* preserve bits 20-23 for voltage regulator */
3870                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3871         }
3872
3873         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3874
3875         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3876                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3877                         if (workaround) {
3878                                 u32 val = serdes_cfg;
3879
3880                                 if (port_a)
3881                                         val |= 0xc010000;
3882                                 else
3883                                         val |= 0x4010000;
3884                                 tw32_f(MAC_SERDES_CFG, val);
3885                         }
3886
3887                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3888                 }
3889                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3890                         tg3_setup_flow_control(tp, 0, 0);
3891                         current_link_up = 1;
3892                 }
3893                 goto out;
3894         }
3895
3896         /* Want auto-negotiation.  */
3897         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3898
3899         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3900         if (flowctrl & ADVERTISE_1000XPAUSE)
3901                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3902         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3903                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3904
3905         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3906                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3907                     tp->serdes_counter &&
3908                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3909                                     MAC_STATUS_RCVD_CFG)) ==
3910                      MAC_STATUS_PCS_SYNCED)) {
3911                         tp->serdes_counter--;
3912                         current_link_up = 1;
3913                         goto out;
3914                 }
3915 restart_autoneg:
3916                 if (workaround)
3917                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3918                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3919                 udelay(5);
3920                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3921
3922                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3923                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3924         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3925                                  MAC_STATUS_SIGNAL_DET)) {
3926                 sg_dig_status = tr32(SG_DIG_STATUS);
3927                 mac_status = tr32(MAC_STATUS);
3928
3929                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3930                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3931                         u32 local_adv = 0, remote_adv = 0;
3932
3933                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3934                                 local_adv |= ADVERTISE_1000XPAUSE;
3935                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3936                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3937
3938                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3939                                 remote_adv |= LPA_1000XPAUSE;
3940                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3941                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3942
3943                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3944                         current_link_up = 1;
3945                         tp->serdes_counter = 0;
3946                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3947                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3948                         if (tp->serdes_counter)
3949                                 tp->serdes_counter--;
3950                         else {
3951                                 if (workaround) {
3952                                         u32 val = serdes_cfg;
3953
3954                                         if (port_a)
3955                                                 val |= 0xc010000;
3956                                         else
3957                                                 val |= 0x4010000;
3958
3959                                         tw32_f(MAC_SERDES_CFG, val);
3960                                 }
3961
3962                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3963                                 udelay(40);
3964
3965                                 /* Link parallel detection - link is up */
3966                                 /* only if we have PCS_SYNC and not */
3967                                 /* receiving config code words */
3968                                 mac_status = tr32(MAC_STATUS);
3969                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3970                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3971                                         tg3_setup_flow_control(tp, 0, 0);
3972                                         current_link_up = 1;
3973                                         tp->phy_flags |=
3974                                                 TG3_PHYFLG_PARALLEL_DETECT;
3975                                         tp->serdes_counter =
3976                                                 SERDES_PARALLEL_DET_TIMEOUT;
3977                                 } else
3978                                         goto restart_autoneg;
3979                         }
3980                 }
3981         } else {
3982                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3983                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3984         }
3985
3986 out:
3987         return current_link_up;
3988 }
3989
3990 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3991 {
3992         int current_link_up = 0;
3993
3994         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3995                 goto out;
3996
3997         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3998                 u32 txflags, rxflags;
3999                 int i;
4000
4001                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4002                         u32 local_adv = 0, remote_adv = 0;
4003
4004                         if (txflags & ANEG_CFG_PS1)
4005                                 local_adv |= ADVERTISE_1000XPAUSE;
4006                         if (txflags & ANEG_CFG_PS2)
4007                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
4008
4009                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
4010                                 remote_adv |= LPA_1000XPAUSE;
4011                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4012                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4013
4014                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4015
4016                         current_link_up = 1;
4017                 }
4018                 for (i = 0; i < 30; i++) {
4019                         udelay(20);
4020                         tw32_f(MAC_STATUS,
4021                                (MAC_STATUS_SYNC_CHANGED |
4022                                 MAC_STATUS_CFG_CHANGED));
4023                         udelay(40);
4024                         if ((tr32(MAC_STATUS) &
4025                              (MAC_STATUS_SYNC_CHANGED |
4026                               MAC_STATUS_CFG_CHANGED)) == 0)
4027                                 break;
4028                 }
4029
4030                 mac_status = tr32(MAC_STATUS);
4031                 if (current_link_up == 0 &&
4032                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4033                     !(mac_status & MAC_STATUS_RCVD_CFG))
4034                         current_link_up = 1;
4035         } else {
4036                 tg3_setup_flow_control(tp, 0, 0);
4037
4038                 /* Forcing 1000FD link up. */
4039                 current_link_up = 1;
4040
4041                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4042                 udelay(40);
4043
4044                 tw32_f(MAC_MODE, tp->mac_mode);
4045                 udelay(40);
4046         }
4047
4048 out:
4049         return current_link_up;
4050 }
4051
4052 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4053 {
4054         u32 orig_pause_cfg;
4055         u16 orig_active_speed;
4056         u8 orig_active_duplex;
4057         u32 mac_status;
4058         int current_link_up;
4059         int i;
4060
4061         orig_pause_cfg = tp->link_config.active_flowctrl;
4062         orig_active_speed = tp->link_config.active_speed;
4063         orig_active_duplex = tp->link_config.active_duplex;
4064
4065         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4066             netif_carrier_ok(tp->dev) &&
4067             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4068                 mac_status = tr32(MAC_STATUS);
4069                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4070                                MAC_STATUS_SIGNAL_DET |
4071                                MAC_STATUS_CFG_CHANGED |
4072                                MAC_STATUS_RCVD_CFG);
4073                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4074                                    MAC_STATUS_SIGNAL_DET)) {
4075                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4076                                             MAC_STATUS_CFG_CHANGED));
4077                         return 0;
4078                 }
4079         }
4080
4081         tw32_f(MAC_TX_AUTO_NEG, 0);
4082
4083         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4084         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4085         tw32_f(MAC_MODE, tp->mac_mode);
4086         udelay(40);
4087
4088         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4089                 tg3_init_bcm8002(tp);
4090
4091         /* Enable link change event even when serdes polling.  */
4092         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4093         udelay(40);
4094
4095         current_link_up = 0;
4096         mac_status = tr32(MAC_STATUS);
4097
4098         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4099                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4100         else
4101                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4102
4103         tp->napi[0].hw_status->status =
4104                 (SD_STATUS_UPDATED |
4105                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4106
4107         for (i = 0; i < 100; i++) {
4108                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4109                                     MAC_STATUS_CFG_CHANGED));
4110                 udelay(5);
4111                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4112                                          MAC_STATUS_CFG_CHANGED |
4113                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4114                         break;
4115         }
4116
4117         mac_status = tr32(MAC_STATUS);
4118         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4119                 current_link_up = 0;
4120                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4121                     tp->serdes_counter == 0) {
4122                         tw32_f(MAC_MODE, (tp->mac_mode |
4123                                           MAC_MODE_SEND_CONFIGS));
4124                         udelay(1);
4125                         tw32_f(MAC_MODE, tp->mac_mode);
4126                 }
4127         }
4128
4129         if (current_link_up == 1) {
4130                 tp->link_config.active_speed = SPEED_1000;
4131                 tp->link_config.active_duplex = DUPLEX_FULL;
4132                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4133                                     LED_CTRL_LNKLED_OVERRIDE |
4134                                     LED_CTRL_1000MBPS_ON));
4135         } else {
4136                 tp->link_config.active_speed = SPEED_INVALID;
4137                 tp->link_config.active_duplex = DUPLEX_INVALID;
4138                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4139                                     LED_CTRL_LNKLED_OVERRIDE |
4140                                     LED_CTRL_TRAFFIC_OVERRIDE));
4141         }
4142
4143         if (current_link_up != netif_carrier_ok(tp->dev)) {
4144                 if (current_link_up)
4145                         netif_carrier_on(tp->dev);
4146                 else
4147                         netif_carrier_off(tp->dev);
4148                 tg3_link_report(tp);
4149         } else {
4150                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4151                 if (orig_pause_cfg != now_pause_cfg ||
4152                     orig_active_speed != tp->link_config.active_speed ||
4153                     orig_active_duplex != tp->link_config.active_duplex)
4154                         tg3_link_report(tp);
4155         }
4156
4157         return 0;
4158 }
4159
4160 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4161 {
4162         int current_link_up, err = 0;
4163         u32 bmsr, bmcr;
4164         u16 current_speed;
4165         u8 current_duplex;
4166         u32 local_adv, remote_adv;
4167
4168         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4169         tw32_f(MAC_MODE, tp->mac_mode);
4170         udelay(40);
4171
4172         tw32(MAC_EVENT, 0);
4173
4174         tw32_f(MAC_STATUS,
4175              (MAC_STATUS_SYNC_CHANGED |
4176               MAC_STATUS_CFG_CHANGED |
4177               MAC_STATUS_MI_COMPLETION |
4178               MAC_STATUS_LNKSTATE_CHANGED));
4179         udelay(40);
4180
4181         if (force_reset)
4182                 tg3_phy_reset(tp);
4183
4184         current_link_up = 0;
4185         current_speed = SPEED_INVALID;
4186         current_duplex = DUPLEX_INVALID;
4187
4188         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4189         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4190         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4191                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4192                         bmsr |= BMSR_LSTATUS;
4193                 else
4194                         bmsr &= ~BMSR_LSTATUS;
4195         }
4196
4197         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4198
4199         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4200             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4201                 /* do nothing, just check for link up at the end */
4202         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4203                 u32 adv, new_adv;
4204
4205                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4206                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4207                                   ADVERTISE_1000XPAUSE |
4208                                   ADVERTISE_1000XPSE_ASYM |
4209                                   ADVERTISE_SLCT);
4210
4211                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4212
4213                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4214                         new_adv |= ADVERTISE_1000XHALF;
4215                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4216                         new_adv |= ADVERTISE_1000XFULL;
4217
4218                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4219                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4220                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4221                         tg3_writephy(tp, MII_BMCR, bmcr);
4222
4223                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4224                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4225                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4226
4227                         return err;
4228                 }
4229         } else {
4230                 u32 new_bmcr;
4231
4232                 bmcr &= ~BMCR_SPEED1000;
4233                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4234
4235                 if (tp->link_config.duplex == DUPLEX_FULL)
4236                         new_bmcr |= BMCR_FULLDPLX;
4237
4238                 if (new_bmcr != bmcr) {
4239                         /* BMCR_SPEED1000 is a reserved bit that needs
4240                          * to be set on write.
4241                          */
4242                         new_bmcr |= BMCR_SPEED1000;
4243
4244                         /* Force a linkdown */
4245                         if (netif_carrier_ok(tp->dev)) {
4246                                 u32 adv;
4247
4248                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4249                                 adv &= ~(ADVERTISE_1000XFULL |
4250                                          ADVERTISE_1000XHALF |
4251                                          ADVERTISE_SLCT);
4252                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4253                                 tg3_writephy(tp, MII_BMCR, bmcr |
4254                                                            BMCR_ANRESTART |
4255                                                            BMCR_ANENABLE);
4256                                 udelay(10);
4257                                 netif_carrier_off(tp->dev);
4258                         }
4259                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4260                         bmcr = new_bmcr;
4261                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4262                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4263                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4264                             ASIC_REV_5714) {
4265                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4266                                         bmsr |= BMSR_LSTATUS;
4267                                 else
4268                                         bmsr &= ~BMSR_LSTATUS;
4269                         }
4270                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4271                 }
4272         }
4273
4274         if (bmsr & BMSR_LSTATUS) {
4275                 current_speed = SPEED_1000;
4276                 current_link_up = 1;
4277                 if (bmcr & BMCR_FULLDPLX)
4278                         current_duplex = DUPLEX_FULL;
4279                 else
4280                         current_duplex = DUPLEX_HALF;
4281
4282                 local_adv = 0;
4283                 remote_adv = 0;
4284
4285                 if (bmcr & BMCR_ANENABLE) {
4286                         u32 common;
4287
4288                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4289                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4290                         common = local_adv & remote_adv;
4291                         if (common & (ADVERTISE_1000XHALF |
4292                                       ADVERTISE_1000XFULL)) {
4293                                 if (common & ADVERTISE_1000XFULL)
4294                                         current_duplex = DUPLEX_FULL;
4295                                 else
4296                                         current_duplex = DUPLEX_HALF;
4297                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4298                                 /* Link is up via parallel detect */
4299                         } else {
4300                                 current_link_up = 0;
4301                         }
4302                 }
4303         }
4304
4305         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4306                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4307
4308         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4309         if (tp->link_config.active_duplex == DUPLEX_HALF)
4310                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4311
4312         tw32_f(MAC_MODE, tp->mac_mode);
4313         udelay(40);
4314
4315         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4316
4317         tp->link_config.active_speed = current_speed;
4318         tp->link_config.active_duplex = current_duplex;
4319
4320         if (current_link_up != netif_carrier_ok(tp->dev)) {
4321                 if (current_link_up)
4322                         netif_carrier_on(tp->dev);
4323                 else {
4324                         netif_carrier_off(tp->dev);
4325                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4326                 }
4327                 tg3_link_report(tp);
4328         }
4329         return err;
4330 }
4331
4332 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4333 {
4334         if (tp->serdes_counter) {
4335                 /* Give autoneg time to complete. */
4336                 tp->serdes_counter--;
4337                 return;
4338         }
4339
4340         if (!netif_carrier_ok(tp->dev) &&
4341             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4342                 u32 bmcr;
4343
4344                 tg3_readphy(tp, MII_BMCR, &bmcr);
4345                 if (bmcr & BMCR_ANENABLE) {
4346                         u32 phy1, phy2;
4347
4348                         /* Select shadow register 0x1f */
4349                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4350                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4351
4352                         /* Select expansion interrupt status register */
4353                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4354                                          MII_TG3_DSP_EXP1_INT_STAT);
4355                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4356                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4357
4358                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4359                                 /* We have signal detect and not receiving
4360                                  * config code words, link is up by parallel
4361                                  * detection.
4362                                  */
4363
4364                                 bmcr &= ~BMCR_ANENABLE;
4365                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4366                                 tg3_writephy(tp, MII_BMCR, bmcr);
4367                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4368                         }
4369                 }
4370         } else if (netif_carrier_ok(tp->dev) &&
4371                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4372                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4373                 u32 phy2;
4374
4375                 /* Select expansion interrupt status register */
4376                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4377                                  MII_TG3_DSP_EXP1_INT_STAT);
4378                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4379                 if (phy2 & 0x20) {
4380                         u32 bmcr;
4381
4382                         /* Config code words received, turn on autoneg. */
4383                         tg3_readphy(tp, MII_BMCR, &bmcr);
4384                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4385
4386                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4387
4388                 }
4389         }
4390 }
4391
4392 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4393 {
4394         u32 val;
4395         int err;
4396
4397         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4398                 err = tg3_setup_fiber_phy(tp, force_reset);
4399         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4400                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4401         else
4402                 err = tg3_setup_copper_phy(tp, force_reset);
4403
4404         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4405                 u32 scale;
4406
4407                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4408                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4409                         scale = 65;
4410                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4411                         scale = 6;
4412                 else
4413                         scale = 12;
4414
4415                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4416                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4417                 tw32(GRC_MISC_CFG, val);
4418         }
4419
4420         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4421               (6 << TX_LENGTHS_IPG_SHIFT);
4422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4423                 val |= tr32(MAC_TX_LENGTHS) &
4424                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
4425                         TX_LENGTHS_CNT_DWN_VAL_MSK);
4426
4427         if (tp->link_config.active_speed == SPEED_1000 &&
4428             tp->link_config.active_duplex == DUPLEX_HALF)
4429                 tw32(MAC_TX_LENGTHS, val |
4430                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4431         else
4432                 tw32(MAC_TX_LENGTHS, val |
4433                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4434
4435         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4436                 if (netif_carrier_ok(tp->dev)) {
4437                         tw32(HOSTCC_STAT_COAL_TICKS,
4438                              tp->coal.stats_block_coalesce_usecs);
4439                 } else {
4440                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4441                 }
4442         }
4443
4444         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4445                 val = tr32(PCIE_PWR_MGMT_THRESH);
4446                 if (!netif_carrier_ok(tp->dev))
4447                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4448                               tp->pwrmgmt_thresh;
4449                 else
4450                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4451                 tw32(PCIE_PWR_MGMT_THRESH, val);
4452         }
4453
4454         return err;
4455 }
4456
4457 static inline int tg3_irq_sync(struct tg3 *tp)
4458 {
4459         return tp->irq_sync;
4460 }
4461
4462 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4463 {
4464         int i;
4465
4466         dst = (u32 *)((u8 *)dst + off);
4467         for (i = 0; i < len; i += sizeof(u32))
4468                 *dst++ = tr32(off + i);
4469 }
4470
4471 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4472 {
4473         tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4474         tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4475         tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4476         tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4477         tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4478         tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4479         tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4480         tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4481         tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4482         tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4483         tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4484         tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4485         tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4486         tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4487         tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4488         tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4489         tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4490         tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4491         tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4492
4493         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)
4494                 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4495
4496         tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4497         tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4498         tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4499         tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4500         tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4501         tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4502         tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4503         tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4504
4505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4506                 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4507                 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4508                 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4509         }
4510
4511         tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4512         tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4513         tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4514         tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4515         tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4516
4517         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4518                 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4519 }
4520
4521 static void tg3_dump_state(struct tg3 *tp)
4522 {
4523         int i;
4524         u32 *regs;
4525
4526         regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4527         if (!regs) {
4528                 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4529                 return;
4530         }
4531
4532         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4533                 /* Read up to but not including private PCI registers */
4534                 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4535                         regs[i / sizeof(u32)] = tr32(i);
4536         } else
4537                 tg3_dump_legacy_regs(tp, regs);
4538
4539         for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4540                 if (!regs[i + 0] && !regs[i + 1] &&
4541                     !regs[i + 2] && !regs[i + 3])
4542                         continue;
4543
4544                 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4545                            i * 4,
4546                            regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4547         }
4548
4549         kfree(regs);
4550
4551         for (i = 0; i < tp->irq_cnt; i++) {
4552                 struct tg3_napi *tnapi = &tp->napi[i];
4553
4554                 /* SW status block */
4555                 netdev_err(tp->dev,
4556                          "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4557                            i,
4558                            tnapi->hw_status->status,
4559                            tnapi->hw_status->status_tag,
4560                            tnapi->hw_status->rx_jumbo_consumer,
4561                            tnapi->hw_status->rx_consumer,
4562                            tnapi->hw_status->rx_mini_consumer,
4563                            tnapi->hw_status->idx[0].rx_producer,
4564                            tnapi->hw_status->idx[0].tx_consumer);
4565
4566                 netdev_err(tp->dev,
4567                 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4568                            i,
4569                            tnapi->last_tag, tnapi->last_irq_tag,
4570                            tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4571                            tnapi->rx_rcb_ptr,
4572                            tnapi->prodring.rx_std_prod_idx,
4573                            tnapi->prodring.rx_std_cons_idx,
4574                            tnapi->prodring.rx_jmb_prod_idx,
4575                            tnapi->prodring.rx_jmb_cons_idx);
4576         }
4577 }
4578
4579 /* This is called whenever we suspect that the system chipset is re-
4580  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4581  * is bogus tx completions. We try to recover by setting the
4582  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4583  * in the workqueue.
4584  */
4585 static void tg3_tx_recover(struct tg3 *tp)
4586 {
4587         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4588                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4589
4590         netdev_warn(tp->dev,
4591                     "The system may be re-ordering memory-mapped I/O "
4592                     "cycles to the network device, attempting to recover. "
4593                     "Please report the problem to the driver maintainer "
4594                     "and include system chipset information.\n");
4595
4596         spin_lock(&tp->lock);
4597         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4598         spin_unlock(&tp->lock);
4599 }
4600
4601 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4602 {
4603         /* Tell compiler to fetch tx indices from memory. */
4604         barrier();
4605         return tnapi->tx_pending -
4606                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4607 }
4608
4609 /* Tigon3 never reports partial packet sends.  So we do not
4610  * need special logic to handle SKBs that have not had all
4611  * of their frags sent yet, like SunGEM does.
4612  */
4613 static void tg3_tx(struct tg3_napi *tnapi)
4614 {
4615         struct tg3 *tp = tnapi->tp;
4616         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4617         u32 sw_idx = tnapi->tx_cons;
4618         struct netdev_queue *txq;
4619         int index = tnapi - tp->napi;
4620
4621         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4622                 index--;
4623
4624         txq = netdev_get_tx_queue(tp->dev, index);
4625
4626         while (sw_idx != hw_idx) {
4627                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4628                 struct sk_buff *skb = ri->skb;
4629                 int i, tx_bug = 0;
4630
4631                 if (unlikely(skb == NULL)) {
4632                         tg3_tx_recover(tp);
4633                         return;
4634                 }
4635
4636                 pci_unmap_single(tp->pdev,
4637                                  dma_unmap_addr(ri, mapping),
4638                                  skb_headlen(skb),
4639                                  PCI_DMA_TODEVICE);
4640
4641                 ri->skb = NULL;
4642
4643                 sw_idx = NEXT_TX(sw_idx);
4644
4645                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4646                         ri = &tnapi->tx_buffers[sw_idx];
4647                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4648                                 tx_bug = 1;
4649
4650                         pci_unmap_page(tp->pdev,
4651                                        dma_unmap_addr(ri, mapping),
4652                                        skb_shinfo(skb)->frags[i].size,
4653                                        PCI_DMA_TODEVICE);
4654                         sw_idx = NEXT_TX(sw_idx);
4655                 }
4656
4657                 dev_kfree_skb(skb);
4658
4659                 if (unlikely(tx_bug)) {
4660                         tg3_tx_recover(tp);
4661                         return;
4662                 }
4663         }
4664
4665         tnapi->tx_cons = sw_idx;
4666
4667         /* Need to make the tx_cons update visible to tg3_start_xmit()
4668          * before checking for netif_queue_stopped().  Without the
4669          * memory barrier, there is a small possibility that tg3_start_xmit()
4670          * will miss it and cause the queue to be stopped forever.
4671          */
4672         smp_mb();
4673
4674         if (unlikely(netif_tx_queue_stopped(txq) &&
4675                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4676                 __netif_tx_lock(txq, smp_processor_id());
4677                 if (netif_tx_queue_stopped(txq) &&
4678                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4679                         netif_tx_wake_queue(txq);
4680                 __netif_tx_unlock(txq);
4681         }
4682 }
4683
4684 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4685 {
4686         if (!ri->skb)
4687                 return;
4688
4689         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4690                          map_sz, PCI_DMA_FROMDEVICE);
4691         dev_kfree_skb_any(ri->skb);
4692         ri->skb = NULL;
4693 }
4694
4695 /* Returns size of skb allocated or < 0 on error.
4696  *
4697  * We only need to fill in the address because the other members
4698  * of the RX descriptor are invariant, see tg3_init_rings.
4699  *
4700  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4701  * posting buffers we only dirty the first cache line of the RX
4702  * descriptor (containing the address).  Whereas for the RX status
4703  * buffers the cpu only reads the last cacheline of the RX descriptor
4704  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4705  */
4706 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4707                             u32 opaque_key, u32 dest_idx_unmasked)
4708 {
4709         struct tg3_rx_buffer_desc *desc;
4710         struct ring_info *map;
4711         struct sk_buff *skb;
4712         dma_addr_t mapping;
4713         int skb_size, dest_idx;
4714
4715         switch (opaque_key) {
4716         case RXD_OPAQUE_RING_STD:
4717                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4718                 desc = &tpr->rx_std[dest_idx];
4719                 map = &tpr->rx_std_buffers[dest_idx];
4720                 skb_size = tp->rx_pkt_map_sz;
4721                 break;
4722
4723         case RXD_OPAQUE_RING_JUMBO:
4724                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4725                 desc = &tpr->rx_jmb[dest_idx].std;
4726                 map = &tpr->rx_jmb_buffers[dest_idx];
4727                 skb_size = TG3_RX_JMB_MAP_SZ;
4728                 break;
4729
4730         default:
4731                 return -EINVAL;
4732         }
4733
4734         /* Do not overwrite any of the map or rp information
4735          * until we are sure we can commit to a new buffer.
4736          *
4737          * Callers depend upon this behavior and assume that
4738          * we leave everything unchanged if we fail.
4739          */
4740         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4741         if (skb == NULL)
4742                 return -ENOMEM;
4743
4744         skb_reserve(skb, tp->rx_offset);
4745
4746         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4747                                  PCI_DMA_FROMDEVICE);
4748         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4749                 dev_kfree_skb(skb);
4750                 return -EIO;
4751         }
4752
4753         map->skb = skb;
4754         dma_unmap_addr_set(map, mapping, mapping);
4755
4756         desc->addr_hi = ((u64)mapping >> 32);
4757         desc->addr_lo = ((u64)mapping & 0xffffffff);
4758
4759         return skb_size;
4760 }
4761
4762 /* We only need to move over in the address because the other
4763  * members of the RX descriptor are invariant.  See notes above
4764  * tg3_alloc_rx_skb for full details.
4765  */
4766 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4767                            struct tg3_rx_prodring_set *dpr,
4768                            u32 opaque_key, int src_idx,
4769                            u32 dest_idx_unmasked)
4770 {
4771         struct tg3 *tp = tnapi->tp;
4772         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4773         struct ring_info *src_map, *dest_map;
4774         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4775         int dest_idx;
4776
4777         switch (opaque_key) {
4778         case RXD_OPAQUE_RING_STD:
4779                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4780                 dest_desc = &dpr->rx_std[dest_idx];
4781                 dest_map = &dpr->rx_std_buffers[dest_idx];
4782                 src_desc = &spr->rx_std[src_idx];
4783                 src_map = &spr->rx_std_buffers[src_idx];
4784                 break;
4785
4786         case RXD_OPAQUE_RING_JUMBO:
4787                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4788                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4789                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4790                 src_desc = &spr->rx_jmb[src_idx].std;
4791                 src_map = &spr->rx_jmb_buffers[src_idx];
4792                 break;
4793
4794         default:
4795                 return;
4796         }
4797
4798         dest_map->skb = src_map->skb;
4799         dma_unmap_addr_set(dest_map, mapping,
4800                            dma_unmap_addr(src_map, mapping));
4801         dest_desc->addr_hi = src_desc->addr_hi;
4802         dest_desc->addr_lo = src_desc->addr_lo;
4803
4804         /* Ensure that the update to the skb happens after the physical
4805          * addresses have been transferred to the new BD location.
4806          */
4807         smp_wmb();
4808
4809         src_map->skb = NULL;
4810 }
4811
4812 /* The RX ring scheme is composed of multiple rings which post fresh
4813  * buffers to the chip, and one special ring the chip uses to report
4814  * status back to the host.
4815  *
4816  * The special ring reports the status of received packets to the
4817  * host.  The chip does not write into the original descriptor the
4818  * RX buffer was obtained from.  The chip simply takes the original
4819  * descriptor as provided by the host, updates the status and length
4820  * field, then writes this into the next status ring entry.
4821  *
4822  * Each ring the host uses to post buffers to the chip is described
4823  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4824  * it is first placed into the on-chip ram.  When the packet's length
4825  * is known, it walks down the TG3_BDINFO entries to select the ring.
4826  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4827  * which is within the range of the new packet's length is chosen.
4828  *
4829  * The "separate ring for rx status" scheme may sound queer, but it makes
4830  * sense from a cache coherency perspective.  If only the host writes
4831  * to the buffer post rings, and only the chip writes to the rx status
4832  * rings, then cache lines never move beyond shared-modified state.
4833  * If both the host and chip were to write into the same ring, cache line
4834  * eviction could occur since both entities want it in an exclusive state.
4835  */
4836 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4837 {
4838         struct tg3 *tp = tnapi->tp;
4839         u32 work_mask, rx_std_posted = 0;
4840         u32 std_prod_idx, jmb_prod_idx;
4841         u32 sw_idx = tnapi->rx_rcb_ptr;
4842         u16 hw_idx;
4843         int received;
4844         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4845
4846         hw_idx = *(tnapi->rx_rcb_prod_idx);
4847         /*
4848          * We need to order the read of hw_idx and the read of
4849          * the opaque cookie.
4850          */
4851         rmb();
4852         work_mask = 0;
4853         received = 0;
4854         std_prod_idx = tpr->rx_std_prod_idx;
4855         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4856         while (sw_idx != hw_idx && budget > 0) {
4857                 struct ring_info *ri;
4858                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4859                 unsigned int len;
4860                 struct sk_buff *skb;
4861                 dma_addr_t dma_addr;
4862                 u32 opaque_key, desc_idx, *post_ptr;
4863
4864                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4865                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4866                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4867                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4868                         dma_addr = dma_unmap_addr(ri, mapping);
4869                         skb = ri->skb;
4870                         post_ptr = &std_prod_idx;
4871                         rx_std_posted++;
4872                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4873                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4874                         dma_addr = dma_unmap_addr(ri, mapping);
4875                         skb = ri->skb;
4876                         post_ptr = &jmb_prod_idx;
4877                 } else
4878                         goto next_pkt_nopost;
4879
4880                 work_mask |= opaque_key;
4881
4882                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4883                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4884                 drop_it:
4885                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4886                                        desc_idx, *post_ptr);
4887                 drop_it_no_recycle:
4888                         /* Other statistics kept track of by card. */
4889                         tp->rx_dropped++;
4890                         goto next_pkt;
4891                 }
4892
4893                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4894                       ETH_FCS_LEN;
4895
4896                 if (len > TG3_RX_COPY_THRESH(tp)) {
4897                         int skb_size;
4898
4899                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4900                                                     *post_ptr);
4901                         if (skb_size < 0)
4902                                 goto drop_it;
4903
4904                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4905                                          PCI_DMA_FROMDEVICE);
4906
4907                         /* Ensure that the update to the skb happens
4908                          * after the usage of the old DMA mapping.
4909                          */
4910                         smp_wmb();
4911
4912                         ri->skb = NULL;
4913
4914                         skb_put(skb, len);
4915                 } else {
4916                         struct sk_buff *copy_skb;
4917
4918                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4919                                        desc_idx, *post_ptr);
4920
4921                         copy_skb = netdev_alloc_skb(tp->dev, len +
4922                                                     TG3_RAW_IP_ALIGN);
4923                         if (copy_skb == NULL)
4924                                 goto drop_it_no_recycle;
4925
4926                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4927                         skb_put(copy_skb, len);
4928                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4929                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4930                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4931
4932                         /* We'll reuse the original ring buffer. */
4933                         skb = copy_skb;
4934                 }
4935
4936                 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4937                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4938                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4939                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4940                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4941                 else
4942                         skb_checksum_none_assert(skb);
4943
4944                 skb->protocol = eth_type_trans(skb, tp->dev);
4945
4946                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4947                     skb->protocol != htons(ETH_P_8021Q)) {
4948                         dev_kfree_skb(skb);
4949                         goto drop_it_no_recycle;
4950                 }
4951
4952                 if (desc->type_flags & RXD_FLAG_VLAN &&
4953                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4954                         __vlan_hwaccel_put_tag(skb,
4955                                                desc->err_vlan & RXD_VLAN_MASK);
4956
4957                 napi_gro_receive(&tnapi->napi, skb);
4958
4959                 received++;
4960                 budget--;
4961
4962 next_pkt:
4963                 (*post_ptr)++;
4964
4965                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4966                         tpr->rx_std_prod_idx = std_prod_idx &
4967                                                tp->rx_std_ring_mask;
4968                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4969                                      tpr->rx_std_prod_idx);
4970                         work_mask &= ~RXD_OPAQUE_RING_STD;
4971                         rx_std_posted = 0;
4972                 }
4973 next_pkt_nopost:
4974                 sw_idx++;
4975                 sw_idx &= tp->rx_ret_ring_mask;
4976
4977                 /* Refresh hw_idx to see if there is new work */
4978                 if (sw_idx == hw_idx) {
4979                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4980                         rmb();
4981                 }
4982         }
4983
4984         /* ACK the status ring. */
4985         tnapi->rx_rcb_ptr = sw_idx;
4986         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4987
4988         /* Refill RX ring(s). */
4989         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4990                 if (work_mask & RXD_OPAQUE_RING_STD) {
4991                         tpr->rx_std_prod_idx = std_prod_idx &
4992                                                tp->rx_std_ring_mask;
4993                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4994                                      tpr->rx_std_prod_idx);
4995                 }
4996                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4997                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4998                                                tp->rx_jmb_ring_mask;
4999                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5000                                      tpr->rx_jmb_prod_idx);
5001                 }
5002                 mmiowb();
5003         } else if (work_mask) {
5004                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5005                  * updated before the producer indices can be updated.
5006                  */
5007                 smp_wmb();
5008
5009                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5010                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5011
5012                 if (tnapi != &tp->napi[1])
5013                         napi_schedule(&tp->napi[1].napi);
5014         }
5015
5016         return received;
5017 }
5018
5019 static void tg3_poll_link(struct tg3 *tp)
5020 {
5021         /* handle link change and other phy events */
5022         if (!(tp->tg3_flags &
5023               (TG3_FLAG_USE_LINKCHG_REG |
5024                TG3_FLAG_POLL_SERDES))) {
5025                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5026
5027                 if (sblk->status & SD_STATUS_LINK_CHG) {
5028                         sblk->status = SD_STATUS_UPDATED |
5029                                        (sblk->status & ~SD_STATUS_LINK_CHG);
5030                         spin_lock(&tp->lock);
5031                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
5032                                 tw32_f(MAC_STATUS,
5033                                      (MAC_STATUS_SYNC_CHANGED |
5034                                       MAC_STATUS_CFG_CHANGED |
5035                                       MAC_STATUS_MI_COMPLETION |
5036                                       MAC_STATUS_LNKSTATE_CHANGED));
5037                                 udelay(40);
5038                         } else
5039                                 tg3_setup_phy(tp, 0);
5040                         spin_unlock(&tp->lock);
5041                 }
5042         }
5043 }
5044
5045 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5046                                 struct tg3_rx_prodring_set *dpr,
5047                                 struct tg3_rx_prodring_set *spr)
5048 {
5049         u32 si, di, cpycnt, src_prod_idx;
5050         int i, err = 0;
5051
5052         while (1) {
5053                 src_prod_idx = spr->rx_std_prod_idx;
5054
5055                 /* Make sure updates to the rx_std_buffers[] entries and the
5056                  * standard producer index are seen in the correct order.
5057                  */
5058                 smp_rmb();
5059
5060                 if (spr->rx_std_cons_idx == src_prod_idx)
5061                         break;
5062
5063                 if (spr->rx_std_cons_idx < src_prod_idx)
5064                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5065                 else
5066                         cpycnt = tp->rx_std_ring_mask + 1 -
5067                                  spr->rx_std_cons_idx;
5068
5069                 cpycnt = min(cpycnt,
5070                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5071
5072                 si = spr->rx_std_cons_idx;
5073                 di = dpr->rx_std_prod_idx;
5074
5075                 for (i = di; i < di + cpycnt; i++) {
5076                         if (dpr->rx_std_buffers[i].skb) {
5077                                 cpycnt = i - di;
5078                                 err = -ENOSPC;
5079                                 break;
5080                         }
5081                 }
5082
5083                 if (!cpycnt)
5084                         break;
5085
5086                 /* Ensure that updates to the rx_std_buffers ring and the
5087                  * shadowed hardware producer ring from tg3_recycle_skb() are
5088                  * ordered correctly WRT the skb check above.
5089                  */
5090                 smp_rmb();
5091
5092                 memcpy(&dpr->rx_std_buffers[di],
5093                        &spr->rx_std_buffers[si],
5094                        cpycnt * sizeof(struct ring_info));
5095
5096                 for (i = 0; i < cpycnt; i++, di++, si++) {
5097                         struct tg3_rx_buffer_desc *sbd, *dbd;
5098                         sbd = &spr->rx_std[si];
5099                         dbd = &dpr->rx_std[di];
5100                         dbd->addr_hi = sbd->addr_hi;
5101                         dbd->addr_lo = sbd->addr_lo;
5102                 }
5103
5104                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5105                                        tp->rx_std_ring_mask;
5106                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5107                                        tp->rx_std_ring_mask;
5108         }
5109
5110         while (1) {
5111                 src_prod_idx = spr->rx_jmb_prod_idx;
5112
5113                 /* Make sure updates to the rx_jmb_buffers[] entries and
5114                  * the jumbo producer index are seen in the correct order.
5115                  */
5116                 smp_rmb();
5117
5118                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5119                         break;
5120
5121                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5122                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5123                 else
5124                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5125                                  spr->rx_jmb_cons_idx;
5126
5127                 cpycnt = min(cpycnt,
5128                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5129
5130                 si = spr->rx_jmb_cons_idx;
5131                 di = dpr->rx_jmb_prod_idx;
5132
5133                 for (i = di; i < di + cpycnt; i++) {
5134                         if (dpr->rx_jmb_buffers[i].skb) {
5135                                 cpycnt = i - di;
5136                                 err = -ENOSPC;
5137                                 break;
5138                         }
5139                 }
5140
5141                 if (!cpycnt)
5142                         break;
5143
5144                 /* Ensure that updates to the rx_jmb_buffers ring and the
5145                  * shadowed hardware producer ring from tg3_recycle_skb() are
5146                  * ordered correctly WRT the skb check above.
5147                  */
5148                 smp_rmb();
5149
5150                 memcpy(&dpr->rx_jmb_buffers[di],
5151                        &spr->rx_jmb_buffers[si],
5152                        cpycnt * sizeof(struct ring_info));
5153
5154                 for (i = 0; i < cpycnt; i++, di++, si++) {
5155                         struct tg3_rx_buffer_desc *sbd, *dbd;
5156                         sbd = &spr->rx_jmb[si].std;
5157                         dbd = &dpr->rx_jmb[di].std;
5158                         dbd->addr_hi = sbd->addr_hi;
5159                         dbd->addr_lo = sbd->addr_lo;
5160                 }
5161
5162                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5163                                        tp->rx_jmb_ring_mask;
5164                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5165                                        tp->rx_jmb_ring_mask;
5166         }
5167
5168         return err;
5169 }
5170
5171 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5172 {
5173         struct tg3 *tp = tnapi->tp;
5174
5175         /* run TX completion thread */
5176         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5177                 tg3_tx(tnapi);
5178                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5179                         return work_done;
5180         }
5181
5182         /* run RX thread, within the bounds set by NAPI.
5183          * All RX "locking" is done by ensuring outside
5184          * code synchronizes with tg3->napi.poll()
5185          */
5186         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5187                 work_done += tg3_rx(tnapi, budget - work_done);
5188
5189         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5190                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5191                 int i, err = 0;
5192                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5193                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5194
5195                 for (i = 1; i < tp->irq_cnt; i++)
5196                         err |= tg3_rx_prodring_xfer(tp, dpr,
5197                                                     &tp->napi[i].prodring);
5198
5199                 wmb();
5200
5201                 if (std_prod_idx != dpr->rx_std_prod_idx)
5202                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5203                                      dpr->rx_std_prod_idx);
5204
5205                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5206                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5207                                      dpr->rx_jmb_prod_idx);
5208
5209                 mmiowb();
5210
5211                 if (err)
5212                         tw32_f(HOSTCC_MODE, tp->coal_now);
5213         }
5214
5215         return work_done;
5216 }
5217
5218 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5219 {
5220         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5221         struct tg3 *tp = tnapi->tp;
5222         int work_done = 0;
5223         struct tg3_hw_status *sblk = tnapi->hw_status;
5224
5225         while (1) {
5226                 work_done = tg3_poll_work(tnapi, work_done, budget);
5227
5228                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5229                         goto tx_recovery;
5230
5231                 if (unlikely(work_done >= budget))
5232                         break;
5233
5234                 /* tp->last_tag is used in tg3_int_reenable() below
5235                  * to tell the hw how much work has been processed,
5236                  * so we must read it before checking for more work.
5237                  */
5238                 tnapi->last_tag = sblk->status_tag;
5239                 tnapi->last_irq_tag = tnapi->last_tag;
5240                 rmb();
5241
5242                 /* check for RX/TX work to do */
5243                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5244                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5245                         napi_complete(napi);
5246                         /* Reenable interrupts. */
5247                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5248                         mmiowb();
5249                         break;
5250                 }
5251         }
5252
5253         return work_done;
5254
5255 tx_recovery:
5256         /* work_done is guaranteed to be less than budget. */
5257         napi_complete(napi);
5258         schedule_work(&tp->reset_task);
5259         return work_done;
5260 }
5261
5262 static void tg3_process_error(struct tg3 *tp)
5263 {
5264         u32 val;
5265         bool real_error = false;
5266
5267         if (tp->tg3_flags & TG3_FLAG_ERROR_PROCESSED)
5268                 return;
5269
5270         /* Check Flow Attention register */
5271         val = tr32(HOSTCC_FLOW_ATTN);
5272         if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5273                 netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
5274                 real_error = true;
5275         }
5276
5277         if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5278                 netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
5279                 real_error = true;
5280         }
5281
5282         if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5283                 netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
5284                 real_error = true;
5285         }
5286
5287         if (!real_error)
5288                 return;
5289
5290         tg3_dump_state(tp);
5291
5292         tp->tg3_flags |= TG3_FLAG_ERROR_PROCESSED;
5293         schedule_work(&tp->reset_task);
5294 }
5295
5296 static int tg3_poll(struct napi_struct *napi, int budget)
5297 {
5298         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5299         struct tg3 *tp = tnapi->tp;
5300         int work_done = 0;
5301         struct tg3_hw_status *sblk = tnapi->hw_status;
5302
5303         while (1) {
5304                 if (sblk->status & SD_STATUS_ERROR)
5305                         tg3_process_error(tp);
5306
5307                 tg3_poll_link(tp);
5308
5309                 work_done = tg3_poll_work(tnapi, work_done, budget);
5310
5311                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5312                         goto tx_recovery;
5313
5314                 if (unlikely(work_done >= budget))
5315                         break;
5316
5317                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5318                         /* tp->last_tag is used in tg3_int_reenable() below
5319                          * to tell the hw how much work has been processed,
5320                          * so we must read it before checking for more work.
5321                          */
5322                         tnapi->last_tag = sblk->status_tag;
5323                         tnapi->last_irq_tag = tnapi->last_tag;
5324                         rmb();
5325                 } else
5326                         sblk->status &= ~SD_STATUS_UPDATED;
5327
5328                 if (likely(!tg3_has_work(tnapi))) {
5329                         napi_complete(napi);
5330                         tg3_int_reenable(tnapi);
5331                         break;
5332                 }
5333         }
5334
5335         return work_done;
5336
5337 tx_recovery:
5338         /* work_done is guaranteed to be less than budget. */
5339         napi_complete(napi);
5340         schedule_work(&tp->reset_task);
5341         return work_done;
5342 }
5343
5344 static void tg3_napi_disable(struct tg3 *tp)
5345 {
5346         int i;
5347
5348         for (i = tp->irq_cnt - 1; i >= 0; i--)
5349                 napi_disable(&tp->napi[i].napi);
5350 }
5351
5352 static void tg3_napi_enable(struct tg3 *tp)
5353 {
5354         int i;
5355
5356         for (i = 0; i < tp->irq_cnt; i++)
5357                 napi_enable(&tp->napi[i].napi);
5358 }
5359
5360 static void tg3_napi_init(struct tg3 *tp)
5361 {
5362         int i;
5363
5364         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5365         for (i = 1; i < tp->irq_cnt; i++)
5366                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5367 }
5368
5369 static void tg3_napi_fini(struct tg3 *tp)
5370 {
5371         int i;
5372
5373         for (i = 0; i < tp->irq_cnt; i++)
5374                 netif_napi_del(&tp->napi[i].napi);
5375 }
5376
5377 static inline void tg3_netif_stop(struct tg3 *tp)
5378 {
5379         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5380         tg3_napi_disable(tp);
5381         netif_tx_disable(tp->dev);
5382 }
5383
5384 static inline void tg3_netif_start(struct tg3 *tp)
5385 {
5386         /* NOTE: unconditional netif_tx_wake_all_queues is only
5387          * appropriate so long as all callers are assured to
5388          * have free tx slots (such as after tg3_init_hw)
5389          */
5390         netif_tx_wake_all_queues(tp->dev);
5391
5392         tg3_napi_enable(tp);
5393         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5394         tg3_enable_ints(tp);
5395 }
5396
5397 static void tg3_irq_quiesce(struct tg3 *tp)
5398 {
5399         int i;
5400
5401         BUG_ON(tp->irq_sync);
5402
5403         tp->irq_sync = 1;
5404         smp_mb();
5405
5406         for (i = 0; i < tp->irq_cnt; i++)
5407                 synchronize_irq(tp->napi[i].irq_vec);
5408 }
5409
5410 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5411  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5412  * with as well.  Most of the time, this is not necessary except when
5413  * shutting down the device.
5414  */
5415 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5416 {
5417         spin_lock_bh(&tp->lock);
5418         if (irq_sync)
5419                 tg3_irq_quiesce(tp);
5420 }
5421
5422 static inline void tg3_full_unlock(struct tg3 *tp)
5423 {
5424         spin_unlock_bh(&tp->lock);
5425 }
5426
5427 /* One-shot MSI handler - Chip automatically disables interrupt
5428  * after sending MSI so driver doesn't have to do it.
5429  */
5430 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5431 {
5432         struct tg3_napi *tnapi = dev_id;
5433         struct tg3 *tp = tnapi->tp;
5434
5435         prefetch(tnapi->hw_status);
5436         if (tnapi->rx_rcb)
5437                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5438
5439         if (likely(!tg3_irq_sync(tp)))
5440                 napi_schedule(&tnapi->napi);
5441
5442         return IRQ_HANDLED;
5443 }
5444
5445 /* MSI ISR - No need to check for interrupt sharing and no need to
5446  * flush status block and interrupt mailbox. PCI ordering rules
5447  * guarantee that MSI will arrive after the status block.
5448  */
5449 static irqreturn_t tg3_msi(int irq, void *dev_id)
5450 {
5451         struct tg3_napi *tnapi = dev_id;
5452         struct tg3 *tp = tnapi->tp;
5453
5454         prefetch(tnapi->hw_status);
5455         if (tnapi->rx_rcb)
5456                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5457         /*
5458          * Writing any value to intr-mbox-0 clears PCI INTA# and
5459          * chip-internal interrupt pending events.
5460          * Writing non-zero to intr-mbox-0 additional tells the
5461          * NIC to stop sending us irqs, engaging "in-intr-handler"
5462          * event coalescing.
5463          */
5464         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5465         if (likely(!tg3_irq_sync(tp)))
5466                 napi_schedule(&tnapi->napi);
5467
5468         return IRQ_RETVAL(1);
5469 }
5470
5471 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5472 {
5473         struct tg3_napi *tnapi = dev_id;
5474         struct tg3 *tp = tnapi->tp;
5475         struct tg3_hw_status *sblk = tnapi->hw_status;
5476         unsigned int handled = 1;
5477
5478         /* In INTx mode, it is possible for the interrupt to arrive at
5479          * the CPU before the status block posted prior to the interrupt.
5480          * Reading the PCI State register will confirm whether the
5481          * interrupt is ours and will flush the status block.
5482          */
5483         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5484                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5485                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5486                         handled = 0;
5487                         goto out;
5488                 }
5489         }
5490
5491         /*
5492          * Writing any value to intr-mbox-0 clears PCI INTA# and
5493          * chip-internal interrupt pending events.
5494          * Writing non-zero to intr-mbox-0 additional tells the
5495          * NIC to stop sending us irqs, engaging "in-intr-handler"
5496          * event coalescing.
5497          *
5498          * Flush the mailbox to de-assert the IRQ immediately to prevent
5499          * spurious interrupts.  The flush impacts performance but
5500          * excessive spurious interrupts can be worse in some cases.
5501          */
5502         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5503         if (tg3_irq_sync(tp))
5504                 goto out;
5505         sblk->status &= ~SD_STATUS_UPDATED;
5506         if (likely(tg3_has_work(tnapi))) {
5507                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5508                 napi_schedule(&tnapi->napi);
5509         } else {
5510                 /* No work, shared interrupt perhaps?  re-enable
5511                  * interrupts, and flush that PCI write
5512                  */
5513                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5514                                0x00000000);
5515         }
5516 out:
5517         return IRQ_RETVAL(handled);
5518 }
5519
5520 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5521 {
5522         struct tg3_napi *tnapi = dev_id;
5523         struct tg3 *tp = tnapi->tp;
5524         struct tg3_hw_status *sblk = tnapi->hw_status;
5525         unsigned int handled = 1;
5526
5527         /* In INTx mode, it is possible for the interrupt to arrive at
5528          * the CPU before the status block posted prior to the interrupt.
5529          * Reading the PCI State register will confirm whether the
5530          * interrupt is ours and will flush the status block.
5531          */
5532         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5533                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5534                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5535                         handled = 0;
5536                         goto out;
5537                 }
5538         }
5539
5540         /*
5541          * writing any value to intr-mbox-0 clears PCI INTA# and
5542          * chip-internal interrupt pending events.
5543          * writing non-zero to intr-mbox-0 additional tells the
5544          * NIC to stop sending us irqs, engaging "in-intr-handler"
5545          * event coalescing.
5546          *
5547          * Flush the mailbox to de-assert the IRQ immediately to prevent
5548          * spurious interrupts.  The flush impacts performance but
5549          * excessive spurious interrupts can be worse in some cases.
5550          */
5551         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5552
5553         /*
5554          * In a shared interrupt configuration, sometimes other devices'
5555          * interrupts will scream.  We record the current status tag here
5556          * so that the above check can report that the screaming interrupts
5557          * are unhandled.  Eventually they will be silenced.
5558          */
5559         tnapi->last_irq_tag = sblk->status_tag;
5560
5561         if (tg3_irq_sync(tp))
5562                 goto out;
5563
5564         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5565
5566         napi_schedule(&tnapi->napi);
5567
5568 out:
5569         return IRQ_RETVAL(handled);
5570 }
5571
5572 /* ISR for interrupt test */
5573 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5574 {
5575         struct tg3_napi *tnapi = dev_id;
5576         struct tg3 *tp = tnapi->tp;
5577         struct tg3_hw_status *sblk = tnapi->hw_status;
5578
5579         if ((sblk->status & SD_STATUS_UPDATED) ||
5580             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5581                 tg3_disable_ints(tp);
5582                 return IRQ_RETVAL(1);
5583         }
5584         return IRQ_RETVAL(0);
5585 }
5586
5587 static int tg3_init_hw(struct tg3 *, int);
5588 static int tg3_halt(struct tg3 *, int, int);
5589
5590 /* Restart hardware after configuration changes, self-test, etc.
5591  * Invoked with tp->lock held.
5592  */
5593 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5594         __releases(tp->lock)
5595         __acquires(tp->lock)
5596 {
5597         int err;
5598
5599         err = tg3_init_hw(tp, reset_phy);
5600         if (err) {
5601                 netdev_err(tp->dev,
5602                            "Failed to re-initialize device, aborting\n");
5603                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5604                 tg3_full_unlock(tp);
5605                 del_timer_sync(&tp->timer);
5606                 tp->irq_sync = 0;
5607                 tg3_napi_enable(tp);
5608                 dev_close(tp->dev);
5609                 tg3_full_lock(tp, 0);
5610         }
5611         return err;
5612 }
5613
5614 #ifdef CONFIG_NET_POLL_CONTROLLER
5615 static void tg3_poll_controller(struct net_device *dev)
5616 {
5617         int i;
5618         struct tg3 *tp = netdev_priv(dev);
5619
5620         for (i = 0; i < tp->irq_cnt; i++)
5621                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5622 }
5623 #endif
5624
5625 static void tg3_reset_task(struct work_struct *work)
5626 {
5627         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5628         int err;
5629         unsigned int restart_timer;
5630
5631         tg3_full_lock(tp, 0);
5632
5633         if (!netif_running(tp->dev)) {
5634                 tg3_full_unlock(tp);
5635                 return;
5636         }
5637
5638         tg3_full_unlock(tp);
5639
5640         tg3_phy_stop(tp);
5641
5642         tg3_netif_stop(tp);
5643
5644         tg3_full_lock(tp, 1);
5645
5646         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5647         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5648
5649         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5650                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5651                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5652                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5653                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5654         }
5655
5656         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5657         err = tg3_init_hw(tp, 1);
5658         if (err)
5659                 goto out;
5660
5661         tg3_netif_start(tp);
5662
5663         if (restart_timer)
5664                 mod_timer(&tp->timer, jiffies + 1);
5665
5666 out:
5667         tg3_full_unlock(tp);
5668
5669         if (!err)
5670                 tg3_phy_start(tp);
5671 }
5672
5673 static void tg3_tx_timeout(struct net_device *dev)
5674 {
5675         struct tg3 *tp = netdev_priv(dev);
5676
5677         if (netif_msg_tx_err(tp)) {
5678                 netdev_err(dev, "transmit timed out, resetting\n");
5679                 tg3_dump_state(tp);
5680         }
5681
5682         schedule_work(&tp->reset_task);
5683 }
5684
5685 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5686 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5687 {
5688         u32 base = (u32) mapping & 0xffffffff;
5689
5690         return (base > 0xffffdcc0) && (base + len + 8 < base);
5691 }
5692
5693 /* Test for DMA addresses > 40-bit */
5694 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5695                                           int len)
5696 {
5697 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5698         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5699                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5700         return 0;
5701 #else
5702         return 0;
5703 #endif
5704 }
5705
5706 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5707
5708 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5709 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5710                                        struct sk_buff *skb, u32 last_plus_one,
5711                                        u32 *start, u32 base_flags, u32 mss)
5712 {
5713         struct tg3 *tp = tnapi->tp;
5714         struct sk_buff *new_skb;
5715         dma_addr_t new_addr = 0;
5716         u32 entry = *start;
5717         int i, ret = 0;
5718
5719         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5720                 new_skb = skb_copy(skb, GFP_ATOMIC);
5721         else {
5722                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5723
5724                 new_skb = skb_copy_expand(skb,
5725                                           skb_headroom(skb) + more_headroom,
5726                                           skb_tailroom(skb), GFP_ATOMIC);
5727         }
5728
5729         if (!new_skb) {
5730                 ret = -1;
5731         } else {
5732                 /* New SKB is guaranteed to be linear. */
5733                 entry = *start;
5734                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5735                                           PCI_DMA_TODEVICE);
5736                 /* Make sure the mapping succeeded */
5737                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5738                         ret = -1;
5739                         dev_kfree_skb(new_skb);
5740                         new_skb = NULL;
5741
5742                 /* Make sure new skb does not cross any 4G boundaries.
5743                  * Drop the packet if it does.
5744                  */
5745                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5746                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5747                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5748                                          PCI_DMA_TODEVICE);
5749                         ret = -1;
5750                         dev_kfree_skb(new_skb);
5751                         new_skb = NULL;
5752                 } else {
5753                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5754                                     base_flags, 1 | (mss << 1));
5755                         *start = NEXT_TX(entry);
5756                 }
5757         }
5758
5759         /* Now clean up the sw ring entries. */
5760         i = 0;
5761         while (entry != last_plus_one) {
5762                 int len;
5763
5764                 if (i == 0)
5765                         len = skb_headlen(skb);
5766                 else
5767                         len = skb_shinfo(skb)->frags[i-1].size;
5768
5769                 pci_unmap_single(tp->pdev,
5770                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5771                                                 mapping),
5772                                  len, PCI_DMA_TODEVICE);
5773                 if (i == 0) {
5774                         tnapi->tx_buffers[entry].skb = new_skb;
5775                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5776                                            new_addr);
5777                 } else {
5778                         tnapi->tx_buffers[entry].skb = NULL;
5779                 }
5780                 entry = NEXT_TX(entry);
5781                 i++;
5782         }
5783
5784         dev_kfree_skb(skb);
5785
5786         return ret;
5787 }
5788
5789 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5790                         dma_addr_t mapping, int len, u32 flags,
5791                         u32 mss_and_is_end)
5792 {
5793         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5794         int is_end = (mss_and_is_end & 0x1);
5795         u32 mss = (mss_and_is_end >> 1);
5796         u32 vlan_tag = 0;
5797
5798         if (is_end)
5799                 flags |= TXD_FLAG_END;
5800         if (flags & TXD_FLAG_VLAN) {
5801                 vlan_tag = flags >> 16;
5802                 flags &= 0xffff;
5803         }
5804         vlan_tag |= (mss << TXD_MSS_SHIFT);
5805
5806         txd->addr_hi = ((u64) mapping >> 32);
5807         txd->addr_lo = ((u64) mapping & 0xffffffff);
5808         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5809         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5810 }
5811
5812 /* hard_start_xmit for devices that don't have any bugs and
5813  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5814  */
5815 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5816                                   struct net_device *dev)
5817 {
5818         struct tg3 *tp = netdev_priv(dev);
5819         u32 len, entry, base_flags, mss;
5820         dma_addr_t mapping;
5821         struct tg3_napi *tnapi;
5822         struct netdev_queue *txq;
5823         unsigned int i, last;
5824
5825         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5826         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5827         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5828                 tnapi++;
5829
5830         /* We are running in BH disabled context with netif_tx_lock
5831          * and TX reclaim runs via tp->napi.poll inside of a software
5832          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5833          * no IRQ context deadlocks to worry about either.  Rejoice!
5834          */
5835         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5836                 if (!netif_tx_queue_stopped(txq)) {
5837                         netif_tx_stop_queue(txq);
5838
5839                         /* This is a hard error, log it. */
5840                         netdev_err(dev,
5841                                    "BUG! Tx Ring full when queue awake!\n");
5842                 }
5843                 return NETDEV_TX_BUSY;
5844         }
5845
5846         entry = tnapi->tx_prod;
5847         base_flags = 0;
5848         mss = skb_shinfo(skb)->gso_size;
5849         if (mss) {
5850                 int tcp_opt_len, ip_tcp_len;
5851                 u32 hdrlen;
5852
5853                 if (skb_header_cloned(skb) &&
5854                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5855                         dev_kfree_skb(skb);
5856                         goto out_unlock;
5857                 }
5858
5859                 if (skb_is_gso_v6(skb)) {
5860                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5861                 } else {
5862                         struct iphdr *iph = ip_hdr(skb);
5863
5864                         tcp_opt_len = tcp_optlen(skb);
5865                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5866
5867                         iph->check = 0;
5868                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5869                         hdrlen = ip_tcp_len + tcp_opt_len;
5870                 }
5871
5872                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5873                         mss |= (hdrlen & 0xc) << 12;
5874                         if (hdrlen & 0x10)
5875                                 base_flags |= 0x00000010;
5876                         base_flags |= (hdrlen & 0x3e0) << 5;
5877                 } else
5878                         mss |= hdrlen << 9;
5879
5880                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5881                                TXD_FLAG_CPU_POST_DMA);
5882
5883                 tcp_hdr(skb)->check = 0;
5884
5885         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5886                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5887         }
5888
5889         if (vlan_tx_tag_present(skb))
5890                 base_flags |= (TXD_FLAG_VLAN |
5891                                (vlan_tx_tag_get(skb) << 16));
5892
5893         len = skb_headlen(skb);
5894
5895         /* Queue skb data, a.k.a. the main skb fragment. */
5896         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5897         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5898                 dev_kfree_skb(skb);
5899                 goto out_unlock;
5900         }
5901
5902         tnapi->tx_buffers[entry].skb = skb;
5903         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5904
5905         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5906             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5907                 base_flags |= TXD_FLAG_JMB_PKT;
5908
5909         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5910                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5911
5912         entry = NEXT_TX(entry);
5913
5914         /* Now loop through additional data fragments, and queue them. */
5915         if (skb_shinfo(skb)->nr_frags > 0) {
5916                 last = skb_shinfo(skb)->nr_frags - 1;
5917                 for (i = 0; i <= last; i++) {
5918                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5919
5920                         len = frag->size;
5921                         mapping = pci_map_page(tp->pdev,
5922                                                frag->page,
5923                                                frag->page_offset,
5924                                                len, PCI_DMA_TODEVICE);
5925                         if (pci_dma_mapping_error(tp->pdev, mapping))
5926                                 goto dma_error;
5927
5928                         tnapi->tx_buffers[entry].skb = NULL;
5929                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5930                                            mapping);
5931
5932                         tg3_set_txd(tnapi, entry, mapping, len,
5933                                     base_flags, (i == last) | (mss << 1));
5934
5935                         entry = NEXT_TX(entry);
5936                 }
5937         }
5938
5939         /* Packets are ready, update Tx producer idx local and on card. */
5940         tw32_tx_mbox(tnapi->prodmbox, entry);
5941
5942         tnapi->tx_prod = entry;
5943         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5944                 netif_tx_stop_queue(txq);
5945
5946                 /* netif_tx_stop_queue() must be done before checking
5947                  * checking tx index in tg3_tx_avail() below, because in
5948                  * tg3_tx(), we update tx index before checking for
5949                  * netif_tx_queue_stopped().
5950                  */
5951                 smp_mb();
5952                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5953                         netif_tx_wake_queue(txq);
5954         }
5955
5956 out_unlock:
5957         mmiowb();
5958
5959         return NETDEV_TX_OK;
5960
5961 dma_error:
5962         last = i;
5963         entry = tnapi->tx_prod;
5964         tnapi->tx_buffers[entry].skb = NULL;
5965         pci_unmap_single(tp->pdev,
5966                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5967                          skb_headlen(skb),
5968                          PCI_DMA_TODEVICE);
5969         for (i = 0; i <= last; i++) {
5970                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5971                 entry = NEXT_TX(entry);
5972
5973                 pci_unmap_page(tp->pdev,
5974                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5975                                               mapping),
5976                                frag->size, PCI_DMA_TODEVICE);
5977         }
5978
5979         dev_kfree_skb(skb);
5980         return NETDEV_TX_OK;
5981 }
5982
5983 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5984                                           struct net_device *);
5985
5986 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5987  * TSO header is greater than 80 bytes.
5988  */
5989 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5990 {
5991         struct sk_buff *segs, *nskb;
5992         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5993
5994         /* Estimate the number of fragments in the worst case */
5995         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5996                 netif_stop_queue(tp->dev);
5997
5998                 /* netif_tx_stop_queue() must be done before checking
5999                  * checking tx index in tg3_tx_avail() below, because in
6000                  * tg3_tx(), we update tx index before checking for
6001                  * netif_tx_queue_stopped().
6002                  */
6003                 smp_mb();
6004                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6005                         return NETDEV_TX_BUSY;
6006
6007                 netif_wake_queue(tp->dev);
6008         }
6009
6010         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6011         if (IS_ERR(segs))
6012                 goto tg3_tso_bug_end;
6013
6014         do {
6015                 nskb = segs;
6016                 segs = segs->next;
6017                 nskb->next = NULL;
6018                 tg3_start_xmit_dma_bug(nskb, tp->dev);
6019         } while (segs);
6020
6021 tg3_tso_bug_end:
6022         dev_kfree_skb(skb);
6023
6024         return NETDEV_TX_OK;
6025 }
6026
6027 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6028  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
6029  */
6030 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
6031                                           struct net_device *dev)
6032 {
6033         struct tg3 *tp = netdev_priv(dev);
6034         u32 len, entry, base_flags, mss;
6035         int would_hit_hwbug;
6036         dma_addr_t mapping;
6037         struct tg3_napi *tnapi;
6038         struct netdev_queue *txq;
6039         unsigned int i, last;
6040
6041         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6042         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6043         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
6044                 tnapi++;
6045
6046         /* We are running in BH disabled context with netif_tx_lock
6047          * and TX reclaim runs via tp->napi.poll inside of a software
6048          * interrupt.  Furthermore, IRQ processing runs lockless so we have
6049          * no IRQ context deadlocks to worry about either.  Rejoice!
6050          */
6051         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
6052                 if (!netif_tx_queue_stopped(txq)) {
6053                         netif_tx_stop_queue(txq);
6054
6055                         /* This is a hard error, log it. */
6056                         netdev_err(dev,
6057                                    "BUG! Tx Ring full when queue awake!\n");
6058                 }
6059                 return NETDEV_TX_BUSY;
6060         }
6061
6062         entry = tnapi->tx_prod;
6063         base_flags = 0;
6064         if (skb->ip_summed == CHECKSUM_PARTIAL)
6065                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6066
6067         mss = skb_shinfo(skb)->gso_size;
6068         if (mss) {
6069                 struct iphdr *iph;
6070                 u32 tcp_opt_len, hdr_len;
6071
6072                 if (skb_header_cloned(skb) &&
6073                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6074                         dev_kfree_skb(skb);
6075                         goto out_unlock;
6076                 }
6077
6078                 iph = ip_hdr(skb);
6079                 tcp_opt_len = tcp_optlen(skb);
6080
6081                 if (skb_is_gso_v6(skb)) {
6082                         hdr_len = skb_headlen(skb) - ETH_HLEN;
6083                 } else {
6084                         u32 ip_tcp_len;
6085
6086                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6087                         hdr_len = ip_tcp_len + tcp_opt_len;
6088
6089                         iph->check = 0;
6090                         iph->tot_len = htons(mss + hdr_len);
6091                 }
6092
6093                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6094                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
6095                         return tg3_tso_bug(tp, skb);
6096
6097                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6098                                TXD_FLAG_CPU_POST_DMA);
6099
6100                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
6101                         tcp_hdr(skb)->check = 0;
6102                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6103                 } else
6104                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6105                                                                  iph->daddr, 0,
6106                                                                  IPPROTO_TCP,
6107                                                                  0);
6108
6109                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
6110                         mss |= (hdr_len & 0xc) << 12;
6111                         if (hdr_len & 0x10)
6112                                 base_flags |= 0x00000010;
6113                         base_flags |= (hdr_len & 0x3e0) << 5;
6114                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
6115                         mss |= hdr_len << 9;
6116                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
6117                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6118                         if (tcp_opt_len || iph->ihl > 5) {
6119                                 int tsflags;
6120
6121                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6122                                 mss |= (tsflags << 11);
6123                         }
6124                 } else {
6125                         if (tcp_opt_len || iph->ihl > 5) {
6126                                 int tsflags;
6127
6128                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6129                                 base_flags |= tsflags << 12;
6130                         }
6131                 }
6132         }
6133
6134         if (vlan_tx_tag_present(skb))
6135                 base_flags |= (TXD_FLAG_VLAN |
6136                                (vlan_tx_tag_get(skb) << 16));
6137
6138         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6139             !mss && skb->len > VLAN_ETH_FRAME_LEN)
6140                 base_flags |= TXD_FLAG_JMB_PKT;
6141
6142         len = skb_headlen(skb);
6143
6144         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6145         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6146                 dev_kfree_skb(skb);
6147                 goto out_unlock;
6148         }
6149
6150         tnapi->tx_buffers[entry].skb = skb;
6151         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6152
6153         would_hit_hwbug = 0;
6154
6155         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6156                 would_hit_hwbug = 1;
6157
6158         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6159             tg3_4g_overflow_test(mapping, len))
6160                 would_hit_hwbug = 1;
6161
6162         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6163             tg3_40bit_overflow_test(tp, mapping, len))
6164                 would_hit_hwbug = 1;
6165
6166         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6167                 would_hit_hwbug = 1;
6168
6169         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6170                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6171
6172         entry = NEXT_TX(entry);
6173
6174         /* Now loop through additional data fragments, and queue them. */
6175         if (skb_shinfo(skb)->nr_frags > 0) {
6176                 last = skb_shinfo(skb)->nr_frags - 1;
6177                 for (i = 0; i <= last; i++) {
6178                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6179
6180                         len = frag->size;
6181                         mapping = pci_map_page(tp->pdev,
6182                                                frag->page,
6183                                                frag->page_offset,
6184                                                len, PCI_DMA_TODEVICE);
6185
6186                         tnapi->tx_buffers[entry].skb = NULL;
6187                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6188                                            mapping);
6189                         if (pci_dma_mapping_error(tp->pdev, mapping))
6190                                 goto dma_error;
6191
6192                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6193                             len <= 8)
6194                                 would_hit_hwbug = 1;
6195
6196                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6197                             tg3_4g_overflow_test(mapping, len))
6198                                 would_hit_hwbug = 1;
6199
6200                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6201                             tg3_40bit_overflow_test(tp, mapping, len))
6202                                 would_hit_hwbug = 1;
6203
6204                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6205                                 tg3_set_txd(tnapi, entry, mapping, len,
6206                                             base_flags, (i == last)|(mss << 1));
6207                         else
6208                                 tg3_set_txd(tnapi, entry, mapping, len,
6209                                             base_flags, (i == last));
6210
6211                         entry = NEXT_TX(entry);
6212                 }
6213         }
6214
6215         if (would_hit_hwbug) {
6216                 u32 last_plus_one = entry;
6217                 u32 start;
6218
6219                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6220                 start &= (TG3_TX_RING_SIZE - 1);
6221
6222                 /* If the workaround fails due to memory/mapping
6223                  * failure, silently drop this packet.
6224                  */
6225                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6226                                                 &start, base_flags, mss))
6227                         goto out_unlock;
6228
6229                 entry = start;
6230         }
6231
6232         /* Packets are ready, update Tx producer idx local and on card. */
6233         tw32_tx_mbox(tnapi->prodmbox, entry);
6234
6235         tnapi->tx_prod = entry;
6236         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6237                 netif_tx_stop_queue(txq);
6238
6239                 /* netif_tx_stop_queue() must be done before checking
6240                  * checking tx index in tg3_tx_avail() below, because in
6241                  * tg3_tx(), we update tx index before checking for
6242                  * netif_tx_queue_stopped().
6243                  */
6244                 smp_mb();
6245                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6246                         netif_tx_wake_queue(txq);
6247         }
6248
6249 out_unlock:
6250         mmiowb();
6251
6252         return NETDEV_TX_OK;
6253
6254 dma_error:
6255         last = i;
6256         entry = tnapi->tx_prod;
6257         tnapi->tx_buffers[entry].skb = NULL;
6258         pci_unmap_single(tp->pdev,
6259                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6260                          skb_headlen(skb),
6261                          PCI_DMA_TODEVICE);
6262         for (i = 0; i <= last; i++) {
6263                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6264                 entry = NEXT_TX(entry);
6265
6266                 pci_unmap_page(tp->pdev,
6267                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6268                                               mapping),
6269                                frag->size, PCI_DMA_TODEVICE);
6270         }
6271
6272         dev_kfree_skb(skb);
6273         return NETDEV_TX_OK;
6274 }
6275
6276 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6277 {
6278         struct tg3 *tp = netdev_priv(dev);
6279
6280         if (dev->mtu > ETH_DATA_LEN && (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6281                 features &= ~NETIF_F_ALL_TSO;
6282
6283         return features;
6284 }
6285
6286 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6287                                int new_mtu)
6288 {
6289         dev->mtu = new_mtu;
6290
6291         if (new_mtu > ETH_DATA_LEN) {
6292                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6293                         netdev_update_features(dev);
6294                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6295                 } else {
6296                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6297                 }
6298         } else {
6299                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6300                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6301                         netdev_update_features(dev);
6302                 }
6303                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6304         }
6305 }
6306
6307 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6308 {
6309         struct tg3 *tp = netdev_priv(dev);
6310         int err;
6311
6312         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6313                 return -EINVAL;
6314
6315         if (!netif_running(dev)) {
6316                 /* We'll just catch it later when the
6317                  * device is up'd.
6318                  */
6319                 tg3_set_mtu(dev, tp, new_mtu);
6320                 return 0;
6321         }
6322
6323         tg3_phy_stop(tp);
6324
6325         tg3_netif_stop(tp);
6326
6327         tg3_full_lock(tp, 1);
6328
6329         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6330
6331         tg3_set_mtu(dev, tp, new_mtu);
6332
6333         err = tg3_restart_hw(tp, 0);
6334
6335         if (!err)
6336                 tg3_netif_start(tp);
6337
6338         tg3_full_unlock(tp);
6339
6340         if (!err)
6341                 tg3_phy_start(tp);
6342
6343         return err;
6344 }
6345
6346 static void tg3_rx_prodring_free(struct tg3 *tp,
6347                                  struct tg3_rx_prodring_set *tpr)
6348 {
6349         int i;
6350
6351         if (tpr != &tp->napi[0].prodring) {
6352                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6353                      i = (i + 1) & tp->rx_std_ring_mask)
6354                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6355                                         tp->rx_pkt_map_sz);
6356
6357                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6358                         for (i = tpr->rx_jmb_cons_idx;
6359                              i != tpr->rx_jmb_prod_idx;
6360                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6361                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6362                                                 TG3_RX_JMB_MAP_SZ);
6363                         }
6364                 }
6365
6366                 return;
6367         }
6368
6369         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6370                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6371                                 tp->rx_pkt_map_sz);
6372
6373         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6374             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6375                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6376                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6377                                         TG3_RX_JMB_MAP_SZ);
6378         }
6379 }
6380
6381 /* Initialize rx rings for packet processing.
6382  *
6383  * The chip has been shut down and the driver detached from
6384  * the networking, so no interrupts or new tx packets will
6385  * end up in the driver.  tp->{tx,}lock are held and thus
6386  * we may not sleep.
6387  */
6388 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6389                                  struct tg3_rx_prodring_set *tpr)
6390 {
6391         u32 i, rx_pkt_dma_sz;
6392
6393         tpr->rx_std_cons_idx = 0;
6394         tpr->rx_std_prod_idx = 0;
6395         tpr->rx_jmb_cons_idx = 0;
6396         tpr->rx_jmb_prod_idx = 0;
6397
6398         if (tpr != &tp->napi[0].prodring) {
6399                 memset(&tpr->rx_std_buffers[0], 0,
6400                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6401                 if (tpr->rx_jmb_buffers)
6402                         memset(&tpr->rx_jmb_buffers[0], 0,
6403                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6404                 goto done;
6405         }
6406
6407         /* Zero out all descriptors. */
6408         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6409
6410         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6411         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6412             tp->dev->mtu > ETH_DATA_LEN)
6413                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6414         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6415
6416         /* Initialize invariants of the rings, we only set this
6417          * stuff once.  This works because the card does not
6418          * write into the rx buffer posting rings.
6419          */
6420         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6421                 struct tg3_rx_buffer_desc *rxd;
6422
6423                 rxd = &tpr->rx_std[i];
6424                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6425                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6426                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6427                                (i << RXD_OPAQUE_INDEX_SHIFT));
6428         }
6429
6430         /* Now allocate fresh SKBs for each rx ring. */
6431         for (i = 0; i < tp->rx_pending; i++) {
6432                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6433                         netdev_warn(tp->dev,
6434                                     "Using a smaller RX standard ring. Only "
6435                                     "%d out of %d buffers were allocated "
6436                                     "successfully\n", i, tp->rx_pending);
6437                         if (i == 0)
6438                                 goto initfail;
6439                         tp->rx_pending = i;
6440                         break;
6441                 }
6442         }
6443
6444         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6445             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6446                 goto done;
6447
6448         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6449
6450         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6451                 goto done;
6452
6453         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6454                 struct tg3_rx_buffer_desc *rxd;
6455
6456                 rxd = &tpr->rx_jmb[i].std;
6457                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6458                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6459                                   RXD_FLAG_JUMBO;
6460                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6461                        (i << RXD_OPAQUE_INDEX_SHIFT));
6462         }
6463
6464         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6465                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6466                         netdev_warn(tp->dev,
6467                                     "Using a smaller RX jumbo ring. Only %d "
6468                                     "out of %d buffers were allocated "
6469                                     "successfully\n", i, tp->rx_jumbo_pending);
6470                         if (i == 0)
6471                                 goto initfail;
6472                         tp->rx_jumbo_pending = i;
6473                         break;
6474                 }
6475         }
6476
6477 done:
6478         return 0;
6479
6480 initfail:
6481         tg3_rx_prodring_free(tp, tpr);
6482         return -ENOMEM;
6483 }
6484
6485 static void tg3_rx_prodring_fini(struct tg3 *tp,
6486                                  struct tg3_rx_prodring_set *tpr)
6487 {
6488         kfree(tpr->rx_std_buffers);
6489         tpr->rx_std_buffers = NULL;
6490         kfree(tpr->rx_jmb_buffers);
6491         tpr->rx_jmb_buffers = NULL;
6492         if (tpr->rx_std) {
6493                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6494                                   tpr->rx_std, tpr->rx_std_mapping);
6495                 tpr->rx_std = NULL;
6496         }
6497         if (tpr->rx_jmb) {
6498                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6499                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6500                 tpr->rx_jmb = NULL;
6501         }
6502 }
6503
6504 static int tg3_rx_prodring_init(struct tg3 *tp,
6505                                 struct tg3_rx_prodring_set *tpr)
6506 {
6507         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6508                                       GFP_KERNEL);
6509         if (!tpr->rx_std_buffers)
6510                 return -ENOMEM;
6511
6512         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6513                                          TG3_RX_STD_RING_BYTES(tp),
6514                                          &tpr->rx_std_mapping,
6515                                          GFP_KERNEL);
6516         if (!tpr->rx_std)
6517                 goto err_out;
6518
6519         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6520             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6521                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6522                                               GFP_KERNEL);
6523                 if (!tpr->rx_jmb_buffers)
6524                         goto err_out;
6525
6526                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6527                                                  TG3_RX_JMB_RING_BYTES(tp),
6528                                                  &tpr->rx_jmb_mapping,
6529                                                  GFP_KERNEL);
6530                 if (!tpr->rx_jmb)
6531                         goto err_out;
6532         }
6533
6534         return 0;
6535
6536 err_out:
6537         tg3_rx_prodring_fini(tp, tpr);
6538         return -ENOMEM;
6539 }
6540
6541 /* Free up pending packets in all rx/tx rings.
6542  *
6543  * The chip has been shut down and the driver detached from
6544  * the networking, so no interrupts or new tx packets will
6545  * end up in the driver.  tp->{tx,}lock is not held and we are not
6546  * in an interrupt context and thus may sleep.
6547  */
6548 static void tg3_free_rings(struct tg3 *tp)
6549 {
6550         int i, j;
6551
6552         for (j = 0; j < tp->irq_cnt; j++) {
6553                 struct tg3_napi *tnapi = &tp->napi[j];
6554
6555                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6556
6557                 if (!tnapi->tx_buffers)
6558                         continue;
6559
6560                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6561                         struct ring_info *txp;
6562                         struct sk_buff *skb;
6563                         unsigned int k;
6564
6565                         txp = &tnapi->tx_buffers[i];
6566                         skb = txp->skb;
6567
6568                         if (skb == NULL) {
6569                                 i++;
6570                                 continue;
6571                         }
6572
6573                         pci_unmap_single(tp->pdev,
6574                                          dma_unmap_addr(txp, mapping),
6575                                          skb_headlen(skb),
6576                                          PCI_DMA_TODEVICE);
6577                         txp->skb = NULL;
6578
6579                         i++;
6580
6581                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6582                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6583                                 pci_unmap_page(tp->pdev,
6584                                                dma_unmap_addr(txp, mapping),
6585                                                skb_shinfo(skb)->frags[k].size,
6586                                                PCI_DMA_TODEVICE);
6587                                 i++;
6588                         }
6589
6590                         dev_kfree_skb_any(skb);
6591                 }
6592         }
6593 }
6594
6595 /* Initialize tx/rx rings for packet processing.
6596  *
6597  * The chip has been shut down and the driver detached from
6598  * the networking, so no interrupts or new tx packets will
6599  * end up in the driver.  tp->{tx,}lock are held and thus
6600  * we may not sleep.
6601  */
6602 static int tg3_init_rings(struct tg3 *tp)
6603 {
6604         int i;
6605
6606         /* Free up all the SKBs. */
6607         tg3_free_rings(tp);
6608
6609         for (i = 0; i < tp->irq_cnt; i++) {
6610                 struct tg3_napi *tnapi = &tp->napi[i];
6611
6612                 tnapi->last_tag = 0;
6613                 tnapi->last_irq_tag = 0;
6614                 tnapi->hw_status->status = 0;
6615                 tnapi->hw_status->status_tag = 0;
6616                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6617
6618                 tnapi->tx_prod = 0;
6619                 tnapi->tx_cons = 0;
6620                 if (tnapi->tx_ring)
6621                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6622
6623                 tnapi->rx_rcb_ptr = 0;
6624                 if (tnapi->rx_rcb)
6625                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6626
6627                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6628                         tg3_free_rings(tp);
6629                         return -ENOMEM;
6630                 }
6631         }
6632
6633         return 0;
6634 }
6635
6636 /*
6637  * Must not be invoked with interrupt sources disabled and
6638  * the hardware shutdown down.
6639  */
6640 static void tg3_free_consistent(struct tg3 *tp)
6641 {
6642         int i;
6643
6644         for (i = 0; i < tp->irq_cnt; i++) {
6645                 struct tg3_napi *tnapi = &tp->napi[i];
6646
6647                 if (tnapi->tx_ring) {
6648                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6649                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6650                         tnapi->tx_ring = NULL;
6651                 }
6652
6653                 kfree(tnapi->tx_buffers);
6654                 tnapi->tx_buffers = NULL;
6655
6656                 if (tnapi->rx_rcb) {
6657                         dma_free_coherent(&tp->pdev->dev,
6658                                           TG3_RX_RCB_RING_BYTES(tp),
6659                                           tnapi->rx_rcb,
6660                                           tnapi->rx_rcb_mapping);
6661                         tnapi->rx_rcb = NULL;
6662                 }
6663
6664                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6665
6666                 if (tnapi->hw_status) {
6667                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6668                                           tnapi->hw_status,
6669                                           tnapi->status_mapping);
6670                         tnapi->hw_status = NULL;
6671                 }
6672         }
6673
6674         if (tp->hw_stats) {
6675                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6676                                   tp->hw_stats, tp->stats_mapping);
6677                 tp->hw_stats = NULL;
6678         }
6679 }
6680
6681 /*
6682  * Must not be invoked with interrupt sources disabled and
6683  * the hardware shutdown down.  Can sleep.
6684  */
6685 static int tg3_alloc_consistent(struct tg3 *tp)
6686 {
6687         int i;
6688
6689         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6690                                           sizeof(struct tg3_hw_stats),
6691                                           &tp->stats_mapping,
6692                                           GFP_KERNEL);
6693         if (!tp->hw_stats)
6694                 goto err_out;
6695
6696         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6697
6698         for (i = 0; i < tp->irq_cnt; i++) {
6699                 struct tg3_napi *tnapi = &tp->napi[i];
6700                 struct tg3_hw_status *sblk;
6701
6702                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6703                                                       TG3_HW_STATUS_SIZE,
6704                                                       &tnapi->status_mapping,
6705                                                       GFP_KERNEL);
6706                 if (!tnapi->hw_status)
6707                         goto err_out;
6708
6709                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6710                 sblk = tnapi->hw_status;
6711
6712                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6713                         goto err_out;
6714
6715                 /* If multivector TSS is enabled, vector 0 does not handle
6716                  * tx interrupts.  Don't allocate any resources for it.
6717                  */
6718                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6719                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6720                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6721                                                     TG3_TX_RING_SIZE,
6722                                                     GFP_KERNEL);
6723                         if (!tnapi->tx_buffers)
6724                                 goto err_out;
6725
6726                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6727                                                             TG3_TX_RING_BYTES,
6728                                                         &tnapi->tx_desc_mapping,
6729                                                             GFP_KERNEL);
6730                         if (!tnapi->tx_ring)
6731                                 goto err_out;
6732                 }
6733
6734                 /*
6735                  * When RSS is enabled, the status block format changes
6736                  * slightly.  The "rx_jumbo_consumer", "reserved",
6737                  * and "rx_mini_consumer" members get mapped to the
6738                  * other three rx return ring producer indexes.
6739                  */
6740                 switch (i) {
6741                 default:
6742                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6743                         break;
6744                 case 2:
6745                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6746                         break;
6747                 case 3:
6748                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6749                         break;
6750                 case 4:
6751                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6752                         break;
6753                 }
6754
6755                 /*
6756                  * If multivector RSS is enabled, vector 0 does not handle
6757                  * rx or tx interrupts.  Don't allocate any resources for it.
6758                  */
6759                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6760                         continue;
6761
6762                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6763                                                    TG3_RX_RCB_RING_BYTES(tp),
6764                                                    &tnapi->rx_rcb_mapping,
6765                                                    GFP_KERNEL);
6766                 if (!tnapi->rx_rcb)
6767                         goto err_out;
6768
6769                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6770         }
6771
6772         return 0;
6773
6774 err_out:
6775         tg3_free_consistent(tp);
6776         return -ENOMEM;
6777 }
6778
6779 #define MAX_WAIT_CNT 1000
6780
6781 /* To stop a block, clear the enable bit and poll till it
6782  * clears.  tp->lock is held.
6783  */
6784 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6785 {
6786         unsigned int i;
6787         u32 val;
6788
6789         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6790                 switch (ofs) {
6791                 case RCVLSC_MODE:
6792                 case DMAC_MODE:
6793                 case MBFREE_MODE:
6794                 case BUFMGR_MODE:
6795                 case MEMARB_MODE:
6796                         /* We can't enable/disable these bits of the
6797                          * 5705/5750, just say success.
6798                          */
6799                         return 0;
6800
6801                 default:
6802                         break;
6803                 }
6804         }
6805
6806         val = tr32(ofs);
6807         val &= ~enable_bit;
6808         tw32_f(ofs, val);
6809
6810         for (i = 0; i < MAX_WAIT_CNT; i++) {
6811                 udelay(100);
6812                 val = tr32(ofs);
6813                 if ((val & enable_bit) == 0)
6814                         break;
6815         }
6816
6817         if (i == MAX_WAIT_CNT && !silent) {
6818                 dev_err(&tp->pdev->dev,
6819                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6820                         ofs, enable_bit);
6821                 return -ENODEV;
6822         }
6823
6824         return 0;
6825 }
6826
6827 /* tp->lock is held. */
6828 static int tg3_abort_hw(struct tg3 *tp, int silent)
6829 {
6830         int i, err;
6831
6832         tg3_disable_ints(tp);
6833
6834         tp->rx_mode &= ~RX_MODE_ENABLE;
6835         tw32_f(MAC_RX_MODE, tp->rx_mode);
6836         udelay(10);
6837
6838         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6839         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6840         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6841         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6842         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6843         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6844
6845         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6846         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6847         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6848         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6849         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6850         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6851         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6852
6853         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6854         tw32_f(MAC_MODE, tp->mac_mode);
6855         udelay(40);
6856
6857         tp->tx_mode &= ~TX_MODE_ENABLE;
6858         tw32_f(MAC_TX_MODE, tp->tx_mode);
6859
6860         for (i = 0; i < MAX_WAIT_CNT; i++) {
6861                 udelay(100);
6862                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6863                         break;
6864         }
6865         if (i >= MAX_WAIT_CNT) {
6866                 dev_err(&tp->pdev->dev,
6867                         "%s timed out, TX_MODE_ENABLE will not clear "
6868                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6869                 err |= -ENODEV;
6870         }
6871
6872         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6873         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6874         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6875
6876         tw32(FTQ_RESET, 0xffffffff);
6877         tw32(FTQ_RESET, 0x00000000);
6878
6879         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6880         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6881
6882         for (i = 0; i < tp->irq_cnt; i++) {
6883                 struct tg3_napi *tnapi = &tp->napi[i];
6884                 if (tnapi->hw_status)
6885                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6886         }
6887         if (tp->hw_stats)
6888                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6889
6890         return err;
6891 }
6892
6893 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6894 {
6895         int i;
6896         u32 apedata;
6897
6898         /* NCSI does not support APE events */
6899         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6900                 return;
6901
6902         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6903         if (apedata != APE_SEG_SIG_MAGIC)
6904                 return;
6905
6906         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6907         if (!(apedata & APE_FW_STATUS_READY))
6908                 return;
6909
6910         /* Wait for up to 1 millisecond for APE to service previous event. */
6911         for (i = 0; i < 10; i++) {
6912                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6913                         return;
6914
6915                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6916
6917                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6918                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6919                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6920
6921                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6922
6923                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6924                         break;
6925
6926                 udelay(100);
6927         }
6928
6929         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6930                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6931 }
6932
6933 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6934 {
6935         u32 event;
6936         u32 apedata;
6937
6938         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6939                 return;
6940
6941         switch (kind) {
6942         case RESET_KIND_INIT:
6943                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6944                                 APE_HOST_SEG_SIG_MAGIC);
6945                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6946                                 APE_HOST_SEG_LEN_MAGIC);
6947                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6948                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6949                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6950                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6951                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6952                                 APE_HOST_BEHAV_NO_PHYLOCK);
6953                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6954                                     TG3_APE_HOST_DRVR_STATE_START);
6955
6956                 event = APE_EVENT_STATUS_STATE_START;
6957                 break;
6958         case RESET_KIND_SHUTDOWN:
6959                 /* With the interface we are currently using,
6960                  * APE does not track driver state.  Wiping
6961                  * out the HOST SEGMENT SIGNATURE forces
6962                  * the APE to assume OS absent status.
6963                  */
6964                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6965
6966                 if (device_may_wakeup(&tp->pdev->dev) &&
6967                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6968                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6969                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6970                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6971                 } else
6972                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6973
6974                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6975
6976                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6977                 break;
6978         case RESET_KIND_SUSPEND:
6979                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6980                 break;
6981         default:
6982                 return;
6983         }
6984
6985         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6986
6987         tg3_ape_send_event(tp, event);
6988 }
6989
6990 /* tp->lock is held. */
6991 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6992 {
6993         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6994                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6995
6996         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6997                 switch (kind) {
6998                 case RESET_KIND_INIT:
6999                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7000                                       DRV_STATE_START);
7001                         break;
7002
7003                 case RESET_KIND_SHUTDOWN:
7004                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7005                                       DRV_STATE_UNLOAD);
7006                         break;
7007
7008                 case RESET_KIND_SUSPEND:
7009                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7010                                       DRV_STATE_SUSPEND);
7011                         break;
7012
7013                 default:
7014                         break;
7015                 }
7016         }
7017
7018         if (kind == RESET_KIND_INIT ||
7019             kind == RESET_KIND_SUSPEND)
7020                 tg3_ape_driver_state_change(tp, kind);
7021 }
7022
7023 /* tp->lock is held. */
7024 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
7025 {
7026         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
7027                 switch (kind) {
7028                 case RESET_KIND_INIT:
7029                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7030                                       DRV_STATE_START_DONE);
7031                         break;
7032
7033                 case RESET_KIND_SHUTDOWN:
7034                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7035                                       DRV_STATE_UNLOAD_DONE);
7036                         break;
7037
7038                 default:
7039                         break;
7040                 }
7041         }
7042
7043         if (kind == RESET_KIND_SHUTDOWN)
7044                 tg3_ape_driver_state_change(tp, kind);
7045 }
7046
7047 /* tp->lock is held. */
7048 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
7049 {
7050         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7051                 switch (kind) {
7052                 case RESET_KIND_INIT:
7053                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7054                                       DRV_STATE_START);
7055                         break;
7056
7057                 case RESET_KIND_SHUTDOWN:
7058                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7059                                       DRV_STATE_UNLOAD);
7060                         break;
7061
7062                 case RESET_KIND_SUSPEND:
7063                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
7064                                       DRV_STATE_SUSPEND);
7065                         break;
7066
7067                 default:
7068                         break;
7069                 }
7070         }
7071 }
7072
7073 static int tg3_poll_fw(struct tg3 *tp)
7074 {
7075         int i;
7076         u32 val;
7077
7078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7079                 /* Wait up to 20ms for init done. */
7080                 for (i = 0; i < 200; i++) {
7081                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
7082                                 return 0;
7083                         udelay(100);
7084                 }
7085                 return -ENODEV;
7086         }
7087
7088         /* Wait for firmware initialization to complete. */
7089         for (i = 0; i < 100000; i++) {
7090                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
7091                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
7092                         break;
7093                 udelay(10);
7094         }
7095
7096         /* Chip might not be fitted with firmware.  Some Sun onboard
7097          * parts are configured like that.  So don't signal the timeout
7098          * of the above loop as an error, but do report the lack of
7099          * running firmware once.
7100          */
7101         if (i >= 100000 &&
7102             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
7103                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
7104
7105                 netdev_info(tp->dev, "No firmware running\n");
7106         }
7107
7108         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7109                 /* The 57765 A0 needs a little more
7110                  * time to do some important work.
7111                  */
7112                 mdelay(10);
7113         }
7114
7115         return 0;
7116 }
7117
7118 /* Save PCI command register before chip reset */
7119 static void tg3_save_pci_state(struct tg3 *tp)
7120 {
7121         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7122 }
7123
7124 /* Restore PCI state after chip reset */
7125 static void tg3_restore_pci_state(struct tg3 *tp)
7126 {
7127         u32 val;
7128
7129         /* Re-enable indirect register accesses. */
7130         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7131                                tp->misc_host_ctrl);
7132
7133         /* Set MAX PCI retry to zero. */
7134         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7135         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7136             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
7137                 val |= PCISTATE_RETRY_SAME_DMA;
7138         /* Allow reads and writes to the APE register and memory space. */
7139         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7140                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7141                        PCISTATE_ALLOW_APE_SHMEM_WR |
7142                        PCISTATE_ALLOW_APE_PSPACE_WR;
7143         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7144
7145         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7146
7147         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7148                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7149                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7150                 else {
7151                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7152                                               tp->pci_cacheline_sz);
7153                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7154                                               tp->pci_lat_timer);
7155                 }
7156         }
7157
7158         /* Make sure PCI-X relaxed ordering bit is clear. */
7159         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7160                 u16 pcix_cmd;
7161
7162                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7163                                      &pcix_cmd);
7164                 pcix_cmd &= ~PCI_X_CMD_ERO;
7165                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7166                                       pcix_cmd);
7167         }
7168
7169         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7170
7171                 /* Chip reset on 5780 will reset MSI enable bit,
7172                  * so need to restore it.
7173                  */
7174                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7175                         u16 ctrl;
7176
7177                         pci_read_config_word(tp->pdev,
7178                                              tp->msi_cap + PCI_MSI_FLAGS,
7179                                              &ctrl);
7180                         pci_write_config_word(tp->pdev,
7181                                               tp->msi_cap + PCI_MSI_FLAGS,
7182                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7183                         val = tr32(MSGINT_MODE);
7184                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7185                 }
7186         }
7187 }
7188
7189 static void tg3_stop_fw(struct tg3 *);
7190
7191 /* tp->lock is held. */
7192 static int tg3_chip_reset(struct tg3 *tp)
7193 {
7194         u32 val;
7195         void (*write_op)(struct tg3 *, u32, u32);
7196         int i, err;
7197
7198         tg3_nvram_lock(tp);
7199
7200         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7201
7202         /* No matching tg3_nvram_unlock() after this because
7203          * chip reset below will undo the nvram lock.
7204          */
7205         tp->nvram_lock_cnt = 0;
7206
7207         /* GRC_MISC_CFG core clock reset will clear the memory
7208          * enable bit in PCI register 4 and the MSI enable bit
7209          * on some chips, so we save relevant registers here.
7210          */
7211         tg3_save_pci_state(tp);
7212
7213         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7214             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7215                 tw32(GRC_FASTBOOT_PC, 0);
7216
7217         /*
7218          * We must avoid the readl() that normally takes place.
7219          * It locks machines, causes machine checks, and other
7220          * fun things.  So, temporarily disable the 5701
7221          * hardware workaround, while we do the reset.
7222          */
7223         write_op = tp->write32;
7224         if (write_op == tg3_write_flush_reg32)
7225                 tp->write32 = tg3_write32;
7226
7227         /* Prevent the irq handler from reading or writing PCI registers
7228          * during chip reset when the memory enable bit in the PCI command
7229          * register may be cleared.  The chip does not generate interrupt
7230          * at this time, but the irq handler may still be called due to irq
7231          * sharing or irqpoll.
7232          */
7233         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7234         for (i = 0; i < tp->irq_cnt; i++) {
7235                 struct tg3_napi *tnapi = &tp->napi[i];
7236                 if (tnapi->hw_status) {
7237                         tnapi->hw_status->status = 0;
7238                         tnapi->hw_status->status_tag = 0;
7239                 }
7240                 tnapi->last_tag = 0;
7241                 tnapi->last_irq_tag = 0;
7242         }
7243         smp_mb();
7244
7245         for (i = 0; i < tp->irq_cnt; i++)
7246                 synchronize_irq(tp->napi[i].irq_vec);
7247
7248         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7249                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7250                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7251         }
7252
7253         /* do the reset */
7254         val = GRC_MISC_CFG_CORECLK_RESET;
7255
7256         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7257                 /* Force PCIe 1.0a mode */
7258                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7259                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
7260                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7261                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7262                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7263
7264                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7265                         tw32(GRC_MISC_CFG, (1 << 29));
7266                         val |= (1 << 29);
7267                 }
7268         }
7269
7270         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7271                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7272                 tw32(GRC_VCPU_EXT_CTRL,
7273                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7274         }
7275
7276         /* Manage gphy power for all CPMU absent PCIe devices. */
7277         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7278             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7279                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7280
7281         tw32(GRC_MISC_CFG, val);
7282
7283         /* restore 5701 hardware bug workaround write method */
7284         tp->write32 = write_op;
7285
7286         /* Unfortunately, we have to delay before the PCI read back.
7287          * Some 575X chips even will not respond to a PCI cfg access
7288          * when the reset command is given to the chip.
7289          *
7290          * How do these hardware designers expect things to work
7291          * properly if the PCI write is posted for a long period
7292          * of time?  It is always necessary to have some method by
7293          * which a register read back can occur to push the write
7294          * out which does the reset.
7295          *
7296          * For most tg3 variants the trick below was working.
7297          * Ho hum...
7298          */
7299         udelay(120);
7300
7301         /* Flush PCI posted writes.  The normal MMIO registers
7302          * are inaccessible at this time so this is the only
7303          * way to make this reliably (actually, this is no longer
7304          * the case, see above).  I tried to use indirect
7305          * register read/write but this upset some 5701 variants.
7306          */
7307         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7308
7309         udelay(120);
7310
7311         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7312                 u16 val16;
7313
7314                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7315                         int i;
7316                         u32 cfg_val;
7317
7318                         /* Wait for link training to complete.  */
7319                         for (i = 0; i < 5000; i++)
7320                                 udelay(100);
7321
7322                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7323                         pci_write_config_dword(tp->pdev, 0xc4,
7324                                                cfg_val | (1 << 15));
7325                 }
7326
7327                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7328                 pci_read_config_word(tp->pdev,
7329                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7330                                      &val16);
7331                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7332                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7333                 /*
7334                  * Older PCIe devices only support the 128 byte
7335                  * MPS setting.  Enforce the restriction.
7336                  */
7337                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7338                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7339                 pci_write_config_word(tp->pdev,
7340                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7341                                       val16);
7342
7343                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7344
7345                 /* Clear error status */
7346                 pci_write_config_word(tp->pdev,
7347                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7348                                       PCI_EXP_DEVSTA_CED |
7349                                       PCI_EXP_DEVSTA_NFED |
7350                                       PCI_EXP_DEVSTA_FED |
7351                                       PCI_EXP_DEVSTA_URD);
7352         }
7353
7354         tg3_restore_pci_state(tp);
7355
7356         tp->tg3_flags &= ~(TG3_FLAG_CHIP_RESETTING |
7357                            TG3_FLAG_ERROR_PROCESSED);
7358
7359         val = 0;
7360         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7361                 val = tr32(MEMARB_MODE);
7362         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7363
7364         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7365                 tg3_stop_fw(tp);
7366                 tw32(0x5000, 0x400);
7367         }
7368
7369         tw32(GRC_MODE, tp->grc_mode);
7370
7371         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7372                 val = tr32(0xc4);
7373
7374                 tw32(0xc4, val | (1 << 15));
7375         }
7376
7377         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7378             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7379                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7380                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7381                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7382                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7383         }
7384
7385         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7386                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7387                                MAC_MODE_APE_RX_EN |
7388                                MAC_MODE_TDE_ENABLE;
7389
7390         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7391                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7392                 val = tp->mac_mode;
7393         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7394                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7395                 val = tp->mac_mode;
7396         } else
7397                 val = 0;
7398
7399         tw32_f(MAC_MODE, val);
7400         udelay(40);
7401
7402         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7403
7404         err = tg3_poll_fw(tp);
7405         if (err)
7406                 return err;
7407
7408         tg3_mdio_start(tp);
7409
7410         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7411             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7412             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7413             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
7414                 val = tr32(0x7c00);
7415
7416                 tw32(0x7c00, val | (1 << 25));
7417         }
7418
7419         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7420                 val = tr32(TG3_CPMU_CLCK_ORIDE);
7421                 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7422         }
7423
7424         /* Reprobe ASF enable state.  */
7425         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7426         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7427         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7428         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7429                 u32 nic_cfg;
7430
7431                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7432                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7433                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7434                         tp->last_event_jiffies = jiffies;
7435                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7436                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7437                 }
7438         }
7439
7440         return 0;
7441 }
7442
7443 /* tp->lock is held. */
7444 static void tg3_stop_fw(struct tg3 *tp)
7445 {
7446         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7447            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7448                 /* Wait for RX cpu to ACK the previous event. */
7449                 tg3_wait_for_event_ack(tp);
7450
7451                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7452
7453                 tg3_generate_fw_event(tp);
7454
7455                 /* Wait for RX cpu to ACK this event. */
7456                 tg3_wait_for_event_ack(tp);
7457         }
7458 }
7459
7460 /* tp->lock is held. */
7461 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7462 {
7463         int err;
7464
7465         tg3_stop_fw(tp);
7466
7467         tg3_write_sig_pre_reset(tp, kind);
7468
7469         tg3_abort_hw(tp, silent);
7470         err = tg3_chip_reset(tp);
7471
7472         __tg3_set_mac_addr(tp, 0);
7473
7474         tg3_write_sig_legacy(tp, kind);
7475         tg3_write_sig_post_reset(tp, kind);
7476
7477         if (err)
7478                 return err;
7479
7480         return 0;
7481 }
7482
7483 #define RX_CPU_SCRATCH_BASE     0x30000
7484 #define RX_CPU_SCRATCH_SIZE     0x04000
7485 #define TX_CPU_SCRATCH_BASE     0x34000
7486 #define TX_CPU_SCRATCH_SIZE     0x04000
7487
7488 /* tp->lock is held. */
7489 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7490 {
7491         int i;
7492
7493         BUG_ON(offset == TX_CPU_BASE &&
7494             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7495
7496         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7497                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7498
7499                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7500                 return 0;
7501         }
7502         if (offset == RX_CPU_BASE) {
7503                 for (i = 0; i < 10000; i++) {
7504                         tw32(offset + CPU_STATE, 0xffffffff);
7505                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7506                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7507                                 break;
7508                 }
7509
7510                 tw32(offset + CPU_STATE, 0xffffffff);
7511                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7512                 udelay(10);
7513         } else {
7514                 for (i = 0; i < 10000; i++) {
7515                         tw32(offset + CPU_STATE, 0xffffffff);
7516                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7517                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7518                                 break;
7519                 }
7520         }
7521
7522         if (i >= 10000) {
7523                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7524                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7525                 return -ENODEV;
7526         }
7527
7528         /* Clear firmware's nvram arbitration. */
7529         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7530                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7531         return 0;
7532 }
7533
7534 struct fw_info {
7535         unsigned int fw_base;
7536         unsigned int fw_len;
7537         const __be32 *fw_data;
7538 };
7539
7540 /* tp->lock is held. */
7541 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7542                                  int cpu_scratch_size, struct fw_info *info)
7543 {
7544         int err, lock_err, i;
7545         void (*write_op)(struct tg3 *, u32, u32);
7546
7547         if (cpu_base == TX_CPU_BASE &&
7548             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7549                 netdev_err(tp->dev,
7550                            "%s: Trying to load TX cpu firmware which is 5705\n",
7551                            __func__);
7552                 return -EINVAL;
7553         }
7554
7555         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7556                 write_op = tg3_write_mem;
7557         else
7558                 write_op = tg3_write_indirect_reg32;
7559
7560         /* It is possible that bootcode is still loading at this point.
7561          * Get the nvram lock first before halting the cpu.
7562          */
7563         lock_err = tg3_nvram_lock(tp);
7564         err = tg3_halt_cpu(tp, cpu_base);
7565         if (!lock_err)
7566                 tg3_nvram_unlock(tp);
7567         if (err)
7568                 goto out;
7569
7570         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7571                 write_op(tp, cpu_scratch_base + i, 0);
7572         tw32(cpu_base + CPU_STATE, 0xffffffff);
7573         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7574         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7575                 write_op(tp, (cpu_scratch_base +
7576                               (info->fw_base & 0xffff) +
7577                               (i * sizeof(u32))),
7578                               be32_to_cpu(info->fw_data[i]));
7579
7580         err = 0;
7581
7582 out:
7583         return err;
7584 }
7585
7586 /* tp->lock is held. */
7587 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7588 {
7589         struct fw_info info;
7590         const __be32 *fw_data;
7591         int err, i;
7592
7593         fw_data = (void *)tp->fw->data;
7594
7595         /* Firmware blob starts with version numbers, followed by
7596            start address and length. We are setting complete length.
7597            length = end_address_of_bss - start_address_of_text.
7598            Remainder is the blob to be loaded contiguously
7599            from start address. */
7600
7601         info.fw_base = be32_to_cpu(fw_data[1]);
7602         info.fw_len = tp->fw->size - 12;
7603         info.fw_data = &fw_data[3];
7604
7605         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7606                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7607                                     &info);
7608         if (err)
7609                 return err;
7610
7611         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7612                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7613                                     &info);
7614         if (err)
7615                 return err;
7616
7617         /* Now startup only the RX cpu. */
7618         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7619         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7620
7621         for (i = 0; i < 5; i++) {
7622                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7623                         break;
7624                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7625                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7626                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7627                 udelay(1000);
7628         }
7629         if (i >= 5) {
7630                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7631                            "should be %08x\n", __func__,
7632                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7633                 return -ENODEV;
7634         }
7635         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7636         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7637
7638         return 0;
7639 }
7640
7641 /* 5705 needs a special version of the TSO firmware.  */
7642
7643 /* tp->lock is held. */
7644 static int tg3_load_tso_firmware(struct tg3 *tp)
7645 {
7646         struct fw_info info;
7647         const __be32 *fw_data;
7648         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7649         int err, i;
7650
7651         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7652                 return 0;
7653
7654         fw_data = (void *)tp->fw->data;
7655
7656         /* Firmware blob starts with version numbers, followed by
7657            start address and length. We are setting complete length.
7658            length = end_address_of_bss - start_address_of_text.
7659            Remainder is the blob to be loaded contiguously
7660            from start address. */
7661
7662         info.fw_base = be32_to_cpu(fw_data[1]);
7663         cpu_scratch_size = tp->fw_len;
7664         info.fw_len = tp->fw->size - 12;
7665         info.fw_data = &fw_data[3];
7666
7667         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7668                 cpu_base = RX_CPU_BASE;
7669                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7670         } else {
7671                 cpu_base = TX_CPU_BASE;
7672                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7673                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7674         }
7675
7676         err = tg3_load_firmware_cpu(tp, cpu_base,
7677                                     cpu_scratch_base, cpu_scratch_size,
7678                                     &info);
7679         if (err)
7680                 return err;
7681
7682         /* Now startup the cpu. */
7683         tw32(cpu_base + CPU_STATE, 0xffffffff);
7684         tw32_f(cpu_base + CPU_PC, info.fw_base);
7685
7686         for (i = 0; i < 5; i++) {
7687                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7688                         break;
7689                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7690                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7691                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7692                 udelay(1000);
7693         }
7694         if (i >= 5) {
7695                 netdev_err(tp->dev,
7696                            "%s fails to set CPU PC, is %08x should be %08x\n",
7697                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7698                 return -ENODEV;
7699         }
7700         tw32(cpu_base + CPU_STATE, 0xffffffff);
7701         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7702         return 0;
7703 }
7704
7705
7706 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7707 {
7708         struct tg3 *tp = netdev_priv(dev);
7709         struct sockaddr *addr = p;
7710         int err = 0, skip_mac_1 = 0;
7711
7712         if (!is_valid_ether_addr(addr->sa_data))
7713                 return -EINVAL;
7714
7715         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7716
7717         if (!netif_running(dev))
7718                 return 0;
7719
7720         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7721                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7722
7723                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7724                 addr0_low = tr32(MAC_ADDR_0_LOW);
7725                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7726                 addr1_low = tr32(MAC_ADDR_1_LOW);
7727
7728                 /* Skip MAC addr 1 if ASF is using it. */
7729                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7730                     !(addr1_high == 0 && addr1_low == 0))
7731                         skip_mac_1 = 1;
7732         }
7733         spin_lock_bh(&tp->lock);
7734         __tg3_set_mac_addr(tp, skip_mac_1);
7735         spin_unlock_bh(&tp->lock);
7736
7737         return err;
7738 }
7739
7740 /* tp->lock is held. */
7741 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7742                            dma_addr_t mapping, u32 maxlen_flags,
7743                            u32 nic_addr)
7744 {
7745         tg3_write_mem(tp,
7746                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7747                       ((u64) mapping >> 32));
7748         tg3_write_mem(tp,
7749                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7750                       ((u64) mapping & 0xffffffff));
7751         tg3_write_mem(tp,
7752                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7753                        maxlen_flags);
7754
7755         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7756                 tg3_write_mem(tp,
7757                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7758                               nic_addr);
7759 }
7760
7761 static void __tg3_set_rx_mode(struct net_device *);
7762 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7763 {
7764         int i;
7765
7766         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7767                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7768                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7769                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7770         } else {
7771                 tw32(HOSTCC_TXCOL_TICKS, 0);
7772                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7773                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7774         }
7775
7776         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7777                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7778                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7779                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7780         } else {
7781                 tw32(HOSTCC_RXCOL_TICKS, 0);
7782                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7783                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7784         }
7785
7786         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7787                 u32 val = ec->stats_block_coalesce_usecs;
7788
7789                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7790                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7791
7792                 if (!netif_carrier_ok(tp->dev))
7793                         val = 0;
7794
7795                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7796         }
7797
7798         for (i = 0; i < tp->irq_cnt - 1; i++) {
7799                 u32 reg;
7800
7801                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7802                 tw32(reg, ec->rx_coalesce_usecs);
7803                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7804                 tw32(reg, ec->rx_max_coalesced_frames);
7805                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7806                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7807
7808                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7809                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7810                         tw32(reg, ec->tx_coalesce_usecs);
7811                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7812                         tw32(reg, ec->tx_max_coalesced_frames);
7813                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7814                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7815                 }
7816         }
7817
7818         for (; i < tp->irq_max - 1; i++) {
7819                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7820                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7821                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7822
7823                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7824                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7825                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7826                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7827                 }
7828         }
7829 }
7830
7831 /* tp->lock is held. */
7832 static void tg3_rings_reset(struct tg3 *tp)
7833 {
7834         int i;
7835         u32 stblk, txrcb, rxrcb, limit;
7836         struct tg3_napi *tnapi = &tp->napi[0];
7837
7838         /* Disable all transmit rings but the first. */
7839         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7840                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7841         else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7842                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7843         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7844                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7845         else
7846                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7847
7848         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7849              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7850                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7851                               BDINFO_FLAGS_DISABLED);
7852
7853
7854         /* Disable all receive return rings but the first. */
7855         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7856                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7857         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7858                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7859         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7860                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7861                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7862         else
7863                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7864
7865         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7866              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7867                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7868                               BDINFO_FLAGS_DISABLED);
7869
7870         /* Disable interrupts */
7871         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7872
7873         /* Zero mailbox registers. */
7874         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7875                 for (i = 1; i < tp->irq_max; i++) {
7876                         tp->napi[i].tx_prod = 0;
7877                         tp->napi[i].tx_cons = 0;
7878                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7879                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7880                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7881                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7882                 }
7883                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7884                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7885         } else {
7886                 tp->napi[0].tx_prod = 0;
7887                 tp->napi[0].tx_cons = 0;
7888                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7889                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7890         }
7891
7892         /* Make sure the NIC-based send BD rings are disabled. */
7893         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7894                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7895                 for (i = 0; i < 16; i++)
7896                         tw32_tx_mbox(mbox + i * 8, 0);
7897         }
7898
7899         txrcb = NIC_SRAM_SEND_RCB;
7900         rxrcb = NIC_SRAM_RCV_RET_RCB;
7901
7902         /* Clear status block in ram. */
7903         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7904
7905         /* Set status block DMA address */
7906         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7907              ((u64) tnapi->status_mapping >> 32));
7908         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7909              ((u64) tnapi->status_mapping & 0xffffffff));
7910
7911         if (tnapi->tx_ring) {
7912                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7913                                (TG3_TX_RING_SIZE <<
7914                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7915                                NIC_SRAM_TX_BUFFER_DESC);
7916                 txrcb += TG3_BDINFO_SIZE;
7917         }
7918
7919         if (tnapi->rx_rcb) {
7920                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7921                                (tp->rx_ret_ring_mask + 1) <<
7922                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7923                 rxrcb += TG3_BDINFO_SIZE;
7924         }
7925
7926         stblk = HOSTCC_STATBLCK_RING1;
7927
7928         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7929                 u64 mapping = (u64)tnapi->status_mapping;
7930                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7931                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7932
7933                 /* Clear status block in ram. */
7934                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7935
7936                 if (tnapi->tx_ring) {
7937                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7938                                        (TG3_TX_RING_SIZE <<
7939                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7940                                        NIC_SRAM_TX_BUFFER_DESC);
7941                         txrcb += TG3_BDINFO_SIZE;
7942                 }
7943
7944                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7945                                ((tp->rx_ret_ring_mask + 1) <<
7946                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7947
7948                 stblk += 8;
7949                 rxrcb += TG3_BDINFO_SIZE;
7950         }
7951 }
7952
7953 /* tp->lock is held. */
7954 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7955 {
7956         u32 val, rdmac_mode;
7957         int i, err, limit;
7958         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7959
7960         tg3_disable_ints(tp);
7961
7962         tg3_stop_fw(tp);
7963
7964         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7965
7966         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7967                 tg3_abort_hw(tp, 1);
7968
7969         /* Enable MAC control of LPI */
7970         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7971                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7972                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7973                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7974
7975                 tw32_f(TG3_CPMU_EEE_CTRL,
7976                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7977
7978                 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7979                       TG3_CPMU_EEEMD_LPI_IN_TX |
7980                       TG3_CPMU_EEEMD_LPI_IN_RX |
7981                       TG3_CPMU_EEEMD_EEE_ENABLE;
7982
7983                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7984                         val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7985
7986                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7987                         val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7988
7989                 tw32_f(TG3_CPMU_EEE_MODE, val);
7990
7991                 tw32_f(TG3_CPMU_EEE_DBTMR1,
7992                        TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7993                        TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7994
7995                 tw32_f(TG3_CPMU_EEE_DBTMR2,
7996                        TG3_CPMU_DBTMR2_APE_TX_2047US |
7997                        TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7998         }
7999
8000         if (reset_phy)
8001                 tg3_phy_reset(tp);
8002
8003         err = tg3_chip_reset(tp);
8004         if (err)
8005                 return err;
8006
8007         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8008
8009         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8010                 val = tr32(TG3_CPMU_CTRL);
8011                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8012                 tw32(TG3_CPMU_CTRL, val);
8013
8014                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8015                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8016                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8017                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8018
8019                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8020                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8021                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8022                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8023
8024                 val = tr32(TG3_CPMU_HST_ACC);
8025                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8026                 val |= CPMU_HST_ACC_MACCLK_6_25;
8027                 tw32(TG3_CPMU_HST_ACC, val);
8028         }
8029
8030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8031                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8032                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8033                        PCIE_PWR_MGMT_L1_THRESH_4MS;
8034                 tw32(PCIE_PWR_MGMT_THRESH, val);
8035
8036                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8037                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8038
8039                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8040
8041                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8042                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8043         }
8044
8045         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
8046                 u32 grc_mode = tr32(GRC_MODE);
8047
8048                 /* Access the lower 1K of PL PCIE block registers. */
8049                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8050                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8051
8052                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8053                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8054                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8055
8056                 tw32(GRC_MODE, grc_mode);
8057         }
8058
8059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8060                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8061                         u32 grc_mode = tr32(GRC_MODE);
8062
8063                         /* Access the lower 1K of PL PCIE block registers. */
8064                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8065                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8066
8067                         val = tr32(TG3_PCIE_TLDLPL_PORT +
8068                                    TG3_PCIE_PL_LO_PHYCTL5);
8069                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8070                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8071
8072                         tw32(GRC_MODE, grc_mode);
8073                 }
8074
8075                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8076                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8077                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8078                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8079         }
8080
8081         /* This works around an issue with Athlon chipsets on
8082          * B3 tigon3 silicon.  This bit has no effect on any
8083          * other revision.  But do not set this on PCI Express
8084          * chips and don't even touch the clocks if the CPMU is present.
8085          */
8086         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
8087                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8088                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8089                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8090         }
8091
8092         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8093             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
8094                 val = tr32(TG3PCI_PCISTATE);
8095                 val |= PCISTATE_RETRY_SAME_DMA;
8096                 tw32(TG3PCI_PCISTATE, val);
8097         }
8098
8099         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
8100                 /* Allow reads and writes to the
8101                  * APE register and memory space.
8102                  */
8103                 val = tr32(TG3PCI_PCISTATE);
8104                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8105                        PCISTATE_ALLOW_APE_SHMEM_WR |
8106                        PCISTATE_ALLOW_APE_PSPACE_WR;
8107                 tw32(TG3PCI_PCISTATE, val);
8108         }
8109
8110         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8111                 /* Enable some hw fixes.  */
8112                 val = tr32(TG3PCI_MSI_DATA);
8113                 val |= (1 << 26) | (1 << 28) | (1 << 29);
8114                 tw32(TG3PCI_MSI_DATA, val);
8115         }
8116
8117         /* Descriptor ring init may make accesses to the
8118          * NIC SRAM area to setup the TX descriptors, so we
8119          * can only do this after the hardware has been
8120          * successfully reset.
8121          */
8122         err = tg3_init_rings(tp);
8123         if (err)
8124                 return err;
8125
8126         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8127                 val = tr32(TG3PCI_DMA_RW_CTRL) &
8128                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8129                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8130                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8131                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8132         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8133                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8134                 /* This value is determined during the probe time DMA
8135                  * engine test, tg3_test_dma.
8136                  */
8137                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8138         }
8139
8140         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8141                           GRC_MODE_4X_NIC_SEND_RINGS |
8142                           GRC_MODE_NO_TX_PHDR_CSUM |
8143                           GRC_MODE_NO_RX_PHDR_CSUM);
8144         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8145
8146         /* Pseudo-header checksum is done by hardware logic and not
8147          * the offload processers, so make the chip do the pseudo-
8148          * header checksums on receive.  For transmit it is more
8149          * convenient to do the pseudo-header checksum in software
8150          * as Linux does that on transmit for us in all cases.
8151          */
8152         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8153
8154         tw32(GRC_MODE,
8155              tp->grc_mode |
8156              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8157
8158         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
8159         val = tr32(GRC_MISC_CFG);
8160         val &= ~0xff;
8161         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8162         tw32(GRC_MISC_CFG, val);
8163
8164         /* Initialize MBUF/DESC pool. */
8165         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8166                 /* Do nothing.  */
8167         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8168                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8169                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8170                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8171                 else
8172                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8173                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8174                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8175         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8176                 int fw_len;
8177
8178                 fw_len = tp->fw_len;
8179                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8180                 tw32(BUFMGR_MB_POOL_ADDR,
8181                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8182                 tw32(BUFMGR_MB_POOL_SIZE,
8183                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8184         }
8185
8186         if (tp->dev->mtu <= ETH_DATA_LEN) {
8187                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8188                      tp->bufmgr_config.mbuf_read_dma_low_water);
8189                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8190                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8191                 tw32(BUFMGR_MB_HIGH_WATER,
8192                      tp->bufmgr_config.mbuf_high_water);
8193         } else {
8194                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8195                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8196                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8197                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8198                 tw32(BUFMGR_MB_HIGH_WATER,
8199                      tp->bufmgr_config.mbuf_high_water_jumbo);
8200         }
8201         tw32(BUFMGR_DMA_LOW_WATER,
8202              tp->bufmgr_config.dma_low_water);
8203         tw32(BUFMGR_DMA_HIGH_WATER,
8204              tp->bufmgr_config.dma_high_water);
8205
8206         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8208                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8209         tw32(BUFMGR_MODE, val);
8210         for (i = 0; i < 2000; i++) {
8211                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8212                         break;
8213                 udelay(10);
8214         }
8215         if (i >= 2000) {
8216                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8217                 return -ENODEV;
8218         }
8219
8220         /* Setup replenish threshold. */
8221         val = tp->rx_pending / 8;
8222         if (val == 0)
8223                 val = 1;
8224         else if (val > tp->rx_std_max_post)
8225                 val = tp->rx_std_max_post;
8226         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8227                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8228                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8229
8230                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8231                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8232         }
8233
8234         tw32(RCVBDI_STD_THRESH, val);
8235
8236         /* Initialize TG3_BDINFO's at:
8237          *  RCVDBDI_STD_BD:     standard eth size rx ring
8238          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8239          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8240          *
8241          * like so:
8242          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8243          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8244          *                              ring attribute flags
8245          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8246          *
8247          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8248          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8249          *
8250          * The size of each ring is fixed in the firmware, but the location is
8251          * configurable.
8252          */
8253         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8254              ((u64) tpr->rx_std_mapping >> 32));
8255         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8256              ((u64) tpr->rx_std_mapping & 0xffffffff));
8257         if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
8258                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8259                      NIC_SRAM_RX_BUFFER_DESC);
8260
8261         /* Disable the mini ring */
8262         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8263                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8264                      BDINFO_FLAGS_DISABLED);
8265
8266         /* Program the jumbo buffer descriptor ring control
8267          * blocks on those devices that have them.
8268          */
8269         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8270             ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8271             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
8272                 /* Setup replenish threshold. */
8273                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8274
8275                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8276                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8277                              ((u64) tpr->rx_jmb_mapping >> 32));
8278                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8279                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8280                         val = TG3_RX_JMB_RING_SIZE(tp) <<
8281                               BDINFO_FLAGS_MAXLEN_SHIFT;
8282                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8283                              val | BDINFO_FLAGS_USE_EXT_RECV);
8284                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8285                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8286                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8287                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8288                 } else {
8289                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8290                              BDINFO_FLAGS_DISABLED);
8291                 }
8292
8293                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8294                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8295                                 val = TG3_RX_STD_MAX_SIZE_5700;
8296                         else
8297                                 val = TG3_RX_STD_MAX_SIZE_5717;
8298                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8299                         val |= (TG3_RX_STD_DMA_SZ << 2);
8300                 } else
8301                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8302         } else
8303                 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8304
8305         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8306
8307         tpr->rx_std_prod_idx = tp->rx_pending;
8308         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8309
8310         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8311                           tp->rx_jumbo_pending : 0;
8312         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8313
8314         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
8315                 tw32(STD_REPLENISH_LWM, 32);
8316                 tw32(JMB_REPLENISH_LWM, 16);
8317         }
8318
8319         tg3_rings_reset(tp);
8320
8321         /* Initialize MAC address and backoff seed. */
8322         __tg3_set_mac_addr(tp, 0);
8323
8324         /* MTU + ethernet header + FCS + optional VLAN tag */
8325         tw32(MAC_RX_MTU_SIZE,
8326              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8327
8328         /* The slot time is changed by tg3_setup_phy if we
8329          * run at gigabit with half duplex.
8330          */
8331         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8332               (6 << TX_LENGTHS_IPG_SHIFT) |
8333               (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8334
8335         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8336                 val |= tr32(MAC_TX_LENGTHS) &
8337                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
8338                         TX_LENGTHS_CNT_DWN_VAL_MSK);
8339
8340         tw32(MAC_TX_LENGTHS, val);
8341
8342         /* Receive rules. */
8343         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8344         tw32(RCVLPC_CONFIG, 0x0181);
8345
8346         /* Calculate RDMAC_MODE setting early, we need it to determine
8347          * the RCVLPC_STATE_ENABLE mask.
8348          */
8349         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8350                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8351                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8352                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8353                       RDMAC_MODE_LNGREAD_ENAB);
8354
8355         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8356                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8357
8358         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8359             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8360             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8361                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8362                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8363                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8364
8365         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8366             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8367                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8368                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8369                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8370                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8371                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8372                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8373                 }
8374         }
8375
8376         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8377                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8378
8379         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8380                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8381
8382         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8383             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8384             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8385                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8386
8387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8388                 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8389
8390         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8391             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8392             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8393             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8394             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
8395                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8396                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8397                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8398                         val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8399                                  TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8400                                  TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8401                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8402                                TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8403                                TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8404                 }
8405                 tw32(TG3_RDMA_RSRVCTRL_REG,
8406                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8407         }
8408
8409         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8410             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8411                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8412                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8413                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8414                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8415         }
8416
8417         /* Receive/send statistics. */
8418         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8419                 val = tr32(RCVLPC_STATS_ENABLE);
8420                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8421                 tw32(RCVLPC_STATS_ENABLE, val);
8422         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8423                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8424                 val = tr32(RCVLPC_STATS_ENABLE);
8425                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8426                 tw32(RCVLPC_STATS_ENABLE, val);
8427         } else {
8428                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8429         }
8430         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8431         tw32(SNDDATAI_STATSENAB, 0xffffff);
8432         tw32(SNDDATAI_STATSCTRL,
8433              (SNDDATAI_SCTRL_ENABLE |
8434               SNDDATAI_SCTRL_FASTUPD));
8435
8436         /* Setup host coalescing engine. */
8437         tw32(HOSTCC_MODE, 0);
8438         for (i = 0; i < 2000; i++) {
8439                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8440                         break;
8441                 udelay(10);
8442         }
8443
8444         __tg3_set_coalesce(tp, &tp->coal);
8445
8446         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8447                 /* Status/statistics block address.  See tg3_timer,
8448                  * the tg3_periodic_fetch_stats call there, and
8449                  * tg3_get_stats to see how this works for 5705/5750 chips.
8450                  */
8451                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8452                      ((u64) tp->stats_mapping >> 32));
8453                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8454                      ((u64) tp->stats_mapping & 0xffffffff));
8455                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8456
8457                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8458
8459                 /* Clear statistics and status block memory areas */
8460                 for (i = NIC_SRAM_STATS_BLK;
8461                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8462                      i += sizeof(u32)) {
8463                         tg3_write_mem(tp, i, 0);
8464                         udelay(40);
8465                 }
8466         }
8467
8468         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8469
8470         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8471         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8472         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8473                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8474
8475         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8476                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8477                 /* reset to prevent losing 1st rx packet intermittently */
8478                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8479                 udelay(10);
8480         }
8481
8482         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8483                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8484         else
8485                 tp->mac_mode = 0;
8486         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8487                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8488         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8489             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8490             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8491                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8492         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8493         udelay(40);
8494
8495         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8496          * If TG3_FLG2_IS_NIC is zero, we should read the
8497          * register to preserve the GPIO settings for LOMs. The GPIOs,
8498          * whether used as inputs or outputs, are set by boot code after
8499          * reset.
8500          */
8501         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8502                 u32 gpio_mask;
8503
8504                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8505                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8506                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8507
8508                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8509                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8510                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8511
8512                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8513                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8514
8515                 tp->grc_local_ctrl &= ~gpio_mask;
8516                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8517
8518                 /* GPIO1 must be driven high for eeprom write protect */
8519                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8520                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8521                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8522         }
8523         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8524         udelay(100);
8525
8526         if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
8527                 tp->irq_cnt > 1) {
8528                 val = tr32(MSGINT_MODE);
8529                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8530                 tw32(MSGINT_MODE, val);
8531         }
8532
8533         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8534                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8535                 udelay(40);
8536         }
8537
8538         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8539                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8540                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8541                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8542                WDMAC_MODE_LNGREAD_ENAB);
8543
8544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8545             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8546                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8547                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8548                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8549                         /* nothing */
8550                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8551                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8552                         val |= WDMAC_MODE_RX_ACCEL;
8553                 }
8554         }
8555
8556         /* Enable host coalescing bug fix */
8557         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8558                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8559
8560         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8561                 val |= WDMAC_MODE_BURST_ALL_DATA;
8562
8563         tw32_f(WDMAC_MODE, val);
8564         udelay(40);
8565
8566         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8567                 u16 pcix_cmd;
8568
8569                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8570                                      &pcix_cmd);
8571                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8572                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8573                         pcix_cmd |= PCI_X_CMD_READ_2K;
8574                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8575                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8576                         pcix_cmd |= PCI_X_CMD_READ_2K;
8577                 }
8578                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8579                                       pcix_cmd);
8580         }
8581
8582         tw32_f(RDMAC_MODE, rdmac_mode);
8583         udelay(40);
8584
8585         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8586         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8587                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8588
8589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8590                 tw32(SNDDATAC_MODE,
8591                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8592         else
8593                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8594
8595         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8596         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8597         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8598         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
8599                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8600         tw32(RCVDBDI_MODE, val);
8601         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8602         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8603                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8604         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8605         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8606                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8607         tw32(SNDBDI_MODE, val);
8608         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8609
8610         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8611                 err = tg3_load_5701_a0_firmware_fix(tp);
8612                 if (err)
8613                         return err;
8614         }
8615
8616         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8617                 err = tg3_load_tso_firmware(tp);
8618                 if (err)
8619                         return err;
8620         }
8621
8622         tp->tx_mode = TX_MODE_ENABLE;
8623
8624         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8625             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8626                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8627
8628         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8629                 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8630                 tp->tx_mode &= ~val;
8631                 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8632         }
8633
8634         tw32_f(MAC_TX_MODE, tp->tx_mode);
8635         udelay(100);
8636
8637         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8638                 u32 reg = MAC_RSS_INDIR_TBL_0;
8639                 u8 *ent = (u8 *)&val;
8640
8641                 /* Setup the indirection table */
8642                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8643                         int idx = i % sizeof(val);
8644
8645                         ent[idx] = i % (tp->irq_cnt - 1);
8646                         if (idx == sizeof(val) - 1) {
8647                                 tw32(reg, val);
8648                                 reg += 4;
8649                         }
8650                 }
8651
8652                 /* Setup the "secret" hash key. */
8653                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8654                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8655                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8656                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8657                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8658                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8659                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8660                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8661                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8662                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8663         }
8664
8665         tp->rx_mode = RX_MODE_ENABLE;
8666         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8667                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8668
8669         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8670                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8671                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8672                                RX_MODE_RSS_IPV6_HASH_EN |
8673                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8674                                RX_MODE_RSS_IPV4_HASH_EN |
8675                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8676
8677         tw32_f(MAC_RX_MODE, tp->rx_mode);
8678         udelay(10);
8679
8680         tw32(MAC_LED_CTRL, tp->led_ctrl);
8681
8682         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8683         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8684                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8685                 udelay(10);
8686         }
8687         tw32_f(MAC_RX_MODE, tp->rx_mode);
8688         udelay(10);
8689
8690         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8691                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8692                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8693                         /* Set drive transmission level to 1.2V  */
8694                         /* only if the signal pre-emphasis bit is not set  */
8695                         val = tr32(MAC_SERDES_CFG);
8696                         val &= 0xfffff000;
8697                         val |= 0x880;
8698                         tw32(MAC_SERDES_CFG, val);
8699                 }
8700                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8701                         tw32(MAC_SERDES_CFG, 0x616000);
8702         }
8703
8704         /* Prevent chip from dropping frames when flow control
8705          * is enabled.
8706          */
8707         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8708                 val = 1;
8709         else
8710                 val = 2;
8711         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8712
8713         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8714             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8715                 /* Use hardware link auto-negotiation */
8716                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8717         }
8718
8719         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8720             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8721                 u32 tmp;
8722
8723                 tmp = tr32(SERDES_RX_CTRL);
8724                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8725                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8726                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8727                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8728         }
8729
8730         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8731                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8732                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8733                         tp->link_config.speed = tp->link_config.orig_speed;
8734                         tp->link_config.duplex = tp->link_config.orig_duplex;
8735                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8736                 }
8737
8738                 err = tg3_setup_phy(tp, 0);
8739                 if (err)
8740                         return err;
8741
8742                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8743                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8744                         u32 tmp;
8745
8746                         /* Clear CRC stats. */
8747                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8748                                 tg3_writephy(tp, MII_TG3_TEST1,
8749                                              tmp | MII_TG3_TEST1_CRC_EN);
8750                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8751                         }
8752                 }
8753         }
8754
8755         __tg3_set_rx_mode(tp->dev);
8756
8757         /* Initialize receive rules. */
8758         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8759         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8760         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8761         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8762
8763         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8764             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8765                 limit = 8;
8766         else
8767                 limit = 16;
8768         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8769                 limit -= 4;
8770         switch (limit) {
8771         case 16:
8772                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8773         case 15:
8774                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8775         case 14:
8776                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8777         case 13:
8778                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8779         case 12:
8780                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8781         case 11:
8782                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8783         case 10:
8784                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8785         case 9:
8786                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8787         case 8:
8788                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8789         case 7:
8790                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8791         case 6:
8792                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8793         case 5:
8794                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8795         case 4:
8796                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8797         case 3:
8798                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8799         case 2:
8800         case 1:
8801
8802         default:
8803                 break;
8804         }
8805
8806         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8807                 /* Write our heartbeat update interval to APE. */
8808                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8809                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8810
8811         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8812
8813         return 0;
8814 }
8815
8816 /* Called at device open time to get the chip ready for
8817  * packet processing.  Invoked with tp->lock held.
8818  */
8819 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8820 {
8821         tg3_switch_clocks(tp);
8822
8823         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8824
8825         return tg3_reset_hw(tp, reset_phy);
8826 }
8827
8828 #define TG3_STAT_ADD32(PSTAT, REG) \
8829 do {    u32 __val = tr32(REG); \
8830         (PSTAT)->low += __val; \
8831         if ((PSTAT)->low < __val) \
8832                 (PSTAT)->high += 1; \
8833 } while (0)
8834
8835 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8836 {
8837         struct tg3_hw_stats *sp = tp->hw_stats;
8838
8839         if (!netif_carrier_ok(tp->dev))
8840                 return;
8841
8842         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8843         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8844         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8845         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8846         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8847         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8848         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8849         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8850         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8851         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8852         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8853         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8854         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8855
8856         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8857         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8858         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8859         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8860         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8861         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8862         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8863         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8864         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8865         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8866         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8867         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8868         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8869         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8870
8871         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8872         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8873         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8874 }
8875
8876 static void tg3_timer(unsigned long __opaque)
8877 {
8878         struct tg3 *tp = (struct tg3 *) __opaque;
8879
8880         if (tp->irq_sync)
8881                 goto restart_timer;
8882
8883         spin_lock(&tp->lock);
8884
8885         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8886                 /* All of this garbage is because when using non-tagged
8887                  * IRQ status the mailbox/status_block protocol the chip
8888                  * uses with the cpu is race prone.
8889                  */
8890                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8891                         tw32(GRC_LOCAL_CTRL,
8892                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8893                 } else {
8894                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8895                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8896                 }
8897
8898                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8899                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8900                         spin_unlock(&tp->lock);
8901                         schedule_work(&tp->reset_task);
8902                         return;
8903                 }
8904         }
8905
8906         /* This part only runs once per second. */
8907         if (!--tp->timer_counter) {
8908                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8909                         tg3_periodic_fetch_stats(tp);
8910
8911                 if (tp->setlpicnt && !--tp->setlpicnt) {
8912                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8913                         tw32(TG3_CPMU_EEE_MODE,
8914                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8915                 }
8916
8917                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8918                         u32 mac_stat;
8919                         int phy_event;
8920
8921                         mac_stat = tr32(MAC_STATUS);
8922
8923                         phy_event = 0;
8924                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8925                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8926                                         phy_event = 1;
8927                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8928                                 phy_event = 1;
8929
8930                         if (phy_event)
8931                                 tg3_setup_phy(tp, 0);
8932                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8933                         u32 mac_stat = tr32(MAC_STATUS);
8934                         int need_setup = 0;
8935
8936                         if (netif_carrier_ok(tp->dev) &&
8937                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8938                                 need_setup = 1;
8939                         }
8940                         if (!netif_carrier_ok(tp->dev) &&
8941                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8942                                          MAC_STATUS_SIGNAL_DET))) {
8943                                 need_setup = 1;
8944                         }
8945                         if (need_setup) {
8946                                 if (!tp->serdes_counter) {
8947                                         tw32_f(MAC_MODE,
8948                                              (tp->mac_mode &
8949                                               ~MAC_MODE_PORT_MODE_MASK));
8950                                         udelay(40);
8951                                         tw32_f(MAC_MODE, tp->mac_mode);
8952                                         udelay(40);
8953                                 }
8954                                 tg3_setup_phy(tp, 0);
8955                         }
8956                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8957                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8958                         tg3_serdes_parallel_detect(tp);
8959                 }
8960
8961                 tp->timer_counter = tp->timer_multiplier;
8962         }
8963
8964         /* Heartbeat is only sent once every 2 seconds.
8965          *
8966          * The heartbeat is to tell the ASF firmware that the host
8967          * driver is still alive.  In the event that the OS crashes,
8968          * ASF needs to reset the hardware to free up the FIFO space
8969          * that may be filled with rx packets destined for the host.
8970          * If the FIFO is full, ASF will no longer function properly.
8971          *
8972          * Unintended resets have been reported on real time kernels
8973          * where the timer doesn't run on time.  Netpoll will also have
8974          * same problem.
8975          *
8976          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8977          * to check the ring condition when the heartbeat is expiring
8978          * before doing the reset.  This will prevent most unintended
8979          * resets.
8980          */
8981         if (!--tp->asf_counter) {
8982                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8983                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8984                         tg3_wait_for_event_ack(tp);
8985
8986                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8987                                       FWCMD_NICDRV_ALIVE3);
8988                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8989                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8990                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8991
8992                         tg3_generate_fw_event(tp);
8993                 }
8994                 tp->asf_counter = tp->asf_multiplier;
8995         }
8996
8997         spin_unlock(&tp->lock);
8998
8999 restart_timer:
9000         tp->timer.expires = jiffies + tp->timer_offset;
9001         add_timer(&tp->timer);
9002 }
9003
9004 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9005 {
9006         irq_handler_t fn;
9007         unsigned long flags;
9008         char *name;
9009         struct tg3_napi *tnapi = &tp->napi[irq_num];
9010
9011         if (tp->irq_cnt == 1)
9012                 name = tp->dev->name;
9013         else {
9014                 name = &tnapi->irq_lbl[0];
9015                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9016                 name[IFNAMSIZ-1] = 0;
9017         }
9018
9019         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9020                 fn = tg3_msi;
9021                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
9022                         fn = tg3_msi_1shot;
9023                 flags = 0;
9024         } else {
9025                 fn = tg3_interrupt;
9026                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9027                         fn = tg3_interrupt_tagged;
9028                 flags = IRQF_SHARED;
9029         }
9030
9031         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9032 }
9033
9034 static int tg3_test_interrupt(struct tg3 *tp)
9035 {
9036         struct tg3_napi *tnapi = &tp->napi[0];
9037         struct net_device *dev = tp->dev;
9038         int err, i, intr_ok = 0;
9039         u32 val;
9040
9041         if (!netif_running(dev))
9042                 return -ENODEV;
9043
9044         tg3_disable_ints(tp);
9045
9046         free_irq(tnapi->irq_vec, tnapi);
9047
9048         /*
9049          * Turn off MSI one shot mode.  Otherwise this test has no
9050          * observable way to know whether the interrupt was delivered.
9051          */
9052         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9053             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9054                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9055                 tw32(MSGINT_MODE, val);
9056         }
9057
9058         err = request_irq(tnapi->irq_vec, tg3_test_isr,
9059                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9060         if (err)
9061                 return err;
9062
9063         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9064         tg3_enable_ints(tp);
9065
9066         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9067                tnapi->coal_now);
9068
9069         for (i = 0; i < 5; i++) {
9070                 u32 int_mbox, misc_host_ctrl;
9071
9072                 int_mbox = tr32_mailbox(tnapi->int_mbox);
9073                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9074
9075                 if ((int_mbox != 0) ||
9076                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9077                         intr_ok = 1;
9078                         break;
9079                 }
9080
9081                 msleep(10);
9082         }
9083
9084         tg3_disable_ints(tp);
9085
9086         free_irq(tnapi->irq_vec, tnapi);
9087
9088         err = tg3_request_irq(tp, 0);
9089
9090         if (err)
9091                 return err;
9092
9093         if (intr_ok) {
9094                 /* Reenable MSI one shot mode. */
9095                 if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9096                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9097                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9098                         tw32(MSGINT_MODE, val);
9099                 }
9100                 return 0;
9101         }
9102
9103         return -EIO;
9104 }
9105
9106 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9107  * successfully restored
9108  */
9109 static int tg3_test_msi(struct tg3 *tp)
9110 {
9111         int err;
9112         u16 pci_cmd;
9113
9114         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
9115                 return 0;
9116
9117         /* Turn off SERR reporting in case MSI terminates with Master
9118          * Abort.
9119          */
9120         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9121         pci_write_config_word(tp->pdev, PCI_COMMAND,
9122                               pci_cmd & ~PCI_COMMAND_SERR);
9123
9124         err = tg3_test_interrupt(tp);
9125
9126         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9127
9128         if (!err)
9129                 return 0;
9130
9131         /* other failures */
9132         if (err != -EIO)
9133                 return err;
9134
9135         /* MSI test failed, go back to INTx mode */
9136         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9137                     "to INTx mode. Please report this failure to the PCI "
9138                     "maintainer and include system chipset information\n");
9139
9140         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9141
9142         pci_disable_msi(tp->pdev);
9143
9144         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
9145         tp->napi[0].irq_vec = tp->pdev->irq;
9146
9147         err = tg3_request_irq(tp, 0);
9148         if (err)
9149                 return err;
9150
9151         /* Need to reset the chip because the MSI cycle may have terminated
9152          * with Master Abort.
9153          */
9154         tg3_full_lock(tp, 1);
9155
9156         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9157         err = tg3_init_hw(tp, 1);
9158
9159         tg3_full_unlock(tp);
9160
9161         if (err)
9162                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9163
9164         return err;
9165 }
9166
9167 static int tg3_request_firmware(struct tg3 *tp)
9168 {
9169         const __be32 *fw_data;
9170
9171         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9172                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9173                            tp->fw_needed);
9174                 return -ENOENT;
9175         }
9176
9177         fw_data = (void *)tp->fw->data;
9178
9179         /* Firmware blob starts with version numbers, followed by
9180          * start address and _full_ length including BSS sections
9181          * (which must be longer than the actual data, of course
9182          */
9183
9184         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
9185         if (tp->fw_len < (tp->fw->size - 12)) {
9186                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9187                            tp->fw_len, tp->fw_needed);
9188                 release_firmware(tp->fw);
9189                 tp->fw = NULL;
9190                 return -EINVAL;
9191         }
9192
9193         /* We no longer need firmware; we have it. */
9194         tp->fw_needed = NULL;
9195         return 0;
9196 }
9197
9198 static bool tg3_enable_msix(struct tg3 *tp)
9199 {
9200         int i, rc, cpus = num_online_cpus();
9201         struct msix_entry msix_ent[tp->irq_max];
9202
9203         if (cpus == 1)
9204                 /* Just fallback to the simpler MSI mode. */
9205                 return false;
9206
9207         /*
9208          * We want as many rx rings enabled as there are cpus.
9209          * The first MSIX vector only deals with link interrupts, etc,
9210          * so we add one to the number of vectors we are requesting.
9211          */
9212         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9213
9214         for (i = 0; i < tp->irq_max; i++) {
9215                 msix_ent[i].entry  = i;
9216                 msix_ent[i].vector = 0;
9217         }
9218
9219         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9220         if (rc < 0) {
9221                 return false;
9222         } else if (rc != 0) {
9223                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9224                         return false;
9225                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9226                               tp->irq_cnt, rc);
9227                 tp->irq_cnt = rc;
9228         }
9229
9230         for (i = 0; i < tp->irq_max; i++)
9231                 tp->napi[i].irq_vec = msix_ent[i].vector;
9232
9233         netif_set_real_num_tx_queues(tp->dev, 1);
9234         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9235         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9236                 pci_disable_msix(tp->pdev);
9237                 return false;
9238         }
9239
9240         if (tp->irq_cnt > 1) {
9241                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9242
9243                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9244                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9245                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9246                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9247                 }
9248         }
9249
9250         return true;
9251 }
9252
9253 static void tg3_ints_init(struct tg3 *tp)
9254 {
9255         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9256             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9257                 /* All MSI supporting chips should support tagged
9258                  * status.  Assert that this is the case.
9259                  */
9260                 netdev_warn(tp->dev,
9261                             "MSI without TAGGED_STATUS? Not using MSI\n");
9262                 goto defcfg;
9263         }
9264
9265         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9266                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9267         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9268                  pci_enable_msi(tp->pdev) == 0)
9269                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9270
9271         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9272                 u32 msi_mode = tr32(MSGINT_MODE);
9273                 if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
9274                     tp->irq_cnt > 1)
9275                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9276                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9277         }
9278 defcfg:
9279         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9280                 tp->irq_cnt = 1;
9281                 tp->napi[0].irq_vec = tp->pdev->irq;
9282                 netif_set_real_num_tx_queues(tp->dev, 1);
9283                 netif_set_real_num_rx_queues(tp->dev, 1);
9284         }
9285 }
9286
9287 static void tg3_ints_fini(struct tg3 *tp)
9288 {
9289         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9290                 pci_disable_msix(tp->pdev);
9291         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9292                 pci_disable_msi(tp->pdev);
9293         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9294         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9295 }
9296
9297 static int tg3_open(struct net_device *dev)
9298 {
9299         struct tg3 *tp = netdev_priv(dev);
9300         int i, err;
9301
9302         if (tp->fw_needed) {
9303                 err = tg3_request_firmware(tp);
9304                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9305                         if (err)
9306                                 return err;
9307                 } else if (err) {
9308                         netdev_warn(tp->dev, "TSO capability disabled\n");
9309                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9310                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9311                         netdev_notice(tp->dev, "TSO capability restored\n");
9312                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9313                 }
9314         }
9315
9316         netif_carrier_off(tp->dev);
9317
9318         err = tg3_power_up(tp);
9319         if (err)
9320                 return err;
9321
9322         tg3_full_lock(tp, 0);
9323
9324         tg3_disable_ints(tp);
9325         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9326
9327         tg3_full_unlock(tp);
9328
9329         /*
9330          * Setup interrupts first so we know how
9331          * many NAPI resources to allocate
9332          */
9333         tg3_ints_init(tp);
9334
9335         /* The placement of this call is tied
9336          * to the setup and use of Host TX descriptors.
9337          */
9338         err = tg3_alloc_consistent(tp);
9339         if (err)
9340                 goto err_out1;
9341
9342         tg3_napi_init(tp);
9343
9344         tg3_napi_enable(tp);
9345
9346         for (i = 0; i < tp->irq_cnt; i++) {
9347                 struct tg3_napi *tnapi = &tp->napi[i];
9348                 err = tg3_request_irq(tp, i);
9349                 if (err) {
9350                         for (i--; i >= 0; i--)
9351                                 free_irq(tnapi->irq_vec, tnapi);
9352                         break;
9353                 }
9354         }
9355
9356         if (err)
9357                 goto err_out2;
9358
9359         tg3_full_lock(tp, 0);
9360
9361         err = tg3_init_hw(tp, 1);
9362         if (err) {
9363                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9364                 tg3_free_rings(tp);
9365         } else {
9366                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9367                         tp->timer_offset = HZ;
9368                 else
9369                         tp->timer_offset = HZ / 10;
9370
9371                 BUG_ON(tp->timer_offset > HZ);
9372                 tp->timer_counter = tp->timer_multiplier =
9373                         (HZ / tp->timer_offset);
9374                 tp->asf_counter = tp->asf_multiplier =
9375                         ((HZ / tp->timer_offset) * 2);
9376
9377                 init_timer(&tp->timer);
9378                 tp->timer.expires = jiffies + tp->timer_offset;
9379                 tp->timer.data = (unsigned long) tp;
9380                 tp->timer.function = tg3_timer;
9381         }
9382
9383         tg3_full_unlock(tp);
9384
9385         if (err)
9386                 goto err_out3;
9387
9388         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9389                 err = tg3_test_msi(tp);
9390
9391                 if (err) {
9392                         tg3_full_lock(tp, 0);
9393                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9394                         tg3_free_rings(tp);
9395                         tg3_full_unlock(tp);
9396
9397                         goto err_out2;
9398                 }
9399
9400                 if (!(tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
9401                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9402                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9403
9404                         tw32(PCIE_TRANSACTION_CFG,
9405                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9406                 }
9407         }
9408
9409         tg3_phy_start(tp);
9410
9411         tg3_full_lock(tp, 0);
9412
9413         add_timer(&tp->timer);
9414         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9415         tg3_enable_ints(tp);
9416
9417         tg3_full_unlock(tp);
9418
9419         netif_tx_start_all_queues(dev);
9420
9421         return 0;
9422
9423 err_out3:
9424         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9425                 struct tg3_napi *tnapi = &tp->napi[i];
9426                 free_irq(tnapi->irq_vec, tnapi);
9427         }
9428
9429 err_out2:
9430         tg3_napi_disable(tp);
9431         tg3_napi_fini(tp);
9432         tg3_free_consistent(tp);
9433
9434 err_out1:
9435         tg3_ints_fini(tp);
9436         return err;
9437 }
9438
9439 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9440                                                  struct rtnl_link_stats64 *);
9441 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9442
9443 static int tg3_close(struct net_device *dev)
9444 {
9445         int i;
9446         struct tg3 *tp = netdev_priv(dev);
9447
9448         tg3_napi_disable(tp);
9449         cancel_work_sync(&tp->reset_task);
9450
9451         netif_tx_stop_all_queues(dev);
9452
9453         del_timer_sync(&tp->timer);
9454
9455         tg3_phy_stop(tp);
9456
9457         tg3_full_lock(tp, 1);
9458
9459         tg3_disable_ints(tp);
9460
9461         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9462         tg3_free_rings(tp);
9463         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9464
9465         tg3_full_unlock(tp);
9466
9467         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9468                 struct tg3_napi *tnapi = &tp->napi[i];
9469                 free_irq(tnapi->irq_vec, tnapi);
9470         }
9471
9472         tg3_ints_fini(tp);
9473
9474         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9475
9476         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9477                sizeof(tp->estats_prev));
9478
9479         tg3_napi_fini(tp);
9480
9481         tg3_free_consistent(tp);
9482
9483         tg3_power_down(tp);
9484
9485         netif_carrier_off(tp->dev);
9486
9487         return 0;
9488 }
9489
9490 static inline u64 get_stat64(tg3_stat64_t *val)
9491 {
9492        return ((u64)val->high << 32) | ((u64)val->low);
9493 }
9494
9495 static u64 calc_crc_errors(struct tg3 *tp)
9496 {
9497         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9498
9499         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9500             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9501              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9502                 u32 val;
9503
9504                 spin_lock_bh(&tp->lock);
9505                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9506                         tg3_writephy(tp, MII_TG3_TEST1,
9507                                      val | MII_TG3_TEST1_CRC_EN);
9508                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9509                 } else
9510                         val = 0;
9511                 spin_unlock_bh(&tp->lock);
9512
9513                 tp->phy_crc_errors += val;
9514
9515                 return tp->phy_crc_errors;
9516         }
9517
9518         return get_stat64(&hw_stats->rx_fcs_errors);
9519 }
9520
9521 #define ESTAT_ADD(member) \
9522         estats->member =        old_estats->member + \
9523                                 get_stat64(&hw_stats->member)
9524
9525 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9526 {
9527         struct tg3_ethtool_stats *estats = &tp->estats;
9528         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9529         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9530
9531         if (!hw_stats)
9532                 return old_estats;
9533
9534         ESTAT_ADD(rx_octets);
9535         ESTAT_ADD(rx_fragments);
9536         ESTAT_ADD(rx_ucast_packets);
9537         ESTAT_ADD(rx_mcast_packets);
9538         ESTAT_ADD(rx_bcast_packets);
9539         ESTAT_ADD(rx_fcs_errors);
9540         ESTAT_ADD(rx_align_errors);
9541         ESTAT_ADD(rx_xon_pause_rcvd);
9542         ESTAT_ADD(rx_xoff_pause_rcvd);
9543         ESTAT_ADD(rx_mac_ctrl_rcvd);
9544         ESTAT_ADD(rx_xoff_entered);
9545         ESTAT_ADD(rx_frame_too_long_errors);
9546         ESTAT_ADD(rx_jabbers);
9547         ESTAT_ADD(rx_undersize_packets);
9548         ESTAT_ADD(rx_in_length_errors);
9549         ESTAT_ADD(rx_out_length_errors);
9550         ESTAT_ADD(rx_64_or_less_octet_packets);
9551         ESTAT_ADD(rx_65_to_127_octet_packets);
9552         ESTAT_ADD(rx_128_to_255_octet_packets);
9553         ESTAT_ADD(rx_256_to_511_octet_packets);
9554         ESTAT_ADD(rx_512_to_1023_octet_packets);
9555         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9556         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9557         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9558         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9559         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9560
9561         ESTAT_ADD(tx_octets);
9562         ESTAT_ADD(tx_collisions);
9563         ESTAT_ADD(tx_xon_sent);
9564         ESTAT_ADD(tx_xoff_sent);
9565         ESTAT_ADD(tx_flow_control);
9566         ESTAT_ADD(tx_mac_errors);
9567         ESTAT_ADD(tx_single_collisions);
9568         ESTAT_ADD(tx_mult_collisions);
9569         ESTAT_ADD(tx_deferred);
9570         ESTAT_ADD(tx_excessive_collisions);
9571         ESTAT_ADD(tx_late_collisions);
9572         ESTAT_ADD(tx_collide_2times);
9573         ESTAT_ADD(tx_collide_3times);
9574         ESTAT_ADD(tx_collide_4times);
9575         ESTAT_ADD(tx_collide_5times);
9576         ESTAT_ADD(tx_collide_6times);
9577         ESTAT_ADD(tx_collide_7times);
9578         ESTAT_ADD(tx_collide_8times);
9579         ESTAT_ADD(tx_collide_9times);
9580         ESTAT_ADD(tx_collide_10times);
9581         ESTAT_ADD(tx_collide_11times);
9582         ESTAT_ADD(tx_collide_12times);
9583         ESTAT_ADD(tx_collide_13times);
9584         ESTAT_ADD(tx_collide_14times);
9585         ESTAT_ADD(tx_collide_15times);
9586         ESTAT_ADD(tx_ucast_packets);
9587         ESTAT_ADD(tx_mcast_packets);
9588         ESTAT_ADD(tx_bcast_packets);
9589         ESTAT_ADD(tx_carrier_sense_errors);
9590         ESTAT_ADD(tx_discards);
9591         ESTAT_ADD(tx_errors);
9592
9593         ESTAT_ADD(dma_writeq_full);
9594         ESTAT_ADD(dma_write_prioq_full);
9595         ESTAT_ADD(rxbds_empty);
9596         ESTAT_ADD(rx_discards);
9597         ESTAT_ADD(rx_errors);
9598         ESTAT_ADD(rx_threshold_hit);
9599
9600         ESTAT_ADD(dma_readq_full);
9601         ESTAT_ADD(dma_read_prioq_full);
9602         ESTAT_ADD(tx_comp_queue_full);
9603
9604         ESTAT_ADD(ring_set_send_prod_index);
9605         ESTAT_ADD(ring_status_update);
9606         ESTAT_ADD(nic_irqs);
9607         ESTAT_ADD(nic_avoided_irqs);
9608         ESTAT_ADD(nic_tx_threshold_hit);
9609
9610         return estats;
9611 }
9612
9613 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9614                                                  struct rtnl_link_stats64 *stats)
9615 {
9616         struct tg3 *tp = netdev_priv(dev);
9617         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9618         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9619
9620         if (!hw_stats)
9621                 return old_stats;
9622
9623         stats->rx_packets = old_stats->rx_packets +
9624                 get_stat64(&hw_stats->rx_ucast_packets) +
9625                 get_stat64(&hw_stats->rx_mcast_packets) +
9626                 get_stat64(&hw_stats->rx_bcast_packets);
9627
9628         stats->tx_packets = old_stats->tx_packets +
9629                 get_stat64(&hw_stats->tx_ucast_packets) +
9630                 get_stat64(&hw_stats->tx_mcast_packets) +
9631                 get_stat64(&hw_stats->tx_bcast_packets);
9632
9633         stats->rx_bytes = old_stats->rx_bytes +
9634                 get_stat64(&hw_stats->rx_octets);
9635         stats->tx_bytes = old_stats->tx_bytes +
9636                 get_stat64(&hw_stats->tx_octets);
9637
9638         stats->rx_errors = old_stats->rx_errors +
9639                 get_stat64(&hw_stats->rx_errors);
9640         stats->tx_errors = old_stats->tx_errors +
9641                 get_stat64(&hw_stats->tx_errors) +
9642                 get_stat64(&hw_stats->tx_mac_errors) +
9643                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9644                 get_stat64(&hw_stats->tx_discards);
9645
9646         stats->multicast = old_stats->multicast +
9647                 get_stat64(&hw_stats->rx_mcast_packets);
9648         stats->collisions = old_stats->collisions +
9649                 get_stat64(&hw_stats->tx_collisions);
9650
9651         stats->rx_length_errors = old_stats->rx_length_errors +
9652                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9653                 get_stat64(&hw_stats->rx_undersize_packets);
9654
9655         stats->rx_over_errors = old_stats->rx_over_errors +
9656                 get_stat64(&hw_stats->rxbds_empty);
9657         stats->rx_frame_errors = old_stats->rx_frame_errors +
9658                 get_stat64(&hw_stats->rx_align_errors);
9659         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9660                 get_stat64(&hw_stats->tx_discards);
9661         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9662                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9663
9664         stats->rx_crc_errors = old_stats->rx_crc_errors +
9665                 calc_crc_errors(tp);
9666
9667         stats->rx_missed_errors = old_stats->rx_missed_errors +
9668                 get_stat64(&hw_stats->rx_discards);
9669
9670         stats->rx_dropped = tp->rx_dropped;
9671
9672         return stats;
9673 }
9674
9675 static inline u32 calc_crc(unsigned char *buf, int len)
9676 {
9677         u32 reg;
9678         u32 tmp;
9679         int j, k;
9680
9681         reg = 0xffffffff;
9682
9683         for (j = 0; j < len; j++) {
9684                 reg ^= buf[j];
9685
9686                 for (k = 0; k < 8; k++) {
9687                         tmp = reg & 0x01;
9688
9689                         reg >>= 1;
9690
9691                         if (tmp)
9692                                 reg ^= 0xedb88320;
9693                 }
9694         }
9695
9696         return ~reg;
9697 }
9698
9699 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9700 {
9701         /* accept or reject all multicast frames */
9702         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9703         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9704         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9705         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9706 }
9707
9708 static void __tg3_set_rx_mode(struct net_device *dev)
9709 {
9710         struct tg3 *tp = netdev_priv(dev);
9711         u32 rx_mode;
9712
9713         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9714                                   RX_MODE_KEEP_VLAN_TAG);
9715
9716 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9717         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9718          * flag clear.
9719          */
9720         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9721                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9722 #endif
9723
9724         if (dev->flags & IFF_PROMISC) {
9725                 /* Promiscuous mode. */
9726                 rx_mode |= RX_MODE_PROMISC;
9727         } else if (dev->flags & IFF_ALLMULTI) {
9728                 /* Accept all multicast. */
9729                 tg3_set_multi(tp, 1);
9730         } else if (netdev_mc_empty(dev)) {
9731                 /* Reject all multicast. */
9732                 tg3_set_multi(tp, 0);
9733         } else {
9734                 /* Accept one or more multicast(s). */
9735                 struct netdev_hw_addr *ha;
9736                 u32 mc_filter[4] = { 0, };
9737                 u32 regidx;
9738                 u32 bit;
9739                 u32 crc;
9740
9741                 netdev_for_each_mc_addr(ha, dev) {
9742                         crc = calc_crc(ha->addr, ETH_ALEN);
9743                         bit = ~crc & 0x7f;
9744                         regidx = (bit & 0x60) >> 5;
9745                         bit &= 0x1f;
9746                         mc_filter[regidx] |= (1 << bit);
9747                 }
9748
9749                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9750                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9751                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9752                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9753         }
9754
9755         if (rx_mode != tp->rx_mode) {
9756                 tp->rx_mode = rx_mode;
9757                 tw32_f(MAC_RX_MODE, rx_mode);
9758                 udelay(10);
9759         }
9760 }
9761
9762 static void tg3_set_rx_mode(struct net_device *dev)
9763 {
9764         struct tg3 *tp = netdev_priv(dev);
9765
9766         if (!netif_running(dev))
9767                 return;
9768
9769         tg3_full_lock(tp, 0);
9770         __tg3_set_rx_mode(dev);
9771         tg3_full_unlock(tp);
9772 }
9773
9774 static int tg3_get_regs_len(struct net_device *dev)
9775 {
9776         return TG3_REG_BLK_SIZE;
9777 }
9778
9779 static void tg3_get_regs(struct net_device *dev,
9780                 struct ethtool_regs *regs, void *_p)
9781 {
9782         struct tg3 *tp = netdev_priv(dev);
9783
9784         regs->version = 0;
9785
9786         memset(_p, 0, TG3_REG_BLK_SIZE);
9787
9788         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9789                 return;
9790
9791         tg3_full_lock(tp, 0);
9792
9793         tg3_dump_legacy_regs(tp, (u32 *)_p);
9794
9795         tg3_full_unlock(tp);
9796 }
9797
9798 static int tg3_get_eeprom_len(struct net_device *dev)
9799 {
9800         struct tg3 *tp = netdev_priv(dev);
9801
9802         return tp->nvram_size;
9803 }
9804
9805 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9806 {
9807         struct tg3 *tp = netdev_priv(dev);
9808         int ret;
9809         u8  *pd;
9810         u32 i, offset, len, b_offset, b_count;
9811         __be32 val;
9812
9813         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9814                 return -EINVAL;
9815
9816         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9817                 return -EAGAIN;
9818
9819         offset = eeprom->offset;
9820         len = eeprom->len;
9821         eeprom->len = 0;
9822
9823         eeprom->magic = TG3_EEPROM_MAGIC;
9824
9825         if (offset & 3) {
9826                 /* adjustments to start on required 4 byte boundary */
9827                 b_offset = offset & 3;
9828                 b_count = 4 - b_offset;
9829                 if (b_count > len) {
9830                         /* i.e. offset=1 len=2 */
9831                         b_count = len;
9832                 }
9833                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9834                 if (ret)
9835                         return ret;
9836                 memcpy(data, ((char *)&val) + b_offset, b_count);
9837                 len -= b_count;
9838                 offset += b_count;
9839                 eeprom->len += b_count;
9840         }
9841
9842         /* read bytes up to the last 4 byte boundary */
9843         pd = &data[eeprom->len];
9844         for (i = 0; i < (len - (len & 3)); i += 4) {
9845                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9846                 if (ret) {
9847                         eeprom->len += i;
9848                         return ret;
9849                 }
9850                 memcpy(pd + i, &val, 4);
9851         }
9852         eeprom->len += i;
9853
9854         if (len & 3) {
9855                 /* read last bytes not ending on 4 byte boundary */
9856                 pd = &data[eeprom->len];
9857                 b_count = len & 3;
9858                 b_offset = offset + len - b_count;
9859                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9860                 if (ret)
9861                         return ret;
9862                 memcpy(pd, &val, b_count);
9863                 eeprom->len += b_count;
9864         }
9865         return 0;
9866 }
9867
9868 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9869
9870 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9871 {
9872         struct tg3 *tp = netdev_priv(dev);
9873         int ret;
9874         u32 offset, len, b_offset, odd_len;
9875         u8 *buf;
9876         __be32 start, end;
9877
9878         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9879                 return -EAGAIN;
9880
9881         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9882             eeprom->magic != TG3_EEPROM_MAGIC)
9883                 return -EINVAL;
9884
9885         offset = eeprom->offset;
9886         len = eeprom->len;
9887
9888         if ((b_offset = (offset & 3))) {
9889                 /* adjustments to start on required 4 byte boundary */
9890                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9891                 if (ret)
9892                         return ret;
9893                 len += b_offset;
9894                 offset &= ~3;
9895                 if (len < 4)
9896                         len = 4;
9897         }
9898
9899         odd_len = 0;
9900         if (len & 3) {
9901                 /* adjustments to end on required 4 byte boundary */
9902                 odd_len = 1;
9903                 len = (len + 3) & ~3;
9904                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9905                 if (ret)
9906                         return ret;
9907         }
9908
9909         buf = data;
9910         if (b_offset || odd_len) {
9911                 buf = kmalloc(len, GFP_KERNEL);
9912                 if (!buf)
9913                         return -ENOMEM;
9914                 if (b_offset)
9915                         memcpy(buf, &start, 4);
9916                 if (odd_len)
9917                         memcpy(buf+len-4, &end, 4);
9918                 memcpy(buf + b_offset, data, eeprom->len);
9919         }
9920
9921         ret = tg3_nvram_write_block(tp, offset, len, buf);
9922
9923         if (buf != data)
9924                 kfree(buf);
9925
9926         return ret;
9927 }
9928
9929 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9930 {
9931         struct tg3 *tp = netdev_priv(dev);
9932
9933         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9934                 struct phy_device *phydev;
9935                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9936                         return -EAGAIN;
9937                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9938                 return phy_ethtool_gset(phydev, cmd);
9939         }
9940
9941         cmd->supported = (SUPPORTED_Autoneg);
9942
9943         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9944                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9945                                    SUPPORTED_1000baseT_Full);
9946
9947         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9948                 cmd->supported |= (SUPPORTED_100baseT_Half |
9949                                   SUPPORTED_100baseT_Full |
9950                                   SUPPORTED_10baseT_Half |
9951                                   SUPPORTED_10baseT_Full |
9952                                   SUPPORTED_TP);
9953                 cmd->port = PORT_TP;
9954         } else {
9955                 cmd->supported |= SUPPORTED_FIBRE;
9956                 cmd->port = PORT_FIBRE;
9957         }
9958
9959         cmd->advertising = tp->link_config.advertising;
9960         if (netif_running(dev)) {
9961                 cmd->speed = tp->link_config.active_speed;
9962                 cmd->duplex = tp->link_config.active_duplex;
9963         } else {
9964                 cmd->speed = SPEED_INVALID;
9965                 cmd->duplex = DUPLEX_INVALID;
9966         }
9967         cmd->phy_address = tp->phy_addr;
9968         cmd->transceiver = XCVR_INTERNAL;
9969         cmd->autoneg = tp->link_config.autoneg;
9970         cmd->maxtxpkt = 0;
9971         cmd->maxrxpkt = 0;
9972         return 0;
9973 }
9974
9975 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9976 {
9977         struct tg3 *tp = netdev_priv(dev);
9978
9979         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9980                 struct phy_device *phydev;
9981                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9982                         return -EAGAIN;
9983                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9984                 return phy_ethtool_sset(phydev, cmd);
9985         }
9986
9987         if (cmd->autoneg != AUTONEG_ENABLE &&
9988             cmd->autoneg != AUTONEG_DISABLE)
9989                 return -EINVAL;
9990
9991         if (cmd->autoneg == AUTONEG_DISABLE &&
9992             cmd->duplex != DUPLEX_FULL &&
9993             cmd->duplex != DUPLEX_HALF)
9994                 return -EINVAL;
9995
9996         if (cmd->autoneg == AUTONEG_ENABLE) {
9997                 u32 mask = ADVERTISED_Autoneg |
9998                            ADVERTISED_Pause |
9999                            ADVERTISED_Asym_Pause;
10000
10001                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10002                         mask |= ADVERTISED_1000baseT_Half |
10003                                 ADVERTISED_1000baseT_Full;
10004
10005                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10006                         mask |= ADVERTISED_100baseT_Half |
10007                                 ADVERTISED_100baseT_Full |
10008                                 ADVERTISED_10baseT_Half |
10009                                 ADVERTISED_10baseT_Full |
10010                                 ADVERTISED_TP;
10011                 else
10012                         mask |= ADVERTISED_FIBRE;
10013
10014                 if (cmd->advertising & ~mask)
10015                         return -EINVAL;
10016
10017                 mask &= (ADVERTISED_1000baseT_Half |
10018                          ADVERTISED_1000baseT_Full |
10019                          ADVERTISED_100baseT_Half |
10020                          ADVERTISED_100baseT_Full |
10021                          ADVERTISED_10baseT_Half |
10022                          ADVERTISED_10baseT_Full);
10023
10024                 cmd->advertising &= mask;
10025         } else {
10026                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10027                         if (cmd->speed != SPEED_1000)
10028                                 return -EINVAL;
10029
10030                         if (cmd->duplex != DUPLEX_FULL)
10031                                 return -EINVAL;
10032                 } else {
10033                         if (cmd->speed != SPEED_100 &&
10034                             cmd->speed != SPEED_10)
10035                                 return -EINVAL;
10036                 }
10037         }
10038
10039         tg3_full_lock(tp, 0);
10040
10041         tp->link_config.autoneg = cmd->autoneg;
10042         if (cmd->autoneg == AUTONEG_ENABLE) {
10043                 tp->link_config.advertising = (cmd->advertising |
10044                                               ADVERTISED_Autoneg);
10045                 tp->link_config.speed = SPEED_INVALID;
10046                 tp->link_config.duplex = DUPLEX_INVALID;
10047         } else {
10048                 tp->link_config.advertising = 0;
10049                 tp->link_config.speed = cmd->speed;
10050                 tp->link_config.duplex = cmd->duplex;
10051         }
10052
10053         tp->link_config.orig_speed = tp->link_config.speed;
10054         tp->link_config.orig_duplex = tp->link_config.duplex;
10055         tp->link_config.orig_autoneg = tp->link_config.autoneg;
10056
10057         if (netif_running(dev))
10058                 tg3_setup_phy(tp, 1);
10059
10060         tg3_full_unlock(tp);
10061
10062         return 0;
10063 }
10064
10065 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10066 {
10067         struct tg3 *tp = netdev_priv(dev);
10068
10069         strcpy(info->driver, DRV_MODULE_NAME);
10070         strcpy(info->version, DRV_MODULE_VERSION);
10071         strcpy(info->fw_version, tp->fw_ver);
10072         strcpy(info->bus_info, pci_name(tp->pdev));
10073 }
10074
10075 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10076 {
10077         struct tg3 *tp = netdev_priv(dev);
10078
10079         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
10080             device_can_wakeup(&tp->pdev->dev))
10081                 wol->supported = WAKE_MAGIC;
10082         else
10083                 wol->supported = 0;
10084         wol->wolopts = 0;
10085         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
10086             device_can_wakeup(&tp->pdev->dev))
10087                 wol->wolopts = WAKE_MAGIC;
10088         memset(&wol->sopass, 0, sizeof(wol->sopass));
10089 }
10090
10091 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10092 {
10093         struct tg3 *tp = netdev_priv(dev);
10094         struct device *dp = &tp->pdev->dev;
10095
10096         if (wol->wolopts & ~WAKE_MAGIC)
10097                 return -EINVAL;
10098         if ((wol->wolopts & WAKE_MAGIC) &&
10099             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
10100                 return -EINVAL;
10101
10102         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10103
10104         spin_lock_bh(&tp->lock);
10105         if (device_may_wakeup(dp))
10106                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10107         else
10108                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10109         spin_unlock_bh(&tp->lock);
10110
10111
10112         return 0;
10113 }
10114
10115 static u32 tg3_get_msglevel(struct net_device *dev)
10116 {
10117         struct tg3 *tp = netdev_priv(dev);
10118         return tp->msg_enable;
10119 }
10120
10121 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10122 {
10123         struct tg3 *tp = netdev_priv(dev);
10124         tp->msg_enable = value;
10125 }
10126
10127 static int tg3_nway_reset(struct net_device *dev)
10128 {
10129         struct tg3 *tp = netdev_priv(dev);
10130         int r;
10131
10132         if (!netif_running(dev))
10133                 return -EAGAIN;
10134
10135         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10136                 return -EINVAL;
10137
10138         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10139                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10140                         return -EAGAIN;
10141                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10142         } else {
10143                 u32 bmcr;
10144
10145                 spin_lock_bh(&tp->lock);
10146                 r = -EINVAL;
10147                 tg3_readphy(tp, MII_BMCR, &bmcr);
10148                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10149                     ((bmcr & BMCR_ANENABLE) ||
10150                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10151                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10152                                                    BMCR_ANENABLE);
10153                         r = 0;
10154                 }
10155                 spin_unlock_bh(&tp->lock);
10156         }
10157
10158         return r;
10159 }
10160
10161 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10162 {
10163         struct tg3 *tp = netdev_priv(dev);
10164
10165         ering->rx_max_pending = tp->rx_std_ring_mask;
10166         ering->rx_mini_max_pending = 0;
10167         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10168                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10169         else
10170                 ering->rx_jumbo_max_pending = 0;
10171
10172         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10173
10174         ering->rx_pending = tp->rx_pending;
10175         ering->rx_mini_pending = 0;
10176         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10177                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10178         else
10179                 ering->rx_jumbo_pending = 0;
10180
10181         ering->tx_pending = tp->napi[0].tx_pending;
10182 }
10183
10184 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10185 {
10186         struct tg3 *tp = netdev_priv(dev);
10187         int i, irq_sync = 0, err = 0;
10188
10189         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10190             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10191             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10192             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10193             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10194              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10195                 return -EINVAL;
10196
10197         if (netif_running(dev)) {
10198                 tg3_phy_stop(tp);
10199                 tg3_netif_stop(tp);
10200                 irq_sync = 1;
10201         }
10202
10203         tg3_full_lock(tp, irq_sync);
10204
10205         tp->rx_pending = ering->rx_pending;
10206
10207         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10208             tp->rx_pending > 63)
10209                 tp->rx_pending = 63;
10210         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10211
10212         for (i = 0; i < tp->irq_max; i++)
10213                 tp->napi[i].tx_pending = ering->tx_pending;
10214
10215         if (netif_running(dev)) {
10216                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10217                 err = tg3_restart_hw(tp, 1);
10218                 if (!err)
10219                         tg3_netif_start(tp);
10220         }
10221
10222         tg3_full_unlock(tp);
10223
10224         if (irq_sync && !err)
10225                 tg3_phy_start(tp);
10226
10227         return err;
10228 }
10229
10230 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10231 {
10232         struct tg3 *tp = netdev_priv(dev);
10233
10234         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10235
10236         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10237                 epause->rx_pause = 1;
10238         else
10239                 epause->rx_pause = 0;
10240
10241         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10242                 epause->tx_pause = 1;
10243         else
10244                 epause->tx_pause = 0;
10245 }
10246
10247 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10248 {
10249         struct tg3 *tp = netdev_priv(dev);
10250         int err = 0;
10251
10252         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10253                 u32 newadv;
10254                 struct phy_device *phydev;
10255
10256                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10257
10258                 if (!(phydev->supported & SUPPORTED_Pause) ||
10259                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10260                      (epause->rx_pause != epause->tx_pause)))
10261                         return -EINVAL;
10262
10263                 tp->link_config.flowctrl = 0;
10264                 if (epause->rx_pause) {
10265                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10266
10267                         if (epause->tx_pause) {
10268                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10269                                 newadv = ADVERTISED_Pause;
10270                         } else
10271                                 newadv = ADVERTISED_Pause |
10272                                          ADVERTISED_Asym_Pause;
10273                 } else if (epause->tx_pause) {
10274                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10275                         newadv = ADVERTISED_Asym_Pause;
10276                 } else
10277                         newadv = 0;
10278
10279                 if (epause->autoneg)
10280                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10281                 else
10282                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10283
10284                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10285                         u32 oldadv = phydev->advertising &
10286                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10287                         if (oldadv != newadv) {
10288                                 phydev->advertising &=
10289                                         ~(ADVERTISED_Pause |
10290                                           ADVERTISED_Asym_Pause);
10291                                 phydev->advertising |= newadv;
10292                                 if (phydev->autoneg) {
10293                                         /*
10294                                          * Always renegotiate the link to
10295                                          * inform our link partner of our
10296                                          * flow control settings, even if the
10297                                          * flow control is forced.  Let
10298                                          * tg3_adjust_link() do the final
10299                                          * flow control setup.
10300                                          */
10301                                         return phy_start_aneg(phydev);
10302                                 }
10303                         }
10304
10305                         if (!epause->autoneg)
10306                                 tg3_setup_flow_control(tp, 0, 0);
10307                 } else {
10308                         tp->link_config.orig_advertising &=
10309                                         ~(ADVERTISED_Pause |
10310                                           ADVERTISED_Asym_Pause);
10311                         tp->link_config.orig_advertising |= newadv;
10312                 }
10313         } else {
10314                 int irq_sync = 0;
10315
10316                 if (netif_running(dev)) {
10317                         tg3_netif_stop(tp);
10318                         irq_sync = 1;
10319                 }
10320
10321                 tg3_full_lock(tp, irq_sync);
10322
10323                 if (epause->autoneg)
10324                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10325                 else
10326                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10327                 if (epause->rx_pause)
10328                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10329                 else
10330                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10331                 if (epause->tx_pause)
10332                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10333                 else
10334                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10335
10336                 if (netif_running(dev)) {
10337                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10338                         err = tg3_restart_hw(tp, 1);
10339                         if (!err)
10340                                 tg3_netif_start(tp);
10341                 }
10342
10343                 tg3_full_unlock(tp);
10344         }
10345
10346         return err;
10347 }
10348
10349 static int tg3_get_sset_count(struct net_device *dev, int sset)
10350 {
10351         switch (sset) {
10352         case ETH_SS_TEST:
10353                 return TG3_NUM_TEST;
10354         case ETH_SS_STATS:
10355                 return TG3_NUM_STATS;
10356         default:
10357                 return -EOPNOTSUPP;
10358         }
10359 }
10360
10361 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10362 {
10363         switch (stringset) {
10364         case ETH_SS_STATS:
10365                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10366                 break;
10367         case ETH_SS_TEST:
10368                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10369                 break;
10370         default:
10371                 WARN_ON(1);     /* we need a WARN() */
10372                 break;
10373         }
10374 }
10375
10376 static int tg3_set_phys_id(struct net_device *dev,
10377                             enum ethtool_phys_id_state state)
10378 {
10379         struct tg3 *tp = netdev_priv(dev);
10380
10381         if (!netif_running(tp->dev))
10382                 return -EAGAIN;
10383
10384         switch (state) {
10385         case ETHTOOL_ID_ACTIVE:
10386                 return -EINVAL;
10387
10388         case ETHTOOL_ID_ON:
10389                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10390                      LED_CTRL_1000MBPS_ON |
10391                      LED_CTRL_100MBPS_ON |
10392                      LED_CTRL_10MBPS_ON |
10393                      LED_CTRL_TRAFFIC_OVERRIDE |
10394                      LED_CTRL_TRAFFIC_BLINK |
10395                      LED_CTRL_TRAFFIC_LED);
10396                 break;
10397
10398         case ETHTOOL_ID_OFF:
10399                 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10400                      LED_CTRL_TRAFFIC_OVERRIDE);
10401                 break;
10402
10403         case ETHTOOL_ID_INACTIVE:
10404                 tw32(MAC_LED_CTRL, tp->led_ctrl);
10405                 break;
10406         }
10407
10408         return 0;
10409 }
10410
10411 static void tg3_get_ethtool_stats(struct net_device *dev,
10412                                    struct ethtool_stats *estats, u64 *tmp_stats)
10413 {
10414         struct tg3 *tp = netdev_priv(dev);
10415         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10416 }
10417
10418 #define NVRAM_TEST_SIZE 0x100
10419 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10420 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10421 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10422 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10423 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10424
10425 static int tg3_test_nvram(struct tg3 *tp)
10426 {
10427         u32 csum, magic;
10428         __be32 *buf;
10429         int i, j, k, err = 0, size;
10430
10431         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10432                 return 0;
10433
10434         if (tg3_nvram_read(tp, 0, &magic) != 0)
10435                 return -EIO;
10436
10437         if (magic == TG3_EEPROM_MAGIC)
10438                 size = NVRAM_TEST_SIZE;
10439         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10440                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10441                     TG3_EEPROM_SB_FORMAT_1) {
10442                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10443                         case TG3_EEPROM_SB_REVISION_0:
10444                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10445                                 break;
10446                         case TG3_EEPROM_SB_REVISION_2:
10447                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10448                                 break;
10449                         case TG3_EEPROM_SB_REVISION_3:
10450                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10451                                 break;
10452                         default:
10453                                 return 0;
10454                         }
10455                 } else
10456                         return 0;
10457         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10458                 size = NVRAM_SELFBOOT_HW_SIZE;
10459         else
10460                 return -EIO;
10461
10462         buf = kmalloc(size, GFP_KERNEL);
10463         if (buf == NULL)
10464                 return -ENOMEM;
10465
10466         err = -EIO;
10467         for (i = 0, j = 0; i < size; i += 4, j++) {
10468                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10469                 if (err)
10470                         break;
10471         }
10472         if (i < size)
10473                 goto out;
10474
10475         /* Selfboot format */
10476         magic = be32_to_cpu(buf[0]);
10477         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10478             TG3_EEPROM_MAGIC_FW) {
10479                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10480
10481                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10482                     TG3_EEPROM_SB_REVISION_2) {
10483                         /* For rev 2, the csum doesn't include the MBA. */
10484                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10485                                 csum8 += buf8[i];
10486                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10487                                 csum8 += buf8[i];
10488                 } else {
10489                         for (i = 0; i < size; i++)
10490                                 csum8 += buf8[i];
10491                 }
10492
10493                 if (csum8 == 0) {
10494                         err = 0;
10495                         goto out;
10496                 }
10497
10498                 err = -EIO;
10499                 goto out;
10500         }
10501
10502         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10503             TG3_EEPROM_MAGIC_HW) {
10504                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10505                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10506                 u8 *buf8 = (u8 *) buf;
10507
10508                 /* Separate the parity bits and the data bytes.  */
10509                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10510                         if ((i == 0) || (i == 8)) {
10511                                 int l;
10512                                 u8 msk;
10513
10514                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10515                                         parity[k++] = buf8[i] & msk;
10516                                 i++;
10517                         } else if (i == 16) {
10518                                 int l;
10519                                 u8 msk;
10520
10521                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10522                                         parity[k++] = buf8[i] & msk;
10523                                 i++;
10524
10525                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10526                                         parity[k++] = buf8[i] & msk;
10527                                 i++;
10528                         }
10529                         data[j++] = buf8[i];
10530                 }
10531
10532                 err = -EIO;
10533                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10534                         u8 hw8 = hweight8(data[i]);
10535
10536                         if ((hw8 & 0x1) && parity[i])
10537                                 goto out;
10538                         else if (!(hw8 & 0x1) && !parity[i])
10539                                 goto out;
10540                 }
10541                 err = 0;
10542                 goto out;
10543         }
10544
10545         err = -EIO;
10546
10547         /* Bootstrap checksum at offset 0x10 */
10548         csum = calc_crc((unsigned char *) buf, 0x10);
10549         if (csum != le32_to_cpu(buf[0x10/4]))
10550                 goto out;
10551
10552         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10553         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10554         if (csum != le32_to_cpu(buf[0xfc/4]))
10555                 goto out;
10556
10557         for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
10558                 /* The data is in little-endian format in NVRAM.
10559                  * Use the big-endian read routines to preserve
10560                  * the byte order as it exists in NVRAM.
10561                  */
10562                 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
10563                         goto out;
10564         }
10565
10566         i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10567                              PCI_VPD_LRDT_RO_DATA);
10568         if (i > 0) {
10569                 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10570                 if (j < 0)
10571                         goto out;
10572
10573                 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10574                         goto out;
10575
10576                 i += PCI_VPD_LRDT_TAG_SIZE;
10577                 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10578                                               PCI_VPD_RO_KEYWORD_CHKSUM);
10579                 if (j > 0) {
10580                         u8 csum8 = 0;
10581
10582                         j += PCI_VPD_INFO_FLD_HDR_SIZE;
10583
10584                         for (i = 0; i <= j; i++)
10585                                 csum8 += ((u8 *)buf)[i];
10586
10587                         if (csum8)
10588                                 goto out;
10589                 }
10590         }
10591
10592         err = 0;
10593
10594 out:
10595         kfree(buf);
10596         return err;
10597 }
10598
10599 #define TG3_SERDES_TIMEOUT_SEC  2
10600 #define TG3_COPPER_TIMEOUT_SEC  6
10601
10602 static int tg3_test_link(struct tg3 *tp)
10603 {
10604         int i, max;
10605
10606         if (!netif_running(tp->dev))
10607                 return -ENODEV;
10608
10609         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10610                 max = TG3_SERDES_TIMEOUT_SEC;
10611         else
10612                 max = TG3_COPPER_TIMEOUT_SEC;
10613
10614         for (i = 0; i < max; i++) {
10615                 if (netif_carrier_ok(tp->dev))
10616                         return 0;
10617
10618                 if (msleep_interruptible(1000))
10619                         break;
10620         }
10621
10622         return -EIO;
10623 }
10624
10625 /* Only test the commonly used registers */
10626 static int tg3_test_registers(struct tg3 *tp)
10627 {
10628         int i, is_5705, is_5750;
10629         u32 offset, read_mask, write_mask, val, save_val, read_val;
10630         static struct {
10631                 u16 offset;
10632                 u16 flags;
10633 #define TG3_FL_5705     0x1
10634 #define TG3_FL_NOT_5705 0x2
10635 #define TG3_FL_NOT_5788 0x4
10636 #define TG3_FL_NOT_5750 0x8
10637                 u32 read_mask;
10638                 u32 write_mask;
10639         } reg_tbl[] = {
10640                 /* MAC Control Registers */
10641                 { MAC_MODE, TG3_FL_NOT_5705,
10642                         0x00000000, 0x00ef6f8c },
10643                 { MAC_MODE, TG3_FL_5705,
10644                         0x00000000, 0x01ef6b8c },
10645                 { MAC_STATUS, TG3_FL_NOT_5705,
10646                         0x03800107, 0x00000000 },
10647                 { MAC_STATUS, TG3_FL_5705,
10648                         0x03800100, 0x00000000 },
10649                 { MAC_ADDR_0_HIGH, 0x0000,
10650                         0x00000000, 0x0000ffff },
10651                 { MAC_ADDR_0_LOW, 0x0000,
10652                         0x00000000, 0xffffffff },
10653                 { MAC_RX_MTU_SIZE, 0x0000,
10654                         0x00000000, 0x0000ffff },
10655                 { MAC_TX_MODE, 0x0000,
10656                         0x00000000, 0x00000070 },
10657                 { MAC_TX_LENGTHS, 0x0000,
10658                         0x00000000, 0x00003fff },
10659                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10660                         0x00000000, 0x000007fc },
10661                 { MAC_RX_MODE, TG3_FL_5705,
10662                         0x00000000, 0x000007dc },
10663                 { MAC_HASH_REG_0, 0x0000,
10664                         0x00000000, 0xffffffff },
10665                 { MAC_HASH_REG_1, 0x0000,
10666                         0x00000000, 0xffffffff },
10667                 { MAC_HASH_REG_2, 0x0000,
10668                         0x00000000, 0xffffffff },
10669                 { MAC_HASH_REG_3, 0x0000,
10670                         0x00000000, 0xffffffff },
10671
10672                 /* Receive Data and Receive BD Initiator Control Registers. */
10673                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10674                         0x00000000, 0xffffffff },
10675                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10676                         0x00000000, 0xffffffff },
10677                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10678                         0x00000000, 0x00000003 },
10679                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10680                         0x00000000, 0xffffffff },
10681                 { RCVDBDI_STD_BD+0, 0x0000,
10682                         0x00000000, 0xffffffff },
10683                 { RCVDBDI_STD_BD+4, 0x0000,
10684                         0x00000000, 0xffffffff },
10685                 { RCVDBDI_STD_BD+8, 0x0000,
10686                         0x00000000, 0xffff0002 },
10687                 { RCVDBDI_STD_BD+0xc, 0x0000,
10688                         0x00000000, 0xffffffff },
10689
10690                 /* Receive BD Initiator Control Registers. */
10691                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10692                         0x00000000, 0xffffffff },
10693                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10694                         0x00000000, 0x000003ff },
10695                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10696                         0x00000000, 0xffffffff },
10697
10698                 /* Host Coalescing Control Registers. */
10699                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10700                         0x00000000, 0x00000004 },
10701                 { HOSTCC_MODE, TG3_FL_5705,
10702                         0x00000000, 0x000000f6 },
10703                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10704                         0x00000000, 0xffffffff },
10705                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10706                         0x00000000, 0x000003ff },
10707                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10708                         0x00000000, 0xffffffff },
10709                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10710                         0x00000000, 0x000003ff },
10711                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10712                         0x00000000, 0xffffffff },
10713                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10714                         0x00000000, 0x000000ff },
10715                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10716                         0x00000000, 0xffffffff },
10717                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10718                         0x00000000, 0x000000ff },
10719                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10720                         0x00000000, 0xffffffff },
10721                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10722                         0x00000000, 0xffffffff },
10723                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10724                         0x00000000, 0xffffffff },
10725                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10726                         0x00000000, 0x000000ff },
10727                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10728                         0x00000000, 0xffffffff },
10729                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10730                         0x00000000, 0x000000ff },
10731                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10732                         0x00000000, 0xffffffff },
10733                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10734                         0x00000000, 0xffffffff },
10735                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10736                         0x00000000, 0xffffffff },
10737                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10738                         0x00000000, 0xffffffff },
10739                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10740                         0x00000000, 0xffffffff },
10741                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10742                         0xffffffff, 0x00000000 },
10743                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10744                         0xffffffff, 0x00000000 },
10745
10746                 /* Buffer Manager Control Registers. */
10747                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10748                         0x00000000, 0x007fff80 },
10749                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10750                         0x00000000, 0x007fffff },
10751                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10752                         0x00000000, 0x0000003f },
10753                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10754                         0x00000000, 0x000001ff },
10755                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10756                         0x00000000, 0x000001ff },
10757                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10758                         0xffffffff, 0x00000000 },
10759                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10760                         0xffffffff, 0x00000000 },
10761
10762                 /* Mailbox Registers */
10763                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10764                         0x00000000, 0x000001ff },
10765                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10766                         0x00000000, 0x000001ff },
10767                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10768                         0x00000000, 0x000007ff },
10769                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10770                         0x00000000, 0x000001ff },
10771
10772                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10773         };
10774
10775         is_5705 = is_5750 = 0;
10776         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10777                 is_5705 = 1;
10778                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10779                         is_5750 = 1;
10780         }
10781
10782         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10783                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10784                         continue;
10785
10786                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10787                         continue;
10788
10789                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10790                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10791                         continue;
10792
10793                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10794                         continue;
10795
10796                 offset = (u32) reg_tbl[i].offset;
10797                 read_mask = reg_tbl[i].read_mask;
10798                 write_mask = reg_tbl[i].write_mask;
10799
10800                 /* Save the original register content */
10801                 save_val = tr32(offset);
10802
10803                 /* Determine the read-only value. */
10804                 read_val = save_val & read_mask;
10805
10806                 /* Write zero to the register, then make sure the read-only bits
10807                  * are not changed and the read/write bits are all zeros.
10808                  */
10809                 tw32(offset, 0);
10810
10811                 val = tr32(offset);
10812
10813                 /* Test the read-only and read/write bits. */
10814                 if (((val & read_mask) != read_val) || (val & write_mask))
10815                         goto out;
10816
10817                 /* Write ones to all the bits defined by RdMask and WrMask, then
10818                  * make sure the read-only bits are not changed and the
10819                  * read/write bits are all ones.
10820                  */
10821                 tw32(offset, read_mask | write_mask);
10822
10823                 val = tr32(offset);
10824
10825                 /* Test the read-only bits. */
10826                 if ((val & read_mask) != read_val)
10827                         goto out;
10828
10829                 /* Test the read/write bits. */
10830                 if ((val & write_mask) != write_mask)
10831                         goto out;
10832
10833                 tw32(offset, save_val);
10834         }
10835
10836         return 0;
10837
10838 out:
10839         if (netif_msg_hw(tp))
10840                 netdev_err(tp->dev,
10841                            "Register test failed at offset %x\n", offset);
10842         tw32(offset, save_val);
10843         return -EIO;
10844 }
10845
10846 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10847 {
10848         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10849         int i;
10850         u32 j;
10851
10852         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10853                 for (j = 0; j < len; j += 4) {
10854                         u32 val;
10855
10856                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10857                         tg3_read_mem(tp, offset + j, &val);
10858                         if (val != test_pattern[i])
10859                                 return -EIO;
10860                 }
10861         }
10862         return 0;
10863 }
10864
10865 static int tg3_test_memory(struct tg3 *tp)
10866 {
10867         static struct mem_entry {
10868                 u32 offset;
10869                 u32 len;
10870         } mem_tbl_570x[] = {
10871                 { 0x00000000, 0x00b50},
10872                 { 0x00002000, 0x1c000},
10873                 { 0xffffffff, 0x00000}
10874         }, mem_tbl_5705[] = {
10875                 { 0x00000100, 0x0000c},
10876                 { 0x00000200, 0x00008},
10877                 { 0x00004000, 0x00800},
10878                 { 0x00006000, 0x01000},
10879                 { 0x00008000, 0x02000},
10880                 { 0x00010000, 0x0e000},
10881                 { 0xffffffff, 0x00000}
10882         }, mem_tbl_5755[] = {
10883                 { 0x00000200, 0x00008},
10884                 { 0x00004000, 0x00800},
10885                 { 0x00006000, 0x00800},
10886                 { 0x00008000, 0x02000},
10887                 { 0x00010000, 0x0c000},
10888                 { 0xffffffff, 0x00000}
10889         }, mem_tbl_5906[] = {
10890                 { 0x00000200, 0x00008},
10891                 { 0x00004000, 0x00400},
10892                 { 0x00006000, 0x00400},
10893                 { 0x00008000, 0x01000},
10894                 { 0x00010000, 0x01000},
10895                 { 0xffffffff, 0x00000}
10896         }, mem_tbl_5717[] = {
10897                 { 0x00000200, 0x00008},
10898                 { 0x00010000, 0x0a000},
10899                 { 0x00020000, 0x13c00},
10900                 { 0xffffffff, 0x00000}
10901         }, mem_tbl_57765[] = {
10902                 { 0x00000200, 0x00008},
10903                 { 0x00004000, 0x00800},
10904                 { 0x00006000, 0x09800},
10905                 { 0x00010000, 0x0a000},
10906                 { 0xffffffff, 0x00000}
10907         };
10908         struct mem_entry *mem_tbl;
10909         int err = 0;
10910         int i;
10911
10912         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
10913                 mem_tbl = mem_tbl_5717;
10914         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10915                 mem_tbl = mem_tbl_57765;
10916         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10917                 mem_tbl = mem_tbl_5755;
10918         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10919                 mem_tbl = mem_tbl_5906;
10920         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10921                 mem_tbl = mem_tbl_5705;
10922         else
10923                 mem_tbl = mem_tbl_570x;
10924
10925         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10926                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10927                 if (err)
10928                         break;
10929         }
10930
10931         return err;
10932 }
10933
10934 #define TG3_MAC_LOOPBACK        0
10935 #define TG3_PHY_LOOPBACK        1
10936
10937 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10938 {
10939         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10940         u32 desc_idx, coal_now;
10941         struct sk_buff *skb, *rx_skb;
10942         u8 *tx_data;
10943         dma_addr_t map;
10944         int num_pkts, tx_len, rx_len, i, err;
10945         struct tg3_rx_buffer_desc *desc;
10946         struct tg3_napi *tnapi, *rnapi;
10947         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10948
10949         tnapi = &tp->napi[0];
10950         rnapi = &tp->napi[0];
10951         if (tp->irq_cnt > 1) {
10952                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10953                         rnapi = &tp->napi[1];
10954                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10955                         tnapi = &tp->napi[1];
10956         }
10957         coal_now = tnapi->coal_now | rnapi->coal_now;
10958
10959         if (loopback_mode == TG3_MAC_LOOPBACK) {
10960                 /* HW errata - mac loopback fails in some cases on 5780.
10961                  * Normal traffic and PHY loopback are not affected by
10962                  * errata.  Also, the MAC loopback test is deprecated for
10963                  * all newer ASIC revisions.
10964                  */
10965                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10966                     (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
10967                         return 0;
10968
10969                 mac_mode = tp->mac_mode &
10970                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10971                 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
10972                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10973                         mac_mode |= MAC_MODE_LINK_POLARITY;
10974                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10975                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10976                 else
10977                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10978                 tw32(MAC_MODE, mac_mode);
10979         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10980                 u32 val;
10981
10982                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10983                         tg3_phy_fet_toggle_apd(tp, false);
10984                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10985                 } else
10986                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10987
10988                 tg3_phy_toggle_automdix(tp, 0);
10989
10990                 tg3_writephy(tp, MII_BMCR, val);
10991                 udelay(40);
10992
10993                 mac_mode = tp->mac_mode &
10994                            ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
10995                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10996                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10997                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10998                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10999                         /* The write needs to be flushed for the AC131 */
11000                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11001                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
11002                         mac_mode |= MAC_MODE_PORT_MODE_MII;
11003                 } else
11004                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
11005
11006                 /* reset to prevent losing 1st rx packet intermittently */
11007                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
11008                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
11009                         udelay(10);
11010                         tw32_f(MAC_RX_MODE, tp->rx_mode);
11011                 }
11012                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
11013                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
11014                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
11015                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
11016                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
11017                                 mac_mode |= MAC_MODE_LINK_POLARITY;
11018                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
11019                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
11020                 }
11021                 tw32(MAC_MODE, mac_mode);
11022
11023                 /* Wait for link */
11024                 for (i = 0; i < 100; i++) {
11025                         if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11026                                 break;
11027                         mdelay(1);
11028                 }
11029         } else {
11030                 return -EINVAL;
11031         }
11032
11033         err = -EIO;
11034
11035         tx_len = 1514;
11036         skb = netdev_alloc_skb(tp->dev, tx_len);
11037         if (!skb)
11038                 return -ENOMEM;
11039
11040         tx_data = skb_put(skb, tx_len);
11041         memcpy(tx_data, tp->dev->dev_addr, 6);
11042         memset(tx_data + 6, 0x0, 8);
11043
11044         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
11045
11046         for (i = 14; i < tx_len; i++)
11047                 tx_data[i] = (u8) (i & 0xff);
11048
11049         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11050         if (pci_dma_mapping_error(tp->pdev, map)) {
11051                 dev_kfree_skb(skb);
11052                 return -EIO;
11053         }
11054
11055         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11056                rnapi->coal_now);
11057
11058         udelay(10);
11059
11060         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11061
11062         num_pkts = 0;
11063
11064         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
11065
11066         tnapi->tx_prod++;
11067         num_pkts++;
11068
11069         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11070         tr32_mailbox(tnapi->prodmbox);
11071
11072         udelay(10);
11073
11074         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
11075         for (i = 0; i < 35; i++) {
11076                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11077                        coal_now);
11078
11079                 udelay(10);
11080
11081                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11082                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11083                 if ((tx_idx == tnapi->tx_prod) &&
11084                     (rx_idx == (rx_start_idx + num_pkts)))
11085                         break;
11086         }
11087
11088         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11089         dev_kfree_skb(skb);
11090
11091         if (tx_idx != tnapi->tx_prod)
11092                 goto out;
11093
11094         if (rx_idx != rx_start_idx + num_pkts)
11095                 goto out;
11096
11097         desc = &rnapi->rx_rcb[rx_start_idx];
11098         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11099         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11100         if (opaque_key != RXD_OPAQUE_RING_STD)
11101                 goto out;
11102
11103         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11104             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11105                 goto out;
11106
11107         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
11108         if (rx_len != tx_len)
11109                 goto out;
11110
11111         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11112
11113         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11114         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11115
11116         for (i = 14; i < tx_len; i++) {
11117                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11118                         goto out;
11119         }
11120         err = 0;
11121
11122         /* tg3_free_rings will unmap and free the rx_skb */
11123 out:
11124         return err;
11125 }
11126
11127 #define TG3_MAC_LOOPBACK_FAILED         1
11128 #define TG3_PHY_LOOPBACK_FAILED         2
11129 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
11130                                          TG3_PHY_LOOPBACK_FAILED)
11131
11132 static int tg3_test_loopback(struct tg3 *tp)
11133 {
11134         int err = 0;
11135         u32 eee_cap, cpmuctrl = 0;
11136
11137         if (!netif_running(tp->dev))
11138                 return TG3_LOOPBACK_FAILED;
11139
11140         eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11141         tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11142
11143         err = tg3_reset_hw(tp, 1);
11144         if (err) {
11145                 err = TG3_LOOPBACK_FAILED;
11146                 goto done;
11147         }
11148
11149         /* Turn off gphy autopowerdown. */
11150         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11151                 tg3_phy_toggle_apd(tp, false);
11152
11153         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11154                 int i;
11155                 u32 status;
11156
11157                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11158
11159                 /* Wait for up to 40 microseconds to acquire lock. */
11160                 for (i = 0; i < 4; i++) {
11161                         status = tr32(TG3_CPMU_MUTEX_GNT);
11162                         if (status == CPMU_MUTEX_GNT_DRIVER)
11163                                 break;
11164                         udelay(10);
11165                 }
11166
11167                 if (status != CPMU_MUTEX_GNT_DRIVER) {
11168                         err = TG3_LOOPBACK_FAILED;
11169                         goto done;
11170                 }
11171
11172                 /* Turn off link-based power management. */
11173                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11174                 tw32(TG3_CPMU_CTRL,
11175                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11176                                   CPMU_CTRL_LINK_AWARE_MODE));
11177         }
11178
11179         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11180                 err |= TG3_MAC_LOOPBACK_FAILED;
11181
11182         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11183                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11184
11185                 /* Release the mutex */
11186                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11187         }
11188
11189         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11190             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11191                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11192                         err |= TG3_PHY_LOOPBACK_FAILED;
11193         }
11194
11195         /* Re-enable gphy autopowerdown. */
11196         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11197                 tg3_phy_toggle_apd(tp, true);
11198
11199 done:
11200         tp->phy_flags |= eee_cap;
11201
11202         return err;
11203 }
11204
11205 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11206                           u64 *data)
11207 {
11208         struct tg3 *tp = netdev_priv(dev);
11209
11210         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11211                 tg3_power_up(tp);
11212
11213         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11214
11215         if (tg3_test_nvram(tp) != 0) {
11216                 etest->flags |= ETH_TEST_FL_FAILED;
11217                 data[0] = 1;
11218         }
11219         if (tg3_test_link(tp) != 0) {
11220                 etest->flags |= ETH_TEST_FL_FAILED;
11221                 data[1] = 1;
11222         }
11223         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11224                 int err, err2 = 0, irq_sync = 0;
11225
11226                 if (netif_running(dev)) {
11227                         tg3_phy_stop(tp);
11228                         tg3_netif_stop(tp);
11229                         irq_sync = 1;
11230                 }
11231
11232                 tg3_full_lock(tp, irq_sync);
11233
11234                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11235                 err = tg3_nvram_lock(tp);
11236                 tg3_halt_cpu(tp, RX_CPU_BASE);
11237                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11238                         tg3_halt_cpu(tp, TX_CPU_BASE);
11239                 if (!err)
11240                         tg3_nvram_unlock(tp);
11241
11242                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11243                         tg3_phy_reset(tp);
11244
11245                 if (tg3_test_registers(tp) != 0) {
11246                         etest->flags |= ETH_TEST_FL_FAILED;
11247                         data[2] = 1;
11248                 }
11249                 if (tg3_test_memory(tp) != 0) {
11250                         etest->flags |= ETH_TEST_FL_FAILED;
11251                         data[3] = 1;
11252                 }
11253                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11254                         etest->flags |= ETH_TEST_FL_FAILED;
11255
11256                 tg3_full_unlock(tp);
11257
11258                 if (tg3_test_interrupt(tp) != 0) {
11259                         etest->flags |= ETH_TEST_FL_FAILED;
11260                         data[5] = 1;
11261                 }
11262
11263                 tg3_full_lock(tp, 0);
11264
11265                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11266                 if (netif_running(dev)) {
11267                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11268                         err2 = tg3_restart_hw(tp, 1);
11269                         if (!err2)
11270                                 tg3_netif_start(tp);
11271                 }
11272
11273                 tg3_full_unlock(tp);
11274
11275                 if (irq_sync && !err2)
11276                         tg3_phy_start(tp);
11277         }
11278         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11279                 tg3_power_down(tp);
11280
11281 }
11282
11283 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11284 {
11285         struct mii_ioctl_data *data = if_mii(ifr);
11286         struct tg3 *tp = netdev_priv(dev);
11287         int err;
11288
11289         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11290                 struct phy_device *phydev;
11291                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11292                         return -EAGAIN;
11293                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11294                 return phy_mii_ioctl(phydev, ifr, cmd);
11295         }
11296
11297         switch (cmd) {
11298         case SIOCGMIIPHY:
11299                 data->phy_id = tp->phy_addr;
11300
11301                 /* fallthru */
11302         case SIOCGMIIREG: {
11303                 u32 mii_regval;
11304
11305                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11306                         break;                  /* We have no PHY */
11307
11308                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11309                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11310                      !netif_running(dev)))
11311                         return -EAGAIN;
11312
11313                 spin_lock_bh(&tp->lock);
11314                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11315                 spin_unlock_bh(&tp->lock);
11316
11317                 data->val_out = mii_regval;
11318
11319                 return err;
11320         }
11321
11322         case SIOCSMIIREG:
11323                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11324                         break;                  /* We have no PHY */
11325
11326                 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
11327                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
11328                      !netif_running(dev)))
11329                         return -EAGAIN;
11330
11331                 spin_lock_bh(&tp->lock);
11332                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11333                 spin_unlock_bh(&tp->lock);
11334
11335                 return err;
11336
11337         default:
11338                 /* do nothing */
11339                 break;
11340         }
11341         return -EOPNOTSUPP;
11342 }
11343
11344 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11345 {
11346         struct tg3 *tp = netdev_priv(dev);
11347
11348         memcpy(ec, &tp->coal, sizeof(*ec));
11349         return 0;
11350 }
11351
11352 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11353 {
11354         struct tg3 *tp = netdev_priv(dev);
11355         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11356         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11357
11358         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11359                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11360                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11361                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11362                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11363         }
11364
11365         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11366             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11367             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11368             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11369             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11370             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11371             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11372             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11373             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11374             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11375                 return -EINVAL;
11376
11377         /* No rx interrupts will be generated if both are zero */
11378         if ((ec->rx_coalesce_usecs == 0) &&
11379             (ec->rx_max_coalesced_frames == 0))
11380                 return -EINVAL;
11381
11382         /* No tx interrupts will be generated if both are zero */
11383         if ((ec->tx_coalesce_usecs == 0) &&
11384             (ec->tx_max_coalesced_frames == 0))
11385                 return -EINVAL;
11386
11387         /* Only copy relevant parameters, ignore all others. */
11388         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11389         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11390         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11391         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11392         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11393         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11394         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11395         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11396         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11397
11398         if (netif_running(dev)) {
11399                 tg3_full_lock(tp, 0);
11400                 __tg3_set_coalesce(tp, &tp->coal);
11401                 tg3_full_unlock(tp);
11402         }
11403         return 0;
11404 }
11405
11406 static const struct ethtool_ops tg3_ethtool_ops = {
11407         .get_settings           = tg3_get_settings,
11408         .set_settings           = tg3_set_settings,
11409         .get_drvinfo            = tg3_get_drvinfo,
11410         .get_regs_len           = tg3_get_regs_len,
11411         .get_regs               = tg3_get_regs,
11412         .get_wol                = tg3_get_wol,
11413         .set_wol                = tg3_set_wol,
11414         .get_msglevel           = tg3_get_msglevel,
11415         .set_msglevel           = tg3_set_msglevel,
11416         .nway_reset             = tg3_nway_reset,
11417         .get_link               = ethtool_op_get_link,
11418         .get_eeprom_len         = tg3_get_eeprom_len,
11419         .get_eeprom             = tg3_get_eeprom,
11420         .set_eeprom             = tg3_set_eeprom,
11421         .get_ringparam          = tg3_get_ringparam,
11422         .set_ringparam          = tg3_set_ringparam,
11423         .get_pauseparam         = tg3_get_pauseparam,
11424         .set_pauseparam         = tg3_set_pauseparam,
11425         .self_test              = tg3_self_test,
11426         .get_strings            = tg3_get_strings,
11427         .set_phys_id            = tg3_set_phys_id,
11428         .get_ethtool_stats      = tg3_get_ethtool_stats,
11429         .get_coalesce           = tg3_get_coalesce,
11430         .set_coalesce           = tg3_set_coalesce,
11431         .get_sset_count         = tg3_get_sset_count,
11432 };
11433
11434 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11435 {
11436         u32 cursize, val, magic;
11437
11438         tp->nvram_size = EEPROM_CHIP_SIZE;
11439
11440         if (tg3_nvram_read(tp, 0, &magic) != 0)
11441                 return;
11442
11443         if ((magic != TG3_EEPROM_MAGIC) &&
11444             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11445             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11446                 return;
11447
11448         /*
11449          * Size the chip by reading offsets at increasing powers of two.
11450          * When we encounter our validation signature, we know the addressing
11451          * has wrapped around, and thus have our chip size.
11452          */
11453         cursize = 0x10;
11454
11455         while (cursize < tp->nvram_size) {
11456                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11457                         return;
11458
11459                 if (val == magic)
11460                         break;
11461
11462                 cursize <<= 1;
11463         }
11464
11465         tp->nvram_size = cursize;
11466 }
11467
11468 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11469 {
11470         u32 val;
11471
11472         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11473             tg3_nvram_read(tp, 0, &val) != 0)
11474                 return;
11475
11476         /* Selfboot format */
11477         if (val != TG3_EEPROM_MAGIC) {
11478                 tg3_get_eeprom_size(tp);
11479                 return;
11480         }
11481
11482         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11483                 if (val != 0) {
11484                         /* This is confusing.  We want to operate on the
11485                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11486                          * call will read from NVRAM and byteswap the data
11487                          * according to the byteswapping settings for all
11488                          * other register accesses.  This ensures the data we
11489                          * want will always reside in the lower 16-bits.
11490                          * However, the data in NVRAM is in LE format, which
11491                          * means the data from the NVRAM read will always be
11492                          * opposite the endianness of the CPU.  The 16-bit
11493                          * byteswap then brings the data to CPU endianness.
11494                          */
11495                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11496                         return;
11497                 }
11498         }
11499         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11500 }
11501
11502 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11503 {
11504         u32 nvcfg1;
11505
11506         nvcfg1 = tr32(NVRAM_CFG1);
11507         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11508                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11509         } else {
11510                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11511                 tw32(NVRAM_CFG1, nvcfg1);
11512         }
11513
11514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11515             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11516                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11517                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11518                         tp->nvram_jedecnum = JEDEC_ATMEL;
11519                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11520                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521                         break;
11522                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11523                         tp->nvram_jedecnum = JEDEC_ATMEL;
11524                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11525                         break;
11526                 case FLASH_VENDOR_ATMEL_EEPROM:
11527                         tp->nvram_jedecnum = JEDEC_ATMEL;
11528                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11529                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11530                         break;
11531                 case FLASH_VENDOR_ST:
11532                         tp->nvram_jedecnum = JEDEC_ST;
11533                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11534                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11535                         break;
11536                 case FLASH_VENDOR_SAIFUN:
11537                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11538                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11539                         break;
11540                 case FLASH_VENDOR_SST_SMALL:
11541                 case FLASH_VENDOR_SST_LARGE:
11542                         tp->nvram_jedecnum = JEDEC_SST;
11543                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11544                         break;
11545                 }
11546         } else {
11547                 tp->nvram_jedecnum = JEDEC_ATMEL;
11548                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11549                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11550         }
11551 }
11552
11553 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11554 {
11555         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11556         case FLASH_5752PAGE_SIZE_256:
11557                 tp->nvram_pagesize = 256;
11558                 break;
11559         case FLASH_5752PAGE_SIZE_512:
11560                 tp->nvram_pagesize = 512;
11561                 break;
11562         case FLASH_5752PAGE_SIZE_1K:
11563                 tp->nvram_pagesize = 1024;
11564                 break;
11565         case FLASH_5752PAGE_SIZE_2K:
11566                 tp->nvram_pagesize = 2048;
11567                 break;
11568         case FLASH_5752PAGE_SIZE_4K:
11569                 tp->nvram_pagesize = 4096;
11570                 break;
11571         case FLASH_5752PAGE_SIZE_264:
11572                 tp->nvram_pagesize = 264;
11573                 break;
11574         case FLASH_5752PAGE_SIZE_528:
11575                 tp->nvram_pagesize = 528;
11576                 break;
11577         }
11578 }
11579
11580 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11581 {
11582         u32 nvcfg1;
11583
11584         nvcfg1 = tr32(NVRAM_CFG1);
11585
11586         /* NVRAM protection for TPM */
11587         if (nvcfg1 & (1 << 27))
11588                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11589
11590         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11591         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11592         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11593                 tp->nvram_jedecnum = JEDEC_ATMEL;
11594                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11595                 break;
11596         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11597                 tp->nvram_jedecnum = JEDEC_ATMEL;
11598                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11599                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11600                 break;
11601         case FLASH_5752VENDOR_ST_M45PE10:
11602         case FLASH_5752VENDOR_ST_M45PE20:
11603         case FLASH_5752VENDOR_ST_M45PE40:
11604                 tp->nvram_jedecnum = JEDEC_ST;
11605                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11606                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11607                 break;
11608         }
11609
11610         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11611                 tg3_nvram_get_pagesize(tp, nvcfg1);
11612         } else {
11613                 /* For eeprom, set pagesize to maximum eeprom size */
11614                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11615
11616                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11617                 tw32(NVRAM_CFG1, nvcfg1);
11618         }
11619 }
11620
11621 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11622 {
11623         u32 nvcfg1, protect = 0;
11624
11625         nvcfg1 = tr32(NVRAM_CFG1);
11626
11627         /* NVRAM protection for TPM */
11628         if (nvcfg1 & (1 << 27)) {
11629                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11630                 protect = 1;
11631         }
11632
11633         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11634         switch (nvcfg1) {
11635         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11636         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11637         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11638         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11639                 tp->nvram_jedecnum = JEDEC_ATMEL;
11640                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11641                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11642                 tp->nvram_pagesize = 264;
11643                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11644                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11645                         tp->nvram_size = (protect ? 0x3e200 :
11646                                           TG3_NVRAM_SIZE_512KB);
11647                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11648                         tp->nvram_size = (protect ? 0x1f200 :
11649                                           TG3_NVRAM_SIZE_256KB);
11650                 else
11651                         tp->nvram_size = (protect ? 0x1f200 :
11652                                           TG3_NVRAM_SIZE_128KB);
11653                 break;
11654         case FLASH_5752VENDOR_ST_M45PE10:
11655         case FLASH_5752VENDOR_ST_M45PE20:
11656         case FLASH_5752VENDOR_ST_M45PE40:
11657                 tp->nvram_jedecnum = JEDEC_ST;
11658                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11659                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11660                 tp->nvram_pagesize = 256;
11661                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11662                         tp->nvram_size = (protect ?
11663                                           TG3_NVRAM_SIZE_64KB :
11664                                           TG3_NVRAM_SIZE_128KB);
11665                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11666                         tp->nvram_size = (protect ?
11667                                           TG3_NVRAM_SIZE_64KB :
11668                                           TG3_NVRAM_SIZE_256KB);
11669                 else
11670                         tp->nvram_size = (protect ?
11671                                           TG3_NVRAM_SIZE_128KB :
11672                                           TG3_NVRAM_SIZE_512KB);
11673                 break;
11674         }
11675 }
11676
11677 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11678 {
11679         u32 nvcfg1;
11680
11681         nvcfg1 = tr32(NVRAM_CFG1);
11682
11683         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11684         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11685         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11686         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11687         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11688                 tp->nvram_jedecnum = JEDEC_ATMEL;
11689                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11690                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11691
11692                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11693                 tw32(NVRAM_CFG1, nvcfg1);
11694                 break;
11695         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11696         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11697         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11698         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11699                 tp->nvram_jedecnum = JEDEC_ATMEL;
11700                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11701                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11702                 tp->nvram_pagesize = 264;
11703                 break;
11704         case FLASH_5752VENDOR_ST_M45PE10:
11705         case FLASH_5752VENDOR_ST_M45PE20:
11706         case FLASH_5752VENDOR_ST_M45PE40:
11707                 tp->nvram_jedecnum = JEDEC_ST;
11708                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11709                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11710                 tp->nvram_pagesize = 256;
11711                 break;
11712         }
11713 }
11714
11715 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11716 {
11717         u32 nvcfg1, protect = 0;
11718
11719         nvcfg1 = tr32(NVRAM_CFG1);
11720
11721         /* NVRAM protection for TPM */
11722         if (nvcfg1 & (1 << 27)) {
11723                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11724                 protect = 1;
11725         }
11726
11727         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11728         switch (nvcfg1) {
11729         case FLASH_5761VENDOR_ATMEL_ADB021D:
11730         case FLASH_5761VENDOR_ATMEL_ADB041D:
11731         case FLASH_5761VENDOR_ATMEL_ADB081D:
11732         case FLASH_5761VENDOR_ATMEL_ADB161D:
11733         case FLASH_5761VENDOR_ATMEL_MDB021D:
11734         case FLASH_5761VENDOR_ATMEL_MDB041D:
11735         case FLASH_5761VENDOR_ATMEL_MDB081D:
11736         case FLASH_5761VENDOR_ATMEL_MDB161D:
11737                 tp->nvram_jedecnum = JEDEC_ATMEL;
11738                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11739                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11740                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11741                 tp->nvram_pagesize = 256;
11742                 break;
11743         case FLASH_5761VENDOR_ST_A_M45PE20:
11744         case FLASH_5761VENDOR_ST_A_M45PE40:
11745         case FLASH_5761VENDOR_ST_A_M45PE80:
11746         case FLASH_5761VENDOR_ST_A_M45PE16:
11747         case FLASH_5761VENDOR_ST_M_M45PE20:
11748         case FLASH_5761VENDOR_ST_M_M45PE40:
11749         case FLASH_5761VENDOR_ST_M_M45PE80:
11750         case FLASH_5761VENDOR_ST_M_M45PE16:
11751                 tp->nvram_jedecnum = JEDEC_ST;
11752                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11753                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11754                 tp->nvram_pagesize = 256;
11755                 break;
11756         }
11757
11758         if (protect) {
11759                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11760         } else {
11761                 switch (nvcfg1) {
11762                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11763                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11764                 case FLASH_5761VENDOR_ST_A_M45PE16:
11765                 case FLASH_5761VENDOR_ST_M_M45PE16:
11766                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11767                         break;
11768                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11769                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11770                 case FLASH_5761VENDOR_ST_A_M45PE80:
11771                 case FLASH_5761VENDOR_ST_M_M45PE80:
11772                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11773                         break;
11774                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11775                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11776                 case FLASH_5761VENDOR_ST_A_M45PE40:
11777                 case FLASH_5761VENDOR_ST_M_M45PE40:
11778                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11779                         break;
11780                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11781                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11782                 case FLASH_5761VENDOR_ST_A_M45PE20:
11783                 case FLASH_5761VENDOR_ST_M_M45PE20:
11784                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11785                         break;
11786                 }
11787         }
11788 }
11789
11790 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11791 {
11792         tp->nvram_jedecnum = JEDEC_ATMEL;
11793         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11794         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11795 }
11796
11797 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11798 {
11799         u32 nvcfg1;
11800
11801         nvcfg1 = tr32(NVRAM_CFG1);
11802
11803         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11804         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11805         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11806                 tp->nvram_jedecnum = JEDEC_ATMEL;
11807                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11808                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11809
11810                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11811                 tw32(NVRAM_CFG1, nvcfg1);
11812                 return;
11813         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11814         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11815         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11816         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11817         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11818         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11819         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11820                 tp->nvram_jedecnum = JEDEC_ATMEL;
11821                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11822                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11823
11824                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11825                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11826                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11827                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11828                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11829                         break;
11830                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11831                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11832                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11833                         break;
11834                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11835                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11836                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11837                         break;
11838                 }
11839                 break;
11840         case FLASH_5752VENDOR_ST_M45PE10:
11841         case FLASH_5752VENDOR_ST_M45PE20:
11842         case FLASH_5752VENDOR_ST_M45PE40:
11843                 tp->nvram_jedecnum = JEDEC_ST;
11844                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11845                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11846
11847                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11848                 case FLASH_5752VENDOR_ST_M45PE10:
11849                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11850                         break;
11851                 case FLASH_5752VENDOR_ST_M45PE20:
11852                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11853                         break;
11854                 case FLASH_5752VENDOR_ST_M45PE40:
11855                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11856                         break;
11857                 }
11858                 break;
11859         default:
11860                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11861                 return;
11862         }
11863
11864         tg3_nvram_get_pagesize(tp, nvcfg1);
11865         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11866                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11867 }
11868
11869
11870 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11871 {
11872         u32 nvcfg1;
11873
11874         nvcfg1 = tr32(NVRAM_CFG1);
11875
11876         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11877         case FLASH_5717VENDOR_ATMEL_EEPROM:
11878         case FLASH_5717VENDOR_MICRO_EEPROM:
11879                 tp->nvram_jedecnum = JEDEC_ATMEL;
11880                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11881                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11882
11883                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11884                 tw32(NVRAM_CFG1, nvcfg1);
11885                 return;
11886         case FLASH_5717VENDOR_ATMEL_MDB011D:
11887         case FLASH_5717VENDOR_ATMEL_ADB011B:
11888         case FLASH_5717VENDOR_ATMEL_ADB011D:
11889         case FLASH_5717VENDOR_ATMEL_MDB021D:
11890         case FLASH_5717VENDOR_ATMEL_ADB021B:
11891         case FLASH_5717VENDOR_ATMEL_ADB021D:
11892         case FLASH_5717VENDOR_ATMEL_45USPT:
11893                 tp->nvram_jedecnum = JEDEC_ATMEL;
11894                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11895                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11896
11897                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11898                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11899                         /* Detect size with tg3_nvram_get_size() */
11900                         break;
11901                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11902                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11903                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11904                         break;
11905                 default:
11906                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11907                         break;
11908                 }
11909                 break;
11910         case FLASH_5717VENDOR_ST_M_M25PE10:
11911         case FLASH_5717VENDOR_ST_A_M25PE10:
11912         case FLASH_5717VENDOR_ST_M_M45PE10:
11913         case FLASH_5717VENDOR_ST_A_M45PE10:
11914         case FLASH_5717VENDOR_ST_M_M25PE20:
11915         case FLASH_5717VENDOR_ST_A_M25PE20:
11916         case FLASH_5717VENDOR_ST_M_M45PE20:
11917         case FLASH_5717VENDOR_ST_A_M45PE20:
11918         case FLASH_5717VENDOR_ST_25USPT:
11919         case FLASH_5717VENDOR_ST_45USPT:
11920                 tp->nvram_jedecnum = JEDEC_ST;
11921                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11922                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11923
11924                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11925                 case FLASH_5717VENDOR_ST_M_M25PE20:
11926                 case FLASH_5717VENDOR_ST_M_M45PE20:
11927                         /* Detect size with tg3_nvram_get_size() */
11928                         break;
11929                 case FLASH_5717VENDOR_ST_A_M25PE20:
11930                 case FLASH_5717VENDOR_ST_A_M45PE20:
11931                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11932                         break;
11933                 default:
11934                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11935                         break;
11936                 }
11937                 break;
11938         default:
11939                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11940                 return;
11941         }
11942
11943         tg3_nvram_get_pagesize(tp, nvcfg1);
11944         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11945                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11946 }
11947
11948 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
11949 {
11950         u32 nvcfg1, nvmpinstrp;
11951
11952         nvcfg1 = tr32(NVRAM_CFG1);
11953         nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
11954
11955         switch (nvmpinstrp) {
11956         case FLASH_5720_EEPROM_HD:
11957         case FLASH_5720_EEPROM_LD:
11958                 tp->nvram_jedecnum = JEDEC_ATMEL;
11959                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11960
11961                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11962                 tw32(NVRAM_CFG1, nvcfg1);
11963                 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
11964                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11965                 else
11966                         tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
11967                 return;
11968         case FLASH_5720VENDOR_M_ATMEL_DB011D:
11969         case FLASH_5720VENDOR_A_ATMEL_DB011B:
11970         case FLASH_5720VENDOR_A_ATMEL_DB011D:
11971         case FLASH_5720VENDOR_M_ATMEL_DB021D:
11972         case FLASH_5720VENDOR_A_ATMEL_DB021B:
11973         case FLASH_5720VENDOR_A_ATMEL_DB021D:
11974         case FLASH_5720VENDOR_M_ATMEL_DB041D:
11975         case FLASH_5720VENDOR_A_ATMEL_DB041B:
11976         case FLASH_5720VENDOR_A_ATMEL_DB041D:
11977         case FLASH_5720VENDOR_M_ATMEL_DB081D:
11978         case FLASH_5720VENDOR_A_ATMEL_DB081D:
11979         case FLASH_5720VENDOR_ATMEL_45USPT:
11980                 tp->nvram_jedecnum = JEDEC_ATMEL;
11981                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11982                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11983
11984                 switch (nvmpinstrp) {
11985                 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11986                 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11987                 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11988                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11989                         break;
11990                 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11991                 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11992                 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11993                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11994                         break;
11995                 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11996                 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11997                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11998                         break;
11999                 default:
12000                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12001                         break;
12002                 }
12003                 break;
12004         case FLASH_5720VENDOR_M_ST_M25PE10:
12005         case FLASH_5720VENDOR_M_ST_M45PE10:
12006         case FLASH_5720VENDOR_A_ST_M25PE10:
12007         case FLASH_5720VENDOR_A_ST_M45PE10:
12008         case FLASH_5720VENDOR_M_ST_M25PE20:
12009         case FLASH_5720VENDOR_M_ST_M45PE20:
12010         case FLASH_5720VENDOR_A_ST_M25PE20:
12011         case FLASH_5720VENDOR_A_ST_M45PE20:
12012         case FLASH_5720VENDOR_M_ST_M25PE40:
12013         case FLASH_5720VENDOR_M_ST_M45PE40:
12014         case FLASH_5720VENDOR_A_ST_M25PE40:
12015         case FLASH_5720VENDOR_A_ST_M45PE40:
12016         case FLASH_5720VENDOR_M_ST_M25PE80:
12017         case FLASH_5720VENDOR_M_ST_M45PE80:
12018         case FLASH_5720VENDOR_A_ST_M25PE80:
12019         case FLASH_5720VENDOR_A_ST_M45PE80:
12020         case FLASH_5720VENDOR_ST_25USPT:
12021         case FLASH_5720VENDOR_ST_45USPT:
12022                 tp->nvram_jedecnum = JEDEC_ST;
12023                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
12024                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
12025
12026                 switch (nvmpinstrp) {
12027                 case FLASH_5720VENDOR_M_ST_M25PE20:
12028                 case FLASH_5720VENDOR_M_ST_M45PE20:
12029                 case FLASH_5720VENDOR_A_ST_M25PE20:
12030                 case FLASH_5720VENDOR_A_ST_M45PE20:
12031                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12032                         break;
12033                 case FLASH_5720VENDOR_M_ST_M25PE40:
12034                 case FLASH_5720VENDOR_M_ST_M45PE40:
12035                 case FLASH_5720VENDOR_A_ST_M25PE40:
12036                 case FLASH_5720VENDOR_A_ST_M45PE40:
12037                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12038                         break;
12039                 case FLASH_5720VENDOR_M_ST_M25PE80:
12040                 case FLASH_5720VENDOR_M_ST_M45PE80:
12041                 case FLASH_5720VENDOR_A_ST_M25PE80:
12042                 case FLASH_5720VENDOR_A_ST_M45PE80:
12043                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12044                         break;
12045                 default:
12046                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12047                         break;
12048                 }
12049                 break;
12050         default:
12051                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
12052                 return;
12053         }
12054
12055         tg3_nvram_get_pagesize(tp, nvcfg1);
12056         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12057                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12058 }
12059
12060 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12061 static void __devinit tg3_nvram_init(struct tg3 *tp)
12062 {
12063         tw32_f(GRC_EEPROM_ADDR,
12064              (EEPROM_ADDR_FSM_RESET |
12065               (EEPROM_DEFAULT_CLOCK_PERIOD <<
12066                EEPROM_ADDR_CLKPERD_SHIFT)));
12067
12068         msleep(1);
12069
12070         /* Enable seeprom accesses. */
12071         tw32_f(GRC_LOCAL_CTRL,
12072              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12073         udelay(100);
12074
12075         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12076             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12077                 tp->tg3_flags |= TG3_FLAG_NVRAM;
12078
12079                 if (tg3_nvram_lock(tp)) {
12080                         netdev_warn(tp->dev,
12081                                     "Cannot get nvram lock, %s failed\n",
12082                                     __func__);
12083                         return;
12084                 }
12085                 tg3_enable_nvram_access(tp);
12086
12087                 tp->nvram_size = 0;
12088
12089                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12090                         tg3_get_5752_nvram_info(tp);
12091                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12092                         tg3_get_5755_nvram_info(tp);
12093                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12094                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12095                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12096                         tg3_get_5787_nvram_info(tp);
12097                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12098                         tg3_get_5761_nvram_info(tp);
12099                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12100                         tg3_get_5906_nvram_info(tp);
12101                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12102                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12103                         tg3_get_57780_nvram_info(tp);
12104                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12105                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12106                         tg3_get_5717_nvram_info(tp);
12107                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12108                         tg3_get_5720_nvram_info(tp);
12109                 else
12110                         tg3_get_nvram_info(tp);
12111
12112                 if (tp->nvram_size == 0)
12113                         tg3_get_nvram_size(tp);
12114
12115                 tg3_disable_nvram_access(tp);
12116                 tg3_nvram_unlock(tp);
12117
12118         } else {
12119                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
12120
12121                 tg3_get_eeprom_size(tp);
12122         }
12123 }
12124
12125 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12126                                     u32 offset, u32 len, u8 *buf)
12127 {
12128         int i, j, rc = 0;
12129         u32 val;
12130
12131         for (i = 0; i < len; i += 4) {
12132                 u32 addr;
12133                 __be32 data;
12134
12135                 addr = offset + i;
12136
12137                 memcpy(&data, buf + i, 4);
12138
12139                 /*
12140                  * The SEEPROM interface expects the data to always be opposite
12141                  * the native endian format.  We accomplish this by reversing
12142                  * all the operations that would have been performed on the
12143                  * data from a call to tg3_nvram_read_be32().
12144                  */
12145                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12146
12147                 val = tr32(GRC_EEPROM_ADDR);
12148                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12149
12150                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12151                         EEPROM_ADDR_READ);
12152                 tw32(GRC_EEPROM_ADDR, val |
12153                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
12154                         (addr & EEPROM_ADDR_ADDR_MASK) |
12155                         EEPROM_ADDR_START |
12156                         EEPROM_ADDR_WRITE);
12157
12158                 for (j = 0; j < 1000; j++) {
12159                         val = tr32(GRC_EEPROM_ADDR);
12160
12161                         if (val & EEPROM_ADDR_COMPLETE)
12162                                 break;
12163                         msleep(1);
12164                 }
12165                 if (!(val & EEPROM_ADDR_COMPLETE)) {
12166                         rc = -EBUSY;
12167                         break;
12168                 }
12169         }
12170
12171         return rc;
12172 }
12173
12174 /* offset and length are dword aligned */
12175 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12176                 u8 *buf)
12177 {
12178         int ret = 0;
12179         u32 pagesize = tp->nvram_pagesize;
12180         u32 pagemask = pagesize - 1;
12181         u32 nvram_cmd;
12182         u8 *tmp;
12183
12184         tmp = kmalloc(pagesize, GFP_KERNEL);
12185         if (tmp == NULL)
12186                 return -ENOMEM;
12187
12188         while (len) {
12189                 int j;
12190                 u32 phy_addr, page_off, size;
12191
12192                 phy_addr = offset & ~pagemask;
12193
12194                 for (j = 0; j < pagesize; j += 4) {
12195                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
12196                                                   (__be32 *) (tmp + j));
12197                         if (ret)
12198                                 break;
12199                 }
12200                 if (ret)
12201                         break;
12202
12203                 page_off = offset & pagemask;
12204                 size = pagesize;
12205                 if (len < size)
12206                         size = len;
12207
12208                 len -= size;
12209
12210                 memcpy(tmp + page_off, buf, size);
12211
12212                 offset = offset + (pagesize - page_off);
12213
12214                 tg3_enable_nvram_access(tp);
12215
12216                 /*
12217                  * Before we can erase the flash page, we need
12218                  * to issue a special "write enable" command.
12219                  */
12220                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12221
12222                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12223                         break;
12224
12225                 /* Erase the target page */
12226                 tw32(NVRAM_ADDR, phy_addr);
12227
12228                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12229                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12230
12231                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12232                         break;
12233
12234                 /* Issue another write enable to start the write. */
12235                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12236
12237                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12238                         break;
12239
12240                 for (j = 0; j < pagesize; j += 4) {
12241                         __be32 data;
12242
12243                         data = *((__be32 *) (tmp + j));
12244
12245                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12246
12247                         tw32(NVRAM_ADDR, phy_addr + j);
12248
12249                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12250                                 NVRAM_CMD_WR;
12251
12252                         if (j == 0)
12253                                 nvram_cmd |= NVRAM_CMD_FIRST;
12254                         else if (j == (pagesize - 4))
12255                                 nvram_cmd |= NVRAM_CMD_LAST;
12256
12257                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12258                                 break;
12259                 }
12260                 if (ret)
12261                         break;
12262         }
12263
12264         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12265         tg3_nvram_exec_cmd(tp, nvram_cmd);
12266
12267         kfree(tmp);
12268
12269         return ret;
12270 }
12271
12272 /* offset and length are dword aligned */
12273 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12274                 u8 *buf)
12275 {
12276         int i, ret = 0;
12277
12278         for (i = 0; i < len; i += 4, offset += 4) {
12279                 u32 page_off, phy_addr, nvram_cmd;
12280                 __be32 data;
12281
12282                 memcpy(&data, buf + i, 4);
12283                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12284
12285                 page_off = offset % tp->nvram_pagesize;
12286
12287                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12288
12289                 tw32(NVRAM_ADDR, phy_addr);
12290
12291                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12292
12293                 if (page_off == 0 || i == 0)
12294                         nvram_cmd |= NVRAM_CMD_FIRST;
12295                 if (page_off == (tp->nvram_pagesize - 4))
12296                         nvram_cmd |= NVRAM_CMD_LAST;
12297
12298                 if (i == (len - 4))
12299                         nvram_cmd |= NVRAM_CMD_LAST;
12300
12301                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12302                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12303                     (tp->nvram_jedecnum == JEDEC_ST) &&
12304                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12305
12306                         if ((ret = tg3_nvram_exec_cmd(tp,
12307                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12308                                 NVRAM_CMD_DONE)))
12309
12310                                 break;
12311                 }
12312                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12313                         /* We always do complete word writes to eeprom. */
12314                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12315                 }
12316
12317                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12318                         break;
12319         }
12320         return ret;
12321 }
12322
12323 /* offset and length are dword aligned */
12324 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12325 {
12326         int ret;
12327
12328         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12329                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12330                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12331                 udelay(40);
12332         }
12333
12334         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12335                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12336         } else {
12337                 u32 grc_mode;
12338
12339                 ret = tg3_nvram_lock(tp);
12340                 if (ret)
12341                         return ret;
12342
12343                 tg3_enable_nvram_access(tp);
12344                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12345                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12346                         tw32(NVRAM_WRITE1, 0x406);
12347
12348                 grc_mode = tr32(GRC_MODE);
12349                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12350
12351                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12352                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12353
12354                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12355                                 buf);
12356                 } else {
12357                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12358                                 buf);
12359                 }
12360
12361                 grc_mode = tr32(GRC_MODE);
12362                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12363
12364                 tg3_disable_nvram_access(tp);
12365                 tg3_nvram_unlock(tp);
12366         }
12367
12368         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12369                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12370                 udelay(40);
12371         }
12372
12373         return ret;
12374 }
12375
12376 struct subsys_tbl_ent {
12377         u16 subsys_vendor, subsys_devid;
12378         u32 phy_id;
12379 };
12380
12381 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12382         /* Broadcom boards. */
12383         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12384           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12385         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12386           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12387         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12388           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12389         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12390           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12391         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12392           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12393         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12394           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12395         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12396           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12397         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12398           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12399         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12400           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12401         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12402           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12403         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12404           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12405
12406         /* 3com boards. */
12407         { TG3PCI_SUBVENDOR_ID_3COM,
12408           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12409         { TG3PCI_SUBVENDOR_ID_3COM,
12410           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12411         { TG3PCI_SUBVENDOR_ID_3COM,
12412           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12413         { TG3PCI_SUBVENDOR_ID_3COM,
12414           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12415         { TG3PCI_SUBVENDOR_ID_3COM,
12416           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12417
12418         /* DELL boards. */
12419         { TG3PCI_SUBVENDOR_ID_DELL,
12420           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12421         { TG3PCI_SUBVENDOR_ID_DELL,
12422           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12423         { TG3PCI_SUBVENDOR_ID_DELL,
12424           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12425         { TG3PCI_SUBVENDOR_ID_DELL,
12426           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12427
12428         /* Compaq boards. */
12429         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12430           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12431         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12432           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12433         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12434           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12435         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12436           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12437         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12438           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12439
12440         /* IBM boards. */
12441         { TG3PCI_SUBVENDOR_ID_IBM,
12442           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12443 };
12444
12445 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12446 {
12447         int i;
12448
12449         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12450                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12451                      tp->pdev->subsystem_vendor) &&
12452                     (subsys_id_to_phy_id[i].subsys_devid ==
12453                      tp->pdev->subsystem_device))
12454                         return &subsys_id_to_phy_id[i];
12455         }
12456         return NULL;
12457 }
12458
12459 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12460 {
12461         u32 val;
12462         u16 pmcsr;
12463
12464         /* On some early chips the SRAM cannot be accessed in D3hot state,
12465          * so need make sure we're in D0.
12466          */
12467         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12468         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12469         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12470         msleep(1);
12471
12472         /* Make sure register accesses (indirect or otherwise)
12473          * will function correctly.
12474          */
12475         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12476                                tp->misc_host_ctrl);
12477
12478         /* The memory arbiter has to be enabled in order for SRAM accesses
12479          * to succeed.  Normally on powerup the tg3 chip firmware will make
12480          * sure it is enabled, but other entities such as system netboot
12481          * code might disable it.
12482          */
12483         val = tr32(MEMARB_MODE);
12484         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12485
12486         tp->phy_id = TG3_PHY_ID_INVALID;
12487         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12488
12489         /* Assume an onboard device and WOL capable by default.  */
12490         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12491
12492         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12493                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12494                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12495                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12496                 }
12497                 val = tr32(VCPU_CFGSHDW);
12498                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12499                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12500                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12501                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12502                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12503                 goto done;
12504         }
12505
12506         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12507         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12508                 u32 nic_cfg, led_cfg;
12509                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12510                 int eeprom_phy_serdes = 0;
12511
12512                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12513                 tp->nic_sram_data_cfg = nic_cfg;
12514
12515                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12516                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12517                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12518                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12519                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12520                     (ver > 0) && (ver < 0x100))
12521                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12522
12523                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12524                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12525
12526                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12527                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12528                         eeprom_phy_serdes = 1;
12529
12530                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12531                 if (nic_phy_id != 0) {
12532                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12533                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12534
12535                         eeprom_phy_id  = (id1 >> 16) << 10;
12536                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12537                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12538                 } else
12539                         eeprom_phy_id = 0;
12540
12541                 tp->phy_id = eeprom_phy_id;
12542                 if (eeprom_phy_serdes) {
12543                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12544                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12545                         else
12546                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12547                 }
12548
12549                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12550                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12551                                     SHASTA_EXT_LED_MODE_MASK);
12552                 else
12553                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12554
12555                 switch (led_cfg) {
12556                 default:
12557                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12558                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12559                         break;
12560
12561                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12562                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12563                         break;
12564
12565                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12566                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12567
12568                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12569                          * read on some older 5700/5701 bootcode.
12570                          */
12571                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12572                             ASIC_REV_5700 ||
12573                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12574                             ASIC_REV_5701)
12575                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12576
12577                         break;
12578
12579                 case SHASTA_EXT_LED_SHARED:
12580                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12581                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12582                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12583                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12584                                                  LED_CTRL_MODE_PHY_2);
12585                         break;
12586
12587                 case SHASTA_EXT_LED_MAC:
12588                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12589                         break;
12590
12591                 case SHASTA_EXT_LED_COMBO:
12592                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12593                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12594                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12595                                                  LED_CTRL_MODE_PHY_2);
12596                         break;
12597
12598                 }
12599
12600                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12601                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12602                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12603                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12604
12605                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12606                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12607
12608                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12609                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12610                         if ((tp->pdev->subsystem_vendor ==
12611                              PCI_VENDOR_ID_ARIMA) &&
12612                             (tp->pdev->subsystem_device == 0x205a ||
12613                              tp->pdev->subsystem_device == 0x2063))
12614                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12615                 } else {
12616                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12617                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12618                 }
12619
12620                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12621                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12622                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12623                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12624                 }
12625
12626                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12627                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12628                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12629
12630                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12631                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12632                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12633
12634                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12635                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12636                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12637
12638                 if (cfg2 & (1 << 17))
12639                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12640
12641                 /* serdes signal pre-emphasis in register 0x590 set by */
12642                 /* bootcode if bit 18 is set */
12643                 if (cfg2 & (1 << 18))
12644                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12645
12646                 if (((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) ||
12647                     ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12648                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12649                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12650                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12651
12652                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12653                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12654                     !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
12655                         u32 cfg3;
12656
12657                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12658                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12659                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12660                 }
12661
12662                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12663                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12664                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12665                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12666                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12667                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12668         }
12669 done:
12670         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
12671                 device_set_wakeup_enable(&tp->pdev->dev,
12672                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12673         else
12674                 device_set_wakeup_capable(&tp->pdev->dev, false);
12675 }
12676
12677 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12678 {
12679         int i;
12680         u32 val;
12681
12682         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12683         tw32(OTP_CTRL, cmd);
12684
12685         /* Wait for up to 1 ms for command to execute. */
12686         for (i = 0; i < 100; i++) {
12687                 val = tr32(OTP_STATUS);
12688                 if (val & OTP_STATUS_CMD_DONE)
12689                         break;
12690                 udelay(10);
12691         }
12692
12693         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12694 }
12695
12696 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12697  * configuration is a 32-bit value that straddles the alignment boundary.
12698  * We do two 32-bit reads and then shift and merge the results.
12699  */
12700 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12701 {
12702         u32 bhalf_otp, thalf_otp;
12703
12704         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12705
12706         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12707                 return 0;
12708
12709         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12710
12711         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12712                 return 0;
12713
12714         thalf_otp = tr32(OTP_READ_DATA);
12715
12716         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12717
12718         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12719                 return 0;
12720
12721         bhalf_otp = tr32(OTP_READ_DATA);
12722
12723         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12724 }
12725
12726 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12727 {
12728         u32 adv = ADVERTISED_Autoneg |
12729                   ADVERTISED_Pause;
12730
12731         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12732                 adv |= ADVERTISED_1000baseT_Half |
12733                        ADVERTISED_1000baseT_Full;
12734
12735         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12736                 adv |= ADVERTISED_100baseT_Half |
12737                        ADVERTISED_100baseT_Full |
12738                        ADVERTISED_10baseT_Half |
12739                        ADVERTISED_10baseT_Full |
12740                        ADVERTISED_TP;
12741         else
12742                 adv |= ADVERTISED_FIBRE;
12743
12744         tp->link_config.advertising = adv;
12745         tp->link_config.speed = SPEED_INVALID;
12746         tp->link_config.duplex = DUPLEX_INVALID;
12747         tp->link_config.autoneg = AUTONEG_ENABLE;
12748         tp->link_config.active_speed = SPEED_INVALID;
12749         tp->link_config.active_duplex = DUPLEX_INVALID;
12750         tp->link_config.orig_speed = SPEED_INVALID;
12751         tp->link_config.orig_duplex = DUPLEX_INVALID;
12752         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12753 }
12754
12755 static int __devinit tg3_phy_probe(struct tg3 *tp)
12756 {
12757         u32 hw_phy_id_1, hw_phy_id_2;
12758         u32 hw_phy_id, hw_phy_id_masked;
12759         int err;
12760
12761         /* flow control autonegotiation is default behavior */
12762         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12763         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12764
12765         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12766                 return tg3_phy_init(tp);
12767
12768         /* Reading the PHY ID register can conflict with ASF
12769          * firmware access to the PHY hardware.
12770          */
12771         err = 0;
12772         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12773             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12774                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12775         } else {
12776                 /* Now read the physical PHY_ID from the chip and verify
12777                  * that it is sane.  If it doesn't look good, we fall back
12778                  * to either the hard-coded table based PHY_ID and failing
12779                  * that the value found in the eeprom area.
12780                  */
12781                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12782                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12783
12784                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12785                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12786                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12787
12788                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12789         }
12790
12791         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12792                 tp->phy_id = hw_phy_id;
12793                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12794                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12795                 else
12796                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12797         } else {
12798                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12799                         /* Do nothing, phy ID already set up in
12800                          * tg3_get_eeprom_hw_cfg().
12801                          */
12802                 } else {
12803                         struct subsys_tbl_ent *p;
12804
12805                         /* No eeprom signature?  Try the hardcoded
12806                          * subsys device table.
12807                          */
12808                         p = tg3_lookup_by_subsys(tp);
12809                         if (!p)
12810                                 return -ENODEV;
12811
12812                         tp->phy_id = p->phy_id;
12813                         if (!tp->phy_id ||
12814                             tp->phy_id == TG3_PHY_ID_BCM8002)
12815                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12816                 }
12817         }
12818
12819         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12820             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12821               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12822              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12823               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12824                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12825
12826         tg3_phy_init_link_config(tp);
12827
12828         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12829             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12830             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12831                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12832
12833                 tg3_readphy(tp, MII_BMSR, &bmsr);
12834                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12835                     (bmsr & BMSR_LSTATUS))
12836                         goto skip_phy_reset;
12837
12838                 err = tg3_phy_reset(tp);
12839                 if (err)
12840                         return err;
12841
12842                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12843                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12844                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12845                 tg3_ctrl = 0;
12846                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12847                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12848                                     MII_TG3_CTRL_ADV_1000_FULL);
12849                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12850                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12851                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12852                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12853                 }
12854
12855                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12856                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12857                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12858                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12859                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12860
12861                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12862                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12863
12864                         tg3_writephy(tp, MII_BMCR,
12865                                      BMCR_ANENABLE | BMCR_ANRESTART);
12866                 }
12867                 tg3_phy_set_wirespeed(tp);
12868
12869                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12870                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12871                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12872         }
12873
12874 skip_phy_reset:
12875         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12876                 err = tg3_init_5401phy_dsp(tp);
12877                 if (err)
12878                         return err;
12879
12880                 err = tg3_init_5401phy_dsp(tp);
12881         }
12882
12883         return err;
12884 }
12885
12886 static void __devinit tg3_read_vpd(struct tg3 *tp)
12887 {
12888         u8 *vpd_data;
12889         unsigned int block_end, rosize, len;
12890         int j, i = 0;
12891         u32 magic;
12892
12893         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12894             tg3_nvram_read(tp, 0x0, &magic))
12895                 goto out_no_vpd;
12896
12897         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12898         if (!vpd_data)
12899                 goto out_no_vpd;
12900
12901         if (magic == TG3_EEPROM_MAGIC) {
12902                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12903                         u32 tmp;
12904
12905                         /* The data is in little-endian format in NVRAM.
12906                          * Use the big-endian read routines to preserve
12907                          * the byte order as it exists in NVRAM.
12908                          */
12909                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12910                                 goto out_not_found;
12911
12912                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12913                 }
12914         } else {
12915                 ssize_t cnt;
12916                 unsigned int pos = 0;
12917
12918                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12919                         cnt = pci_read_vpd(tp->pdev, pos,
12920                                            TG3_NVM_VPD_LEN - pos,
12921                                            &vpd_data[pos]);
12922                         if (cnt == -ETIMEDOUT || cnt == -EINTR)
12923                                 cnt = 0;
12924                         else if (cnt < 0)
12925                                 goto out_not_found;
12926                 }
12927                 if (pos != TG3_NVM_VPD_LEN)
12928                         goto out_not_found;
12929         }
12930
12931         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12932                              PCI_VPD_LRDT_RO_DATA);
12933         if (i < 0)
12934                 goto out_not_found;
12935
12936         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12937         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12938         i += PCI_VPD_LRDT_TAG_SIZE;
12939
12940         if (block_end > TG3_NVM_VPD_LEN)
12941                 goto out_not_found;
12942
12943         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12944                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12945         if (j > 0) {
12946                 len = pci_vpd_info_field_size(&vpd_data[j]);
12947
12948                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12949                 if (j + len > block_end || len != 4 ||
12950                     memcmp(&vpd_data[j], "1028", 4))
12951                         goto partno;
12952
12953                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12954                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12955                 if (j < 0)
12956                         goto partno;
12957
12958                 len = pci_vpd_info_field_size(&vpd_data[j]);
12959
12960                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12961                 if (j + len > block_end)
12962                         goto partno;
12963
12964                 memcpy(tp->fw_ver, &vpd_data[j], len);
12965                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12966         }
12967
12968 partno:
12969         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12970                                       PCI_VPD_RO_KEYWORD_PARTNO);
12971         if (i < 0)
12972                 goto out_not_found;
12973
12974         len = pci_vpd_info_field_size(&vpd_data[i]);
12975
12976         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12977         if (len > TG3_BPN_SIZE ||
12978             (len + i) > TG3_NVM_VPD_LEN)
12979                 goto out_not_found;
12980
12981         memcpy(tp->board_part_number, &vpd_data[i], len);
12982
12983 out_not_found:
12984         kfree(vpd_data);
12985         if (tp->board_part_number[0])
12986                 return;
12987
12988 out_no_vpd:
12989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12990                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12991                         strcpy(tp->board_part_number, "BCM5717");
12992                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12993                         strcpy(tp->board_part_number, "BCM5718");
12994                 else
12995                         goto nomatch;
12996         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12997                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12998                         strcpy(tp->board_part_number, "BCM57780");
12999                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13000                         strcpy(tp->board_part_number, "BCM57760");
13001                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13002                         strcpy(tp->board_part_number, "BCM57790");
13003                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13004                         strcpy(tp->board_part_number, "BCM57788");
13005                 else
13006                         goto nomatch;
13007         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13008                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13009                         strcpy(tp->board_part_number, "BCM57761");
13010                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13011                         strcpy(tp->board_part_number, "BCM57765");
13012                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13013                         strcpy(tp->board_part_number, "BCM57781");
13014                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13015                         strcpy(tp->board_part_number, "BCM57785");
13016                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13017                         strcpy(tp->board_part_number, "BCM57791");
13018                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13019                         strcpy(tp->board_part_number, "BCM57795");
13020                 else
13021                         goto nomatch;
13022         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13023                 strcpy(tp->board_part_number, "BCM95906");
13024         } else {
13025 nomatch:
13026                 strcpy(tp->board_part_number, "none");
13027         }
13028 }
13029
13030 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13031 {
13032         u32 val;
13033
13034         if (tg3_nvram_read(tp, offset, &val) ||
13035             (val & 0xfc000000) != 0x0c000000 ||
13036             tg3_nvram_read(tp, offset + 4, &val) ||
13037             val != 0)
13038                 return 0;
13039
13040         return 1;
13041 }
13042
13043 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13044 {
13045         u32 val, offset, start, ver_offset;
13046         int i, dst_off;
13047         bool newver = false;
13048
13049         if (tg3_nvram_read(tp, 0xc, &offset) ||
13050             tg3_nvram_read(tp, 0x4, &start))
13051                 return;
13052
13053         offset = tg3_nvram_logical_addr(tp, offset);
13054
13055         if (tg3_nvram_read(tp, offset, &val))
13056                 return;
13057
13058         if ((val & 0xfc000000) == 0x0c000000) {
13059                 if (tg3_nvram_read(tp, offset + 4, &val))
13060                         return;
13061
13062                 if (val == 0)
13063                         newver = true;
13064         }
13065
13066         dst_off = strlen(tp->fw_ver);
13067
13068         if (newver) {
13069                 if (TG3_VER_SIZE - dst_off < 16 ||
13070                     tg3_nvram_read(tp, offset + 8, &ver_offset))
13071                         return;
13072
13073                 offset = offset + ver_offset - start;
13074                 for (i = 0; i < 16; i += 4) {
13075                         __be32 v;
13076                         if (tg3_nvram_read_be32(tp, offset + i, &v))
13077                                 return;
13078
13079                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13080                 }
13081         } else {
13082                 u32 major, minor;
13083
13084                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13085                         return;
13086
13087                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13088                         TG3_NVM_BCVER_MAJSFT;
13089                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13090                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13091                          "v%d.%02d", major, minor);
13092         }
13093 }
13094
13095 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13096 {
13097         u32 val, major, minor;
13098
13099         /* Use native endian representation */
13100         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13101                 return;
13102
13103         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13104                 TG3_NVM_HWSB_CFG1_MAJSFT;
13105         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13106                 TG3_NVM_HWSB_CFG1_MINSFT;
13107
13108         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13109 }
13110
13111 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13112 {
13113         u32 offset, major, minor, build;
13114
13115         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13116
13117         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13118                 return;
13119
13120         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13121         case TG3_EEPROM_SB_REVISION_0:
13122                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13123                 break;
13124         case TG3_EEPROM_SB_REVISION_2:
13125                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13126                 break;
13127         case TG3_EEPROM_SB_REVISION_3:
13128                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13129                 break;
13130         case TG3_EEPROM_SB_REVISION_4:
13131                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13132                 break;
13133         case TG3_EEPROM_SB_REVISION_5:
13134                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13135                 break;
13136         case TG3_EEPROM_SB_REVISION_6:
13137                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13138                 break;
13139         default:
13140                 return;
13141         }
13142
13143         if (tg3_nvram_read(tp, offset, &val))
13144                 return;
13145
13146         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13147                 TG3_EEPROM_SB_EDH_BLD_SHFT;
13148         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13149                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13150         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
13151
13152         if (minor > 99 || build > 26)
13153                 return;
13154
13155         offset = strlen(tp->fw_ver);
13156         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13157                  " v%d.%02d", major, minor);
13158
13159         if (build > 0) {
13160                 offset = strlen(tp->fw_ver);
13161                 if (offset < TG3_VER_SIZE - 1)
13162                         tp->fw_ver[offset] = 'a' + build - 1;
13163         }
13164 }
13165
13166 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13167 {
13168         u32 val, offset, start;
13169         int i, vlen;
13170
13171         for (offset = TG3_NVM_DIR_START;
13172              offset < TG3_NVM_DIR_END;
13173              offset += TG3_NVM_DIRENT_SIZE) {
13174                 if (tg3_nvram_read(tp, offset, &val))
13175                         return;
13176
13177                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13178                         break;
13179         }
13180
13181         if (offset == TG3_NVM_DIR_END)
13182                 return;
13183
13184         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
13185                 start = 0x08000000;
13186         else if (tg3_nvram_read(tp, offset - 4, &start))
13187                 return;
13188
13189         if (tg3_nvram_read(tp, offset + 4, &offset) ||
13190             !tg3_fw_img_is_valid(tp, offset) ||
13191             tg3_nvram_read(tp, offset + 8, &val))
13192                 return;
13193
13194         offset += val - start;
13195
13196         vlen = strlen(tp->fw_ver);
13197
13198         tp->fw_ver[vlen++] = ',';
13199         tp->fw_ver[vlen++] = ' ';
13200
13201         for (i = 0; i < 4; i++) {
13202                 __be32 v;
13203                 if (tg3_nvram_read_be32(tp, offset, &v))
13204                         return;
13205
13206                 offset += sizeof(v);
13207
13208                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13209                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13210                         break;
13211                 }
13212
13213                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13214                 vlen += sizeof(v);
13215         }
13216 }
13217
13218 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13219 {
13220         int vlen;
13221         u32 apedata;
13222         char *fwtype;
13223
13224         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
13225             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
13226                 return;
13227
13228         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13229         if (apedata != APE_SEG_SIG_MAGIC)
13230                 return;
13231
13232         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13233         if (!(apedata & APE_FW_STATUS_READY))
13234                 return;
13235
13236         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13237
13238         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13239                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
13240                 fwtype = "NCSI";
13241         } else {
13242                 fwtype = "DASH";
13243         }
13244
13245         vlen = strlen(tp->fw_ver);
13246
13247         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13248                  fwtype,
13249                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13250                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13251                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13252                  (apedata & APE_FW_VERSION_BLDMSK));
13253 }
13254
13255 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13256 {
13257         u32 val;
13258         bool vpd_vers = false;
13259
13260         if (tp->fw_ver[0] != 0)
13261                 vpd_vers = true;
13262
13263         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13264                 strcat(tp->fw_ver, "sb");
13265                 return;
13266         }
13267
13268         if (tg3_nvram_read(tp, 0, &val))
13269                 return;
13270
13271         if (val == TG3_EEPROM_MAGIC)
13272                 tg3_read_bc_ver(tp);
13273         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13274                 tg3_read_sb_ver(tp, val);
13275         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13276                 tg3_read_hwsb_ver(tp);
13277         else
13278                 return;
13279
13280         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13281              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13282                 goto done;
13283
13284         tg3_read_mgmtfw_ver(tp);
13285
13286 done:
13287         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13288 }
13289
13290 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13291
13292 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13293 {
13294         if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
13295                 return TG3_RX_RET_MAX_SIZE_5717;
13296         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13297                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13298                 return TG3_RX_RET_MAX_SIZE_5700;
13299         else
13300                 return TG3_RX_RET_MAX_SIZE_5705;
13301 }
13302
13303 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13304         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13305         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13306         { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13307         { },
13308 };
13309
13310 static int __devinit tg3_get_invariants(struct tg3 *tp)
13311 {
13312         u32 misc_ctrl_reg;
13313         u32 pci_state_reg, grc_misc_cfg;
13314         u32 val;
13315         u16 pci_cmd;
13316         int err;
13317
13318         /* Force memory write invalidate off.  If we leave it on,
13319          * then on 5700_BX chips we have to enable a workaround.
13320          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13321          * to match the cacheline size.  The Broadcom driver have this
13322          * workaround but turns MWI off all the times so never uses
13323          * it.  This seems to suggest that the workaround is insufficient.
13324          */
13325         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13326         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13327         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13328
13329         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13330          * has the register indirect write enable bit set before
13331          * we try to access any of the MMIO registers.  It is also
13332          * critical that the PCI-X hw workaround situation is decided
13333          * before that as well.
13334          */
13335         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13336                               &misc_ctrl_reg);
13337
13338         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13339                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13341                 u32 prod_id_asic_rev;
13342
13343                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13344                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13345                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13346                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13347                         pci_read_config_dword(tp->pdev,
13348                                               TG3PCI_GEN2_PRODID_ASICREV,
13349                                               &prod_id_asic_rev);
13350                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13351                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13352                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13353                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13354                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13355                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13356                         pci_read_config_dword(tp->pdev,
13357                                               TG3PCI_GEN15_PRODID_ASICREV,
13358                                               &prod_id_asic_rev);
13359                 else
13360                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13361                                               &prod_id_asic_rev);
13362
13363                 tp->pci_chip_rev_id = prod_id_asic_rev;
13364         }
13365
13366         /* Wrong chip ID in 5752 A0. This code can be removed later
13367          * as A0 is not in production.
13368          */
13369         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13370                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13371
13372         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13373          * we need to disable memory and use config. cycles
13374          * only to access all registers. The 5702/03 chips
13375          * can mistakenly decode the special cycles from the
13376          * ICH chipsets as memory write cycles, causing corruption
13377          * of register and memory space. Only certain ICH bridges
13378          * will drive special cycles with non-zero data during the
13379          * address phase which can fall within the 5703's address
13380          * range. This is not an ICH bug as the PCI spec allows
13381          * non-zero address during special cycles. However, only
13382          * these ICH bridges are known to drive non-zero addresses
13383          * during special cycles.
13384          *
13385          * Since special cycles do not cross PCI bridges, we only
13386          * enable this workaround if the 5703 is on the secondary
13387          * bus of these ICH bridges.
13388          */
13389         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13390             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13391                 static struct tg3_dev_id {
13392                         u32     vendor;
13393                         u32     device;
13394                         u32     rev;
13395                 } ich_chipsets[] = {
13396                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13397                           PCI_ANY_ID },
13398                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13399                           PCI_ANY_ID },
13400                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13401                           0xa },
13402                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13403                           PCI_ANY_ID },
13404                         { },
13405                 };
13406                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13407                 struct pci_dev *bridge = NULL;
13408
13409                 while (pci_id->vendor != 0) {
13410                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13411                                                 bridge);
13412                         if (!bridge) {
13413                                 pci_id++;
13414                                 continue;
13415                         }
13416                         if (pci_id->rev != PCI_ANY_ID) {
13417                                 if (bridge->revision > pci_id->rev)
13418                                         continue;
13419                         }
13420                         if (bridge->subordinate &&
13421                             (bridge->subordinate->number ==
13422                              tp->pdev->bus->number)) {
13423
13424                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13425                                 pci_dev_put(bridge);
13426                                 break;
13427                         }
13428                 }
13429         }
13430
13431         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13432                 static struct tg3_dev_id {
13433                         u32     vendor;
13434                         u32     device;
13435                 } bridge_chipsets[] = {
13436                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13437                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13438                         { },
13439                 };
13440                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13441                 struct pci_dev *bridge = NULL;
13442
13443                 while (pci_id->vendor != 0) {
13444                         bridge = pci_get_device(pci_id->vendor,
13445                                                 pci_id->device,
13446                                                 bridge);
13447                         if (!bridge) {
13448                                 pci_id++;
13449                                 continue;
13450                         }
13451                         if (bridge->subordinate &&
13452                             (bridge->subordinate->number <=
13453                              tp->pdev->bus->number) &&
13454                             (bridge->subordinate->subordinate >=
13455                              tp->pdev->bus->number)) {
13456                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13457                                 pci_dev_put(bridge);
13458                                 break;
13459                         }
13460                 }
13461         }
13462
13463         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13464          * DMA addresses > 40-bit. This bridge may have other additional
13465          * 57xx devices behind it in some 4-port NIC designs for example.
13466          * Any tg3 device found behind the bridge will also need the 40-bit
13467          * DMA workaround.
13468          */
13469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13470             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13471                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13472                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13473                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13474         } else {
13475                 struct pci_dev *bridge = NULL;
13476
13477                 do {
13478                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13479                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13480                                                 bridge);
13481                         if (bridge && bridge->subordinate &&
13482                             (bridge->subordinate->number <=
13483                              tp->pdev->bus->number) &&
13484                             (bridge->subordinate->subordinate >=
13485                              tp->pdev->bus->number)) {
13486                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13487                                 pci_dev_put(bridge);
13488                                 break;
13489                         }
13490                 } while (bridge);
13491         }
13492
13493         /* Initialize misc host control in PCI block. */
13494         tp->misc_host_ctrl |= (misc_ctrl_reg &
13495                                MISC_HOST_CTRL_CHIPREV);
13496         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13497                                tp->misc_host_ctrl);
13498
13499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13500             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13501             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13502             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13503                 tp->pdev_peer = tg3_find_peer(tp);
13504
13505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13506             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13507             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13508                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13509
13510         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13511             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13512                 tp->tg3_flags3 |= TG3_FLG3_57765_PLUS;
13513
13514         /* Intentionally exclude ASIC_REV_5906 */
13515         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13516             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13517             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13518             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13519             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13520             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13521             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13522                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13523
13524         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13525             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13526             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13527             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13528             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13529                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13530
13531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13532             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13533                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13534
13535         /* 5700 B0 chips do not support checksumming correctly due
13536          * to hardware bugs.
13537          */
13538         if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
13539                 u32 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
13540
13541                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13542                         features |= NETIF_F_IPV6_CSUM;
13543                 tp->dev->features |= features;
13544                 tp->dev->hw_features |= features;
13545                 tp->dev->vlan_features |= features;
13546         }
13547
13548         /* Determine TSO capabilities */
13549         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13550                 ; /* Do nothing. HW bug. */
13551         else if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
13552                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13553         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13554                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13555                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13556         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13557                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13558                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13559                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13560                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13561         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13562                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13563                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13564                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13565                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13566                         tp->fw_needed = FIRMWARE_TG3TSO5;
13567                 else
13568                         tp->fw_needed = FIRMWARE_TG3TSO;
13569         }
13570
13571         tp->irq_max = 1;
13572
13573         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13574                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13575                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13576                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13577                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13578                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13579                      tp->pdev_peer == tp->pdev))
13580                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13581
13582                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13583                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13584                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13585                 }
13586
13587                 if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
13588                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13589                         tp->irq_max = TG3_IRQ_MAX_VECS;
13590                 }
13591         }
13592
13593         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13594             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13595             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13596                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13597         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13598                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13599                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13600         }
13601
13602         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13603                 tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
13604
13605         if ((tp->tg3_flags3 & TG3_FLG3_57765_PLUS) &&
13606             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13607                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13608
13609         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13610             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13611             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13612                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13613
13614         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13615                               &pci_state_reg);
13616
13617         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13618         if (tp->pcie_cap != 0) {
13619                 u16 lnkctl;
13620
13621                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13622
13623                 tp->pcie_readrq = 4096;
13624                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13625                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13626                         tp->pcie_readrq = 2048;
13627
13628                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13629
13630                 pci_read_config_word(tp->pdev,
13631                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13632                                      &lnkctl);
13633                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13634                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13635                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13636                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13637                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13638                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13639                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13640                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13641                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13642                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13643                 }
13644         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13645                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13646         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13647                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13648                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13649                 if (!tp->pcix_cap) {
13650                         dev_err(&tp->pdev->dev,
13651                                 "Cannot find PCI-X capability, aborting\n");
13652                         return -EIO;
13653                 }
13654
13655                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13656                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13657         }
13658
13659         /* If we have an AMD 762 or VIA K8T800 chipset, write
13660          * reordering to the mailbox registers done by the host
13661          * controller can cause major troubles.  We read back from
13662          * every mailbox register write to force the writes to be
13663          * posted to the chip in order.
13664          */
13665         if (pci_dev_present(tg3_write_reorder_chipsets) &&
13666             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13667                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13668
13669         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13670                              &tp->pci_cacheline_sz);
13671         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13672                              &tp->pci_lat_timer);
13673         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13674             tp->pci_lat_timer < 64) {
13675                 tp->pci_lat_timer = 64;
13676                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13677                                       tp->pci_lat_timer);
13678         }
13679
13680         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13681                 /* 5700 BX chips need to have their TX producer index
13682                  * mailboxes written twice to workaround a bug.
13683                  */
13684                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13685
13686                 /* If we are in PCI-X mode, enable register write workaround.
13687                  *
13688                  * The workaround is to use indirect register accesses
13689                  * for all chip writes not to mailbox registers.
13690                  */
13691                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13692                         u32 pm_reg;
13693
13694                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13695
13696                         /* The chip can have it's power management PCI config
13697                          * space registers clobbered due to this bug.
13698                          * So explicitly force the chip into D0 here.
13699                          */
13700                         pci_read_config_dword(tp->pdev,
13701                                               tp->pm_cap + PCI_PM_CTRL,
13702                                               &pm_reg);
13703                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13704                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13705                         pci_write_config_dword(tp->pdev,
13706                                                tp->pm_cap + PCI_PM_CTRL,
13707                                                pm_reg);
13708
13709                         /* Also, force SERR#/PERR# in PCI command. */
13710                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13711                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13712                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13713                 }
13714         }
13715
13716         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13717                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13718         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13719                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13720
13721         /* Chip-specific fixup from Broadcom driver */
13722         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13723             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13724                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13725                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13726         }
13727
13728         /* Default fast path register access methods */
13729         tp->read32 = tg3_read32;
13730         tp->write32 = tg3_write32;
13731         tp->read32_mbox = tg3_read32;
13732         tp->write32_mbox = tg3_write32;
13733         tp->write32_tx_mbox = tg3_write32;
13734         tp->write32_rx_mbox = tg3_write32;
13735
13736         /* Various workaround register access methods */
13737         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13738                 tp->write32 = tg3_write_indirect_reg32;
13739         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13740                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13741                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13742                 /*
13743                  * Back to back register writes can cause problems on these
13744                  * chips, the workaround is to read back all reg writes
13745                  * except those to mailbox regs.
13746                  *
13747                  * See tg3_write_indirect_reg32().
13748                  */
13749                 tp->write32 = tg3_write_flush_reg32;
13750         }
13751
13752         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13753             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13754                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13755                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13756                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13757         }
13758
13759         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13760                 tp->read32 = tg3_read_indirect_reg32;
13761                 tp->write32 = tg3_write_indirect_reg32;
13762                 tp->read32_mbox = tg3_read_indirect_mbox;
13763                 tp->write32_mbox = tg3_write_indirect_mbox;
13764                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13765                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13766
13767                 iounmap(tp->regs);
13768                 tp->regs = NULL;
13769
13770                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13771                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13772                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13773         }
13774         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13775                 tp->read32_mbox = tg3_read32_mbox_5906;
13776                 tp->write32_mbox = tg3_write32_mbox_5906;
13777                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13778                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13779         }
13780
13781         if (tp->write32 == tg3_write_indirect_reg32 ||
13782             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13783              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13784               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13785                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13786
13787         /* Get eeprom hw config before calling tg3_set_power_state().
13788          * In particular, the TG3_FLG2_IS_NIC flag must be
13789          * determined before calling tg3_set_power_state() so that
13790          * we know whether or not to switch out of Vaux power.
13791          * When the flag is set, it means that GPIO1 is used for eeprom
13792          * write protect and also implies that it is a LOM where GPIOs
13793          * are not used to switch power.
13794          */
13795         tg3_get_eeprom_hw_cfg(tp);
13796
13797         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13798                 /* Allow reads and writes to the
13799                  * APE register and memory space.
13800                  */
13801                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13802                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13803                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13804                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13805                                        pci_state_reg);
13806         }
13807
13808         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13809             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13810             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13811             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13812             (tp->tg3_flags3 & TG3_FLG3_57765_PLUS))
13813                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13814
13815         /* Set up tp->grc_local_ctrl before calling tg_power_up().
13816          * GPIO1 driven high will bring 5700's external PHY out of reset.
13817          * It is also used as eeprom write protect on LOMs.
13818          */
13819         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13820         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13821             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13822                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13823                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13824         /* Unused GPIO3 must be driven as output on 5752 because there
13825          * are no pull-up resistors on unused GPIO pins.
13826          */
13827         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13828                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13829
13830         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13831             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13832             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13833                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13834
13835         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13836             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13837                 /* Turn off the debug UART. */
13838                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13839                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13840                         /* Keep VMain power. */
13841                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13842                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13843         }
13844
13845         /* Force the chip into D0. */
13846         err = tg3_power_up(tp);
13847         if (err) {
13848                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13849                 return err;
13850         }
13851
13852         /* Derive initial jumbo mode from MTU assigned in
13853          * ether_setup() via the alloc_etherdev() call
13854          */
13855         if (tp->dev->mtu > ETH_DATA_LEN &&
13856             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13857                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13858
13859         /* Determine WakeOnLan speed to use. */
13860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13861             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13862             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13863             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13864                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13865         } else {
13866                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13867         }
13868
13869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13870                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13871
13872         /* A few boards don't want Ethernet@WireSpeed phy feature */
13873         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13874             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13875              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13876              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13877             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13878             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13879                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13880
13881         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13882             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13883                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13884         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13885                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13886
13887         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13888             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13889             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13890             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13891             !(tp->tg3_flags3 & TG3_FLG3_57765_PLUS)) {
13892                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13893                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13894                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13895                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13896                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13897                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13898                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13899                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13900                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13901                 } else
13902                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13903         }
13904
13905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13906             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13907                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13908                 if (tp->phy_otp == 0)
13909                         tp->phy_otp = TG3_OTP_DEFAULT;
13910         }
13911
13912         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13913                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13914         else
13915                 tp->mi_mode = MAC_MI_MODE_BASE;
13916
13917         tp->coalesce_mode = 0;
13918         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13919             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13920                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13921
13922         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13923             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13924                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13925
13926         err = tg3_mdio_init(tp);
13927         if (err)
13928                 return err;
13929
13930         /* Initialize data/descriptor byte/word swapping. */
13931         val = tr32(GRC_MODE);
13932         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13933                 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
13934                         GRC_MODE_WORD_SWAP_B2HRX_DATA |
13935                         GRC_MODE_B2HRX_ENABLE |
13936                         GRC_MODE_HTX2B_ENABLE |
13937                         GRC_MODE_HOST_STACKUP);
13938         else
13939                 val &= GRC_MODE_HOST_STACKUP;
13940
13941         tw32(GRC_MODE, val | tp->grc_mode);
13942
13943         tg3_switch_clocks(tp);
13944
13945         /* Clear this out for sanity. */
13946         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13947
13948         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13949                               &pci_state_reg);
13950         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13951             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13952                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13953
13954                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13955                     chiprevid == CHIPREV_ID_5701_B0 ||
13956                     chiprevid == CHIPREV_ID_5701_B2 ||
13957                     chiprevid == CHIPREV_ID_5701_B5) {
13958                         void __iomem *sram_base;
13959
13960                         /* Write some dummy words into the SRAM status block
13961                          * area, see if it reads back correctly.  If the return
13962                          * value is bad, force enable the PCIX workaround.
13963                          */
13964                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13965
13966                         writel(0x00000000, sram_base);
13967                         writel(0x00000000, sram_base + 4);
13968                         writel(0xffffffff, sram_base + 4);
13969                         if (readl(sram_base) != 0x00000000)
13970                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13971                 }
13972         }
13973
13974         udelay(50);
13975         tg3_nvram_init(tp);
13976
13977         grc_misc_cfg = tr32(GRC_MISC_CFG);
13978         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13979
13980         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13981             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13982              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13983                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13984
13985         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13986             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13987                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13988         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13989                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13990                                       HOSTCC_MODE_CLRTICK_TXBD);
13991
13992                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13993                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13994                                        tp->misc_host_ctrl);
13995         }
13996
13997         /* Preserve the APE MAC_MODE bits */
13998         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13999                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14000         else
14001                 tp->mac_mode = TG3_DEF_MAC_MODE;
14002
14003         /* these are limited to 10/100 only */
14004         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14005              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14006             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14007              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14008              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14009               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14010               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14011             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14012              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14013               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14014               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14015             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14016             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14017             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14018             (tp->phy_flags & TG3_PHYFLG_IS_FET))
14019                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14020
14021         err = tg3_phy_probe(tp);
14022         if (err) {
14023                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14024                 /* ... but do not return immediately ... */
14025                 tg3_mdio_fini(tp);
14026         }
14027
14028         tg3_read_vpd(tp);
14029         tg3_read_fw_ver(tp);
14030
14031         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14032                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14033         } else {
14034                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14035                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14036                 else
14037                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14038         }
14039
14040         /* 5700 {AX,BX} chips have a broken status block link
14041          * change bit implementation, so we must use the
14042          * status register in those cases.
14043          */
14044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14045                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14046         else
14047                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
14048
14049         /* The led_ctrl is set during tg3_phy_probe, here we might
14050          * have to force the link status polling mechanism based
14051          * upon subsystem IDs.
14052          */
14053         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14055             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14056                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14057                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
14058         }
14059
14060         /* For all SERDES we poll the MAC status register. */
14061         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14062                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
14063         else
14064                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
14065
14066         tp->rx_offset = NET_IP_ALIGN;
14067         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14068         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14069             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
14070                 tp->rx_offset = 0;
14071 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14072                 tp->rx_copy_thresh = ~(u16)0;
14073 #endif
14074         }
14075
14076         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14077         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14078         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14079
14080         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14081
14082         /* Increment the rx prod index on the rx std ring by at most
14083          * 8 for these chips to workaround hw errata.
14084          */
14085         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14086             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14087             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14088                 tp->rx_std_max_post = 8;
14089
14090         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
14091                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14092                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
14093
14094         return err;
14095 }
14096
14097 #ifdef CONFIG_SPARC
14098 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14099 {
14100         struct net_device *dev = tp->dev;
14101         struct pci_dev *pdev = tp->pdev;
14102         struct device_node *dp = pci_device_to_OF_node(pdev);
14103         const unsigned char *addr;
14104         int len;
14105
14106         addr = of_get_property(dp, "local-mac-address", &len);
14107         if (addr && len == 6) {
14108                 memcpy(dev->dev_addr, addr, 6);
14109                 memcpy(dev->perm_addr, dev->dev_addr, 6);
14110                 return 0;
14111         }
14112         return -ENODEV;
14113 }
14114
14115 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14116 {
14117         struct net_device *dev = tp->dev;
14118
14119         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14120         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14121         return 0;
14122 }
14123 #endif
14124
14125 static int __devinit tg3_get_device_address(struct tg3 *tp)
14126 {
14127         struct net_device *dev = tp->dev;
14128         u32 hi, lo, mac_offset;
14129         int addr_ok = 0;
14130
14131 #ifdef CONFIG_SPARC
14132         if (!tg3_get_macaddr_sparc(tp))
14133                 return 0;
14134 #endif
14135
14136         mac_offset = 0x7c;
14137         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
14138             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
14139                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14140                         mac_offset = 0xcc;
14141                 if (tg3_nvram_lock(tp))
14142                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14143                 else
14144                         tg3_nvram_unlock(tp);
14145         } else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14146                 if (PCI_FUNC(tp->pdev->devfn) & 1)
14147                         mac_offset = 0xcc;
14148                 if (PCI_FUNC(tp->pdev->devfn) > 1)
14149                         mac_offset += 0x18c;
14150         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14151                 mac_offset = 0x10;
14152
14153         /* First try to get it from MAC address mailbox. */
14154         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14155         if ((hi >> 16) == 0x484b) {
14156                 dev->dev_addr[0] = (hi >>  8) & 0xff;
14157                 dev->dev_addr[1] = (hi >>  0) & 0xff;
14158
14159                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14160                 dev->dev_addr[2] = (lo >> 24) & 0xff;
14161                 dev->dev_addr[3] = (lo >> 16) & 0xff;
14162                 dev->dev_addr[4] = (lo >>  8) & 0xff;
14163                 dev->dev_addr[5] = (lo >>  0) & 0xff;
14164
14165                 /* Some old bootcode may report a 0 MAC address in SRAM */
14166                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14167         }
14168         if (!addr_ok) {
14169                 /* Next, try NVRAM. */
14170                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
14171                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14172                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14173                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14174                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14175                 }
14176                 /* Finally just fetch it out of the MAC control regs. */
14177                 else {
14178                         hi = tr32(MAC_ADDR_0_HIGH);
14179                         lo = tr32(MAC_ADDR_0_LOW);
14180
14181                         dev->dev_addr[5] = lo & 0xff;
14182                         dev->dev_addr[4] = (lo >> 8) & 0xff;
14183                         dev->dev_addr[3] = (lo >> 16) & 0xff;
14184                         dev->dev_addr[2] = (lo >> 24) & 0xff;
14185                         dev->dev_addr[1] = hi & 0xff;
14186                         dev->dev_addr[0] = (hi >> 8) & 0xff;
14187                 }
14188         }
14189
14190         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14191 #ifdef CONFIG_SPARC
14192                 if (!tg3_get_default_macaddr_sparc(tp))
14193                         return 0;
14194 #endif
14195                 return -EINVAL;
14196         }
14197         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14198         return 0;
14199 }
14200
14201 #define BOUNDARY_SINGLE_CACHELINE       1
14202 #define BOUNDARY_MULTI_CACHELINE        2
14203
14204 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14205 {
14206         int cacheline_size;
14207         u8 byte;
14208         int goal;
14209
14210         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14211         if (byte == 0)
14212                 cacheline_size = 1024;
14213         else
14214                 cacheline_size = (int) byte * 4;
14215
14216         /* On 5703 and later chips, the boundary bits have no
14217          * effect.
14218          */
14219         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14220             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14221             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14222                 goto out;
14223
14224 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14225         goal = BOUNDARY_MULTI_CACHELINE;
14226 #else
14227 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14228         goal = BOUNDARY_SINGLE_CACHELINE;
14229 #else
14230         goal = 0;
14231 #endif
14232 #endif
14233
14234         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14235                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14236                 goto out;
14237         }
14238
14239         if (!goal)
14240                 goto out;
14241
14242         /* PCI controllers on most RISC systems tend to disconnect
14243          * when a device tries to burst across a cache-line boundary.
14244          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14245          *
14246          * Unfortunately, for PCI-E there are only limited
14247          * write-side controls for this, and thus for reads
14248          * we will still get the disconnects.  We'll also waste
14249          * these PCI cycles for both read and write for chips
14250          * other than 5700 and 5701 which do not implement the
14251          * boundary bits.
14252          */
14253         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14254             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14255                 switch (cacheline_size) {
14256                 case 16:
14257                 case 32:
14258                 case 64:
14259                 case 128:
14260                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14261                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14262                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14263                         } else {
14264                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14265                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14266                         }
14267                         break;
14268
14269                 case 256:
14270                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14271                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14272                         break;
14273
14274                 default:
14275                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14276                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14277                         break;
14278                 }
14279         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14280                 switch (cacheline_size) {
14281                 case 16:
14282                 case 32:
14283                 case 64:
14284                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14285                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14286                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14287                                 break;
14288                         }
14289                         /* fallthrough */
14290                 case 128:
14291                 default:
14292                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14293                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14294                         break;
14295                 }
14296         } else {
14297                 switch (cacheline_size) {
14298                 case 16:
14299                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14300                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14301                                         DMA_RWCTRL_WRITE_BNDRY_16);
14302                                 break;
14303                         }
14304                         /* fallthrough */
14305                 case 32:
14306                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14307                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14308                                         DMA_RWCTRL_WRITE_BNDRY_32);
14309                                 break;
14310                         }
14311                         /* fallthrough */
14312                 case 64:
14313                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14314                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14315                                         DMA_RWCTRL_WRITE_BNDRY_64);
14316                                 break;
14317                         }
14318                         /* fallthrough */
14319                 case 128:
14320                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14321                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14322                                         DMA_RWCTRL_WRITE_BNDRY_128);
14323                                 break;
14324                         }
14325                         /* fallthrough */
14326                 case 256:
14327                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14328                                 DMA_RWCTRL_WRITE_BNDRY_256);
14329                         break;
14330                 case 512:
14331                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14332                                 DMA_RWCTRL_WRITE_BNDRY_512);
14333                         break;
14334                 case 1024:
14335                 default:
14336                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14337                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14338                         break;
14339                 }
14340         }
14341
14342 out:
14343         return val;
14344 }
14345
14346 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14347 {
14348         struct tg3_internal_buffer_desc test_desc;
14349         u32 sram_dma_descs;
14350         int i, ret;
14351
14352         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14353
14354         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14355         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14356         tw32(RDMAC_STATUS, 0);
14357         tw32(WDMAC_STATUS, 0);
14358
14359         tw32(BUFMGR_MODE, 0);
14360         tw32(FTQ_RESET, 0);
14361
14362         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14363         test_desc.addr_lo = buf_dma & 0xffffffff;
14364         test_desc.nic_mbuf = 0x00002100;
14365         test_desc.len = size;
14366
14367         /*
14368          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14369          * the *second* time the tg3 driver was getting loaded after an
14370          * initial scan.
14371          *
14372          * Broadcom tells me:
14373          *   ...the DMA engine is connected to the GRC block and a DMA
14374          *   reset may affect the GRC block in some unpredictable way...
14375          *   The behavior of resets to individual blocks has not been tested.
14376          *
14377          * Broadcom noted the GRC reset will also reset all sub-components.
14378          */
14379         if (to_device) {
14380                 test_desc.cqid_sqid = (13 << 8) | 2;
14381
14382                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14383                 udelay(40);
14384         } else {
14385                 test_desc.cqid_sqid = (16 << 8) | 7;
14386
14387                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14388                 udelay(40);
14389         }
14390         test_desc.flags = 0x00000005;
14391
14392         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14393                 u32 val;
14394
14395                 val = *(((u32 *)&test_desc) + i);
14396                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14397                                        sram_dma_descs + (i * sizeof(u32)));
14398                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14399         }
14400         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14401
14402         if (to_device)
14403                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14404         else
14405                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14406
14407         ret = -ENODEV;
14408         for (i = 0; i < 40; i++) {
14409                 u32 val;
14410
14411                 if (to_device)
14412                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14413                 else
14414                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14415                 if ((val & 0xffff) == sram_dma_descs) {
14416                         ret = 0;
14417                         break;
14418                 }
14419
14420                 udelay(100);
14421         }
14422
14423         return ret;
14424 }
14425
14426 #define TEST_BUFFER_SIZE        0x2000
14427
14428 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14429         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14430         { },
14431 };
14432
14433 static int __devinit tg3_test_dma(struct tg3 *tp)
14434 {
14435         dma_addr_t buf_dma;
14436         u32 *buf, saved_dma_rwctrl;
14437         int ret = 0;
14438
14439         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14440                                  &buf_dma, GFP_KERNEL);
14441         if (!buf) {
14442                 ret = -ENOMEM;
14443                 goto out_nofree;
14444         }
14445
14446         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14447                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14448
14449         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14450
14451         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS)
14452                 goto out;
14453
14454         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14455                 /* DMA read watermark not used on PCIE */
14456                 tp->dma_rwctrl |= 0x00180000;
14457         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14458                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14459                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14460                         tp->dma_rwctrl |= 0x003f0000;
14461                 else
14462                         tp->dma_rwctrl |= 0x003f000f;
14463         } else {
14464                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14465                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14466                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14467                         u32 read_water = 0x7;
14468
14469                         /* If the 5704 is behind the EPB bridge, we can
14470                          * do the less restrictive ONE_DMA workaround for
14471                          * better performance.
14472                          */
14473                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14474                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14475                                 tp->dma_rwctrl |= 0x8000;
14476                         else if (ccval == 0x6 || ccval == 0x7)
14477                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14478
14479                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14480                                 read_water = 4;
14481                         /* Set bit 23 to enable PCIX hw bug fix */
14482                         tp->dma_rwctrl |=
14483                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14484                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14485                                 (1 << 23);
14486                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14487                         /* 5780 always in PCIX mode */
14488                         tp->dma_rwctrl |= 0x00144000;
14489                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14490                         /* 5714 always in PCIX mode */
14491                         tp->dma_rwctrl |= 0x00148000;
14492                 } else {
14493                         tp->dma_rwctrl |= 0x001b000f;
14494                 }
14495         }
14496
14497         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14498             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14499                 tp->dma_rwctrl &= 0xfffffff0;
14500
14501         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14502             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14503                 /* Remove this if it causes problems for some boards. */
14504                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14505
14506                 /* On 5700/5701 chips, we need to set this bit.
14507                  * Otherwise the chip will issue cacheline transactions
14508                  * to streamable DMA memory with not all the byte
14509                  * enables turned on.  This is an error on several
14510                  * RISC PCI controllers, in particular sparc64.
14511                  *
14512                  * On 5703/5704 chips, this bit has been reassigned
14513                  * a different meaning.  In particular, it is used
14514                  * on those chips to enable a PCI-X workaround.
14515                  */
14516                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14517         }
14518
14519         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14520
14521 #if 0
14522         /* Unneeded, already done by tg3_get_invariants.  */
14523         tg3_switch_clocks(tp);
14524 #endif
14525
14526         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14527             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14528                 goto out;
14529
14530         /* It is best to perform DMA test with maximum write burst size
14531          * to expose the 5700/5701 write DMA bug.
14532          */
14533         saved_dma_rwctrl = tp->dma_rwctrl;
14534         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14535         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14536
14537         while (1) {
14538                 u32 *p = buf, i;
14539
14540                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14541                         p[i] = i;
14542
14543                 /* Send the buffer to the chip. */
14544                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14545                 if (ret) {
14546                         dev_err(&tp->pdev->dev,
14547                                 "%s: Buffer write failed. err = %d\n",
14548                                 __func__, ret);
14549                         break;
14550                 }
14551
14552 #if 0
14553                 /* validate data reached card RAM correctly. */
14554                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14555                         u32 val;
14556                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14557                         if (le32_to_cpu(val) != p[i]) {
14558                                 dev_err(&tp->pdev->dev,
14559                                         "%s: Buffer corrupted on device! "
14560                                         "(%d != %d)\n", __func__, val, i);
14561                                 /* ret = -ENODEV here? */
14562                         }
14563                         p[i] = 0;
14564                 }
14565 #endif
14566                 /* Now read it back. */
14567                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14568                 if (ret) {
14569                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14570                                 "err = %d\n", __func__, ret);
14571                         break;
14572                 }
14573
14574                 /* Verify it. */
14575                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14576                         if (p[i] == i)
14577                                 continue;
14578
14579                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14580                             DMA_RWCTRL_WRITE_BNDRY_16) {
14581                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14582                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14583                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14584                                 break;
14585                         } else {
14586                                 dev_err(&tp->pdev->dev,
14587                                         "%s: Buffer corrupted on read back! "
14588                                         "(%d != %d)\n", __func__, p[i], i);
14589                                 ret = -ENODEV;
14590                                 goto out;
14591                         }
14592                 }
14593
14594                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14595                         /* Success. */
14596                         ret = 0;
14597                         break;
14598                 }
14599         }
14600         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14601             DMA_RWCTRL_WRITE_BNDRY_16) {
14602
14603                 /* DMA test passed without adjusting DMA boundary,
14604                  * now look for chipsets that are known to expose the
14605                  * DMA bug without failing the test.
14606                  */
14607                 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14608                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14609                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14610                 } else {
14611                         /* Safe to use the calculated DMA boundary. */
14612                         tp->dma_rwctrl = saved_dma_rwctrl;
14613                 }
14614
14615                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14616         }
14617
14618 out:
14619         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14620 out_nofree:
14621         return ret;
14622 }
14623
14624 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14625 {
14626         if (tp->tg3_flags3 & TG3_FLG3_57765_PLUS) {
14627                 tp->bufmgr_config.mbuf_read_dma_low_water =
14628                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14629                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14630                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14631                 tp->bufmgr_config.mbuf_high_water =
14632                         DEFAULT_MB_HIGH_WATER_57765;
14633
14634                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14635                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14636                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14637                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14638                 tp->bufmgr_config.mbuf_high_water_jumbo =
14639                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14640         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14641                 tp->bufmgr_config.mbuf_read_dma_low_water =
14642                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14643                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14644                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14645                 tp->bufmgr_config.mbuf_high_water =
14646                         DEFAULT_MB_HIGH_WATER_5705;
14647                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14648                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14649                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14650                         tp->bufmgr_config.mbuf_high_water =
14651                                 DEFAULT_MB_HIGH_WATER_5906;
14652                 }
14653
14654                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14655                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14656                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14657                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14658                 tp->bufmgr_config.mbuf_high_water_jumbo =
14659                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14660         } else {
14661                 tp->bufmgr_config.mbuf_read_dma_low_water =
14662                         DEFAULT_MB_RDMA_LOW_WATER;
14663                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14664                         DEFAULT_MB_MACRX_LOW_WATER;
14665                 tp->bufmgr_config.mbuf_high_water =
14666                         DEFAULT_MB_HIGH_WATER;
14667
14668                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14669                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14670                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14671                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14672                 tp->bufmgr_config.mbuf_high_water_jumbo =
14673                         DEFAULT_MB_HIGH_WATER_JUMBO;
14674         }
14675
14676         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14677         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14678 }
14679
14680 static char * __devinit tg3_phy_string(struct tg3 *tp)
14681 {
14682         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14683         case TG3_PHY_ID_BCM5400:        return "5400";
14684         case TG3_PHY_ID_BCM5401:        return "5401";
14685         case TG3_PHY_ID_BCM5411:        return "5411";
14686         case TG3_PHY_ID_BCM5701:        return "5701";
14687         case TG3_PHY_ID_BCM5703:        return "5703";
14688         case TG3_PHY_ID_BCM5704:        return "5704";
14689         case TG3_PHY_ID_BCM5705:        return "5705";
14690         case TG3_PHY_ID_BCM5750:        return "5750";
14691         case TG3_PHY_ID_BCM5752:        return "5752";
14692         case TG3_PHY_ID_BCM5714:        return "5714";
14693         case TG3_PHY_ID_BCM5780:        return "5780";
14694         case TG3_PHY_ID_BCM5755:        return "5755";
14695         case TG3_PHY_ID_BCM5787:        return "5787";
14696         case TG3_PHY_ID_BCM5784:        return "5784";
14697         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14698         case TG3_PHY_ID_BCM5906:        return "5906";
14699         case TG3_PHY_ID_BCM5761:        return "5761";
14700         case TG3_PHY_ID_BCM5718C:       return "5718C";
14701         case TG3_PHY_ID_BCM5718S:       return "5718S";
14702         case TG3_PHY_ID_BCM57765:       return "57765";
14703         case TG3_PHY_ID_BCM5719C:       return "5719C";
14704         case TG3_PHY_ID_BCM5720C:       return "5720C";
14705         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14706         case 0:                 return "serdes";
14707         default:                return "unknown";
14708         }
14709 }
14710
14711 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14712 {
14713         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14714                 strcpy(str, "PCI Express");
14715                 return str;
14716         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14717                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14718
14719                 strcpy(str, "PCIX:");
14720
14721                 if ((clock_ctrl == 7) ||
14722                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14723                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14724                         strcat(str, "133MHz");
14725                 else if (clock_ctrl == 0)
14726                         strcat(str, "33MHz");
14727                 else if (clock_ctrl == 2)
14728                         strcat(str, "50MHz");
14729                 else if (clock_ctrl == 4)
14730                         strcat(str, "66MHz");
14731                 else if (clock_ctrl == 6)
14732                         strcat(str, "100MHz");
14733         } else {
14734                 strcpy(str, "PCI:");
14735                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14736                         strcat(str, "66MHz");
14737                 else
14738                         strcat(str, "33MHz");
14739         }
14740         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14741                 strcat(str, ":32-bit");
14742         else
14743                 strcat(str, ":64-bit");
14744         return str;
14745 }
14746
14747 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14748 {
14749         struct pci_dev *peer;
14750         unsigned int func, devnr = tp->pdev->devfn & ~7;
14751
14752         for (func = 0; func < 8; func++) {
14753                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14754                 if (peer && peer != tp->pdev)
14755                         break;
14756                 pci_dev_put(peer);
14757         }
14758         /* 5704 can be configured in single-port mode, set peer to
14759          * tp->pdev in that case.
14760          */
14761         if (!peer) {
14762                 peer = tp->pdev;
14763                 return peer;
14764         }
14765
14766         /*
14767          * We don't need to keep the refcount elevated; there's no way
14768          * to remove one half of this device without removing the other
14769          */
14770         pci_dev_put(peer);
14771
14772         return peer;
14773 }
14774
14775 static void __devinit tg3_init_coal(struct tg3 *tp)
14776 {
14777         struct ethtool_coalesce *ec = &tp->coal;
14778
14779         memset(ec, 0, sizeof(*ec));
14780         ec->cmd = ETHTOOL_GCOALESCE;
14781         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14782         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14783         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14784         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14785         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14786         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14787         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14788         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14789         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14790
14791         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14792                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14793                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14794                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14795                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14796                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14797         }
14798
14799         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14800                 ec->rx_coalesce_usecs_irq = 0;
14801                 ec->tx_coalesce_usecs_irq = 0;
14802                 ec->stats_block_coalesce_usecs = 0;
14803         }
14804 }
14805
14806 static const struct net_device_ops tg3_netdev_ops = {
14807         .ndo_open               = tg3_open,
14808         .ndo_stop               = tg3_close,
14809         .ndo_start_xmit         = tg3_start_xmit,
14810         .ndo_get_stats64        = tg3_get_stats64,
14811         .ndo_validate_addr      = eth_validate_addr,
14812         .ndo_set_multicast_list = tg3_set_rx_mode,
14813         .ndo_set_mac_address    = tg3_set_mac_addr,
14814         .ndo_do_ioctl           = tg3_ioctl,
14815         .ndo_tx_timeout         = tg3_tx_timeout,
14816         .ndo_change_mtu         = tg3_change_mtu,
14817         .ndo_fix_features       = tg3_fix_features,
14818 #ifdef CONFIG_NET_POLL_CONTROLLER
14819         .ndo_poll_controller    = tg3_poll_controller,
14820 #endif
14821 };
14822
14823 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14824         .ndo_open               = tg3_open,
14825         .ndo_stop               = tg3_close,
14826         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14827         .ndo_get_stats64        = tg3_get_stats64,
14828         .ndo_validate_addr      = eth_validate_addr,
14829         .ndo_set_multicast_list = tg3_set_rx_mode,
14830         .ndo_set_mac_address    = tg3_set_mac_addr,
14831         .ndo_do_ioctl           = tg3_ioctl,
14832         .ndo_tx_timeout         = tg3_tx_timeout,
14833         .ndo_change_mtu         = tg3_change_mtu,
14834 #ifdef CONFIG_NET_POLL_CONTROLLER
14835         .ndo_poll_controller    = tg3_poll_controller,
14836 #endif
14837 };
14838
14839 static int __devinit tg3_init_one(struct pci_dev *pdev,
14840                                   const struct pci_device_id *ent)
14841 {
14842         struct net_device *dev;
14843         struct tg3 *tp;
14844         int i, err, pm_cap;
14845         u32 sndmbx, rcvmbx, intmbx;
14846         char str[40];
14847         u64 dma_mask, persist_dma_mask;
14848         u32 hw_features = 0;
14849
14850         printk_once(KERN_INFO "%s\n", version);
14851
14852         err = pci_enable_device(pdev);
14853         if (err) {
14854                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14855                 return err;
14856         }
14857
14858         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14859         if (err) {
14860                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14861                 goto err_out_disable_pdev;
14862         }
14863
14864         pci_set_master(pdev);
14865
14866         /* Find power-management capability. */
14867         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14868         if (pm_cap == 0) {
14869                 dev_err(&pdev->dev,
14870                         "Cannot find Power Management capability, aborting\n");
14871                 err = -EIO;
14872                 goto err_out_free_res;
14873         }
14874
14875         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14876         if (!dev) {
14877                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14878                 err = -ENOMEM;
14879                 goto err_out_free_res;
14880         }
14881
14882         SET_NETDEV_DEV(dev, &pdev->dev);
14883
14884         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14885
14886         tp = netdev_priv(dev);
14887         tp->pdev = pdev;
14888         tp->dev = dev;
14889         tp->pm_cap = pm_cap;
14890         tp->rx_mode = TG3_DEF_RX_MODE;
14891         tp->tx_mode = TG3_DEF_TX_MODE;
14892
14893         if (tg3_debug > 0)
14894                 tp->msg_enable = tg3_debug;
14895         else
14896                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14897
14898         /* The word/byte swap controls here control register access byte
14899          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14900          * setting below.
14901          */
14902         tp->misc_host_ctrl =
14903                 MISC_HOST_CTRL_MASK_PCI_INT |
14904                 MISC_HOST_CTRL_WORD_SWAP |
14905                 MISC_HOST_CTRL_INDIR_ACCESS |
14906                 MISC_HOST_CTRL_PCISTATE_RW;
14907
14908         /* The NONFRM (non-frame) byte/word swap controls take effect
14909          * on descriptor entries, anything which isn't packet data.
14910          *
14911          * The StrongARM chips on the board (one for tx, one for rx)
14912          * are running in big-endian mode.
14913          */
14914         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14915                         GRC_MODE_WSWAP_NONFRM_DATA);
14916 #ifdef __BIG_ENDIAN
14917         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14918 #endif
14919         spin_lock_init(&tp->lock);
14920         spin_lock_init(&tp->indirect_lock);
14921         INIT_WORK(&tp->reset_task, tg3_reset_task);
14922
14923         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14924         if (!tp->regs) {
14925                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14926                 err = -ENOMEM;
14927                 goto err_out_free_dev;
14928         }
14929
14930         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14931         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14932
14933         dev->ethtool_ops = &tg3_ethtool_ops;
14934         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14935         dev->irq = pdev->irq;
14936
14937         err = tg3_get_invariants(tp);
14938         if (err) {
14939                 dev_err(&pdev->dev,
14940                         "Problem fetching invariants of chip, aborting\n");
14941                 goto err_out_iounmap;
14942         }
14943
14944         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14945             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
14946                 dev->netdev_ops = &tg3_netdev_ops;
14947         else
14948                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14949
14950
14951         /* The EPB bridge inside 5714, 5715, and 5780 and any
14952          * device behind the EPB cannot support DMA addresses > 40-bit.
14953          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14954          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14955          * do DMA address check in tg3_start_xmit().
14956          */
14957         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14958                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14959         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14960                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14961 #ifdef CONFIG_HIGHMEM
14962                 dma_mask = DMA_BIT_MASK(64);
14963 #endif
14964         } else
14965                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14966
14967         /* Configure DMA attributes. */
14968         if (dma_mask > DMA_BIT_MASK(32)) {
14969                 err = pci_set_dma_mask(pdev, dma_mask);
14970                 if (!err) {
14971                         dev->features |= NETIF_F_HIGHDMA;
14972                         err = pci_set_consistent_dma_mask(pdev,
14973                                                           persist_dma_mask);
14974                         if (err < 0) {
14975                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14976                                         "DMA for consistent allocations\n");
14977                                 goto err_out_iounmap;
14978                         }
14979                 }
14980         }
14981         if (err || dma_mask == DMA_BIT_MASK(32)) {
14982                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14983                 if (err) {
14984                         dev_err(&pdev->dev,
14985                                 "No usable DMA configuration, aborting\n");
14986                         goto err_out_iounmap;
14987                 }
14988         }
14989
14990         tg3_init_bufmgr_config(tp);
14991
14992         /* Selectively allow TSO based on operating conditions */
14993         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14994             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14995                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14996         else {
14997                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14998                 tp->fw_needed = NULL;
14999         }
15000
15001         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
15002                 tp->fw_needed = FIRMWARE_TG3;
15003
15004         /* TSO is on by default on chips that support hardware TSO.
15005          * Firmware TSO on older chips gives lower performance, so it
15006          * is off by default, but can be enabled using ethtool.
15007          */
15008         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
15009             (dev->features & NETIF_F_IP_CSUM))
15010                 hw_features |= NETIF_F_TSO;
15011         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
15012             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
15013                 if (dev->features & NETIF_F_IPV6_CSUM)
15014                         hw_features |= NETIF_F_TSO6;
15015                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
15016                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15017                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15018                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15019                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15020                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15021                         hw_features |= NETIF_F_TSO_ECN;
15022         }
15023
15024         dev->hw_features |= hw_features;
15025         dev->features |= hw_features;
15026         dev->vlan_features |= hw_features;
15027
15028         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15029             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
15030             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15031                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
15032                 tp->rx_pending = 63;
15033         }
15034
15035         err = tg3_get_device_address(tp);
15036         if (err) {
15037                 dev_err(&pdev->dev,
15038                         "Could not obtain valid ethernet address, aborting\n");
15039                 goto err_out_iounmap;
15040         }
15041
15042         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
15043                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15044                 if (!tp->aperegs) {
15045                         dev_err(&pdev->dev,
15046                                 "Cannot map APE registers, aborting\n");
15047                         err = -ENOMEM;
15048                         goto err_out_iounmap;
15049                 }
15050
15051                 tg3_ape_lock_init(tp);
15052
15053                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
15054                         tg3_read_dash_ver(tp);
15055         }
15056
15057         /*
15058          * Reset chip in case UNDI or EFI driver did not shutdown
15059          * DMA self test will enable WDMAC and we'll see (spurious)
15060          * pending DMA on the PCI bus at that point.
15061          */
15062         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15063             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15064                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15065                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15066         }
15067
15068         err = tg3_test_dma(tp);
15069         if (err) {
15070                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15071                 goto err_out_apeunmap;
15072         }
15073
15074         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15075         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15076         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15077         for (i = 0; i < tp->irq_max; i++) {
15078                 struct tg3_napi *tnapi = &tp->napi[i];
15079
15080                 tnapi->tp = tp;
15081                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15082
15083                 tnapi->int_mbox = intmbx;
15084                 if (i < 4)
15085                         intmbx += 0x8;
15086                 else
15087                         intmbx += 0x4;
15088
15089                 tnapi->consmbox = rcvmbx;
15090                 tnapi->prodmbox = sndmbx;
15091
15092                 if (i)
15093                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15094                 else
15095                         tnapi->coal_now = HOSTCC_MODE_NOW;
15096
15097                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
15098                         break;
15099
15100                 /*
15101                  * If we support MSIX, we'll be using RSS.  If we're using
15102                  * RSS, the first vector only handles link interrupts and the
15103                  * remaining vectors handle rx and tx interrupts.  Reuse the
15104                  * mailbox values for the next iteration.  The values we setup
15105                  * above are still useful for the single vectored mode.
15106                  */
15107                 if (!i)
15108                         continue;
15109
15110                 rcvmbx += 0x8;
15111
15112                 if (sndmbx & 0x4)
15113                         sndmbx -= 0x4;
15114                 else
15115                         sndmbx += 0xc;
15116         }
15117
15118         tg3_init_coal(tp);
15119
15120         pci_set_drvdata(pdev, dev);
15121
15122         err = register_netdev(dev);
15123         if (err) {
15124                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15125                 goto err_out_apeunmap;
15126         }
15127
15128         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15129                     tp->board_part_number,
15130                     tp->pci_chip_rev_id,
15131                     tg3_bus_string(tp, str),
15132                     dev->dev_addr);
15133
15134         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15135                 struct phy_device *phydev;
15136                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15137                 netdev_info(dev,
15138                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15139                             phydev->drv->name, dev_name(&phydev->dev));
15140         } else {
15141                 char *ethtype;
15142
15143                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15144                         ethtype = "10/100Base-TX";
15145                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15146                         ethtype = "1000Base-SX";
15147                 else
15148                         ethtype = "10/100/1000Base-T";
15149
15150                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15151                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
15152                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
15153         }
15154
15155         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15156                     (dev->features & NETIF_F_RXCSUM) != 0,
15157                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
15158                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15159                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
15160                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
15161         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15162                     tp->dma_rwctrl,
15163                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15164                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15165
15166         return 0;
15167
15168 err_out_apeunmap:
15169         if (tp->aperegs) {
15170                 iounmap(tp->aperegs);
15171                 tp->aperegs = NULL;
15172         }
15173
15174 err_out_iounmap:
15175         if (tp->regs) {
15176                 iounmap(tp->regs);
15177                 tp->regs = NULL;
15178         }
15179
15180 err_out_free_dev:
15181         free_netdev(dev);
15182
15183 err_out_free_res:
15184         pci_release_regions(pdev);
15185
15186 err_out_disable_pdev:
15187         pci_disable_device(pdev);
15188         pci_set_drvdata(pdev, NULL);
15189         return err;
15190 }
15191
15192 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15193 {
15194         struct net_device *dev = pci_get_drvdata(pdev);
15195
15196         if (dev) {
15197                 struct tg3 *tp = netdev_priv(dev);
15198
15199                 if (tp->fw)
15200                         release_firmware(tp->fw);
15201
15202                 cancel_work_sync(&tp->reset_task);
15203
15204                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15205                         tg3_phy_fini(tp);
15206                         tg3_mdio_fini(tp);
15207                 }
15208
15209                 unregister_netdev(dev);
15210                 if (tp->aperegs) {
15211                         iounmap(tp->aperegs);
15212                         tp->aperegs = NULL;
15213                 }
15214                 if (tp->regs) {
15215                         iounmap(tp->regs);
15216                         tp->regs = NULL;
15217                 }
15218                 free_netdev(dev);
15219                 pci_release_regions(pdev);
15220                 pci_disable_device(pdev);
15221                 pci_set_drvdata(pdev, NULL);
15222         }
15223 }
15224
15225 #ifdef CONFIG_PM_SLEEP
15226 static int tg3_suspend(struct device *device)
15227 {
15228         struct pci_dev *pdev = to_pci_dev(device);
15229         struct net_device *dev = pci_get_drvdata(pdev);
15230         struct tg3 *tp = netdev_priv(dev);
15231         int err;
15232
15233         if (!netif_running(dev))
15234                 return 0;
15235
15236         flush_work_sync(&tp->reset_task);
15237         tg3_phy_stop(tp);
15238         tg3_netif_stop(tp);
15239
15240         del_timer_sync(&tp->timer);
15241
15242         tg3_full_lock(tp, 1);
15243         tg3_disable_ints(tp);
15244         tg3_full_unlock(tp);
15245
15246         netif_device_detach(dev);
15247
15248         tg3_full_lock(tp, 0);
15249         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15250         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15251         tg3_full_unlock(tp);
15252
15253         err = tg3_power_down_prepare(tp);
15254         if (err) {
15255                 int err2;
15256
15257                 tg3_full_lock(tp, 0);
15258
15259                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15260                 err2 = tg3_restart_hw(tp, 1);
15261                 if (err2)
15262                         goto out;
15263
15264                 tp->timer.expires = jiffies + tp->timer_offset;
15265                 add_timer(&tp->timer);
15266
15267                 netif_device_attach(dev);
15268                 tg3_netif_start(tp);
15269
15270 out:
15271                 tg3_full_unlock(tp);
15272
15273                 if (!err2)
15274                         tg3_phy_start(tp);
15275         }
15276
15277         return err;
15278 }
15279
15280 static int tg3_resume(struct device *device)
15281 {
15282         struct pci_dev *pdev = to_pci_dev(device);
15283         struct net_device *dev = pci_get_drvdata(pdev);
15284         struct tg3 *tp = netdev_priv(dev);
15285         int err;
15286
15287         if (!netif_running(dev))
15288                 return 0;
15289
15290         netif_device_attach(dev);
15291
15292         tg3_full_lock(tp, 0);
15293
15294         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15295         err = tg3_restart_hw(tp, 1);
15296         if (err)
15297                 goto out;
15298
15299         tp->timer.expires = jiffies + tp->timer_offset;
15300         add_timer(&tp->timer);
15301
15302         tg3_netif_start(tp);
15303
15304 out:
15305         tg3_full_unlock(tp);
15306
15307         if (!err)
15308                 tg3_phy_start(tp);
15309
15310         return err;
15311 }
15312
15313 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15314 #define TG3_PM_OPS (&tg3_pm_ops)
15315
15316 #else
15317
15318 #define TG3_PM_OPS NULL
15319
15320 #endif /* CONFIG_PM_SLEEP */
15321
15322 static struct pci_driver tg3_driver = {
15323         .name           = DRV_MODULE_NAME,
15324         .id_table       = tg3_pci_tbl,
15325         .probe          = tg3_init_one,
15326         .remove         = __devexit_p(tg3_remove_one),
15327         .driver.pm      = TG3_PM_OPS,
15328 };
15329
15330 static int __init tg3_init(void)
15331 {
15332         return pci_register_driver(&tg3_driver);
15333 }
15334
15335 static void __exit tg3_cleanup(void)
15336 {
15337         pci_unregister_driver(&tg3_driver);
15338 }
15339
15340 module_init(tg3_init);
15341 module_exit(tg3_cleanup);