drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/ip.h>
  38 #include <linux/tcp.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <net/checksum.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC64
  51 #include <asm/idprom.h>
  52 #include <asm/oplib.h>
  53 #include <asm/pbm.h>
  54 #endif
  55
  56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  57 #define TG3_VLAN_TAG_USED 1
  58 #else
  59 #define TG3_VLAN_TAG_USED 0
  60 #endif
  61
  62 #ifdef NETIF_F_TSO
  63 #define TG3_TSO_SUPPORT 1
  64 #else
  65 #define TG3_TSO_SUPPORT 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define PFX DRV_MODULE_NAME     ": "
  72 #define DRV_MODULE_VERSION      "3.57"
  73 #define DRV_MODULE_RELDATE      "Apr 28, 2006"
  74
  75 #define TG3_DEF_MAC_MODE        0
  76 #define TG3_DEF_RX_MODE         0
  77 #define TG3_DEF_TX_MODE         0
  78 #define TG3_DEF_MSG_ENABLE        \
  79         (NETIF_MSG_DRV          | \
  80          NETIF_MSG_PROBE        | \
  81          NETIF_MSG_LINK         | \
  82          NETIF_MSG_TIMER        | \
  83          NETIF_MSG_IFDOWN       | \
  84          NETIF_MSG_IFUP         | \
  85          NETIF_MSG_RX_ERR       | \
  86          NETIF_MSG_TX_ERR)
  87
  88 /* length of time before we decide the hardware is borked,
  89  * and dev->tx_timeout() should be called to fix the problem
  90  */
  91 #define TG3_TX_TIMEOUT                  (5 * HZ)
  92
  93 /* hardware minimum and maximum for a single frame's data payload */
  94 #define TG3_MIN_MTU                     60
  95 #define TG3_MAX_MTU(tp) \
  96         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  97
  98 /* These numbers seem to be hard coded in the NIC firmware somehow.
  99  * You can't change the ring sizes, but you can change where you place
 100  * them in the NIC onboard memory.
 101  */
 102 #define TG3_RX_RING_SIZE                512
 103 #define TG3_DEF_RX_RING_PENDING         200
 104 #define TG3_RX_JUMBO_RING_SIZE          256
 105 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                    TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define TX_BUFFS_AVAIL(TP)                                              \
 128         ((TP)->tx_pending -                                             \
 129          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
 130 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 131
 132 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 133 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 134
 135 /* minimum number of free TX descriptors required to wake up TX process */
 136 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 137
 138 /* number of ETHTOOL_GSTATS u64's */
 139 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 140
 141 #define TG3_NUM_TEST            6
 142
 143 static char version[] __devinitdata =
 144         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 145
 146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 148 MODULE_LICENSE("GPL");
 149 MODULE_VERSION(DRV_MODULE_VERSION);
 150
 151 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 152 module_param(tg3_debug, int, 0);
 153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 154
 155 static struct pci_device_id tg3_pci_tbl[] = {
 156         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 157           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 158         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 160         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 161           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 162         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 163           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 164         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 165           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 166         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 167           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 168         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 169           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 170         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 171           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 172         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 173           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 174         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 175           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 176         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 177           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 178         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 179           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 180         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 181           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 182         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 183           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 184         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 185           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 186         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 187           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 188         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 189           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 190         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 191           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 192         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 193           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 194         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 195           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 196         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 197           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 198         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 199           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 200         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 201           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 202         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 203           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 204         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 205           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 206         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 207           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 208         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 209           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 210         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 211           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 212         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 213           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 214         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 215           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 216         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 217           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 218         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 219           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 220         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 221           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 222         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 223           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 224         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
 225           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 226         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
 227           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 228         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
 229           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 230         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
 231           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 232         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
 233           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 234         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
 235           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 236         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
 237           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 238         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
 239           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 240         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
 241           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 242         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
 243           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 244         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 245           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 246         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 247           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 248         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 249           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 250         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 251           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 252         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 253           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 254         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 255           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 256         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 257           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 258         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 259           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 260         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 261           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 262         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 263           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 264         { 0, }
 265 };
 266
 267 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 268
 269 static struct {
 270         const char string[ETH_GSTRING_LEN];
 271 } ethtool_stats_keys[TG3_NUM_STATS] = {
 272         { "rx_octets" },
 273         { "rx_fragments" },
 274         { "rx_ucast_packets" },
 275         { "rx_mcast_packets" },
 276         { "rx_bcast_packets" },
 277         { "rx_fcs_errors" },
 278         { "rx_align_errors" },
 279         { "rx_xon_pause_rcvd" },
 280         { "rx_xoff_pause_rcvd" },
 281         { "rx_mac_ctrl_rcvd" },
 282         { "rx_xoff_entered" },
 283         { "rx_frame_too_long_errors" },
 284         { "rx_jabbers" },
 285         { "rx_undersize_packets" },
 286         { "rx_in_length_errors" },
 287         { "rx_out_length_errors" },
 288         { "rx_64_or_less_octet_packets" },
 289         { "rx_65_to_127_octet_packets" },
 290         { "rx_128_to_255_octet_packets" },
 291         { "rx_256_to_511_octet_packets" },
 292         { "rx_512_to_1023_octet_packets" },
 293         { "rx_1024_to_1522_octet_packets" },
 294         { "rx_1523_to_2047_octet_packets" },
 295         { "rx_2048_to_4095_octet_packets" },
 296         { "rx_4096_to_8191_octet_packets" },
 297         { "rx_8192_to_9022_octet_packets" },
 298
 299         { "tx_octets" },
 300         { "tx_collisions" },
 301
 302         { "tx_xon_sent" },
 303         { "tx_xoff_sent" },
 304         { "tx_flow_control" },
 305         { "tx_mac_errors" },
 306         { "tx_single_collisions" },
 307         { "tx_mult_collisions" },
 308         { "tx_deferred" },
 309         { "tx_excessive_collisions" },
 310         { "tx_late_collisions" },
 311         { "tx_collide_2times" },
 312         { "tx_collide_3times" },
 313         { "tx_collide_4times" },
 314         { "tx_collide_5times" },
 315         { "tx_collide_6times" },
 316         { "tx_collide_7times" },
 317         { "tx_collide_8times" },
 318         { "tx_collide_9times" },
 319         { "tx_collide_10times" },
 320         { "tx_collide_11times" },
 321         { "tx_collide_12times" },
 322         { "tx_collide_13times" },
 323         { "tx_collide_14times" },
 324         { "tx_collide_15times" },
 325         { "tx_ucast_packets" },
 326         { "tx_mcast_packets" },
 327         { "tx_bcast_packets" },
 328         { "tx_carrier_sense_errors" },
 329         { "tx_discards" },
 330         { "tx_errors" },
 331
 332         { "dma_writeq_full" },
 333         { "dma_write_prioq_full" },
 334         { "rxbds_empty" },
 335         { "rx_discards" },
 336         { "rx_errors" },
 337         { "rx_threshold_hit" },
 338
 339         { "dma_readq_full" },
 340         { "dma_read_prioq_full" },
 341         { "tx_comp_queue_full" },
 342
 343         { "ring_set_send_prod_index" },
 344         { "ring_status_update" },
 345         { "nic_irqs" },
 346         { "nic_avoided_irqs" },
 347         { "nic_tx_threshold_hit" }
 348 };
 349
 350 static struct {
 351         const char string[ETH_GSTRING_LEN];
 352 } ethtool_test_keys[TG3_NUM_TEST] = {
 353         { "nvram test     (online) " },
 354         { "link test      (online) " },
 355         { "register test  (offline)" },
 356         { "memory test    (offline)" },
 357         { "loopback test  (offline)" },
 358         { "interrupt test (offline)" },
 359 };
 360
 361 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364 }
 365
 366 static u32 tg3_read32(struct tg3 *tp, u32 off)
 367 {
 368         return (readl(tp->regs + off));
 369 }
 370
 371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 372 {
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&tp->indirect_lock, flags);
 376         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 378         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 379 }
 380
 381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384         readl(tp->regs + off);
 385 }
 386
 387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 388 {
 389         unsigned long flags;
 390         u32 val;
 391
 392         spin_lock_irqsave(&tp->indirect_lock, flags);
 393         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 394         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 395         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 396         return val;
 397 }
 398
 399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 405                                        TG3_64BIT_REG_LOW, val);
 406                 return;
 407         }
 408         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418
 419         /* In indirect mode when disabling interrupts, we also need
 420          * to clear the interrupt bit in the GRC local ctrl register.
 421          */
 422         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 423             (val == 0x1)) {
 424                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 425                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 426         }
 427 }
 428
 429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 430 {
 431         unsigned long flags;
 432         u32 val;
 433
 434         spin_lock_irqsave(&tp->indirect_lock, flags);
 435         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 436         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 437         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 438         return val;
 439 }
 440
 441 /* usec_wait specifies the wait time in usec when writing to certain registers
 442  * where it is unsafe to read back the register without some delay.
 443  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 444  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 445  */
 446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 447 {
 448         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 449             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 450                 /* Non-posted methods */
 451                 tp->write32(tp, off, val);
 452         else {
 453                 /* Posted method */
 454                 tg3_write32(tp, off, val);
 455                 if (usec_wait)
 456                         udelay(usec_wait);
 457                 tp->read32(tp, off);
 458         }
 459         /* Wait again after the read for the posted method to guarantee that
 460          * the wait time is met.
 461          */
 462         if (usec_wait)
 463                 udelay(usec_wait);
 464 }
 465
 466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 467 {
 468         tp->write32_mbox(tp, off, val);
 469         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 470             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 471                 tp->read32_mbox(tp, off);
 472 }
 473
 474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         void __iomem *mbox = tp->regs + off;
 477         writel(val, mbox);
 478         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 479                 writel(val, mbox);
 480         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 481                 readl(mbox);
 482 }
 483
 484 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 485 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 486 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 487 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 488 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 489
 490 #define tw32(reg,val)           tp->write32(tp, reg, val)
 491 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 493 #define tr32(reg)               tp->read32(tp, reg)
 494
 495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 496 {
 497         unsigned long flags;
 498
 499         spin_lock_irqsave(&tp->indirect_lock, flags);
 500         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 501                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         } else {
 507                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 508                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 509
 510                 /* Always leave this as zero. */
 511                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 512         }
 513         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 514 }
 515
 516 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 517 {
 518         unsigned long flags;
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_disable_ints(struct tg3 *tp)
 538 {
 539         tw32(TG3PCI_MISC_HOST_CTRL,
 540              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 541         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 542 }
 543
 544 static inline void tg3_cond_int(struct tg3 *tp)
 545 {
 546         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 547             (tp->hw_status->status & SD_STATUS_UPDATED))
 548                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 549 }
 550
 551 static void tg3_enable_ints(struct tg3 *tp)
 552 {
 553         tp->irq_sync = 0;
 554         wmb();
 555
 556         tw32(TG3PCI_MISC_HOST_CTRL,
 557              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 558         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 559                        (tp->last_tag << 24));
 560         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 561                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 562                                (tp->last_tag << 24));
 563         tg3_cond_int(tp);
 564 }
 565
 566 static inline unsigned int tg3_has_work(struct tg3 *tp)
 567 {
 568         struct tg3_hw_status *sblk = tp->hw_status;
 569         unsigned int work_exists = 0;
 570
 571         /* check for phy events */
 572         if (!(tp->tg3_flags &
 573               (TG3_FLAG_USE_LINKCHG_REG |
 574                TG3_FLAG_POLL_SERDES))) {
 575                 if (sblk->status & SD_STATUS_LINK_CHG)
 576                         work_exists = 1;
 577         }
 578         /* check for RX/TX work to do */
 579         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 580             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 581                 work_exists = 1;
 582
 583         return work_exists;
 584 }
 585
 586 /* tg3_restart_ints
 587  *  similar to tg3_enable_ints, but it accurately determines whether there
 588  *  is new work pending and can return without flushing the PIO write
 589  *  which reenables interrupts
 590  */
 591 static void tg3_restart_ints(struct tg3 *tp)
 592 {
 593         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 594                      tp->last_tag << 24);
 595         mmiowb();
 596
 597         /* When doing tagged status, this work check is unnecessary.
 598          * The last_tag we write above tells the chip which piece of
 599          * work we've completed.
 600          */
 601         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 602             tg3_has_work(tp))
 603                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 604                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 605 }
 606
 607 static inline void tg3_netif_stop(struct tg3 *tp)
 608 {
 609         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 610         netif_poll_disable(tp->dev);
 611         netif_tx_disable(tp->dev);
 612 }
 613
 614 static inline void tg3_netif_start(struct tg3 *tp)
 615 {
 616         netif_wake_queue(tp->dev);
 617         /* NOTE: unconditional netif_wake_queue is only appropriate
 618          * so long as all callers are assured to have free tx slots
 619          * (such as after tg3_init_hw)
 620          */
 621         netif_poll_enable(tp->dev);
 622         tp->hw_status->status |= SD_STATUS_UPDATED;
 623         tg3_enable_ints(tp);
 624 }
 625
 626 static void tg3_switch_clocks(struct tg3 *tp)
 627 {
 628         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 629         u32 orig_clock_ctrl;
 630
 631         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 632                 return;
 633
 634         orig_clock_ctrl = clock_ctrl;
 635         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 636                        CLOCK_CTRL_CLKRUN_OENABLE |
 637                        0x1f);
 638         tp->pci_clock_ctrl = clock_ctrl;
 639
 640         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 641                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 642                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 643                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 644                 }
 645         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 646                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 647                             clock_ctrl |
 648                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 649                             40);
 650                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 651                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 652                             40);
 653         }
 654         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 655 }
 656
 657 #define PHY_BUSY_LOOPS  5000
 658
 659 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 660 {
 661         u32 frame_val;
 662         unsigned int loops;
 663         int ret;
 664
 665         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 666                 tw32_f(MAC_MI_MODE,
 667                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 668                 udelay(80);
 669         }
 670
 671         *val = 0x0;
 672
 673         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 674                       MI_COM_PHY_ADDR_MASK);
 675         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 676                       MI_COM_REG_ADDR_MASK);
 677         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 678
 679         tw32_f(MAC_MI_COM, frame_val);
 680
 681         loops = PHY_BUSY_LOOPS;
 682         while (loops != 0) {
 683                 udelay(10);
 684                 frame_val = tr32(MAC_MI_COM);
 685
 686                 if ((frame_val & MI_COM_BUSY) == 0) {
 687                         udelay(5);
 688                         frame_val = tr32(MAC_MI_COM);
 689                         break;
 690                 }
 691                 loops -= 1;
 692         }
 693
 694         ret = -EBUSY;
 695         if (loops != 0) {
 696                 *val = frame_val & MI_COM_DATA_MASK;
 697                 ret = 0;
 698         }
 699
 700         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 701                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 702                 udelay(80);
 703         }
 704
 705         return ret;
 706 }
 707
 708 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 709 {
 710         u32 frame_val;
 711         unsigned int loops;
 712         int ret;
 713
 714         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 715                 tw32_f(MAC_MI_MODE,
 716                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 717                 udelay(80);
 718         }
 719
 720         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 721                       MI_COM_PHY_ADDR_MASK);
 722         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 723                       MI_COM_REG_ADDR_MASK);
 724         frame_val |= (val & MI_COM_DATA_MASK);
 725         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 726
 727         tw32_f(MAC_MI_COM, frame_val);
 728
 729         loops = PHY_BUSY_LOOPS;
 730         while (loops != 0) {
 731                 udelay(10);
 732                 frame_val = tr32(MAC_MI_COM);
 733                 if ((frame_val & MI_COM_BUSY) == 0) {
 734                         udelay(5);
 735                         frame_val = tr32(MAC_MI_COM);
 736                         break;
 737                 }
 738                 loops -= 1;
 739         }
 740
 741         ret = -EBUSY;
 742         if (loops != 0)
 743                 ret = 0;
 744
 745         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 746                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 747                 udelay(80);
 748         }
 749
 750         return ret;
 751 }
 752
 753 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 754 {
 755         u32 val;
 756
 757         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 758                 return;
 759
 760         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 761             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 762                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 763                              (val | (1 << 15) | (1 << 4)));
 764 }
 765
 766 static int tg3_bmcr_reset(struct tg3 *tp)
 767 {
 768         u32 phy_control;
 769         int limit, err;
 770
 771         /* OK, reset it, and poll the BMCR_RESET bit until it
 772          * clears or we time out.
 773          */
 774         phy_control = BMCR_RESET;
 775         err = tg3_writephy(tp, MII_BMCR, phy_control);
 776         if (err != 0)
 777                 return -EBUSY;
 778
 779         limit = 5000;
 780         while (limit--) {
 781                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 782                 if (err != 0)
 783                         return -EBUSY;
 784
 785                 if ((phy_control & BMCR_RESET) == 0) {
 786                         udelay(40);
 787                         break;
 788                 }
 789                 udelay(10);
 790         }
 791         if (limit <= 0)
 792                 return -EBUSY;
 793
 794         return 0;
 795 }
 796
 797 static int tg3_wait_macro_done(struct tg3 *tp)
 798 {
 799         int limit = 100;
 800
 801         while (limit--) {
 802                 u32 tmp32;
 803
 804                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 805                         if ((tmp32 & 0x1000) == 0)
 806                                 break;
 807                 }
 808         }
 809         if (limit <= 0)
 810                 return -EBUSY;
 811
 812         return 0;
 813 }
 814
 815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 816 {
 817         static const u32 test_pat[4][6] = {
 818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 822         };
 823         int chan;
 824
 825         for (chan = 0; chan < 4; chan++) {
 826                 int i;
 827
 828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 829                              (chan * 0x2000) | 0x0200);
 830                 tg3_writephy(tp, 0x16, 0x0002);
 831
 832                 for (i = 0; i < 6; i++)
 833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 834                                      test_pat[chan][i]);
 835
 836                 tg3_writephy(tp, 0x16, 0x0202);
 837                 if (tg3_wait_macro_done(tp)) {
 838                         *resetp = 1;
 839                         return -EBUSY;
 840                 }
 841
 842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 843                              (chan * 0x2000) | 0x0200);
 844                 tg3_writephy(tp, 0x16, 0x0082);
 845                 if (tg3_wait_macro_done(tp)) {
 846                         *resetp = 1;
 847                         return -EBUSY;
 848                 }
 849
 850                 tg3_writephy(tp, 0x16, 0x0802);
 851                 if (tg3_wait_macro_done(tp)) {
 852                         *resetp = 1;
 853                         return -EBUSY;
 854                 }
 855
 856                 for (i = 0; i < 6; i += 2) {
 857                         u32 low, high;
 858
 859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 861                             tg3_wait_macro_done(tp)) {
 862                                 *resetp = 1;
 863                                 return -EBUSY;
 864                         }
 865                         low &= 0x7fff;
 866                         high &= 0x000f;
 867                         if (low != test_pat[chan][i] ||
 868                             high != test_pat[chan][i+1]) {
 869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 872
 873                                 return -EBUSY;
 874                         }
 875                 }
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 882 {
 883         int chan;
 884
 885         for (chan = 0; chan < 4; chan++) {
 886                 int i;
 887
 888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 889                              (chan * 0x2000) | 0x0200);
 890                 tg3_writephy(tp, 0x16, 0x0002);
 891                 for (i = 0; i < 6; i++)
 892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 893                 tg3_writephy(tp, 0x16, 0x0202);
 894                 if (tg3_wait_macro_done(tp))
 895                         return -EBUSY;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 902 {
 903         u32 reg32, phy9_orig;
 904         int retries, do_phy_reset, err;
 905
 906         retries = 10;
 907         do_phy_reset = 1;
 908         do {
 909                 if (do_phy_reset) {
 910                         err = tg3_bmcr_reset(tp);
 911                         if (err)
 912                                 return err;
 913                         do_phy_reset = 0;
 914                 }
 915
 916                 /* Disable transmitter and interrupt.  */
 917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 918                         continue;
 919
 920                 reg32 |= 0x3000;
 921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 922
 923                 /* Set full-duplex, 1000 mbps.  */
 924                 tg3_writephy(tp, MII_BMCR,
 925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 926
 927                 /* Set to master mode.  */
 928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 929                         continue;
 930
 931                 tg3_writephy(tp, MII_TG3_CTRL,
 932                              (MII_TG3_CTRL_AS_MASTER |
 933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 934
 935                 /* Enable SM_DSP_CLOCK and 6dB.  */
 936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 937
 938                 /* Block the PHY control access.  */
 939                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 940                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 941
 942                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 943                 if (!err)
 944                         break;
 945         } while (--retries);
 946
 947         err = tg3_phy_reset_chanpat(tp);
 948         if (err)
 949                 return err;
 950
 951         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 952         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 953
 954         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 955         tg3_writephy(tp, 0x16, 0x0000);
 956
 957         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 958             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 959                 /* Set Extended packet length bit for jumbo frames */
 960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 961         }
 962         else {
 963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 964         }
 965
 966         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 967
 968         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 969                 reg32 &= ~0x3000;
 970                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 971         } else if (!err)
 972                 err = -EBUSY;
 973
 974         return err;
 975 }
 976
 977 static void tg3_link_report(struct tg3 *);
 978
 979 /* This will reset the tigon3 PHY if there is no valid
 980  * link unless the FORCE argument is non-zero.
 981  */
 982 static int tg3_phy_reset(struct tg3 *tp)
 983 {
 984         u32 phy_status;
 985         int err;
 986
 987         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 988         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 989         if (err != 0)
 990                 return -EBUSY;
 991
 992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 993                 netif_carrier_off(tp->dev);
 994                 tg3_link_report(tp);
 995         }
 996
 997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1000                 err = tg3_phy_reset_5703_4_5(tp);
1001                 if (err)
1002                         return err;
1003                 goto out;
1004         }
1005
1006         err = tg3_bmcr_reset(tp);
1007         if (err)
1008                 return err;
1009
1010 out:
1011         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1014                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1015                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1016                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1018         }
1019         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1020                 tg3_writephy(tp, 0x1c, 0x8d68);
1021                 tg3_writephy(tp, 0x1c, 0x8d68);
1022         }
1023         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1024                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1025                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1026                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1027                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1028                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1030                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1031                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1032         }
1033         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1038         }
1039         /* Set Extended packet length bit (bit 14) on all chips that */
1040         /* support jumbo frames */
1041         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1042                 /* Cannot do read-modify-write on 5401 */
1043                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1044         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1045                 u32 phy_reg;
1046
1047                 /* Set bit 14 with read-modify-write to preserve other bits */
1048                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1049                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1050                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1051         }
1052
1053         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1054          * jumbo frames transmission.
1055          */
1056         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1057                 u32 phy_reg;
1058
1059                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1060                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1061                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1062         }
1063
1064         tg3_phy_set_wirespeed(tp);
1065         return 0;
1066 }
1067
1068 static void tg3_frob_aux_power(struct tg3 *tp)
1069 {
1070         struct tg3 *tp_peer = tp;
1071
1072         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1073                 return;
1074
1075         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1076             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1077                 struct net_device *dev_peer;
1078
1079                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1080                 /* remove_one() may have been run on the peer. */
1081                 if (!dev_peer)
1082                         tp_peer = tp;
1083                 else
1084                         tp_peer = netdev_priv(dev_peer);
1085         }
1086
1087         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1088             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1089             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1091                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1092                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1093                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094                                     (GRC_LCLCTRL_GPIO_OE0 |
1095                                      GRC_LCLCTRL_GPIO_OE1 |
1096                                      GRC_LCLCTRL_GPIO_OE2 |
1097                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1099                                     100);
1100                 } else {
1101                         u32 no_gpio2;
1102                         u32 grc_local_ctrl = 0;
1103
1104                         if (tp_peer != tp &&
1105                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1106                                 return;
1107
1108                         /* Workaround to prevent overdrawing Amps. */
1109                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1110                             ASIC_REV_5714) {
1111                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1112                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1113                                             grc_local_ctrl, 100);
1114                         }
1115
1116                         /* On 5753 and variants, GPIO2 cannot be used. */
1117                         no_gpio2 = tp->nic_sram_data_cfg &
1118                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1119
1120                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1121                                          GRC_LCLCTRL_GPIO_OE1 |
1122                                          GRC_LCLCTRL_GPIO_OE2 |
1123                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1125                         if (no_gpio2) {
1126                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1127                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1128                         }
1129                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1130                                                     grc_local_ctrl, 100);
1131
1132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1133
1134                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1135                                                     grc_local_ctrl, 100);
1136
1137                         if (!no_gpio2) {
1138                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1139                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140                                             grc_local_ctrl, 100);
1141                         }
1142                 }
1143         } else {
1144                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1145                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1146                         if (tp_peer != tp &&
1147                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1148                                 return;
1149
1150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151                                     (GRC_LCLCTRL_GPIO_OE1 |
1152                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153
1154                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1155                                     GRC_LCLCTRL_GPIO_OE1, 100);
1156
1157                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1158                                     (GRC_LCLCTRL_GPIO_OE1 |
1159                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1160                 }
1161         }
1162 }
1163
1164 static int tg3_setup_phy(struct tg3 *, int);
1165
1166 #define RESET_KIND_SHUTDOWN     0
1167 #define RESET_KIND_INIT         1
1168 #define RESET_KIND_SUSPEND      2
1169
1170 static void tg3_write_sig_post_reset(struct tg3 *, int);
1171 static int tg3_halt_cpu(struct tg3 *, u32);
1172 static int tg3_nvram_lock(struct tg3 *);
1173 static void tg3_nvram_unlock(struct tg3 *);
1174
1175 static void tg3_power_down_phy(struct tg3 *tp)
1176 {
1177         /* The PHY should not be powered down on some chips because
1178          * of bugs.
1179          */
1180         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1181             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1182             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1183              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1184                 return;
1185         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1186 }
1187
1188 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1189 {
1190         u32 misc_host_ctrl;
1191         u16 power_control, power_caps;
1192         int pm = tp->pm_cap;
1193
1194         /* Make sure register accesses (indirect or otherwise)
1195          * will function correctly.
1196          */
1197         pci_write_config_dword(tp->pdev,
1198                                TG3PCI_MISC_HOST_CTRL,
1199                                tp->misc_host_ctrl);
1200
1201         pci_read_config_word(tp->pdev,
1202                              pm + PCI_PM_CTRL,
1203                              &power_control);
1204         power_control |= PCI_PM_CTRL_PME_STATUS;
1205         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1206         switch (state) {
1207         case PCI_D0:
1208                 power_control |= 0;
1209                 pci_write_config_word(tp->pdev,
1210                                       pm + PCI_PM_CTRL,
1211                                       power_control);
1212                 udelay(100);    /* Delay after power state change */
1213
1214                 /* Switch out of Vaux if it is not a LOM */
1215                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1216                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1217
1218                 return 0;
1219
1220         case PCI_D1:
1221                 power_control |= 1;
1222                 break;
1223
1224         case PCI_D2:
1225                 power_control |= 2;
1226                 break;
1227
1228         case PCI_D3hot:
1229                 power_control |= 3;
1230                 break;
1231
1232         default:
1233                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1234                        "requested.\n",
1235                        tp->dev->name, state);
1236                 return -EINVAL;
1237         };
1238
1239         power_control |= PCI_PM_CTRL_PME_ENABLE;
1240
1241         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1242         tw32(TG3PCI_MISC_HOST_CTRL,
1243              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1244
1245         if (tp->link_config.phy_is_low_power == 0) {
1246                 tp->link_config.phy_is_low_power = 1;
1247                 tp->link_config.orig_speed = tp->link_config.speed;
1248                 tp->link_config.orig_duplex = tp->link_config.duplex;
1249                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1250         }
1251
1252         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1253                 tp->link_config.speed = SPEED_10;
1254                 tp->link_config.duplex = DUPLEX_HALF;
1255                 tp->link_config.autoneg = AUTONEG_ENABLE;
1256                 tg3_setup_phy(tp, 0);
1257         }
1258
1259         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1260                 int i;
1261                 u32 val;
1262
1263                 for (i = 0; i < 200; i++) {
1264                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1265                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1266                                 break;
1267                         msleep(1);
1268                 }
1269         }
1270         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1271                                              WOL_DRV_STATE_SHUTDOWN |
1272                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1273
1274         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1275
1276         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1277                 u32 mac_mode;
1278
1279                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1280                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1281                         udelay(40);
1282
1283                         mac_mode = MAC_MODE_PORT_MODE_MII;
1284
1285                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1286                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1287                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1288                 } else {
1289                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1290                 }
1291
1292                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1293                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1294
1295                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1296                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1297                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1298
1299                 tw32_f(MAC_MODE, mac_mode);
1300                 udelay(100);
1301
1302                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1303                 udelay(10);
1304         }
1305
1306         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1307             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1308              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1309                 u32 base_val;
1310
1311                 base_val = tp->pci_clock_ctrl;
1312                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1313                              CLOCK_CTRL_TXCLK_DISABLE);
1314
1315                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1316                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1317         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1318                 /* do nothing */
1319         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1320                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1321                 u32 newbits1, newbits2;
1322
1323                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1324                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1325                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1326                                     CLOCK_CTRL_TXCLK_DISABLE |
1327                                     CLOCK_CTRL_ALTCLK);
1328                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1329                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1330                         newbits1 = CLOCK_CTRL_625_CORE;
1331                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1332                 } else {
1333                         newbits1 = CLOCK_CTRL_ALTCLK;
1334                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1335                 }
1336
1337                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1338                             40);
1339
1340                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1341                             40);
1342
1343                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1344                         u32 newbits3;
1345
1346                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1347                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1348                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1349                                             CLOCK_CTRL_TXCLK_DISABLE |
1350                                             CLOCK_CTRL_44MHZ_CORE);
1351                         } else {
1352                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1353                         }
1354
1355                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1356                                     tp->pci_clock_ctrl | newbits3, 40);
1357                 }
1358         }
1359
1360         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1361             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1362                 /* Turn off the PHY */
1363                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1364                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1365                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1366                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1367                         tg3_power_down_phy(tp);
1368                 }
1369         }
1370
1371         tg3_frob_aux_power(tp);
1372
1373         /* Workaround for unstable PLL clock */
1374         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1375             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1376                 u32 val = tr32(0x7d00);
1377
1378                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1379                 tw32(0x7d00, val);
1380                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1381                         int err;
1382
1383                         err = tg3_nvram_lock(tp);
1384                         tg3_halt_cpu(tp, RX_CPU_BASE);
1385                         if (!err)
1386                                 tg3_nvram_unlock(tp);
1387                 }
1388         }
1389
1390         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1391
1392         /* Finally, set the new power state. */
1393         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1394         udelay(100);    /* Delay after power state change */
1395
1396         return 0;
1397 }
1398
1399 static void tg3_link_report(struct tg3 *tp)
1400 {
1401         if (!netif_carrier_ok(tp->dev)) {
1402                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1403         } else {
1404                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1405                        tp->dev->name,
1406                        (tp->link_config.active_speed == SPEED_1000 ?
1407                         1000 :
1408                         (tp->link_config.active_speed == SPEED_100 ?
1409                          100 : 10)),
1410                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1411                         "full" : "half"));
1412
1413                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1414                        "%s for RX.\n",
1415                        tp->dev->name,
1416                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1417                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1418         }
1419 }
1420
1421 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1422 {
1423         u32 new_tg3_flags = 0;
1424         u32 old_rx_mode = tp->rx_mode;
1425         u32 old_tx_mode = tp->tx_mode;
1426
1427         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1428
1429                 /* Convert 1000BaseX flow control bits to 1000BaseT
1430                  * bits before resolving flow control.
1431                  */
1432                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1433                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1434                                        ADVERTISE_PAUSE_ASYM);
1435                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1436
1437                         if (local_adv & ADVERTISE_1000XPAUSE)
1438                                 local_adv |= ADVERTISE_PAUSE_CAP;
1439                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1440                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1441                         if (remote_adv & LPA_1000XPAUSE)
1442                                 remote_adv |= LPA_PAUSE_CAP;
1443                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1444                                 remote_adv |= LPA_PAUSE_ASYM;
1445                 }
1446
1447                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1448                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1449                                 if (remote_adv & LPA_PAUSE_CAP)
1450                                         new_tg3_flags |=
1451                                                 (TG3_FLAG_RX_PAUSE |
1452                                                 TG3_FLAG_TX_PAUSE);
1453                                 else if (remote_adv & LPA_PAUSE_ASYM)
1454                                         new_tg3_flags |=
1455                                                 (TG3_FLAG_RX_PAUSE);
1456                         } else {
1457                                 if (remote_adv & LPA_PAUSE_CAP)
1458                                         new_tg3_flags |=
1459                                                 (TG3_FLAG_RX_PAUSE |
1460                                                 TG3_FLAG_TX_PAUSE);
1461                         }
1462                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1463                         if ((remote_adv & LPA_PAUSE_CAP) &&
1464                         (remote_adv & LPA_PAUSE_ASYM))
1465                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1466                 }
1467
1468                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1469                 tp->tg3_flags |= new_tg3_flags;
1470         } else {
1471                 new_tg3_flags = tp->tg3_flags;
1472         }
1473
1474         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1475                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1476         else
1477                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1478
1479         if (old_rx_mode != tp->rx_mode) {
1480                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1481         }
1482
1483         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1484                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1485         else
1486                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1487
1488         if (old_tx_mode != tp->tx_mode) {
1489                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1490         }
1491 }
1492
1493 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1494 {
1495         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1496         case MII_TG3_AUX_STAT_10HALF:
1497                 *speed = SPEED_10;
1498                 *duplex = DUPLEX_HALF;
1499                 break;
1500
1501         case MII_TG3_AUX_STAT_10FULL:
1502                 *speed = SPEED_10;
1503                 *duplex = DUPLEX_FULL;
1504                 break;
1505
1506         case MII_TG3_AUX_STAT_100HALF:
1507                 *speed = SPEED_100;
1508                 *duplex = DUPLEX_HALF;
1509                 break;
1510
1511         case MII_TG3_AUX_STAT_100FULL:
1512                 *speed = SPEED_100;
1513                 *duplex = DUPLEX_FULL;
1514                 break;
1515
1516         case MII_TG3_AUX_STAT_1000HALF:
1517                 *speed = SPEED_1000;
1518                 *duplex = DUPLEX_HALF;
1519                 break;
1520
1521         case MII_TG3_AUX_STAT_1000FULL:
1522                 *speed = SPEED_1000;
1523                 *duplex = DUPLEX_FULL;
1524                 break;
1525
1526         default:
1527                 *speed = SPEED_INVALID;
1528                 *duplex = DUPLEX_INVALID;
1529                 break;
1530         };
1531 }
1532
1533 static void tg3_phy_copper_begin(struct tg3 *tp)
1534 {
1535         u32 new_adv;
1536         int i;
1537
1538         if (tp->link_config.phy_is_low_power) {
1539                 /* Entering low power mode.  Disable gigabit and
1540                  * 100baseT advertisements.
1541                  */
1542                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1543
1544                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1545                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1546                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1547                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1548
1549                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1550         } else if (tp->link_config.speed == SPEED_INVALID) {
1551                 tp->link_config.advertising =
1552                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1553                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1554                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1555                          ADVERTISED_Autoneg | ADVERTISED_MII);
1556
1557                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1558                         tp->link_config.advertising &=
1559                                 ~(ADVERTISED_1000baseT_Half |
1560                                   ADVERTISED_1000baseT_Full);
1561
1562                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1563                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1564                         new_adv |= ADVERTISE_10HALF;
1565                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1566                         new_adv |= ADVERTISE_10FULL;
1567                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1568                         new_adv |= ADVERTISE_100HALF;
1569                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1570                         new_adv |= ADVERTISE_100FULL;
1571                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1572
1573                 if (tp->link_config.advertising &
1574                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1575                         new_adv = 0;
1576                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1577                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1578                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1579                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1580                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1581                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1582                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1583                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1584                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1585                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1586                 } else {
1587                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1588                 }
1589         } else {
1590                 /* Asking for a specific link mode. */
1591                 if (tp->link_config.speed == SPEED_1000) {
1592                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1593                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1594
1595                         if (tp->link_config.duplex == DUPLEX_FULL)
1596                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1597                         else
1598                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1599                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1600                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1601                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1602                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1603                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1604                 } else {
1605                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1606
1607                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1608                         if (tp->link_config.speed == SPEED_100) {
1609                                 if (tp->link_config.duplex == DUPLEX_FULL)
1610                                         new_adv |= ADVERTISE_100FULL;
1611                                 else
1612                                         new_adv |= ADVERTISE_100HALF;
1613                         } else {
1614                                 if (tp->link_config.duplex == DUPLEX_FULL)
1615                                         new_adv |= ADVERTISE_10FULL;
1616                                 else
1617                                         new_adv |= ADVERTISE_10HALF;
1618                         }
1619                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1620                 }
1621         }
1622
1623         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1624             tp->link_config.speed != SPEED_INVALID) {
1625                 u32 bmcr, orig_bmcr;
1626
1627                 tp->link_config.active_speed = tp->link_config.speed;
1628                 tp->link_config.active_duplex = tp->link_config.duplex;
1629
1630                 bmcr = 0;
1631                 switch (tp->link_config.speed) {
1632                 default:
1633                 case SPEED_10:
1634                         break;
1635
1636                 case SPEED_100:
1637                         bmcr |= BMCR_SPEED100;
1638                         break;
1639
1640                 case SPEED_1000:
1641                         bmcr |= TG3_BMCR_SPEED1000;
1642                         break;
1643                 };
1644
1645                 if (tp->link_config.duplex == DUPLEX_FULL)
1646                         bmcr |= BMCR_FULLDPLX;
1647
1648                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1649                     (bmcr != orig_bmcr)) {
1650                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1651                         for (i = 0; i < 1500; i++) {
1652                                 u32 tmp;
1653
1654                                 udelay(10);
1655                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1656                                     tg3_readphy(tp, MII_BMSR, &tmp))
1657                                         continue;
1658                                 if (!(tmp & BMSR_LSTATUS)) {
1659                                         udelay(40);
1660                                         break;
1661                                 }
1662                         }
1663                         tg3_writephy(tp, MII_BMCR, bmcr);
1664                         udelay(40);
1665                 }
1666         } else {
1667                 tg3_writephy(tp, MII_BMCR,
1668                              BMCR_ANENABLE | BMCR_ANRESTART);
1669         }
1670 }
1671
1672 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1673 {
1674         int err;
1675
1676         /* Turn off tap power management. */
1677         /* Set Extended packet length bit */
1678         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1679
1680         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1681         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1682
1683         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1684         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1685
1686         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1687         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1688
1689         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1690         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1691
1692         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1693         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1694
1695         udelay(40);
1696
1697         return err;
1698 }
1699
1700 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1701 {
1702         u32 adv_reg, all_mask;
1703
1704         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1705                 return 0;
1706
1707         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1708                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1709         if ((adv_reg & all_mask) != all_mask)
1710                 return 0;
1711         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1712                 u32 tg3_ctrl;
1713
1714                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1715                         return 0;
1716
1717                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1718                             MII_TG3_CTRL_ADV_1000_FULL);
1719                 if ((tg3_ctrl & all_mask) != all_mask)
1720                         return 0;
1721         }
1722         return 1;
1723 }
1724
1725 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1726 {
1727         int current_link_up;
1728         u32 bmsr, dummy;
1729         u16 current_speed;
1730         u8 current_duplex;
1731         int i, err;
1732
1733         tw32(MAC_EVENT, 0);
1734
1735         tw32_f(MAC_STATUS,
1736              (MAC_STATUS_SYNC_CHANGED |
1737               MAC_STATUS_CFG_CHANGED |
1738               MAC_STATUS_MI_COMPLETION |
1739               MAC_STATUS_LNKSTATE_CHANGED));
1740         udelay(40);
1741
1742         tp->mi_mode = MAC_MI_MODE_BASE;
1743         tw32_f(MAC_MI_MODE, tp->mi_mode);
1744         udelay(80);
1745
1746         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1747
1748         /* Some third-party PHYs need to be reset on link going
1749          * down.
1750          */
1751         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1752              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1753              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1754             netif_carrier_ok(tp->dev)) {
1755                 tg3_readphy(tp, MII_BMSR, &bmsr);
1756                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1757                     !(bmsr & BMSR_LSTATUS))
1758                         force_reset = 1;
1759         }
1760         if (force_reset)
1761                 tg3_phy_reset(tp);
1762
1763         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1764                 tg3_readphy(tp, MII_BMSR, &bmsr);
1765                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1766                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1767                         bmsr = 0;
1768
1769                 if (!(bmsr & BMSR_LSTATUS)) {
1770                         err = tg3_init_5401phy_dsp(tp);
1771                         if (err)
1772                                 return err;
1773
1774                         tg3_readphy(tp, MII_BMSR, &bmsr);
1775                         for (i = 0; i < 1000; i++) {
1776                                 udelay(10);
1777                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1778                                     (bmsr & BMSR_LSTATUS)) {
1779                                         udelay(40);
1780                                         break;
1781                                 }
1782                         }
1783
1784                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1785                             !(bmsr & BMSR_LSTATUS) &&
1786                             tp->link_config.active_speed == SPEED_1000) {
1787                                 err = tg3_phy_reset(tp);
1788                                 if (!err)
1789                                         err = tg3_init_5401phy_dsp(tp);
1790                                 if (err)
1791                                         return err;
1792                         }
1793                 }
1794         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1795                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1796                 /* 5701 {A0,B0} CRC bug workaround */
1797                 tg3_writephy(tp, 0x15, 0x0a75);
1798                 tg3_writephy(tp, 0x1c, 0x8c68);
1799                 tg3_writephy(tp, 0x1c, 0x8d68);
1800                 tg3_writephy(tp, 0x1c, 0x8c68);
1801         }
1802
1803         /* Clear pending interrupts... */
1804         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1805         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1806
1807         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1808                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1809         else
1810                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1811
1812         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1814                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1815                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1816                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1817                 else
1818                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1819         }
1820
1821         current_link_up = 0;
1822         current_speed = SPEED_INVALID;
1823         current_duplex = DUPLEX_INVALID;
1824
1825         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1826                 u32 val;
1827
1828                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1829                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1830                 if (!(val & (1 << 10))) {
1831                         val |= (1 << 10);
1832                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1833                         goto relink;
1834                 }
1835         }
1836
1837         bmsr = 0;
1838         for (i = 0; i < 100; i++) {
1839                 tg3_readphy(tp, MII_BMSR, &bmsr);
1840                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1841                     (bmsr & BMSR_LSTATUS))
1842                         break;
1843                 udelay(40);
1844         }
1845
1846         if (bmsr & BMSR_LSTATUS) {
1847                 u32 aux_stat, bmcr;
1848
1849                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1850                 for (i = 0; i < 2000; i++) {
1851                         udelay(10);
1852                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1853                             aux_stat)
1854                                 break;
1855                 }
1856
1857                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1858                                              &current_speed,
1859                                              &current_duplex);
1860
1861                 bmcr = 0;
1862                 for (i = 0; i < 200; i++) {
1863                         tg3_readphy(tp, MII_BMCR, &bmcr);
1864                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1865                                 continue;
1866                         if (bmcr && bmcr != 0x7fff)
1867                                 break;
1868                         udelay(10);
1869                 }
1870
1871                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1872                         if (bmcr & BMCR_ANENABLE) {
1873                                 current_link_up = 1;
1874
1875                                 /* Force autoneg restart if we are exiting
1876                                  * low power mode.
1877                                  */
1878                                 if (!tg3_copper_is_advertising_all(tp))
1879                                         current_link_up = 0;
1880                         } else {
1881                                 current_link_up = 0;
1882                         }
1883                 } else {
1884                         if (!(bmcr & BMCR_ANENABLE) &&
1885                             tp->link_config.speed == current_speed &&
1886                             tp->link_config.duplex == current_duplex) {
1887                                 current_link_up = 1;
1888                         } else {
1889                                 current_link_up = 0;
1890                         }
1891                 }
1892
1893                 tp->link_config.active_speed = current_speed;
1894                 tp->link_config.active_duplex = current_duplex;
1895         }
1896
1897         if (current_link_up == 1 &&
1898             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1899             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1900                 u32 local_adv, remote_adv;
1901
1902                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1903                         local_adv = 0;
1904                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1905
1906                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1907                         remote_adv = 0;
1908
1909                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1910
1911                 /* If we are not advertising full pause capability,
1912                  * something is wrong.  Bring the link down and reconfigure.
1913                  */
1914                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1915                         current_link_up = 0;
1916                 } else {
1917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1918                 }
1919         }
1920 relink:
1921         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1922                 u32 tmp;
1923
1924                 tg3_phy_copper_begin(tp);
1925
1926                 tg3_readphy(tp, MII_BMSR, &tmp);
1927                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1928                     (tmp & BMSR_LSTATUS))
1929                         current_link_up = 1;
1930         }
1931
1932         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1933         if (current_link_up == 1) {
1934                 if (tp->link_config.active_speed == SPEED_100 ||
1935                     tp->link_config.active_speed == SPEED_10)
1936                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1937                 else
1938                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1939         } else
1940                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1941
1942         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1943         if (tp->link_config.active_duplex == DUPLEX_HALF)
1944                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1945
1946         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1948                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1949                     (current_link_up == 1 &&
1950                      tp->link_config.active_speed == SPEED_10))
1951                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1952         } else {
1953                 if (current_link_up == 1)
1954                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1955         }
1956
1957         /* ??? Without this setting Netgear GA302T PHY does not
1958          * ??? send/receive packets...
1959          */
1960         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1961             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1962                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1963                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1964                 udelay(80);
1965         }
1966
1967         tw32_f(MAC_MODE, tp->mac_mode);
1968         udelay(40);
1969
1970         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1971                 /* Polled via timer. */
1972                 tw32_f(MAC_EVENT, 0);
1973         } else {
1974                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1975         }
1976         udelay(40);
1977
1978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1979             current_link_up == 1 &&
1980             tp->link_config.active_speed == SPEED_1000 &&
1981             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1982              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1983                 udelay(120);
1984                 tw32_f(MAC_STATUS,
1985                      (MAC_STATUS_SYNC_CHANGED |
1986                       MAC_STATUS_CFG_CHANGED));
1987                 udelay(40);
1988                 tg3_write_mem(tp,
1989                               NIC_SRAM_FIRMWARE_MBOX,
1990                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1991         }
1992
1993         if (current_link_up != netif_carrier_ok(tp->dev)) {
1994                 if (current_link_up)
1995                         netif_carrier_on(tp->dev);
1996                 else
1997                         netif_carrier_off(tp->dev);
1998                 tg3_link_report(tp);
1999         }
2000
2001         return 0;
2002 }
2003
2004 struct tg3_fiber_aneginfo {
2005         int state;
2006 #define ANEG_STATE_UNKNOWN              0
2007 #define ANEG_STATE_AN_ENABLE            1
2008 #define ANEG_STATE_RESTART_INIT         2
2009 #define ANEG_STATE_RESTART              3
2010 #define ANEG_STATE_DISABLE_LINK_OK      4
2011 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2012 #define ANEG_STATE_ABILITY_DETECT       6
2013 #define ANEG_STATE_ACK_DETECT_INIT      7
2014 #define ANEG_STATE_ACK_DETECT           8
2015 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2016 #define ANEG_STATE_COMPLETE_ACK         10
2017 #define ANEG_STATE_IDLE_DETECT_INIT     11
2018 #define ANEG_STATE_IDLE_DETECT          12
2019 #define ANEG_STATE_LINK_OK              13
2020 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2021 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2022
2023         u32 flags;
2024 #define MR_AN_ENABLE            0x00000001
2025 #define MR_RESTART_AN           0x00000002
2026 #define MR_AN_COMPLETE          0x00000004
2027 #define MR_PAGE_RX              0x00000008
2028 #define MR_NP_LOADED            0x00000010
2029 #define MR_TOGGLE_TX            0x00000020
2030 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2031 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2032 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2033 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2034 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2035 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2036 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2037 #define MR_TOGGLE_RX            0x00002000
2038 #define MR_NP_RX                0x00004000
2039
2040 #define MR_LINK_OK              0x80000000
2041
2042         unsigned long link_time, cur_time;
2043
2044         u32 ability_match_cfg;
2045         int ability_match_count;
2046
2047         char ability_match, idle_match, ack_match;
2048
2049         u32 txconfig, rxconfig;
2050 #define ANEG_CFG_NP             0x00000080
2051 #define ANEG_CFG_ACK            0x00000040
2052 #define ANEG_CFG_RF2            0x00000020
2053 #define ANEG_CFG_RF1            0x00000010
2054 #define ANEG_CFG_PS2            0x00000001
2055 #define ANEG_CFG_PS1            0x00008000
2056 #define ANEG_CFG_HD             0x00004000
2057 #define ANEG_CFG_FD             0x00002000
2058 #define ANEG_CFG_INVAL          0x00001f06
2059
2060 };
2061 #define ANEG_OK         0
2062 #define ANEG_DONE       1
2063 #define ANEG_TIMER_ENAB 2
2064 #define ANEG_FAILED     -1
2065
2066 #define ANEG_STATE_SETTLE_TIME  10000
2067
2068 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2069                                    struct tg3_fiber_aneginfo *ap)
2070 {
2071         unsigned long delta;
2072         u32 rx_cfg_reg;
2073         int ret;
2074
2075         if (ap->state == ANEG_STATE_UNKNOWN) {
2076                 ap->rxconfig = 0;
2077                 ap->link_time = 0;
2078                 ap->cur_time = 0;
2079                 ap->ability_match_cfg = 0;
2080                 ap->ability_match_count = 0;
2081                 ap->ability_match = 0;
2082                 ap->idle_match = 0;
2083                 ap->ack_match = 0;
2084         }
2085         ap->cur_time++;
2086
2087         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2088                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2089
2090                 if (rx_cfg_reg != ap->ability_match_cfg) {
2091                         ap->ability_match_cfg = rx_cfg_reg;
2092                         ap->ability_match = 0;
2093                         ap->ability_match_count = 0;
2094                 } else {
2095                         if (++ap->ability_match_count > 1) {
2096                                 ap->ability_match = 1;
2097                                 ap->ability_match_cfg = rx_cfg_reg;
2098                         }
2099                 }
2100                 if (rx_cfg_reg & ANEG_CFG_ACK)
2101                         ap->ack_match = 1;
2102                 else
2103                         ap->ack_match = 0;
2104
2105                 ap->idle_match = 0;
2106         } else {
2107                 ap->idle_match = 1;
2108                 ap->ability_match_cfg = 0;
2109                 ap->ability_match_count = 0;
2110                 ap->ability_match = 0;
2111                 ap->ack_match = 0;
2112
2113                 rx_cfg_reg = 0;
2114         }
2115
2116         ap->rxconfig = rx_cfg_reg;
2117         ret = ANEG_OK;
2118
2119         switch(ap->state) {
2120         case ANEG_STATE_UNKNOWN:
2121                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2122                         ap->state = ANEG_STATE_AN_ENABLE;
2123
2124                 /* fallthru */
2125         case ANEG_STATE_AN_ENABLE:
2126                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2127                 if (ap->flags & MR_AN_ENABLE) {
2128                         ap->link_time = 0;
2129                         ap->cur_time = 0;
2130                         ap->ability_match_cfg = 0;
2131                         ap->ability_match_count = 0;
2132                         ap->ability_match = 0;
2133                         ap->idle_match = 0;
2134                         ap->ack_match = 0;
2135
2136                         ap->state = ANEG_STATE_RESTART_INIT;
2137                 } else {
2138                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2139                 }
2140                 break;
2141
2142         case ANEG_STATE_RESTART_INIT:
2143                 ap->link_time = ap->cur_time;
2144                 ap->flags &= ~(MR_NP_LOADED);
2145                 ap->txconfig = 0;
2146                 tw32(MAC_TX_AUTO_NEG, 0);
2147                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2148                 tw32_f(MAC_MODE, tp->mac_mode);
2149                 udelay(40);
2150
2151                 ret = ANEG_TIMER_ENAB;
2152                 ap->state = ANEG_STATE_RESTART;
2153
2154                 /* fallthru */
2155         case ANEG_STATE_RESTART:
2156                 delta = ap->cur_time - ap->link_time;
2157                 if (delta > ANEG_STATE_SETTLE_TIME) {
2158                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2159                 } else {
2160                         ret = ANEG_TIMER_ENAB;
2161                 }
2162                 break;
2163
2164         case ANEG_STATE_DISABLE_LINK_OK:
2165                 ret = ANEG_DONE;
2166                 break;
2167
2168         case ANEG_STATE_ABILITY_DETECT_INIT:
2169                 ap->flags &= ~(MR_TOGGLE_TX);
2170                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2171                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2172                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2173                 tw32_f(MAC_MODE, tp->mac_mode);
2174                 udelay(40);
2175
2176                 ap->state = ANEG_STATE_ABILITY_DETECT;
2177                 break;
2178
2179         case ANEG_STATE_ABILITY_DETECT:
2180                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2181                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2182                 }
2183                 break;
2184
2185         case ANEG_STATE_ACK_DETECT_INIT:
2186                 ap->txconfig |= ANEG_CFG_ACK;
2187                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2188                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2189                 tw32_f(MAC_MODE, tp->mac_mode);
2190                 udelay(40);
2191
2192                 ap->state = ANEG_STATE_ACK_DETECT;
2193
2194                 /* fallthru */
2195         case ANEG_STATE_ACK_DETECT:
2196                 if (ap->ack_match != 0) {
2197                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2198                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2199                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2200                         } else {
2201                                 ap->state = ANEG_STATE_AN_ENABLE;
2202                         }
2203                 } else if (ap->ability_match != 0 &&
2204                            ap->rxconfig == 0) {
2205                         ap->state = ANEG_STATE_AN_ENABLE;
2206                 }
2207                 break;
2208
2209         case ANEG_STATE_COMPLETE_ACK_INIT:
2210                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2211                         ret = ANEG_FAILED;
2212                         break;
2213                 }
2214                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2215                                MR_LP_ADV_HALF_DUPLEX |
2216                                MR_LP_ADV_SYM_PAUSE |
2217                                MR_LP_ADV_ASYM_PAUSE |
2218                                MR_LP_ADV_REMOTE_FAULT1 |
2219                                MR_LP_ADV_REMOTE_FAULT2 |
2220                                MR_LP_ADV_NEXT_PAGE |
2221                                MR_TOGGLE_RX |
2222                                MR_NP_RX);
2223                 if (ap->rxconfig & ANEG_CFG_FD)
2224                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2225                 if (ap->rxconfig & ANEG_CFG_HD)
2226                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2227                 if (ap->rxconfig & ANEG_CFG_PS1)
2228                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2229                 if (ap->rxconfig & ANEG_CFG_PS2)
2230                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2231                 if (ap->rxconfig & ANEG_CFG_RF1)
2232                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2233                 if (ap->rxconfig & ANEG_CFG_RF2)
2234                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2235                 if (ap->rxconfig & ANEG_CFG_NP)
2236                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2237
2238                 ap->link_time = ap->cur_time;
2239
2240                 ap->flags ^= (MR_TOGGLE_TX);
2241                 if (ap->rxconfig & 0x0008)
2242                         ap->flags |= MR_TOGGLE_RX;
2243                 if (ap->rxconfig & ANEG_CFG_NP)
2244                         ap->flags |= MR_NP_RX;
2245                 ap->flags |= MR_PAGE_RX;
2246
2247                 ap->state = ANEG_STATE_COMPLETE_ACK;
2248                 ret = ANEG_TIMER_ENAB;
2249                 break;
2250
2251         case ANEG_STATE_COMPLETE_ACK:
2252                 if (ap->ability_match != 0 &&
2253                     ap->rxconfig == 0) {
2254                         ap->state = ANEG_STATE_AN_ENABLE;
2255                         break;
2256                 }
2257                 delta = ap->cur_time - ap->link_time;
2258                 if (delta > ANEG_STATE_SETTLE_TIME) {
2259                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2260                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2261                         } else {
2262                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2263                                     !(ap->flags & MR_NP_RX)) {
2264                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2265                                 } else {
2266                                         ret = ANEG_FAILED;
2267                                 }
2268                         }
2269                 }
2270                 break;
2271
2272         case ANEG_STATE_IDLE_DETECT_INIT:
2273                 ap->link_time = ap->cur_time;
2274                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2275                 tw32_f(MAC_MODE, tp->mac_mode);
2276                 udelay(40);
2277
2278                 ap->state = ANEG_STATE_IDLE_DETECT;
2279                 ret = ANEG_TIMER_ENAB;
2280                 break;
2281
2282         case ANEG_STATE_IDLE_DETECT:
2283                 if (ap->ability_match != 0 &&
2284                     ap->rxconfig == 0) {
2285                         ap->state = ANEG_STATE_AN_ENABLE;
2286                         break;
2287                 }
2288                 delta = ap->cur_time - ap->link_time;
2289                 if (delta > ANEG_STATE_SETTLE_TIME) {
2290                         /* XXX another gem from the Broadcom driver :( */
2291                         ap->state = ANEG_STATE_LINK_OK;
2292                 }
2293                 break;
2294
2295         case ANEG_STATE_LINK_OK:
2296                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2297                 ret = ANEG_DONE;
2298                 break;
2299
2300         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2301                 /* ??? unimplemented */
2302                 break;
2303
2304         case ANEG_STATE_NEXT_PAGE_WAIT:
2305                 /* ??? unimplemented */
2306                 break;
2307
2308         default:
2309                 ret = ANEG_FAILED;
2310                 break;
2311         };
2312
2313         return ret;
2314 }
2315
2316 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2317 {
2318         int res = 0;
2319         struct tg3_fiber_aneginfo aninfo;
2320         int status = ANEG_FAILED;
2321         unsigned int tick;
2322         u32 tmp;
2323
2324         tw32_f(MAC_TX_AUTO_NEG, 0);
2325
2326         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2327         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2328         udelay(40);
2329
2330         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2331         udelay(40);
2332
2333         memset(&aninfo, 0, sizeof(aninfo));
2334         aninfo.flags |= MR_AN_ENABLE;
2335         aninfo.state = ANEG_STATE_UNKNOWN;
2336         aninfo.cur_time = 0;
2337         tick = 0;
2338         while (++tick < 195000) {
2339                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2340                 if (status == ANEG_DONE || status == ANEG_FAILED)
2341                         break;
2342
2343                 udelay(1);
2344         }
2345
2346         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2347         tw32_f(MAC_MODE, tp->mac_mode);
2348         udelay(40);
2349
2350         *flags = aninfo.flags;
2351
2352         if (status == ANEG_DONE &&
2353             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2354                              MR_LP_ADV_FULL_DUPLEX)))
2355                 res = 1;
2356
2357         return res;
2358 }
2359
2360 static void tg3_init_bcm8002(struct tg3 *tp)
2361 {
2362         u32 mac_status = tr32(MAC_STATUS);
2363         int i;
2364
2365         /* Reset when initting first time or we have a link. */
2366         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2367             !(mac_status & MAC_STATUS_PCS_SYNCED))
2368                 return;
2369
2370         /* Set PLL lock range. */
2371         tg3_writephy(tp, 0x16, 0x8007);
2372
2373         /* SW reset */
2374         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2375
2376         /* Wait for reset to complete. */
2377         /* XXX schedule_timeout() ... */
2378         for (i = 0; i < 500; i++)
2379                 udelay(10);
2380
2381         /* Config mode; select PMA/Ch 1 regs. */
2382         tg3_writephy(tp, 0x10, 0x8411);
2383
2384         /* Enable auto-lock and comdet, select txclk for tx. */
2385         tg3_writephy(tp, 0x11, 0x0a10);
2386
2387         tg3_writephy(tp, 0x18, 0x00a0);
2388         tg3_writephy(tp, 0x16, 0x41ff);
2389
2390         /* Assert and deassert POR. */
2391         tg3_writephy(tp, 0x13, 0x0400);
2392         udelay(40);
2393         tg3_writephy(tp, 0x13, 0x0000);
2394
2395         tg3_writephy(tp, 0x11, 0x0a50);
2396         udelay(40);
2397         tg3_writephy(tp, 0x11, 0x0a10);
2398
2399         /* Wait for signal to stabilize */
2400         /* XXX schedule_timeout() ... */
2401         for (i = 0; i < 15000; i++)
2402                 udelay(10);
2403
2404         /* Deselect the channel register so we can read the PHYID
2405          * later.
2406          */
2407         tg3_writephy(tp, 0x10, 0x8011);
2408 }
2409
2410 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2411 {
2412         u32 sg_dig_ctrl, sg_dig_status;
2413         u32 serdes_cfg, expected_sg_dig_ctrl;
2414         int workaround, port_a;
2415         int current_link_up;
2416
2417         serdes_cfg = 0;
2418         expected_sg_dig_ctrl = 0;
2419         workaround = 0;
2420         port_a = 1;
2421         current_link_up = 0;
2422
2423         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2424             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2425                 workaround = 1;
2426                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2427                         port_a = 0;
2428
2429                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2430                 /* preserve bits 20-23 for voltage regulator */
2431                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2432         }
2433
2434         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2435
2436         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2437                 if (sg_dig_ctrl & (1 << 31)) {
2438                         if (workaround) {
2439                                 u32 val = serdes_cfg;
2440
2441                                 if (port_a)
2442                                         val |= 0xc010000;
2443                                 else
2444                                         val |= 0x4010000;
2445                                 tw32_f(MAC_SERDES_CFG, val);
2446                         }
2447                         tw32_f(SG_DIG_CTRL, 0x01388400);
2448                 }
2449                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2450                         tg3_setup_flow_control(tp, 0, 0);
2451                         current_link_up = 1;
2452                 }
2453                 goto out;
2454         }
2455
2456         /* Want auto-negotiation.  */
2457         expected_sg_dig_ctrl = 0x81388400;
2458
2459         /* Pause capability */
2460         expected_sg_dig_ctrl |= (1 << 11);
2461
2462         /* Asymettric pause */
2463         expected_sg_dig_ctrl |= (1 << 12);
2464
2465         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2466                 if (workaround)
2467                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2468                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2469                 udelay(5);
2470                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2471
2472                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2473         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2474                                  MAC_STATUS_SIGNAL_DET)) {
2475                 int i;
2476
2477                 /* Giver time to negotiate (~200ms) */
2478                 for (i = 0; i < 40000; i++) {
2479                         sg_dig_status = tr32(SG_DIG_STATUS);
2480                         if (sg_dig_status & (0x3))
2481                                 break;
2482                         udelay(5);
2483                 }
2484                 mac_status = tr32(MAC_STATUS);
2485
2486                 if ((sg_dig_status & (1 << 1)) &&
2487                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2488                         u32 local_adv, remote_adv;
2489
2490                         local_adv = ADVERTISE_PAUSE_CAP;
2491                         remote_adv = 0;
2492                         if (sg_dig_status & (1 << 19))
2493                                 remote_adv |= LPA_PAUSE_CAP;
2494                         if (sg_dig_status & (1 << 20))
2495                                 remote_adv |= LPA_PAUSE_ASYM;
2496
2497                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2498                         current_link_up = 1;
2499                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2500                 } else if (!(sg_dig_status & (1 << 1))) {
2501                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2502                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2503                         else {
2504                                 if (workaround) {
2505                                         u32 val = serdes_cfg;
2506
2507                                         if (port_a)
2508                                                 val |= 0xc010000;
2509                                         else
2510                                                 val |= 0x4010000;
2511
2512                                         tw32_f(MAC_SERDES_CFG, val);
2513                                 }
2514
2515                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2516                                 udelay(40);
2517
2518                                 /* Link parallel detection - link is up */
2519                                 /* only if we have PCS_SYNC and not */
2520                                 /* receiving config code words */
2521                                 mac_status = tr32(MAC_STATUS);
2522                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2523                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2524                                         tg3_setup_flow_control(tp, 0, 0);
2525                                         current_link_up = 1;
2526                                 }
2527                         }
2528                 }
2529         }
2530
2531 out:
2532         return current_link_up;
2533 }
2534
2535 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2536 {
2537         int current_link_up = 0;
2538
2539         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2540                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2541                 goto out;
2542         }
2543
2544         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2545                 u32 flags;
2546                 int i;
2547
2548                 if (fiber_autoneg(tp, &flags)) {
2549                         u32 local_adv, remote_adv;
2550
2551                         local_adv = ADVERTISE_PAUSE_CAP;
2552                         remote_adv = 0;
2553                         if (flags & MR_LP_ADV_SYM_PAUSE)
2554                                 remote_adv |= LPA_PAUSE_CAP;
2555                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2556                                 remote_adv |= LPA_PAUSE_ASYM;
2557
2558                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2559
2560                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2561                         current_link_up = 1;
2562                 }
2563                 for (i = 0; i < 30; i++) {
2564                         udelay(20);
2565                         tw32_f(MAC_STATUS,
2566                                (MAC_STATUS_SYNC_CHANGED |
2567                                 MAC_STATUS_CFG_CHANGED));
2568                         udelay(40);
2569                         if ((tr32(MAC_STATUS) &
2570                              (MAC_STATUS_SYNC_CHANGED |
2571                               MAC_STATUS_CFG_CHANGED)) == 0)
2572                                 break;
2573                 }
2574
2575                 mac_status = tr32(MAC_STATUS);
2576                 if (current_link_up == 0 &&
2577                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2578                     !(mac_status & MAC_STATUS_RCVD_CFG))
2579                         current_link_up = 1;
2580         } else {
2581                 /* Forcing 1000FD link up. */
2582                 current_link_up = 1;
2583                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2584
2585                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2586                 udelay(40);
2587         }
2588
2589 out:
2590         return current_link_up;
2591 }
2592
2593 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2594 {
2595         u32 orig_pause_cfg;
2596         u16 orig_active_speed;
2597         u8 orig_active_duplex;
2598         u32 mac_status;
2599         int current_link_up;
2600         int i;
2601
2602         orig_pause_cfg =
2603                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2604                                   TG3_FLAG_TX_PAUSE));
2605         orig_active_speed = tp->link_config.active_speed;
2606         orig_active_duplex = tp->link_config.active_duplex;
2607
2608         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2609             netif_carrier_ok(tp->dev) &&
2610             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2611                 mac_status = tr32(MAC_STATUS);
2612                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2613                                MAC_STATUS_SIGNAL_DET |
2614                                MAC_STATUS_CFG_CHANGED |
2615                                MAC_STATUS_RCVD_CFG);
2616                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2617                                    MAC_STATUS_SIGNAL_DET)) {
2618                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2619                                             MAC_STATUS_CFG_CHANGED));
2620                         return 0;
2621                 }
2622         }
2623
2624         tw32_f(MAC_TX_AUTO_NEG, 0);
2625
2626         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2627         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2628         tw32_f(MAC_MODE, tp->mac_mode);
2629         udelay(40);
2630
2631         if (tp->phy_id == PHY_ID_BCM8002)
2632                 tg3_init_bcm8002(tp);
2633
2634         /* Enable link change event even when serdes polling.  */
2635         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2636         udelay(40);
2637
2638         current_link_up = 0;
2639         mac_status = tr32(MAC_STATUS);
2640
2641         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2642                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2643         else
2644                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2645
2646         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2647         tw32_f(MAC_MODE, tp->mac_mode);
2648         udelay(40);
2649
2650         tp->hw_status->status =
2651                 (SD_STATUS_UPDATED |
2652                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2653
2654         for (i = 0; i < 100; i++) {
2655                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2656                                     MAC_STATUS_CFG_CHANGED));
2657                 udelay(5);
2658                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2659                                          MAC_STATUS_CFG_CHANGED)) == 0)
2660                         break;
2661         }
2662
2663         mac_status = tr32(MAC_STATUS);
2664         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2665                 current_link_up = 0;
2666                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2667                         tw32_f(MAC_MODE, (tp->mac_mode |
2668                                           MAC_MODE_SEND_CONFIGS));
2669                         udelay(1);
2670                         tw32_f(MAC_MODE, tp->mac_mode);
2671                 }
2672         }
2673
2674         if (current_link_up == 1) {
2675                 tp->link_config.active_speed = SPEED_1000;
2676                 tp->link_config.active_duplex = DUPLEX_FULL;
2677                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2678                                     LED_CTRL_LNKLED_OVERRIDE |
2679                                     LED_CTRL_1000MBPS_ON));
2680         } else {
2681                 tp->link_config.active_speed = SPEED_INVALID;
2682                 tp->link_config.active_duplex = DUPLEX_INVALID;
2683                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2684                                     LED_CTRL_LNKLED_OVERRIDE |
2685                                     LED_CTRL_TRAFFIC_OVERRIDE));
2686         }
2687
2688         if (current_link_up != netif_carrier_ok(tp->dev)) {
2689                 if (current_link_up)
2690                         netif_carrier_on(tp->dev);
2691                 else
2692                         netif_carrier_off(tp->dev);
2693                 tg3_link_report(tp);
2694         } else {
2695                 u32 now_pause_cfg =
2696                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2697                                          TG3_FLAG_TX_PAUSE);
2698                 if (orig_pause_cfg != now_pause_cfg ||
2699                     orig_active_speed != tp->link_config.active_speed ||
2700                     orig_active_duplex != tp->link_config.active_duplex)
2701                         tg3_link_report(tp);
2702         }
2703
2704         return 0;
2705 }
2706
2707 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2708 {
2709         int current_link_up, err = 0;
2710         u32 bmsr, bmcr;
2711         u16 current_speed;
2712         u8 current_duplex;
2713
2714         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2715         tw32_f(MAC_MODE, tp->mac_mode);
2716         udelay(40);
2717
2718         tw32(MAC_EVENT, 0);
2719
2720         tw32_f(MAC_STATUS,
2721              (MAC_STATUS_SYNC_CHANGED |
2722               MAC_STATUS_CFG_CHANGED |
2723               MAC_STATUS_MI_COMPLETION |
2724               MAC_STATUS_LNKSTATE_CHANGED));
2725         udelay(40);
2726
2727         if (force_reset)
2728                 tg3_phy_reset(tp);
2729
2730         current_link_up = 0;
2731         current_speed = SPEED_INVALID;
2732         current_duplex = DUPLEX_INVALID;
2733
2734         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2735         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2736         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2737                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2738                         bmsr |= BMSR_LSTATUS;
2739                 else
2740                         bmsr &= ~BMSR_LSTATUS;
2741         }
2742
2743         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2744
2745         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2746             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2747                 /* do nothing, just check for link up at the end */
2748         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2749                 u32 adv, new_adv;
2750
2751                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2752                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2753                                   ADVERTISE_1000XPAUSE |
2754                                   ADVERTISE_1000XPSE_ASYM |
2755                                   ADVERTISE_SLCT);
2756
2757                 /* Always advertise symmetric PAUSE just like copper */
2758                 new_adv |= ADVERTISE_1000XPAUSE;
2759
2760                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2761                         new_adv |= ADVERTISE_1000XHALF;
2762                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2763                         new_adv |= ADVERTISE_1000XFULL;
2764
2765                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2766                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2767                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2768                         tg3_writephy(tp, MII_BMCR, bmcr);
2769
2770                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2771                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2772                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2773
2774                         return err;
2775                 }
2776         } else {
2777                 u32 new_bmcr;
2778
2779                 bmcr &= ~BMCR_SPEED1000;
2780                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2781
2782                 if (tp->link_config.duplex == DUPLEX_FULL)
2783                         new_bmcr |= BMCR_FULLDPLX;
2784
2785                 if (new_bmcr != bmcr) {
2786                         /* BMCR_SPEED1000 is a reserved bit that needs
2787                          * to be set on write.
2788                          */
2789                         new_bmcr |= BMCR_SPEED1000;
2790
2791                         /* Force a linkdown */
2792                         if (netif_carrier_ok(tp->dev)) {
2793                                 u32 adv;
2794
2795                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2796                                 adv &= ~(ADVERTISE_1000XFULL |
2797                                          ADVERTISE_1000XHALF |
2798                                          ADVERTISE_SLCT);
2799                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2800                                 tg3_writephy(tp, MII_BMCR, bmcr |
2801                                                            BMCR_ANRESTART |
2802                                                            BMCR_ANENABLE);
2803                                 udelay(10);
2804                                 netif_carrier_off(tp->dev);
2805                         }
2806                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2807                         bmcr = new_bmcr;
2808                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2809                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2810                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2811                             ASIC_REV_5714) {
2812                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2813                                         bmsr |= BMSR_LSTATUS;
2814                                 else
2815                                         bmsr &= ~BMSR_LSTATUS;
2816                         }
2817                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2818                 }
2819         }
2820
2821         if (bmsr & BMSR_LSTATUS) {
2822                 current_speed = SPEED_1000;
2823                 current_link_up = 1;
2824                 if (bmcr & BMCR_FULLDPLX)
2825                         current_duplex = DUPLEX_FULL;
2826                 else
2827                         current_duplex = DUPLEX_HALF;
2828
2829                 if (bmcr & BMCR_ANENABLE) {
2830                         u32 local_adv, remote_adv, common;
2831
2832                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2833                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2834                         common = local_adv & remote_adv;
2835                         if (common & (ADVERTISE_1000XHALF |
2836                                       ADVERTISE_1000XFULL)) {
2837                                 if (common & ADVERTISE_1000XFULL)
2838                                         current_duplex = DUPLEX_FULL;
2839                                 else
2840                                         current_duplex = DUPLEX_HALF;
2841
2842                                 tg3_setup_flow_control(tp, local_adv,
2843                                                        remote_adv);
2844                         }
2845                         else
2846                                 current_link_up = 0;
2847                 }
2848         }
2849
2850         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2851         if (tp->link_config.active_duplex == DUPLEX_HALF)
2852                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2853
2854         tw32_f(MAC_MODE, tp->mac_mode);
2855         udelay(40);
2856
2857         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2858
2859         tp->link_config.active_speed = current_speed;
2860         tp->link_config.active_duplex = current_duplex;
2861
2862         if (current_link_up != netif_carrier_ok(tp->dev)) {
2863                 if (current_link_up)
2864                         netif_carrier_on(tp->dev);
2865                 else {
2866                         netif_carrier_off(tp->dev);
2867                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2868                 }
2869                 tg3_link_report(tp);
2870         }
2871         return err;
2872 }
2873
2874 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2875 {
2876         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2877                 /* Give autoneg time to complete. */
2878                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2879                 return;
2880         }
2881         if (!netif_carrier_ok(tp->dev) &&
2882             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2883                 u32 bmcr;
2884
2885                 tg3_readphy(tp, MII_BMCR, &bmcr);
2886                 if (bmcr & BMCR_ANENABLE) {
2887                         u32 phy1, phy2;
2888
2889                         /* Select shadow register 0x1f */
2890                         tg3_writephy(tp, 0x1c, 0x7c00);
2891                         tg3_readphy(tp, 0x1c, &phy1);
2892
2893                         /* Select expansion interrupt status register */
2894                         tg3_writephy(tp, 0x17, 0x0f01);
2895                         tg3_readphy(tp, 0x15, &phy2);
2896                         tg3_readphy(tp, 0x15, &phy2);
2897
2898                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2899                                 /* We have signal detect and not receiving
2900                                  * config code words, link is up by parallel
2901                                  * detection.
2902                                  */
2903
2904                                 bmcr &= ~BMCR_ANENABLE;
2905                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2906                                 tg3_writephy(tp, MII_BMCR, bmcr);
2907                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2908                         }
2909                 }
2910         }
2911         else if (netif_carrier_ok(tp->dev) &&
2912                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2913                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2914                 u32 phy2;
2915
2916                 /* Select expansion interrupt status register */
2917                 tg3_writephy(tp, 0x17, 0x0f01);
2918                 tg3_readphy(tp, 0x15, &phy2);
2919                 if (phy2 & 0x20) {
2920                         u32 bmcr;
2921
2922                         /* Config code words received, turn on autoneg. */
2923                         tg3_readphy(tp, MII_BMCR, &bmcr);
2924                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2925
2926                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927
2928                 }
2929         }
2930 }
2931
2932 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2933 {
2934         int err;
2935
2936         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2937                 err = tg3_setup_fiber_phy(tp, force_reset);
2938         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2939                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2940         } else {
2941                 err = tg3_setup_copper_phy(tp, force_reset);
2942         }
2943
2944         if (tp->link_config.active_speed == SPEED_1000 &&
2945             tp->link_config.active_duplex == DUPLEX_HALF)
2946                 tw32(MAC_TX_LENGTHS,
2947                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2948                       (6 << TX_LENGTHS_IPG_SHIFT) |
2949                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2950         else
2951                 tw32(MAC_TX_LENGTHS,
2952                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2953                       (6 << TX_LENGTHS_IPG_SHIFT) |
2954                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2955
2956         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2957                 if (netif_carrier_ok(tp->dev)) {
2958                         tw32(HOSTCC_STAT_COAL_TICKS,
2959                              tp->coal.stats_block_coalesce_usecs);
2960                 } else {
2961                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2962                 }
2963         }
2964
2965         return err;
2966 }
2967
2968 /* Tigon3 never reports partial packet sends.  So we do not
2969  * need special logic to handle SKBs that have not had all
2970  * of their frags sent yet, like SunGEM does.
2971  */
2972 static void tg3_tx(struct tg3 *tp)
2973 {
2974         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2975         u32 sw_idx = tp->tx_cons;
2976
2977         while (sw_idx != hw_idx) {
2978                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2979                 struct sk_buff *skb = ri->skb;
2980                 int i;
2981
2982                 BUG_ON(skb == NULL);
2983                 pci_unmap_single(tp->pdev,
2984                                  pci_unmap_addr(ri, mapping),
2985                                  skb_headlen(skb),
2986                                  PCI_DMA_TODEVICE);
2987
2988                 ri->skb = NULL;
2989
2990                 sw_idx = NEXT_TX(sw_idx);
2991
2992                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2993                         BUG_ON(sw_idx == hw_idx);
2994
2995                         ri = &tp->tx_buffers[sw_idx];
2996                         BUG_ON(ri->skb != NULL);
2997
2998                         pci_unmap_page(tp->pdev,
2999                                        pci_unmap_addr(ri, mapping),
3000                                        skb_shinfo(skb)->frags[i].size,
3001                                        PCI_DMA_TODEVICE);
3002
3003                         sw_idx = NEXT_TX(sw_idx);
3004                 }
3005
3006                 dev_kfree_skb(skb);
3007         }
3008
3009         tp->tx_cons = sw_idx;
3010
3011         if (unlikely(netif_queue_stopped(tp->dev))) {
3012                 spin_lock(&tp->tx_lock);
3013                 if (netif_queue_stopped(tp->dev) &&
3014                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
3015                         netif_wake_queue(tp->dev);
3016                 spin_unlock(&tp->tx_lock);
3017         }
3018 }
3019
3020 /* Returns size of skb allocated or < 0 on error.
3021  *
3022  * We only need to fill in the address because the other members
3023  * of the RX descriptor are invariant, see tg3_init_rings.
3024  *
3025  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3026  * posting buffers we only dirty the first cache line of the RX
3027  * descriptor (containing the address).  Whereas for the RX status
3028  * buffers the cpu only reads the last cacheline of the RX descriptor
3029  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3030  */
3031 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3032                             int src_idx, u32 dest_idx_unmasked)
3033 {
3034         struct tg3_rx_buffer_desc *desc;
3035         struct ring_info *map, *src_map;
3036         struct sk_buff *skb;
3037         dma_addr_t mapping;
3038         int skb_size, dest_idx;
3039
3040         src_map = NULL;
3041         switch (opaque_key) {
3042         case RXD_OPAQUE_RING_STD:
3043                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3044                 desc = &tp->rx_std[dest_idx];
3045                 map = &tp->rx_std_buffers[dest_idx];
3046                 if (src_idx >= 0)
3047                         src_map = &tp->rx_std_buffers[src_idx];
3048                 skb_size = tp->rx_pkt_buf_sz;
3049                 break;
3050
3051         case RXD_OPAQUE_RING_JUMBO:
3052                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3053                 desc = &tp->rx_jumbo[dest_idx];
3054                 map = &tp->rx_jumbo_buffers[dest_idx];
3055                 if (src_idx >= 0)
3056                         src_map = &tp->rx_jumbo_buffers[src_idx];
3057                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3058                 break;
3059
3060         default:
3061                 return -EINVAL;
3062         };
3063
3064         /* Do not overwrite any of the map or rp information
3065          * until we are sure we can commit to a new buffer.
3066          *
3067          * Callers depend upon this behavior and assume that
3068          * we leave everything unchanged if we fail.
3069          */
3070         skb = dev_alloc_skb(skb_size);
3071         if (skb == NULL)
3072                 return -ENOMEM;
3073
3074         skb->dev = tp->dev;
3075         skb_reserve(skb, tp->rx_offset);
3076
3077         mapping = pci_map_single(tp->pdev, skb->data,
3078                                  skb_size - tp->rx_offset,
3079                                  PCI_DMA_FROMDEVICE);
3080
3081         map->skb = skb;
3082         pci_unmap_addr_set(map, mapping, mapping);
3083
3084         if (src_map != NULL)
3085                 src_map->skb = NULL;
3086
3087         desc->addr_hi = ((u64)mapping >> 32);
3088         desc->addr_lo = ((u64)mapping & 0xffffffff);
3089
3090         return skb_size;
3091 }
3092
3093 /* We only need to move over in the address because the other
3094  * members of the RX descriptor are invariant.  See notes above
3095  * tg3_alloc_rx_skb for full details.
3096  */
3097 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3098                            int src_idx, u32 dest_idx_unmasked)
3099 {
3100         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3101         struct ring_info *src_map, *dest_map;
3102         int dest_idx;
3103
3104         switch (opaque_key) {
3105         case RXD_OPAQUE_RING_STD:
3106                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3107                 dest_desc = &tp->rx_std[dest_idx];
3108                 dest_map = &tp->rx_std_buffers[dest_idx];
3109                 src_desc = &tp->rx_std[src_idx];
3110                 src_map = &tp->rx_std_buffers[src_idx];
3111                 break;
3112
3113         case RXD_OPAQUE_RING_JUMBO:
3114                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3115                 dest_desc = &tp->rx_jumbo[dest_idx];
3116                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3117                 src_desc = &tp->rx_jumbo[src_idx];
3118                 src_map = &tp->rx_jumbo_buffers[src_idx];
3119                 break;
3120
3121         default:
3122                 return;
3123         };
3124
3125         dest_map->skb = src_map->skb;
3126         pci_unmap_addr_set(dest_map, mapping,
3127                            pci_unmap_addr(src_map, mapping));
3128         dest_desc->addr_hi = src_desc->addr_hi;
3129         dest_desc->addr_lo = src_desc->addr_lo;
3130
3131         src_map->skb = NULL;
3132 }
3133
3134 #if TG3_VLAN_TAG_USED
3135 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3136 {
3137         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3138 }
3139 #endif
3140
3141 /* The RX ring scheme is composed of multiple rings which post fresh
3142  * buffers to the chip, and one special ring the chip uses to report
3143  * status back to the host.
3144  *
3145  * The special ring reports the status of received packets to the
3146  * host.  The chip does not write into the original descriptor the
3147  * RX buffer was obtained from.  The chip simply takes the original
3148  * descriptor as provided by the host, updates the status and length
3149  * field, then writes this into the next status ring entry.
3150  *
3151  * Each ring the host uses to post buffers to the chip is described
3152  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3153  * it is first placed into the on-chip ram.  When the packet's length
3154  * is known, it walks down the TG3_BDINFO entries to select the ring.
3155  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3156  * which is within the range of the new packet's length is chosen.
3157  *
3158  * The "separate ring for rx status" scheme may sound queer, but it makes
3159  * sense from a cache coherency perspective.  If only the host writes
3160  * to the buffer post rings, and only the chip writes to the rx status
3161  * rings, then cache lines never move beyond shared-modified state.
3162  * If both the host and chip were to write into the same ring, cache line
3163  * eviction could occur since both entities want it in an exclusive state.
3164  */
3165 static int tg3_rx(struct tg3 *tp, int budget)
3166 {
3167         u32 work_mask;
3168         u32 sw_idx = tp->rx_rcb_ptr;
3169         u16 hw_idx;
3170         int received;
3171
3172         hw_idx = tp->hw_status->idx[0].rx_producer;
3173         /*
3174          * We need to order the read of hw_idx and the read of
3175          * the opaque cookie.
3176          */
3177         rmb();
3178         work_mask = 0;
3179         received = 0;
3180         while (sw_idx != hw_idx && budget > 0) {
3181                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3182                 unsigned int len;
3183                 struct sk_buff *skb;
3184                 dma_addr_t dma_addr;
3185                 u32 opaque_key, desc_idx, *post_ptr;
3186
3187                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3188                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3189                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3190                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3191                                                   mapping);
3192                         skb = tp->rx_std_buffers[desc_idx].skb;
3193                         post_ptr = &tp->rx_std_ptr;
3194                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3195                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3196                                                   mapping);
3197                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3198                         post_ptr = &tp->rx_jumbo_ptr;
3199                 }
3200                 else {
3201                         goto next_pkt_nopost;
3202                 }
3203
3204                 work_mask |= opaque_key;
3205
3206                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3207                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3208                 drop_it:
3209                         tg3_recycle_rx(tp, opaque_key,
3210                                        desc_idx, *post_ptr);
3211                 drop_it_no_recycle:
3212                         /* Other statistics kept track of by card. */
3213                         tp->net_stats.rx_dropped++;
3214                         goto next_pkt;
3215                 }
3216
3217                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3218
3219                 if (len > RX_COPY_THRESHOLD
3220                         && tp->rx_offset == 2
3221                         /* rx_offset != 2 iff this is a 5701 card running
3222                          * in PCI-X mode [see tg3_get_invariants()] */
3223                 ) {
3224                         int skb_size;
3225
3226                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3227                                                     desc_idx, *post_ptr);
3228                         if (skb_size < 0)
3229                                 goto drop_it;
3230
3231                         pci_unmap_single(tp->pdev, dma_addr,
3232                                          skb_size - tp->rx_offset,
3233                                          PCI_DMA_FROMDEVICE);
3234
3235                         skb_put(skb, len);
3236                 } else {
3237                         struct sk_buff *copy_skb;
3238
3239                         tg3_recycle_rx(tp, opaque_key,
3240                                        desc_idx, *post_ptr);
3241
3242                         copy_skb = dev_alloc_skb(len + 2);
3243                         if (copy_skb == NULL)
3244                                 goto drop_it_no_recycle;
3245
3246                         copy_skb->dev = tp->dev;
3247                         skb_reserve(copy_skb, 2);
3248                         skb_put(copy_skb, len);
3249                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3250                         memcpy(copy_skb->data, skb->data, len);
3251                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3252
3253                         /* We'll reuse the original ring buffer. */
3254                         skb = copy_skb;
3255                 }
3256
3257                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3258                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3259                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3260                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3261                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3262                 else
3263                         skb->ip_summed = CHECKSUM_NONE;
3264
3265                 skb->protocol = eth_type_trans(skb, tp->dev);
3266 #if TG3_VLAN_TAG_USED
3267                 if (tp->vlgrp != NULL &&
3268                     desc->type_flags & RXD_FLAG_VLAN) {
3269                         tg3_vlan_rx(tp, skb,
3270                                     desc->err_vlan & RXD_VLAN_MASK);
3271                 } else
3272 #endif
3273                         netif_receive_skb(skb);
3274
3275                 tp->dev->last_rx = jiffies;
3276                 received++;
3277                 budget--;
3278
3279 next_pkt:
3280                 (*post_ptr)++;
3281 next_pkt_nopost:
3282                 sw_idx++;
3283                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3284
3285                 /* Refresh hw_idx to see if there is new work */
3286                 if (sw_idx == hw_idx) {
3287                         hw_idx = tp->hw_status->idx[0].rx_producer;
3288                         rmb();
3289                 }
3290         }
3291
3292         /* ACK the status ring. */
3293         tp->rx_rcb_ptr = sw_idx;
3294         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3295
3296         /* Refill RX ring(s). */
3297         if (work_mask & RXD_OPAQUE_RING_STD) {
3298                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3299                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3300                              sw_idx);
3301         }
3302         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3303                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3304                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3305                              sw_idx);
3306         }
3307         mmiowb();
3308
3309         return received;
3310 }
3311
3312 static int tg3_poll(struct net_device *netdev, int *budget)
3313 {
3314         struct tg3 *tp = netdev_priv(netdev);
3315         struct tg3_hw_status *sblk = tp->hw_status;
3316         int done;
3317
3318         /* handle link change and other phy events */
3319         if (!(tp->tg3_flags &
3320               (TG3_FLAG_USE_LINKCHG_REG |
3321                TG3_FLAG_POLL_SERDES))) {
3322                 if (sblk->status & SD_STATUS_LINK_CHG) {
3323                         sblk->status = SD_STATUS_UPDATED |
3324                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3325                         spin_lock(&tp->lock);
3326                         tg3_setup_phy(tp, 0);
3327                         spin_unlock(&tp->lock);
3328                 }
3329         }
3330
3331         /* run TX completion thread */
3332         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3333                 tg3_tx(tp);
3334         }
3335
3336         /* run RX thread, within the bounds set by NAPI.
3337          * All RX "locking" is done by ensuring outside
3338          * code synchronizes with dev->poll()
3339          */
3340         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3341                 int orig_budget = *budget;
3342                 int work_done;
3343
3344                 if (orig_budget > netdev->quota)
3345                         orig_budget = netdev->quota;
3346
3347                 work_done = tg3_rx(tp, orig_budget);
3348
3349                 *budget -= work_done;
3350                 netdev->quota -= work_done;
3351         }
3352
3353         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3354                 tp->last_tag = sblk->status_tag;
3355                 rmb();
3356         } else
3357                 sblk->status &= ~SD_STATUS_UPDATED;
3358
3359         /* if no more work, tell net stack and NIC we're done */
3360         done = !tg3_has_work(tp);
3361         if (done) {
3362                 netif_rx_complete(netdev);
3363                 tg3_restart_ints(tp);
3364         }
3365
3366         return (done ? 0 : 1);
3367 }
3368
3369 static void tg3_irq_quiesce(struct tg3 *tp)
3370 {
3371         BUG_ON(tp->irq_sync);
3372
3373         tp->irq_sync = 1;
3374         smp_mb();
3375
3376         synchronize_irq(tp->pdev->irq);
3377 }
3378
3379 static inline int tg3_irq_sync(struct tg3 *tp)
3380 {
3381         return tp->irq_sync;
3382 }
3383
3384 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3385  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3386  * with as well.  Most of the time, this is not necessary except when
3387  * shutting down the device.
3388  */
3389 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3390 {
3391         if (irq_sync)
3392                 tg3_irq_quiesce(tp);
3393         spin_lock_bh(&tp->lock);
3394         spin_lock(&tp->tx_lock);
3395 }
3396
3397 static inline void tg3_full_unlock(struct tg3 *tp)
3398 {
3399         spin_unlock(&tp->tx_lock);
3400         spin_unlock_bh(&tp->lock);
3401 }
3402
3403 /* One-shot MSI handler - Chip automatically disables interrupt
3404  * after sending MSI so driver doesn't have to do it.
3405  */
3406 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3407 {
3408         struct net_device *dev = dev_id;
3409         struct tg3 *tp = netdev_priv(dev);
3410
3411         prefetch(tp->hw_status);
3412         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3413
3414         if (likely(!tg3_irq_sync(tp)))
3415                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3416
3417         return IRQ_HANDLED;
3418 }
3419
3420 /* MSI ISR - No need to check for interrupt sharing and no need to
3421  * flush status block and interrupt mailbox. PCI ordering rules
3422  * guarantee that MSI will arrive after the status block.
3423  */
3424 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3425 {
3426         struct net_device *dev = dev_id;
3427         struct tg3 *tp = netdev_priv(dev);
3428
3429         prefetch(tp->hw_status);
3430         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3431         /*
3432          * Writing any value to intr-mbox-0 clears PCI INTA# and
3433          * chip-internal interrupt pending events.
3434          * Writing non-zero to intr-mbox-0 additional tells the
3435          * NIC to stop sending us irqs, engaging "in-intr-handler"
3436          * event coalescing.
3437          */
3438         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3439         if (likely(!tg3_irq_sync(tp)))
3440                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3441
3442         return IRQ_RETVAL(1);
3443 }
3444
3445 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3446 {
3447         struct net_device *dev = dev_id;
3448         struct tg3 *tp = netdev_priv(dev);
3449         struct tg3_hw_status *sblk = tp->hw_status;
3450         unsigned int handled = 1;
3451
3452         /* In INTx mode, it is possible for the interrupt to arrive at
3453          * the CPU before the status block posted prior to the interrupt.
3454          * Reading the PCI State register will confirm whether the
3455          * interrupt is ours and will flush the status block.
3456          */
3457         if ((sblk->status & SD_STATUS_UPDATED) ||
3458             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3459                 /*
3460                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3461                  * chip-internal interrupt pending events.
3462                  * Writing non-zero to intr-mbox-0 additional tells the
3463                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3464                  * event coalescing.
3465                  */
3466                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3467                              0x00000001);
3468                 if (tg3_irq_sync(tp))
3469                         goto out;
3470                 sblk->status &= ~SD_STATUS_UPDATED;
3471                 if (likely(tg3_has_work(tp))) {
3472                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3473                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3474                 } else {
3475                         /* No work, shared interrupt perhaps?  re-enable
3476                          * interrupts, and flush that PCI write
3477                          */
3478                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3479                                 0x00000000);
3480                 }
3481         } else {        /* shared interrupt */
3482                 handled = 0;
3483         }
3484 out:
3485         return IRQ_RETVAL(handled);
3486 }
3487
3488 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3489 {
3490         struct net_device *dev = dev_id;
3491         struct tg3 *tp = netdev_priv(dev);
3492         struct tg3_hw_status *sblk = tp->hw_status;
3493         unsigned int handled = 1;
3494
3495         /* In INTx mode, it is possible for the interrupt to arrive at
3496          * the CPU before the status block posted prior to the interrupt.
3497          * Reading the PCI State register will confirm whether the
3498          * interrupt is ours and will flush the status block.
3499          */
3500         if ((sblk->status_tag != tp->last_tag) ||
3501             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3502                 /*
3503                  * writing any value to intr-mbox-0 clears PCI INTA# and
3504                  * chip-internal interrupt pending events.
3505                  * writing non-zero to intr-mbox-0 additional tells the
3506                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3507                  * event coalescing.
3508                  */
3509                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3510                              0x00000001);
3511                 if (tg3_irq_sync(tp))
3512                         goto out;
3513                 if (netif_rx_schedule_prep(dev)) {
3514                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3515                         /* Update last_tag to mark that this status has been
3516                          * seen. Because interrupt may be shared, we may be
3517                          * racing with tg3_poll(), so only update last_tag
3518                          * if tg3_poll() is not scheduled.
3519                          */
3520                         tp->last_tag = sblk->status_tag;
3521                         __netif_rx_schedule(dev);
3522                 }
3523         } else {        /* shared interrupt */
3524                 handled = 0;
3525         }
3526 out:
3527         return IRQ_RETVAL(handled);
3528 }
3529
3530 /* ISR for interrupt test */
3531 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3532                 struct pt_regs *regs)
3533 {
3534         struct net_device *dev = dev_id;
3535         struct tg3 *tp = netdev_priv(dev);
3536         struct tg3_hw_status *sblk = tp->hw_status;
3537
3538         if ((sblk->status & SD_STATUS_UPDATED) ||
3539             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3540                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3541                              0x00000001);
3542                 return IRQ_RETVAL(1);
3543         }
3544         return IRQ_RETVAL(0);
3545 }
3546
3547 static int tg3_init_hw(struct tg3 *, int);
3548 static int tg3_halt(struct tg3 *, int, int);
3549
3550 #ifdef CONFIG_NET_POLL_CONTROLLER
3551 static void tg3_poll_controller(struct net_device *dev)
3552 {
3553         struct tg3 *tp = netdev_priv(dev);
3554
3555         tg3_interrupt(tp->pdev->irq, dev, NULL);
3556 }
3557 #endif
3558
3559 static void tg3_reset_task(void *_data)
3560 {
3561         struct tg3 *tp = _data;
3562         unsigned int restart_timer;
3563
3564         tg3_full_lock(tp, 0);
3565         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3566
3567         if (!netif_running(tp->dev)) {
3568                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3569                 tg3_full_unlock(tp);
3570                 return;
3571         }
3572
3573         tg3_full_unlock(tp);
3574
3575         tg3_netif_stop(tp);
3576
3577         tg3_full_lock(tp, 1);
3578
3579         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3580         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3581
3582         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3583         tg3_init_hw(tp, 1);
3584
3585         tg3_netif_start(tp);
3586
3587         if (restart_timer)
3588                 mod_timer(&tp->timer, jiffies + 1);
3589
3590         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3591
3592         tg3_full_unlock(tp);
3593 }
3594
3595 static void tg3_tx_timeout(struct net_device *dev)
3596 {
3597         struct tg3 *tp = netdev_priv(dev);
3598
3599         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3600                dev->name);
3601
3602         schedule_work(&tp->reset_task);
3603 }
3604
3605 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3606 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3607 {
3608         u32 base = (u32) mapping & 0xffffffff;
3609
3610         return ((base > 0xffffdcc0) &&
3611                 (base + len + 8 < base));
3612 }
3613
3614 /* Test for DMA addresses > 40-bit */
3615 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3616                                           int len)
3617 {
3618 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3619         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3620                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3621         return 0;
3622 #else
3623         return 0;
3624 #endif
3625 }
3626
3627 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3628
3629 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3630 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3631                                        u32 last_plus_one, u32 *start,
3632                                        u32 base_flags, u32 mss)
3633 {
3634         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3635         dma_addr_t new_addr = 0;
3636         u32 entry = *start;
3637         int i, ret = 0;
3638
3639         if (!new_skb) {
3640                 ret = -1;
3641         } else {
3642                 /* New SKB is guaranteed to be linear. */
3643                 entry = *start;
3644                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3645                                           PCI_DMA_TODEVICE);
3646                 /* Make sure new skb does not cross any 4G boundaries.
3647                  * Drop the packet if it does.
3648                  */
3649                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3650                         ret = -1;
3651                         dev_kfree_skb(new_skb);
3652                         new_skb = NULL;
3653                 } else {
3654                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3655                                     base_flags, 1 | (mss << 1));
3656                         *start = NEXT_TX(entry);
3657                 }
3658         }
3659
3660         /* Now clean up the sw ring entries. */
3661         i = 0;
3662         while (entry != last_plus_one) {
3663                 int len;
3664
3665                 if (i == 0)
3666                         len = skb_headlen(skb);
3667                 else
3668                         len = skb_shinfo(skb)->frags[i-1].size;
3669                 pci_unmap_single(tp->pdev,
3670                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3671                                  len, PCI_DMA_TODEVICE);
3672                 if (i == 0) {
3673                         tp->tx_buffers[entry].skb = new_skb;
3674                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3675                 } else {
3676                         tp->tx_buffers[entry].skb = NULL;
3677                 }
3678                 entry = NEXT_TX(entry);
3679                 i++;
3680         }
3681
3682         dev_kfree_skb(skb);
3683
3684         return ret;
3685 }
3686
3687 static void tg3_set_txd(struct tg3 *tp, int entry,
3688                         dma_addr_t mapping, int len, u32 flags,
3689                         u32 mss_and_is_end)
3690 {
3691         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3692         int is_end = (mss_and_is_end & 0x1);
3693         u32 mss = (mss_and_is_end >> 1);
3694         u32 vlan_tag = 0;
3695
3696         if (is_end)
3697                 flags |= TXD_FLAG_END;
3698         if (flags & TXD_FLAG_VLAN) {
3699                 vlan_tag = flags >> 16;
3700                 flags &= 0xffff;
3701         }
3702         vlan_tag |= (mss << TXD_MSS_SHIFT);
3703
3704         txd->addr_hi = ((u64) mapping >> 32);
3705         txd->addr_lo = ((u64) mapping & 0xffffffff);
3706         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3707         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3708 }
3709
3710 /* hard_start_xmit for devices that don't have any bugs and
3711  * support TG3_FLG2_HW_TSO_2 only.
3712  */
3713 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3714 {
3715         struct tg3 *tp = netdev_priv(dev);
3716         dma_addr_t mapping;
3717         u32 len, entry, base_flags, mss;
3718
3719         len = skb_headlen(skb);
3720
3721         /* No BH disabling for tx_lock here.  We are running in BH disabled
3722          * context and TX reclaim runs via tp->poll inside of a software
3723          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3724          * no IRQ context deadlocks to worry about either.  Rejoice!
3725          */
3726         if (!spin_trylock(&tp->tx_lock))
3727                 return NETDEV_TX_LOCKED;
3728
3729         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3730                 if (!netif_queue_stopped(dev)) {
3731                         netif_stop_queue(dev);
3732
3733                         /* This is a hard error, log it. */
3734                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3735                                "queue awake!\n", dev->name);
3736                 }
3737                 spin_unlock(&tp->tx_lock);
3738                 return NETDEV_TX_BUSY;
3739         }
3740
3741         entry = tp->tx_prod;
3742         base_flags = 0;
3743 #if TG3_TSO_SUPPORT != 0
3744         mss = 0;
3745         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3746             (mss = skb_shinfo(skb)->tso_size) != 0) {
3747                 int tcp_opt_len, ip_tcp_len;
3748
3749                 if (skb_header_cloned(skb) &&
3750                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3751                         dev_kfree_skb(skb);
3752                         goto out_unlock;
3753                 }
3754
3755                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3756                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3757
3758                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3759                                TXD_FLAG_CPU_POST_DMA);
3760
3761                 skb->nh.iph->check = 0;
3762                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3763
3764                 skb->h.th->check = 0;
3765
3766                 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3767         }
3768         else if (skb->ip_summed == CHECKSUM_HW)
3769                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3770 #else
3771         mss = 0;
3772         if (skb->ip_summed == CHECKSUM_HW)
3773                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3774 #endif
3775 #if TG3_VLAN_TAG_USED
3776         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3777                 base_flags |= (TXD_FLAG_VLAN |
3778                                (vlan_tx_tag_get(skb) << 16));
3779 #endif
3780
3781         /* Queue skb data, a.k.a. the main skb fragment. */
3782         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3783
3784         tp->tx_buffers[entry].skb = skb;
3785         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3786
3787         tg3_set_txd(tp, entry, mapping, len, base_flags,
3788                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3789
3790         entry = NEXT_TX(entry);
3791
3792         /* Now loop through additional data fragments, and queue them. */
3793         if (skb_shinfo(skb)->nr_frags > 0) {
3794                 unsigned int i, last;
3795
3796                 last = skb_shinfo(skb)->nr_frags - 1;
3797                 for (i = 0; i <= last; i++) {
3798                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3799
3800                         len = frag->size;
3801                         mapping = pci_map_page(tp->pdev,
3802                                                frag->page,
3803                                                frag->page_offset,
3804                                                len, PCI_DMA_TODEVICE);
3805
3806                         tp->tx_buffers[entry].skb = NULL;
3807                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3808
3809                         tg3_set_txd(tp, entry, mapping, len,
3810                                     base_flags, (i == last) | (mss << 1));
3811
3812                         entry = NEXT_TX(entry);
3813                 }
3814         }
3815
3816         /* Packets are ready, update Tx producer idx local and on card. */
3817         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3818
3819         tp->tx_prod = entry;
3820         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3821                 netif_stop_queue(dev);
3822                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3823                         netif_wake_queue(tp->dev);
3824         }
3825
3826 out_unlock:
3827         mmiowb();
3828         spin_unlock(&tp->tx_lock);
3829
3830         dev->trans_start = jiffies;
3831
3832         return NETDEV_TX_OK;
3833 }
3834
3835 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3836  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3837  */
3838 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3839 {
3840         struct tg3 *tp = netdev_priv(dev);
3841         dma_addr_t mapping;
3842         u32 len, entry, base_flags, mss;
3843         int would_hit_hwbug;
3844
3845         len = skb_headlen(skb);
3846
3847         /* No BH disabling for tx_lock here.  We are running in BH disabled
3848          * context and TX reclaim runs via tp->poll inside of a software
3849          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3850          * no IRQ context deadlocks to worry about either.  Rejoice!
3851          */
3852         if (!spin_trylock(&tp->tx_lock))
3853                 return NETDEV_TX_LOCKED;
3854
3855         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3856                 if (!netif_queue_stopped(dev)) {
3857                         netif_stop_queue(dev);
3858
3859                         /* This is a hard error, log it. */
3860                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3861                                "queue awake!\n", dev->name);
3862                 }
3863                 spin_unlock(&tp->tx_lock);
3864                 return NETDEV_TX_BUSY;
3865         }
3866
3867         entry = tp->tx_prod;
3868         base_flags = 0;
3869         if (skb->ip_summed == CHECKSUM_HW)
3870                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3871 #if TG3_TSO_SUPPORT != 0
3872         mss = 0;
3873         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3874             (mss = skb_shinfo(skb)->tso_size) != 0) {
3875                 int tcp_opt_len, ip_tcp_len;
3876
3877                 if (skb_header_cloned(skb) &&
3878                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3879                         dev_kfree_skb(skb);
3880                         goto out_unlock;
3881                 }
3882
3883                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3884                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3885
3886                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3887                                TXD_FLAG_CPU_POST_DMA);
3888
3889                 skb->nh.iph->check = 0;
3890                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3891                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3892                         skb->h.th->check = 0;
3893                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3894                 }
3895                 else {
3896                         skb->h.th->check =
3897                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3898                                                    skb->nh.iph->daddr,
3899                                                    0, IPPROTO_TCP, 0);
3900                 }
3901
3902                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3903                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3904                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3905                                 int tsflags;
3906
3907                                 tsflags = ((skb->nh.iph->ihl - 5) +
3908                                            (tcp_opt_len >> 2));
3909                                 mss |= (tsflags << 11);
3910                         }
3911                 } else {
3912                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3913                                 int tsflags;
3914
3915                                 tsflags = ((skb->nh.iph->ihl - 5) +
3916                                            (tcp_opt_len >> 2));
3917                                 base_flags |= tsflags << 12;
3918                         }
3919                 }
3920         }
3921 #else
3922         mss = 0;
3923 #endif
3924 #if TG3_VLAN_TAG_USED
3925         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3926                 base_flags |= (TXD_FLAG_VLAN |
3927                                (vlan_tx_tag_get(skb) << 16));
3928 #endif
3929
3930         /* Queue skb data, a.k.a. the main skb fragment. */
3931         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3932
3933         tp->tx_buffers[entry].skb = skb;
3934         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3935
3936         would_hit_hwbug = 0;
3937
3938         if (tg3_4g_overflow_test(mapping, len))
3939                 would_hit_hwbug = 1;
3940
3941         tg3_set_txd(tp, entry, mapping, len, base_flags,
3942                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3943
3944         entry = NEXT_TX(entry);
3945
3946         /* Now loop through additional data fragments, and queue them. */
3947         if (skb_shinfo(skb)->nr_frags > 0) {
3948                 unsigned int i, last;
3949
3950                 last = skb_shinfo(skb)->nr_frags - 1;
3951                 for (i = 0; i <= last; i++) {
3952                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3953
3954                         len = frag->size;
3955                         mapping = pci_map_page(tp->pdev,
3956                                                frag->page,
3957                                                frag->page_offset,
3958                                                len, PCI_DMA_TODEVICE);
3959
3960                         tp->tx_buffers[entry].skb = NULL;
3961                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3962
3963                         if (tg3_4g_overflow_test(mapping, len))
3964                                 would_hit_hwbug = 1;
3965
3966                         if (tg3_40bit_overflow_test(tp, mapping, len))
3967                                 would_hit_hwbug = 1;
3968
3969                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3970                                 tg3_set_txd(tp, entry, mapping, len,
3971                                             base_flags, (i == last)|(mss << 1));
3972                         else
3973                                 tg3_set_txd(tp, entry, mapping, len,
3974                                             base_flags, (i == last));
3975
3976                         entry = NEXT_TX(entry);
3977                 }
3978         }
3979
3980         if (would_hit_hwbug) {
3981                 u32 last_plus_one = entry;
3982                 u32 start;
3983
3984                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3985                 start &= (TG3_TX_RING_SIZE - 1);
3986
3987                 /* If the workaround fails due to memory/mapping
3988                  * failure, silently drop this packet.
3989                  */
3990                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
3991                                                 &start, base_flags, mss))
3992                         goto out_unlock;
3993
3994                 entry = start;
3995         }
3996
3997         /* Packets are ready, update Tx producer idx local and on card. */
3998         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3999
4000         tp->tx_prod = entry;
4001         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
4002                 netif_stop_queue(dev);
4003                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
4004                         netif_wake_queue(tp->dev);
4005         }
4006
4007 out_unlock:
4008         mmiowb();
4009         spin_unlock(&tp->tx_lock);
4010
4011         dev->trans_start = jiffies;
4012
4013         return NETDEV_TX_OK;
4014 }
4015
4016 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4017                                int new_mtu)
4018 {
4019         dev->mtu = new_mtu;
4020
4021         if (new_mtu > ETH_DATA_LEN) {
4022                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4023                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4024                         ethtool_op_set_tso(dev, 0);
4025                 }
4026                 else
4027                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4028         } else {
4029                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4030                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4031                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4032         }
4033 }
4034
4035 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4036 {
4037         struct tg3 *tp = netdev_priv(dev);
4038
4039         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4040                 return -EINVAL;
4041
4042         if (!netif_running(dev)) {
4043                 /* We'll just catch it later when the
4044                  * device is up'd.
4045                  */
4046                 tg3_set_mtu(dev, tp, new_mtu);
4047                 return 0;
4048         }
4049
4050         tg3_netif_stop(tp);
4051
4052         tg3_full_lock(tp, 1);
4053
4054         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4055
4056         tg3_set_mtu(dev, tp, new_mtu);
4057
4058         tg3_init_hw(tp, 0);
4059
4060         tg3_netif_start(tp);
4061
4062         tg3_full_unlock(tp);
4063
4064         return 0;
4065 }
4066
4067 /* Free up pending packets in all rx/tx rings.
4068  *
4069  * The chip has been shut down and the driver detached from
4070  * the networking, so no interrupts or new tx packets will
4071  * end up in the driver.  tp->{tx,}lock is not held and we are not
4072  * in an interrupt context and thus may sleep.
4073  */
4074 static void tg3_free_rings(struct tg3 *tp)
4075 {
4076         struct ring_info *rxp;
4077         int i;
4078
4079         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4080                 rxp = &tp->rx_std_buffers[i];
4081
4082                 if (rxp->skb == NULL)
4083                         continue;
4084                 pci_unmap_single(tp->pdev,
4085                                  pci_unmap_addr(rxp, mapping),
4086                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4087                                  PCI_DMA_FROMDEVICE);
4088                 dev_kfree_skb_any(rxp->skb);
4089                 rxp->skb = NULL;
4090         }
4091
4092         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4093                 rxp = &tp->rx_jumbo_buffers[i];
4094
4095                 if (rxp->skb == NULL)
4096                         continue;
4097                 pci_unmap_single(tp->pdev,
4098                                  pci_unmap_addr(rxp, mapping),
4099                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4100                                  PCI_DMA_FROMDEVICE);
4101                 dev_kfree_skb_any(rxp->skb);
4102                 rxp->skb = NULL;
4103         }
4104
4105         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4106                 struct tx_ring_info *txp;
4107                 struct sk_buff *skb;
4108                 int j;
4109
4110                 txp = &tp->tx_buffers[i];
4111                 skb = txp->skb;
4112
4113                 if (skb == NULL) {
4114                         i++;
4115                         continue;
4116                 }
4117
4118                 pci_unmap_single(tp->pdev,
4119                                  pci_unmap_addr(txp, mapping),
4120                                  skb_headlen(skb),
4121                                  PCI_DMA_TODEVICE);
4122                 txp->skb = NULL;
4123
4124                 i++;
4125
4126                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4127                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4128                         pci_unmap_page(tp->pdev,
4129                                        pci_unmap_addr(txp, mapping),
4130                                        skb_shinfo(skb)->frags[j].size,
4131                                        PCI_DMA_TODEVICE);
4132                         i++;
4133                 }
4134
4135                 dev_kfree_skb_any(skb);
4136         }
4137 }
4138
4139 /* Initialize tx/rx rings for packet processing.
4140  *
4141  * The chip has been shut down and the driver detached from
4142  * the networking, so no interrupts or new tx packets will
4143  * end up in the driver.  tp->{tx,}lock are held and thus
4144  * we may not sleep.
4145  */
4146 static void tg3_init_rings(struct tg3 *tp)
4147 {
4148         u32 i;
4149
4150         /* Free up all the SKBs. */
4151         tg3_free_rings(tp);
4152
4153         /* Zero out all descriptors. */
4154         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4155         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4156         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4157         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4158
4159         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4160         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4161             (tp->dev->mtu > ETH_DATA_LEN))
4162                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4163
4164         /* Initialize invariants of the rings, we only set this
4165          * stuff once.  This works because the card does not
4166          * write into the rx buffer posting rings.
4167          */
4168         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4169                 struct tg3_rx_buffer_desc *rxd;
4170
4171                 rxd = &tp->rx_std[i];
4172                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4173                         << RXD_LEN_SHIFT;
4174                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4175                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4176                                (i << RXD_OPAQUE_INDEX_SHIFT));
4177         }
4178
4179         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4180                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4181                         struct tg3_rx_buffer_desc *rxd;
4182
4183                         rxd = &tp->rx_jumbo[i];
4184                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4185                                 << RXD_LEN_SHIFT;
4186                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4187                                 RXD_FLAG_JUMBO;
4188                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4189                                (i << RXD_OPAQUE_INDEX_SHIFT));
4190                 }
4191         }
4192
4193         /* Now allocate fresh SKBs for each rx ring. */
4194         for (i = 0; i < tp->rx_pending; i++) {
4195                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
4196                                      -1, i) < 0)
4197                         break;
4198         }
4199
4200         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4201                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4202                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4203                                              -1, i) < 0)
4204                                 break;
4205                 }
4206         }
4207 }
4208
4209 /*
4210  * Must not be invoked with interrupt sources disabled and
4211  * the hardware shutdown down.
4212  */
4213 static void tg3_free_consistent(struct tg3 *tp)
4214 {
4215         kfree(tp->rx_std_buffers);
4216         tp->rx_std_buffers = NULL;
4217         if (tp->rx_std) {
4218                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4219                                     tp->rx_std, tp->rx_std_mapping);
4220                 tp->rx_std = NULL;
4221         }
4222         if (tp->rx_jumbo) {
4223                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4224                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4225                 tp->rx_jumbo = NULL;
4226         }
4227         if (tp->rx_rcb) {
4228                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4229                                     tp->rx_rcb, tp->rx_rcb_mapping);
4230                 tp->rx_rcb = NULL;
4231         }
4232         if (tp->tx_ring) {
4233                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4234                         tp->tx_ring, tp->tx_desc_mapping);
4235                 tp->tx_ring = NULL;
4236         }
4237         if (tp->hw_status) {
4238                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4239                                     tp->hw_status, tp->status_mapping);
4240                 tp->hw_status = NULL;
4241         }
4242         if (tp->hw_stats) {
4243                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4244                                     tp->hw_stats, tp->stats_mapping);
4245                 tp->hw_stats = NULL;
4246         }
4247 }
4248
4249 /*
4250  * Must not be invoked with interrupt sources disabled and
4251  * the hardware shutdown down.  Can sleep.
4252  */
4253 static int tg3_alloc_consistent(struct tg3 *tp)
4254 {
4255         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4256                                       (TG3_RX_RING_SIZE +
4257                                        TG3_RX_JUMBO_RING_SIZE)) +
4258                                      (sizeof(struct tx_ring_info) *
4259                                       TG3_TX_RING_SIZE),
4260                                      GFP_KERNEL);
4261         if (!tp->rx_std_buffers)
4262                 return -ENOMEM;
4263
4264         memset(tp->rx_std_buffers, 0,
4265                (sizeof(struct ring_info) *
4266                 (TG3_RX_RING_SIZE +
4267                  TG3_RX_JUMBO_RING_SIZE)) +
4268                (sizeof(struct tx_ring_info) *
4269                 TG3_TX_RING_SIZE));
4270
4271         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4272         tp->tx_buffers = (struct tx_ring_info *)
4273                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4274
4275         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4276                                           &tp->rx_std_mapping);
4277         if (!tp->rx_std)
4278                 goto err_out;
4279
4280         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4281                                             &tp->rx_jumbo_mapping);
4282
4283         if (!tp->rx_jumbo)
4284                 goto err_out;
4285
4286         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4287                                           &tp->rx_rcb_mapping);
4288         if (!tp->rx_rcb)
4289                 goto err_out;
4290
4291         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4292                                            &tp->tx_desc_mapping);
4293         if (!tp->tx_ring)
4294                 goto err_out;
4295
4296         tp->hw_status = pci_alloc_consistent(tp->pdev,
4297                                              TG3_HW_STATUS_SIZE,
4298                                              &tp->status_mapping);
4299         if (!tp->hw_status)
4300                 goto err_out;
4301
4302         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4303                                             sizeof(struct tg3_hw_stats),
4304                                             &tp->stats_mapping);
4305         if (!tp->hw_stats)
4306                 goto err_out;
4307
4308         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4309         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4310
4311         return 0;
4312
4313 err_out:
4314         tg3_free_consistent(tp);
4315         return -ENOMEM;
4316 }
4317
4318 #define MAX_WAIT_CNT 1000
4319
4320 /* To stop a block, clear the enable bit and poll till it
4321  * clears.  tp->lock is held.
4322  */
4323 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4324 {
4325         unsigned int i;
4326         u32 val;
4327
4328         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4329                 switch (ofs) {
4330                 case RCVLSC_MODE:
4331                 case DMAC_MODE:
4332                 case MBFREE_MODE:
4333                 case BUFMGR_MODE:
4334                 case MEMARB_MODE:
4335                         /* We can't enable/disable these bits of the
4336                          * 5705/5750, just say success.
4337                          */
4338                         return 0;
4339
4340                 default:
4341                         break;
4342                 };
4343         }
4344
4345         val = tr32(ofs);
4346         val &= ~enable_bit;
4347         tw32_f(ofs, val);
4348
4349         for (i = 0; i < MAX_WAIT_CNT; i++) {
4350                 udelay(100);
4351                 val = tr32(ofs);
4352                 if ((val & enable_bit) == 0)
4353                         break;
4354         }
4355
4356         if (i == MAX_WAIT_CNT && !silent) {
4357                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4358                        "ofs=%lx enable_bit=%x\n",
4359                        ofs, enable_bit);
4360                 return -ENODEV;
4361         }
4362
4363         return 0;
4364 }
4365
4366 /* tp->lock is held. */
4367 static int tg3_abort_hw(struct tg3 *tp, int silent)
4368 {
4369         int i, err;
4370
4371         tg3_disable_ints(tp);
4372
4373         tp->rx_mode &= ~RX_MODE_ENABLE;
4374         tw32_f(MAC_RX_MODE, tp->rx_mode);
4375         udelay(10);
4376
4377         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4378         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4379         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4380         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4381         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4382         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4383
4384         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4385         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4386         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4387         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4388         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4389         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4390         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4391
4392         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4393         tw32_f(MAC_MODE, tp->mac_mode);
4394         udelay(40);
4395
4396         tp->tx_mode &= ~TX_MODE_ENABLE;
4397         tw32_f(MAC_TX_MODE, tp->tx_mode);
4398
4399         for (i = 0; i < MAX_WAIT_CNT; i++) {
4400                 udelay(100);
4401                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4402                         break;
4403         }
4404         if (i >= MAX_WAIT_CNT) {
4405                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4406                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4407                        tp->dev->name, tr32(MAC_TX_MODE));
4408                 err |= -ENODEV;
4409         }
4410
4411         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4412         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4413         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4414
4415         tw32(FTQ_RESET, 0xffffffff);
4416         tw32(FTQ_RESET, 0x00000000);
4417
4418         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4419         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4420
4421         if (tp->hw_status)
4422                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4423         if (tp->hw_stats)
4424                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4425
4426         return err;
4427 }
4428
4429 /* tp->lock is held. */
4430 static int tg3_nvram_lock(struct tg3 *tp)
4431 {
4432         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4433                 int i;
4434
4435                 if (tp->nvram_lock_cnt == 0) {
4436                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4437                         for (i = 0; i < 8000; i++) {
4438                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4439                                         break;
4440                                 udelay(20);
4441                         }
4442                         if (i == 8000) {
4443                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4444                                 return -ENODEV;
4445                         }
4446                 }
4447                 tp->nvram_lock_cnt++;
4448         }
4449         return 0;
4450 }
4451
4452 /* tp->lock is held. */
4453 static void tg3_nvram_unlock(struct tg3 *tp)
4454 {
4455         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4456                 if (tp->nvram_lock_cnt > 0)
4457                         tp->nvram_lock_cnt--;
4458                 if (tp->nvram_lock_cnt == 0)
4459                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4460         }
4461 }
4462
4463 /* tp->lock is held. */
4464 static void tg3_enable_nvram_access(struct tg3 *tp)
4465 {
4466         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4467             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4468                 u32 nvaccess = tr32(NVRAM_ACCESS);
4469
4470                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4471         }
4472 }
4473
4474 /* tp->lock is held. */
4475 static void tg3_disable_nvram_access(struct tg3 *tp)
4476 {
4477         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4478             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4479                 u32 nvaccess = tr32(NVRAM_ACCESS);
4480
4481                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4482         }
4483 }
4484
4485 /* tp->lock is held. */
4486 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4487 {
4488         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4489                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4490                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4491
4492         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4493                 switch (kind) {
4494                 case RESET_KIND_INIT:
4495                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4496                                       DRV_STATE_START);
4497                         break;
4498
4499                 case RESET_KIND_SHUTDOWN:
4500                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4501                                       DRV_STATE_UNLOAD);
4502                         break;
4503
4504                 case RESET_KIND_SUSPEND:
4505                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4506                                       DRV_STATE_SUSPEND);
4507                         break;
4508
4509                 default:
4510                         break;
4511                 };
4512         }
4513 }
4514
4515 /* tp->lock is held. */
4516 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4517 {
4518         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4519                 switch (kind) {
4520                 case RESET_KIND_INIT:
4521                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4522                                       DRV_STATE_START_DONE);
4523                         break;
4524
4525                 case RESET_KIND_SHUTDOWN:
4526                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4527                                       DRV_STATE_UNLOAD_DONE);
4528                         break;
4529
4530                 default:
4531                         break;
4532                 };
4533         }
4534 }
4535
4536 /* tp->lock is held. */
4537 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4538 {
4539         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4540                 switch (kind) {
4541                 case RESET_KIND_INIT:
4542                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4543                                       DRV_STATE_START);
4544                         break;
4545
4546                 case RESET_KIND_SHUTDOWN:
4547                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4548                                       DRV_STATE_UNLOAD);
4549                         break;
4550
4551                 case RESET_KIND_SUSPEND:
4552                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4553                                       DRV_STATE_SUSPEND);
4554                         break;
4555
4556                 default:
4557                         break;
4558                 };
4559         }
4560 }
4561
4562 static void tg3_stop_fw(struct tg3 *);
4563
4564 /* tp->lock is held. */
4565 static int tg3_chip_reset(struct tg3 *tp)
4566 {
4567         u32 val;
4568         void (*write_op)(struct tg3 *, u32, u32);
4569         int i;
4570
4571         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4572                 tg3_nvram_lock(tp);
4573                 /* No matching tg3_nvram_unlock() after this because
4574                  * chip reset below will undo the nvram lock.
4575                  */
4576                 tp->nvram_lock_cnt = 0;
4577         }
4578
4579         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4580             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4581             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4582                 tw32(GRC_FASTBOOT_PC, 0);
4583
4584         /*
4585          * We must avoid the readl() that normally takes place.
4586          * It locks machines, causes machine checks, and other
4587          * fun things.  So, temporarily disable the 5701
4588          * hardware workaround, while we do the reset.
4589          */
4590         write_op = tp->write32;
4591         if (write_op == tg3_write_flush_reg32)
4592                 tp->write32 = tg3_write32;
4593
4594         /* do the reset */
4595         val = GRC_MISC_CFG_CORECLK_RESET;
4596
4597         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4598                 if (tr32(0x7e2c) == 0x60) {
4599                         tw32(0x7e2c, 0x20);
4600                 }
4601                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4602                         tw32(GRC_MISC_CFG, (1 << 29));
4603                         val |= (1 << 29);
4604                 }
4605         }
4606
4607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4608                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4609         tw32(GRC_MISC_CFG, val);
4610
4611         /* restore 5701 hardware bug workaround write method */
4612         tp->write32 = write_op;
4613
4614         /* Unfortunately, we have to delay before the PCI read back.
4615          * Some 575X chips even will not respond to a PCI cfg access
4616          * when the reset command is given to the chip.
4617          *
4618          * How do these hardware designers expect things to work
4619          * properly if the PCI write is posted for a long period
4620          * of time?  It is always necessary to have some method by
4621          * which a register read back can occur to push the write
4622          * out which does the reset.
4623          *
4624          * For most tg3 variants the trick below was working.
4625          * Ho hum...
4626          */
4627         udelay(120);
4628
4629         /* Flush PCI posted writes.  The normal MMIO registers
4630          * are inaccessible at this time so this is the only
4631          * way to make this reliably (actually, this is no longer
4632          * the case, see above).  I tried to use indirect
4633          * register read/write but this upset some 5701 variants.
4634          */
4635         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4636
4637         udelay(120);
4638
4639         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4640                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4641                         int i;
4642                         u32 cfg_val;
4643
4644                         /* Wait for link training to complete.  */
4645                         for (i = 0; i < 5000; i++)
4646                                 udelay(100);
4647
4648                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4649                         pci_write_config_dword(tp->pdev, 0xc4,
4650                                                cfg_val | (1 << 15));
4651                 }
4652                 /* Set PCIE max payload size and clear error status.  */
4653                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4654         }
4655
4656         /* Re-enable indirect register accesses. */
4657         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4658                                tp->misc_host_ctrl);
4659
4660         /* Set MAX PCI retry to zero. */
4661         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4662         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4663             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4664                 val |= PCISTATE_RETRY_SAME_DMA;
4665         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4666
4667         pci_restore_state(tp->pdev);
4668
4669         /* Make sure PCI-X relaxed ordering bit is clear. */
4670         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4671         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4672         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4673
4674         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4675                 u32 val;
4676
4677                 /* Chip reset on 5780 will reset MSI enable bit,
4678                  * so need to restore it.
4679                  */
4680                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4681                         u16 ctrl;
4682
4683                         pci_read_config_word(tp->pdev,
4684                                              tp->msi_cap + PCI_MSI_FLAGS,
4685                                              &ctrl);
4686                         pci_write_config_word(tp->pdev,
4687                                               tp->msi_cap + PCI_MSI_FLAGS,
4688                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4689                         val = tr32(MSGINT_MODE);
4690                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4691                 }
4692
4693                 val = tr32(MEMARB_MODE);
4694                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4695
4696         } else
4697                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4698
4699         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4700                 tg3_stop_fw(tp);
4701                 tw32(0x5000, 0x400);
4702         }
4703
4704         tw32(GRC_MODE, tp->grc_mode);
4705
4706         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4707                 u32 val = tr32(0xc4);
4708
4709                 tw32(0xc4, val | (1 << 15));
4710         }
4711
4712         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4713             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4714                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4715                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4716                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4717                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4718         }
4719
4720         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4721                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4722                 tw32_f(MAC_MODE, tp->mac_mode);
4723         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4724                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4725                 tw32_f(MAC_MODE, tp->mac_mode);
4726         } else
4727                 tw32_f(MAC_MODE, 0);
4728         udelay(40);
4729
4730         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4731                 /* Wait for firmware initialization to complete. */
4732                 for (i = 0; i < 100000; i++) {
4733                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4734                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4735                                 break;
4736                         udelay(10);
4737                 }
4738                 if (i >= 100000) {
4739                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4740                                "firmware will not restart magic=%08x\n",
4741                                tp->dev->name, val);
4742                         return -ENODEV;
4743                 }
4744         }
4745
4746         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4747             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4748                 u32 val = tr32(0x7c00);
4749
4750                 tw32(0x7c00, val | (1 << 25));
4751         }
4752
4753         /* Reprobe ASF enable state.  */
4754         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4755         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4756         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4757         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4758                 u32 nic_cfg;
4759
4760                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4761                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4762                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4763                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4764                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4765                 }
4766         }
4767
4768         return 0;
4769 }
4770
4771 /* tp->lock is held. */
4772 static void tg3_stop_fw(struct tg3 *tp)
4773 {
4774         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4775                 u32 val;
4776                 int i;
4777
4778                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4779                 val = tr32(GRC_RX_CPU_EVENT);
4780                 val |= (1 << 14);
4781                 tw32(GRC_RX_CPU_EVENT, val);
4782
4783                 /* Wait for RX cpu to ACK the event.  */
4784                 for (i = 0; i < 100; i++) {
4785                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4786                                 break;
4787                         udelay(1);
4788                 }
4789         }
4790 }
4791
4792 /* tp->lock is held. */
4793 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4794 {
4795         int err;
4796
4797         tg3_stop_fw(tp);
4798
4799         tg3_write_sig_pre_reset(tp, kind);
4800
4801         tg3_abort_hw(tp, silent);
4802         err = tg3_chip_reset(tp);
4803
4804         tg3_write_sig_legacy(tp, kind);
4805         tg3_write_sig_post_reset(tp, kind);
4806
4807         if (err)
4808                 return err;
4809
4810         return 0;
4811 }
4812
4813 #define TG3_FW_RELEASE_MAJOR    0x0
4814 #define TG3_FW_RELASE_MINOR     0x0
4815 #define TG3_FW_RELEASE_FIX      0x0
4816 #define TG3_FW_START_ADDR       0x08000000
4817 #define TG3_FW_TEXT_ADDR        0x08000000
4818 #define TG3_FW_TEXT_LEN         0x9c0
4819 #define TG3_FW_RODATA_ADDR      0x080009c0
4820 #define TG3_FW_RODATA_LEN       0x60
4821 #define TG3_FW_DATA_ADDR        0x08000a40
4822 #define TG3_FW_DATA_LEN         0x20
4823 #define TG3_FW_SBSS_ADDR        0x08000a60
4824 #define TG3_FW_SBSS_LEN         0xc
4825 #define TG3_FW_BSS_ADDR         0x08000a70
4826 #define TG3_FW_BSS_LEN          0x10
4827
4828 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4829         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4830         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4831         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4832         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4833         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4834         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4835         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4836         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4837         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4838         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4839         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4840         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4841         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4842         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4843         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4844         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4845         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4846         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4847         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4848         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4849         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4850         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4851         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4852         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4853         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4854         0, 0, 0, 0, 0, 0,
4855         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4856         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4857         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4858         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4859         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4860         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4861         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4862         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4863         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4864         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4865         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4866         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4867         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4868         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4869         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4870         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4871         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4872         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4873         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4874         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4875         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4876         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4877         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4878         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4879         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4880         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4881         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4882         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4883         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4884         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4885         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4886         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4887         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4888         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4889         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4890         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4891         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4892         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4893         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4894         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4895         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4896         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4897         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4898         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4899         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4900         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4901         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4902         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4903         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4904         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4905         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4906         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4907         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4908         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4909         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4910         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4911         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4912         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4913         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4914         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4915         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4916         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4917         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4918         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4919         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4920 };
4921
4922 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4923         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4924         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4925         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4926         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4927         0x00000000
4928 };
4929
4930 #if 0 /* All zeros, don't eat up space with it. */
4931 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4932         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4933         0x00000000, 0x00000000, 0x00000000, 0x00000000
4934 };
4935 #endif
4936
4937 #define RX_CPU_SCRATCH_BASE     0x30000
4938 #define RX_CPU_SCRATCH_SIZE     0x04000
4939 #define TX_CPU_SCRATCH_BASE     0x34000
4940 #define TX_CPU_SCRATCH_SIZE     0x04000
4941
4942 /* tp->lock is held. */
4943 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4944 {
4945         int i;
4946
4947         BUG_ON(offset == TX_CPU_BASE &&
4948             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
4949
4950         if (offset == RX_CPU_BASE) {
4951                 for (i = 0; i < 10000; i++) {
4952                         tw32(offset + CPU_STATE, 0xffffffff);
4953                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4954                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4955                                 break;
4956                 }
4957
4958                 tw32(offset + CPU_STATE, 0xffffffff);
4959                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4960                 udelay(10);
4961         } else {
4962                 for (i = 0; i < 10000; i++) {
4963                         tw32(offset + CPU_STATE, 0xffffffff);
4964                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4965                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4966                                 break;
4967                 }
4968         }
4969
4970         if (i >= 10000) {
4971                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4972                        "and %s CPU\n",
4973                        tp->dev->name,
4974                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4975                 return -ENODEV;
4976         }
4977
4978         /* Clear firmware's nvram arbitration. */
4979         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4980                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
4981         return 0;
4982 }
4983
4984 struct fw_info {
4985         unsigned int text_base;
4986         unsigned int text_len;
4987         u32 *text_data;
4988         unsigned int rodata_base;
4989         unsigned int rodata_len;
4990         u32 *rodata_data;
4991         unsigned int data_base;
4992         unsigned int data_len;
4993         u32 *data_data;
4994 };
4995
4996 /* tp->lock is held. */
4997 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4998                                  int cpu_scratch_size, struct fw_info *info)
4999 {
5000         int err, lock_err, i;
5001         void (*write_op)(struct tg3 *, u32, u32);
5002
5003         if (cpu_base == TX_CPU_BASE &&
5004             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5005                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5006                        "TX cpu firmware on %s which is 5705.\n",
5007                        tp->dev->name);
5008                 return -EINVAL;
5009         }
5010
5011         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5012                 write_op = tg3_write_mem;
5013         else
5014                 write_op = tg3_write_indirect_reg32;
5015
5016         /* It is possible that bootcode is still loading at this point.
5017          * Get the nvram lock first before halting the cpu.
5018          */
5019         lock_err = tg3_nvram_lock(tp);
5020         err = tg3_halt_cpu(tp, cpu_base);
5021         if (!lock_err)
5022                 tg3_nvram_unlock(tp);
5023         if (err)
5024                 goto out;
5025
5026         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5027                 write_op(tp, cpu_scratch_base + i, 0);
5028         tw32(cpu_base + CPU_STATE, 0xffffffff);
5029         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5030         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5031                 write_op(tp, (cpu_scratch_base +
5032                               (info->text_base & 0xffff) +
5033                               (i * sizeof(u32))),
5034                          (info->text_data ?
5035                           info->text_data[i] : 0));
5036         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5037                 write_op(tp, (cpu_scratch_base +
5038                               (info->rodata_base & 0xffff) +
5039                               (i * sizeof(u32))),
5040                          (info->rodata_data ?
5041                           info->rodata_data[i] : 0));
5042         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5043                 write_op(tp, (cpu_scratch_base +
5044                               (info->data_base & 0xffff) +
5045                               (i * sizeof(u32))),
5046                          (info->data_data ?
5047                           info->data_data[i] : 0));
5048
5049         err = 0;
5050
5051 out:
5052         return err;
5053 }
5054
5055 /* tp->lock is held. */
5056 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5057 {
5058         struct fw_info info;
5059         int err, i;
5060
5061         info.text_base = TG3_FW_TEXT_ADDR;
5062         info.text_len = TG3_FW_TEXT_LEN;
5063         info.text_data = &tg3FwText[0];
5064         info.rodata_base = TG3_FW_RODATA_ADDR;
5065         info.rodata_len = TG3_FW_RODATA_LEN;
5066         info.rodata_data = &tg3FwRodata[0];
5067         info.data_base = TG3_FW_DATA_ADDR;
5068         info.data_len = TG3_FW_DATA_LEN;
5069         info.data_data = NULL;
5070
5071         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5072                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5073                                     &info);
5074         if (err)
5075                 return err;
5076
5077         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5078                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5079                                     &info);
5080         if (err)
5081                 return err;
5082
5083         /* Now startup only the RX cpu. */
5084         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5085         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5086
5087         for (i = 0; i < 5; i++) {
5088                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5089                         break;
5090                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5091                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5092                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5093                 udelay(1000);
5094         }
5095         if (i >= 5) {
5096                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5097                        "to set RX CPU PC, is %08x should be %08x\n",
5098                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5099                        TG3_FW_TEXT_ADDR);
5100                 return -ENODEV;
5101         }
5102         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5103         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5104
5105         return 0;
5106 }
5107
5108 #if TG3_TSO_SUPPORT != 0
5109
5110 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5111 #define TG3_TSO_FW_RELASE_MINOR         0x6
5112 #define TG3_TSO_FW_RELEASE_FIX          0x0
5113 #define TG3_TSO_FW_START_ADDR           0x08000000
5114 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5115 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5116 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5117 #define TG3_TSO_FW_RODATA_LEN           0x60
5118 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5119 #define TG3_TSO_FW_DATA_LEN             0x30
5120 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5121 #define TG3_TSO_FW_SBSS_LEN             0x2c
5122 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5123 #define TG3_TSO_FW_BSS_LEN              0x894
5124
5125 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5126         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5127         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5128         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5129         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5130         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5131         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5132         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5133         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5134         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5135         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5136         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5137         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5138         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5139         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5140         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5141         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5142         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5143         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5144         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5145         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5146         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5147         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5148         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5149         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5150         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5151         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5152         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5153         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5154         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5155         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5156         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5157         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5158         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5159         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5160         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5161         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5162         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5163         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5164         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5165         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5166         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5167         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5168         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5169         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5170         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5171         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5172         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5173         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5174         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5175         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5176         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5177         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5178         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5179         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5180         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5181         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5182         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5183         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5184         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5185         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5186         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5187         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5188         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5189         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5190         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5191         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5192         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5193         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5194         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5195         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5196         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5197         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5198         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5199         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5200         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5201         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5202         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5203         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5204         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5205         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5206         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5207         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5208         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5209         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5210         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5211         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5212         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5213         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5214         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5215         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5216         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5217         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5218         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5219         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5220         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5221         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5222         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5223         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5224         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5225         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5226         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5227         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5228         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5229         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5230         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5231         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5232         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5233         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5234         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5235         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5236         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5237         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5238         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5239         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5240         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5241         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5242         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5243         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5244         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5245         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5246         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5247         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5248         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5249         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5250         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5251         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5252         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5253         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5254         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5255         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5256         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5257         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5258         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5259         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5260         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5261         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5262         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5263         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5264         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5265         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5266         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5267         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5268         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5269         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5270         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5271         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5272         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5273         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5274         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5275         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5276         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5277         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5278         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5279         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5280         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5281         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5282         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5283         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5284         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5285         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5286         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5287         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5288         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5289         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5290         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5291         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5292         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5293         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5294         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5295         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5296         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5297         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5298         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5299         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5300         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5301         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5302         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5303         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5304         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5305         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5306         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5307         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5308         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5309         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5310         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5311         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5312         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5313         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5314         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5315         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5316         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5317         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5318         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5319         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5320         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5321         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5322         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5323         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5324         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5325         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5326         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5327         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5328         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5329         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5330         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5331         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5332         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5333         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5334         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5335         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5336         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5337         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5338         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5339         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5340         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5341         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5342         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5343         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5344         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5345         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5346         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5347         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5348         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5349         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5350         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5351         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5352         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5353         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5354         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5355         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5356         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5357         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5358         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5359         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5360         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5361         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5362         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5363         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5364         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5365         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5366         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5367         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5368         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5369         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5370         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5371         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5372         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5373         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5374         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5375         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5376         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5377         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5378         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5379         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5380         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5381         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5382         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5383         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5384         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5385         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5386         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5387         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5388         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5389         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5390         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5391         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5392         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5393         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5394         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5395         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5396         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5397         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5398         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5399         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5400         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5401         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5402         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5403         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5404         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5405         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5406         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5407         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5408         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5409         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5410 };
5411
5412 static u32 tg3TsoFwRodata[] = {
5413         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5414         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5415         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5416         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5417         0x00000000,
5418 };
5419
5420 static u32 tg3TsoFwData[] = {
5421         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5422         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5423         0x00000000,
5424 };
5425
5426 /* 5705 needs a special version of the TSO firmware.  */
5427 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5428 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5429 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5430 #define TG3_TSO5_FW_START_ADDR          0x00010000
5431 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5432 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5433 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5434 #define TG3_TSO5_FW_RODATA_LEN          0x50
5435 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5436 #define TG3_TSO5_FW_DATA_LEN            0x20
5437 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5438 #define TG3_TSO5_FW_SBSS_LEN            0x28
5439 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5440 #define TG3_TSO5_FW_BSS_LEN             0x88
5441
5442 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5443         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5444         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5445         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5446         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5447         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5448         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5449         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5450         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5451         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5452         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5453         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5454         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5455         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5456         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5457         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5458         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5459         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5460         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5461         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5462         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5463         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5464         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5465         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5466         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5467         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5468         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5469         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5470         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5471         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5472         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5473         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5474         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5475         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5476         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5477         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5478         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5479         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5480         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5481         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5482         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5483         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5484         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5485         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5486         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5487         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5488         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5489         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5490         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5491         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5492         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5493         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5494         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5495         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5496         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5497         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5498         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5499         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5500         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5501         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5502         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5503         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5504         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5505         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5506         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5507         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5508         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5509         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5510         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5511         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5512         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5513         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5514         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5515         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5516         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5517         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5518         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5519         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5520         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5521         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5522         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5523         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5524         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5525         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5526         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5527         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5528         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5529         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5530         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5531         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5532         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5533         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5534         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5535         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5536         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5537         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5538         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5539         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5540         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5541         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5542         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5543         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5544         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5545         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5546         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5547         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5548         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5549         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5550         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5551         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5552         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5553         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5554         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5555         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5556         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5557         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5558         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5559         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5560         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5561         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5562         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5563         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5564         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5565         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5566         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5567         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5568         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5569         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5570         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5571         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5572         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5573         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5574         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5575         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5576         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5577         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5578         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5579         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5580         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5581         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5582         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5583         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5584         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5585         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5586         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5587         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5588         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5589         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5590         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5591         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5592         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5593         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5594         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5595         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5596         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5597         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5598         0x00000000, 0x00000000, 0x00000000,
5599 };
5600
5601 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5602         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5603         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5604         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5605         0x00000000, 0x00000000, 0x00000000,
5606 };
5607
5608 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5609         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5610         0x00000000, 0x00000000, 0x00000000,
5611 };
5612
5613 /* tp->lock is held. */
5614 static int tg3_load_tso_firmware(struct tg3 *tp)
5615 {
5616         struct fw_info info;
5617         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5618         int err, i;
5619
5620         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5621                 return 0;
5622
5623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5624                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5625                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5626                 info.text_data = &tg3Tso5FwText[0];
5627                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5628                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5629                 info.rodata_data = &tg3Tso5FwRodata[0];
5630                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5631                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5632                 info.data_data = &tg3Tso5FwData[0];
5633                 cpu_base = RX_CPU_BASE;
5634                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5635                 cpu_scratch_size = (info.text_len +
5636                                     info.rodata_len +
5637                                     info.data_len +
5638                                     TG3_TSO5_FW_SBSS_LEN +
5639                                     TG3_TSO5_FW_BSS_LEN);
5640         } else {
5641                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5642                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5643                 info.text_data = &tg3TsoFwText[0];
5644                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5645                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5646                 info.rodata_data = &tg3TsoFwRodata[0];
5647                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5648                 info.data_len = TG3_TSO_FW_DATA_LEN;
5649                 info.data_data = &tg3TsoFwData[0];
5650                 cpu_base = TX_CPU_BASE;
5651                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5652                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5653         }
5654
5655         err = tg3_load_firmware_cpu(tp, cpu_base,
5656                                     cpu_scratch_base, cpu_scratch_size,
5657                                     &info);
5658         if (err)
5659                 return err;
5660
5661         /* Now startup the cpu. */
5662         tw32(cpu_base + CPU_STATE, 0xffffffff);
5663         tw32_f(cpu_base + CPU_PC,    info.text_base);
5664
5665         for (i = 0; i < 5; i++) {
5666                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5667                         break;
5668                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5669                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5670                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5671                 udelay(1000);
5672         }
5673         if (i >= 5) {
5674                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5675                        "to set CPU PC, is %08x should be %08x\n",
5676                        tp->dev->name, tr32(cpu_base + CPU_PC),
5677                        info.text_base);
5678                 return -ENODEV;
5679         }
5680         tw32(cpu_base + CPU_STATE, 0xffffffff);
5681         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5682         return 0;
5683 }
5684
5685 #endif /* TG3_TSO_SUPPORT != 0 */
5686
5687 /* tp->lock is held. */
5688 static void __tg3_set_mac_addr(struct tg3 *tp)
5689 {
5690         u32 addr_high, addr_low;
5691         int i;
5692
5693         addr_high = ((tp->dev->dev_addr[0] << 8) |
5694                      tp->dev->dev_addr[1]);
5695         addr_low = ((tp->dev->dev_addr[2] << 24) |
5696                     (tp->dev->dev_addr[3] << 16) |
5697                     (tp->dev->dev_addr[4] <<  8) |
5698                     (tp->dev->dev_addr[5] <<  0));
5699         for (i = 0; i < 4; i++) {
5700                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5701                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5702         }
5703
5704         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5705             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5706                 for (i = 0; i < 12; i++) {
5707                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5708                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5709                 }
5710         }
5711
5712         addr_high = (tp->dev->dev_addr[0] +
5713                      tp->dev->dev_addr[1] +
5714                      tp->dev->dev_addr[2] +
5715                      tp->dev->dev_addr[3] +
5716                      tp->dev->dev_addr[4] +
5717                      tp->dev->dev_addr[5]) &
5718                 TX_BACKOFF_SEED_MASK;
5719         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5720 }
5721
5722 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5723 {
5724         struct tg3 *tp = netdev_priv(dev);
5725         struct sockaddr *addr = p;
5726
5727         if (!is_valid_ether_addr(addr->sa_data))
5728                 return -EINVAL;
5729
5730         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5731
5732         if (!netif_running(dev))
5733                 return 0;
5734
5735         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5736                 /* Reset chip so that ASF can re-init any MAC addresses it
5737                  * needs.
5738                  */
5739                 tg3_netif_stop(tp);
5740                 tg3_full_lock(tp, 1);
5741
5742                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5743                 tg3_init_hw(tp, 0);
5744
5745                 tg3_netif_start(tp);
5746                 tg3_full_unlock(tp);
5747         } else {
5748                 spin_lock_bh(&tp->lock);
5749                 __tg3_set_mac_addr(tp);
5750                 spin_unlock_bh(&tp->lock);
5751         }
5752
5753         return 0;
5754 }
5755
5756 /* tp->lock is held. */
5757 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5758                            dma_addr_t mapping, u32 maxlen_flags,
5759                            u32 nic_addr)
5760 {
5761         tg3_write_mem(tp,
5762                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5763                       ((u64) mapping >> 32));
5764         tg3_write_mem(tp,
5765                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5766                       ((u64) mapping & 0xffffffff));
5767         tg3_write_mem(tp,
5768                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5769                        maxlen_flags);
5770
5771         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5772                 tg3_write_mem(tp,
5773                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5774                               nic_addr);
5775 }
5776
5777 static void __tg3_set_rx_mode(struct net_device *);
5778 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5779 {
5780         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5781         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5782         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5783         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5784         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5785                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5786                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5787         }
5788         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5789         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5790         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5791                 u32 val = ec->stats_block_coalesce_usecs;
5792
5793                 if (!netif_carrier_ok(tp->dev))
5794                         val = 0;
5795
5796                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5797         }
5798 }
5799
5800 /* tp->lock is held. */
5801 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5802 {
5803         u32 val, rdmac_mode;
5804         int i, err, limit;
5805
5806         tg3_disable_ints(tp);
5807
5808         tg3_stop_fw(tp);
5809
5810         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5811
5812         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5813                 tg3_abort_hw(tp, 1);
5814         }
5815
5816         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5817                 tg3_phy_reset(tp);
5818
5819         err = tg3_chip_reset(tp);
5820         if (err)
5821                 return err;
5822
5823         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5824
5825         /* This works around an issue with Athlon chipsets on
5826          * B3 tigon3 silicon.  This bit has no effect on any
5827          * other revision.  But do not set this on PCI Express
5828          * chips.
5829          */
5830         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5831                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5832         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5833
5834         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5835             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5836                 val = tr32(TG3PCI_PCISTATE);
5837                 val |= PCISTATE_RETRY_SAME_DMA;
5838                 tw32(TG3PCI_PCISTATE, val);
5839         }
5840
5841         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5842                 /* Enable some hw fixes.  */
5843                 val = tr32(TG3PCI_MSI_DATA);
5844                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5845                 tw32(TG3PCI_MSI_DATA, val);
5846         }
5847
5848         /* Descriptor ring init may make accesses to the
5849          * NIC SRAM area to setup the TX descriptors, so we
5850          * can only do this after the hardware has been
5851          * successfully reset.
5852          */
5853         tg3_init_rings(tp);
5854
5855         /* This value is determined during the probe time DMA
5856          * engine test, tg3_test_dma.
5857          */
5858         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5859
5860         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5861                           GRC_MODE_4X_NIC_SEND_RINGS |
5862                           GRC_MODE_NO_TX_PHDR_CSUM |
5863                           GRC_MODE_NO_RX_PHDR_CSUM);
5864         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5865
5866         /* Pseudo-header checksum is done by hardware logic and not
5867          * the offload processers, so make the chip do the pseudo-
5868          * header checksums on receive.  For transmit it is more
5869          * convenient to do the pseudo-header checksum in software
5870          * as Linux does that on transmit for us in all cases.
5871          */
5872         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5873
5874         tw32(GRC_MODE,
5875              tp->grc_mode |
5876              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5877
5878         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5879         val = tr32(GRC_MISC_CFG);
5880         val &= ~0xff;
5881         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5882         tw32(GRC_MISC_CFG, val);
5883
5884         /* Initialize MBUF/DESC pool. */
5885         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5886                 /* Do nothing.  */
5887         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5888                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5889                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5890                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5891                 else
5892                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5893                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5894                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5895         }
5896 #if TG3_TSO_SUPPORT != 0
5897         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5898                 int fw_len;
5899
5900                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5901                           TG3_TSO5_FW_RODATA_LEN +
5902                           TG3_TSO5_FW_DATA_LEN +
5903                           TG3_TSO5_FW_SBSS_LEN +
5904                           TG3_TSO5_FW_BSS_LEN);
5905                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5906                 tw32(BUFMGR_MB_POOL_ADDR,
5907                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5908                 tw32(BUFMGR_MB_POOL_SIZE,
5909                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5910         }
5911 #endif
5912
5913         if (tp->dev->mtu <= ETH_DATA_LEN) {
5914                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5915                      tp->bufmgr_config.mbuf_read_dma_low_water);
5916                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5917                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5918                 tw32(BUFMGR_MB_HIGH_WATER,
5919                      tp->bufmgr_config.mbuf_high_water);
5920         } else {
5921                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5922                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5923                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5924                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5925                 tw32(BUFMGR_MB_HIGH_WATER,
5926                      tp->bufmgr_config.mbuf_high_water_jumbo);
5927         }
5928         tw32(BUFMGR_DMA_LOW_WATER,
5929              tp->bufmgr_config.dma_low_water);
5930         tw32(BUFMGR_DMA_HIGH_WATER,
5931              tp->bufmgr_config.dma_high_water);
5932
5933         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5934         for (i = 0; i < 2000; i++) {
5935                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5936                         break;
5937                 udelay(10);
5938         }
5939         if (i >= 2000) {
5940                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5941                        tp->dev->name);
5942                 return -ENODEV;
5943         }
5944
5945         /* Setup replenish threshold. */
5946         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5947
5948         /* Initialize TG3_BDINFO's at:
5949          *  RCVDBDI_STD_BD:     standard eth size rx ring
5950          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5951          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5952          *
5953          * like so:
5954          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5955          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5956          *                              ring attribute flags
5957          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5958          *
5959          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5960          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5961          *
5962          * The size of each ring is fixed in the firmware, but the location is
5963          * configurable.
5964          */
5965         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5966              ((u64) tp->rx_std_mapping >> 32));
5967         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5968              ((u64) tp->rx_std_mapping & 0xffffffff));
5969         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5970              NIC_SRAM_RX_BUFFER_DESC);
5971
5972         /* Don't even try to program the JUMBO/MINI buffer descriptor
5973          * configs on 5705.
5974          */
5975         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5976                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5977                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5978         } else {
5979                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5980                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5981
5982                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5983                      BDINFO_FLAGS_DISABLED);
5984
5985                 /* Setup replenish threshold. */
5986                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5987
5988                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5989                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5990                              ((u64) tp->rx_jumbo_mapping >> 32));
5991                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5992                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5993                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5994                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5995                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5996                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5997                 } else {
5998                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5999                              BDINFO_FLAGS_DISABLED);
6000                 }
6001
6002         }
6003
6004         /* There is only one send ring on 5705/5750, no need to explicitly
6005          * disable the others.
6006          */
6007         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6008                 /* Clear out send RCB ring in SRAM. */
6009                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6010                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6011                                       BDINFO_FLAGS_DISABLED);
6012         }
6013
6014         tp->tx_prod = 0;
6015         tp->tx_cons = 0;
6016         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6017         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6018
6019         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6020                        tp->tx_desc_mapping,
6021                        (TG3_TX_RING_SIZE <<
6022                         BDINFO_FLAGS_MAXLEN_SHIFT),
6023                        NIC_SRAM_TX_BUFFER_DESC);
6024
6025         /* There is only one receive return ring on 5705/5750, no need
6026          * to explicitly disable the others.
6027          */
6028         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6029                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6030                      i += TG3_BDINFO_SIZE) {
6031                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6032                                       BDINFO_FLAGS_DISABLED);
6033                 }
6034         }
6035
6036         tp->rx_rcb_ptr = 0;
6037         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6038
6039         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6040                        tp->rx_rcb_mapping,
6041                        (TG3_RX_RCB_RING_SIZE(tp) <<
6042                         BDINFO_FLAGS_MAXLEN_SHIFT),
6043                        0);
6044
6045         tp->rx_std_ptr = tp->rx_pending;
6046         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6047                      tp->rx_std_ptr);
6048
6049         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6050                                                 tp->rx_jumbo_pending : 0;
6051         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6052                      tp->rx_jumbo_ptr);
6053
6054         /* Initialize MAC address and backoff seed. */
6055         __tg3_set_mac_addr(tp);
6056
6057         /* MTU + ethernet header + FCS + optional VLAN tag */
6058         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6059
6060         /* The slot time is changed by tg3_setup_phy if we
6061          * run at gigabit with half duplex.
6062          */
6063         tw32(MAC_TX_LENGTHS,
6064              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6065              (6 << TX_LENGTHS_IPG_SHIFT) |
6066              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6067
6068         /* Receive rules. */
6069         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6070         tw32(RCVLPC_CONFIG, 0x0181);
6071
6072         /* Calculate RDMAC_MODE setting early, we need it to determine
6073          * the RCVLPC_STATE_ENABLE mask.
6074          */
6075         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6076                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6077                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6078                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6079                       RDMAC_MODE_LNGREAD_ENAB);
6080         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6081                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6082
6083         /* If statement applies to 5705 and 5750 PCI devices only */
6084         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6085              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6086             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6087                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6088                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6089                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6090                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6091                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6092                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6093                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6094                 }
6095         }
6096
6097         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6098                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6099
6100 #if TG3_TSO_SUPPORT != 0
6101         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6102                 rdmac_mode |= (1 << 27);
6103 #endif
6104
6105         /* Receive/send statistics. */
6106         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6107             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6108                 val = tr32(RCVLPC_STATS_ENABLE);
6109                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6110                 tw32(RCVLPC_STATS_ENABLE, val);
6111         } else {
6112                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6113         }
6114         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6115         tw32(SNDDATAI_STATSENAB, 0xffffff);
6116         tw32(SNDDATAI_STATSCTRL,
6117              (SNDDATAI_SCTRL_ENABLE |
6118               SNDDATAI_SCTRL_FASTUPD));
6119
6120         /* Setup host coalescing engine. */
6121         tw32(HOSTCC_MODE, 0);
6122         for (i = 0; i < 2000; i++) {
6123                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6124                         break;
6125                 udelay(10);
6126         }
6127
6128         __tg3_set_coalesce(tp, &tp->coal);
6129
6130         /* set status block DMA address */
6131         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6132              ((u64) tp->status_mapping >> 32));
6133         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6134              ((u64) tp->status_mapping & 0xffffffff));
6135
6136         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6137                 /* Status/statistics block address.  See tg3_timer,
6138                  * the tg3_periodic_fetch_stats call there, and
6139                  * tg3_get_stats to see how this works for 5705/5750 chips.
6140                  */
6141                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6142                      ((u64) tp->stats_mapping >> 32));
6143                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6144                      ((u64) tp->stats_mapping & 0xffffffff));
6145                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6146                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6147         }
6148
6149         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6150
6151         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6152         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6153         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6154                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6155
6156         /* Clear statistics/status block in chip, and status block in ram. */
6157         for (i = NIC_SRAM_STATS_BLK;
6158              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6159              i += sizeof(u32)) {
6160                 tg3_write_mem(tp, i, 0);
6161                 udelay(40);
6162         }
6163         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6164
6165         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6166                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6167                 /* reset to prevent losing 1st rx packet intermittently */
6168                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6169                 udelay(10);
6170         }
6171
6172         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6173                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6174         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6175         udelay(40);
6176
6177         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6178          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6179          * register to preserve the GPIO settings for LOMs. The GPIOs,
6180          * whether used as inputs or outputs, are set by boot code after
6181          * reset.
6182          */
6183         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6184                 u32 gpio_mask;
6185
6186                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6187                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6188
6189                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6190                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6191                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6192
6193                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6194                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6195
6196                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6197
6198                 /* GPIO1 must be driven high for eeprom write protect */
6199                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6200                                        GRC_LCLCTRL_GPIO_OUTPUT1);
6201         }
6202         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6203         udelay(100);
6204
6205         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6206         tp->last_tag = 0;
6207
6208         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6209                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6210                 udelay(40);
6211         }
6212
6213         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6214                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6215                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6216                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6217                WDMAC_MODE_LNGREAD_ENAB);
6218
6219         /* If statement applies to 5705 and 5750 PCI devices only */
6220         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6221              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6222             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6223                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6224                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6225                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6226                         /* nothing */
6227                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6228                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6229                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6230                         val |= WDMAC_MODE_RX_ACCEL;
6231                 }
6232         }
6233
6234         /* Enable host coalescing bug fix */
6235         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6236             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6237                 val |= (1 << 29);
6238
6239         tw32_f(WDMAC_MODE, val);
6240         udelay(40);
6241
6242         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6243                 val = tr32(TG3PCI_X_CAPS);
6244                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6245                         val &= ~PCIX_CAPS_BURST_MASK;
6246                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6247                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6248                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6249                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6250                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6251                                 val |= (tp->split_mode_max_reqs <<
6252                                         PCIX_CAPS_SPLIT_SHIFT);
6253                 }
6254                 tw32(TG3PCI_X_CAPS, val);
6255         }
6256
6257         tw32_f(RDMAC_MODE, rdmac_mode);
6258         udelay(40);
6259
6260         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6261         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6262                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6263         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6264         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6265         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6266         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6267         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6268 #if TG3_TSO_SUPPORT != 0
6269         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6270                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6271 #endif
6272         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6273         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6274
6275         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6276                 err = tg3_load_5701_a0_firmware_fix(tp);
6277                 if (err)
6278                         return err;
6279         }
6280
6281 #if TG3_TSO_SUPPORT != 0
6282         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6283                 err = tg3_load_tso_firmware(tp);
6284                 if (err)
6285                         return err;
6286         }
6287 #endif
6288
6289         tp->tx_mode = TX_MODE_ENABLE;
6290         tw32_f(MAC_TX_MODE, tp->tx_mode);
6291         udelay(100);
6292
6293         tp->rx_mode = RX_MODE_ENABLE;
6294         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6295                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6296
6297         tw32_f(MAC_RX_MODE, tp->rx_mode);
6298         udelay(10);
6299
6300         if (tp->link_config.phy_is_low_power) {
6301                 tp->link_config.phy_is_low_power = 0;
6302                 tp->link_config.speed = tp->link_config.orig_speed;
6303                 tp->link_config.duplex = tp->link_config.orig_duplex;
6304                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6305         }
6306
6307         tp->mi_mode = MAC_MI_MODE_BASE;
6308         tw32_f(MAC_MI_MODE, tp->mi_mode);
6309         udelay(80);
6310
6311         tw32(MAC_LED_CTRL, tp->led_ctrl);
6312
6313         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6314         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6315                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6316                 udelay(10);
6317         }
6318         tw32_f(MAC_RX_MODE, tp->rx_mode);
6319         udelay(10);
6320
6321         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6322                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6323                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6324                         /* Set drive transmission level to 1.2V  */
6325                         /* only if the signal pre-emphasis bit is not set  */
6326                         val = tr32(MAC_SERDES_CFG);
6327                         val &= 0xfffff000;
6328                         val |= 0x880;
6329                         tw32(MAC_SERDES_CFG, val);
6330                 }
6331                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6332                         tw32(MAC_SERDES_CFG, 0x616000);
6333         }
6334
6335         /* Prevent chip from dropping frames when flow control
6336          * is enabled.
6337          */
6338         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6339
6340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6341             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6342                 /* Use hardware link auto-negotiation */
6343                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6344         }
6345
6346         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6347             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6348                 u32 tmp;
6349
6350                 tmp = tr32(SERDES_RX_CTRL);
6351                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6352                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6353                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6354                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6355         }
6356
6357         err = tg3_setup_phy(tp, reset_phy);
6358         if (err)
6359                 return err;
6360
6361         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6362                 u32 tmp;
6363
6364                 /* Clear CRC stats. */
6365                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6366                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6367                         tg3_readphy(tp, 0x14, &tmp);
6368                 }
6369         }
6370
6371         __tg3_set_rx_mode(tp->dev);
6372
6373         /* Initialize receive rules. */
6374         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6375         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6376         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6377         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6378
6379         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6380             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6381                 limit = 8;
6382         else
6383                 limit = 16;
6384         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6385                 limit -= 4;
6386         switch (limit) {
6387         case 16:
6388                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6389         case 15:
6390                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6391         case 14:
6392                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6393         case 13:
6394                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6395         case 12:
6396                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6397         case 11:
6398                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6399         case 10:
6400                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6401         case 9:
6402                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6403         case 8:
6404                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6405         case 7:
6406                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6407         case 6:
6408                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6409         case 5:
6410                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6411         case 4:
6412                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6413         case 3:
6414                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6415         case 2:
6416         case 1:
6417
6418         default:
6419                 break;
6420         };
6421
6422         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6423
6424         return 0;
6425 }
6426
6427 /* Called at device open time to get the chip ready for
6428  * packet processing.  Invoked with tp->lock held.
6429  */
6430 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6431 {
6432         int err;
6433
6434         /* Force the chip into D0. */
6435         err = tg3_set_power_state(tp, PCI_D0);
6436         if (err)
6437                 goto out;
6438
6439         tg3_switch_clocks(tp);
6440
6441         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6442
6443         err = tg3_reset_hw(tp, reset_phy);
6444
6445 out:
6446         return err;
6447 }
6448
6449 #define TG3_STAT_ADD32(PSTAT, REG) \
6450 do {    u32 __val = tr32(REG); \
6451         (PSTAT)->low += __val; \
6452         if ((PSTAT)->low < __val) \
6453                 (PSTAT)->high += 1; \
6454 } while (0)
6455
6456 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6457 {
6458         struct tg3_hw_stats *sp = tp->hw_stats;
6459
6460         if (!netif_carrier_ok(tp->dev))
6461                 return;
6462
6463         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6464         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6465         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6466         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6467         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6468         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6469         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6470         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6471         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6472         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6473         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6474         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6475         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6476
6477         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6478         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6479         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6480         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6481         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6482         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6483         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6484         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6485         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6486         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6487         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6488         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6489         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6490         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6491 }
6492
6493 static void tg3_timer(unsigned long __opaque)
6494 {
6495         struct tg3 *tp = (struct tg3 *) __opaque;
6496
6497         if (tp->irq_sync)
6498                 goto restart_timer;
6499
6500         spin_lock(&tp->lock);
6501
6502         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6503                 /* All of this garbage is because when using non-tagged
6504                  * IRQ status the mailbox/status_block protocol the chip
6505                  * uses with the cpu is race prone.
6506                  */
6507                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6508                         tw32(GRC_LOCAL_CTRL,
6509                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6510                 } else {
6511                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6512                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6513                 }
6514
6515                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6516                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6517                         spin_unlock(&tp->lock);
6518                         schedule_work(&tp->reset_task);
6519                         return;
6520                 }
6521         }
6522
6523         /* This part only runs once per second. */
6524         if (!--tp->timer_counter) {
6525                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6526                         tg3_periodic_fetch_stats(tp);
6527
6528                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6529                         u32 mac_stat;
6530                         int phy_event;
6531
6532                         mac_stat = tr32(MAC_STATUS);
6533
6534                         phy_event = 0;
6535                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6536                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6537                                         phy_event = 1;
6538                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6539                                 phy_event = 1;
6540
6541                         if (phy_event)
6542                                 tg3_setup_phy(tp, 0);
6543                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6544                         u32 mac_stat = tr32(MAC_STATUS);
6545                         int need_setup = 0;
6546
6547                         if (netif_carrier_ok(tp->dev) &&
6548                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6549                                 need_setup = 1;
6550                         }
6551                         if (! netif_carrier_ok(tp->dev) &&
6552                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6553                                          MAC_STATUS_SIGNAL_DET))) {
6554                                 need_setup = 1;
6555                         }
6556                         if (need_setup) {
6557                                 tw32_f(MAC_MODE,
6558                                      (tp->mac_mode &
6559                                       ~MAC_MODE_PORT_MODE_MASK));
6560                                 udelay(40);
6561                                 tw32_f(MAC_MODE, tp->mac_mode);
6562                                 udelay(40);
6563                                 tg3_setup_phy(tp, 0);
6564                         }
6565                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6566                         tg3_serdes_parallel_detect(tp);
6567
6568                 tp->timer_counter = tp->timer_multiplier;
6569         }
6570
6571         /* Heartbeat is only sent once every 2 seconds.  */
6572         if (!--tp->asf_counter) {
6573                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6574                         u32 val;
6575
6576                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6577                                       FWCMD_NICDRV_ALIVE2);
6578                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6579                         /* 5 seconds timeout */
6580                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6581                         val = tr32(GRC_RX_CPU_EVENT);
6582                         val |= (1 << 14);
6583                         tw32(GRC_RX_CPU_EVENT, val);
6584                 }
6585                 tp->asf_counter = tp->asf_multiplier;
6586         }
6587
6588         spin_unlock(&tp->lock);
6589
6590 restart_timer:
6591         tp->timer.expires = jiffies + tp->timer_offset;
6592         add_timer(&tp->timer);
6593 }
6594
6595 static int tg3_request_irq(struct tg3 *tp)
6596 {
6597         irqreturn_t (*fn)(int, void *, struct pt_regs *);
6598         unsigned long flags;
6599         struct net_device *dev = tp->dev;
6600
6601         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6602                 fn = tg3_msi;
6603                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6604                         fn = tg3_msi_1shot;
6605                 flags = SA_SAMPLE_RANDOM;
6606         } else {
6607                 fn = tg3_interrupt;
6608                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6609                         fn = tg3_interrupt_tagged;
6610                 flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
6611         }
6612         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6613 }
6614
6615 static int tg3_test_interrupt(struct tg3 *tp)
6616 {
6617         struct net_device *dev = tp->dev;
6618         int err, i;
6619         u32 int_mbox = 0;
6620
6621         if (!netif_running(dev))
6622                 return -ENODEV;
6623
6624         tg3_disable_ints(tp);
6625
6626         free_irq(tp->pdev->irq, dev);
6627
6628         err = request_irq(tp->pdev->irq, tg3_test_isr,
6629                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6630         if (err)
6631                 return err;
6632
6633         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6634         tg3_enable_ints(tp);
6635
6636         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6637                HOSTCC_MODE_NOW);
6638
6639         for (i = 0; i < 5; i++) {
6640                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6641                                         TG3_64BIT_REG_LOW);
6642                 if (int_mbox != 0)
6643                         break;
6644                 msleep(10);
6645         }
6646
6647         tg3_disable_ints(tp);
6648
6649         free_irq(tp->pdev->irq, dev);
6650
6651         err = tg3_request_irq(tp);
6652
6653         if (err)
6654                 return err;
6655
6656         if (int_mbox != 0)
6657                 return 0;
6658
6659         return -EIO;
6660 }
6661
6662 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6663  * successfully restored
6664  */
6665 static int tg3_test_msi(struct tg3 *tp)
6666 {
6667         struct net_device *dev = tp->dev;
6668         int err;
6669         u16 pci_cmd;
6670
6671         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6672                 return 0;
6673
6674         /* Turn off SERR reporting in case MSI terminates with Master
6675          * Abort.
6676          */
6677         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6678         pci_write_config_word(tp->pdev, PCI_COMMAND,
6679                               pci_cmd & ~PCI_COMMAND_SERR);
6680
6681         err = tg3_test_interrupt(tp);
6682
6683         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6684
6685         if (!err)
6686                 return 0;
6687
6688         /* other failures */
6689         if (err != -EIO)
6690                 return err;
6691
6692         /* MSI test failed, go back to INTx mode */
6693         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6694                "switching to INTx mode. Please report this failure to "
6695                "the PCI maintainer and include system chipset information.\n",
6696                        tp->dev->name);
6697
6698         free_irq(tp->pdev->irq, dev);
6699         pci_disable_msi(tp->pdev);
6700
6701         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6702
6703         err = tg3_request_irq(tp);
6704         if (err)
6705                 return err;
6706
6707         /* Need to reset the chip because the MSI cycle may have terminated
6708          * with Master Abort.
6709          */
6710         tg3_full_lock(tp, 1);
6711
6712         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6713         err = tg3_init_hw(tp, 1);
6714
6715         tg3_full_unlock(tp);
6716
6717         if (err)
6718                 free_irq(tp->pdev->irq, dev);
6719
6720         return err;
6721 }
6722
6723 static int tg3_open(struct net_device *dev)
6724 {
6725         struct tg3 *tp = netdev_priv(dev);
6726         int err;
6727
6728         tg3_full_lock(tp, 0);
6729
6730         err = tg3_set_power_state(tp, PCI_D0);
6731         if (err)
6732                 return err;
6733
6734         tg3_disable_ints(tp);
6735         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6736
6737         tg3_full_unlock(tp);
6738
6739         /* The placement of this call is tied
6740          * to the setup and use of Host TX descriptors.
6741          */
6742         err = tg3_alloc_consistent(tp);
6743         if (err)
6744                 return err;
6745
6746         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6747             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6748             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6749             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
6750               (tp->pdev_peer == tp->pdev))) {
6751                 /* All MSI supporting chips should support tagged
6752                  * status.  Assert that this is the case.
6753                  */
6754                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6755                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6756                                "Not using MSI.\n", tp->dev->name);
6757                 } else if (pci_enable_msi(tp->pdev) == 0) {
6758                         u32 msi_mode;
6759
6760                         msi_mode = tr32(MSGINT_MODE);
6761                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6762                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6763                 }
6764         }
6765         err = tg3_request_irq(tp);
6766
6767         if (err) {
6768                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6769                         pci_disable_msi(tp->pdev);
6770                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6771                 }
6772                 tg3_free_consistent(tp);
6773                 return err;
6774         }
6775
6776         tg3_full_lock(tp, 0);
6777
6778         err = tg3_init_hw(tp, 1);
6779         if (err) {
6780                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6781                 tg3_free_rings(tp);
6782         } else {
6783                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6784                         tp->timer_offset = HZ;
6785                 else
6786                         tp->timer_offset = HZ / 10;
6787
6788                 BUG_ON(tp->timer_offset > HZ);
6789                 tp->timer_counter = tp->timer_multiplier =
6790                         (HZ / tp->timer_offset);
6791                 tp->asf_counter = tp->asf_multiplier =
6792                         ((HZ / tp->timer_offset) * 2);
6793
6794                 init_timer(&tp->timer);
6795                 tp->timer.expires = jiffies + tp->timer_offset;
6796                 tp->timer.data = (unsigned long) tp;
6797                 tp->timer.function = tg3_timer;
6798         }
6799
6800         tg3_full_unlock(tp);
6801
6802         if (err) {
6803                 free_irq(tp->pdev->irq, dev);
6804                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6805                         pci_disable_msi(tp->pdev);
6806                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6807                 }
6808                 tg3_free_consistent(tp);
6809                 return err;
6810         }
6811
6812         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6813                 err = tg3_test_msi(tp);
6814
6815                 if (err) {
6816                         tg3_full_lock(tp, 0);
6817
6818                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6819                                 pci_disable_msi(tp->pdev);
6820                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6821                         }
6822                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6823                         tg3_free_rings(tp);
6824                         tg3_free_consistent(tp);
6825
6826                         tg3_full_unlock(tp);
6827
6828                         return err;
6829                 }
6830
6831                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6832                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
6833                                 u32 val = tr32(0x7c04);
6834
6835                                 tw32(0x7c04, val | (1 << 29));
6836                         }
6837                 }
6838         }
6839
6840         tg3_full_lock(tp, 0);
6841
6842         add_timer(&tp->timer);
6843         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6844         tg3_enable_ints(tp);
6845
6846         tg3_full_unlock(tp);
6847
6848         netif_start_queue(dev);
6849
6850         return 0;
6851 }
6852
6853 #if 0
6854 /*static*/ void tg3_dump_state(struct tg3 *tp)
6855 {
6856         u32 val32, val32_2, val32_3, val32_4, val32_5;
6857         u16 val16;
6858         int i;
6859
6860         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6861         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6862         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6863                val16, val32);
6864
6865         /* MAC block */
6866         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6867                tr32(MAC_MODE), tr32(MAC_STATUS));
6868         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6869                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6870         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6871                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6872         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6873                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6874
6875         /* Send data initiator control block */
6876         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6877                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6878         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6879                tr32(SNDDATAI_STATSCTRL));
6880
6881         /* Send data completion control block */
6882         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6883
6884         /* Send BD ring selector block */
6885         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6886                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6887
6888         /* Send BD initiator control block */
6889         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6890                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6891
6892         /* Send BD completion control block */
6893         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6894
6895         /* Receive list placement control block */
6896         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6897                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6898         printk("       RCVLPC_STATSCTRL[%08x]\n",
6899                tr32(RCVLPC_STATSCTRL));
6900
6901         /* Receive data and receive BD initiator control block */
6902         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6903                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6904
6905         /* Receive data completion control block */
6906         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6907                tr32(RCVDCC_MODE));
6908
6909         /* Receive BD initiator control block */
6910         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6911                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6912
6913         /* Receive BD completion control block */
6914         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6915                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6916
6917         /* Receive list selector control block */
6918         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6919                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6920
6921         /* Mbuf cluster free block */
6922         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6923                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6924
6925         /* Host coalescing control block */
6926         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6927                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6928         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6929                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6930                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6931         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6932                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6933                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6934         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6935                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6936         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6937                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6938
6939         /* Memory arbiter control block */
6940         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6941                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6942
6943         /* Buffer manager control block */
6944         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6945                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6946         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6947                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6948         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6949                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6950                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6951                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6952
6953         /* Read DMA control block */
6954         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6955                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6956
6957         /* Write DMA control block */
6958         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6959                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6960
6961         /* DMA completion block */
6962         printk("DEBUG: DMAC_MODE[%08x]\n",
6963                tr32(DMAC_MODE));
6964
6965         /* GRC block */
6966         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6967                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6968         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6969                tr32(GRC_LOCAL_CTRL));
6970
6971         /* TG3_BDINFOs */
6972         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6973                tr32(RCVDBDI_JUMBO_BD + 0x0),
6974                tr32(RCVDBDI_JUMBO_BD + 0x4),
6975                tr32(RCVDBDI_JUMBO_BD + 0x8),
6976                tr32(RCVDBDI_JUMBO_BD + 0xc));
6977         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6978                tr32(RCVDBDI_STD_BD + 0x0),
6979                tr32(RCVDBDI_STD_BD + 0x4),
6980                tr32(RCVDBDI_STD_BD + 0x8),
6981                tr32(RCVDBDI_STD_BD + 0xc));
6982         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6983                tr32(RCVDBDI_MINI_BD + 0x0),
6984                tr32(RCVDBDI_MINI_BD + 0x4),
6985                tr32(RCVDBDI_MINI_BD + 0x8),
6986                tr32(RCVDBDI_MINI_BD + 0xc));
6987
6988         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6989         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6990         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6991         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6992         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6993                val32, val32_2, val32_3, val32_4);
6994
6995         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6996         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6997         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6998         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6999         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7000                val32, val32_2, val32_3, val32_4);
7001
7002         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7003         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7004         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7005         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7006         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7007         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7008                val32, val32_2, val32_3, val32_4, val32_5);
7009
7010         /* SW status block */
7011         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7012                tp->hw_status->status,
7013                tp->hw_status->status_tag,
7014                tp->hw_status->rx_jumbo_consumer,
7015                tp->hw_status->rx_consumer,
7016                tp->hw_status->rx_mini_consumer,
7017                tp->hw_status->idx[0].rx_producer,
7018                tp->hw_status->idx[0].tx_consumer);
7019
7020         /* SW statistics block */
7021         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7022                ((u32 *)tp->hw_stats)[0],
7023                ((u32 *)tp->hw_stats)[1],
7024                ((u32 *)tp->hw_stats)[2],
7025                ((u32 *)tp->hw_stats)[3]);
7026
7027         /* Mailboxes */
7028         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7029                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7030                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7031                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7032                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7033
7034         /* NIC side send descriptors. */
7035         for (i = 0; i < 6; i++) {
7036                 unsigned long txd;
7037
7038                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7039                         + (i * sizeof(struct tg3_tx_buffer_desc));
7040                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7041                        i,
7042                        readl(txd + 0x0), readl(txd + 0x4),
7043                        readl(txd + 0x8), readl(txd + 0xc));
7044         }
7045
7046         /* NIC side RX descriptors. */
7047         for (i = 0; i < 6; i++) {
7048                 unsigned long rxd;
7049
7050                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7051                         + (i * sizeof(struct tg3_rx_buffer_desc));
7052                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7053                        i,
7054                        readl(rxd + 0x0), readl(rxd + 0x4),
7055                        readl(rxd + 0x8), readl(rxd + 0xc));
7056                 rxd += (4 * sizeof(u32));
7057                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7058                        i,
7059                        readl(rxd + 0x0), readl(rxd + 0x4),
7060                        readl(rxd + 0x8), readl(rxd + 0xc));
7061         }
7062
7063         for (i = 0; i < 6; i++) {
7064                 unsigned long rxd;
7065
7066                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7067                         + (i * sizeof(struct tg3_rx_buffer_desc));
7068                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7069                        i,
7070                        readl(rxd + 0x0), readl(rxd + 0x4),
7071                        readl(rxd + 0x8), readl(rxd + 0xc));
7072                 rxd += (4 * sizeof(u32));
7073                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7074                        i,
7075                        readl(rxd + 0x0), readl(rxd + 0x4),
7076                        readl(rxd + 0x8), readl(rxd + 0xc));
7077         }
7078 }
7079 #endif
7080
7081 static struct net_device_stats *tg3_get_stats(struct net_device *);
7082 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7083
7084 static int tg3_close(struct net_device *dev)
7085 {
7086         struct tg3 *tp = netdev_priv(dev);
7087
7088         /* Calling flush_scheduled_work() may deadlock because
7089          * linkwatch_event() may be on the workqueue and it will try to get
7090          * the rtnl_lock which we are holding.
7091          */
7092         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7093                 msleep(1);
7094
7095         netif_stop_queue(dev);
7096
7097         del_timer_sync(&tp->timer);
7098
7099         tg3_full_lock(tp, 1);
7100 #if 0
7101         tg3_dump_state(tp);
7102 #endif
7103
7104         tg3_disable_ints(tp);
7105
7106         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7107         tg3_free_rings(tp);
7108         tp->tg3_flags &=
7109                 ~(TG3_FLAG_INIT_COMPLETE |
7110                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7111
7112         tg3_full_unlock(tp);
7113
7114         free_irq(tp->pdev->irq, dev);
7115         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7116                 pci_disable_msi(tp->pdev);
7117                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7118         }
7119
7120         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7121                sizeof(tp->net_stats_prev));
7122         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7123                sizeof(tp->estats_prev));
7124
7125         tg3_free_consistent(tp);
7126
7127         tg3_set_power_state(tp, PCI_D3hot);
7128
7129         netif_carrier_off(tp->dev);
7130
7131         return 0;
7132 }
7133
7134 static inline unsigned long get_stat64(tg3_stat64_t *val)
7135 {
7136         unsigned long ret;
7137
7138 #if (BITS_PER_LONG == 32)
7139         ret = val->low;
7140 #else
7141         ret = ((u64)val->high << 32) | ((u64)val->low);
7142 #endif
7143         return ret;
7144 }
7145
7146 static unsigned long calc_crc_errors(struct tg3 *tp)
7147 {
7148         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7149
7150         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7151             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7152              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7153                 u32 val;
7154
7155                 spin_lock_bh(&tp->lock);
7156                 if (!tg3_readphy(tp, 0x1e, &val)) {
7157                         tg3_writephy(tp, 0x1e, val | 0x8000);
7158                         tg3_readphy(tp, 0x14, &val);
7159                 } else
7160                         val = 0;
7161                 spin_unlock_bh(&tp->lock);
7162
7163                 tp->phy_crc_errors += val;
7164
7165                 return tp->phy_crc_errors;
7166         }
7167
7168         return get_stat64(&hw_stats->rx_fcs_errors);
7169 }
7170
7171 #define ESTAT_ADD(member) \
7172         estats->member =        old_estats->member + \
7173                                 get_stat64(&hw_stats->member)
7174
7175 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7176 {
7177         struct tg3_ethtool_stats *estats = &tp->estats;
7178         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7179         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7180
7181         if (!hw_stats)
7182                 return old_estats;
7183
7184         ESTAT_ADD(rx_octets);
7185         ESTAT_ADD(rx_fragments);
7186         ESTAT_ADD(rx_ucast_packets);
7187         ESTAT_ADD(rx_mcast_packets);
7188         ESTAT_ADD(rx_bcast_packets);
7189         ESTAT_ADD(rx_fcs_errors);
7190         ESTAT_ADD(rx_align_errors);
7191         ESTAT_ADD(rx_xon_pause_rcvd);
7192         ESTAT_ADD(rx_xoff_pause_rcvd);
7193         ESTAT_ADD(rx_mac_ctrl_rcvd);
7194         ESTAT_ADD(rx_xoff_entered);
7195         ESTAT_ADD(rx_frame_too_long_errors);
7196         ESTAT_ADD(rx_jabbers);
7197         ESTAT_ADD(rx_undersize_packets);
7198         ESTAT_ADD(rx_in_length_errors);
7199         ESTAT_ADD(rx_out_length_errors);
7200         ESTAT_ADD(rx_64_or_less_octet_packets);
7201         ESTAT_ADD(rx_65_to_127_octet_packets);
7202         ESTAT_ADD(rx_128_to_255_octet_packets);
7203         ESTAT_ADD(rx_256_to_511_octet_packets);
7204         ESTAT_ADD(rx_512_to_1023_octet_packets);
7205         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7206         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7207         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7208         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7209         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7210
7211         ESTAT_ADD(tx_octets);
7212         ESTAT_ADD(tx_collisions);
7213         ESTAT_ADD(tx_xon_sent);
7214         ESTAT_ADD(tx_xoff_sent);
7215         ESTAT_ADD(tx_flow_control);
7216         ESTAT_ADD(tx_mac_errors);
7217         ESTAT_ADD(tx_single_collisions);
7218         ESTAT_ADD(tx_mult_collisions);
7219         ESTAT_ADD(tx_deferred);
7220         ESTAT_ADD(tx_excessive_collisions);
7221         ESTAT_ADD(tx_late_collisions);
7222         ESTAT_ADD(tx_collide_2times);
7223         ESTAT_ADD(tx_collide_3times);
7224         ESTAT_ADD(tx_collide_4times);
7225         ESTAT_ADD(tx_collide_5times);
7226         ESTAT_ADD(tx_collide_6times);
7227         ESTAT_ADD(tx_collide_7times);
7228         ESTAT_ADD(tx_collide_8times);
7229         ESTAT_ADD(tx_collide_9times);
7230         ESTAT_ADD(tx_collide_10times);
7231         ESTAT_ADD(tx_collide_11times);
7232         ESTAT_ADD(tx_collide_12times);
7233         ESTAT_ADD(tx_collide_13times);
7234         ESTAT_ADD(tx_collide_14times);
7235         ESTAT_ADD(tx_collide_15times);
7236         ESTAT_ADD(tx_ucast_packets);
7237         ESTAT_ADD(tx_mcast_packets);
7238         ESTAT_ADD(tx_bcast_packets);
7239         ESTAT_ADD(tx_carrier_sense_errors);
7240         ESTAT_ADD(tx_discards);
7241         ESTAT_ADD(tx_errors);
7242
7243         ESTAT_ADD(dma_writeq_full);
7244         ESTAT_ADD(dma_write_prioq_full);
7245         ESTAT_ADD(rxbds_empty);
7246         ESTAT_ADD(rx_discards);
7247         ESTAT_ADD(rx_errors);
7248         ESTAT_ADD(rx_threshold_hit);
7249
7250         ESTAT_ADD(dma_readq_full);
7251         ESTAT_ADD(dma_read_prioq_full);
7252         ESTAT_ADD(tx_comp_queue_full);
7253
7254         ESTAT_ADD(ring_set_send_prod_index);
7255         ESTAT_ADD(ring_status_update);
7256         ESTAT_ADD(nic_irqs);
7257         ESTAT_ADD(nic_avoided_irqs);
7258         ESTAT_ADD(nic_tx_threshold_hit);
7259
7260         return estats;
7261 }
7262
7263 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7264 {
7265         struct tg3 *tp = netdev_priv(dev);
7266         struct net_device_stats *stats = &tp->net_stats;
7267         struct net_device_stats *old_stats = &tp->net_stats_prev;
7268         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7269
7270         if (!hw_stats)
7271                 return old_stats;
7272
7273         stats->rx_packets = old_stats->rx_packets +
7274                 get_stat64(&hw_stats->rx_ucast_packets) +
7275                 get_stat64(&hw_stats->rx_mcast_packets) +
7276                 get_stat64(&hw_stats->rx_bcast_packets);
7277
7278         stats->tx_packets = old_stats->tx_packets +
7279                 get_stat64(&hw_stats->tx_ucast_packets) +
7280                 get_stat64(&hw_stats->tx_mcast_packets) +
7281                 get_stat64(&hw_stats->tx_bcast_packets);
7282
7283         stats->rx_bytes = old_stats->rx_bytes +
7284                 get_stat64(&hw_stats->rx_octets);
7285         stats->tx_bytes = old_stats->tx_bytes +
7286                 get_stat64(&hw_stats->tx_octets);
7287
7288         stats->rx_errors = old_stats->rx_errors +
7289                 get_stat64(&hw_stats->rx_errors);
7290         stats->tx_errors = old_stats->tx_errors +
7291                 get_stat64(&hw_stats->tx_errors) +
7292                 get_stat64(&hw_stats->tx_mac_errors) +
7293                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7294                 get_stat64(&hw_stats->tx_discards);
7295
7296         stats->multicast = old_stats->multicast +
7297                 get_stat64(&hw_stats->rx_mcast_packets);
7298         stats->collisions = old_stats->collisions +
7299                 get_stat64(&hw_stats->tx_collisions);
7300
7301         stats->rx_length_errors = old_stats->rx_length_errors +
7302                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7303                 get_stat64(&hw_stats->rx_undersize_packets);
7304
7305         stats->rx_over_errors = old_stats->rx_over_errors +
7306                 get_stat64(&hw_stats->rxbds_empty);
7307         stats->rx_frame_errors = old_stats->rx_frame_errors +
7308                 get_stat64(&hw_stats->rx_align_errors);
7309         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7310                 get_stat64(&hw_stats->tx_discards);
7311         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7312                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7313
7314         stats->rx_crc_errors = old_stats->rx_crc_errors +
7315                 calc_crc_errors(tp);
7316
7317         stats->rx_missed_errors = old_stats->rx_missed_errors +
7318                 get_stat64(&hw_stats->rx_discards);
7319
7320         return stats;
7321 }
7322
7323 static inline u32 calc_crc(unsigned char *buf, int len)
7324 {
7325         u32 reg;
7326         u32 tmp;
7327         int j, k;
7328
7329         reg = 0xffffffff;
7330
7331         for (j = 0; j < len; j++) {
7332                 reg ^= buf[j];
7333
7334                 for (k = 0; k < 8; k++) {
7335                         tmp = reg & 0x01;
7336
7337                         reg >>= 1;
7338
7339                         if (tmp) {
7340                                 reg ^= 0xedb88320;
7341                         }
7342                 }
7343         }
7344
7345         return ~reg;
7346 }
7347
7348 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7349 {
7350         /* accept or reject all multicast frames */
7351         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7352         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7353         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7354         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7355 }
7356
7357 static void __tg3_set_rx_mode(struct net_device *dev)
7358 {
7359         struct tg3 *tp = netdev_priv(dev);
7360         u32 rx_mode;
7361
7362         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7363                                   RX_MODE_KEEP_VLAN_TAG);
7364
7365         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7366          * flag clear.
7367          */
7368 #if TG3_VLAN_TAG_USED
7369         if (!tp->vlgrp &&
7370             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7371                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7372 #else
7373         /* By definition, VLAN is disabled always in this
7374          * case.
7375          */
7376         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7377                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7378 #endif
7379
7380         if (dev->flags & IFF_PROMISC) {
7381                 /* Promiscuous mode. */
7382                 rx_mode |= RX_MODE_PROMISC;
7383         } else if (dev->flags & IFF_ALLMULTI) {
7384                 /* Accept all multicast. */
7385                 tg3_set_multi (tp, 1);
7386         } else if (dev->mc_count < 1) {
7387                 /* Reject all multicast. */
7388                 tg3_set_multi (tp, 0);
7389         } else {
7390                 /* Accept one or more multicast(s). */
7391                 struct dev_mc_list *mclist;
7392                 unsigned int i;
7393                 u32 mc_filter[4] = { 0, };
7394                 u32 regidx;
7395                 u32 bit;
7396                 u32 crc;
7397
7398                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7399                      i++, mclist = mclist->next) {
7400
7401                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7402                         bit = ~crc & 0x7f;
7403                         regidx = (bit & 0x60) >> 5;
7404                         bit &= 0x1f;
7405                         mc_filter[regidx] |= (1 << bit);
7406                 }
7407
7408                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7409                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7410                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7411                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7412         }
7413
7414         if (rx_mode != tp->rx_mode) {
7415                 tp->rx_mode = rx_mode;
7416                 tw32_f(MAC_RX_MODE, rx_mode);
7417                 udelay(10);
7418         }
7419 }
7420
7421 static void tg3_set_rx_mode(struct net_device *dev)
7422 {
7423         struct tg3 *tp = netdev_priv(dev);
7424
7425         if (!netif_running(dev))
7426                 return;
7427
7428         tg3_full_lock(tp, 0);
7429         __tg3_set_rx_mode(dev);
7430         tg3_full_unlock(tp);
7431 }
7432
7433 #define TG3_REGDUMP_LEN         (32 * 1024)
7434
7435 static int tg3_get_regs_len(struct net_device *dev)
7436 {
7437         return TG3_REGDUMP_LEN;
7438 }
7439
7440 static void tg3_get_regs(struct net_device *dev,
7441                 struct ethtool_regs *regs, void *_p)
7442 {
7443         u32 *p = _p;
7444         struct tg3 *tp = netdev_priv(dev);
7445         u8 *orig_p = _p;
7446         int i;
7447
7448         regs->version = 0;
7449
7450         memset(p, 0, TG3_REGDUMP_LEN);
7451
7452         if (tp->link_config.phy_is_low_power)
7453                 return;
7454
7455         tg3_full_lock(tp, 0);
7456
7457 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7458 #define GET_REG32_LOOP(base,len)                \
7459 do {    p = (u32 *)(orig_p + (base));           \
7460         for (i = 0; i < len; i += 4)            \
7461                 __GET_REG32((base) + i);        \
7462 } while (0)
7463 #define GET_REG32_1(reg)                        \
7464 do {    p = (u32 *)(orig_p + (reg));            \
7465         __GET_REG32((reg));                     \
7466 } while (0)
7467
7468         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7469         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7470         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7471         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7472         GET_REG32_1(SNDDATAC_MODE);
7473         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7474         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7475         GET_REG32_1(SNDBDC_MODE);
7476         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7477         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7478         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7479         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7480         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7481         GET_REG32_1(RCVDCC_MODE);
7482         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7483         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7484         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7485         GET_REG32_1(MBFREE_MODE);
7486         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7487         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7488         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7489         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7490         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7491         GET_REG32_1(RX_CPU_MODE);
7492         GET_REG32_1(RX_CPU_STATE);
7493         GET_REG32_1(RX_CPU_PGMCTR);
7494         GET_REG32_1(RX_CPU_HWBKPT);
7495         GET_REG32_1(TX_CPU_MODE);
7496         GET_REG32_1(TX_CPU_STATE);
7497         GET_REG32_1(TX_CPU_PGMCTR);
7498         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7499         GET_REG32_LOOP(FTQ_RESET, 0x120);
7500         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7501         GET_REG32_1(DMAC_MODE);
7502         GET_REG32_LOOP(GRC_MODE, 0x4c);
7503         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7504                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7505
7506 #undef __GET_REG32
7507 #undef GET_REG32_LOOP
7508 #undef GET_REG32_1
7509
7510         tg3_full_unlock(tp);
7511 }
7512
7513 static int tg3_get_eeprom_len(struct net_device *dev)
7514 {
7515         struct tg3 *tp = netdev_priv(dev);
7516
7517         return tp->nvram_size;
7518 }
7519
7520 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7521 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7522
7523 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7524 {
7525         struct tg3 *tp = netdev_priv(dev);
7526         int ret;
7527         u8  *pd;
7528         u32 i, offset, len, val, b_offset, b_count;
7529
7530         if (tp->link_config.phy_is_low_power)
7531                 return -EAGAIN;
7532
7533         offset = eeprom->offset;
7534         len = eeprom->len;
7535         eeprom->len = 0;
7536
7537         eeprom->magic = TG3_EEPROM_MAGIC;
7538
7539         if (offset & 3) {
7540                 /* adjustments to start on required 4 byte boundary */
7541                 b_offset = offset & 3;
7542                 b_count = 4 - b_offset;
7543                 if (b_count > len) {
7544                         /* i.e. offset=1 len=2 */
7545                         b_count = len;
7546                 }
7547                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7548                 if (ret)
7549                         return ret;
7550                 val = cpu_to_le32(val);
7551                 memcpy(data, ((char*)&val) + b_offset, b_count);
7552                 len -= b_count;
7553                 offset += b_count;
7554                 eeprom->len += b_count;
7555         }
7556
7557         /* read bytes upto the last 4 byte boundary */
7558         pd = &data[eeprom->len];
7559         for (i = 0; i < (len - (len & 3)); i += 4) {
7560                 ret = tg3_nvram_read(tp, offset + i, &val);
7561                 if (ret) {
7562                         eeprom->len += i;
7563                         return ret;
7564                 }
7565                 val = cpu_to_le32(val);
7566                 memcpy(pd + i, &val, 4);
7567         }
7568         eeprom->len += i;
7569
7570         if (len & 3) {
7571                 /* read last bytes not ending on 4 byte boundary */
7572                 pd = &data[eeprom->len];
7573                 b_count = len & 3;
7574                 b_offset = offset + len - b_count;
7575                 ret = tg3_nvram_read(tp, b_offset, &val);
7576                 if (ret)
7577                         return ret;
7578                 val = cpu_to_le32(val);
7579                 memcpy(pd, ((char*)&val), b_count);
7580                 eeprom->len += b_count;
7581         }
7582         return 0;
7583 }
7584
7585 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7586
7587 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7588 {
7589         struct tg3 *tp = netdev_priv(dev);
7590         int ret;
7591         u32 offset, len, b_offset, odd_len, start, end;
7592         u8 *buf;
7593
7594         if (tp->link_config.phy_is_low_power)
7595                 return -EAGAIN;
7596
7597         if (eeprom->magic != TG3_EEPROM_MAGIC)
7598                 return -EINVAL;
7599
7600         offset = eeprom->offset;
7601         len = eeprom->len;
7602
7603         if ((b_offset = (offset & 3))) {
7604                 /* adjustments to start on required 4 byte boundary */
7605                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7606                 if (ret)
7607                         return ret;
7608                 start = cpu_to_le32(start);
7609                 len += b_offset;
7610                 offset &= ~3;
7611                 if (len < 4)
7612                         len = 4;
7613         }
7614
7615         odd_len = 0;
7616         if (len & 3) {
7617                 /* adjustments to end on required 4 byte boundary */
7618                 odd_len = 1;
7619                 len = (len + 3) & ~3;
7620                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7621                 if (ret)
7622                         return ret;
7623                 end = cpu_to_le32(end);
7624         }
7625
7626         buf = data;
7627         if (b_offset || odd_len) {
7628                 buf = kmalloc(len, GFP_KERNEL);
7629                 if (buf == 0)
7630                         return -ENOMEM;
7631                 if (b_offset)
7632                         memcpy(buf, &start, 4);
7633                 if (odd_len)
7634                         memcpy(buf+len-4, &end, 4);
7635                 memcpy(buf + b_offset, data, eeprom->len);
7636         }
7637
7638         ret = tg3_nvram_write_block(tp, offset, len, buf);
7639
7640         if (buf != data)
7641                 kfree(buf);
7642
7643         return ret;
7644 }
7645
7646 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7647 {
7648         struct tg3 *tp = netdev_priv(dev);
7649
7650         cmd->supported = (SUPPORTED_Autoneg);
7651
7652         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7653                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7654                                    SUPPORTED_1000baseT_Full);
7655
7656         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7657                 cmd->supported |= (SUPPORTED_100baseT_Half |
7658                                   SUPPORTED_100baseT_Full |
7659                                   SUPPORTED_10baseT_Half |
7660                                   SUPPORTED_10baseT_Full |
7661                                   SUPPORTED_MII);
7662                 cmd->port = PORT_TP;
7663         } else {
7664                 cmd->supported |= SUPPORTED_FIBRE;
7665                 cmd->port = PORT_FIBRE;
7666         }
7667
7668         cmd->advertising = tp->link_config.advertising;
7669         if (netif_running(dev)) {
7670                 cmd->speed = tp->link_config.active_speed;
7671                 cmd->duplex = tp->link_config.active_duplex;
7672         }
7673         cmd->phy_address = PHY_ADDR;
7674         cmd->transceiver = 0;
7675         cmd->autoneg = tp->link_config.autoneg;
7676         cmd->maxtxpkt = 0;
7677         cmd->maxrxpkt = 0;
7678         return 0;
7679 }
7680
7681 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7682 {
7683         struct tg3 *tp = netdev_priv(dev);
7684
7685         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7686                 /* These are the only valid advertisement bits allowed.  */
7687                 if (cmd->autoneg == AUTONEG_ENABLE &&
7688                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7689                                           ADVERTISED_1000baseT_Full |
7690                                           ADVERTISED_Autoneg |
7691                                           ADVERTISED_FIBRE)))
7692                         return -EINVAL;
7693                 /* Fiber can only do SPEED_1000.  */
7694                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7695                          (cmd->speed != SPEED_1000))
7696                         return -EINVAL;
7697         /* Copper cannot force SPEED_1000.  */
7698         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7699                    (cmd->speed == SPEED_1000))
7700                 return -EINVAL;
7701         else if ((cmd->speed == SPEED_1000) &&
7702                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7703                 return -EINVAL;
7704
7705         tg3_full_lock(tp, 0);
7706
7707         tp->link_config.autoneg = cmd->autoneg;
7708         if (cmd->autoneg == AUTONEG_ENABLE) {
7709                 tp->link_config.advertising = cmd->advertising;
7710                 tp->link_config.speed = SPEED_INVALID;
7711                 tp->link_config.duplex = DUPLEX_INVALID;
7712         } else {
7713                 tp->link_config.advertising = 0;
7714                 tp->link_config.speed = cmd->speed;
7715                 tp->link_config.duplex = cmd->duplex;
7716         }
7717
7718         if (netif_running(dev))
7719                 tg3_setup_phy(tp, 1);
7720
7721         tg3_full_unlock(tp);
7722
7723         return 0;
7724 }
7725
7726 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7727 {
7728         struct tg3 *tp = netdev_priv(dev);
7729
7730         strcpy(info->driver, DRV_MODULE_NAME);
7731         strcpy(info->version, DRV_MODULE_VERSION);
7732         strcpy(info->fw_version, tp->fw_ver);
7733         strcpy(info->bus_info, pci_name(tp->pdev));
7734 }
7735
7736 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7737 {
7738         struct tg3 *tp = netdev_priv(dev);
7739
7740         wol->supported = WAKE_MAGIC;
7741         wol->wolopts = 0;
7742         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7743                 wol->wolopts = WAKE_MAGIC;
7744         memset(&wol->sopass, 0, sizeof(wol->sopass));
7745 }
7746
7747 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7748 {
7749         struct tg3 *tp = netdev_priv(dev);
7750
7751         if (wol->wolopts & ~WAKE_MAGIC)
7752                 return -EINVAL;
7753         if ((wol->wolopts & WAKE_MAGIC) &&
7754             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7755             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7756                 return -EINVAL;
7757
7758         spin_lock_bh(&tp->lock);
7759         if (wol->wolopts & WAKE_MAGIC)
7760                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7761         else
7762                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7763         spin_unlock_bh(&tp->lock);
7764
7765         return 0;
7766 }
7767
7768 static u32 tg3_get_msglevel(struct net_device *dev)
7769 {
7770         struct tg3 *tp = netdev_priv(dev);
7771         return tp->msg_enable;
7772 }
7773
7774 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7775 {
7776         struct tg3 *tp = netdev_priv(dev);
7777         tp->msg_enable = value;
7778 }
7779
7780 #if TG3_TSO_SUPPORT != 0
7781 static int tg3_set_tso(struct net_device *dev, u32 value)
7782 {
7783         struct tg3 *tp = netdev_priv(dev);
7784
7785         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7786                 if (value)
7787                         return -EINVAL;
7788                 return 0;
7789         }
7790         return ethtool_op_set_tso(dev, value);
7791 }
7792 #endif
7793
7794 static int tg3_nway_reset(struct net_device *dev)
7795 {
7796         struct tg3 *tp = netdev_priv(dev);
7797         u32 bmcr;
7798         int r;
7799
7800         if (!netif_running(dev))
7801                 return -EAGAIN;
7802
7803         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7804                 return -EINVAL;
7805
7806         spin_lock_bh(&tp->lock);
7807         r = -EINVAL;
7808         tg3_readphy(tp, MII_BMCR, &bmcr);
7809         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7810             ((bmcr & BMCR_ANENABLE) ||
7811              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7812                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7813                                            BMCR_ANENABLE);
7814                 r = 0;
7815         }
7816         spin_unlock_bh(&tp->lock);
7817
7818         return r;
7819 }
7820
7821 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7822 {
7823         struct tg3 *tp = netdev_priv(dev);
7824
7825         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7826         ering->rx_mini_max_pending = 0;
7827         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7828                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7829         else
7830                 ering->rx_jumbo_max_pending = 0;
7831
7832         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7833
7834         ering->rx_pending = tp->rx_pending;
7835         ering->rx_mini_pending = 0;
7836         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7837                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7838         else
7839                 ering->rx_jumbo_pending = 0;
7840
7841         ering->tx_pending = tp->tx_pending;
7842 }
7843
7844 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7845 {
7846         struct tg3 *tp = netdev_priv(dev);
7847         int irq_sync = 0;
7848
7849         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7850             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7851             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7852                 return -EINVAL;
7853
7854         if (netif_running(dev)) {
7855                 tg3_netif_stop(tp);
7856                 irq_sync = 1;
7857         }
7858
7859         tg3_full_lock(tp, irq_sync);
7860
7861         tp->rx_pending = ering->rx_pending;
7862
7863         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7864             tp->rx_pending > 63)
7865                 tp->rx_pending = 63;
7866         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7867         tp->tx_pending = ering->tx_pending;
7868
7869         if (netif_running(dev)) {
7870                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7871                 tg3_init_hw(tp, 1);
7872                 tg3_netif_start(tp);
7873         }
7874
7875         tg3_full_unlock(tp);
7876
7877         return 0;
7878 }
7879
7880 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7881 {
7882         struct tg3 *tp = netdev_priv(dev);
7883
7884         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7885         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7886         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7887 }
7888
7889 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7890 {
7891         struct tg3 *tp = netdev_priv(dev);
7892         int irq_sync = 0;
7893
7894         if (netif_running(dev)) {
7895                 tg3_netif_stop(tp);
7896                 irq_sync = 1;
7897         }
7898
7899         tg3_full_lock(tp, irq_sync);
7900
7901         if (epause->autoneg)
7902                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7903         else
7904                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7905         if (epause->rx_pause)
7906                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7907         else
7908                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7909         if (epause->tx_pause)
7910                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7911         else
7912                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7913
7914         if (netif_running(dev)) {
7915                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7916                 tg3_init_hw(tp, 1);
7917                 tg3_netif_start(tp);
7918         }
7919
7920         tg3_full_unlock(tp);
7921
7922         return 0;
7923 }
7924
7925 static u32 tg3_get_rx_csum(struct net_device *dev)
7926 {
7927         struct tg3 *tp = netdev_priv(dev);
7928         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7929 }
7930
7931 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7932 {
7933         struct tg3 *tp = netdev_priv(dev);
7934
7935         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7936                 if (data != 0)
7937                         return -EINVAL;
7938                 return 0;
7939         }
7940
7941         spin_lock_bh(&tp->lock);
7942         if (data)
7943                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7944         else
7945                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7946         spin_unlock_bh(&tp->lock);
7947
7948         return 0;
7949 }
7950
7951 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7952 {
7953         struct tg3 *tp = netdev_priv(dev);
7954
7955         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7956                 if (data != 0)
7957                         return -EINVAL;
7958                 return 0;
7959         }
7960
7961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7962             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7963                 ethtool_op_set_tx_hw_csum(dev, data);
7964         else
7965                 ethtool_op_set_tx_csum(dev, data);
7966
7967         return 0;
7968 }
7969
7970 static int tg3_get_stats_count (struct net_device *dev)
7971 {
7972         return TG3_NUM_STATS;
7973 }
7974
7975 static int tg3_get_test_count (struct net_device *dev)
7976 {
7977         return TG3_NUM_TEST;
7978 }
7979
7980 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7981 {
7982         switch (stringset) {
7983         case ETH_SS_STATS:
7984                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7985                 break;
7986         case ETH_SS_TEST:
7987                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7988                 break;
7989         default:
7990                 WARN_ON(1);     /* we need a WARN() */
7991                 break;
7992         }
7993 }
7994
7995 static int tg3_phys_id(struct net_device *dev, u32 data)
7996 {
7997         struct tg3 *tp = netdev_priv(dev);
7998         int i;
7999
8000         if (!netif_running(tp->dev))
8001                 return -EAGAIN;
8002
8003         if (data == 0)
8004                 data = 2;
8005
8006         for (i = 0; i < (data * 2); i++) {
8007                 if ((i % 2) == 0)
8008                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8009                                            LED_CTRL_1000MBPS_ON |
8010                                            LED_CTRL_100MBPS_ON |
8011                                            LED_CTRL_10MBPS_ON |
8012                                            LED_CTRL_TRAFFIC_OVERRIDE |
8013                                            LED_CTRL_TRAFFIC_BLINK |
8014                                            LED_CTRL_TRAFFIC_LED);
8015
8016                 else
8017                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8018                                            LED_CTRL_TRAFFIC_OVERRIDE);
8019
8020                 if (msleep_interruptible(500))
8021                         break;
8022         }
8023         tw32(MAC_LED_CTRL, tp->led_ctrl);
8024         return 0;
8025 }
8026
8027 static void tg3_get_ethtool_stats (struct net_device *dev,
8028                                    struct ethtool_stats *estats, u64 *tmp_stats)
8029 {
8030         struct tg3 *tp = netdev_priv(dev);
8031         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8032 }
8033
8034 #define NVRAM_TEST_SIZE 0x100
8035 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8036
8037 static int tg3_test_nvram(struct tg3 *tp)
8038 {
8039         u32 *buf, csum, magic;
8040         int i, j, err = 0, size;
8041
8042         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8043                 return -EIO;
8044
8045         if (magic == TG3_EEPROM_MAGIC)
8046                 size = NVRAM_TEST_SIZE;
8047         else if ((magic & 0xff000000) == 0xa5000000) {
8048                 if ((magic & 0xe00000) == 0x200000)
8049                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8050                 else
8051                         return 0;
8052         } else
8053                 return -EIO;
8054
8055         buf = kmalloc(size, GFP_KERNEL);
8056         if (buf == NULL)
8057                 return -ENOMEM;
8058
8059         err = -EIO;
8060         for (i = 0, j = 0; i < size; i += 4, j++) {
8061                 u32 val;
8062
8063                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8064                         break;
8065                 buf[j] = cpu_to_le32(val);
8066         }
8067         if (i < size)
8068                 goto out;
8069
8070         /* Selfboot format */
8071         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
8072                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8073
8074                 for (i = 0; i < size; i++)
8075                         csum8 += buf8[i];
8076
8077                 if (csum8 == 0) {
8078                         err = 0;
8079                         goto out;
8080                 }
8081
8082                 err = -EIO;
8083                 goto out;
8084         }
8085
8086         /* Bootstrap checksum at offset 0x10 */
8087         csum = calc_crc((unsigned char *) buf, 0x10);
8088         if(csum != cpu_to_le32(buf[0x10/4]))
8089                 goto out;
8090
8091         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8092         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8093         if (csum != cpu_to_le32(buf[0xfc/4]))
8094                  goto out;
8095
8096         err = 0;
8097
8098 out:
8099         kfree(buf);
8100         return err;
8101 }
8102
8103 #define TG3_SERDES_TIMEOUT_SEC  2
8104 #define TG3_COPPER_TIMEOUT_SEC  6
8105
8106 static int tg3_test_link(struct tg3 *tp)
8107 {
8108         int i, max;
8109
8110         if (!netif_running(tp->dev))
8111                 return -ENODEV;
8112
8113         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8114                 max = TG3_SERDES_TIMEOUT_SEC;
8115         else
8116                 max = TG3_COPPER_TIMEOUT_SEC;
8117
8118         for (i = 0; i < max; i++) {
8119                 if (netif_carrier_ok(tp->dev))
8120                         return 0;
8121
8122                 if (msleep_interruptible(1000))
8123                         break;
8124         }
8125
8126         return -EIO;
8127 }
8128
8129 /* Only test the commonly used registers */
8130 static int tg3_test_registers(struct tg3 *tp)
8131 {
8132         int i, is_5705;
8133         u32 offset, read_mask, write_mask, val, save_val, read_val;
8134         static struct {
8135                 u16 offset;
8136                 u16 flags;
8137 #define TG3_FL_5705     0x1
8138 #define TG3_FL_NOT_5705 0x2
8139 #define TG3_FL_NOT_5788 0x4
8140                 u32 read_mask;
8141                 u32 write_mask;
8142         } reg_tbl[] = {
8143                 /* MAC Control Registers */
8144                 { MAC_MODE, TG3_FL_NOT_5705,
8145                         0x00000000, 0x00ef6f8c },
8146                 { MAC_MODE, TG3_FL_5705,
8147                         0x00000000, 0x01ef6b8c },
8148                 { MAC_STATUS, TG3_FL_NOT_5705,
8149                         0x03800107, 0x00000000 },
8150                 { MAC_STATUS, TG3_FL_5705,
8151                         0x03800100, 0x00000000 },
8152                 { MAC_ADDR_0_HIGH, 0x0000,
8153                         0x00000000, 0x0000ffff },
8154                 { MAC_ADDR_0_LOW, 0x0000,
8155                         0x00000000, 0xffffffff },
8156                 { MAC_RX_MTU_SIZE, 0x0000,
8157                         0x00000000, 0x0000ffff },
8158                 { MAC_TX_MODE, 0x0000,
8159                         0x00000000, 0x00000070 },
8160                 { MAC_TX_LENGTHS, 0x0000,
8161                         0x00000000, 0x00003fff },
8162                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8163                         0x00000000, 0x000007fc },
8164                 { MAC_RX_MODE, TG3_FL_5705,
8165                         0x00000000, 0x000007dc },
8166                 { MAC_HASH_REG_0, 0x0000,
8167                         0x00000000, 0xffffffff },
8168                 { MAC_HASH_REG_1, 0x0000,
8169                         0x00000000, 0xffffffff },
8170                 { MAC_HASH_REG_2, 0x0000,
8171                         0x00000000, 0xffffffff },
8172                 { MAC_HASH_REG_3, 0x0000,
8173                         0x00000000, 0xffffffff },
8174
8175                 /* Receive Data and Receive BD Initiator Control Registers. */
8176                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8177                         0x00000000, 0xffffffff },
8178                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8179                         0x00000000, 0xffffffff },
8180                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8181                         0x00000000, 0x00000003 },
8182                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8183                         0x00000000, 0xffffffff },
8184                 { RCVDBDI_STD_BD+0, 0x0000,
8185                         0x00000000, 0xffffffff },
8186                 { RCVDBDI_STD_BD+4, 0x0000,
8187                         0x00000000, 0xffffffff },
8188                 { RCVDBDI_STD_BD+8, 0x0000,
8189                         0x00000000, 0xffff0002 },
8190                 { RCVDBDI_STD_BD+0xc, 0x0000,
8191                         0x00000000, 0xffffffff },
8192
8193                 /* Receive BD Initiator Control Registers. */
8194                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8195                         0x00000000, 0xffffffff },
8196                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8197                         0x00000000, 0x000003ff },
8198                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8199                         0x00000000, 0xffffffff },
8200
8201                 /* Host Coalescing Control Registers. */
8202                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8203                         0x00000000, 0x00000004 },
8204                 { HOSTCC_MODE, TG3_FL_5705,
8205                         0x00000000, 0x000000f6 },
8206                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8207                         0x00000000, 0xffffffff },
8208                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8209                         0x00000000, 0x000003ff },
8210                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8211                         0x00000000, 0xffffffff },
8212                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8213                         0x00000000, 0x000003ff },
8214                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8215                         0x00000000, 0xffffffff },
8216                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8217                         0x00000000, 0x000000ff },
8218                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8219                         0x00000000, 0xffffffff },
8220                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8221                         0x00000000, 0x000000ff },
8222                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8223                         0x00000000, 0xffffffff },
8224                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8225                         0x00000000, 0xffffffff },
8226                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8227                         0x00000000, 0xffffffff },
8228                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8229                         0x00000000, 0x000000ff },
8230                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8231                         0x00000000, 0xffffffff },
8232                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8233                         0x00000000, 0x000000ff },
8234                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8235                         0x00000000, 0xffffffff },
8236                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8237                         0x00000000, 0xffffffff },
8238                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8239                         0x00000000, 0xffffffff },
8240                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8241                         0x00000000, 0xffffffff },
8242                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8243                         0x00000000, 0xffffffff },
8244                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8245                         0xffffffff, 0x00000000 },
8246                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8247                         0xffffffff, 0x00000000 },
8248
8249                 /* Buffer Manager Control Registers. */
8250                 { BUFMGR_MB_POOL_ADDR, 0x0000,
8251                         0x00000000, 0x007fff80 },
8252                 { BUFMGR_MB_POOL_SIZE, 0x0000,
8253                         0x00000000, 0x007fffff },
8254                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8255                         0x00000000, 0x0000003f },
8256                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8257                         0x00000000, 0x000001ff },
8258                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8259                         0x00000000, 0x000001ff },
8260                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8261                         0xffffffff, 0x00000000 },
8262                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8263                         0xffffffff, 0x00000000 },
8264
8265                 /* Mailbox Registers */
8266                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8267                         0x00000000, 0x000001ff },
8268                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8269                         0x00000000, 0x000001ff },
8270                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8271                         0x00000000, 0x000007ff },
8272                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8273                         0x00000000, 0x000001ff },
8274
8275                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8276         };
8277
8278         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8279                 is_5705 = 1;
8280         else
8281                 is_5705 = 0;
8282
8283         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8284                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8285                         continue;
8286
8287                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8288                         continue;
8289
8290                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8291                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8292                         continue;
8293
8294                 offset = (u32) reg_tbl[i].offset;
8295                 read_mask = reg_tbl[i].read_mask;
8296                 write_mask = reg_tbl[i].write_mask;
8297
8298                 /* Save the original register content */
8299                 save_val = tr32(offset);
8300
8301                 /* Determine the read-only value. */
8302                 read_val = save_val & read_mask;
8303
8304                 /* Write zero to the register, then make sure the read-only bits
8305                  * are not changed and the read/write bits are all zeros.
8306                  */
8307                 tw32(offset, 0);
8308
8309                 val = tr32(offset);
8310
8311                 /* Test the read-only and read/write bits. */
8312                 if (((val & read_mask) != read_val) || (val & write_mask))
8313                         goto out;
8314
8315                 /* Write ones to all the bits defined by RdMask and WrMask, then
8316                  * make sure the read-only bits are not changed and the
8317                  * read/write bits are all ones.
8318                  */
8319                 tw32(offset, read_mask | write_mask);
8320
8321                 val = tr32(offset);
8322
8323                 /* Test the read-only bits. */
8324                 if ((val & read_mask) != read_val)
8325                         goto out;
8326
8327                 /* Test the read/write bits. */
8328                 if ((val & write_mask) != write_mask)
8329                         goto out;
8330
8331                 tw32(offset, save_val);
8332         }
8333
8334         return 0;
8335
8336 out:
8337         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8338         tw32(offset, save_val);
8339         return -EIO;
8340 }
8341
8342 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8343 {
8344         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8345         int i;
8346         u32 j;
8347
8348         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8349                 for (j = 0; j < len; j += 4) {
8350                         u32 val;
8351
8352                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8353                         tg3_read_mem(tp, offset + j, &val);
8354                         if (val != test_pattern[i])
8355                                 return -EIO;
8356                 }
8357         }
8358         return 0;
8359 }
8360
8361 static int tg3_test_memory(struct tg3 *tp)
8362 {
8363         static struct mem_entry {
8364                 u32 offset;
8365                 u32 len;
8366         } mem_tbl_570x[] = {
8367                 { 0x00000000, 0x00b50},
8368                 { 0x00002000, 0x1c000},
8369                 { 0xffffffff, 0x00000}
8370         }, mem_tbl_5705[] = {
8371                 { 0x00000100, 0x0000c},
8372                 { 0x00000200, 0x00008},
8373                 { 0x00004000, 0x00800},
8374                 { 0x00006000, 0x01000},
8375                 { 0x00008000, 0x02000},
8376                 { 0x00010000, 0x0e000},
8377                 { 0xffffffff, 0x00000}
8378         }, mem_tbl_5755[] = {
8379                 { 0x00000200, 0x00008},
8380                 { 0x00004000, 0x00800},
8381                 { 0x00006000, 0x00800},
8382                 { 0x00008000, 0x02000},
8383                 { 0x00010000, 0x0c000},
8384                 { 0xffffffff, 0x00000}
8385         };
8386         struct mem_entry *mem_tbl;
8387         int err = 0;
8388         int i;
8389
8390         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8391                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8392                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8393                         mem_tbl = mem_tbl_5755;
8394                 else
8395                         mem_tbl = mem_tbl_5705;
8396         } else
8397                 mem_tbl = mem_tbl_570x;
8398
8399         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8400                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8401                     mem_tbl[i].len)) != 0)
8402                         break;
8403         }
8404
8405         return err;
8406 }
8407
8408 #define TG3_MAC_LOOPBACK        0
8409 #define TG3_PHY_LOOPBACK        1
8410
8411 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8412 {
8413         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8414         u32 desc_idx;
8415         struct sk_buff *skb, *rx_skb;
8416         u8 *tx_data;
8417         dma_addr_t map;
8418         int num_pkts, tx_len, rx_len, i, err;
8419         struct tg3_rx_buffer_desc *desc;
8420
8421         if (loopback_mode == TG3_MAC_LOOPBACK) {
8422                 /* HW errata - mac loopback fails in some cases on 5780.
8423                  * Normal traffic and PHY loopback are not affected by
8424                  * errata.
8425                  */
8426                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8427                         return 0;
8428
8429                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8430                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8431                            MAC_MODE_PORT_MODE_GMII;
8432                 tw32(MAC_MODE, mac_mode);
8433         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8434                 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8435                                            BMCR_SPEED1000);
8436                 udelay(40);
8437                 /* reset to prevent losing 1st rx packet intermittently */
8438                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8439                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8440                         udelay(10);
8441                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8442                 }
8443                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8444                            MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8445                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8446                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8447                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8448                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8449                 }
8450                 tw32(MAC_MODE, mac_mode);
8451         }
8452         else
8453                 return -EINVAL;
8454
8455         err = -EIO;
8456
8457         tx_len = 1514;
8458         skb = dev_alloc_skb(tx_len);
8459         if (!skb)
8460                 return -ENOMEM;
8461
8462         tx_data = skb_put(skb, tx_len);
8463         memcpy(tx_data, tp->dev->dev_addr, 6);
8464         memset(tx_data + 6, 0x0, 8);
8465
8466         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8467
8468         for (i = 14; i < tx_len; i++)
8469                 tx_data[i] = (u8) (i & 0xff);
8470
8471         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8472
8473         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8474              HOSTCC_MODE_NOW);
8475
8476         udelay(10);
8477
8478         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8479
8480         num_pkts = 0;
8481
8482         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8483
8484         tp->tx_prod++;
8485         num_pkts++;
8486
8487         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8488                      tp->tx_prod);
8489         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8490
8491         udelay(10);
8492
8493         for (i = 0; i < 10; i++) {
8494                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8495                        HOSTCC_MODE_NOW);
8496
8497                 udelay(10);
8498
8499                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8500                 rx_idx = tp->hw_status->idx[0].rx_producer;
8501                 if ((tx_idx == tp->tx_prod) &&
8502                     (rx_idx == (rx_start_idx + num_pkts)))
8503                         break;
8504         }
8505
8506         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8507         dev_kfree_skb(skb);
8508
8509         if (tx_idx != tp->tx_prod)
8510                 goto out;
8511
8512         if (rx_idx != rx_start_idx + num_pkts)
8513                 goto out;
8514
8515         desc = &tp->rx_rcb[rx_start_idx];
8516         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8517         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8518         if (opaque_key != RXD_OPAQUE_RING_STD)
8519                 goto out;
8520
8521         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8522             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8523                 goto out;
8524
8525         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8526         if (rx_len != tx_len)
8527                 goto out;
8528
8529         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8530
8531         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8532         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8533
8534         for (i = 14; i < tx_len; i++) {
8535                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8536                         goto out;
8537         }
8538         err = 0;
8539
8540         /* tg3_free_rings will unmap and free the rx_skb */
8541 out:
8542         return err;
8543 }
8544
8545 #define TG3_MAC_LOOPBACK_FAILED         1
8546 #define TG3_PHY_LOOPBACK_FAILED         2
8547 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8548                                          TG3_PHY_LOOPBACK_FAILED)
8549
8550 static int tg3_test_loopback(struct tg3 *tp)
8551 {
8552         int err = 0;
8553
8554         if (!netif_running(tp->dev))
8555                 return TG3_LOOPBACK_FAILED;
8556
8557         tg3_reset_hw(tp, 1);
8558
8559         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8560                 err |= TG3_MAC_LOOPBACK_FAILED;
8561         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8562                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8563                         err |= TG3_PHY_LOOPBACK_FAILED;
8564         }
8565
8566         return err;
8567 }
8568
8569 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8570                           u64 *data)
8571 {
8572         struct tg3 *tp = netdev_priv(dev);
8573
8574         if (tp->link_config.phy_is_low_power)
8575                 tg3_set_power_state(tp, PCI_D0);
8576
8577         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8578
8579         if (tg3_test_nvram(tp) != 0) {
8580                 etest->flags |= ETH_TEST_FL_FAILED;
8581                 data[0] = 1;
8582         }
8583         if (tg3_test_link(tp) != 0) {
8584                 etest->flags |= ETH_TEST_FL_FAILED;
8585                 data[1] = 1;
8586         }
8587         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8588                 int err, irq_sync = 0;
8589
8590                 if (netif_running(dev)) {
8591                         tg3_netif_stop(tp);
8592                         irq_sync = 1;
8593                 }
8594
8595                 tg3_full_lock(tp, irq_sync);
8596
8597                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8598                 err = tg3_nvram_lock(tp);
8599                 tg3_halt_cpu(tp, RX_CPU_BASE);
8600                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8601                         tg3_halt_cpu(tp, TX_CPU_BASE);
8602                 if (!err)
8603                         tg3_nvram_unlock(tp);
8604
8605                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8606                         tg3_phy_reset(tp);
8607
8608                 if (tg3_test_registers(tp) != 0) {
8609                         etest->flags |= ETH_TEST_FL_FAILED;
8610                         data[2] = 1;
8611                 }
8612                 if (tg3_test_memory(tp) != 0) {
8613                         etest->flags |= ETH_TEST_FL_FAILED;
8614                         data[3] = 1;
8615                 }
8616                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8617                         etest->flags |= ETH_TEST_FL_FAILED;
8618
8619                 tg3_full_unlock(tp);
8620
8621                 if (tg3_test_interrupt(tp) != 0) {
8622                         etest->flags |= ETH_TEST_FL_FAILED;
8623                         data[5] = 1;
8624                 }
8625
8626                 tg3_full_lock(tp, 0);
8627
8628                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8629                 if (netif_running(dev)) {
8630                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8631                         tg3_init_hw(tp, 1);
8632                         tg3_netif_start(tp);
8633                 }
8634
8635                 tg3_full_unlock(tp);
8636         }
8637         if (tp->link_config.phy_is_low_power)
8638                 tg3_set_power_state(tp, PCI_D3hot);
8639
8640 }
8641
8642 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8643 {
8644         struct mii_ioctl_data *data = if_mii(ifr);
8645         struct tg3 *tp = netdev_priv(dev);
8646         int err;
8647
8648         switch(cmd) {
8649         case SIOCGMIIPHY:
8650                 data->phy_id = PHY_ADDR;
8651
8652                 /* fallthru */
8653         case SIOCGMIIREG: {
8654                 u32 mii_regval;
8655
8656                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8657                         break;                  /* We have no PHY */
8658
8659                 if (tp->link_config.phy_is_low_power)
8660                         return -EAGAIN;
8661
8662                 spin_lock_bh(&tp->lock);
8663                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8664                 spin_unlock_bh(&tp->lock);
8665
8666                 data->val_out = mii_regval;
8667
8668                 return err;
8669         }
8670
8671         case SIOCSMIIREG:
8672                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8673                         break;                  /* We have no PHY */
8674
8675                 if (!capable(CAP_NET_ADMIN))
8676                         return -EPERM;
8677
8678                 if (tp->link_config.phy_is_low_power)
8679                         return -EAGAIN;
8680
8681                 spin_lock_bh(&tp->lock);
8682                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8683                 spin_unlock_bh(&tp->lock);
8684
8685                 return err;
8686
8687         default:
8688                 /* do nothing */
8689                 break;
8690         }
8691         return -EOPNOTSUPP;
8692 }
8693
8694 #if TG3_VLAN_TAG_USED
8695 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8696 {
8697         struct tg3 *tp = netdev_priv(dev);
8698
8699         tg3_full_lock(tp, 0);
8700
8701         tp->vlgrp = grp;
8702
8703         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8704         __tg3_set_rx_mode(dev);
8705
8706         tg3_full_unlock(tp);
8707 }
8708
8709 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8710 {
8711         struct tg3 *tp = netdev_priv(dev);
8712
8713         tg3_full_lock(tp, 0);
8714         if (tp->vlgrp)
8715                 tp->vlgrp->vlan_devices[vid] = NULL;
8716         tg3_full_unlock(tp);
8717 }
8718 #endif
8719
8720 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8721 {
8722         struct tg3 *tp = netdev_priv(dev);
8723
8724         memcpy(ec, &tp->coal, sizeof(*ec));
8725         return 0;
8726 }
8727
8728 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8729 {
8730         struct tg3 *tp = netdev_priv(dev);
8731         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8732         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8733
8734         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8735                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8736                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8737                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8738                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8739         }
8740
8741         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8742             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8743             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8744             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8745             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8746             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8747             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8748             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8749             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8750             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8751                 return -EINVAL;
8752
8753         /* No rx interrupts will be generated if both are zero */
8754         if ((ec->rx_coalesce_usecs == 0) &&
8755             (ec->rx_max_coalesced_frames == 0))
8756                 return -EINVAL;
8757
8758         /* No tx interrupts will be generated if both are zero */
8759         if ((ec->tx_coalesce_usecs == 0) &&
8760             (ec->tx_max_coalesced_frames == 0))
8761                 return -EINVAL;
8762
8763         /* Only copy relevant parameters, ignore all others. */
8764         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8765         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8766         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8767         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8768         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8769         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8770         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8771         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8772         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8773
8774         if (netif_running(dev)) {
8775                 tg3_full_lock(tp, 0);
8776                 __tg3_set_coalesce(tp, &tp->coal);
8777                 tg3_full_unlock(tp);
8778         }
8779         return 0;
8780 }
8781
8782 static struct ethtool_ops tg3_ethtool_ops = {
8783         .get_settings           = tg3_get_settings,
8784         .set_settings           = tg3_set_settings,
8785         .get_drvinfo            = tg3_get_drvinfo,
8786         .get_regs_len           = tg3_get_regs_len,
8787         .get_regs               = tg3_get_regs,
8788         .get_wol                = tg3_get_wol,
8789         .set_wol                = tg3_set_wol,
8790         .get_msglevel           = tg3_get_msglevel,
8791         .set_msglevel           = tg3_set_msglevel,
8792         .nway_reset             = tg3_nway_reset,
8793         .get_link               = ethtool_op_get_link,
8794         .get_eeprom_len         = tg3_get_eeprom_len,
8795         .get_eeprom             = tg3_get_eeprom,
8796         .set_eeprom             = tg3_set_eeprom,
8797         .get_ringparam          = tg3_get_ringparam,
8798         .set_ringparam          = tg3_set_ringparam,
8799         .get_pauseparam         = tg3_get_pauseparam,
8800         .set_pauseparam         = tg3_set_pauseparam,
8801         .get_rx_csum            = tg3_get_rx_csum,
8802         .set_rx_csum            = tg3_set_rx_csum,
8803         .get_tx_csum            = ethtool_op_get_tx_csum,
8804         .set_tx_csum            = tg3_set_tx_csum,
8805         .get_sg                 = ethtool_op_get_sg,
8806         .set_sg                 = ethtool_op_set_sg,
8807 #if TG3_TSO_SUPPORT != 0
8808         .get_tso                = ethtool_op_get_tso,
8809         .set_tso                = tg3_set_tso,
8810 #endif
8811         .self_test_count        = tg3_get_test_count,
8812         .self_test              = tg3_self_test,
8813         .get_strings            = tg3_get_strings,
8814         .phys_id                = tg3_phys_id,
8815         .get_stats_count        = tg3_get_stats_count,
8816         .get_ethtool_stats      = tg3_get_ethtool_stats,
8817         .get_coalesce           = tg3_get_coalesce,
8818         .set_coalesce           = tg3_set_coalesce,
8819         .get_perm_addr          = ethtool_op_get_perm_addr,
8820 };
8821
8822 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8823 {
8824         u32 cursize, val, magic;
8825
8826         tp->nvram_size = EEPROM_CHIP_SIZE;
8827
8828         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8829                 return;
8830
8831         if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
8832                 return;
8833
8834         /*
8835          * Size the chip by reading offsets at increasing powers of two.
8836          * When we encounter our validation signature, we know the addressing
8837          * has wrapped around, and thus have our chip size.
8838          */
8839         cursize = 0x10;
8840
8841         while (cursize < tp->nvram_size) {
8842                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8843                         return;
8844
8845                 if (val == magic)
8846                         break;
8847
8848                 cursize <<= 1;
8849         }
8850
8851         tp->nvram_size = cursize;
8852 }
8853
8854 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8855 {
8856         u32 val;
8857
8858         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
8859                 return;
8860
8861         /* Selfboot format */
8862         if (val != TG3_EEPROM_MAGIC) {
8863                 tg3_get_eeprom_size(tp);
8864                 return;
8865         }
8866
8867         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8868                 if (val != 0) {
8869                         tp->nvram_size = (val >> 16) * 1024;
8870                         return;
8871                 }
8872         }
8873         tp->nvram_size = 0x20000;
8874 }
8875
8876 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8877 {
8878         u32 nvcfg1;
8879
8880         nvcfg1 = tr32(NVRAM_CFG1);
8881         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8882                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8883         }
8884         else {
8885                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8886                 tw32(NVRAM_CFG1, nvcfg1);
8887         }
8888
8889         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8890             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8891                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8892                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8893                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8894                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8895                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8896                                 break;
8897                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8898                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8899                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8900                                 break;
8901                         case FLASH_VENDOR_ATMEL_EEPROM:
8902                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8903                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8904                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8905                                 break;
8906                         case FLASH_VENDOR_ST:
8907                                 tp->nvram_jedecnum = JEDEC_ST;
8908                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8909                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8910                                 break;
8911                         case FLASH_VENDOR_SAIFUN:
8912                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8913                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8914                                 break;
8915                         case FLASH_VENDOR_SST_SMALL:
8916                         case FLASH_VENDOR_SST_LARGE:
8917                                 tp->nvram_jedecnum = JEDEC_SST;
8918                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8919                                 break;
8920                 }
8921         }
8922         else {
8923                 tp->nvram_jedecnum = JEDEC_ATMEL;
8924                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8925                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8926         }
8927 }
8928
8929 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8930 {
8931         u32 nvcfg1;
8932
8933         nvcfg1 = tr32(NVRAM_CFG1);
8934
8935         /* NVRAM protection for TPM */
8936         if (nvcfg1 & (1 << 27))
8937                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8938
8939         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8940                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8941                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8942                         tp->nvram_jedecnum = JEDEC_ATMEL;
8943                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8944                         break;
8945                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8946                         tp->nvram_jedecnum = JEDEC_ATMEL;
8947                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8948                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8949                         break;
8950                 case FLASH_5752VENDOR_ST_M45PE10:
8951                 case FLASH_5752VENDOR_ST_M45PE20:
8952                 case FLASH_5752VENDOR_ST_M45PE40:
8953                         tp->nvram_jedecnum = JEDEC_ST;
8954                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8955                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8956                         break;
8957         }
8958
8959         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8960                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8961                         case FLASH_5752PAGE_SIZE_256:
8962                                 tp->nvram_pagesize = 256;
8963                                 break;
8964                         case FLASH_5752PAGE_SIZE_512:
8965                                 tp->nvram_pagesize = 512;
8966                                 break;
8967                         case FLASH_5752PAGE_SIZE_1K:
8968                                 tp->nvram_pagesize = 1024;
8969                                 break;
8970                         case FLASH_5752PAGE_SIZE_2K:
8971                                 tp->nvram_pagesize = 2048;
8972                                 break;
8973                         case FLASH_5752PAGE_SIZE_4K:
8974                                 tp->nvram_pagesize = 4096;
8975                                 break;
8976                         case FLASH_5752PAGE_SIZE_264:
8977                                 tp->nvram_pagesize = 264;
8978                                 break;
8979                 }
8980         }
8981         else {
8982                 /* For eeprom, set pagesize to maximum eeprom size */
8983                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8984
8985                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8986                 tw32(NVRAM_CFG1, nvcfg1);
8987         }
8988 }
8989
8990 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
8991 {
8992         u32 nvcfg1;
8993
8994         nvcfg1 = tr32(NVRAM_CFG1);
8995
8996         /* NVRAM protection for TPM */
8997         if (nvcfg1 & (1 << 27))
8998                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8999
9000         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9001                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9002                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9003                         tp->nvram_jedecnum = JEDEC_ATMEL;
9004                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9005                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9006
9007                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9008                         tw32(NVRAM_CFG1, nvcfg1);
9009                         break;
9010                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9011                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9012                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9013                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9014                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9015                         tp->nvram_jedecnum = JEDEC_ATMEL;
9016                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9017                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9018                         tp->nvram_pagesize = 264;
9019                         break;
9020                 case FLASH_5752VENDOR_ST_M45PE10:
9021                 case FLASH_5752VENDOR_ST_M45PE20:
9022                 case FLASH_5752VENDOR_ST_M45PE40:
9023                         tp->nvram_jedecnum = JEDEC_ST;
9024                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9025                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9026                         tp->nvram_pagesize = 256;
9027                         break;
9028         }
9029 }
9030
9031 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9032 {
9033         u32 nvcfg1;
9034
9035         nvcfg1 = tr32(NVRAM_CFG1);
9036
9037         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9038                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9039                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9040                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9041                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9042                         tp->nvram_jedecnum = JEDEC_ATMEL;
9043                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9044                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9045
9046                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9047                         tw32(NVRAM_CFG1, nvcfg1);
9048                         break;
9049                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9050                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9051                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9052                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9053                         tp->nvram_jedecnum = JEDEC_ATMEL;
9054                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9055                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9056                         tp->nvram_pagesize = 264;
9057                         break;
9058                 case FLASH_5752VENDOR_ST_M45PE10:
9059                 case FLASH_5752VENDOR_ST_M45PE20:
9060                 case FLASH_5752VENDOR_ST_M45PE40:
9061                         tp->nvram_jedecnum = JEDEC_ST;
9062                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9063                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9064                         tp->nvram_pagesize = 256;
9065                         break;
9066         }
9067 }
9068
9069 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9070 static void __devinit tg3_nvram_init(struct tg3 *tp)
9071 {
9072         int j;
9073
9074         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
9075                 return;
9076
9077         tw32_f(GRC_EEPROM_ADDR,
9078              (EEPROM_ADDR_FSM_RESET |
9079               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9080                EEPROM_ADDR_CLKPERD_SHIFT)));
9081
9082         /* XXX schedule_timeout() ... */
9083         for (j = 0; j < 100; j++)
9084                 udelay(10);
9085
9086         /* Enable seeprom accesses. */
9087         tw32_f(GRC_LOCAL_CTRL,
9088              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9089         udelay(100);
9090
9091         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9092             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9093                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9094
9095                 if (tg3_nvram_lock(tp)) {
9096                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9097                                "tg3_nvram_init failed.\n", tp->dev->name);
9098                         return;
9099                 }
9100                 tg3_enable_nvram_access(tp);
9101
9102                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9103                         tg3_get_5752_nvram_info(tp);
9104                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9105                         tg3_get_5755_nvram_info(tp);
9106                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9107                         tg3_get_5787_nvram_info(tp);
9108                 else
9109                         tg3_get_nvram_info(tp);
9110
9111                 tg3_get_nvram_size(tp);
9112
9113                 tg3_disable_nvram_access(tp);
9114                 tg3_nvram_unlock(tp);
9115
9116         } else {
9117                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9118
9119                 tg3_get_eeprom_size(tp);
9120         }
9121 }
9122
9123 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9124                                         u32 offset, u32 *val)
9125 {
9126         u32 tmp;
9127         int i;
9128
9129         if (offset > EEPROM_ADDR_ADDR_MASK ||
9130             (offset % 4) != 0)
9131                 return -EINVAL;
9132
9133         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9134                                         EEPROM_ADDR_DEVID_MASK |
9135                                         EEPROM_ADDR_READ);
9136         tw32(GRC_EEPROM_ADDR,
9137              tmp |
9138              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9139              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9140               EEPROM_ADDR_ADDR_MASK) |
9141              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9142
9143         for (i = 0; i < 10000; i++) {
9144                 tmp = tr32(GRC_EEPROM_ADDR);
9145
9146                 if (tmp & EEPROM_ADDR_COMPLETE)
9147                         break;
9148                 udelay(100);
9149         }
9150         if (!(tmp & EEPROM_ADDR_COMPLETE))
9151                 return -EBUSY;
9152
9153         *val = tr32(GRC_EEPROM_DATA);
9154         return 0;
9155 }
9156
9157 #define NVRAM_CMD_TIMEOUT 10000
9158
9159 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9160 {
9161         int i;
9162
9163         tw32(NVRAM_CMD, nvram_cmd);
9164         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9165                 udelay(10);
9166                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9167                         udelay(10);
9168                         break;
9169                 }
9170         }
9171         if (i == NVRAM_CMD_TIMEOUT) {
9172                 return -EBUSY;
9173         }
9174         return 0;
9175 }
9176
9177 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9178 {
9179         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9180             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9181             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9182             (tp->nvram_jedecnum == JEDEC_ATMEL))
9183
9184                 addr = ((addr / tp->nvram_pagesize) <<
9185                         ATMEL_AT45DB0X1B_PAGE_POS) +
9186                        (addr % tp->nvram_pagesize);
9187
9188         return addr;
9189 }
9190
9191 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9192 {
9193         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9194             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9195             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9196             (tp->nvram_jedecnum == JEDEC_ATMEL))
9197
9198                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9199                         tp->nvram_pagesize) +
9200                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9201
9202         return addr;
9203 }
9204
9205 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9206 {
9207         int ret;
9208
9209         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9210                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
9211                 return -EINVAL;
9212         }
9213
9214         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9215                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9216
9217         offset = tg3_nvram_phys_addr(tp, offset);
9218
9219         if (offset > NVRAM_ADDR_MSK)
9220                 return -EINVAL;
9221
9222         ret = tg3_nvram_lock(tp);
9223         if (ret)
9224                 return ret;
9225
9226         tg3_enable_nvram_access(tp);
9227
9228         tw32(NVRAM_ADDR, offset);
9229         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9230                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9231
9232         if (ret == 0)
9233                 *val = swab32(tr32(NVRAM_RDDATA));
9234
9235         tg3_disable_nvram_access(tp);
9236
9237         tg3_nvram_unlock(tp);
9238
9239         return ret;
9240 }
9241
9242 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9243 {
9244         int err;
9245         u32 tmp;
9246
9247         err = tg3_nvram_read(tp, offset, &tmp);
9248         *val = swab32(tmp);
9249         return err;
9250 }
9251
9252 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9253                                     u32 offset, u32 len, u8 *buf)
9254 {
9255         int i, j, rc = 0;
9256         u32 val;
9257
9258         for (i = 0; i < len; i += 4) {
9259                 u32 addr, data;
9260
9261                 addr = offset + i;
9262
9263                 memcpy(&data, buf + i, 4);
9264
9265                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9266
9267                 val = tr32(GRC_EEPROM_ADDR);
9268                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9269
9270                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9271                         EEPROM_ADDR_READ);
9272                 tw32(GRC_EEPROM_ADDR, val |
9273                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9274                         (addr & EEPROM_ADDR_ADDR_MASK) |
9275                         EEPROM_ADDR_START |
9276                         EEPROM_ADDR_WRITE);
9277
9278                 for (j = 0; j < 10000; j++) {
9279                         val = tr32(GRC_EEPROM_ADDR);
9280
9281                         if (val & EEPROM_ADDR_COMPLETE)
9282                                 break;
9283                         udelay(100);
9284                 }
9285                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9286                         rc = -EBUSY;
9287                         break;
9288                 }
9289         }
9290
9291         return rc;
9292 }
9293
9294 /* offset and length are dword aligned */
9295 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9296                 u8 *buf)
9297 {
9298         int ret = 0;
9299         u32 pagesize = tp->nvram_pagesize;
9300         u32 pagemask = pagesize - 1;
9301         u32 nvram_cmd;
9302         u8 *tmp;
9303
9304         tmp = kmalloc(pagesize, GFP_KERNEL);
9305         if (tmp == NULL)
9306                 return -ENOMEM;
9307
9308         while (len) {
9309                 int j;
9310                 u32 phy_addr, page_off, size;
9311
9312                 phy_addr = offset & ~pagemask;
9313
9314                 for (j = 0; j < pagesize; j += 4) {
9315                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9316                                                 (u32 *) (tmp + j))))
9317                                 break;
9318                 }
9319                 if (ret)
9320                         break;
9321
9322                 page_off = offset & pagemask;
9323                 size = pagesize;
9324                 if (len < size)
9325                         size = len;
9326
9327                 len -= size;
9328
9329                 memcpy(tmp + page_off, buf, size);
9330
9331                 offset = offset + (pagesize - page_off);
9332
9333                 tg3_enable_nvram_access(tp);
9334
9335                 /*
9336                  * Before we can erase the flash page, we need
9337                  * to issue a special "write enable" command.
9338                  */
9339                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9340
9341                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9342                         break;
9343
9344                 /* Erase the target page */
9345                 tw32(NVRAM_ADDR, phy_addr);
9346
9347                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9348                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9349
9350                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9351                         break;
9352
9353                 /* Issue another write enable to start the write. */
9354                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9355
9356                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9357                         break;
9358
9359                 for (j = 0; j < pagesize; j += 4) {
9360                         u32 data;
9361
9362                         data = *((u32 *) (tmp + j));
9363                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9364
9365                         tw32(NVRAM_ADDR, phy_addr + j);
9366
9367                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9368                                 NVRAM_CMD_WR;
9369
9370                         if (j == 0)
9371                                 nvram_cmd |= NVRAM_CMD_FIRST;
9372                         else if (j == (pagesize - 4))
9373                                 nvram_cmd |= NVRAM_CMD_LAST;
9374
9375                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9376                                 break;
9377                 }
9378                 if (ret)
9379                         break;
9380         }
9381
9382         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9383         tg3_nvram_exec_cmd(tp, nvram_cmd);
9384
9385         kfree(tmp);
9386
9387         return ret;
9388 }
9389
9390 /* offset and length are dword aligned */
9391 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9392                 u8 *buf)
9393 {
9394         int i, ret = 0;
9395
9396         for (i = 0; i < len; i += 4, offset += 4) {
9397                 u32 data, page_off, phy_addr, nvram_cmd;
9398
9399                 memcpy(&data, buf + i, 4);
9400                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9401
9402                 page_off = offset % tp->nvram_pagesize;
9403
9404                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9405
9406                 tw32(NVRAM_ADDR, phy_addr);
9407
9408                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9409
9410                 if ((page_off == 0) || (i == 0))
9411                         nvram_cmd |= NVRAM_CMD_FIRST;
9412                 if (page_off == (tp->nvram_pagesize - 4))
9413                         nvram_cmd |= NVRAM_CMD_LAST;
9414
9415                 if (i == (len - 4))
9416                         nvram_cmd |= NVRAM_CMD_LAST;
9417
9418                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9419                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9420                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9421                     (tp->nvram_jedecnum == JEDEC_ST) &&
9422                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9423
9424                         if ((ret = tg3_nvram_exec_cmd(tp,
9425                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9426                                 NVRAM_CMD_DONE)))
9427
9428                                 break;
9429                 }
9430                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9431                         /* We always do complete word writes to eeprom. */
9432                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9433                 }
9434
9435                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9436                         break;
9437         }
9438         return ret;
9439 }
9440
9441 /* offset and length are dword aligned */
9442 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9443 {
9444         int ret;
9445
9446         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9447                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
9448                 return -EINVAL;
9449         }
9450
9451         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9452                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9453                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9454                 udelay(40);
9455         }
9456
9457         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9458                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9459         }
9460         else {
9461                 u32 grc_mode;
9462
9463                 ret = tg3_nvram_lock(tp);
9464                 if (ret)
9465                         return ret;
9466
9467                 tg3_enable_nvram_access(tp);
9468                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9469                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9470                         tw32(NVRAM_WRITE1, 0x406);
9471
9472                 grc_mode = tr32(GRC_MODE);
9473                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9474
9475                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9476                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9477
9478                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9479                                 buf);
9480                 }
9481                 else {
9482                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9483                                 buf);
9484                 }
9485
9486                 grc_mode = tr32(GRC_MODE);
9487                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9488
9489                 tg3_disable_nvram_access(tp);
9490                 tg3_nvram_unlock(tp);
9491         }
9492
9493         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9494                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9495                 udelay(40);
9496         }
9497
9498         return ret;
9499 }
9500
9501 struct subsys_tbl_ent {
9502         u16 subsys_vendor, subsys_devid;
9503         u32 phy_id;
9504 };
9505
9506 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9507         /* Broadcom boards. */
9508         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9509         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9510         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9511         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9512         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9513         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9514         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9515         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9516         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9517         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9518         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9519
9520         /* 3com boards. */
9521         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9522         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9523         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9524         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9525         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9526
9527         /* DELL boards. */
9528         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9529         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9530         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9531         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9532
9533         /* Compaq boards. */
9534         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9535         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9536         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9537         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9538         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9539
9540         /* IBM boards. */
9541         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9542 };
9543
9544 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9545 {
9546         int i;
9547
9548         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9549                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9550                      tp->pdev->subsystem_vendor) &&
9551                     (subsys_id_to_phy_id[i].subsys_devid ==
9552                      tp->pdev->subsystem_device))
9553                         return &subsys_id_to_phy_id[i];
9554         }
9555         return NULL;
9556 }
9557
9558 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9559 {
9560         u32 val;
9561         u16 pmcsr;
9562
9563         /* On some early chips the SRAM cannot be accessed in D3hot state,
9564          * so need make sure we're in D0.
9565          */
9566         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9567         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9568         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9569         msleep(1);
9570
9571         /* Make sure register accesses (indirect or otherwise)
9572          * will function correctly.
9573          */
9574         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9575                                tp->misc_host_ctrl);
9576
9577         tp->phy_id = PHY_ID_INVALID;
9578         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9579
9580         /* Do not even try poking around in here on Sun parts.  */
9581         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9582                 /* All SUN chips are built-in LOMs. */
9583                 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9584                 return;
9585         }
9586
9587         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9588         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9589                 u32 nic_cfg, led_cfg;
9590                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9591                 int eeprom_phy_serdes = 0;
9592
9593                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9594                 tp->nic_sram_data_cfg = nic_cfg;
9595
9596                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9597                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9598                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9599                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9600                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9601                     (ver > 0) && (ver < 0x100))
9602                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9603
9604                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9605                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9606                         eeprom_phy_serdes = 1;
9607
9608                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9609                 if (nic_phy_id != 0) {
9610                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9611                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9612
9613                         eeprom_phy_id  = (id1 >> 16) << 10;
9614                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
9615                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
9616                 } else
9617                         eeprom_phy_id = 0;
9618
9619                 tp->phy_id = eeprom_phy_id;
9620                 if (eeprom_phy_serdes) {
9621                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9622                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9623                         else
9624                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9625                 }
9626
9627                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9628                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9629                                     SHASTA_EXT_LED_MODE_MASK);
9630                 else
9631                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9632
9633                 switch (led_cfg) {
9634                 default:
9635                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9636                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9637                         break;
9638
9639                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9640                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9641                         break;
9642
9643                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9644                         tp->led_ctrl = LED_CTRL_MODE_MAC;
9645
9646                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9647                          * read on some older 5700/5701 bootcode.
9648                          */
9649                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9650                             ASIC_REV_5700 ||
9651                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
9652                             ASIC_REV_5701)
9653                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9654
9655                         break;
9656
9657                 case SHASTA_EXT_LED_SHARED:
9658                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
9659                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9660                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9661                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9662                                                  LED_CTRL_MODE_PHY_2);
9663                         break;
9664
9665                 case SHASTA_EXT_LED_MAC:
9666                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9667                         break;
9668
9669                 case SHASTA_EXT_LED_COMBO:
9670                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
9671                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9672                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9673                                                  LED_CTRL_MODE_PHY_2);
9674                         break;
9675
9676                 };
9677
9678                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9679                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9680                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9681                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9682
9683                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9684                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9685
9686                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9687                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9688                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9689                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9690                 }
9691                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9692                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9693
9694                 if (cfg2 & (1 << 17))
9695                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9696
9697                 /* serdes signal pre-emphasis in register 0x590 set by */
9698                 /* bootcode if bit 18 is set */
9699                 if (cfg2 & (1 << 18))
9700                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9701         }
9702 }
9703
9704 static int __devinit tg3_phy_probe(struct tg3 *tp)
9705 {
9706         u32 hw_phy_id_1, hw_phy_id_2;
9707         u32 hw_phy_id, hw_phy_id_masked;
9708         int err;
9709
9710         /* Reading the PHY ID register can conflict with ASF
9711          * firwmare access to the PHY hardware.
9712          */
9713         err = 0;
9714         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9715                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9716         } else {
9717                 /* Now read the physical PHY_ID from the chip and verify
9718                  * that it is sane.  If it doesn't look good, we fall back
9719                  * to either the hard-coded table based PHY_ID and failing
9720                  * that the value found in the eeprom area.
9721                  */
9722                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9723                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9724
9725                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
9726                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9727                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
9728
9729                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9730         }
9731
9732         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9733                 tp->phy_id = hw_phy_id;
9734                 if (hw_phy_id_masked == PHY_ID_BCM8002)
9735                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9736                 else
9737                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9738         } else {
9739                 if (tp->phy_id != PHY_ID_INVALID) {
9740                         /* Do nothing, phy ID already set up in
9741                          * tg3_get_eeprom_hw_cfg().
9742                          */
9743                 } else {
9744                         struct subsys_tbl_ent *p;
9745
9746                         /* No eeprom signature?  Try the hardcoded
9747                          * subsys device table.
9748                          */
9749                         p = lookup_by_subsys(tp);
9750                         if (!p)
9751                                 return -ENODEV;
9752
9753                         tp->phy_id = p->phy_id;
9754                         if (!tp->phy_id ||
9755                             tp->phy_id == PHY_ID_BCM8002)
9756                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9757                 }
9758         }
9759
9760         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9761             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9762                 u32 bmsr, adv_reg, tg3_ctrl;
9763
9764                 tg3_readphy(tp, MII_BMSR, &bmsr);
9765                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9766                     (bmsr & BMSR_LSTATUS))
9767                         goto skip_phy_reset;
9768
9769                 err = tg3_phy_reset(tp);
9770                 if (err)
9771                         return err;
9772
9773                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9774                            ADVERTISE_100HALF | ADVERTISE_100FULL |
9775                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9776                 tg3_ctrl = 0;
9777                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9778                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9779                                     MII_TG3_CTRL_ADV_1000_FULL);
9780                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9781                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9782                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9783                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
9784                 }
9785
9786                 if (!tg3_copper_is_advertising_all(tp)) {
9787                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9788
9789                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9790                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9791
9792                         tg3_writephy(tp, MII_BMCR,
9793                                      BMCR_ANENABLE | BMCR_ANRESTART);
9794                 }
9795                 tg3_phy_set_wirespeed(tp);
9796
9797                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9798                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9799                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9800         }
9801
9802 skip_phy_reset:
9803         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9804                 err = tg3_init_5401phy_dsp(tp);
9805                 if (err)
9806                         return err;
9807         }
9808
9809         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9810                 err = tg3_init_5401phy_dsp(tp);
9811         }
9812
9813         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9814                 tp->link_config.advertising =
9815                         (ADVERTISED_1000baseT_Half |
9816                          ADVERTISED_1000baseT_Full |
9817                          ADVERTISED_Autoneg |
9818                          ADVERTISED_FIBRE);
9819         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9820                 tp->link_config.advertising &=
9821                         ~(ADVERTISED_1000baseT_Half |
9822                           ADVERTISED_1000baseT_Full);
9823
9824         return err;
9825 }
9826
9827 static void __devinit tg3_read_partno(struct tg3 *tp)
9828 {
9829         unsigned char vpd_data[256];
9830         int i;
9831         u32 magic;
9832
9833         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9834                 /* Sun decided not to put the necessary bits in the
9835                  * NVRAM of their onboard tg3 parts :(
9836                  */
9837                 strcpy(tp->board_part_number, "Sun 570X");
9838                 return;
9839         }
9840
9841         if (tg3_nvram_read_swab(tp, 0x0, &magic))
9842                 return;
9843
9844         if (magic == TG3_EEPROM_MAGIC) {
9845                 for (i = 0; i < 256; i += 4) {
9846                         u32 tmp;
9847
9848                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9849                                 goto out_not_found;
9850
9851                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
9852                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
9853                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9854                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9855                 }
9856         } else {
9857                 int vpd_cap;
9858
9859                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
9860                 for (i = 0; i < 256; i += 4) {
9861                         u32 tmp, j = 0;
9862                         u16 tmp16;
9863
9864                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
9865                                               i);
9866                         while (j++ < 100) {
9867                                 pci_read_config_word(tp->pdev, vpd_cap +
9868                                                      PCI_VPD_ADDR, &tmp16);
9869                                 if (tmp16 & 0x8000)
9870                                         break;
9871                                 msleep(1);
9872                         }
9873                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9874                                               &tmp);
9875                         tmp = cpu_to_le32(tmp);
9876                         memcpy(&vpd_data[i], &tmp, 4);
9877                 }
9878         }
9879
9880         /* Now parse and find the part number. */
9881         for (i = 0; i < 256; ) {
9882                 unsigned char val = vpd_data[i];
9883                 int block_end;
9884
9885                 if (val == 0x82 || val == 0x91) {
9886                         i = (i + 3 +
9887                              (vpd_data[i + 1] +
9888                               (vpd_data[i + 2] << 8)));
9889                         continue;
9890                 }
9891
9892                 if (val != 0x90)
9893                         goto out_not_found;
9894
9895                 block_end = (i + 3 +
9896                              (vpd_data[i + 1] +
9897                               (vpd_data[i + 2] << 8)));
9898                 i += 3;
9899                 while (i < block_end) {
9900                         if (vpd_data[i + 0] == 'P' &&
9901                             vpd_data[i + 1] == 'N') {
9902                                 int partno_len = vpd_data[i + 2];
9903
9904                                 if (partno_len > 24)
9905                                         goto out_not_found;
9906
9907                                 memcpy(tp->board_part_number,
9908                                        &vpd_data[i + 3],
9909                                        partno_len);
9910
9911                                 /* Success. */
9912                                 return;
9913                         }
9914                 }
9915
9916                 /* Part number not found. */
9917                 goto out_not_found;
9918         }
9919
9920 out_not_found:
9921         strcpy(tp->board_part_number, "none");
9922 }
9923
9924 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9925 {
9926         u32 val, offset, start;
9927
9928         if (tg3_nvram_read_swab(tp, 0, &val))
9929                 return;
9930
9931         if (val != TG3_EEPROM_MAGIC)
9932                 return;
9933
9934         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
9935             tg3_nvram_read_swab(tp, 0x4, &start))
9936                 return;
9937
9938         offset = tg3_nvram_logical_addr(tp, offset);
9939         if (tg3_nvram_read_swab(tp, offset, &val))
9940                 return;
9941
9942         if ((val & 0xfc000000) == 0x0c000000) {
9943                 u32 ver_offset, addr;
9944                 int i;
9945
9946                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
9947                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
9948                         return;
9949
9950                 if (val != 0)
9951                         return;
9952
9953                 addr = offset + ver_offset - start;
9954                 for (i = 0; i < 16; i += 4) {
9955                         if (tg3_nvram_read(tp, addr + i, &val))
9956                                 return;
9957
9958                         val = cpu_to_le32(val);
9959                         memcpy(tp->fw_ver + i, &val, 4);
9960                 }
9961         }
9962 }
9963
9964 #ifdef CONFIG_SPARC64
9965 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9966 {
9967         struct pci_dev *pdev = tp->pdev;
9968         struct pcidev_cookie *pcp = pdev->sysdata;
9969
9970         if (pcp != NULL) {
9971                 int node = pcp->prom_node;
9972                 u32 venid;
9973                 int err;
9974
9975                 err = prom_getproperty(node, "subsystem-vendor-id",
9976                                        (char *) &venid, sizeof(venid));
9977                 if (err == 0 || err == -1)
9978                         return 0;
9979                 if (venid == PCI_VENDOR_ID_SUN)
9980                         return 1;
9981
9982                 /* TG3 chips onboard the SunBlade-2500 don't have the
9983                  * subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
9984                  * are distinguishable from non-Sun variants by being
9985                  * named "network" by the firmware.  Non-Sun cards will
9986                  * show up as being named "ethernet".
9987                  */
9988                 if (!strcmp(pcp->prom_name, "network"))
9989                         return 1;
9990         }
9991         return 0;
9992 }
9993 #endif
9994
9995 static int __devinit tg3_get_invariants(struct tg3 *tp)
9996 {
9997         static struct pci_device_id write_reorder_chipsets[] = {
9998                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9999                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10000                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10001                              PCI_DEVICE_ID_VIA_8385_0) },
10002                 { },
10003         };
10004         u32 misc_ctrl_reg;
10005         u32 cacheline_sz_reg;
10006         u32 pci_state_reg, grc_misc_cfg;
10007         u32 val;
10008         u16 pci_cmd;
10009         int err;
10010
10011 #ifdef CONFIG_SPARC64
10012         if (tg3_is_sun_570X(tp))
10013                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
10014 #endif
10015
10016         /* Force memory write invalidate off.  If we leave it on,
10017          * then on 5700_BX chips we have to enable a workaround.
10018          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10019          * to match the cacheline size.  The Broadcom driver have this
10020          * workaround but turns MWI off all the times so never uses
10021          * it.  This seems to suggest that the workaround is insufficient.
10022          */
10023         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10024         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10025         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10026
10027         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10028          * has the register indirect write enable bit set before
10029          * we try to access any of the MMIO registers.  It is also
10030          * critical that the PCI-X hw workaround situation is decided
10031          * before that as well.
10032          */
10033         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10034                               &misc_ctrl_reg);
10035
10036         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10037                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10038
10039         /* Wrong chip ID in 5752 A0. This code can be removed later
10040          * as A0 is not in production.
10041          */
10042         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10043                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10044
10045         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10046          * we need to disable memory and use config. cycles
10047          * only to access all registers. The 5702/03 chips
10048          * can mistakenly decode the special cycles from the
10049          * ICH chipsets as memory write cycles, causing corruption
10050          * of register and memory space. Only certain ICH bridges
10051          * will drive special cycles with non-zero data during the
10052          * address phase which can fall within the 5703's address
10053          * range. This is not an ICH bug as the PCI spec allows
10054          * non-zero address during special cycles. However, only
10055          * these ICH bridges are known to drive non-zero addresses
10056          * during special cycles.
10057          *
10058          * Since special cycles do not cross PCI bridges, we only
10059          * enable this workaround if the 5703 is on the secondary
10060          * bus of these ICH bridges.
10061          */
10062         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10063             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10064                 static struct tg3_dev_id {
10065                         u32     vendor;
10066                         u32     device;
10067                         u32     rev;
10068                 } ich_chipsets[] = {
10069                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10070                           PCI_ANY_ID },
10071                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10072                           PCI_ANY_ID },
10073                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10074                           0xa },
10075                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10076                           PCI_ANY_ID },
10077                         { },
10078                 };
10079                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10080                 struct pci_dev *bridge = NULL;
10081
10082                 while (pci_id->vendor != 0) {
10083                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10084                                                 bridge);
10085                         if (!bridge) {
10086                                 pci_id++;
10087                                 continue;
10088                         }
10089                         if (pci_id->rev != PCI_ANY_ID) {
10090                                 u8 rev;
10091
10092                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10093                                                      &rev);
10094                                 if (rev > pci_id->rev)
10095                                         continue;
10096                         }
10097                         if (bridge->subordinate &&
10098                             (bridge->subordinate->number ==
10099                              tp->pdev->bus->number)) {
10100
10101                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10102                                 pci_dev_put(bridge);
10103                                 break;
10104                         }
10105                 }
10106         }
10107
10108         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10109          * DMA addresses > 40-bit. This bridge may have other additional
10110          * 57xx devices behind it in some 4-port NIC designs for example.
10111          * Any tg3 device found behind the bridge will also need the 40-bit
10112          * DMA workaround.
10113          */
10114         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10116                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10117                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10118                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10119         }
10120         else {
10121                 struct pci_dev *bridge = NULL;
10122
10123                 do {
10124                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10125                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10126                                                 bridge);
10127                         if (bridge && bridge->subordinate &&
10128                             (bridge->subordinate->number <=
10129                              tp->pdev->bus->number) &&
10130                             (bridge->subordinate->subordinate >=
10131                              tp->pdev->bus->number)) {
10132                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10133                                 pci_dev_put(bridge);
10134                                 break;
10135                         }
10136                 } while (bridge);
10137         }
10138
10139         /* Initialize misc host control in PCI block. */
10140         tp->misc_host_ctrl |= (misc_ctrl_reg &
10141                                MISC_HOST_CTRL_CHIPREV);
10142         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10143                                tp->misc_host_ctrl);
10144
10145         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10146                               &cacheline_sz_reg);
10147
10148         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10149         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10150         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10151         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10152
10153         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10154             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10155             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10156             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10157             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10158                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10159
10160         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10161             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10162                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10163
10164         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10165                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10166                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10167                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10168                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10169                 } else
10170                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
10171         }
10172
10173         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10174             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10175             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10176             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10177             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
10178                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10179
10180         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10181                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10182
10183         /* If we have an AMD 762 or VIA K8T800 chipset, write
10184          * reordering to the mailbox registers done by the host
10185          * controller can cause major troubles.  We read back from
10186          * every mailbox register write to force the writes to be
10187          * posted to the chip in order.
10188          */
10189         if (pci_dev_present(write_reorder_chipsets) &&
10190             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10191                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10192
10193         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10194             tp->pci_lat_timer < 64) {
10195                 tp->pci_lat_timer = 64;
10196
10197                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10198                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10199                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10200                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10201
10202                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10203                                        cacheline_sz_reg);
10204         }
10205
10206         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10207                               &pci_state_reg);
10208
10209         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10210                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10211
10212                 /* If this is a 5700 BX chipset, and we are in PCI-X
10213                  * mode, enable register write workaround.
10214                  *
10215                  * The workaround is to use indirect register accesses
10216                  * for all chip writes not to mailbox registers.
10217                  */
10218                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10219                         u32 pm_reg;
10220                         u16 pci_cmd;
10221
10222                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10223
10224                         /* The chip can have it's power management PCI config
10225                          * space registers clobbered due to this bug.
10226                          * So explicitly force the chip into D0 here.
10227                          */
10228                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10229                                               &pm_reg);
10230                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10231                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10232                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10233                                                pm_reg);
10234
10235                         /* Also, force SERR#/PERR# in PCI command. */
10236                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10237                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10238                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10239                 }
10240         }
10241
10242         /* 5700 BX chips need to have their TX producer index mailboxes
10243          * written twice to workaround a bug.
10244          */
10245         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10246                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10247
10248         /* Back to back register writes can cause problems on this chip,
10249          * the workaround is to read back all reg writes except those to
10250          * mailbox regs.  See tg3_write_indirect_reg32().
10251          *
10252          * PCI Express 5750_A0 rev chips need this workaround too.
10253          */
10254         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10255             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10256              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10257                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10258
10259         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10260                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10261         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10262                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10263
10264         /* Chip-specific fixup from Broadcom driver */
10265         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10266             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10267                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10268                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10269         }
10270
10271         /* Default fast path register access methods */
10272         tp->read32 = tg3_read32;
10273         tp->write32 = tg3_write32;
10274         tp->read32_mbox = tg3_read32;
10275         tp->write32_mbox = tg3_write32;
10276         tp->write32_tx_mbox = tg3_write32;
10277         tp->write32_rx_mbox = tg3_write32;
10278
10279         /* Various workaround register access methods */
10280         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10281                 tp->write32 = tg3_write_indirect_reg32;
10282         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10283                 tp->write32 = tg3_write_flush_reg32;
10284
10285         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10286             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10287                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10288                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10289                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10290         }
10291
10292         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10293                 tp->read32 = tg3_read_indirect_reg32;
10294                 tp->write32 = tg3_write_indirect_reg32;
10295                 tp->read32_mbox = tg3_read_indirect_mbox;
10296                 tp->write32_mbox = tg3_write_indirect_mbox;
10297                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10298                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10299
10300                 iounmap(tp->regs);
10301                 tp->regs = NULL;
10302
10303                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10304                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10305                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10306         }
10307
10308         if (tp->write32 == tg3_write_indirect_reg32 ||
10309             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10310              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10311               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
10312             (tp->tg3_flags2 & TG3_FLG2_SUN_570X))
10313                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10314
10315         /* Get eeprom hw config before calling tg3_set_power_state().
10316          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10317          * determined before calling tg3_set_power_state() so that
10318          * we know whether or not to switch out of Vaux power.
10319          * When the flag is set, it means that GPIO1 is used for eeprom
10320          * write protect and also implies that it is a LOM where GPIOs
10321          * are not used to switch power.
10322          */
10323         tg3_get_eeprom_hw_cfg(tp);
10324
10325         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10326          * GPIO1 driven high will bring 5700's external PHY out of reset.
10327          * It is also used as eeprom write protect on LOMs.
10328          */
10329         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10330         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10331             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10332                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10333                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10334         /* Unused GPIO3 must be driven as output on 5752 because there
10335          * are no pull-up resistors on unused GPIO pins.
10336          */
10337         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10338                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10339
10340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10341                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10342
10343         /* Force the chip into D0. */
10344         err = tg3_set_power_state(tp, PCI_D0);
10345         if (err) {
10346                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10347                        pci_name(tp->pdev));
10348                 return err;
10349         }
10350
10351         /* 5700 B0 chips do not support checksumming correctly due
10352          * to hardware bugs.
10353          */
10354         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10355                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10356
10357         /* Derive initial jumbo mode from MTU assigned in
10358          * ether_setup() via the alloc_etherdev() call
10359          */
10360         if (tp->dev->mtu > ETH_DATA_LEN &&
10361             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10362                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10363
10364         /* Determine WakeOnLan speed to use. */
10365         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10366             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10367             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10368             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10369                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10370         } else {
10371                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10372         }
10373
10374         /* A few boards don't want Ethernet@WireSpeed phy feature */
10375         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10376             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10377              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10378              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10379             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10380                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10381
10382         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10383             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10384                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10385         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10386                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10387
10388         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10389                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10390                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10391                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10392                 else
10393                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10394         }
10395
10396         tp->coalesce_mode = 0;
10397         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10398             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10399                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10400
10401         /* Initialize MAC MI mode, polling disabled. */
10402         tw32_f(MAC_MI_MODE, tp->mi_mode);
10403         udelay(80);
10404
10405         /* Initialize data/descriptor byte/word swapping. */
10406         val = tr32(GRC_MODE);
10407         val &= GRC_MODE_HOST_STACKUP;
10408         tw32(GRC_MODE, val | tp->grc_mode);
10409
10410         tg3_switch_clocks(tp);
10411
10412         /* Clear this out for sanity. */
10413         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10414
10415         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10416                               &pci_state_reg);
10417         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10418             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10419                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10420
10421                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10422                     chiprevid == CHIPREV_ID_5701_B0 ||
10423                     chiprevid == CHIPREV_ID_5701_B2 ||
10424                     chiprevid == CHIPREV_ID_5701_B5) {
10425                         void __iomem *sram_base;
10426
10427                         /* Write some dummy words into the SRAM status block
10428                          * area, see if it reads back correctly.  If the return
10429                          * value is bad, force enable the PCIX workaround.
10430                          */
10431                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10432
10433                         writel(0x00000000, sram_base);
10434                         writel(0x00000000, sram_base + 4);
10435                         writel(0xffffffff, sram_base + 4);
10436                         if (readl(sram_base) != 0x00000000)
10437                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10438                 }
10439         }
10440
10441         udelay(50);
10442         tg3_nvram_init(tp);
10443
10444         grc_misc_cfg = tr32(GRC_MISC_CFG);
10445         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10446
10447         /* Broadcom's driver says that CIOBE multisplit has a bug */
10448 #if 0
10449         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10450             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10451                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10452                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10453         }
10454 #endif
10455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10456             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10457              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10458                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10459
10460         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10461             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10462                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10463         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10464                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10465                                       HOSTCC_MODE_CLRTICK_TXBD);
10466
10467                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10468                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10469                                        tp->misc_host_ctrl);
10470         }
10471
10472         /* these are limited to 10/100 only */
10473         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10474              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10475             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10476              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10477              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10478               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10479               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10480             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10481              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10482               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10483                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10484
10485         err = tg3_phy_probe(tp);
10486         if (err) {
10487                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10488                        pci_name(tp->pdev), err);
10489                 /* ... but do not return immediately ... */
10490         }
10491
10492         tg3_read_partno(tp);
10493         tg3_read_fw_ver(tp);
10494
10495         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10496                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10497         } else {
10498                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10499                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10500                 else
10501                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10502         }
10503
10504         /* 5700 {AX,BX} chips have a broken status block link
10505          * change bit implementation, so we must use the
10506          * status register in those cases.
10507          */
10508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10509                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10510         else
10511                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10512
10513         /* The led_ctrl is set during tg3_phy_probe, here we might
10514          * have to force the link status polling mechanism based
10515          * upon subsystem IDs.
10516          */
10517         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10518             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10519                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10520                                   TG3_FLAG_USE_LINKCHG_REG);
10521         }
10522
10523         /* For all SERDES we poll the MAC status register. */
10524         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10525                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10526         else
10527                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10528
10529         /* All chips before 5787 can get confused if TX buffers
10530          * straddle the 4GB address boundary in some cases.
10531          */
10532         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10533             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10534                 tp->dev->hard_start_xmit = tg3_start_xmit;
10535         else
10536                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10537
10538         tp->rx_offset = 2;
10539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10540             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10541                 tp->rx_offset = 0;
10542
10543         /* By default, disable wake-on-lan.  User can change this
10544          * using ETHTOOL_SWOL.
10545          */
10546         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10547
10548         return err;
10549 }
10550
10551 #ifdef CONFIG_SPARC64
10552 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10553 {
10554         struct net_device *dev = tp->dev;
10555         struct pci_dev *pdev = tp->pdev;
10556         struct pcidev_cookie *pcp = pdev->sysdata;
10557
10558         if (pcp != NULL) {
10559                 int node = pcp->prom_node;
10560
10561                 if (prom_getproplen(node, "local-mac-address") == 6) {
10562                         prom_getproperty(node, "local-mac-address",
10563                                          dev->dev_addr, 6);
10564                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10565                         return 0;
10566                 }
10567         }
10568         return -ENODEV;
10569 }
10570
10571 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10572 {
10573         struct net_device *dev = tp->dev;
10574
10575         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10576         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10577         return 0;
10578 }
10579 #endif
10580
10581 static int __devinit tg3_get_device_address(struct tg3 *tp)
10582 {
10583         struct net_device *dev = tp->dev;
10584         u32 hi, lo, mac_offset;
10585         int addr_ok = 0;
10586
10587 #ifdef CONFIG_SPARC64
10588         if (!tg3_get_macaddr_sparc(tp))
10589                 return 0;
10590 #endif
10591
10592         mac_offset = 0x7c;
10593         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10594              !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
10595             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10596                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10597                         mac_offset = 0xcc;
10598                 if (tg3_nvram_lock(tp))
10599                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10600                 else
10601                         tg3_nvram_unlock(tp);
10602         }
10603
10604         /* First try to get it from MAC address mailbox. */
10605         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10606         if ((hi >> 16) == 0x484b) {
10607                 dev->dev_addr[0] = (hi >>  8) & 0xff;
10608                 dev->dev_addr[1] = (hi >>  0) & 0xff;
10609
10610                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10611                 dev->dev_addr[2] = (lo >> 24) & 0xff;
10612                 dev->dev_addr[3] = (lo >> 16) & 0xff;
10613                 dev->dev_addr[4] = (lo >>  8) & 0xff;
10614                 dev->dev_addr[5] = (lo >>  0) & 0xff;
10615
10616                 /* Some old bootcode may report a 0 MAC address in SRAM */
10617                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10618         }
10619         if (!addr_ok) {
10620                 /* Next, try NVRAM. */
10621                 if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
10622                     !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10623                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10624                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
10625                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
10626                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
10627                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
10628                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
10629                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
10630                 }
10631                 /* Finally just fetch it out of the MAC control regs. */
10632                 else {
10633                         hi = tr32(MAC_ADDR_0_HIGH);
10634                         lo = tr32(MAC_ADDR_0_LOW);
10635
10636                         dev->dev_addr[5] = lo & 0xff;
10637                         dev->dev_addr[4] = (lo >> 8) & 0xff;
10638                         dev->dev_addr[3] = (lo >> 16) & 0xff;
10639                         dev->dev_addr[2] = (lo >> 24) & 0xff;
10640                         dev->dev_addr[1] = hi & 0xff;
10641                         dev->dev_addr[0] = (hi >> 8) & 0xff;
10642                 }
10643         }
10644
10645         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
10646 #ifdef CONFIG_SPARC64
10647                 if (!tg3_get_default_macaddr_sparc(tp))
10648                         return 0;
10649 #endif
10650                 return -EINVAL;
10651         }
10652         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
10653         return 0;
10654 }
10655
10656 #define BOUNDARY_SINGLE_CACHELINE       1
10657 #define BOUNDARY_MULTI_CACHELINE        2
10658
10659 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10660 {
10661         int cacheline_size;
10662         u8 byte;
10663         int goal;
10664
10665         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10666         if (byte == 0)
10667                 cacheline_size = 1024;
10668         else
10669                 cacheline_size = (int) byte * 4;
10670
10671         /* On 5703 and later chips, the boundary bits have no
10672          * effect.
10673          */
10674         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10675             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10676             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10677                 goto out;
10678
10679 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10680         goal = BOUNDARY_MULTI_CACHELINE;
10681 #else
10682 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10683         goal = BOUNDARY_SINGLE_CACHELINE;
10684 #else
10685         goal = 0;
10686 #endif
10687 #endif
10688
10689         if (!goal)
10690                 goto out;
10691
10692         /* PCI controllers on most RISC systems tend to disconnect
10693          * when a device tries to burst across a cache-line boundary.
10694          * Therefore, letting tg3 do so just wastes PCI bandwidth.
10695          *
10696          * Unfortunately, for PCI-E there are only limited
10697          * write-side controls for this, and thus for reads
10698          * we will still get the disconnects.  We'll also waste
10699          * these PCI cycles for both read and write for chips
10700          * other than 5700 and 5701 which do not implement the
10701          * boundary bits.
10702          */
10703         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10704             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10705                 switch (cacheline_size) {
10706                 case 16:
10707                 case 32:
10708                 case 64:
10709                 case 128:
10710                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10711                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10712                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10713                         } else {
10714                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10715                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10716                         }
10717                         break;
10718
10719                 case 256:
10720                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10721                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10722                         break;
10723
10724                 default:
10725                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10726                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10727                         break;
10728                 };
10729         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10730                 switch (cacheline_size) {
10731                 case 16:
10732                 case 32:
10733                 case 64:
10734                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10735                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10736                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10737                                 break;
10738                         }
10739                         /* fallthrough */
10740                 case 128:
10741                 default:
10742                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10743                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10744                         break;
10745                 };
10746         } else {
10747                 switch (cacheline_size) {
10748                 case 16:
10749                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10750                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10751                                         DMA_RWCTRL_WRITE_BNDRY_16);
10752                                 break;
10753                         }
10754                         /* fallthrough */
10755                 case 32:
10756                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10757                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10758                                         DMA_RWCTRL_WRITE_BNDRY_32);
10759                                 break;
10760                         }
10761                         /* fallthrough */
10762                 case 64:
10763                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10764                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10765                                         DMA_RWCTRL_WRITE_BNDRY_64);
10766                                 break;
10767                         }
10768                         /* fallthrough */
10769                 case 128:
10770                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10771                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10772                                         DMA_RWCTRL_WRITE_BNDRY_128);
10773                                 break;
10774                         }
10775                         /* fallthrough */
10776                 case 256:
10777                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
10778                                 DMA_RWCTRL_WRITE_BNDRY_256);
10779                         break;
10780                 case 512:
10781                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
10782                                 DMA_RWCTRL_WRITE_BNDRY_512);
10783                         break;
10784                 case 1024:
10785                 default:
10786                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10787                                 DMA_RWCTRL_WRITE_BNDRY_1024);
10788                         break;
10789                 };
10790         }
10791
10792 out:
10793         return val;
10794 }
10795
10796 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10797 {
10798         struct tg3_internal_buffer_desc test_desc;
10799         u32 sram_dma_descs;
10800         int i, ret;
10801
10802         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10803
10804         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10805         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10806         tw32(RDMAC_STATUS, 0);
10807         tw32(WDMAC_STATUS, 0);
10808
10809         tw32(BUFMGR_MODE, 0);
10810         tw32(FTQ_RESET, 0);
10811
10812         test_desc.addr_hi = ((u64) buf_dma) >> 32;
10813         test_desc.addr_lo = buf_dma & 0xffffffff;
10814         test_desc.nic_mbuf = 0x00002100;
10815         test_desc.len = size;
10816
10817         /*
10818          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10819          * the *second* time the tg3 driver was getting loaded after an
10820          * initial scan.
10821          *
10822          * Broadcom tells me:
10823          *   ...the DMA engine is connected to the GRC block and a DMA
10824          *   reset may affect the GRC block in some unpredictable way...
10825          *   The behavior of resets to individual blocks has not been tested.
10826          *
10827          * Broadcom noted the GRC reset will also reset all sub-components.
10828          */
10829         if (to_device) {
10830                 test_desc.cqid_sqid = (13 << 8) | 2;
10831
10832                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10833                 udelay(40);
10834         } else {
10835                 test_desc.cqid_sqid = (16 << 8) | 7;
10836
10837                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10838                 udelay(40);
10839         }
10840         test_desc.flags = 0x00000005;
10841
10842         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10843                 u32 val;
10844
10845                 val = *(((u32 *)&test_desc) + i);
10846                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10847                                        sram_dma_descs + (i * sizeof(u32)));
10848                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10849         }
10850         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10851
10852         if (to_device) {
10853                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10854         } else {
10855                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10856         }
10857
10858         ret = -ENODEV;
10859         for (i = 0; i < 40; i++) {
10860                 u32 val;
10861
10862                 if (to_device)
10863                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10864                 else
10865                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10866                 if ((val & 0xffff) == sram_dma_descs) {
10867                         ret = 0;
10868                         break;
10869                 }
10870
10871                 udelay(100);
10872         }
10873
10874         return ret;
10875 }
10876
10877 #define TEST_BUFFER_SIZE        0x2000
10878
10879 static int __devinit tg3_test_dma(struct tg3 *tp)
10880 {
10881         dma_addr_t buf_dma;
10882         u32 *buf, saved_dma_rwctrl;
10883         int ret;
10884
10885         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10886         if (!buf) {
10887                 ret = -ENOMEM;
10888                 goto out_nofree;
10889         }
10890
10891         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10892                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10893
10894         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10895
10896         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10897                 /* DMA read watermark not used on PCIE */
10898                 tp->dma_rwctrl |= 0x00180000;
10899         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10900                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10901                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10902                         tp->dma_rwctrl |= 0x003f0000;
10903                 else
10904                         tp->dma_rwctrl |= 0x003f000f;
10905         } else {
10906                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10907                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10908                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10909
10910                         /* If the 5704 is behind the EPB bridge, we can
10911                          * do the less restrictive ONE_DMA workaround for
10912                          * better performance.
10913                          */
10914                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
10915                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10916                                 tp->dma_rwctrl |= 0x8000;
10917                         else if (ccval == 0x6 || ccval == 0x7)
10918                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10919
10920                         /* Set bit 23 to enable PCIX hw bug fix */
10921                         tp->dma_rwctrl |= 0x009f0000;
10922                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10923                         /* 5780 always in PCIX mode */
10924                         tp->dma_rwctrl |= 0x00144000;
10925                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10926                         /* 5714 always in PCIX mode */
10927                         tp->dma_rwctrl |= 0x00148000;
10928                 } else {
10929                         tp->dma_rwctrl |= 0x001b000f;
10930                 }
10931         }
10932
10933         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10934             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10935                 tp->dma_rwctrl &= 0xfffffff0;
10936
10937         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10939                 /* Remove this if it causes problems for some boards. */
10940                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10941
10942                 /* On 5700/5701 chips, we need to set this bit.
10943                  * Otherwise the chip will issue cacheline transactions
10944                  * to streamable DMA memory with not all the byte
10945                  * enables turned on.  This is an error on several
10946                  * RISC PCI controllers, in particular sparc64.
10947                  *
10948                  * On 5703/5704 chips, this bit has been reassigned
10949                  * a different meaning.  In particular, it is used
10950                  * on those chips to enable a PCI-X workaround.
10951                  */
10952                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10953         }
10954
10955         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10956
10957 #if 0
10958         /* Unneeded, already done by tg3_get_invariants.  */
10959         tg3_switch_clocks(tp);
10960 #endif
10961
10962         ret = 0;
10963         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10964             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10965                 goto out;
10966
10967         /* It is best to perform DMA test with maximum write burst size
10968          * to expose the 5700/5701 write DMA bug.
10969          */
10970         saved_dma_rwctrl = tp->dma_rwctrl;
10971         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10972         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10973
10974         while (1) {
10975                 u32 *p = buf, i;
10976
10977                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10978                         p[i] = i;
10979
10980                 /* Send the buffer to the chip. */
10981                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10982                 if (ret) {
10983                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10984                         break;
10985                 }
10986
10987 #if 0
10988                 /* validate data reached card RAM correctly. */
10989                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10990                         u32 val;
10991                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
10992                         if (le32_to_cpu(val) != p[i]) {
10993                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
10994                                 /* ret = -ENODEV here? */
10995                         }
10996                         p[i] = 0;
10997                 }
10998 #endif
10999                 /* Now read it back. */
11000                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11001                 if (ret) {
11002                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11003
11004                         break;
11005                 }
11006
11007                 /* Verify it. */
11008                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11009                         if (p[i] == i)
11010                                 continue;
11011
11012                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11013                             DMA_RWCTRL_WRITE_BNDRY_16) {
11014                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11015                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11016                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11017                                 break;
11018                         } else {
11019                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11020                                 ret = -ENODEV;
11021                                 goto out;
11022                         }
11023                 }
11024
11025                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11026                         /* Success. */
11027                         ret = 0;
11028                         break;
11029                 }
11030         }
11031         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11032             DMA_RWCTRL_WRITE_BNDRY_16) {
11033                 static struct pci_device_id dma_wait_state_chipsets[] = {
11034                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11035                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11036                         { },
11037                 };
11038
11039                 /* DMA test passed without adjusting DMA boundary,
11040                  * now look for chipsets that are known to expose the
11041                  * DMA bug without failing the test.
11042                  */
11043                 if (pci_dev_present(dma_wait_state_chipsets)) {
11044                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11045                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11046                 }
11047                 else
11048                         /* Safe to use the calculated DMA boundary. */
11049                         tp->dma_rwctrl = saved_dma_rwctrl;
11050
11051                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11052         }
11053
11054 out:
11055         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11056 out_nofree:
11057         return ret;
11058 }
11059
11060 static void __devinit tg3_init_link_config(struct tg3 *tp)
11061 {
11062         tp->link_config.advertising =
11063                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11064                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11065                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11066                  ADVERTISED_Autoneg | ADVERTISED_MII);
11067         tp->link_config.speed = SPEED_INVALID;
11068         tp->link_config.duplex = DUPLEX_INVALID;
11069         tp->link_config.autoneg = AUTONEG_ENABLE;
11070         tp->link_config.active_speed = SPEED_INVALID;
11071         tp->link_config.active_duplex = DUPLEX_INVALID;
11072         tp->link_config.phy_is_low_power = 0;
11073         tp->link_config.orig_speed = SPEED_INVALID;
11074         tp->link_config.orig_duplex = DUPLEX_INVALID;
11075         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11076 }
11077
11078 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11079 {
11080         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11081                 tp->bufmgr_config.mbuf_read_dma_low_water =
11082                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11083                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11084                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11085                 tp->bufmgr_config.mbuf_high_water =
11086                         DEFAULT_MB_HIGH_WATER_5705;
11087
11088                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11089                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11090                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11091                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11092                 tp->bufmgr_config.mbuf_high_water_jumbo =
11093                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11094         } else {
11095                 tp->bufmgr_config.mbuf_read_dma_low_water =
11096                         DEFAULT_MB_RDMA_LOW_WATER;
11097                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11098                         DEFAULT_MB_MACRX_LOW_WATER;
11099                 tp->bufmgr_config.mbuf_high_water =
11100                         DEFAULT_MB_HIGH_WATER;
11101
11102                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11103                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11104                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11105                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11106                 tp->bufmgr_config.mbuf_high_water_jumbo =
11107                         DEFAULT_MB_HIGH_WATER_JUMBO;
11108         }
11109
11110         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11111         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11112 }
11113
11114 static char * __devinit tg3_phy_string(struct tg3 *tp)
11115 {
11116         switch (tp->phy_id & PHY_ID_MASK) {
11117         case PHY_ID_BCM5400:    return "5400";
11118         case PHY_ID_BCM5401:    return "5401";
11119         case PHY_ID_BCM5411:    return "5411";
11120         case PHY_ID_BCM5701:    return "5701";
11121         case PHY_ID_BCM5703:    return "5703";
11122         case PHY_ID_BCM5704:    return "5704";
11123         case PHY_ID_BCM5705:    return "5705";
11124         case PHY_ID_BCM5750:    return "5750";
11125         case PHY_ID_BCM5752:    return "5752";
11126         case PHY_ID_BCM5714:    return "5714";
11127         case PHY_ID_BCM5780:    return "5780";
11128         case PHY_ID_BCM5755:    return "5755";
11129         case PHY_ID_BCM5787:    return "5787";
11130         case PHY_ID_BCM8002:    return "8002/serdes";
11131         case 0:                 return "serdes";
11132         default:                return "unknown";
11133         };
11134 }
11135
11136 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11137 {
11138         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11139                 strcpy(str, "PCI Express");
11140                 return str;
11141         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11142                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11143
11144                 strcpy(str, "PCIX:");
11145
11146                 if ((clock_ctrl == 7) ||
11147                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11148                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11149                         strcat(str, "133MHz");
11150                 else if (clock_ctrl == 0)
11151                         strcat(str, "33MHz");
11152                 else if (clock_ctrl == 2)
11153                         strcat(str, "50MHz");
11154                 else if (clock_ctrl == 4)
11155                         strcat(str, "66MHz");
11156                 else if (clock_ctrl == 6)
11157                         strcat(str, "100MHz");
11158         } else {
11159                 strcpy(str, "PCI:");
11160                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11161                         strcat(str, "66MHz");
11162                 else
11163                         strcat(str, "33MHz");
11164         }
11165         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11166                 strcat(str, ":32-bit");
11167         else
11168                 strcat(str, ":64-bit");
11169         return str;
11170 }
11171
11172 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11173 {
11174         struct pci_dev *peer;
11175         unsigned int func, devnr = tp->pdev->devfn & ~7;
11176
11177         for (func = 0; func < 8; func++) {
11178                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11179                 if (peer && peer != tp->pdev)
11180                         break;
11181                 pci_dev_put(peer);
11182         }
11183         /* 5704 can be configured in single-port mode, set peer to
11184          * tp->pdev in that case.
11185          */
11186         if (!peer) {
11187                 peer = tp->pdev;
11188                 return peer;
11189         }
11190
11191         /*
11192          * We don't need to keep the refcount elevated; there's no way
11193          * to remove one half of this device without removing the other
11194          */
11195         pci_dev_put(peer);
11196
11197         return peer;
11198 }
11199
11200 static void __devinit tg3_init_coal(struct tg3 *tp)
11201 {
11202         struct ethtool_coalesce *ec = &tp->coal;
11203
11204         memset(ec, 0, sizeof(*ec));
11205         ec->cmd = ETHTOOL_GCOALESCE;
11206         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11207         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11208         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11209         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11210         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11211         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11212         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11213         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11214         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11215
11216         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11217                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11218                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11219                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11220                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11221                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11222         }
11223
11224         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11225                 ec->rx_coalesce_usecs_irq = 0;
11226                 ec->tx_coalesce_usecs_irq = 0;
11227                 ec->stats_block_coalesce_usecs = 0;
11228         }
11229 }
11230
11231 static int __devinit tg3_init_one(struct pci_dev *pdev,
11232                                   const struct pci_device_id *ent)
11233 {
11234         static int tg3_version_printed = 0;
11235         unsigned long tg3reg_base, tg3reg_len;
11236         struct net_device *dev;
11237         struct tg3 *tp;
11238         int i, err, pm_cap;
11239         char str[40];
11240         u64 dma_mask, persist_dma_mask;
11241
11242         if (tg3_version_printed++ == 0)
11243                 printk(KERN_INFO "%s", version);
11244
11245         err = pci_enable_device(pdev);
11246         if (err) {
11247                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11248                        "aborting.\n");
11249                 return err;
11250         }
11251
11252         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11253                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11254                        "base address, aborting.\n");
11255                 err = -ENODEV;
11256                 goto err_out_disable_pdev;
11257         }
11258
11259         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11260         if (err) {
11261                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11262                        "aborting.\n");
11263                 goto err_out_disable_pdev;
11264         }
11265
11266         pci_set_master(pdev);
11267
11268         /* Find power-management capability. */
11269         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11270         if (pm_cap == 0) {
11271                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11272                        "aborting.\n");
11273                 err = -EIO;
11274                 goto err_out_free_res;
11275         }
11276
11277         tg3reg_base = pci_resource_start(pdev, 0);
11278         tg3reg_len = pci_resource_len(pdev, 0);
11279
11280         dev = alloc_etherdev(sizeof(*tp));
11281         if (!dev) {
11282                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11283                 err = -ENOMEM;
11284                 goto err_out_free_res;
11285         }
11286
11287         SET_MODULE_OWNER(dev);
11288         SET_NETDEV_DEV(dev, &pdev->dev);
11289
11290         dev->features |= NETIF_F_LLTX;
11291 #if TG3_VLAN_TAG_USED
11292         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11293         dev->vlan_rx_register = tg3_vlan_rx_register;
11294         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11295 #endif
11296
11297         tp = netdev_priv(dev);
11298         tp->pdev = pdev;
11299         tp->dev = dev;
11300         tp->pm_cap = pm_cap;
11301         tp->mac_mode = TG3_DEF_MAC_MODE;
11302         tp->rx_mode = TG3_DEF_RX_MODE;
11303         tp->tx_mode = TG3_DEF_TX_MODE;
11304         tp->mi_mode = MAC_MI_MODE_BASE;
11305         if (tg3_debug > 0)
11306                 tp->msg_enable = tg3_debug;
11307         else
11308                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11309
11310         /* The word/byte swap controls here control register access byte
11311          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11312          * setting below.
11313          */
11314         tp->misc_host_ctrl =
11315                 MISC_HOST_CTRL_MASK_PCI_INT |
11316                 MISC_HOST_CTRL_WORD_SWAP |
11317                 MISC_HOST_CTRL_INDIR_ACCESS |
11318                 MISC_HOST_CTRL_PCISTATE_RW;
11319
11320         /* The NONFRM (non-frame) byte/word swap controls take effect
11321          * on descriptor entries, anything which isn't packet data.
11322          *
11323          * The StrongARM chips on the board (one for tx, one for rx)
11324          * are running in big-endian mode.
11325          */
11326         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11327                         GRC_MODE_WSWAP_NONFRM_DATA);
11328 #ifdef __BIG_ENDIAN
11329         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11330 #endif
11331         spin_lock_init(&tp->lock);
11332         spin_lock_init(&tp->tx_lock);
11333         spin_lock_init(&tp->indirect_lock);
11334         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11335
11336         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11337         if (tp->regs == 0UL) {
11338                 printk(KERN_ERR PFX "Cannot map device registers, "
11339                        "aborting.\n");
11340                 err = -ENOMEM;
11341                 goto err_out_free_dev;
11342         }
11343
11344         tg3_init_link_config(tp);
11345
11346         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11347         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11348         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11349
11350         dev->open = tg3_open;
11351         dev->stop = tg3_close;
11352         dev->get_stats = tg3_get_stats;
11353         dev->set_multicast_list = tg3_set_rx_mode;
11354         dev->set_mac_address = tg3_set_mac_addr;
11355         dev->do_ioctl = tg3_ioctl;
11356         dev->tx_timeout = tg3_tx_timeout;
11357         dev->poll = tg3_poll;
11358         dev->ethtool_ops = &tg3_ethtool_ops;
11359         dev->weight = 64;
11360         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11361         dev->change_mtu = tg3_change_mtu;
11362         dev->irq = pdev->irq;
11363 #ifdef CONFIG_NET_POLL_CONTROLLER
11364         dev->poll_controller = tg3_poll_controller;
11365 #endif
11366
11367         err = tg3_get_invariants(tp);
11368         if (err) {
11369                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11370                        "aborting.\n");
11371                 goto err_out_iounmap;
11372         }
11373
11374         /* The EPB bridge inside 5714, 5715, and 5780 and any
11375          * device behind the EPB cannot support DMA addresses > 40-bit.
11376          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11377          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11378          * do DMA address check in tg3_start_xmit().
11379          */
11380         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11381                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11382         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11383                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11384 #ifdef CONFIG_HIGHMEM
11385                 dma_mask = DMA_64BIT_MASK;
11386 #endif
11387         } else
11388                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11389
11390         /* Configure DMA attributes. */
11391         if (dma_mask > DMA_32BIT_MASK) {
11392                 err = pci_set_dma_mask(pdev, dma_mask);
11393                 if (!err) {
11394                         dev->features |= NETIF_F_HIGHDMA;
11395                         err = pci_set_consistent_dma_mask(pdev,
11396                                                           persist_dma_mask);
11397                         if (err < 0) {
11398                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11399                                        "DMA for consistent allocations\n");
11400                                 goto err_out_iounmap;
11401                         }
11402                 }
11403         }
11404         if (err || dma_mask == DMA_32BIT_MASK) {
11405                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11406                 if (err) {
11407                         printk(KERN_ERR PFX "No usable DMA configuration, "
11408                                "aborting.\n");
11409                         goto err_out_iounmap;
11410                 }
11411         }
11412
11413         tg3_init_bufmgr_config(tp);
11414
11415 #if TG3_TSO_SUPPORT != 0
11416         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11417                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11418         }
11419         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11420             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11421             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11422             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11423                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11424         } else {
11425                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11426         }
11427
11428         /* TSO is on by default on chips that support hardware TSO.
11429          * Firmware TSO on older chips gives lower performance, so it
11430          * is off by default, but can be enabled using ethtool.
11431          */
11432         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
11433                 dev->features |= NETIF_F_TSO;
11434
11435 #endif
11436
11437         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11438             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11439             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11440                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11441                 tp->rx_pending = 63;
11442         }
11443
11444         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11445             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11446                 tp->pdev_peer = tg3_find_peer(tp);
11447
11448         err = tg3_get_device_address(tp);
11449         if (err) {
11450                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11451                        "aborting.\n");
11452                 goto err_out_iounmap;
11453         }
11454
11455         /*
11456          * Reset chip in case UNDI or EFI driver did not shutdown
11457          * DMA self test will enable WDMAC and we'll see (spurious)
11458          * pending DMA on the PCI bus at that point.
11459          */
11460         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11461             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11462                 pci_save_state(tp->pdev);
11463                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11464                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11465         }
11466
11467         err = tg3_test_dma(tp);
11468         if (err) {
11469                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11470                 goto err_out_iounmap;
11471         }
11472
11473         /* Tigon3 can do ipv4 only... and some chips have buggy
11474          * checksumming.
11475          */
11476         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11477                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11478                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11479                         dev->features |= NETIF_F_HW_CSUM;
11480                 else
11481                         dev->features |= NETIF_F_IP_CSUM;
11482                 dev->features |= NETIF_F_SG;
11483                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11484         } else
11485                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11486
11487         /* flow control autonegotiation is default behavior */
11488         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11489
11490         tg3_init_coal(tp);
11491
11492         /* Now that we have fully setup the chip, save away a snapshot
11493          * of the PCI config space.  We need to restore this after
11494          * GRC_MISC_CFG core clock resets and some resume events.
11495          */
11496         pci_save_state(tp->pdev);
11497
11498         err = register_netdev(dev);
11499         if (err) {
11500                 printk(KERN_ERR PFX "Cannot register net device, "
11501                        "aborting.\n");
11502                 goto err_out_iounmap;
11503         }
11504
11505         pci_set_drvdata(pdev, dev);
11506
11507         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11508                dev->name,
11509                tp->board_part_number,
11510                tp->pci_chip_rev_id,
11511                tg3_phy_string(tp),
11512                tg3_bus_string(tp, str),
11513                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11514
11515         for (i = 0; i < 6; i++)
11516                 printk("%2.2x%c", dev->dev_addr[i],
11517                        i == 5 ? '\n' : ':');
11518
11519         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11520                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11521                "TSOcap[%d] \n",
11522                dev->name,
11523                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11524                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11525                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11526                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11527                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11528                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11529                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11530         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11531                dev->name, tp->dma_rwctrl,
11532                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11533                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11534
11535         netif_carrier_off(tp->dev);
11536
11537         return 0;
11538
11539 err_out_iounmap:
11540         if (tp->regs) {
11541                 iounmap(tp->regs);
11542                 tp->regs = NULL;
11543         }
11544
11545 err_out_free_dev:
11546         free_netdev(dev);
11547
11548 err_out_free_res:
11549         pci_release_regions(pdev);
11550
11551 err_out_disable_pdev:
11552         pci_disable_device(pdev);
11553         pci_set_drvdata(pdev, NULL);
11554         return err;
11555 }
11556
11557 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11558 {
11559         struct net_device *dev = pci_get_drvdata(pdev);
11560
11561         if (dev) {
11562                 struct tg3 *tp = netdev_priv(dev);
11563
11564                 flush_scheduled_work();
11565                 unregister_netdev(dev);
11566                 if (tp->regs) {
11567                         iounmap(tp->regs);
11568                         tp->regs = NULL;
11569                 }
11570                 free_netdev(dev);
11571                 pci_release_regions(pdev);
11572                 pci_disable_device(pdev);
11573                 pci_set_drvdata(pdev, NULL);
11574         }
11575 }
11576
11577 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11578 {
11579         struct net_device *dev = pci_get_drvdata(pdev);
11580         struct tg3 *tp = netdev_priv(dev);
11581         int err;
11582
11583         if (!netif_running(dev))
11584                 return 0;
11585
11586         flush_scheduled_work();
11587         tg3_netif_stop(tp);
11588
11589         del_timer_sync(&tp->timer);
11590
11591         tg3_full_lock(tp, 1);
11592         tg3_disable_ints(tp);
11593         tg3_full_unlock(tp);
11594
11595         netif_device_detach(dev);
11596
11597         tg3_full_lock(tp, 0);
11598         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11599         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11600         tg3_full_unlock(tp);
11601
11602         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11603         if (err) {
11604                 tg3_full_lock(tp, 0);
11605
11606                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11607                 tg3_init_hw(tp, 1);
11608
11609                 tp->timer.expires = jiffies + tp->timer_offset;
11610                 add_timer(&tp->timer);
11611
11612                 netif_device_attach(dev);
11613                 tg3_netif_start(tp);
11614
11615                 tg3_full_unlock(tp);
11616         }
11617
11618         return err;
11619 }
11620
11621 static int tg3_resume(struct pci_dev *pdev)
11622 {
11623         struct net_device *dev = pci_get_drvdata(pdev);
11624         struct tg3 *tp = netdev_priv(dev);
11625         int err;
11626
11627         if (!netif_running(dev))
11628                 return 0;
11629
11630         pci_restore_state(tp->pdev);
11631
11632         err = tg3_set_power_state(tp, PCI_D0);
11633         if (err)
11634                 return err;
11635
11636         netif_device_attach(dev);
11637
11638         tg3_full_lock(tp, 0);
11639
11640         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11641         tg3_init_hw(tp, 1);
11642
11643         tp->timer.expires = jiffies + tp->timer_offset;
11644         add_timer(&tp->timer);
11645
11646         tg3_netif_start(tp);
11647
11648         tg3_full_unlock(tp);
11649
11650         return 0;
11651 }
11652
11653 static struct pci_driver tg3_driver = {
11654         .name           = DRV_MODULE_NAME,
11655         .id_table       = tg3_pci_tbl,
11656         .probe          = tg3_init_one,
11657         .remove         = __devexit_p(tg3_remove_one),
11658         .suspend        = tg3_suspend,
11659         .resume         = tg3_resume
11660 };
11661
11662 static int __init tg3_init(void)
11663 {
11664         return pci_module_init(&tg3_driver);
11665 }
11666
11667 static void __exit tg3_cleanup(void)
11668 {
11669         pci_unregister_driver(&tg3_driver);
11670 }
11671
11672 module_init(tg3_init);
11673 module_exit(tg3_cleanup);