drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.99"
  72 #define DRV_MODULE_RELDATE      "April 20, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 #define TG3_RAW_IP_ALIGN 2
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 #define FIRMWARE_TG3            "tigon/tg3.bin"
 142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 144
 145 static char version[] __devinitdata =
 146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 147
 148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 150 MODULE_LICENSE("GPL");
 151 MODULE_VERSION(DRV_MODULE_VERSION);
 152 MODULE_FIRMWARE(FIRMWARE_TG3);
 153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 155
 156
 157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 158 module_param(tg3_debug, int, 0);
 159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 160
 161 static struct pci_device_id tg3_pci_tbl[] = {
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 234         {}
 235 };
 236
 237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 238
 239 static const struct {
 240         const char string[ETH_GSTRING_LEN];
 241 } ethtool_stats_keys[TG3_NUM_STATS] = {
 242         { "rx_octets" },
 243         { "rx_fragments" },
 244         { "rx_ucast_packets" },
 245         { "rx_mcast_packets" },
 246         { "rx_bcast_packets" },
 247         { "rx_fcs_errors" },
 248         { "rx_align_errors" },
 249         { "rx_xon_pause_rcvd" },
 250         { "rx_xoff_pause_rcvd" },
 251         { "rx_mac_ctrl_rcvd" },
 252         { "rx_xoff_entered" },
 253         { "rx_frame_too_long_errors" },
 254         { "rx_jabbers" },
 255         { "rx_undersize_packets" },
 256         { "rx_in_length_errors" },
 257         { "rx_out_length_errors" },
 258         { "rx_64_or_less_octet_packets" },
 259         { "rx_65_to_127_octet_packets" },
 260         { "rx_128_to_255_octet_packets" },
 261         { "rx_256_to_511_octet_packets" },
 262         { "rx_512_to_1023_octet_packets" },
 263         { "rx_1024_to_1522_octet_packets" },
 264         { "rx_1523_to_2047_octet_packets" },
 265         { "rx_2048_to_4095_octet_packets" },
 266         { "rx_4096_to_8191_octet_packets" },
 267         { "rx_8192_to_9022_octet_packets" },
 268
 269         { "tx_octets" },
 270         { "tx_collisions" },
 271
 272         { "tx_xon_sent" },
 273         { "tx_xoff_sent" },
 274         { "tx_flow_control" },
 275         { "tx_mac_errors" },
 276         { "tx_single_collisions" },
 277         { "tx_mult_collisions" },
 278         { "tx_deferred" },
 279         { "tx_excessive_collisions" },
 280         { "tx_late_collisions" },
 281         { "tx_collide_2times" },
 282         { "tx_collide_3times" },
 283         { "tx_collide_4times" },
 284         { "tx_collide_5times" },
 285         { "tx_collide_6times" },
 286         { "tx_collide_7times" },
 287         { "tx_collide_8times" },
 288         { "tx_collide_9times" },
 289         { "tx_collide_10times" },
 290         { "tx_collide_11times" },
 291         { "tx_collide_12times" },
 292         { "tx_collide_13times" },
 293         { "tx_collide_14times" },
 294         { "tx_collide_15times" },
 295         { "tx_ucast_packets" },
 296         { "tx_mcast_packets" },
 297         { "tx_bcast_packets" },
 298         { "tx_carrier_sense_errors" },
 299         { "tx_discards" },
 300         { "tx_errors" },
 301
 302         { "dma_writeq_full" },
 303         { "dma_write_prioq_full" },
 304         { "rxbds_empty" },
 305         { "rx_discards" },
 306         { "rx_errors" },
 307         { "rx_threshold_hit" },
 308
 309         { "dma_readq_full" },
 310         { "dma_read_prioq_full" },
 311         { "tx_comp_queue_full" },
 312
 313         { "ring_set_send_prod_index" },
 314         { "ring_status_update" },
 315         { "nic_irqs" },
 316         { "nic_avoided_irqs" },
 317         { "nic_tx_threshold_hit" }
 318 };
 319
 320 static const struct {
 321         const char string[ETH_GSTRING_LEN];
 322 } ethtool_test_keys[TG3_NUM_TEST] = {
 323         { "nvram test     (online) " },
 324         { "link test      (online) " },
 325         { "register test  (offline)" },
 326         { "memory test    (offline)" },
 327         { "loopback test  (offline)" },
 328         { "interrupt test (offline)" },
 329 };
 330
 331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 332 {
 333         writel(val, tp->regs + off);
 334 }
 335
 336 static u32 tg3_read32(struct tg3 *tp, u32 off)
 337 {
 338         return (readl(tp->regs + off));
 339 }
 340
 341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->aperegs + off);
 344 }
 345
 346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->aperegs + off));
 349 }
 350
 351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&tp->indirect_lock, flags);
 356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 359 }
 360
 361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364         readl(tp->regs + off);
 365 }
 366
 367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 368 {
 369         unsigned long flags;
 370         u32 val;
 371
 372         spin_lock_irqsave(&tp->indirect_lock, flags);
 373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 376         return val;
 377 }
 378
 379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         unsigned long flags;
 382
 383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 385                                        TG3_64BIT_REG_LOW, val);
 386                 return;
 387         }
 388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 390                                        TG3_64BIT_REG_LOW, val);
 391                 return;
 392         }
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398
 399         /* In indirect mode when disabling interrupts, we also need
 400          * to clear the interrupt bit in the GRC local ctrl register.
 401          */
 402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 403             (val == 0x1)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 406         }
 407 }
 408
 409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 /* usec_wait specifies the wait time in usec when writing to certain registers
 422  * where it is unsafe to read back the register without some delay.
 423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 425  */
 426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 427 {
 428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 /* Non-posted methods */
 431                 tp->write32(tp, off, val);
 432         else {
 433                 /* Posted method */
 434                 tg3_write32(tp, off, val);
 435                 if (usec_wait)
 436                         udelay(usec_wait);
 437                 tp->read32(tp, off);
 438         }
 439         /* Wait again after the read for the posted method to guarantee that
 440          * the wait time is met.
 441          */
 442         if (usec_wait)
 443                 udelay(usec_wait);
 444 }
 445
 446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 447 {
 448         tp->write32_mbox(tp, off, val);
 449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 451                 tp->read32_mbox(tp, off);
 452 }
 453
 454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         void __iomem *mbox = tp->regs + off;
 457         writel(val, mbox);
 458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 459                 writel(val, mbox);
 460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 461                 readl(mbox);
 462 }
 463
 464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 465 {
 466         return (readl(tp->regs + off + GRCMBOX_BASE));
 467 }
 468
 469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 470 {
 471         writel(val, tp->regs + off + GRCMBOX_BASE);
 472 }
 473
 474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 479
 480 #define tw32(reg,val)           tp->write32(tp, reg, val)
 481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 483 #define tr32(reg)               tp->read32(tp, reg)
 484
 485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 486 {
 487         unsigned long flags;
 488
 489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 491                 return;
 492
 493         spin_lock_irqsave(&tp->indirect_lock, flags);
 494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 497
 498                 /* Always leave this as zero. */
 499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 500         } else {
 501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         }
 507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 508 }
 509
 510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 511 {
 512         unsigned long flags;
 513
 514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 516                 *val = 0;
 517                 return;
 518         }
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_ape_lock_init(struct tg3 *tp)
 538 {
 539         int i;
 540
 541         /* Make sure the driver hasn't any stale locks. */
 542         for (i = 0; i < 8; i++)
 543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 544                                 APE_LOCK_GRANT_DRIVER);
 545 }
 546
 547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 548 {
 549         int i, off;
 550         int ret = 0;
 551         u32 status;
 552
 553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 554                 return 0;
 555
 556         switch (locknum) {
 557                 case TG3_APE_LOCK_GRC:
 558                 case TG3_APE_LOCK_MEM:
 559                         break;
 560                 default:
 561                         return -EINVAL;
 562         }
 563
 564         off = 4 * locknum;
 565
 566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 567
 568         /* Wait for up to 1 millisecond to acquire lock. */
 569         for (i = 0; i < 100; i++) {
 570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 571                 if (status == APE_LOCK_GRANT_DRIVER)
 572                         break;
 573                 udelay(10);
 574         }
 575
 576         if (status != APE_LOCK_GRANT_DRIVER) {
 577                 /* Revoke the lock request. */
 578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 579                                 APE_LOCK_GRANT_DRIVER);
 580
 581                 ret = -EBUSY;
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 588 {
 589         int off;
 590
 591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 592                 return;
 593
 594         switch (locknum) {
 595                 case TG3_APE_LOCK_GRC:
 596                 case TG3_APE_LOCK_MEM:
 597                         break;
 598                 default:
 599                         return;
 600         }
 601
 602         off = 4 * locknum;
 603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 604 }
 605
 606 static void tg3_disable_ints(struct tg3 *tp)
 607 {
 608         tw32(TG3PCI_MISC_HOST_CTRL,
 609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 611 }
 612
 613 static inline void tg3_cond_int(struct tg3 *tp)
 614 {
 615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 616             (tp->hw_status->status & SD_STATUS_UPDATED))
 617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 618         else
 619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 621 }
 622
 623 static void tg3_enable_ints(struct tg3 *tp)
 624 {
 625         tp->irq_sync = 0;
 626         wmb();
 627
 628         tw32(TG3PCI_MISC_HOST_CTRL,
 629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 631                        (tp->last_tag << 24));
 632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 634                                (tp->last_tag << 24));
 635         tg3_cond_int(tp);
 636 }
 637
 638 static inline unsigned int tg3_has_work(struct tg3 *tp)
 639 {
 640         struct tg3_hw_status *sblk = tp->hw_status;
 641         unsigned int work_exists = 0;
 642
 643         /* check for phy events */
 644         if (!(tp->tg3_flags &
 645               (TG3_FLAG_USE_LINKCHG_REG |
 646                TG3_FLAG_POLL_SERDES))) {
 647                 if (sblk->status & SD_STATUS_LINK_CHG)
 648                         work_exists = 1;
 649         }
 650         /* check for RX/TX work to do */
 651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 653                 work_exists = 1;
 654
 655         return work_exists;
 656 }
 657
 658 /* tg3_restart_ints
 659  *  similar to tg3_enable_ints, but it accurately determines whether there
 660  *  is new work pending and can return without flushing the PIO write
 661  *  which reenables interrupts
 662  */
 663 static void tg3_restart_ints(struct tg3 *tp)
 664 {
 665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 666                      tp->last_tag << 24);
 667         mmiowb();
 668
 669         /* When doing tagged status, this work check is unnecessary.
 670          * The last_tag we write above tells the chip which piece of
 671          * work we've completed.
 672          */
 673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 674             tg3_has_work(tp))
 675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 677 }
 678
 679 static inline void tg3_netif_stop(struct tg3 *tp)
 680 {
 681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 682         napi_disable(&tp->napi);
 683         netif_tx_disable(tp->dev);
 684 }
 685
 686 static inline void tg3_netif_start(struct tg3 *tp)
 687 {
 688         netif_wake_queue(tp->dev);
 689         /* NOTE: unconditional netif_wake_queue is only appropriate
 690          * so long as all callers are assured to have free tx slots
 691          * (such as after tg3_init_hw)
 692          */
 693         napi_enable(&tp->napi);
 694         tp->hw_status->status |= SD_STATUS_UPDATED;
 695         tg3_enable_ints(tp);
 696 }
 697
 698 static void tg3_switch_clocks(struct tg3 *tp)
 699 {
 700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 701         u32 orig_clock_ctrl;
 702
 703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 705                 return;
 706
 707         orig_clock_ctrl = clock_ctrl;
 708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 709                        CLOCK_CTRL_CLKRUN_OENABLE |
 710                        0x1f);
 711         tp->pci_clock_ctrl = clock_ctrl;
 712
 713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 717                 }
 718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 720                             clock_ctrl |
 721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 722                             40);
 723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 725                             40);
 726         }
 727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 728 }
 729
 730 #define PHY_BUSY_LOOPS  5000
 731
 732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 733 {
 734         u32 frame_val;
 735         unsigned int loops;
 736         int ret;
 737
 738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 739                 tw32_f(MAC_MI_MODE,
 740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 741                 udelay(80);
 742         }
 743
 744         *val = 0x0;
 745
 746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 747                       MI_COM_PHY_ADDR_MASK);
 748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 749                       MI_COM_REG_ADDR_MASK);
 750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 751
 752         tw32_f(MAC_MI_COM, frame_val);
 753
 754         loops = PHY_BUSY_LOOPS;
 755         while (loops != 0) {
 756                 udelay(10);
 757                 frame_val = tr32(MAC_MI_COM);
 758
 759                 if ((frame_val & MI_COM_BUSY) == 0) {
 760                         udelay(5);
 761                         frame_val = tr32(MAC_MI_COM);
 762                         break;
 763                 }
 764                 loops -= 1;
 765         }
 766
 767         ret = -EBUSY;
 768         if (loops != 0) {
 769                 *val = frame_val & MI_COM_DATA_MASK;
 770                 ret = 0;
 771         }
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 775                 udelay(80);
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 782 {
 783         u32 frame_val;
 784         unsigned int loops;
 785         int ret;
 786
 787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 789                 return 0;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 798                       MI_COM_PHY_ADDR_MASK);
 799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 800                       MI_COM_REG_ADDR_MASK);
 801         frame_val |= (val & MI_COM_DATA_MASK);
 802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810                 if ((frame_val & MI_COM_BUSY) == 0) {
 811                         udelay(5);
 812                         frame_val = tr32(MAC_MI_COM);
 813                         break;
 814                 }
 815                 loops -= 1;
 816         }
 817
 818         ret = -EBUSY;
 819         if (loops != 0)
 820                 ret = 0;
 821
 822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 824                 udelay(80);
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int tg3_bmcr_reset(struct tg3 *tp)
 831 {
 832         u32 phy_control;
 833         int limit, err;
 834
 835         /* OK, reset it, and poll the BMCR_RESET bit until it
 836          * clears or we time out.
 837          */
 838         phy_control = BMCR_RESET;
 839         err = tg3_writephy(tp, MII_BMCR, phy_control);
 840         if (err != 0)
 841                 return -EBUSY;
 842
 843         limit = 5000;
 844         while (limit--) {
 845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 846                 if (err != 0)
 847                         return -EBUSY;
 848
 849                 if ((phy_control & BMCR_RESET) == 0) {
 850                         udelay(40);
 851                         break;
 852                 }
 853                 udelay(10);
 854         }
 855         if (limit < 0)
 856                 return -EBUSY;
 857
 858         return 0;
 859 }
 860
 861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 862 {
 863         struct tg3 *tp = bp->priv;
 864         u32 val;
 865
 866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 867                 return -EAGAIN;
 868
 869         if (tg3_readphy(tp, reg, &val))
 870                 return -EIO;
 871
 872         return val;
 873 }
 874
 875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 876 {
 877         struct tg3 *tp = bp->priv;
 878
 879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 880                 return -EAGAIN;
 881
 882         if (tg3_writephy(tp, reg, val))
 883                 return -EIO;
 884
 885         return 0;
 886 }
 887
 888 static int tg3_mdio_reset(struct mii_bus *bp)
 889 {
 890         return 0;
 891 }
 892
 893 static void tg3_mdio_config_5785(struct tg3 *tp)
 894 {
 895         u32 val;
 896         struct phy_device *phydev;
 897
 898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 900         case TG3_PHY_ID_BCM50610:
 901                 val = MAC_PHYCFG2_50610_LED_MODES;
 902                 break;
 903         case TG3_PHY_ID_BCMAC131:
 904                 val = MAC_PHYCFG2_AC131_LED_MODES;
 905                 break;
 906         case TG3_PHY_ID_RTL8211C:
 907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 908                 break;
 909         case TG3_PHY_ID_RTL8201E:
 910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 911                 break;
 912         default:
 913                 return;
 914         }
 915
 916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 917                 tw32(MAC_PHYCFG2, val);
 918
 919                 val = tr32(MAC_PHYCFG1);
 920                 val &= ~MAC_PHYCFG1_RGMII_INT;
 921                 tw32(MAC_PHYCFG1, val);
 922
 923                 return;
 924         }
 925
 926         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 927                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 928                        MAC_PHYCFG2_FMODE_MASK_MASK |
 929                        MAC_PHYCFG2_GMODE_MASK_MASK |
 930                        MAC_PHYCFG2_ACT_MASK_MASK   |
 931                        MAC_PHYCFG2_QUAL_MASK_MASK |
 932                        MAC_PHYCFG2_INBAND_ENABLE;
 933
 934         tw32(MAC_PHYCFG2, val);
 935
 936         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 937                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 938         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 939                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 940                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 941                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 942                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 943         }
 944         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 945
 946         val = tr32(MAC_EXT_RGMII_MODE);
 947         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 948                  MAC_RGMII_MODE_RX_QUALITY |
 949                  MAC_RGMII_MODE_RX_ACTIVITY |
 950                  MAC_RGMII_MODE_RX_ENG_DET |
 951                  MAC_RGMII_MODE_TX_ENABLE |
 952                  MAC_RGMII_MODE_TX_LOWPWR |
 953                  MAC_RGMII_MODE_TX_RESET);
 954         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 956                         val |= MAC_RGMII_MODE_RX_INT_B |
 957                                MAC_RGMII_MODE_RX_QUALITY |
 958                                MAC_RGMII_MODE_RX_ACTIVITY |
 959                                MAC_RGMII_MODE_RX_ENG_DET;
 960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 961                         val |= MAC_RGMII_MODE_TX_ENABLE |
 962                                MAC_RGMII_MODE_TX_LOWPWR |
 963                                MAC_RGMII_MODE_TX_RESET;
 964         }
 965         tw32(MAC_EXT_RGMII_MODE, val);
 966 }
 967
 968 static void tg3_mdio_start(struct tg3 *tp)
 969 {
 970         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 971                 mutex_lock(&tp->mdio_bus->mdio_lock);
 972                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 973                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 974         }
 975
 976         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 977         tw32_f(MAC_MI_MODE, tp->mi_mode);
 978         udelay(80);
 979
 980         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 982                 tg3_mdio_config_5785(tp);
 983 }
 984
 985 static void tg3_mdio_stop(struct tg3 *tp)
 986 {
 987         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 988                 mutex_lock(&tp->mdio_bus->mdio_lock);
 989                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 990                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 991         }
 992 }
 993
 994 static int tg3_mdio_init(struct tg3 *tp)
 995 {
 996         int i;
 997         u32 reg;
 998         struct phy_device *phydev;
 999
1000         tg3_mdio_start(tp);
1001
1002         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004                 return 0;
1005
1006         tp->mdio_bus = mdiobus_alloc();
1007         if (tp->mdio_bus == NULL)
1008                 return -ENOMEM;
1009
1010         tp->mdio_bus->name     = "tg3 mdio bus";
1011         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013         tp->mdio_bus->priv     = tp;
1014         tp->mdio_bus->parent   = &tp->pdev->dev;
1015         tp->mdio_bus->read     = &tg3_mdio_read;
1016         tp->mdio_bus->write    = &tg3_mdio_write;
1017         tp->mdio_bus->reset    = &tg3_mdio_reset;
1018         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1020
1021         for (i = 0; i < PHY_MAX_ADDR; i++)
1022                 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024         /* The bus registration will look for all the PHYs on the mdio bus.
1025          * Unfortunately, it does not ensure the PHY is powered up before
1026          * accessing the PHY ID registers.  A chip reset is the
1027          * quickest way to bring the device back to an operational state..
1028          */
1029         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030                 tg3_bmcr_reset(tp);
1031
1032         i = mdiobus_register(tp->mdio_bus);
1033         if (i) {
1034                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035                         tp->dev->name, i);
1036                 mdiobus_free(tp->mdio_bus);
1037                 return i;
1038         }
1039
1040         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042         if (!phydev || !phydev->drv) {
1043                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044                 mdiobus_unregister(tp->mdio_bus);
1045                 mdiobus_free(tp->mdio_bus);
1046                 return -ENODEV;
1047         }
1048
1049         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050         case TG3_PHY_ID_BCM57780:
1051                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052                 break;
1053         case TG3_PHY_ID_BCM50610:
1054                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060                 /* fallthru */
1061         case TG3_PHY_ID_RTL8211C:
1062                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063                 break;
1064         case TG3_PHY_ID_RTL8201E:
1065         case TG3_PHY_ID_BCMAC131:
1066                 phydev->interface = PHY_INTERFACE_MODE_MII;
1067                 break;
1068         }
1069
1070         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073                 tg3_mdio_config_5785(tp);
1074
1075         return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082                 mdiobus_unregister(tp->mdio_bus);
1083                 mdiobus_free(tp->mdio_bus);
1084                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085         }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091         u32 val;
1092
1093         val = tr32(GRC_RX_CPU_EVENT);
1094         val |= GRC_RX_CPU_DRIVER_EVENT;
1095         tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097         tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105         int i;
1106         unsigned int delay_cnt;
1107         long time_remain;
1108
1109         /* If enough time has passed, no wait is necessary. */
1110         time_remain = (long)(tp->last_event_jiffies + 1 +
1111                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112                       (long)jiffies;
1113         if (time_remain < 0)
1114                 return;
1115
1116         /* Check if we can shorten the wait time. */
1117         delay_cnt = jiffies_to_usecs(time_remain);
1118         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120         delay_cnt = (delay_cnt >> 3) + 1;
1121
1122         for (i = 0; i < delay_cnt; i++) {
1123                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124                         break;
1125                 udelay(8);
1126         }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132         u32 reg;
1133         u32 val;
1134
1135         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1137                 return;
1138
1139         tg3_wait_for_event_ack(tp);
1140
1141         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_BMCR, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_BMSR, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_LPA, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159         val = 0;
1160         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162                         val = reg << 16;
1163                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164                         val |= (reg & 0xffff);
1165         }
1166         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169                 val = reg << 16;
1170         else
1171                 val = 0;
1172         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174         tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179         if (!netif_carrier_ok(tp->dev)) {
1180                 if (netif_msg_link(tp))
1181                         printk(KERN_INFO PFX "%s: Link is down.\n",
1182                                tp->dev->name);
1183                 tg3_ump_link_report(tp);
1184         } else if (netif_msg_link(tp)) {
1185                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186                        tp->dev->name,
1187                        (tp->link_config.active_speed == SPEED_1000 ?
1188                         1000 :
1189                         (tp->link_config.active_speed == SPEED_100 ?
1190                          100 : 10)),
1191                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1192                         "full" : "half"));
1193
1194                 printk(KERN_INFO PFX
1195                        "%s: Flow control is %s for TX and %s for RX.\n",
1196                        tp->dev->name,
1197                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198                        "on" : "off",
1199                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200                        "on" : "off");
1201                 tg3_ump_link_report(tp);
1202         }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207         u16 miireg;
1208
1209         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210                 miireg = ADVERTISE_PAUSE_CAP;
1211         else if (flow_ctrl & FLOW_CTRL_TX)
1212                 miireg = ADVERTISE_PAUSE_ASYM;
1213         else if (flow_ctrl & FLOW_CTRL_RX)
1214                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215         else
1216                 miireg = 0;
1217
1218         return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223         u16 miireg;
1224
1225         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226                 miireg = ADVERTISE_1000XPAUSE;
1227         else if (flow_ctrl & FLOW_CTRL_TX)
1228                 miireg = ADVERTISE_1000XPSE_ASYM;
1229         else if (flow_ctrl & FLOW_CTRL_RX)
1230                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231         else
1232                 miireg = 0;
1233
1234         return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239         u8 cap = 0;
1240
1241         if (lcladv & ADVERTISE_1000XPAUSE) {
1242                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243                         if (rmtadv & LPA_1000XPAUSE)
1244                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246                                 cap = FLOW_CTRL_RX;
1247                 } else {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                 }
1251         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253                         cap = FLOW_CTRL_TX;
1254         }
1255
1256         return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261         u8 autoneg;
1262         u8 flowctrl = 0;
1263         u32 old_rx_mode = tp->rx_mode;
1264         u32 old_tx_mode = tp->tx_mode;
1265
1266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268         else
1269                 autoneg = tp->link_config.autoneg;
1270
1271         if (autoneg == AUTONEG_ENABLE &&
1272             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275                 else
1276                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277         } else
1278                 flowctrl = tp->link_config.flowctrl;
1279
1280         tp->link_config.active_flowctrl = flowctrl;
1281
1282         if (flowctrl & FLOW_CTRL_RX)
1283                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284         else
1285                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287         if (old_rx_mode != tp->rx_mode)
1288                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290         if (flowctrl & FLOW_CTRL_TX)
1291                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292         else
1293                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295         if (old_tx_mode != tp->tx_mode)
1296                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301         u8 oldflowctrl, linkmesg = 0;
1302         u32 mac_mode, lcl_adv, rmt_adv;
1303         struct tg3 *tp = netdev_priv(dev);
1304         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306         spin_lock(&tp->lock);
1307
1308         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309                                     MAC_MODE_HALF_DUPLEX);
1310
1311         oldflowctrl = tp->link_config.active_flowctrl;
1312
1313         if (phydev->link) {
1314                 lcl_adv = 0;
1315                 rmt_adv = 0;
1316
1317                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1319                 else
1320                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322                 if (phydev->duplex == DUPLEX_HALF)
1323                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1324                 else {
1325                         lcl_adv = tg3_advert_flowctrl_1000T(
1326                                   tp->link_config.flowctrl);
1327
1328                         if (phydev->pause)
1329                                 rmt_adv = LPA_PAUSE_CAP;
1330                         if (phydev->asym_pause)
1331                                 rmt_adv |= LPA_PAUSE_ASYM;
1332                 }
1333
1334                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335         } else
1336                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338         if (mac_mode != tp->mac_mode) {
1339                 tp->mac_mode = mac_mode;
1340                 tw32_f(MAC_MODE, tp->mac_mode);
1341                 udelay(40);
1342         }
1343
1344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345                 if (phydev->speed == SPEED_10)
1346                         tw32(MAC_MI_STAT,
1347                              MAC_MI_STAT_10MBPS_MODE |
1348                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349                 else
1350                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351         }
1352
1353         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354                 tw32(MAC_TX_LENGTHS,
1355                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356                       (6 << TX_LENGTHS_IPG_SHIFT) |
1357                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358         else
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366             phydev->speed != tp->link_config.active_speed ||
1367             phydev->duplex != tp->link_config.active_duplex ||
1368             oldflowctrl != tp->link_config.active_flowctrl)
1369             linkmesg = 1;
1370
1371         tp->link_config.active_speed = phydev->speed;
1372         tp->link_config.active_duplex = phydev->duplex;
1373
1374         spin_unlock(&tp->lock);
1375
1376         if (linkmesg)
1377                 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382         struct phy_device *phydev;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385                 return 0;
1386
1387         /* Bring the PHY back to a known state. */
1388         tg3_bmcr_reset(tp);
1389
1390         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392         /* Attach the MAC to the PHY. */
1393         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394                              phydev->dev_flags, phydev->interface);
1395         if (IS_ERR(phydev)) {
1396                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397                 return PTR_ERR(phydev);
1398         }
1399
1400         /* Mask with MAC supported features. */
1401         switch (phydev->interface) {
1402         case PHY_INTERFACE_MODE_GMII:
1403         case PHY_INTERFACE_MODE_RGMII:
1404                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405                         phydev->supported &= (PHY_GBIT_FEATURES |
1406                                               SUPPORTED_Pause |
1407                                               SUPPORTED_Asym_Pause);
1408                         break;
1409                 }
1410                 /* fallthru */
1411         case PHY_INTERFACE_MODE_MII:
1412                 phydev->supported &= (PHY_BASIC_FEATURES |
1413                                       SUPPORTED_Pause |
1414                                       SUPPORTED_Asym_Pause);
1415                 break;
1416         default:
1417                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418                 return -EINVAL;
1419         }
1420
1421         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423         phydev->advertising = phydev->supported;
1424
1425         return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430         struct phy_device *phydev;
1431
1432         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433                 return;
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         if (tp->link_config.phy_is_low_power) {
1438                 tp->link_config.phy_is_low_power = 0;
1439                 phydev->speed = tp->link_config.orig_speed;
1440                 phydev->duplex = tp->link_config.orig_duplex;
1441                 phydev->autoneg = tp->link_config.orig_autoneg;
1442                 phydev->advertising = tp->link_config.orig_advertising;
1443         }
1444
1445         phy_start(phydev);
1446
1447         phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453                 return;
1454
1455         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463         }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474         u32 reg;
1475
1476         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478                 return;
1479
1480         reg = MII_TG3_MISC_SHDW_WREN |
1481               MII_TG3_MISC_SHDW_SCR5_SEL |
1482               MII_TG3_MISC_SHDW_SCR5_LPED |
1483               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484               MII_TG3_MISC_SHDW_SCR5_SDTL |
1485               MII_TG3_MISC_SHDW_SCR5_C125OE;
1486         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492         reg = MII_TG3_MISC_SHDW_WREN |
1493               MII_TG3_MISC_SHDW_APD_SEL |
1494               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495         if (enable)
1496                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503         u32 phy;
1504
1505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507                 return;
1508
1509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510                 u32 ephy;
1511
1512                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1515                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516                                 if (enable)
1517                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518                                 else
1519                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521                         }
1522                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523                 }
1524         } else {
1525                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1527                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529                         if (enable)
1530                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531                         else
1532                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1534                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535                 }
1536         }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541         u32 val;
1542
1543         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544                 return;
1545
1546         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549                              (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554         u32 otp, phy;
1555
1556         if (!tp->phy_otp)
1557                 return;
1558
1559         otp = tp->phy_otp;
1560
1561         /* Enable SM_DSP clock and tx 6dB coding. */
1562         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564               MII_TG3_AUXCTL_ACTL_TX_6DB;
1565         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589         /* Turn off SM_DSP clock. */
1590         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591               MII_TG3_AUXCTL_ACTL_TX_6DB;
1592         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597         int limit = 100;
1598
1599         while (limit--) {
1600                 u32 tmp32;
1601
1602                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603                         if ((tmp32 & 0x1000) == 0)
1604                                 break;
1605                 }
1606         }
1607         if (limit < 0)
1608                 return -EBUSY;
1609
1610         return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615         static const u32 test_pat[4][6] = {
1616         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620         };
1621         int chan;
1622
1623         for (chan = 0; chan < 4; chan++) {
1624                 int i;
1625
1626                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627                              (chan * 0x2000) | 0x0200);
1628                 tg3_writephy(tp, 0x16, 0x0002);
1629
1630                 for (i = 0; i < 6; i++)
1631                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632                                      test_pat[chan][i]);
1633
1634                 tg3_writephy(tp, 0x16, 0x0202);
1635                 if (tg3_wait_macro_done(tp)) {
1636                         *resetp = 1;
1637                         return -EBUSY;
1638                 }
1639
1640                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641                              (chan * 0x2000) | 0x0200);
1642                 tg3_writephy(tp, 0x16, 0x0082);
1643                 if (tg3_wait_macro_done(tp)) {
1644                         *resetp = 1;
1645                         return -EBUSY;
1646                 }
1647
1648                 tg3_writephy(tp, 0x16, 0x0802);
1649                 if (tg3_wait_macro_done(tp)) {
1650                         *resetp = 1;
1651                         return -EBUSY;
1652                 }
1653
1654                 for (i = 0; i < 6; i += 2) {
1655                         u32 low, high;
1656
1657                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659                             tg3_wait_macro_done(tp)) {
1660                                 *resetp = 1;
1661                                 return -EBUSY;
1662                         }
1663                         low &= 0x7fff;
1664                         high &= 0x000f;
1665                         if (low != test_pat[chan][i] ||
1666                             high != test_pat[chan][i+1]) {
1667                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671                                 return -EBUSY;
1672                         }
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681         int chan;
1682
1683         for (chan = 0; chan < 4; chan++) {
1684                 int i;
1685
1686                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687                              (chan * 0x2000) | 0x0200);
1688                 tg3_writephy(tp, 0x16, 0x0002);
1689                 for (i = 0; i < 6; i++)
1690                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691                 tg3_writephy(tp, 0x16, 0x0202);
1692                 if (tg3_wait_macro_done(tp))
1693                         return -EBUSY;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701         u32 reg32, phy9_orig;
1702         int retries, do_phy_reset, err;
1703
1704         retries = 10;
1705         do_phy_reset = 1;
1706         do {
1707                 if (do_phy_reset) {
1708                         err = tg3_bmcr_reset(tp);
1709                         if (err)
1710                                 return err;
1711                         do_phy_reset = 0;
1712                 }
1713
1714                 /* Disable transmitter and interrupt.  */
1715                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716                         continue;
1717
1718                 reg32 |= 0x3000;
1719                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721                 /* Set full-duplex, 1000 mbps.  */
1722                 tg3_writephy(tp, MII_BMCR,
1723                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725                 /* Set to master mode.  */
1726                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727                         continue;
1728
1729                 tg3_writephy(tp, MII_TG3_CTRL,
1730                              (MII_TG3_CTRL_AS_MASTER |
1731                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733                 /* Enable SM_DSP_CLOCK and 6dB.  */
1734                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736                 /* Block the PHY control access.  */
1737                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741                 if (!err)
1742                         break;
1743         } while (--retries);
1744
1745         err = tg3_phy_reset_chanpat(tp);
1746         if (err)
1747                 return err;
1748
1749         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753         tg3_writephy(tp, 0x16, 0x0000);
1754
1755         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757                 /* Set Extended packet length bit for jumbo frames */
1758                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759         }
1760         else {
1761                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762         }
1763
1764         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767                 reg32 &= ~0x3000;
1768                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769         } else if (!err)
1770                 err = -EBUSY;
1771
1772         return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776  * link unless the FORCE argument is non-zero.
1777  */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780         u32 cpmuctrl;
1781         u32 phy_status;
1782         int err;
1783
1784         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785                 u32 val;
1786
1787                 val = tr32(GRC_MISC_CFG);
1788                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789                 udelay(40);
1790         }
1791         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1792         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793         if (err != 0)
1794                 return -EBUSY;
1795
1796         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797                 netif_carrier_off(tp->dev);
1798                 tg3_link_report(tp);
1799         }
1800
1801         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804                 err = tg3_phy_reset_5703_4_5(tp);
1805                 if (err)
1806                         return err;
1807                 goto out;
1808         }
1809
1810         cpmuctrl = 0;
1811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815                         tw32(TG3_CPMU_CTRL,
1816                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817         }
1818
1819         err = tg3_bmcr_reset(tp);
1820         if (err)
1821                 return err;
1822
1823         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824                 u32 phy;
1825
1826                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830         }
1831
1832         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834                 u32 val;
1835
1836                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1839                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840                         udelay(40);
1841                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842                 }
1843         }
1844
1845         tg3_phy_apply_otp(tp);
1846
1847         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848                 tg3_phy_toggle_apd(tp, true);
1849         else
1850                 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860         }
1861         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862                 tg3_writephy(tp, 0x1c, 0x8d68);
1863                 tg3_writephy(tp, 0x1c, 0x8d68);
1864         }
1865         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874         }
1875         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880                         tg3_writephy(tp, MII_TG3_TEST1,
1881                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1882                 } else
1883                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885         }
1886         /* Set Extended packet length bit (bit 14) on all chips that */
1887         /* support jumbo frames */
1888         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889                 /* Cannot do read-modify-write on 5401 */
1890                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892                 u32 phy_reg;
1893
1894                 /* Set bit 14 with read-modify-write to preserve other bits */
1895                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898         }
1899
1900         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901          * jumbo frames transmission.
1902          */
1903         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904                 u32 phy_reg;
1905
1906                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909         }
1910
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912                 /* adjust output voltage */
1913                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914         }
1915
1916         tg3_phy_toggle_automdix(tp, 1);
1917         tg3_phy_set_wirespeed(tp);
1918         return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923         struct tg3 *tp_peer = tp;
1924
1925         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926                 return;
1927
1928         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930                 struct net_device *dev_peer;
1931
1932                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933                 /* remove_one() may have been run on the peer. */
1934                 if (!dev_peer)
1935                         tp_peer = tp;
1936                 else
1937                         tp_peer = netdev_priv(dev_peer);
1938         }
1939
1940         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947                                     (GRC_LCLCTRL_GPIO_OE0 |
1948                                      GRC_LCLCTRL_GPIO_OE1 |
1949                                      GRC_LCLCTRL_GPIO_OE2 |
1950                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1951                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1952                                     100);
1953                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1954                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1955                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1956                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1957                                              GRC_LCLCTRL_GPIO_OE1 |
1958                                              GRC_LCLCTRL_GPIO_OE2 |
1959                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1960                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1961                                              tp->grc_local_ctrl;
1962                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1963
1964                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1965                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1966
1967                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1968                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1969                 } else {
1970                         u32 no_gpio2;
1971                         u32 grc_local_ctrl = 0;
1972
1973                         if (tp_peer != tp &&
1974                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1975                                 return;
1976
1977                         /* Workaround to prevent overdrawing Amps. */
1978                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1979                             ASIC_REV_5714) {
1980                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1981                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1982                                             grc_local_ctrl, 100);
1983                         }
1984
1985                         /* On 5753 and variants, GPIO2 cannot be used. */
1986                         no_gpio2 = tp->nic_sram_data_cfg &
1987                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1988
1989                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1990                                          GRC_LCLCTRL_GPIO_OE1 |
1991                                          GRC_LCLCTRL_GPIO_OE2 |
1992                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1993                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1994                         if (no_gpio2) {
1995                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1996                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1997                         }
1998                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1999                                                     grc_local_ctrl, 100);
2000
2001                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2002
2003                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2004                                                     grc_local_ctrl, 100);
2005
2006                         if (!no_gpio2) {
2007                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2008                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2009                                             grc_local_ctrl, 100);
2010                         }
2011                 }
2012         } else {
2013                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2014                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2015                         if (tp_peer != tp &&
2016                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017                                 return;
2018
2019                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2020                                     (GRC_LCLCTRL_GPIO_OE1 |
2021                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2022
2023                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024                                     GRC_LCLCTRL_GPIO_OE1, 100);
2025
2026                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027                                     (GRC_LCLCTRL_GPIO_OE1 |
2028                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2029                 }
2030         }
2031 }
2032
2033 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2034 {
2035         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2036                 return 1;
2037         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2038                 if (speed != SPEED_10)
2039                         return 1;
2040         } else if (speed == SPEED_10)
2041                 return 1;
2042
2043         return 0;
2044 }
2045
2046 static int tg3_setup_phy(struct tg3 *, int);
2047
2048 #define RESET_KIND_SHUTDOWN     0
2049 #define RESET_KIND_INIT         1
2050 #define RESET_KIND_SUSPEND      2
2051
2052 static void tg3_write_sig_post_reset(struct tg3 *, int);
2053 static int tg3_halt_cpu(struct tg3 *, u32);
2054
2055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056 {
2057         u32 val;
2058
2059         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064                         sg_dig_ctrl |=
2065                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068                 }
2069                 return;
2070         }
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2073                 tg3_bmcr_reset(tp);
2074                 val = tr32(GRC_MISC_CFG);
2075                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076                 udelay(40);
2077                 return;
2078         } else if (do_low_power) {
2079                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081
2082                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2087         }
2088
2089         /* The PHY should not be powered down on some chips because
2090          * of bugs.
2091          */
2092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096                 return;
2097
2098         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104         }
2105
2106         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107 }
2108
2109 /* tp->lock is held. */
2110 static int tg3_nvram_lock(struct tg3 *tp)
2111 {
2112         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2113                 int i;
2114
2115                 if (tp->nvram_lock_cnt == 0) {
2116                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2117                         for (i = 0; i < 8000; i++) {
2118                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2119                                         break;
2120                                 udelay(20);
2121                         }
2122                         if (i == 8000) {
2123                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2124                                 return -ENODEV;
2125                         }
2126                 }
2127                 tp->nvram_lock_cnt++;
2128         }
2129         return 0;
2130 }
2131
2132 /* tp->lock is held. */
2133 static void tg3_nvram_unlock(struct tg3 *tp)
2134 {
2135         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2136                 if (tp->nvram_lock_cnt > 0)
2137                         tp->nvram_lock_cnt--;
2138                 if (tp->nvram_lock_cnt == 0)
2139                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2140         }
2141 }
2142
2143 /* tp->lock is held. */
2144 static void tg3_enable_nvram_access(struct tg3 *tp)
2145 {
2146         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2147             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2148                 u32 nvaccess = tr32(NVRAM_ACCESS);
2149
2150                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2151         }
2152 }
2153
2154 /* tp->lock is held. */
2155 static void tg3_disable_nvram_access(struct tg3 *tp)
2156 {
2157         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2158             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2159                 u32 nvaccess = tr32(NVRAM_ACCESS);
2160
2161                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2162         }
2163 }
2164
2165 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2166                                         u32 offset, u32 *val)
2167 {
2168         u32 tmp;
2169         int i;
2170
2171         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2172                 return -EINVAL;
2173
2174         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2175                                         EEPROM_ADDR_DEVID_MASK |
2176                                         EEPROM_ADDR_READ);
2177         tw32(GRC_EEPROM_ADDR,
2178              tmp |
2179              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2180              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2181               EEPROM_ADDR_ADDR_MASK) |
2182              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2183
2184         for (i = 0; i < 1000; i++) {
2185                 tmp = tr32(GRC_EEPROM_ADDR);
2186
2187                 if (tmp & EEPROM_ADDR_COMPLETE)
2188                         break;
2189                 msleep(1);
2190         }
2191         if (!(tmp & EEPROM_ADDR_COMPLETE))
2192                 return -EBUSY;
2193
2194         tmp = tr32(GRC_EEPROM_DATA);
2195
2196         /*
2197          * The data will always be opposite the native endian
2198          * format.  Perform a blind byteswap to compensate.
2199          */
2200         *val = swab32(tmp);
2201
2202         return 0;
2203 }
2204
2205 #define NVRAM_CMD_TIMEOUT 10000
2206
2207 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2208 {
2209         int i;
2210
2211         tw32(NVRAM_CMD, nvram_cmd);
2212         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2213                 udelay(10);
2214                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2215                         udelay(10);
2216                         break;
2217                 }
2218         }
2219
2220         if (i == NVRAM_CMD_TIMEOUT)
2221                 return -EBUSY;
2222
2223         return 0;
2224 }
2225
2226 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2227 {
2228         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2229             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2230             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2231            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2232             (tp->nvram_jedecnum == JEDEC_ATMEL))
2233
2234                 addr = ((addr / tp->nvram_pagesize) <<
2235                         ATMEL_AT45DB0X1B_PAGE_POS) +
2236                        (addr % tp->nvram_pagesize);
2237
2238         return addr;
2239 }
2240
2241 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2242 {
2243         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2244             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2245             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2246            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2247             (tp->nvram_jedecnum == JEDEC_ATMEL))
2248
2249                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2250                         tp->nvram_pagesize) +
2251                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2252
2253         return addr;
2254 }
2255
2256 /* NOTE: Data read in from NVRAM is byteswapped according to
2257  * the byteswapping settings for all other register accesses.
2258  * tg3 devices are BE devices, so on a BE machine, the data
2259  * returned will be exactly as it is seen in NVRAM.  On a LE
2260  * machine, the 32-bit value will be byteswapped.
2261  */
2262 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2263 {
2264         int ret;
2265
2266         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2267                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2268
2269         offset = tg3_nvram_phys_addr(tp, offset);
2270
2271         if (offset > NVRAM_ADDR_MSK)
2272                 return -EINVAL;
2273
2274         ret = tg3_nvram_lock(tp);
2275         if (ret)
2276                 return ret;
2277
2278         tg3_enable_nvram_access(tp);
2279
2280         tw32(NVRAM_ADDR, offset);
2281         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2282                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2283
2284         if (ret == 0)
2285                 *val = tr32(NVRAM_RDDATA);
2286
2287         tg3_disable_nvram_access(tp);
2288
2289         tg3_nvram_unlock(tp);
2290
2291         return ret;
2292 }
2293
2294 /* Ensures NVRAM data is in bytestream format. */
2295 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2296 {
2297         u32 v;
2298         int res = tg3_nvram_read(tp, offset, &v);
2299         if (!res)
2300                 *val = cpu_to_be32(v);
2301         return res;
2302 }
2303
2304 /* tp->lock is held. */
2305 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2306 {
2307         u32 addr_high, addr_low;
2308         int i;
2309
2310         addr_high = ((tp->dev->dev_addr[0] << 8) |
2311                      tp->dev->dev_addr[1]);
2312         addr_low = ((tp->dev->dev_addr[2] << 24) |
2313                     (tp->dev->dev_addr[3] << 16) |
2314                     (tp->dev->dev_addr[4] <<  8) |
2315                     (tp->dev->dev_addr[5] <<  0));
2316         for (i = 0; i < 4; i++) {
2317                 if (i == 1 && skip_mac_1)
2318                         continue;
2319                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2320                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2321         }
2322
2323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2324             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2325                 for (i = 0; i < 12; i++) {
2326                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2327                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2328                 }
2329         }
2330
2331         addr_high = (tp->dev->dev_addr[0] +
2332                      tp->dev->dev_addr[1] +
2333                      tp->dev->dev_addr[2] +
2334                      tp->dev->dev_addr[3] +
2335                      tp->dev->dev_addr[4] +
2336                      tp->dev->dev_addr[5]) &
2337                 TX_BACKOFF_SEED_MASK;
2338         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2339 }
2340
2341 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2342 {
2343         u32 misc_host_ctrl;
2344         bool device_should_wake, do_low_power;
2345
2346         /* Make sure register accesses (indirect or otherwise)
2347          * will function correctly.
2348          */
2349         pci_write_config_dword(tp->pdev,
2350                                TG3PCI_MISC_HOST_CTRL,
2351                                tp->misc_host_ctrl);
2352
2353         switch (state) {
2354         case PCI_D0:
2355                 pci_enable_wake(tp->pdev, state, false);
2356                 pci_set_power_state(tp->pdev, PCI_D0);
2357
2358                 /* Switch out of Vaux if it is a NIC */
2359                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2360                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2361
2362                 return 0;
2363
2364         case PCI_D1:
2365         case PCI_D2:
2366         case PCI_D3hot:
2367                 break;
2368
2369         default:
2370                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2371                         tp->dev->name, state);
2372                 return -EINVAL;
2373         }
2374
2375         /* Restore the CLKREQ setting. */
2376         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2377                 u16 lnkctl;
2378
2379                 pci_read_config_word(tp->pdev,
2380                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2381                                      &lnkctl);
2382                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2383                 pci_write_config_word(tp->pdev,
2384                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2385                                       lnkctl);
2386         }
2387
2388         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2389         tw32(TG3PCI_MISC_HOST_CTRL,
2390              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2391
2392         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2393                              device_may_wakeup(&tp->pdev->dev) &&
2394                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2395
2396         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2397                 do_low_power = false;
2398                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2399                     !tp->link_config.phy_is_low_power) {
2400                         struct phy_device *phydev;
2401                         u32 phyid, advertising;
2402
2403                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2404
2405                         tp->link_config.phy_is_low_power = 1;
2406
2407                         tp->link_config.orig_speed = phydev->speed;
2408                         tp->link_config.orig_duplex = phydev->duplex;
2409                         tp->link_config.orig_autoneg = phydev->autoneg;
2410                         tp->link_config.orig_advertising = phydev->advertising;
2411
2412                         advertising = ADVERTISED_TP |
2413                                       ADVERTISED_Pause |
2414                                       ADVERTISED_Autoneg |
2415                                       ADVERTISED_10baseT_Half;
2416
2417                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2418                             device_should_wake) {
2419                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2420                                         advertising |=
2421                                                 ADVERTISED_100baseT_Half |
2422                                                 ADVERTISED_100baseT_Full |
2423                                                 ADVERTISED_10baseT_Full;
2424                                 else
2425                                         advertising |= ADVERTISED_10baseT_Full;
2426                         }
2427
2428                         phydev->advertising = advertising;
2429
2430                         phy_start_aneg(phydev);
2431
2432                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2433                         if (phyid != TG3_PHY_ID_BCMAC131) {
2434                                 phyid &= TG3_PHY_OUI_MASK;
2435                                 if (phyid == TG3_PHY_OUI_1 ||
2436                                     phyid == TG3_PHY_OUI_2 ||
2437                                     phyid == TG3_PHY_OUI_3)
2438                                         do_low_power = true;
2439                         }
2440                 }
2441         } else {
2442                 do_low_power = true;
2443
2444                 if (tp->link_config.phy_is_low_power == 0) {
2445                         tp->link_config.phy_is_low_power = 1;
2446                         tp->link_config.orig_speed = tp->link_config.speed;
2447                         tp->link_config.orig_duplex = tp->link_config.duplex;
2448                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2449                 }
2450
2451                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2452                         tp->link_config.speed = SPEED_10;
2453                         tp->link_config.duplex = DUPLEX_HALF;
2454                         tp->link_config.autoneg = AUTONEG_ENABLE;
2455                         tg3_setup_phy(tp, 0);
2456                 }
2457         }
2458
2459         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2460                 u32 val;
2461
2462                 val = tr32(GRC_VCPU_EXT_CTRL);
2463                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2464         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2465                 int i;
2466                 u32 val;
2467
2468                 for (i = 0; i < 200; i++) {
2469                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2470                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2471                                 break;
2472                         msleep(1);
2473                 }
2474         }
2475         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2476                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2477                                                      WOL_DRV_STATE_SHUTDOWN |
2478                                                      WOL_DRV_WOL |
2479                                                      WOL_SET_MAGIC_PKT);
2480
2481         if (device_should_wake) {
2482                 u32 mac_mode;
2483
2484                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2485                         if (do_low_power) {
2486                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2487                                 udelay(40);
2488                         }
2489
2490                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2491                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2492                         else
2493                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2494
2495                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2496                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2497                             ASIC_REV_5700) {
2498                                 u32 speed = (tp->tg3_flags &
2499                                              TG3_FLAG_WOL_SPEED_100MB) ?
2500                                              SPEED_100 : SPEED_10;
2501                                 if (tg3_5700_link_polarity(tp, speed))
2502                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2503                                 else
2504                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2505                         }
2506                 } else {
2507                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2508                 }
2509
2510                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2511                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2512
2513                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2514                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2515                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2516                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2517                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2518                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2519
2520                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2521                         mac_mode |= tp->mac_mode &
2522                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2523                         if (mac_mode & MAC_MODE_APE_TX_EN)
2524                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2525                 }
2526
2527                 tw32_f(MAC_MODE, mac_mode);
2528                 udelay(100);
2529
2530                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2531                 udelay(10);
2532         }
2533
2534         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2535             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2536              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2537                 u32 base_val;
2538
2539                 base_val = tp->pci_clock_ctrl;
2540                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2541                              CLOCK_CTRL_TXCLK_DISABLE);
2542
2543                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2544                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2545         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2546                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2547                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2548                 /* do nothing */
2549         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2550                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2551                 u32 newbits1, newbits2;
2552
2553                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2554                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2555                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2556                                     CLOCK_CTRL_TXCLK_DISABLE |
2557                                     CLOCK_CTRL_ALTCLK);
2558                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2559                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2560                         newbits1 = CLOCK_CTRL_625_CORE;
2561                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2562                 } else {
2563                         newbits1 = CLOCK_CTRL_ALTCLK;
2564                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2565                 }
2566
2567                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2568                             40);
2569
2570                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2571                             40);
2572
2573                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2574                         u32 newbits3;
2575
2576                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2577                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2578                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2579                                             CLOCK_CTRL_TXCLK_DISABLE |
2580                                             CLOCK_CTRL_44MHZ_CORE);
2581                         } else {
2582                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2583                         }
2584
2585                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2586                                     tp->pci_clock_ctrl | newbits3, 40);
2587                 }
2588         }
2589
2590         if (!(device_should_wake) &&
2591             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2592                 tg3_power_down_phy(tp, do_low_power);
2593
2594         tg3_frob_aux_power(tp);
2595
2596         /* Workaround for unstable PLL clock */
2597         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2598             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2599                 u32 val = tr32(0x7d00);
2600
2601                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2602                 tw32(0x7d00, val);
2603                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2604                         int err;
2605
2606                         err = tg3_nvram_lock(tp);
2607                         tg3_halt_cpu(tp, RX_CPU_BASE);
2608                         if (!err)
2609                                 tg3_nvram_unlock(tp);
2610                 }
2611         }
2612
2613         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2614
2615         if (device_should_wake)
2616                 pci_enable_wake(tp->pdev, state, true);
2617
2618         /* Finally, set the new power state. */
2619         pci_set_power_state(tp->pdev, state);
2620
2621         return 0;
2622 }
2623
2624 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2625 {
2626         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2627         case MII_TG3_AUX_STAT_10HALF:
2628                 *speed = SPEED_10;
2629                 *duplex = DUPLEX_HALF;
2630                 break;
2631
2632         case MII_TG3_AUX_STAT_10FULL:
2633                 *speed = SPEED_10;
2634                 *duplex = DUPLEX_FULL;
2635                 break;
2636
2637         case MII_TG3_AUX_STAT_100HALF:
2638                 *speed = SPEED_100;
2639                 *duplex = DUPLEX_HALF;
2640                 break;
2641
2642         case MII_TG3_AUX_STAT_100FULL:
2643                 *speed = SPEED_100;
2644                 *duplex = DUPLEX_FULL;
2645                 break;
2646
2647         case MII_TG3_AUX_STAT_1000HALF:
2648                 *speed = SPEED_1000;
2649                 *duplex = DUPLEX_HALF;
2650                 break;
2651
2652         case MII_TG3_AUX_STAT_1000FULL:
2653                 *speed = SPEED_1000;
2654                 *duplex = DUPLEX_FULL;
2655                 break;
2656
2657         default:
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2659                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2660                                  SPEED_10;
2661                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2662                                   DUPLEX_HALF;
2663                         break;
2664                 }
2665                 *speed = SPEED_INVALID;
2666                 *duplex = DUPLEX_INVALID;
2667                 break;
2668         }
2669 }
2670
2671 static void tg3_phy_copper_begin(struct tg3 *tp)
2672 {
2673         u32 new_adv;
2674         int i;
2675
2676         if (tp->link_config.phy_is_low_power) {
2677                 /* Entering low power mode.  Disable gigabit and
2678                  * 100baseT advertisements.
2679                  */
2680                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2681
2682                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2683                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2684                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2685                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2686
2687                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2688         } else if (tp->link_config.speed == SPEED_INVALID) {
2689                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2690                         tp->link_config.advertising &=
2691                                 ~(ADVERTISED_1000baseT_Half |
2692                                   ADVERTISED_1000baseT_Full);
2693
2694                 new_adv = ADVERTISE_CSMA;
2695                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2696                         new_adv |= ADVERTISE_10HALF;
2697                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2698                         new_adv |= ADVERTISE_10FULL;
2699                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2700                         new_adv |= ADVERTISE_100HALF;
2701                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2702                         new_adv |= ADVERTISE_100FULL;
2703
2704                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2705
2706                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2707
2708                 if (tp->link_config.advertising &
2709                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2710                         new_adv = 0;
2711                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2712                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2713                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2714                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2715                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2716                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2717                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2718                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2719                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2720                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2721                 } else {
2722                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2723                 }
2724         } else {
2725                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2726                 new_adv |= ADVERTISE_CSMA;
2727
2728                 /* Asking for a specific link mode. */
2729                 if (tp->link_config.speed == SPEED_1000) {
2730                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2731
2732                         if (tp->link_config.duplex == DUPLEX_FULL)
2733                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2734                         else
2735                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2736                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2737                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2738                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2739                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2740                 } else {
2741                         if (tp->link_config.speed == SPEED_100) {
2742                                 if (tp->link_config.duplex == DUPLEX_FULL)
2743                                         new_adv |= ADVERTISE_100FULL;
2744                                 else
2745                                         new_adv |= ADVERTISE_100HALF;
2746                         } else {
2747                                 if (tp->link_config.duplex == DUPLEX_FULL)
2748                                         new_adv |= ADVERTISE_10FULL;
2749                                 else
2750                                         new_adv |= ADVERTISE_10HALF;
2751                         }
2752                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2753
2754                         new_adv = 0;
2755                 }
2756
2757                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2758         }
2759
2760         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2761             tp->link_config.speed != SPEED_INVALID) {
2762                 u32 bmcr, orig_bmcr;
2763
2764                 tp->link_config.active_speed = tp->link_config.speed;
2765                 tp->link_config.active_duplex = tp->link_config.duplex;
2766
2767                 bmcr = 0;
2768                 switch (tp->link_config.speed) {
2769                 default:
2770                 case SPEED_10:
2771                         break;
2772
2773                 case SPEED_100:
2774                         bmcr |= BMCR_SPEED100;
2775                         break;
2776
2777                 case SPEED_1000:
2778                         bmcr |= TG3_BMCR_SPEED1000;
2779                         break;
2780                 }
2781
2782                 if (tp->link_config.duplex == DUPLEX_FULL)
2783                         bmcr |= BMCR_FULLDPLX;
2784
2785                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2786                     (bmcr != orig_bmcr)) {
2787                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2788                         for (i = 0; i < 1500; i++) {
2789                                 u32 tmp;
2790
2791                                 udelay(10);
2792                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2793                                     tg3_readphy(tp, MII_BMSR, &tmp))
2794                                         continue;
2795                                 if (!(tmp & BMSR_LSTATUS)) {
2796                                         udelay(40);
2797                                         break;
2798                                 }
2799                         }
2800                         tg3_writephy(tp, MII_BMCR, bmcr);
2801                         udelay(40);
2802                 }
2803         } else {
2804                 tg3_writephy(tp, MII_BMCR,
2805                              BMCR_ANENABLE | BMCR_ANRESTART);
2806         }
2807 }
2808
2809 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2810 {
2811         int err;
2812
2813         /* Turn off tap power management. */
2814         /* Set Extended packet length bit */
2815         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2816
2817         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2818         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2819
2820         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2821         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2822
2823         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2824         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2825
2826         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2827         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2828
2829         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2830         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2831
2832         udelay(40);
2833
2834         return err;
2835 }
2836
2837 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2838 {
2839         u32 adv_reg, all_mask = 0;
2840
2841         if (mask & ADVERTISED_10baseT_Half)
2842                 all_mask |= ADVERTISE_10HALF;
2843         if (mask & ADVERTISED_10baseT_Full)
2844                 all_mask |= ADVERTISE_10FULL;
2845         if (mask & ADVERTISED_100baseT_Half)
2846                 all_mask |= ADVERTISE_100HALF;
2847         if (mask & ADVERTISED_100baseT_Full)
2848                 all_mask |= ADVERTISE_100FULL;
2849
2850         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2851                 return 0;
2852
2853         if ((adv_reg & all_mask) != all_mask)
2854                 return 0;
2855         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2856                 u32 tg3_ctrl;
2857
2858                 all_mask = 0;
2859                 if (mask & ADVERTISED_1000baseT_Half)
2860                         all_mask |= ADVERTISE_1000HALF;
2861                 if (mask & ADVERTISED_1000baseT_Full)
2862                         all_mask |= ADVERTISE_1000FULL;
2863
2864                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2865                         return 0;
2866
2867                 if ((tg3_ctrl & all_mask) != all_mask)
2868                         return 0;
2869         }
2870         return 1;
2871 }
2872
2873 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2874 {
2875         u32 curadv, reqadv;
2876
2877         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2878                 return 1;
2879
2880         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2881         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2882
2883         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2884                 if (curadv != reqadv)
2885                         return 0;
2886
2887                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2888                         tg3_readphy(tp, MII_LPA, rmtadv);
2889         } else {
2890                 /* Reprogram the advertisement register, even if it
2891                  * does not affect the current link.  If the link
2892                  * gets renegotiated in the future, we can save an
2893                  * additional renegotiation cycle by advertising
2894                  * it correctly in the first place.
2895                  */
2896                 if (curadv != reqadv) {
2897                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2898                                      ADVERTISE_PAUSE_ASYM);
2899                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2900                 }
2901         }
2902
2903         return 1;
2904 }
2905
2906 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2907 {
2908         int current_link_up;
2909         u32 bmsr, dummy;
2910         u32 lcl_adv, rmt_adv;
2911         u16 current_speed;
2912         u8 current_duplex;
2913         int i, err;
2914
2915         tw32(MAC_EVENT, 0);
2916
2917         tw32_f(MAC_STATUS,
2918              (MAC_STATUS_SYNC_CHANGED |
2919               MAC_STATUS_CFG_CHANGED |
2920               MAC_STATUS_MI_COMPLETION |
2921               MAC_STATUS_LNKSTATE_CHANGED));
2922         udelay(40);
2923
2924         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2925                 tw32_f(MAC_MI_MODE,
2926                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2927                 udelay(80);
2928         }
2929
2930         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2931
2932         /* Some third-party PHYs need to be reset on link going
2933          * down.
2934          */
2935         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2936              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2937              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2938             netif_carrier_ok(tp->dev)) {
2939                 tg3_readphy(tp, MII_BMSR, &bmsr);
2940                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2941                     !(bmsr & BMSR_LSTATUS))
2942                         force_reset = 1;
2943         }
2944         if (force_reset)
2945                 tg3_phy_reset(tp);
2946
2947         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2948                 tg3_readphy(tp, MII_BMSR, &bmsr);
2949                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2950                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2951                         bmsr = 0;
2952
2953                 if (!(bmsr & BMSR_LSTATUS)) {
2954                         err = tg3_init_5401phy_dsp(tp);
2955                         if (err)
2956                                 return err;
2957
2958                         tg3_readphy(tp, MII_BMSR, &bmsr);
2959                         for (i = 0; i < 1000; i++) {
2960                                 udelay(10);
2961                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2962                                     (bmsr & BMSR_LSTATUS)) {
2963                                         udelay(40);
2964                                         break;
2965                                 }
2966                         }
2967
2968                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2969                             !(bmsr & BMSR_LSTATUS) &&
2970                             tp->link_config.active_speed == SPEED_1000) {
2971                                 err = tg3_phy_reset(tp);
2972                                 if (!err)
2973                                         err = tg3_init_5401phy_dsp(tp);
2974                                 if (err)
2975                                         return err;
2976                         }
2977                 }
2978         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2979                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2980                 /* 5701 {A0,B0} CRC bug workaround */
2981                 tg3_writephy(tp, 0x15, 0x0a75);
2982                 tg3_writephy(tp, 0x1c, 0x8c68);
2983                 tg3_writephy(tp, 0x1c, 0x8d68);
2984                 tg3_writephy(tp, 0x1c, 0x8c68);
2985         }
2986
2987         /* Clear pending interrupts... */
2988         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2989         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2990
2991         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2992                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2993         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2994                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2995
2996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2998                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2999                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3000                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3001                 else
3002                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3003         }
3004
3005         current_link_up = 0;
3006         current_speed = SPEED_INVALID;
3007         current_duplex = DUPLEX_INVALID;
3008
3009         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3010                 u32 val;
3011
3012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3013                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3014                 if (!(val & (1 << 10))) {
3015                         val |= (1 << 10);
3016                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3017                         goto relink;
3018                 }
3019         }
3020
3021         bmsr = 0;
3022         for (i = 0; i < 100; i++) {
3023                 tg3_readphy(tp, MII_BMSR, &bmsr);
3024                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3025                     (bmsr & BMSR_LSTATUS))
3026                         break;
3027                 udelay(40);
3028         }
3029
3030         if (bmsr & BMSR_LSTATUS) {
3031                 u32 aux_stat, bmcr;
3032
3033                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3034                 for (i = 0; i < 2000; i++) {
3035                         udelay(10);
3036                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3037                             aux_stat)
3038                                 break;
3039                 }
3040
3041                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3042                                              &current_speed,
3043                                              &current_duplex);
3044
3045                 bmcr = 0;
3046                 for (i = 0; i < 200; i++) {
3047                         tg3_readphy(tp, MII_BMCR, &bmcr);
3048                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3049                                 continue;
3050                         if (bmcr && bmcr != 0x7fff)
3051                                 break;
3052                         udelay(10);
3053                 }
3054
3055                 lcl_adv = 0;
3056                 rmt_adv = 0;
3057
3058                 tp->link_config.active_speed = current_speed;
3059                 tp->link_config.active_duplex = current_duplex;
3060
3061                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3062                         if ((bmcr & BMCR_ANENABLE) &&
3063                             tg3_copper_is_advertising_all(tp,
3064                                                 tp->link_config.advertising)) {
3065                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3066                                                                   &rmt_adv))
3067                                         current_link_up = 1;
3068                         }
3069                 } else {
3070                         if (!(bmcr & BMCR_ANENABLE) &&
3071                             tp->link_config.speed == current_speed &&
3072                             tp->link_config.duplex == current_duplex &&
3073                             tp->link_config.flowctrl ==
3074                             tp->link_config.active_flowctrl) {
3075                                 current_link_up = 1;
3076                         }
3077                 }
3078
3079                 if (current_link_up == 1 &&
3080                     tp->link_config.active_duplex == DUPLEX_FULL)
3081                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3082         }
3083
3084 relink:
3085         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3086                 u32 tmp;
3087
3088                 tg3_phy_copper_begin(tp);
3089
3090                 tg3_readphy(tp, MII_BMSR, &tmp);
3091                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3092                     (tmp & BMSR_LSTATUS))
3093                         current_link_up = 1;
3094         }
3095
3096         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3097         if (current_link_up == 1) {
3098                 if (tp->link_config.active_speed == SPEED_100 ||
3099                     tp->link_config.active_speed == SPEED_10)
3100                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3101                 else
3102                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3103         } else
3104                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3105
3106         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3107         if (tp->link_config.active_duplex == DUPLEX_HALF)
3108                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3109
3110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3111                 if (current_link_up == 1 &&
3112                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3113                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3114                 else
3115                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3116         }
3117
3118         /* ??? Without this setting Netgear GA302T PHY does not
3119          * ??? send/receive packets...
3120          */
3121         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3122             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3123                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3124                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3125                 udelay(80);
3126         }
3127
3128         tw32_f(MAC_MODE, tp->mac_mode);
3129         udelay(40);
3130
3131         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3132                 /* Polled via timer. */
3133                 tw32_f(MAC_EVENT, 0);
3134         } else {
3135                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3136         }
3137         udelay(40);
3138
3139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3140             current_link_up == 1 &&
3141             tp->link_config.active_speed == SPEED_1000 &&
3142             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3143              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3144                 udelay(120);
3145                 tw32_f(MAC_STATUS,
3146                      (MAC_STATUS_SYNC_CHANGED |
3147                       MAC_STATUS_CFG_CHANGED));
3148                 udelay(40);
3149                 tg3_write_mem(tp,
3150                               NIC_SRAM_FIRMWARE_MBOX,
3151                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3152         }
3153
3154         /* Prevent send BD corruption. */
3155         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3156                 u16 oldlnkctl, newlnkctl;
3157
3158                 pci_read_config_word(tp->pdev,
3159                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3160                                      &oldlnkctl);
3161                 if (tp->link_config.active_speed == SPEED_100 ||
3162                     tp->link_config.active_speed == SPEED_10)
3163                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3164                 else
3165                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3166                 if (newlnkctl != oldlnkctl)
3167                         pci_write_config_word(tp->pdev,
3168                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3169                                               newlnkctl);
3170         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3171                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3172                 if (tp->link_config.active_speed == SPEED_100 ||
3173                     tp->link_config.active_speed == SPEED_10)
3174                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3175                 else
3176                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3177                 if (newreg != oldreg)
3178                         tw32(TG3_PCIE_LNKCTL, newreg);
3179         }
3180
3181         if (current_link_up != netif_carrier_ok(tp->dev)) {
3182                 if (current_link_up)
3183                         netif_carrier_on(tp->dev);
3184                 else
3185                         netif_carrier_off(tp->dev);
3186                 tg3_link_report(tp);
3187         }
3188
3189         return 0;
3190 }
3191
3192 struct tg3_fiber_aneginfo {
3193         int state;
3194 #define ANEG_STATE_UNKNOWN              0
3195 #define ANEG_STATE_AN_ENABLE            1
3196 #define ANEG_STATE_RESTART_INIT         2
3197 #define ANEG_STATE_RESTART              3
3198 #define ANEG_STATE_DISABLE_LINK_OK      4
3199 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3200 #define ANEG_STATE_ABILITY_DETECT       6
3201 #define ANEG_STATE_ACK_DETECT_INIT      7
3202 #define ANEG_STATE_ACK_DETECT           8
3203 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3204 #define ANEG_STATE_COMPLETE_ACK         10
3205 #define ANEG_STATE_IDLE_DETECT_INIT     11
3206 #define ANEG_STATE_IDLE_DETECT          12
3207 #define ANEG_STATE_LINK_OK              13
3208 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3209 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3210
3211         u32 flags;
3212 #define MR_AN_ENABLE            0x00000001
3213 #define MR_RESTART_AN           0x00000002
3214 #define MR_AN_COMPLETE          0x00000004
3215 #define MR_PAGE_RX              0x00000008
3216 #define MR_NP_LOADED            0x00000010
3217 #define MR_TOGGLE_TX            0x00000020
3218 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3219 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3220 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3221 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3222 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3223 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3224 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3225 #define MR_TOGGLE_RX            0x00002000
3226 #define MR_NP_RX                0x00004000
3227
3228 #define MR_LINK_OK              0x80000000
3229
3230         unsigned long link_time, cur_time;
3231
3232         u32 ability_match_cfg;
3233         int ability_match_count;
3234
3235         char ability_match, idle_match, ack_match;
3236
3237         u32 txconfig, rxconfig;
3238 #define ANEG_CFG_NP             0x00000080
3239 #define ANEG_CFG_ACK            0x00000040
3240 #define ANEG_CFG_RF2            0x00000020
3241 #define ANEG_CFG_RF1            0x00000010
3242 #define ANEG_CFG_PS2            0x00000001
3243 #define ANEG_CFG_PS1            0x00008000
3244 #define ANEG_CFG_HD             0x00004000
3245 #define ANEG_CFG_FD             0x00002000
3246 #define ANEG_CFG_INVAL          0x00001f06
3247
3248 };
3249 #define ANEG_OK         0
3250 #define ANEG_DONE       1
3251 #define ANEG_TIMER_ENAB 2
3252 #define ANEG_FAILED     -1
3253
3254 #define ANEG_STATE_SETTLE_TIME  10000
3255
3256 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3257                                    struct tg3_fiber_aneginfo *ap)
3258 {
3259         u16 flowctrl;
3260         unsigned long delta;
3261         u32 rx_cfg_reg;
3262         int ret;
3263
3264         if (ap->state == ANEG_STATE_UNKNOWN) {
3265                 ap->rxconfig = 0;
3266                 ap->link_time = 0;
3267                 ap->cur_time = 0;
3268                 ap->ability_match_cfg = 0;
3269                 ap->ability_match_count = 0;
3270                 ap->ability_match = 0;
3271                 ap->idle_match = 0;
3272                 ap->ack_match = 0;
3273         }
3274         ap->cur_time++;
3275
3276         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3277                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3278
3279                 if (rx_cfg_reg != ap->ability_match_cfg) {
3280                         ap->ability_match_cfg = rx_cfg_reg;
3281                         ap->ability_match = 0;
3282                         ap->ability_match_count = 0;
3283                 } else {
3284                         if (++ap->ability_match_count > 1) {
3285                                 ap->ability_match = 1;
3286                                 ap->ability_match_cfg = rx_cfg_reg;
3287                         }
3288                 }
3289                 if (rx_cfg_reg & ANEG_CFG_ACK)
3290                         ap->ack_match = 1;
3291                 else
3292                         ap->ack_match = 0;
3293
3294                 ap->idle_match = 0;
3295         } else {
3296                 ap->idle_match = 1;
3297                 ap->ability_match_cfg = 0;
3298                 ap->ability_match_count = 0;
3299                 ap->ability_match = 0;
3300                 ap->ack_match = 0;
3301
3302                 rx_cfg_reg = 0;
3303         }
3304
3305         ap->rxconfig = rx_cfg_reg;
3306         ret = ANEG_OK;
3307
3308         switch(ap->state) {
3309         case ANEG_STATE_UNKNOWN:
3310                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3311                         ap->state = ANEG_STATE_AN_ENABLE;
3312
3313                 /* fallthru */
3314         case ANEG_STATE_AN_ENABLE:
3315                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3316                 if (ap->flags & MR_AN_ENABLE) {
3317                         ap->link_time = 0;
3318                         ap->cur_time = 0;
3319                         ap->ability_match_cfg = 0;
3320                         ap->ability_match_count = 0;
3321                         ap->ability_match = 0;
3322                         ap->idle_match = 0;
3323                         ap->ack_match = 0;
3324
3325                         ap->state = ANEG_STATE_RESTART_INIT;
3326                 } else {
3327                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3328                 }
3329                 break;
3330
3331         case ANEG_STATE_RESTART_INIT:
3332                 ap->link_time = ap->cur_time;
3333                 ap->flags &= ~(MR_NP_LOADED);
3334                 ap->txconfig = 0;
3335                 tw32(MAC_TX_AUTO_NEG, 0);
3336                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3337                 tw32_f(MAC_MODE, tp->mac_mode);
3338                 udelay(40);
3339
3340                 ret = ANEG_TIMER_ENAB;
3341                 ap->state = ANEG_STATE_RESTART;
3342
3343                 /* fallthru */
3344         case ANEG_STATE_RESTART:
3345                 delta = ap->cur_time - ap->link_time;
3346                 if (delta > ANEG_STATE_SETTLE_TIME) {
3347                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3348                 } else {
3349                         ret = ANEG_TIMER_ENAB;
3350                 }
3351                 break;
3352
3353         case ANEG_STATE_DISABLE_LINK_OK:
3354                 ret = ANEG_DONE;
3355                 break;
3356
3357         case ANEG_STATE_ABILITY_DETECT_INIT:
3358                 ap->flags &= ~(MR_TOGGLE_TX);
3359                 ap->txconfig = ANEG_CFG_FD;
3360                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3361                 if (flowctrl & ADVERTISE_1000XPAUSE)
3362                         ap->txconfig |= ANEG_CFG_PS1;
3363                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3364                         ap->txconfig |= ANEG_CFG_PS2;
3365                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3366                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3367                 tw32_f(MAC_MODE, tp->mac_mode);
3368                 udelay(40);
3369
3370                 ap->state = ANEG_STATE_ABILITY_DETECT;
3371                 break;
3372
3373         case ANEG_STATE_ABILITY_DETECT:
3374                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3375                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3376                 }
3377                 break;
3378
3379         case ANEG_STATE_ACK_DETECT_INIT:
3380                 ap->txconfig |= ANEG_CFG_ACK;
3381                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3382                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3383                 tw32_f(MAC_MODE, tp->mac_mode);
3384                 udelay(40);
3385
3386                 ap->state = ANEG_STATE_ACK_DETECT;
3387
3388                 /* fallthru */
3389         case ANEG_STATE_ACK_DETECT:
3390                 if (ap->ack_match != 0) {
3391                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3392                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3393                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3394                         } else {
3395                                 ap->state = ANEG_STATE_AN_ENABLE;
3396                         }
3397                 } else if (ap->ability_match != 0 &&
3398                            ap->rxconfig == 0) {
3399                         ap->state = ANEG_STATE_AN_ENABLE;
3400                 }
3401                 break;
3402
3403         case ANEG_STATE_COMPLETE_ACK_INIT:
3404                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3405                         ret = ANEG_FAILED;
3406                         break;
3407                 }
3408                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3409                                MR_LP_ADV_HALF_DUPLEX |
3410                                MR_LP_ADV_SYM_PAUSE |
3411                                MR_LP_ADV_ASYM_PAUSE |
3412                                MR_LP_ADV_REMOTE_FAULT1 |
3413                                MR_LP_ADV_REMOTE_FAULT2 |
3414                                MR_LP_ADV_NEXT_PAGE |
3415                                MR_TOGGLE_RX |
3416                                MR_NP_RX);
3417                 if (ap->rxconfig & ANEG_CFG_FD)
3418                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3419                 if (ap->rxconfig & ANEG_CFG_HD)
3420                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3421                 if (ap->rxconfig & ANEG_CFG_PS1)
3422                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3423                 if (ap->rxconfig & ANEG_CFG_PS2)
3424                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3425                 if (ap->rxconfig & ANEG_CFG_RF1)
3426                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3427                 if (ap->rxconfig & ANEG_CFG_RF2)
3428                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3429                 if (ap->rxconfig & ANEG_CFG_NP)
3430                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3431
3432                 ap->link_time = ap->cur_time;
3433
3434                 ap->flags ^= (MR_TOGGLE_TX);
3435                 if (ap->rxconfig & 0x0008)
3436                         ap->flags |= MR_TOGGLE_RX;
3437                 if (ap->rxconfig & ANEG_CFG_NP)
3438                         ap->flags |= MR_NP_RX;
3439                 ap->flags |= MR_PAGE_RX;
3440
3441                 ap->state = ANEG_STATE_COMPLETE_ACK;
3442                 ret = ANEG_TIMER_ENAB;
3443                 break;
3444
3445         case ANEG_STATE_COMPLETE_ACK:
3446                 if (ap->ability_match != 0 &&
3447                     ap->rxconfig == 0) {
3448                         ap->state = ANEG_STATE_AN_ENABLE;
3449                         break;
3450                 }
3451                 delta = ap->cur_time - ap->link_time;
3452                 if (delta > ANEG_STATE_SETTLE_TIME) {
3453                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3454                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3455                         } else {
3456                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3457                                     !(ap->flags & MR_NP_RX)) {
3458                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3459                                 } else {
3460                                         ret = ANEG_FAILED;
3461                                 }
3462                         }
3463                 }
3464                 break;
3465
3466         case ANEG_STATE_IDLE_DETECT_INIT:
3467                 ap->link_time = ap->cur_time;
3468                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3469                 tw32_f(MAC_MODE, tp->mac_mode);
3470                 udelay(40);
3471
3472                 ap->state = ANEG_STATE_IDLE_DETECT;
3473                 ret = ANEG_TIMER_ENAB;
3474                 break;
3475
3476         case ANEG_STATE_IDLE_DETECT:
3477                 if (ap->ability_match != 0 &&
3478                     ap->rxconfig == 0) {
3479                         ap->state = ANEG_STATE_AN_ENABLE;
3480                         break;
3481                 }
3482                 delta = ap->cur_time - ap->link_time;
3483                 if (delta > ANEG_STATE_SETTLE_TIME) {
3484                         /* XXX another gem from the Broadcom driver :( */
3485                         ap->state = ANEG_STATE_LINK_OK;
3486                 }
3487                 break;
3488
3489         case ANEG_STATE_LINK_OK:
3490                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3491                 ret = ANEG_DONE;
3492                 break;
3493
3494         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3495                 /* ??? unimplemented */
3496                 break;
3497
3498         case ANEG_STATE_NEXT_PAGE_WAIT:
3499                 /* ??? unimplemented */
3500                 break;
3501
3502         default:
3503                 ret = ANEG_FAILED;
3504                 break;
3505         }
3506
3507         return ret;
3508 }
3509
3510 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3511 {
3512         int res = 0;
3513         struct tg3_fiber_aneginfo aninfo;
3514         int status = ANEG_FAILED;
3515         unsigned int tick;
3516         u32 tmp;
3517
3518         tw32_f(MAC_TX_AUTO_NEG, 0);
3519
3520         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3521         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3522         udelay(40);
3523
3524         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3525         udelay(40);
3526
3527         memset(&aninfo, 0, sizeof(aninfo));
3528         aninfo.flags |= MR_AN_ENABLE;
3529         aninfo.state = ANEG_STATE_UNKNOWN;
3530         aninfo.cur_time = 0;
3531         tick = 0;
3532         while (++tick < 195000) {
3533                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3534                 if (status == ANEG_DONE || status == ANEG_FAILED)
3535                         break;
3536
3537                 udelay(1);
3538         }
3539
3540         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3541         tw32_f(MAC_MODE, tp->mac_mode);
3542         udelay(40);
3543
3544         *txflags = aninfo.txconfig;
3545         *rxflags = aninfo.flags;
3546
3547         if (status == ANEG_DONE &&
3548             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3549                              MR_LP_ADV_FULL_DUPLEX)))
3550                 res = 1;
3551
3552         return res;
3553 }
3554
3555 static void tg3_init_bcm8002(struct tg3 *tp)
3556 {
3557         u32 mac_status = tr32(MAC_STATUS);
3558         int i;
3559
3560         /* Reset when initting first time or we have a link. */
3561         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3562             !(mac_status & MAC_STATUS_PCS_SYNCED))
3563                 return;
3564
3565         /* Set PLL lock range. */
3566         tg3_writephy(tp, 0x16, 0x8007);
3567
3568         /* SW reset */
3569         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3570
3571         /* Wait for reset to complete. */
3572         /* XXX schedule_timeout() ... */
3573         for (i = 0; i < 500; i++)
3574                 udelay(10);
3575
3576         /* Config mode; select PMA/Ch 1 regs. */
3577         tg3_writephy(tp, 0x10, 0x8411);
3578
3579         /* Enable auto-lock and comdet, select txclk for tx. */
3580         tg3_writephy(tp, 0x11, 0x0a10);
3581
3582         tg3_writephy(tp, 0x18, 0x00a0);
3583         tg3_writephy(tp, 0x16, 0x41ff);
3584
3585         /* Assert and deassert POR. */
3586         tg3_writephy(tp, 0x13, 0x0400);
3587         udelay(40);
3588         tg3_writephy(tp, 0x13, 0x0000);
3589
3590         tg3_writephy(tp, 0x11, 0x0a50);
3591         udelay(40);
3592         tg3_writephy(tp, 0x11, 0x0a10);
3593
3594         /* Wait for signal to stabilize */
3595         /* XXX schedule_timeout() ... */
3596         for (i = 0; i < 15000; i++)
3597                 udelay(10);
3598
3599         /* Deselect the channel register so we can read the PHYID
3600          * later.
3601          */
3602         tg3_writephy(tp, 0x10, 0x8011);
3603 }
3604
3605 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3606 {
3607         u16 flowctrl;
3608         u32 sg_dig_ctrl, sg_dig_status;
3609         u32 serdes_cfg, expected_sg_dig_ctrl;
3610         int workaround, port_a;
3611         int current_link_up;
3612
3613         serdes_cfg = 0;
3614         expected_sg_dig_ctrl = 0;
3615         workaround = 0;
3616         port_a = 1;
3617         current_link_up = 0;
3618
3619         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3620             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3621                 workaround = 1;
3622                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3623                         port_a = 0;
3624
3625                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3626                 /* preserve bits 20-23 for voltage regulator */
3627                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3628         }
3629
3630         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3631
3632         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3633                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3634                         if (workaround) {
3635                                 u32 val = serdes_cfg;
3636
3637                                 if (port_a)
3638                                         val |= 0xc010000;
3639                                 else
3640                                         val |= 0x4010000;
3641                                 tw32_f(MAC_SERDES_CFG, val);
3642                         }
3643
3644                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3645                 }
3646                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3647                         tg3_setup_flow_control(tp, 0, 0);
3648                         current_link_up = 1;
3649                 }
3650                 goto out;
3651         }
3652
3653         /* Want auto-negotiation.  */
3654         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3655
3656         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3657         if (flowctrl & ADVERTISE_1000XPAUSE)
3658                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3659         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3660                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3661
3662         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3663                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3664                     tp->serdes_counter &&
3665                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3666                                     MAC_STATUS_RCVD_CFG)) ==
3667                      MAC_STATUS_PCS_SYNCED)) {
3668                         tp->serdes_counter--;
3669                         current_link_up = 1;
3670                         goto out;
3671                 }
3672 restart_autoneg:
3673                 if (workaround)
3674                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3675                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3676                 udelay(5);
3677                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3678
3679                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3680                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3681         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3682                                  MAC_STATUS_SIGNAL_DET)) {
3683                 sg_dig_status = tr32(SG_DIG_STATUS);
3684                 mac_status = tr32(MAC_STATUS);
3685
3686                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3687                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3688                         u32 local_adv = 0, remote_adv = 0;
3689
3690                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3691                                 local_adv |= ADVERTISE_1000XPAUSE;
3692                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3693                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3694
3695                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3696                                 remote_adv |= LPA_1000XPAUSE;
3697                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3698                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3699
3700                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3701                         current_link_up = 1;
3702                         tp->serdes_counter = 0;
3703                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3704                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3705                         if (tp->serdes_counter)
3706                                 tp->serdes_counter--;
3707                         else {
3708                                 if (workaround) {
3709                                         u32 val = serdes_cfg;
3710
3711                                         if (port_a)
3712                                                 val |= 0xc010000;
3713                                         else
3714                                                 val |= 0x4010000;
3715
3716                                         tw32_f(MAC_SERDES_CFG, val);
3717                                 }
3718
3719                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3720                                 udelay(40);
3721
3722                                 /* Link parallel detection - link is up */
3723                                 /* only if we have PCS_SYNC and not */
3724                                 /* receiving config code words */
3725                                 mac_status = tr32(MAC_STATUS);
3726                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3727                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3728                                         tg3_setup_flow_control(tp, 0, 0);
3729                                         current_link_up = 1;
3730                                         tp->tg3_flags2 |=
3731                                                 TG3_FLG2_PARALLEL_DETECT;
3732                                         tp->serdes_counter =
3733                                                 SERDES_PARALLEL_DET_TIMEOUT;
3734                                 } else
3735                                         goto restart_autoneg;
3736                         }
3737                 }
3738         } else {
3739                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3740                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3741         }
3742
3743 out:
3744         return current_link_up;
3745 }
3746
3747 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3748 {
3749         int current_link_up = 0;
3750
3751         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3752                 goto out;
3753
3754         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3755                 u32 txflags, rxflags;
3756                 int i;
3757
3758                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3759                         u32 local_adv = 0, remote_adv = 0;
3760
3761                         if (txflags & ANEG_CFG_PS1)
3762                                 local_adv |= ADVERTISE_1000XPAUSE;
3763                         if (txflags & ANEG_CFG_PS2)
3764                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3765
3766                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3767                                 remote_adv |= LPA_1000XPAUSE;
3768                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3769                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3770
3771                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3772
3773                         current_link_up = 1;
3774                 }
3775                 for (i = 0; i < 30; i++) {
3776                         udelay(20);
3777                         tw32_f(MAC_STATUS,
3778                                (MAC_STATUS_SYNC_CHANGED |
3779                                 MAC_STATUS_CFG_CHANGED));
3780                         udelay(40);
3781                         if ((tr32(MAC_STATUS) &
3782                              (MAC_STATUS_SYNC_CHANGED |
3783                               MAC_STATUS_CFG_CHANGED)) == 0)
3784                                 break;
3785                 }
3786
3787                 mac_status = tr32(MAC_STATUS);
3788                 if (current_link_up == 0 &&
3789                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3790                     !(mac_status & MAC_STATUS_RCVD_CFG))
3791                         current_link_up = 1;
3792         } else {
3793                 tg3_setup_flow_control(tp, 0, 0);
3794
3795                 /* Forcing 1000FD link up. */
3796                 current_link_up = 1;
3797
3798                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3799                 udelay(40);
3800
3801                 tw32_f(MAC_MODE, tp->mac_mode);
3802                 udelay(40);
3803         }
3804
3805 out:
3806         return current_link_up;
3807 }
3808
3809 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3810 {
3811         u32 orig_pause_cfg;
3812         u16 orig_active_speed;
3813         u8 orig_active_duplex;
3814         u32 mac_status;
3815         int current_link_up;
3816         int i;
3817
3818         orig_pause_cfg = tp->link_config.active_flowctrl;
3819         orig_active_speed = tp->link_config.active_speed;
3820         orig_active_duplex = tp->link_config.active_duplex;
3821
3822         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3823             netif_carrier_ok(tp->dev) &&
3824             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3825                 mac_status = tr32(MAC_STATUS);
3826                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3827                                MAC_STATUS_SIGNAL_DET |
3828                                MAC_STATUS_CFG_CHANGED |
3829                                MAC_STATUS_RCVD_CFG);
3830                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3831                                    MAC_STATUS_SIGNAL_DET)) {
3832                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3833                                             MAC_STATUS_CFG_CHANGED));
3834                         return 0;
3835                 }
3836         }
3837
3838         tw32_f(MAC_TX_AUTO_NEG, 0);
3839
3840         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3841         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3842         tw32_f(MAC_MODE, tp->mac_mode);
3843         udelay(40);
3844
3845         if (tp->phy_id == PHY_ID_BCM8002)
3846                 tg3_init_bcm8002(tp);
3847
3848         /* Enable link change event even when serdes polling.  */
3849         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3850         udelay(40);
3851
3852         current_link_up = 0;
3853         mac_status = tr32(MAC_STATUS);
3854
3855         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3856                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3857         else
3858                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3859
3860         tp->hw_status->status =
3861                 (SD_STATUS_UPDATED |
3862                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3863
3864         for (i = 0; i < 100; i++) {
3865                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3866                                     MAC_STATUS_CFG_CHANGED));
3867                 udelay(5);
3868                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3869                                          MAC_STATUS_CFG_CHANGED |
3870                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3871                         break;
3872         }
3873
3874         mac_status = tr32(MAC_STATUS);
3875         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3876                 current_link_up = 0;
3877                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3878                     tp->serdes_counter == 0) {
3879                         tw32_f(MAC_MODE, (tp->mac_mode |
3880                                           MAC_MODE_SEND_CONFIGS));
3881                         udelay(1);
3882                         tw32_f(MAC_MODE, tp->mac_mode);
3883                 }
3884         }
3885
3886         if (current_link_up == 1) {
3887                 tp->link_config.active_speed = SPEED_1000;
3888                 tp->link_config.active_duplex = DUPLEX_FULL;
3889                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3890                                     LED_CTRL_LNKLED_OVERRIDE |
3891                                     LED_CTRL_1000MBPS_ON));
3892         } else {
3893                 tp->link_config.active_speed = SPEED_INVALID;
3894                 tp->link_config.active_duplex = DUPLEX_INVALID;
3895                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3896                                     LED_CTRL_LNKLED_OVERRIDE |
3897                                     LED_CTRL_TRAFFIC_OVERRIDE));
3898         }
3899
3900         if (current_link_up != netif_carrier_ok(tp->dev)) {
3901                 if (current_link_up)
3902                         netif_carrier_on(tp->dev);
3903                 else
3904                         netif_carrier_off(tp->dev);
3905                 tg3_link_report(tp);
3906         } else {
3907                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3908                 if (orig_pause_cfg != now_pause_cfg ||
3909                     orig_active_speed != tp->link_config.active_speed ||
3910                     orig_active_duplex != tp->link_config.active_duplex)
3911                         tg3_link_report(tp);
3912         }
3913
3914         return 0;
3915 }
3916
3917 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3918 {
3919         int current_link_up, err = 0;
3920         u32 bmsr, bmcr;
3921         u16 current_speed;
3922         u8 current_duplex;
3923         u32 local_adv, remote_adv;
3924
3925         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3926         tw32_f(MAC_MODE, tp->mac_mode);
3927         udelay(40);
3928
3929         tw32(MAC_EVENT, 0);
3930
3931         tw32_f(MAC_STATUS,
3932              (MAC_STATUS_SYNC_CHANGED |
3933               MAC_STATUS_CFG_CHANGED |
3934               MAC_STATUS_MI_COMPLETION |
3935               MAC_STATUS_LNKSTATE_CHANGED));
3936         udelay(40);
3937
3938         if (force_reset)
3939                 tg3_phy_reset(tp);
3940
3941         current_link_up = 0;
3942         current_speed = SPEED_INVALID;
3943         current_duplex = DUPLEX_INVALID;
3944
3945         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3946         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3948                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3949                         bmsr |= BMSR_LSTATUS;
3950                 else
3951                         bmsr &= ~BMSR_LSTATUS;
3952         }
3953
3954         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3955
3956         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3957             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3958                 /* do nothing, just check for link up at the end */
3959         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3960                 u32 adv, new_adv;
3961
3962                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3963                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3964                                   ADVERTISE_1000XPAUSE |
3965                                   ADVERTISE_1000XPSE_ASYM |
3966                                   ADVERTISE_SLCT);
3967
3968                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3969
3970                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3971                         new_adv |= ADVERTISE_1000XHALF;
3972                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3973                         new_adv |= ADVERTISE_1000XFULL;
3974
3975                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3976                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3977                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3978                         tg3_writephy(tp, MII_BMCR, bmcr);
3979
3980                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3981                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3982                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3983
3984                         return err;
3985                 }
3986         } else {
3987                 u32 new_bmcr;
3988
3989                 bmcr &= ~BMCR_SPEED1000;
3990                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3991
3992                 if (tp->link_config.duplex == DUPLEX_FULL)
3993                         new_bmcr |= BMCR_FULLDPLX;
3994
3995                 if (new_bmcr != bmcr) {
3996                         /* BMCR_SPEED1000 is a reserved bit that needs
3997                          * to be set on write.
3998                          */
3999                         new_bmcr |= BMCR_SPEED1000;
4000
4001                         /* Force a linkdown */
4002                         if (netif_carrier_ok(tp->dev)) {
4003                                 u32 adv;
4004
4005                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4006                                 adv &= ~(ADVERTISE_1000XFULL |
4007                                          ADVERTISE_1000XHALF |
4008                                          ADVERTISE_SLCT);
4009                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4010                                 tg3_writephy(tp, MII_BMCR, bmcr |
4011                                                            BMCR_ANRESTART |
4012                                                            BMCR_ANENABLE);
4013                                 udelay(10);
4014                                 netif_carrier_off(tp->dev);
4015                         }
4016                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4017                         bmcr = new_bmcr;
4018                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4019                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4020                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4021                             ASIC_REV_5714) {
4022                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4023                                         bmsr |= BMSR_LSTATUS;
4024                                 else
4025                                         bmsr &= ~BMSR_LSTATUS;
4026                         }
4027                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4028                 }
4029         }
4030
4031         if (bmsr & BMSR_LSTATUS) {
4032                 current_speed = SPEED_1000;
4033                 current_link_up = 1;
4034                 if (bmcr & BMCR_FULLDPLX)
4035                         current_duplex = DUPLEX_FULL;
4036                 else
4037                         current_duplex = DUPLEX_HALF;
4038
4039                 local_adv = 0;
4040                 remote_adv = 0;
4041
4042                 if (bmcr & BMCR_ANENABLE) {
4043                         u32 common;
4044
4045                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4046                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4047                         common = local_adv & remote_adv;
4048                         if (common & (ADVERTISE_1000XHALF |
4049                                       ADVERTISE_1000XFULL)) {
4050                                 if (common & ADVERTISE_1000XFULL)
4051                                         current_duplex = DUPLEX_FULL;
4052                                 else
4053                                         current_duplex = DUPLEX_HALF;
4054                         }
4055                         else
4056                                 current_link_up = 0;
4057                 }
4058         }
4059
4060         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4061                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4062
4063         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4064         if (tp->link_config.active_duplex == DUPLEX_HALF)
4065                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4066
4067         tw32_f(MAC_MODE, tp->mac_mode);
4068         udelay(40);
4069
4070         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4071
4072         tp->link_config.active_speed = current_speed;
4073         tp->link_config.active_duplex = current_duplex;
4074
4075         if (current_link_up != netif_carrier_ok(tp->dev)) {
4076                 if (current_link_up)
4077                         netif_carrier_on(tp->dev);
4078                 else {
4079                         netif_carrier_off(tp->dev);
4080                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4081                 }
4082                 tg3_link_report(tp);
4083         }
4084         return err;
4085 }
4086
4087 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4088 {
4089         if (tp->serdes_counter) {
4090                 /* Give autoneg time to complete. */
4091                 tp->serdes_counter--;
4092                 return;
4093         }
4094         if (!netif_carrier_ok(tp->dev) &&
4095             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4096                 u32 bmcr;
4097
4098                 tg3_readphy(tp, MII_BMCR, &bmcr);
4099                 if (bmcr & BMCR_ANENABLE) {
4100                         u32 phy1, phy2;
4101
4102                         /* Select shadow register 0x1f */
4103                         tg3_writephy(tp, 0x1c, 0x7c00);
4104                         tg3_readphy(tp, 0x1c, &phy1);
4105
4106                         /* Select expansion interrupt status register */
4107                         tg3_writephy(tp, 0x17, 0x0f01);
4108                         tg3_readphy(tp, 0x15, &phy2);
4109                         tg3_readphy(tp, 0x15, &phy2);
4110
4111                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4112                                 /* We have signal detect and not receiving
4113                                  * config code words, link is up by parallel
4114                                  * detection.
4115                                  */
4116
4117                                 bmcr &= ~BMCR_ANENABLE;
4118                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4119                                 tg3_writephy(tp, MII_BMCR, bmcr);
4120                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4121                         }
4122                 }
4123         }
4124         else if (netif_carrier_ok(tp->dev) &&
4125                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4126                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4127                 u32 phy2;
4128
4129                 /* Select expansion interrupt status register */
4130                 tg3_writephy(tp, 0x17, 0x0f01);
4131                 tg3_readphy(tp, 0x15, &phy2);
4132                 if (phy2 & 0x20) {
4133                         u32 bmcr;
4134
4135                         /* Config code words received, turn on autoneg. */
4136                         tg3_readphy(tp, MII_BMCR, &bmcr);
4137                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4138
4139                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4140
4141                 }
4142         }
4143 }
4144
4145 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4146 {
4147         int err;
4148
4149         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4150                 err = tg3_setup_fiber_phy(tp, force_reset);
4151         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4152                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4153         } else {
4154                 err = tg3_setup_copper_phy(tp, force_reset);
4155         }
4156
4157         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4158                 u32 val, scale;
4159
4160                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4161                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4162                         scale = 65;
4163                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4164                         scale = 6;
4165                 else
4166                         scale = 12;
4167
4168                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4169                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4170                 tw32(GRC_MISC_CFG, val);
4171         }
4172
4173         if (tp->link_config.active_speed == SPEED_1000 &&
4174             tp->link_config.active_duplex == DUPLEX_HALF)
4175                 tw32(MAC_TX_LENGTHS,
4176                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4177                       (6 << TX_LENGTHS_IPG_SHIFT) |
4178                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4179         else
4180                 tw32(MAC_TX_LENGTHS,
4181                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4182                       (6 << TX_LENGTHS_IPG_SHIFT) |
4183                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4184
4185         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4186                 if (netif_carrier_ok(tp->dev)) {
4187                         tw32(HOSTCC_STAT_COAL_TICKS,
4188                              tp->coal.stats_block_coalesce_usecs);
4189                 } else {
4190                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4191                 }
4192         }
4193
4194         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4195                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4196                 if (!netif_carrier_ok(tp->dev))
4197                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4198                               tp->pwrmgmt_thresh;
4199                 else
4200                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4201                 tw32(PCIE_PWR_MGMT_THRESH, val);
4202         }
4203
4204         return err;
4205 }
4206
4207 /* This is called whenever we suspect that the system chipset is re-
4208  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4209  * is bogus tx completions. We try to recover by setting the
4210  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4211  * in the workqueue.
4212  */
4213 static void tg3_tx_recover(struct tg3 *tp)
4214 {
4215         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4216                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4217
4218         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4219                "mapped I/O cycles to the network device, attempting to "
4220                "recover. Please report the problem to the driver maintainer "
4221                "and include system chipset information.\n", tp->dev->name);
4222
4223         spin_lock(&tp->lock);
4224         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4225         spin_unlock(&tp->lock);
4226 }
4227
4228 static inline u32 tg3_tx_avail(struct tg3 *tp)
4229 {
4230         smp_mb();
4231         return (tp->tx_pending -
4232                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4233 }
4234
4235 /* Tigon3 never reports partial packet sends.  So we do not
4236  * need special logic to handle SKBs that have not had all
4237  * of their frags sent yet, like SunGEM does.
4238  */
4239 static void tg3_tx(struct tg3 *tp)
4240 {
4241         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4242         u32 sw_idx = tp->tx_cons;
4243
4244         while (sw_idx != hw_idx) {
4245                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4246                 struct sk_buff *skb = ri->skb;
4247                 int i, tx_bug = 0;
4248
4249                 if (unlikely(skb == NULL)) {
4250                         tg3_tx_recover(tp);
4251                         return;
4252                 }
4253
4254                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4255
4256                 ri->skb = NULL;
4257
4258                 sw_idx = NEXT_TX(sw_idx);
4259
4260                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4261                         ri = &tp->tx_buffers[sw_idx];
4262                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4263                                 tx_bug = 1;
4264                         sw_idx = NEXT_TX(sw_idx);
4265                 }
4266
4267                 dev_kfree_skb(skb);
4268
4269                 if (unlikely(tx_bug)) {
4270                         tg3_tx_recover(tp);
4271                         return;
4272                 }
4273         }
4274
4275         tp->tx_cons = sw_idx;
4276
4277         /* Need to make the tx_cons update visible to tg3_start_xmit()
4278          * before checking for netif_queue_stopped().  Without the
4279          * memory barrier, there is a small possibility that tg3_start_xmit()
4280          * will miss it and cause the queue to be stopped forever.
4281          */
4282         smp_mb();
4283
4284         if (unlikely(netif_queue_stopped(tp->dev) &&
4285                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4286                 netif_tx_lock(tp->dev);
4287                 if (netif_queue_stopped(tp->dev) &&
4288                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4289                         netif_wake_queue(tp->dev);
4290                 netif_tx_unlock(tp->dev);
4291         }
4292 }
4293
4294 /* Returns size of skb allocated or < 0 on error.
4295  *
4296  * We only need to fill in the address because the other members
4297  * of the RX descriptor are invariant, see tg3_init_rings.
4298  *
4299  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4300  * posting buffers we only dirty the first cache line of the RX
4301  * descriptor (containing the address).  Whereas for the RX status
4302  * buffers the cpu only reads the last cacheline of the RX descriptor
4303  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4304  */
4305 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4306                             int src_idx, u32 dest_idx_unmasked)
4307 {
4308         struct tg3_rx_buffer_desc *desc;
4309         struct ring_info *map, *src_map;
4310         struct sk_buff *skb;
4311         dma_addr_t mapping;
4312         int skb_size, dest_idx;
4313
4314         src_map = NULL;
4315         switch (opaque_key) {
4316         case RXD_OPAQUE_RING_STD:
4317                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4318                 desc = &tp->rx_std[dest_idx];
4319                 map = &tp->rx_std_buffers[dest_idx];
4320                 if (src_idx >= 0)
4321                         src_map = &tp->rx_std_buffers[src_idx];
4322                 skb_size = tp->rx_pkt_buf_sz;
4323                 break;
4324
4325         case RXD_OPAQUE_RING_JUMBO:
4326                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4327                 desc = &tp->rx_jumbo[dest_idx];
4328                 map = &tp->rx_jumbo_buffers[dest_idx];
4329                 if (src_idx >= 0)
4330                         src_map = &tp->rx_jumbo_buffers[src_idx];
4331                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4332                 break;
4333
4334         default:
4335                 return -EINVAL;
4336         }
4337
4338         /* Do not overwrite any of the map or rp information
4339          * until we are sure we can commit to a new buffer.
4340          *
4341          * Callers depend upon this behavior and assume that
4342          * we leave everything unchanged if we fail.
4343          */
4344         skb = netdev_alloc_skb(tp->dev, skb_size);
4345         if (skb == NULL)
4346                 return -ENOMEM;
4347
4348         skb_reserve(skb, tp->rx_offset);
4349
4350         mapping = pci_map_single(tp->pdev, skb->data,
4351                                  skb_size - tp->rx_offset,
4352                                  PCI_DMA_FROMDEVICE);
4353
4354         map->skb = skb;
4355         pci_unmap_addr_set(map, mapping, mapping);
4356
4357         if (src_map != NULL)
4358                 src_map->skb = NULL;
4359
4360         desc->addr_hi = ((u64)mapping >> 32);
4361         desc->addr_lo = ((u64)mapping & 0xffffffff);
4362
4363         return skb_size;
4364 }
4365
4366 /* We only need to move over in the address because the other
4367  * members of the RX descriptor are invariant.  See notes above
4368  * tg3_alloc_rx_skb for full details.
4369  */
4370 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4371                            int src_idx, u32 dest_idx_unmasked)
4372 {
4373         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4374         struct ring_info *src_map, *dest_map;
4375         int dest_idx;
4376
4377         switch (opaque_key) {
4378         case RXD_OPAQUE_RING_STD:
4379                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4380                 dest_desc = &tp->rx_std[dest_idx];
4381                 dest_map = &tp->rx_std_buffers[dest_idx];
4382                 src_desc = &tp->rx_std[src_idx];
4383                 src_map = &tp->rx_std_buffers[src_idx];
4384                 break;
4385
4386         case RXD_OPAQUE_RING_JUMBO:
4387                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4388                 dest_desc = &tp->rx_jumbo[dest_idx];
4389                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4390                 src_desc = &tp->rx_jumbo[src_idx];
4391                 src_map = &tp->rx_jumbo_buffers[src_idx];
4392                 break;
4393
4394         default:
4395                 return;
4396         }
4397
4398         dest_map->skb = src_map->skb;
4399         pci_unmap_addr_set(dest_map, mapping,
4400                            pci_unmap_addr(src_map, mapping));
4401         dest_desc->addr_hi = src_desc->addr_hi;
4402         dest_desc->addr_lo = src_desc->addr_lo;
4403
4404         src_map->skb = NULL;
4405 }
4406
4407 #if TG3_VLAN_TAG_USED
4408 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4409 {
4410         return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4411 }
4412 #endif
4413
4414 /* The RX ring scheme is composed of multiple rings which post fresh
4415  * buffers to the chip, and one special ring the chip uses to report
4416  * status back to the host.
4417  *
4418  * The special ring reports the status of received packets to the
4419  * host.  The chip does not write into the original descriptor the
4420  * RX buffer was obtained from.  The chip simply takes the original
4421  * descriptor as provided by the host, updates the status and length
4422  * field, then writes this into the next status ring entry.
4423  *
4424  * Each ring the host uses to post buffers to the chip is described
4425  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4426  * it is first placed into the on-chip ram.  When the packet's length
4427  * is known, it walks down the TG3_BDINFO entries to select the ring.
4428  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4429  * which is within the range of the new packet's length is chosen.
4430  *
4431  * The "separate ring for rx status" scheme may sound queer, but it makes
4432  * sense from a cache coherency perspective.  If only the host writes
4433  * to the buffer post rings, and only the chip writes to the rx status
4434  * rings, then cache lines never move beyond shared-modified state.
4435  * If both the host and chip were to write into the same ring, cache line
4436  * eviction could occur since both entities want it in an exclusive state.
4437  */
4438 static int tg3_rx(struct tg3 *tp, int budget)
4439 {
4440         u32 work_mask, rx_std_posted = 0;
4441         u32 sw_idx = tp->rx_rcb_ptr;
4442         u16 hw_idx;
4443         int received;
4444
4445         hw_idx = tp->hw_status->idx[0].rx_producer;
4446         /*
4447          * We need to order the read of hw_idx and the read of
4448          * the opaque cookie.
4449          */
4450         rmb();
4451         work_mask = 0;
4452         received = 0;
4453         while (sw_idx != hw_idx && budget > 0) {
4454                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4455                 unsigned int len;
4456                 struct sk_buff *skb;
4457                 dma_addr_t dma_addr;
4458                 u32 opaque_key, desc_idx, *post_ptr;
4459
4460                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4461                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4462                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4463                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4464                                                   mapping);
4465                         skb = tp->rx_std_buffers[desc_idx].skb;
4466                         post_ptr = &tp->rx_std_ptr;
4467                         rx_std_posted++;
4468                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4469                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4470                                                   mapping);
4471                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4472                         post_ptr = &tp->rx_jumbo_ptr;
4473                 }
4474                 else {
4475                         goto next_pkt_nopost;
4476                 }
4477
4478                 work_mask |= opaque_key;
4479
4480                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4481                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4482                 drop_it:
4483                         tg3_recycle_rx(tp, opaque_key,
4484                                        desc_idx, *post_ptr);
4485                 drop_it_no_recycle:
4486                         /* Other statistics kept track of by card. */
4487                         tp->net_stats.rx_dropped++;
4488                         goto next_pkt;
4489                 }
4490
4491                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4492                       ETH_FCS_LEN;
4493
4494                 if (len > RX_COPY_THRESHOLD
4495                         && tp->rx_offset == NET_IP_ALIGN
4496                         /* rx_offset will likely not equal NET_IP_ALIGN
4497                          * if this is a 5701 card running in PCI-X mode
4498                          * [see tg3_get_invariants()]
4499                          */
4500                 ) {
4501                         int skb_size;
4502
4503                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4504                                                     desc_idx, *post_ptr);
4505                         if (skb_size < 0)
4506                                 goto drop_it;
4507
4508                         pci_unmap_single(tp->pdev, dma_addr,
4509                                          skb_size - tp->rx_offset,
4510                                          PCI_DMA_FROMDEVICE);
4511
4512                         skb_put(skb, len);
4513                 } else {
4514                         struct sk_buff *copy_skb;
4515
4516                         tg3_recycle_rx(tp, opaque_key,
4517                                        desc_idx, *post_ptr);
4518
4519                         copy_skb = netdev_alloc_skb(tp->dev,
4520                                                     len + TG3_RAW_IP_ALIGN);
4521                         if (copy_skb == NULL)
4522                                 goto drop_it_no_recycle;
4523
4524                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4525                         skb_put(copy_skb, len);
4526                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4527                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4528                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4529
4530                         /* We'll reuse the original ring buffer. */
4531                         skb = copy_skb;
4532                 }
4533
4534                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4535                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4536                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4537                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4538                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4539                 else
4540                         skb->ip_summed = CHECKSUM_NONE;
4541
4542                 skb->protocol = eth_type_trans(skb, tp->dev);
4543
4544                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4545                     skb->protocol != htons(ETH_P_8021Q)) {
4546                         dev_kfree_skb(skb);
4547                         goto next_pkt;
4548                 }
4549
4550 #if TG3_VLAN_TAG_USED
4551                 if (tp->vlgrp != NULL &&
4552                     desc->type_flags & RXD_FLAG_VLAN) {
4553                         tg3_vlan_rx(tp, skb,
4554                                     desc->err_vlan & RXD_VLAN_MASK);
4555                 } else
4556 #endif
4557                         napi_gro_receive(&tp->napi, skb);
4558
4559                 received++;
4560                 budget--;
4561
4562 next_pkt:
4563                 (*post_ptr)++;
4564
4565                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4566                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4567
4568                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4569                                      TG3_64BIT_REG_LOW, idx);
4570                         work_mask &= ~RXD_OPAQUE_RING_STD;
4571                         rx_std_posted = 0;
4572                 }
4573 next_pkt_nopost:
4574                 sw_idx++;
4575                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4576
4577                 /* Refresh hw_idx to see if there is new work */
4578                 if (sw_idx == hw_idx) {
4579                         hw_idx = tp->hw_status->idx[0].rx_producer;
4580                         rmb();
4581                 }
4582         }
4583
4584         /* ACK the status ring. */
4585         tp->rx_rcb_ptr = sw_idx;
4586         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4587
4588         /* Refill RX ring(s). */
4589         if (work_mask & RXD_OPAQUE_RING_STD) {
4590                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4591                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4592                              sw_idx);
4593         }
4594         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4595                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4596                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4597                              sw_idx);
4598         }
4599         mmiowb();
4600
4601         return received;
4602 }
4603
4604 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4605 {
4606         struct tg3_hw_status *sblk = tp->hw_status;
4607
4608         /* handle link change and other phy events */
4609         if (!(tp->tg3_flags &
4610               (TG3_FLAG_USE_LINKCHG_REG |
4611                TG3_FLAG_POLL_SERDES))) {
4612                 if (sblk->status & SD_STATUS_LINK_CHG) {
4613                         sblk->status = SD_STATUS_UPDATED |
4614                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4615                         spin_lock(&tp->lock);
4616                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4617                                 tw32_f(MAC_STATUS,
4618                                      (MAC_STATUS_SYNC_CHANGED |
4619                                       MAC_STATUS_CFG_CHANGED |
4620                                       MAC_STATUS_MI_COMPLETION |
4621                                       MAC_STATUS_LNKSTATE_CHANGED));
4622                                 udelay(40);
4623                         } else
4624                                 tg3_setup_phy(tp, 0);
4625                         spin_unlock(&tp->lock);
4626                 }
4627         }
4628
4629         /* run TX completion thread */
4630         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4631                 tg3_tx(tp);
4632                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4633                         return work_done;
4634         }
4635
4636         /* run RX thread, within the bounds set by NAPI.
4637          * All RX "locking" is done by ensuring outside
4638          * code synchronizes with tg3->napi.poll()
4639          */
4640         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4641                 work_done += tg3_rx(tp, budget - work_done);
4642
4643         return work_done;
4644 }
4645
4646 static int tg3_poll(struct napi_struct *napi, int budget)
4647 {
4648         struct tg3 *tp = container_of(napi, struct tg3, napi);
4649         int work_done = 0;
4650         struct tg3_hw_status *sblk = tp->hw_status;
4651
4652         while (1) {
4653                 work_done = tg3_poll_work(tp, work_done, budget);
4654
4655                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4656                         goto tx_recovery;
4657
4658                 if (unlikely(work_done >= budget))
4659                         break;
4660
4661                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4662                         /* tp->last_tag is used in tg3_restart_ints() below
4663                          * to tell the hw how much work has been processed,
4664                          * so we must read it before checking for more work.
4665                          */
4666                         tp->last_tag = sblk->status_tag;
4667                         tp->last_irq_tag = tp->last_tag;
4668                         rmb();
4669                 } else
4670                         sblk->status &= ~SD_STATUS_UPDATED;
4671
4672                 if (likely(!tg3_has_work(tp))) {
4673                         napi_complete(napi);
4674                         tg3_restart_ints(tp);
4675                         break;
4676                 }
4677         }
4678
4679         return work_done;
4680
4681 tx_recovery:
4682         /* work_done is guaranteed to be less than budget. */
4683         napi_complete(napi);
4684         schedule_work(&tp->reset_task);
4685         return work_done;
4686 }
4687
4688 static void tg3_irq_quiesce(struct tg3 *tp)
4689 {
4690         BUG_ON(tp->irq_sync);
4691
4692         tp->irq_sync = 1;
4693         smp_mb();
4694
4695         synchronize_irq(tp->pdev->irq);
4696 }
4697
4698 static inline int tg3_irq_sync(struct tg3 *tp)
4699 {
4700         return tp->irq_sync;
4701 }
4702
4703 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4704  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4705  * with as well.  Most of the time, this is not necessary except when
4706  * shutting down the device.
4707  */
4708 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4709 {
4710         spin_lock_bh(&tp->lock);
4711         if (irq_sync)
4712                 tg3_irq_quiesce(tp);
4713 }
4714
4715 static inline void tg3_full_unlock(struct tg3 *tp)
4716 {
4717         spin_unlock_bh(&tp->lock);
4718 }
4719
4720 /* One-shot MSI handler - Chip automatically disables interrupt
4721  * after sending MSI so driver doesn't have to do it.
4722  */
4723 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4724 {
4725         struct net_device *dev = dev_id;
4726         struct tg3 *tp = netdev_priv(dev);
4727
4728         prefetch(tp->hw_status);
4729         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4730
4731         if (likely(!tg3_irq_sync(tp)))
4732                 napi_schedule(&tp->napi);
4733
4734         return IRQ_HANDLED;
4735 }
4736
4737 /* MSI ISR - No need to check for interrupt sharing and no need to
4738  * flush status block and interrupt mailbox. PCI ordering rules
4739  * guarantee that MSI will arrive after the status block.
4740  */
4741 static irqreturn_t tg3_msi(int irq, void *dev_id)
4742 {
4743         struct net_device *dev = dev_id;
4744         struct tg3 *tp = netdev_priv(dev);
4745
4746         prefetch(tp->hw_status);
4747         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4748         /*
4749          * Writing any value to intr-mbox-0 clears PCI INTA# and
4750          * chip-internal interrupt pending events.
4751          * Writing non-zero to intr-mbox-0 additional tells the
4752          * NIC to stop sending us irqs, engaging "in-intr-handler"
4753          * event coalescing.
4754          */
4755         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4756         if (likely(!tg3_irq_sync(tp)))
4757                 napi_schedule(&tp->napi);
4758
4759         return IRQ_RETVAL(1);
4760 }
4761
4762 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4763 {
4764         struct net_device *dev = dev_id;
4765         struct tg3 *tp = netdev_priv(dev);
4766         struct tg3_hw_status *sblk = tp->hw_status;
4767         unsigned int handled = 1;
4768
4769         /* In INTx mode, it is possible for the interrupt to arrive at
4770          * the CPU before the status block posted prior to the interrupt.
4771          * Reading the PCI State register will confirm whether the
4772          * interrupt is ours and will flush the status block.
4773          */
4774         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4775                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4776                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4777                         handled = 0;
4778                         goto out;
4779                 }
4780         }
4781
4782         /*
4783          * Writing any value to intr-mbox-0 clears PCI INTA# and
4784          * chip-internal interrupt pending events.
4785          * Writing non-zero to intr-mbox-0 additional tells the
4786          * NIC to stop sending us irqs, engaging "in-intr-handler"
4787          * event coalescing.
4788          *
4789          * Flush the mailbox to de-assert the IRQ immediately to prevent
4790          * spurious interrupts.  The flush impacts performance but
4791          * excessive spurious interrupts can be worse in some cases.
4792          */
4793         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4794         if (tg3_irq_sync(tp))
4795                 goto out;
4796         sblk->status &= ~SD_STATUS_UPDATED;
4797         if (likely(tg3_has_work(tp))) {
4798                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4799                 napi_schedule(&tp->napi);
4800         } else {
4801                 /* No work, shared interrupt perhaps?  re-enable
4802                  * interrupts, and flush that PCI write
4803                  */
4804                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4805                                0x00000000);
4806         }
4807 out:
4808         return IRQ_RETVAL(handled);
4809 }
4810
4811 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4812 {
4813         struct net_device *dev = dev_id;
4814         struct tg3 *tp = netdev_priv(dev);
4815         struct tg3_hw_status *sblk = tp->hw_status;
4816         unsigned int handled = 1;
4817
4818         /* In INTx mode, it is possible for the interrupt to arrive at
4819          * the CPU before the status block posted prior to the interrupt.
4820          * Reading the PCI State register will confirm whether the
4821          * interrupt is ours and will flush the status block.
4822          */
4823         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4824                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4825                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4826                         handled = 0;
4827                         goto out;
4828                 }
4829         }
4830
4831         /*
4832          * writing any value to intr-mbox-0 clears PCI INTA# and
4833          * chip-internal interrupt pending events.
4834          * writing non-zero to intr-mbox-0 additional tells the
4835          * NIC to stop sending us irqs, engaging "in-intr-handler"
4836          * event coalescing.
4837          *
4838          * Flush the mailbox to de-assert the IRQ immediately to prevent
4839          * spurious interrupts.  The flush impacts performance but
4840          * excessive spurious interrupts can be worse in some cases.
4841          */
4842         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4843
4844         /*
4845          * In a shared interrupt configuration, sometimes other devices'
4846          * interrupts will scream.  We record the current status tag here
4847          * so that the above check can report that the screaming interrupts
4848          * are unhandled.  Eventually they will be silenced.
4849          */
4850         tp->last_irq_tag = sblk->status_tag;
4851
4852         if (tg3_irq_sync(tp))
4853                 goto out;
4854
4855         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4856
4857         napi_schedule(&tp->napi);
4858
4859 out:
4860         return IRQ_RETVAL(handled);
4861 }
4862
4863 /* ISR for interrupt test */
4864 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4865 {
4866         struct net_device *dev = dev_id;
4867         struct tg3 *tp = netdev_priv(dev);
4868         struct tg3_hw_status *sblk = tp->hw_status;
4869
4870         if ((sblk->status & SD_STATUS_UPDATED) ||
4871             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4872                 tg3_disable_ints(tp);
4873                 return IRQ_RETVAL(1);
4874         }
4875         return IRQ_RETVAL(0);
4876 }
4877
4878 static int tg3_init_hw(struct tg3 *, int);
4879 static int tg3_halt(struct tg3 *, int, int);
4880
4881 /* Restart hardware after configuration changes, self-test, etc.
4882  * Invoked with tp->lock held.
4883  */
4884 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4885         __releases(tp->lock)
4886         __acquires(tp->lock)
4887 {
4888         int err;
4889
4890         err = tg3_init_hw(tp, reset_phy);
4891         if (err) {
4892                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4893                        "aborting.\n", tp->dev->name);
4894                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4895                 tg3_full_unlock(tp);
4896                 del_timer_sync(&tp->timer);
4897                 tp->irq_sync = 0;
4898                 napi_enable(&tp->napi);
4899                 dev_close(tp->dev);
4900                 tg3_full_lock(tp, 0);
4901         }
4902         return err;
4903 }
4904
4905 #ifdef CONFIG_NET_POLL_CONTROLLER
4906 static void tg3_poll_controller(struct net_device *dev)
4907 {
4908         struct tg3 *tp = netdev_priv(dev);
4909
4910         tg3_interrupt(tp->pdev->irq, dev);
4911 }
4912 #endif
4913
4914 static void tg3_reset_task(struct work_struct *work)
4915 {
4916         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4917         int err;
4918         unsigned int restart_timer;
4919
4920         tg3_full_lock(tp, 0);
4921
4922         if (!netif_running(tp->dev)) {
4923                 tg3_full_unlock(tp);
4924                 return;
4925         }
4926
4927         tg3_full_unlock(tp);
4928
4929         tg3_phy_stop(tp);
4930
4931         tg3_netif_stop(tp);
4932
4933         tg3_full_lock(tp, 1);
4934
4935         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4936         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4937
4938         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4939                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4940                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4941                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4942                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4943         }
4944
4945         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4946         err = tg3_init_hw(tp, 1);
4947         if (err)
4948                 goto out;
4949
4950         tg3_netif_start(tp);
4951
4952         if (restart_timer)
4953                 mod_timer(&tp->timer, jiffies + 1);
4954
4955 out:
4956         tg3_full_unlock(tp);
4957
4958         if (!err)
4959                 tg3_phy_start(tp);
4960 }
4961
4962 static void tg3_dump_short_state(struct tg3 *tp)
4963 {
4964         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4965                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4966         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4967                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4968 }
4969
4970 static void tg3_tx_timeout(struct net_device *dev)
4971 {
4972         struct tg3 *tp = netdev_priv(dev);
4973
4974         if (netif_msg_tx_err(tp)) {
4975                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4976                        dev->name);
4977                 tg3_dump_short_state(tp);
4978         }
4979
4980         schedule_work(&tp->reset_task);
4981 }
4982
4983 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4984 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4985 {
4986         u32 base = (u32) mapping & 0xffffffff;
4987
4988         return ((base > 0xffffdcc0) &&
4989                 (base + len + 8 < base));
4990 }
4991
4992 /* Test for DMA addresses > 40-bit */
4993 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4994                                           int len)
4995 {
4996 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4997         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4998                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
4999         return 0;
5000 #else
5001         return 0;
5002 #endif
5003 }
5004
5005 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5006
5007 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5008 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5009                                        u32 last_plus_one, u32 *start,
5010                                        u32 base_flags, u32 mss)
5011 {
5012         struct sk_buff *new_skb;
5013         dma_addr_t new_addr = 0;
5014         u32 entry = *start;
5015         int i, ret = 0;
5016
5017         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5018                 new_skb = skb_copy(skb, GFP_ATOMIC);
5019         else {
5020                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5021
5022                 new_skb = skb_copy_expand(skb,
5023                                           skb_headroom(skb) + more_headroom,
5024                                           skb_tailroom(skb), GFP_ATOMIC);
5025         }
5026
5027         if (!new_skb) {
5028                 ret = -1;
5029         } else {
5030                 /* New SKB is guaranteed to be linear. */
5031                 entry = *start;
5032                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5033                 new_addr = skb_shinfo(new_skb)->dma_head;
5034
5035                 /* Make sure new skb does not cross any 4G boundaries.
5036                  * Drop the packet if it does.
5037                  */
5038                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5039                         if (!ret)
5040                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5041                                               DMA_TO_DEVICE);
5042                         ret = -1;
5043                         dev_kfree_skb(new_skb);
5044                         new_skb = NULL;
5045                 } else {
5046                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5047                                     base_flags, 1 | (mss << 1));
5048                         *start = NEXT_TX(entry);
5049                 }
5050         }
5051
5052         /* Now clean up the sw ring entries. */
5053         i = 0;
5054         while (entry != last_plus_one) {
5055                 if (i == 0) {
5056                         tp->tx_buffers[entry].skb = new_skb;
5057                 } else {
5058                         tp->tx_buffers[entry].skb = NULL;
5059                 }
5060                 entry = NEXT_TX(entry);
5061                 i++;
5062         }
5063
5064         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5065         dev_kfree_skb(skb);
5066
5067         return ret;
5068 }
5069
5070 static void tg3_set_txd(struct tg3 *tp, int entry,
5071                         dma_addr_t mapping, int len, u32 flags,
5072                         u32 mss_and_is_end)
5073 {
5074         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5075         int is_end = (mss_and_is_end & 0x1);
5076         u32 mss = (mss_and_is_end >> 1);
5077         u32 vlan_tag = 0;
5078
5079         if (is_end)
5080                 flags |= TXD_FLAG_END;
5081         if (flags & TXD_FLAG_VLAN) {
5082                 vlan_tag = flags >> 16;
5083                 flags &= 0xffff;
5084         }
5085         vlan_tag |= (mss << TXD_MSS_SHIFT);
5086
5087         txd->addr_hi = ((u64) mapping >> 32);
5088         txd->addr_lo = ((u64) mapping & 0xffffffff);
5089         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5090         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5091 }
5092
5093 /* hard_start_xmit for devices that don't have any bugs and
5094  * support TG3_FLG2_HW_TSO_2 only.
5095  */
5096 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5097 {
5098         struct tg3 *tp = netdev_priv(dev);
5099         u32 len, entry, base_flags, mss;
5100         struct skb_shared_info *sp;
5101         dma_addr_t mapping;
5102
5103         len = skb_headlen(skb);
5104
5105         /* We are running in BH disabled context with netif_tx_lock
5106          * and TX reclaim runs via tp->napi.poll inside of a software
5107          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5108          * no IRQ context deadlocks to worry about either.  Rejoice!
5109          */
5110         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5111                 if (!netif_queue_stopped(dev)) {
5112                         netif_stop_queue(dev);
5113
5114                         /* This is a hard error, log it. */
5115                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5116                                "queue awake!\n", dev->name);
5117                 }
5118                 return NETDEV_TX_BUSY;
5119         }
5120
5121         entry = tp->tx_prod;
5122         base_flags = 0;
5123         mss = 0;
5124         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5125                 int tcp_opt_len, ip_tcp_len;
5126
5127                 if (skb_header_cloned(skb) &&
5128                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5129                         dev_kfree_skb(skb);
5130                         goto out_unlock;
5131                 }
5132
5133                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5134                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5135                 else {
5136                         struct iphdr *iph = ip_hdr(skb);
5137
5138                         tcp_opt_len = tcp_optlen(skb);
5139                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5140
5141                         iph->check = 0;
5142                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5143                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5144                 }
5145
5146                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5147                                TXD_FLAG_CPU_POST_DMA);
5148
5149                 tcp_hdr(skb)->check = 0;
5150
5151         }
5152         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5153                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5154 #if TG3_VLAN_TAG_USED
5155         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5156                 base_flags |= (TXD_FLAG_VLAN |
5157                                (vlan_tx_tag_get(skb) << 16));
5158 #endif
5159
5160         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5161                 dev_kfree_skb(skb);
5162                 goto out_unlock;
5163         }
5164
5165         sp = skb_shinfo(skb);
5166
5167         mapping = sp->dma_head;
5168
5169         tp->tx_buffers[entry].skb = skb;
5170
5171         tg3_set_txd(tp, entry, mapping, len, base_flags,
5172                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5173
5174         entry = NEXT_TX(entry);
5175
5176         /* Now loop through additional data fragments, and queue them. */
5177         if (skb_shinfo(skb)->nr_frags > 0) {
5178                 unsigned int i, last;
5179
5180                 last = skb_shinfo(skb)->nr_frags - 1;
5181                 for (i = 0; i <= last; i++) {
5182                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5183
5184                         len = frag->size;
5185                         mapping = sp->dma_maps[i];
5186                         tp->tx_buffers[entry].skb = NULL;
5187
5188                         tg3_set_txd(tp, entry, mapping, len,
5189                                     base_flags, (i == last) | (mss << 1));
5190
5191                         entry = NEXT_TX(entry);
5192                 }
5193         }
5194
5195         /* Packets are ready, update Tx producer idx local and on card. */
5196         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5197
5198         tp->tx_prod = entry;
5199         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5200                 netif_stop_queue(dev);
5201                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5202                         netif_wake_queue(tp->dev);
5203         }
5204
5205 out_unlock:
5206         mmiowb();
5207
5208         return NETDEV_TX_OK;
5209 }
5210
5211 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5212
5213 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5214  * TSO header is greater than 80 bytes.
5215  */
5216 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5217 {
5218         struct sk_buff *segs, *nskb;
5219
5220         /* Estimate the number of fragments in the worst case */
5221         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5222                 netif_stop_queue(tp->dev);
5223                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5224                         return NETDEV_TX_BUSY;
5225
5226                 netif_wake_queue(tp->dev);
5227         }
5228
5229         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5230         if (IS_ERR(segs))
5231                 goto tg3_tso_bug_end;
5232
5233         do {
5234                 nskb = segs;
5235                 segs = segs->next;
5236                 nskb->next = NULL;
5237                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5238         } while (segs);
5239
5240 tg3_tso_bug_end:
5241         dev_kfree_skb(skb);
5242
5243         return NETDEV_TX_OK;
5244 }
5245
5246 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5247  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5248  */
5249 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5250 {
5251         struct tg3 *tp = netdev_priv(dev);
5252         u32 len, entry, base_flags, mss;
5253         struct skb_shared_info *sp;
5254         int would_hit_hwbug;
5255         dma_addr_t mapping;
5256
5257         len = skb_headlen(skb);
5258
5259         /* We are running in BH disabled context with netif_tx_lock
5260          * and TX reclaim runs via tp->napi.poll inside of a software
5261          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5262          * no IRQ context deadlocks to worry about either.  Rejoice!
5263          */
5264         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5265                 if (!netif_queue_stopped(dev)) {
5266                         netif_stop_queue(dev);
5267
5268                         /* This is a hard error, log it. */
5269                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5270                                "queue awake!\n", dev->name);
5271                 }
5272                 return NETDEV_TX_BUSY;
5273         }
5274
5275         entry = tp->tx_prod;
5276         base_flags = 0;
5277         if (skb->ip_summed == CHECKSUM_PARTIAL)
5278                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5279         mss = 0;
5280         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5281                 struct iphdr *iph;
5282                 int tcp_opt_len, ip_tcp_len, hdr_len;
5283
5284                 if (skb_header_cloned(skb) &&
5285                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5286                         dev_kfree_skb(skb);
5287                         goto out_unlock;
5288                 }
5289
5290                 tcp_opt_len = tcp_optlen(skb);
5291                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5292
5293                 hdr_len = ip_tcp_len + tcp_opt_len;
5294                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5295                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5296                         return (tg3_tso_bug(tp, skb));
5297
5298                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5299                                TXD_FLAG_CPU_POST_DMA);
5300
5301                 iph = ip_hdr(skb);
5302                 iph->check = 0;
5303                 iph->tot_len = htons(mss + hdr_len);
5304                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5305                         tcp_hdr(skb)->check = 0;
5306                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5307                 } else
5308                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5309                                                                  iph->daddr, 0,
5310                                                                  IPPROTO_TCP,
5311                                                                  0);
5312
5313                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5314                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5315                         if (tcp_opt_len || iph->ihl > 5) {
5316                                 int tsflags;
5317
5318                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5319                                 mss |= (tsflags << 11);
5320                         }
5321                 } else {
5322                         if (tcp_opt_len || iph->ihl > 5) {
5323                                 int tsflags;
5324
5325                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5326                                 base_flags |= tsflags << 12;
5327                         }
5328                 }
5329         }
5330 #if TG3_VLAN_TAG_USED
5331         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5332                 base_flags |= (TXD_FLAG_VLAN |
5333                                (vlan_tx_tag_get(skb) << 16));
5334 #endif
5335
5336         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5337                 dev_kfree_skb(skb);
5338                 goto out_unlock;
5339         }
5340
5341         sp = skb_shinfo(skb);
5342
5343         mapping = sp->dma_head;
5344
5345         tp->tx_buffers[entry].skb = skb;
5346
5347         would_hit_hwbug = 0;
5348
5349         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5350                 would_hit_hwbug = 1;
5351         else if (tg3_4g_overflow_test(mapping, len))
5352                 would_hit_hwbug = 1;
5353
5354         tg3_set_txd(tp, entry, mapping, len, base_flags,
5355                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5356
5357         entry = NEXT_TX(entry);
5358
5359         /* Now loop through additional data fragments, and queue them. */
5360         if (skb_shinfo(skb)->nr_frags > 0) {
5361                 unsigned int i, last;
5362
5363                 last = skb_shinfo(skb)->nr_frags - 1;
5364                 for (i = 0; i <= last; i++) {
5365                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5366
5367                         len = frag->size;
5368                         mapping = sp->dma_maps[i];
5369
5370                         tp->tx_buffers[entry].skb = NULL;
5371
5372                         if (tg3_4g_overflow_test(mapping, len))
5373                                 would_hit_hwbug = 1;
5374
5375                         if (tg3_40bit_overflow_test(tp, mapping, len))
5376                                 would_hit_hwbug = 1;
5377
5378                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5379                                 tg3_set_txd(tp, entry, mapping, len,
5380                                             base_flags, (i == last)|(mss << 1));
5381                         else
5382                                 tg3_set_txd(tp, entry, mapping, len,
5383                                             base_flags, (i == last));
5384
5385                         entry = NEXT_TX(entry);
5386                 }
5387         }
5388
5389         if (would_hit_hwbug) {
5390                 u32 last_plus_one = entry;
5391                 u32 start;
5392
5393                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5394                 start &= (TG3_TX_RING_SIZE - 1);
5395
5396                 /* If the workaround fails due to memory/mapping
5397                  * failure, silently drop this packet.
5398                  */
5399                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5400                                                 &start, base_flags, mss))
5401                         goto out_unlock;
5402
5403                 entry = start;
5404         }
5405
5406         /* Packets are ready, update Tx producer idx local and on card. */
5407         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5408
5409         tp->tx_prod = entry;
5410         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5411                 netif_stop_queue(dev);
5412                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5413                         netif_wake_queue(tp->dev);
5414         }
5415
5416 out_unlock:
5417         mmiowb();
5418
5419         return NETDEV_TX_OK;
5420 }
5421
5422 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5423                                int new_mtu)
5424 {
5425         dev->mtu = new_mtu;
5426
5427         if (new_mtu > ETH_DATA_LEN) {
5428                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5429                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5430                         ethtool_op_set_tso(dev, 0);
5431                 }
5432                 else
5433                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5434         } else {
5435                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5436                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5437                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5438         }
5439 }
5440
5441 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5442 {
5443         struct tg3 *tp = netdev_priv(dev);
5444         int err;
5445
5446         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5447                 return -EINVAL;
5448
5449         if (!netif_running(dev)) {
5450                 /* We'll just catch it later when the
5451                  * device is up'd.
5452                  */
5453                 tg3_set_mtu(dev, tp, new_mtu);
5454                 return 0;
5455         }
5456
5457         tg3_phy_stop(tp);
5458
5459         tg3_netif_stop(tp);
5460
5461         tg3_full_lock(tp, 1);
5462
5463         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5464
5465         tg3_set_mtu(dev, tp, new_mtu);
5466
5467         err = tg3_restart_hw(tp, 0);
5468
5469         if (!err)
5470                 tg3_netif_start(tp);
5471
5472         tg3_full_unlock(tp);
5473
5474         if (!err)
5475                 tg3_phy_start(tp);
5476
5477         return err;
5478 }
5479
5480 /* Free up pending packets in all rx/tx rings.
5481  *
5482  * The chip has been shut down and the driver detached from
5483  * the networking, so no interrupts or new tx packets will
5484  * end up in the driver.  tp->{tx,}lock is not held and we are not
5485  * in an interrupt context and thus may sleep.
5486  */
5487 static void tg3_free_rings(struct tg3 *tp)
5488 {
5489         struct ring_info *rxp;
5490         int i;
5491
5492         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5493                 rxp = &tp->rx_std_buffers[i];
5494
5495                 if (rxp->skb == NULL)
5496                         continue;
5497                 pci_unmap_single(tp->pdev,
5498                                  pci_unmap_addr(rxp, mapping),
5499                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5500                                  PCI_DMA_FROMDEVICE);
5501                 dev_kfree_skb_any(rxp->skb);
5502                 rxp->skb = NULL;
5503         }
5504
5505         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5506                 rxp = &tp->rx_jumbo_buffers[i];
5507
5508                 if (rxp->skb == NULL)
5509                         continue;
5510                 pci_unmap_single(tp->pdev,
5511                                  pci_unmap_addr(rxp, mapping),
5512                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5513                                  PCI_DMA_FROMDEVICE);
5514                 dev_kfree_skb_any(rxp->skb);
5515                 rxp->skb = NULL;
5516         }
5517
5518         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5519                 struct tx_ring_info *txp;
5520                 struct sk_buff *skb;
5521
5522                 txp = &tp->tx_buffers[i];
5523                 skb = txp->skb;
5524
5525                 if (skb == NULL) {
5526                         i++;
5527                         continue;
5528                 }
5529
5530                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5531
5532                 txp->skb = NULL;
5533
5534                 i += skb_shinfo(skb)->nr_frags + 1;
5535
5536                 dev_kfree_skb_any(skb);
5537         }
5538 }
5539
5540 /* Initialize tx/rx rings for packet processing.
5541  *
5542  * The chip has been shut down and the driver detached from
5543  * the networking, so no interrupts or new tx packets will
5544  * end up in the driver.  tp->{tx,}lock are held and thus
5545  * we may not sleep.
5546  */
5547 static int tg3_init_rings(struct tg3 *tp)
5548 {
5549         u32 i;
5550
5551         /* Free up all the SKBs. */
5552         tg3_free_rings(tp);
5553
5554         /* Zero out all descriptors. */
5555         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5556         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5557         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5558         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5559
5560         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5561         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5562             (tp->dev->mtu > ETH_DATA_LEN))
5563                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5564
5565         /* Initialize invariants of the rings, we only set this
5566          * stuff once.  This works because the card does not
5567          * write into the rx buffer posting rings.
5568          */
5569         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5570                 struct tg3_rx_buffer_desc *rxd;
5571
5572                 rxd = &tp->rx_std[i];
5573                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5574                         << RXD_LEN_SHIFT;
5575                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5576                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5577                                (i << RXD_OPAQUE_INDEX_SHIFT));
5578         }
5579
5580         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5581                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5582                         struct tg3_rx_buffer_desc *rxd;
5583
5584                         rxd = &tp->rx_jumbo[i];
5585                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5586                                 << RXD_LEN_SHIFT;
5587                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5588                                 RXD_FLAG_JUMBO;
5589                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5590                                (i << RXD_OPAQUE_INDEX_SHIFT));
5591                 }
5592         }
5593
5594         /* Now allocate fresh SKBs for each rx ring. */
5595         for (i = 0; i < tp->rx_pending; i++) {
5596                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5597                         printk(KERN_WARNING PFX
5598                                "%s: Using a smaller RX standard ring, "
5599                                "only %d out of %d buffers were allocated "
5600                                "successfully.\n",
5601                                tp->dev->name, i, tp->rx_pending);
5602                         if (i == 0)
5603                                 return -ENOMEM;
5604                         tp->rx_pending = i;
5605                         break;
5606                 }
5607         }
5608
5609         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5610                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5611                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5612                                              -1, i) < 0) {
5613                                 printk(KERN_WARNING PFX
5614                                        "%s: Using a smaller RX jumbo ring, "
5615                                        "only %d out of %d buffers were "
5616                                        "allocated successfully.\n",
5617                                        tp->dev->name, i, tp->rx_jumbo_pending);
5618                                 if (i == 0) {
5619                                         tg3_free_rings(tp);
5620                                         return -ENOMEM;
5621                                 }
5622                                 tp->rx_jumbo_pending = i;
5623                                 break;
5624                         }
5625                 }
5626         }
5627         return 0;
5628 }
5629
5630 /*
5631  * Must not be invoked with interrupt sources disabled and
5632  * the hardware shutdown down.
5633  */
5634 static void tg3_free_consistent(struct tg3 *tp)
5635 {
5636         kfree(tp->rx_std_buffers);
5637         tp->rx_std_buffers = NULL;
5638         if (tp->rx_std) {
5639                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5640                                     tp->rx_std, tp->rx_std_mapping);
5641                 tp->rx_std = NULL;
5642         }
5643         if (tp->rx_jumbo) {
5644                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5645                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5646                 tp->rx_jumbo = NULL;
5647         }
5648         if (tp->rx_rcb) {
5649                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5650                                     tp->rx_rcb, tp->rx_rcb_mapping);
5651                 tp->rx_rcb = NULL;
5652         }
5653         if (tp->tx_ring) {
5654                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5655                         tp->tx_ring, tp->tx_desc_mapping);
5656                 tp->tx_ring = NULL;
5657         }
5658         if (tp->hw_status) {
5659                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5660                                     tp->hw_status, tp->status_mapping);
5661                 tp->hw_status = NULL;
5662         }
5663         if (tp->hw_stats) {
5664                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5665                                     tp->hw_stats, tp->stats_mapping);
5666                 tp->hw_stats = NULL;
5667         }
5668 }
5669
5670 /*
5671  * Must not be invoked with interrupt sources disabled and
5672  * the hardware shutdown down.  Can sleep.
5673  */
5674 static int tg3_alloc_consistent(struct tg3 *tp)
5675 {
5676         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5677                                       (TG3_RX_RING_SIZE +
5678                                        TG3_RX_JUMBO_RING_SIZE)) +
5679                                      (sizeof(struct tx_ring_info) *
5680                                       TG3_TX_RING_SIZE),
5681                                      GFP_KERNEL);
5682         if (!tp->rx_std_buffers)
5683                 return -ENOMEM;
5684
5685         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5686         tp->tx_buffers = (struct tx_ring_info *)
5687                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5688
5689         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5690                                           &tp->rx_std_mapping);
5691         if (!tp->rx_std)
5692                 goto err_out;
5693
5694         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5695                                             &tp->rx_jumbo_mapping);
5696
5697         if (!tp->rx_jumbo)
5698                 goto err_out;
5699
5700         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5701                                           &tp->rx_rcb_mapping);
5702         if (!tp->rx_rcb)
5703                 goto err_out;
5704
5705         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5706                                            &tp->tx_desc_mapping);
5707         if (!tp->tx_ring)
5708                 goto err_out;
5709
5710         tp->hw_status = pci_alloc_consistent(tp->pdev,
5711                                              TG3_HW_STATUS_SIZE,
5712                                              &tp->status_mapping);
5713         if (!tp->hw_status)
5714                 goto err_out;
5715
5716         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5717                                             sizeof(struct tg3_hw_stats),
5718                                             &tp->stats_mapping);
5719         if (!tp->hw_stats)
5720                 goto err_out;
5721
5722         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5723         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5724
5725         return 0;
5726
5727 err_out:
5728         tg3_free_consistent(tp);
5729         return -ENOMEM;
5730 }
5731
5732 #define MAX_WAIT_CNT 1000
5733
5734 /* To stop a block, clear the enable bit and poll till it
5735  * clears.  tp->lock is held.
5736  */
5737 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5738 {
5739         unsigned int i;
5740         u32 val;
5741
5742         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5743                 switch (ofs) {
5744                 case RCVLSC_MODE:
5745                 case DMAC_MODE:
5746                 case MBFREE_MODE:
5747                 case BUFMGR_MODE:
5748                 case MEMARB_MODE:
5749                         /* We can't enable/disable these bits of the
5750                          * 5705/5750, just say success.
5751                          */
5752                         return 0;
5753
5754                 default:
5755                         break;
5756                 }
5757         }
5758
5759         val = tr32(ofs);
5760         val &= ~enable_bit;
5761         tw32_f(ofs, val);
5762
5763         for (i = 0; i < MAX_WAIT_CNT; i++) {
5764                 udelay(100);
5765                 val = tr32(ofs);
5766                 if ((val & enable_bit) == 0)
5767                         break;
5768         }
5769
5770         if (i == MAX_WAIT_CNT && !silent) {
5771                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5772                        "ofs=%lx enable_bit=%x\n",
5773                        ofs, enable_bit);
5774                 return -ENODEV;
5775         }
5776
5777         return 0;
5778 }
5779
5780 /* tp->lock is held. */
5781 static int tg3_abort_hw(struct tg3 *tp, int silent)
5782 {
5783         int i, err;
5784
5785         tg3_disable_ints(tp);
5786
5787         tp->rx_mode &= ~RX_MODE_ENABLE;
5788         tw32_f(MAC_RX_MODE, tp->rx_mode);
5789         udelay(10);
5790
5791         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5792         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5793         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5794         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5795         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5796         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5797
5798         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5799         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5800         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5801         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5802         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5803         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5804         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5805
5806         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5807         tw32_f(MAC_MODE, tp->mac_mode);
5808         udelay(40);
5809
5810         tp->tx_mode &= ~TX_MODE_ENABLE;
5811         tw32_f(MAC_TX_MODE, tp->tx_mode);
5812
5813         for (i = 0; i < MAX_WAIT_CNT; i++) {
5814                 udelay(100);
5815                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5816                         break;
5817         }
5818         if (i >= MAX_WAIT_CNT) {
5819                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5820                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5821                        tp->dev->name, tr32(MAC_TX_MODE));
5822                 err |= -ENODEV;
5823         }
5824
5825         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5826         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5827         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5828
5829         tw32(FTQ_RESET, 0xffffffff);
5830         tw32(FTQ_RESET, 0x00000000);
5831
5832         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5833         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5834
5835         if (tp->hw_status)
5836                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5837         if (tp->hw_stats)
5838                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5839
5840         return err;
5841 }
5842
5843 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5844 {
5845         int i;
5846         u32 apedata;
5847
5848         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5849         if (apedata != APE_SEG_SIG_MAGIC)
5850                 return;
5851
5852         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5853         if (!(apedata & APE_FW_STATUS_READY))
5854                 return;
5855
5856         /* Wait for up to 1 millisecond for APE to service previous event. */
5857         for (i = 0; i < 10; i++) {
5858                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5859                         return;
5860
5861                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5862
5863                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5864                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5865                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5866
5867                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5868
5869                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5870                         break;
5871
5872                 udelay(100);
5873         }
5874
5875         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5876                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5877 }
5878
5879 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5880 {
5881         u32 event;
5882         u32 apedata;
5883
5884         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5885                 return;
5886
5887         switch (kind) {
5888                 case RESET_KIND_INIT:
5889                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5890                                         APE_HOST_SEG_SIG_MAGIC);
5891                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5892                                         APE_HOST_SEG_LEN_MAGIC);
5893                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5894                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5895                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5896                                         APE_HOST_DRIVER_ID_MAGIC);
5897                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5898                                         APE_HOST_BEHAV_NO_PHYLOCK);
5899
5900                         event = APE_EVENT_STATUS_STATE_START;
5901                         break;
5902                 case RESET_KIND_SHUTDOWN:
5903                         /* With the interface we are currently using,
5904                          * APE does not track driver state.  Wiping
5905                          * out the HOST SEGMENT SIGNATURE forces
5906                          * the APE to assume OS absent status.
5907                          */
5908                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5909
5910                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5911                         break;
5912                 case RESET_KIND_SUSPEND:
5913                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5914                         break;
5915                 default:
5916                         return;
5917         }
5918
5919         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5920
5921         tg3_ape_send_event(tp, event);
5922 }
5923
5924 /* tp->lock is held. */
5925 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5926 {
5927         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5928                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5929
5930         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5931                 switch (kind) {
5932                 case RESET_KIND_INIT:
5933                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5934                                       DRV_STATE_START);
5935                         break;
5936
5937                 case RESET_KIND_SHUTDOWN:
5938                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5939                                       DRV_STATE_UNLOAD);
5940                         break;
5941
5942                 case RESET_KIND_SUSPEND:
5943                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5944                                       DRV_STATE_SUSPEND);
5945                         break;
5946
5947                 default:
5948                         break;
5949                 }
5950         }
5951
5952         if (kind == RESET_KIND_INIT ||
5953             kind == RESET_KIND_SUSPEND)
5954                 tg3_ape_driver_state_change(tp, kind);
5955 }
5956
5957 /* tp->lock is held. */
5958 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5959 {
5960         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5961                 switch (kind) {
5962                 case RESET_KIND_INIT:
5963                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5964                                       DRV_STATE_START_DONE);
5965                         break;
5966
5967                 case RESET_KIND_SHUTDOWN:
5968                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5969                                       DRV_STATE_UNLOAD_DONE);
5970                         break;
5971
5972                 default:
5973                         break;
5974                 }
5975         }
5976
5977         if (kind == RESET_KIND_SHUTDOWN)
5978                 tg3_ape_driver_state_change(tp, kind);
5979 }
5980
5981 /* tp->lock is held. */
5982 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5983 {
5984         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5985                 switch (kind) {
5986                 case RESET_KIND_INIT:
5987                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5988                                       DRV_STATE_START);
5989                         break;
5990
5991                 case RESET_KIND_SHUTDOWN:
5992                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5993                                       DRV_STATE_UNLOAD);
5994                         break;
5995
5996                 case RESET_KIND_SUSPEND:
5997                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5998                                       DRV_STATE_SUSPEND);
5999                         break;
6000
6001                 default:
6002                         break;
6003                 }
6004         }
6005 }
6006
6007 static int tg3_poll_fw(struct tg3 *tp)
6008 {
6009         int i;
6010         u32 val;
6011
6012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6013                 /* Wait up to 20ms for init done. */
6014                 for (i = 0; i < 200; i++) {
6015                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6016                                 return 0;
6017                         udelay(100);
6018                 }
6019                 return -ENODEV;
6020         }
6021
6022         /* Wait for firmware initialization to complete. */
6023         for (i = 0; i < 100000; i++) {
6024                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6025                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6026                         break;
6027                 udelay(10);
6028         }
6029
6030         /* Chip might not be fitted with firmware.  Some Sun onboard
6031          * parts are configured like that.  So don't signal the timeout
6032          * of the above loop as an error, but do report the lack of
6033          * running firmware once.
6034          */
6035         if (i >= 100000 &&
6036             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6037                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6038
6039                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6040                        tp->dev->name);
6041         }
6042
6043         return 0;
6044 }
6045
6046 /* Save PCI command register before chip reset */
6047 static void tg3_save_pci_state(struct tg3 *tp)
6048 {
6049         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6050 }
6051
6052 /* Restore PCI state after chip reset */
6053 static void tg3_restore_pci_state(struct tg3 *tp)
6054 {
6055         u32 val;
6056
6057         /* Re-enable indirect register accesses. */
6058         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6059                                tp->misc_host_ctrl);
6060
6061         /* Set MAX PCI retry to zero. */
6062         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6063         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6064             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6065                 val |= PCISTATE_RETRY_SAME_DMA;
6066         /* Allow reads and writes to the APE register and memory space. */
6067         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6068                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6069                        PCISTATE_ALLOW_APE_SHMEM_WR;
6070         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6071
6072         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6073
6074         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6075                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6076                         pcie_set_readrq(tp->pdev, 4096);
6077                 else {
6078                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6079                                               tp->pci_cacheline_sz);
6080                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6081                                               tp->pci_lat_timer);
6082                 }
6083         }
6084
6085         /* Make sure PCI-X relaxed ordering bit is clear. */
6086         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6087                 u16 pcix_cmd;
6088
6089                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6090                                      &pcix_cmd);
6091                 pcix_cmd &= ~PCI_X_CMD_ERO;
6092                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6093                                       pcix_cmd);
6094         }
6095
6096         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6097
6098                 /* Chip reset on 5780 will reset MSI enable bit,
6099                  * so need to restore it.
6100                  */
6101                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6102                         u16 ctrl;
6103
6104                         pci_read_config_word(tp->pdev,
6105                                              tp->msi_cap + PCI_MSI_FLAGS,
6106                                              &ctrl);
6107                         pci_write_config_word(tp->pdev,
6108                                               tp->msi_cap + PCI_MSI_FLAGS,
6109                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6110                         val = tr32(MSGINT_MODE);
6111                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6112                 }
6113         }
6114 }
6115
6116 static void tg3_stop_fw(struct tg3 *);
6117
6118 /* tp->lock is held. */
6119 static int tg3_chip_reset(struct tg3 *tp)
6120 {
6121         u32 val;
6122         void (*write_op)(struct tg3 *, u32, u32);
6123         int err;
6124
6125         tg3_nvram_lock(tp);
6126
6127         tg3_mdio_stop(tp);
6128
6129         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6130
6131         /* No matching tg3_nvram_unlock() after this because
6132          * chip reset below will undo the nvram lock.
6133          */
6134         tp->nvram_lock_cnt = 0;
6135
6136         /* GRC_MISC_CFG core clock reset will clear the memory
6137          * enable bit in PCI register 4 and the MSI enable bit
6138          * on some chips, so we save relevant registers here.
6139          */
6140         tg3_save_pci_state(tp);
6141
6142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6143             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6144                 tw32(GRC_FASTBOOT_PC, 0);
6145
6146         /*
6147          * We must avoid the readl() that normally takes place.
6148          * It locks machines, causes machine checks, and other
6149          * fun things.  So, temporarily disable the 5701
6150          * hardware workaround, while we do the reset.
6151          */
6152         write_op = tp->write32;
6153         if (write_op == tg3_write_flush_reg32)
6154                 tp->write32 = tg3_write32;
6155
6156         /* Prevent the irq handler from reading or writing PCI registers
6157          * during chip reset when the memory enable bit in the PCI command
6158          * register may be cleared.  The chip does not generate interrupt
6159          * at this time, but the irq handler may still be called due to irq
6160          * sharing or irqpoll.
6161          */
6162         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6163         if (tp->hw_status) {
6164                 tp->hw_status->status = 0;
6165                 tp->hw_status->status_tag = 0;
6166         }
6167         tp->last_tag = 0;
6168         tp->last_irq_tag = 0;
6169         smp_mb();
6170         synchronize_irq(tp->pdev->irq);
6171
6172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6173                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6174                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6175         }
6176
6177         /* do the reset */
6178         val = GRC_MISC_CFG_CORECLK_RESET;
6179
6180         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6181                 if (tr32(0x7e2c) == 0x60) {
6182                         tw32(0x7e2c, 0x20);
6183                 }
6184                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6185                         tw32(GRC_MISC_CFG, (1 << 29));
6186                         val |= (1 << 29);
6187                 }
6188         }
6189
6190         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6191                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6192                 tw32(GRC_VCPU_EXT_CTRL,
6193                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6194         }
6195
6196         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6197                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6198         tw32(GRC_MISC_CFG, val);
6199
6200         /* restore 5701 hardware bug workaround write method */
6201         tp->write32 = write_op;
6202
6203         /* Unfortunately, we have to delay before the PCI read back.
6204          * Some 575X chips even will not respond to a PCI cfg access
6205          * when the reset command is given to the chip.
6206          *
6207          * How do these hardware designers expect things to work
6208          * properly if the PCI write is posted for a long period
6209          * of time?  It is always necessary to have some method by
6210          * which a register read back can occur to push the write
6211          * out which does the reset.
6212          *
6213          * For most tg3 variants the trick below was working.
6214          * Ho hum...
6215          */
6216         udelay(120);
6217
6218         /* Flush PCI posted writes.  The normal MMIO registers
6219          * are inaccessible at this time so this is the only
6220          * way to make this reliably (actually, this is no longer
6221          * the case, see above).  I tried to use indirect
6222          * register read/write but this upset some 5701 variants.
6223          */
6224         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6225
6226         udelay(120);
6227
6228         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6229                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6230                         int i;
6231                         u32 cfg_val;
6232
6233                         /* Wait for link training to complete.  */
6234                         for (i = 0; i < 5000; i++)
6235                                 udelay(100);
6236
6237                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6238                         pci_write_config_dword(tp->pdev, 0xc4,
6239                                                cfg_val | (1 << 15));
6240                 }
6241
6242                 /* Set PCIE max payload size to 128 bytes and
6243                  * clear the "no snoop" and "relaxed ordering" bits.
6244                  */
6245                 pci_write_config_word(tp->pdev,
6246                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6247                                       0);
6248
6249                 pcie_set_readrq(tp->pdev, 4096);
6250
6251                 /* Clear error status */
6252                 pci_write_config_word(tp->pdev,
6253                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6254                                       PCI_EXP_DEVSTA_CED |
6255                                       PCI_EXP_DEVSTA_NFED |
6256                                       PCI_EXP_DEVSTA_FED |
6257                                       PCI_EXP_DEVSTA_URD);
6258         }
6259
6260         tg3_restore_pci_state(tp);
6261
6262         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6263
6264         val = 0;
6265         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6266                 val = tr32(MEMARB_MODE);
6267         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6268
6269         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6270                 tg3_stop_fw(tp);
6271                 tw32(0x5000, 0x400);
6272         }
6273
6274         tw32(GRC_MODE, tp->grc_mode);
6275
6276         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6277                 val = tr32(0xc4);
6278
6279                 tw32(0xc4, val | (1 << 15));
6280         }
6281
6282         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6283             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6284                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6285                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6286                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6287                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6288         }
6289
6290         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6291                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6292                 tw32_f(MAC_MODE, tp->mac_mode);
6293         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6294                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6295                 tw32_f(MAC_MODE, tp->mac_mode);
6296         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6297                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6298                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6299                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6300                 tw32_f(MAC_MODE, tp->mac_mode);
6301         } else
6302                 tw32_f(MAC_MODE, 0);
6303         udelay(40);
6304
6305         tg3_mdio_start(tp);
6306
6307         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6308
6309         err = tg3_poll_fw(tp);
6310         if (err)
6311                 return err;
6312
6313         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6314             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6315                 val = tr32(0x7c00);
6316
6317                 tw32(0x7c00, val | (1 << 25));
6318         }
6319
6320         /* Reprobe ASF enable state.  */
6321         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6322         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6323         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6324         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6325                 u32 nic_cfg;
6326
6327                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6328                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6329                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6330                         tp->last_event_jiffies = jiffies;
6331                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6332                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6333                 }
6334         }
6335
6336         return 0;
6337 }
6338
6339 /* tp->lock is held. */
6340 static void tg3_stop_fw(struct tg3 *tp)
6341 {
6342         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6343            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6344                 /* Wait for RX cpu to ACK the previous event. */
6345                 tg3_wait_for_event_ack(tp);
6346
6347                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6348
6349                 tg3_generate_fw_event(tp);
6350
6351                 /* Wait for RX cpu to ACK this event. */
6352                 tg3_wait_for_event_ack(tp);
6353         }
6354 }
6355
6356 /* tp->lock is held. */
6357 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6358 {
6359         int err;
6360
6361         tg3_stop_fw(tp);
6362
6363         tg3_write_sig_pre_reset(tp, kind);
6364
6365         tg3_abort_hw(tp, silent);
6366         err = tg3_chip_reset(tp);
6367
6368         __tg3_set_mac_addr(tp, 0);
6369
6370         tg3_write_sig_legacy(tp, kind);
6371         tg3_write_sig_post_reset(tp, kind);
6372
6373         if (err)
6374                 return err;
6375
6376         return 0;
6377 }
6378
6379 #define RX_CPU_SCRATCH_BASE     0x30000
6380 #define RX_CPU_SCRATCH_SIZE     0x04000
6381 #define TX_CPU_SCRATCH_BASE     0x34000
6382 #define TX_CPU_SCRATCH_SIZE     0x04000
6383
6384 /* tp->lock is held. */
6385 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6386 {
6387         int i;
6388
6389         BUG_ON(offset == TX_CPU_BASE &&
6390             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6391
6392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6393                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6394
6395                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6396                 return 0;
6397         }
6398         if (offset == RX_CPU_BASE) {
6399                 for (i = 0; i < 10000; i++) {
6400                         tw32(offset + CPU_STATE, 0xffffffff);
6401                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6402                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6403                                 break;
6404                 }
6405
6406                 tw32(offset + CPU_STATE, 0xffffffff);
6407                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6408                 udelay(10);
6409         } else {
6410                 for (i = 0; i < 10000; i++) {
6411                         tw32(offset + CPU_STATE, 0xffffffff);
6412                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6413                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6414                                 break;
6415                 }
6416         }
6417
6418         if (i >= 10000) {
6419                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6420                        "and %s CPU\n",
6421                        tp->dev->name,
6422                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6423                 return -ENODEV;
6424         }
6425
6426         /* Clear firmware's nvram arbitration. */
6427         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6428                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6429         return 0;
6430 }
6431
6432 struct fw_info {
6433         unsigned int fw_base;
6434         unsigned int fw_len;
6435         const __be32 *fw_data;
6436 };
6437
6438 /* tp->lock is held. */
6439 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6440                                  int cpu_scratch_size, struct fw_info *info)
6441 {
6442         int err, lock_err, i;
6443         void (*write_op)(struct tg3 *, u32, u32);
6444
6445         if (cpu_base == TX_CPU_BASE &&
6446             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6447                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6448                        "TX cpu firmware on %s which is 5705.\n",
6449                        tp->dev->name);
6450                 return -EINVAL;
6451         }
6452
6453         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6454                 write_op = tg3_write_mem;
6455         else
6456                 write_op = tg3_write_indirect_reg32;
6457
6458         /* It is possible that bootcode is still loading at this point.
6459          * Get the nvram lock first before halting the cpu.
6460          */
6461         lock_err = tg3_nvram_lock(tp);
6462         err = tg3_halt_cpu(tp, cpu_base);
6463         if (!lock_err)
6464                 tg3_nvram_unlock(tp);
6465         if (err)
6466                 goto out;
6467
6468         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6469                 write_op(tp, cpu_scratch_base + i, 0);
6470         tw32(cpu_base + CPU_STATE, 0xffffffff);
6471         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6472         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6473                 write_op(tp, (cpu_scratch_base +
6474                               (info->fw_base & 0xffff) +
6475                               (i * sizeof(u32))),
6476                               be32_to_cpu(info->fw_data[i]));
6477
6478         err = 0;
6479
6480 out:
6481         return err;
6482 }
6483
6484 /* tp->lock is held. */
6485 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6486 {
6487         struct fw_info info;
6488         const __be32 *fw_data;
6489         int err, i;
6490
6491         fw_data = (void *)tp->fw->data;
6492
6493         /* Firmware blob starts with version numbers, followed by
6494            start address and length. We are setting complete length.
6495            length = end_address_of_bss - start_address_of_text.
6496            Remainder is the blob to be loaded contiguously
6497            from start address. */
6498
6499         info.fw_base = be32_to_cpu(fw_data[1]);
6500         info.fw_len = tp->fw->size - 12;
6501         info.fw_data = &fw_data[3];
6502
6503         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6504                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6505                                     &info);
6506         if (err)
6507                 return err;
6508
6509         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6510                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6511                                     &info);
6512         if (err)
6513                 return err;
6514
6515         /* Now startup only the RX cpu. */
6516         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6517         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6518
6519         for (i = 0; i < 5; i++) {
6520                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6521                         break;
6522                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6523                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6524                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6525                 udelay(1000);
6526         }
6527         if (i >= 5) {
6528                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6529                        "to set RX CPU PC, is %08x should be %08x\n",
6530                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6531                        info.fw_base);
6532                 return -ENODEV;
6533         }
6534         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6535         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6536
6537         return 0;
6538 }
6539
6540 /* 5705 needs a special version of the TSO firmware.  */
6541
6542 /* tp->lock is held. */
6543 static int tg3_load_tso_firmware(struct tg3 *tp)
6544 {
6545         struct fw_info info;
6546         const __be32 *fw_data;
6547         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6548         int err, i;
6549
6550         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6551                 return 0;
6552
6553         fw_data = (void *)tp->fw->data;
6554
6555         /* Firmware blob starts with version numbers, followed by
6556            start address and length. We are setting complete length.
6557            length = end_address_of_bss - start_address_of_text.
6558            Remainder is the blob to be loaded contiguously
6559            from start address. */
6560
6561         info.fw_base = be32_to_cpu(fw_data[1]);
6562         cpu_scratch_size = tp->fw_len;
6563         info.fw_len = tp->fw->size - 12;
6564         info.fw_data = &fw_data[3];
6565
6566         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6567                 cpu_base = RX_CPU_BASE;
6568                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6569         } else {
6570                 cpu_base = TX_CPU_BASE;
6571                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6572                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6573         }
6574
6575         err = tg3_load_firmware_cpu(tp, cpu_base,
6576                                     cpu_scratch_base, cpu_scratch_size,
6577                                     &info);
6578         if (err)
6579                 return err;
6580
6581         /* Now startup the cpu. */
6582         tw32(cpu_base + CPU_STATE, 0xffffffff);
6583         tw32_f(cpu_base + CPU_PC, info.fw_base);
6584
6585         for (i = 0; i < 5; i++) {
6586                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6587                         break;
6588                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6589                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6590                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6591                 udelay(1000);
6592         }
6593         if (i >= 5) {
6594                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6595                        "to set CPU PC, is %08x should be %08x\n",
6596                        tp->dev->name, tr32(cpu_base + CPU_PC),
6597                        info.fw_base);
6598                 return -ENODEV;
6599         }
6600         tw32(cpu_base + CPU_STATE, 0xffffffff);
6601         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6602         return 0;
6603 }
6604
6605
6606 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6607 {
6608         struct tg3 *tp = netdev_priv(dev);
6609         struct sockaddr *addr = p;
6610         int err = 0, skip_mac_1 = 0;
6611
6612         if (!is_valid_ether_addr(addr->sa_data))
6613                 return -EINVAL;
6614
6615         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6616
6617         if (!netif_running(dev))
6618                 return 0;
6619
6620         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6621                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6622
6623                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6624                 addr0_low = tr32(MAC_ADDR_0_LOW);
6625                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6626                 addr1_low = tr32(MAC_ADDR_1_LOW);
6627
6628                 /* Skip MAC addr 1 if ASF is using it. */
6629                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6630                     !(addr1_high == 0 && addr1_low == 0))
6631                         skip_mac_1 = 1;
6632         }
6633         spin_lock_bh(&tp->lock);
6634         __tg3_set_mac_addr(tp, skip_mac_1);
6635         spin_unlock_bh(&tp->lock);
6636
6637         return err;
6638 }
6639
6640 /* tp->lock is held. */
6641 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6642                            dma_addr_t mapping, u32 maxlen_flags,
6643                            u32 nic_addr)
6644 {
6645         tg3_write_mem(tp,
6646                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6647                       ((u64) mapping >> 32));
6648         tg3_write_mem(tp,
6649                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6650                       ((u64) mapping & 0xffffffff));
6651         tg3_write_mem(tp,
6652                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6653                        maxlen_flags);
6654
6655         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6656                 tg3_write_mem(tp,
6657                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6658                               nic_addr);
6659 }
6660
6661 static void __tg3_set_rx_mode(struct net_device *);
6662 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6663 {
6664         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6665         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6666         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6667         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6668         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6669                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6670                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6671         }
6672         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6673         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6674         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6675                 u32 val = ec->stats_block_coalesce_usecs;
6676
6677                 if (!netif_carrier_ok(tp->dev))
6678                         val = 0;
6679
6680                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6681         }
6682 }
6683
6684 /* tp->lock is held. */
6685 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6686 {
6687         u32 val, rdmac_mode;
6688         int i, err, limit;
6689
6690         tg3_disable_ints(tp);
6691
6692         tg3_stop_fw(tp);
6693
6694         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6695
6696         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6697                 tg3_abort_hw(tp, 1);
6698         }
6699
6700         if (reset_phy &&
6701             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6702                 tg3_phy_reset(tp);
6703
6704         err = tg3_chip_reset(tp);
6705         if (err)
6706                 return err;
6707
6708         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6709
6710         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6711                 val = tr32(TG3_CPMU_CTRL);
6712                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6713                 tw32(TG3_CPMU_CTRL, val);
6714
6715                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6716                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6717                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6718                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6719
6720                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6721                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6722                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6723                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6724
6725                 val = tr32(TG3_CPMU_HST_ACC);
6726                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6727                 val |= CPMU_HST_ACC_MACCLK_6_25;
6728                 tw32(TG3_CPMU_HST_ACC, val);
6729         }
6730
6731         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6732                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6733                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6734                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6735                 tw32(PCIE_PWR_MGMT_THRESH, val);
6736
6737                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6738                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6739
6740                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6741         }
6742
6743         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6744                 val = tr32(TG3_PCIE_LNKCTL);
6745                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6746                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6747                 else
6748                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6749                 tw32(TG3_PCIE_LNKCTL, val);
6750         }
6751
6752         /* This works around an issue with Athlon chipsets on
6753          * B3 tigon3 silicon.  This bit has no effect on any
6754          * other revision.  But do not set this on PCI Express
6755          * chips and don't even touch the clocks if the CPMU is present.
6756          */
6757         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6758                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6759                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6760                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6761         }
6762
6763         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6764             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6765                 val = tr32(TG3PCI_PCISTATE);
6766                 val |= PCISTATE_RETRY_SAME_DMA;
6767                 tw32(TG3PCI_PCISTATE, val);
6768         }
6769
6770         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6771                 /* Allow reads and writes to the
6772                  * APE register and memory space.
6773                  */
6774                 val = tr32(TG3PCI_PCISTATE);
6775                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6776                        PCISTATE_ALLOW_APE_SHMEM_WR;
6777                 tw32(TG3PCI_PCISTATE, val);
6778         }
6779
6780         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6781                 /* Enable some hw fixes.  */
6782                 val = tr32(TG3PCI_MSI_DATA);
6783                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6784                 tw32(TG3PCI_MSI_DATA, val);
6785         }
6786
6787         /* Descriptor ring init may make accesses to the
6788          * NIC SRAM area to setup the TX descriptors, so we
6789          * can only do this after the hardware has been
6790          * successfully reset.
6791          */
6792         err = tg3_init_rings(tp);
6793         if (err)
6794                 return err;
6795
6796         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6797             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6798                 /* This value is determined during the probe time DMA
6799                  * engine test, tg3_test_dma.
6800                  */
6801                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6802         }
6803
6804         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6805                           GRC_MODE_4X_NIC_SEND_RINGS |
6806                           GRC_MODE_NO_TX_PHDR_CSUM |
6807                           GRC_MODE_NO_RX_PHDR_CSUM);
6808         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6809
6810         /* Pseudo-header checksum is done by hardware logic and not
6811          * the offload processers, so make the chip do the pseudo-
6812          * header checksums on receive.  For transmit it is more
6813          * convenient to do the pseudo-header checksum in software
6814          * as Linux does that on transmit for us in all cases.
6815          */
6816         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6817
6818         tw32(GRC_MODE,
6819              tp->grc_mode |
6820              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6821
6822         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6823         val = tr32(GRC_MISC_CFG);
6824         val &= ~0xff;
6825         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6826         tw32(GRC_MISC_CFG, val);
6827
6828         /* Initialize MBUF/DESC pool. */
6829         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6830                 /* Do nothing.  */
6831         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6832                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6833                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6834                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6835                 else
6836                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6837                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6838                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6839         }
6840         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6841                 int fw_len;
6842
6843                 fw_len = tp->fw_len;
6844                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6845                 tw32(BUFMGR_MB_POOL_ADDR,
6846                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6847                 tw32(BUFMGR_MB_POOL_SIZE,
6848                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6849         }
6850
6851         if (tp->dev->mtu <= ETH_DATA_LEN) {
6852                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6853                      tp->bufmgr_config.mbuf_read_dma_low_water);
6854                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6855                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6856                 tw32(BUFMGR_MB_HIGH_WATER,
6857                      tp->bufmgr_config.mbuf_high_water);
6858         } else {
6859                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6860                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6861                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6862                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6863                 tw32(BUFMGR_MB_HIGH_WATER,
6864                      tp->bufmgr_config.mbuf_high_water_jumbo);
6865         }
6866         tw32(BUFMGR_DMA_LOW_WATER,
6867              tp->bufmgr_config.dma_low_water);
6868         tw32(BUFMGR_DMA_HIGH_WATER,
6869              tp->bufmgr_config.dma_high_water);
6870
6871         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6872         for (i = 0; i < 2000; i++) {
6873                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6874                         break;
6875                 udelay(10);
6876         }
6877         if (i >= 2000) {
6878                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6879                        tp->dev->name);
6880                 return -ENODEV;
6881         }
6882
6883         /* Setup replenish threshold. */
6884         val = tp->rx_pending / 8;
6885         if (val == 0)
6886                 val = 1;
6887         else if (val > tp->rx_std_max_post)
6888                 val = tp->rx_std_max_post;
6889         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6890                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6891                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6892
6893                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6894                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6895         }
6896
6897         tw32(RCVBDI_STD_THRESH, val);
6898
6899         /* Initialize TG3_BDINFO's at:
6900          *  RCVDBDI_STD_BD:     standard eth size rx ring
6901          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6902          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6903          *
6904          * like so:
6905          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6906          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6907          *                              ring attribute flags
6908          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6909          *
6910          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6911          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6912          *
6913          * The size of each ring is fixed in the firmware, but the location is
6914          * configurable.
6915          */
6916         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6917              ((u64) tp->rx_std_mapping >> 32));
6918         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6919              ((u64) tp->rx_std_mapping & 0xffffffff));
6920         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6921              NIC_SRAM_RX_BUFFER_DESC);
6922
6923         /* Don't even try to program the JUMBO/MINI buffer descriptor
6924          * configs on 5705.
6925          */
6926         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6927                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6928                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6929         } else {
6930                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6931                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6932
6933                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6934                      BDINFO_FLAGS_DISABLED);
6935
6936                 /* Setup replenish threshold. */
6937                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6938
6939                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6940                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6941                              ((u64) tp->rx_jumbo_mapping >> 32));
6942                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6943                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6944                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6945                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6946                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6947                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6948                 } else {
6949                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6950                              BDINFO_FLAGS_DISABLED);
6951                 }
6952
6953         }
6954
6955         /* There is only one send ring on 5705/5750, no need to explicitly
6956          * disable the others.
6957          */
6958         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6959                 /* Clear out send RCB ring in SRAM. */
6960                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6961                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6962                                       BDINFO_FLAGS_DISABLED);
6963         }
6964
6965         tp->tx_prod = 0;
6966         tp->tx_cons = 0;
6967         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6968         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6969
6970         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6971                        tp->tx_desc_mapping,
6972                        (TG3_TX_RING_SIZE <<
6973                         BDINFO_FLAGS_MAXLEN_SHIFT),
6974                        NIC_SRAM_TX_BUFFER_DESC);
6975
6976         /* There is only one receive return ring on 5705/5750, no need
6977          * to explicitly disable the others.
6978          */
6979         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6980                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6981                      i += TG3_BDINFO_SIZE) {
6982                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6983                                       BDINFO_FLAGS_DISABLED);
6984                 }
6985         }
6986
6987         tp->rx_rcb_ptr = 0;
6988         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6989
6990         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6991                        tp->rx_rcb_mapping,
6992                        (TG3_RX_RCB_RING_SIZE(tp) <<
6993                         BDINFO_FLAGS_MAXLEN_SHIFT),
6994                        0);
6995
6996         tp->rx_std_ptr = tp->rx_pending;
6997         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6998                      tp->rx_std_ptr);
6999
7000         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7001                                                 tp->rx_jumbo_pending : 0;
7002         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7003                      tp->rx_jumbo_ptr);
7004
7005         /* Initialize MAC address and backoff seed. */
7006         __tg3_set_mac_addr(tp, 0);
7007
7008         /* MTU + ethernet header + FCS + optional VLAN tag */
7009         tw32(MAC_RX_MTU_SIZE,
7010              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7011
7012         /* The slot time is changed by tg3_setup_phy if we
7013          * run at gigabit with half duplex.
7014          */
7015         tw32(MAC_TX_LENGTHS,
7016              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7017              (6 << TX_LENGTHS_IPG_SHIFT) |
7018              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7019
7020         /* Receive rules. */
7021         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7022         tw32(RCVLPC_CONFIG, 0x0181);
7023
7024         /* Calculate RDMAC_MODE setting early, we need it to determine
7025          * the RCVLPC_STATE_ENABLE mask.
7026          */
7027         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7028                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7029                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7030                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7031                       RDMAC_MODE_LNGREAD_ENAB);
7032
7033         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7036                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7037                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7038                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7039
7040         /* If statement applies to 5705 and 5750 PCI devices only */
7041         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7042              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7043             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7044                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7045                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7046                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7047                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7048                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7049                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7050                 }
7051         }
7052
7053         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7054                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7055
7056         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7057                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7058
7059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7060             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7061                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7062
7063         /* Receive/send statistics. */
7064         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7065                 val = tr32(RCVLPC_STATS_ENABLE);
7066                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7067                 tw32(RCVLPC_STATS_ENABLE, val);
7068         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7069                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7070                 val = tr32(RCVLPC_STATS_ENABLE);
7071                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7072                 tw32(RCVLPC_STATS_ENABLE, val);
7073         } else {
7074                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7075         }
7076         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7077         tw32(SNDDATAI_STATSENAB, 0xffffff);
7078         tw32(SNDDATAI_STATSCTRL,
7079              (SNDDATAI_SCTRL_ENABLE |
7080               SNDDATAI_SCTRL_FASTUPD));
7081
7082         /* Setup host coalescing engine. */
7083         tw32(HOSTCC_MODE, 0);
7084         for (i = 0; i < 2000; i++) {
7085                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7086                         break;
7087                 udelay(10);
7088         }
7089
7090         __tg3_set_coalesce(tp, &tp->coal);
7091
7092         /* set status block DMA address */
7093         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7094              ((u64) tp->status_mapping >> 32));
7095         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7096              ((u64) tp->status_mapping & 0xffffffff));
7097
7098         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7099                 /* Status/statistics block address.  See tg3_timer,
7100                  * the tg3_periodic_fetch_stats call there, and
7101                  * tg3_get_stats to see how this works for 5705/5750 chips.
7102                  */
7103                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7104                      ((u64) tp->stats_mapping >> 32));
7105                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7106                      ((u64) tp->stats_mapping & 0xffffffff));
7107                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7108                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7109         }
7110
7111         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7112
7113         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7114         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7115         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7116                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7117
7118         /* Clear statistics/status block in chip, and status block in ram. */
7119         for (i = NIC_SRAM_STATS_BLK;
7120              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7121              i += sizeof(u32)) {
7122                 tg3_write_mem(tp, i, 0);
7123                 udelay(40);
7124         }
7125         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7126
7127         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7128                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7129                 /* reset to prevent losing 1st rx packet intermittently */
7130                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7131                 udelay(10);
7132         }
7133
7134         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7135                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7136         else
7137                 tp->mac_mode = 0;
7138         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7139                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7140         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7141             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7142             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7143                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7144         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7145         udelay(40);
7146
7147         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7148          * If TG3_FLG2_IS_NIC is zero, we should read the
7149          * register to preserve the GPIO settings for LOMs. The GPIOs,
7150          * whether used as inputs or outputs, are set by boot code after
7151          * reset.
7152          */
7153         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7154                 u32 gpio_mask;
7155
7156                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7157                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7158                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7159
7160                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7161                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7162                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7163
7164                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7165                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7166
7167                 tp->grc_local_ctrl &= ~gpio_mask;
7168                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7169
7170                 /* GPIO1 must be driven high for eeprom write protect */
7171                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7172                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7173                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7174         }
7175         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7176         udelay(100);
7177
7178         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7179
7180         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7181                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7182                 udelay(40);
7183         }
7184
7185         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7186                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7187                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7188                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7189                WDMAC_MODE_LNGREAD_ENAB);
7190
7191         /* If statement applies to 5705 and 5750 PCI devices only */
7192         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7193              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7194             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7195                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7196                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7197                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7198                         /* nothing */
7199                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7200                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7201                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7202                         val |= WDMAC_MODE_RX_ACCEL;
7203                 }
7204         }
7205
7206         /* Enable host coalescing bug fix */
7207         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7208                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7209
7210         tw32_f(WDMAC_MODE, val);
7211         udelay(40);
7212
7213         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7214                 u16 pcix_cmd;
7215
7216                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7217                                      &pcix_cmd);
7218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7219                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7220                         pcix_cmd |= PCI_X_CMD_READ_2K;
7221                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7222                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7223                         pcix_cmd |= PCI_X_CMD_READ_2K;
7224                 }
7225                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7226                                       pcix_cmd);
7227         }
7228
7229         tw32_f(RDMAC_MODE, rdmac_mode);
7230         udelay(40);
7231
7232         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7233         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7234                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7235
7236         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7237                 tw32(SNDDATAC_MODE,
7238                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7239         else
7240                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7241
7242         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7243         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7244         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7245         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7246         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7247                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7248         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7249         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7250
7251         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7252                 err = tg3_load_5701_a0_firmware_fix(tp);
7253                 if (err)
7254                         return err;
7255         }
7256
7257         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7258                 err = tg3_load_tso_firmware(tp);
7259                 if (err)
7260                         return err;
7261         }
7262
7263         tp->tx_mode = TX_MODE_ENABLE;
7264         tw32_f(MAC_TX_MODE, tp->tx_mode);
7265         udelay(100);
7266
7267         tp->rx_mode = RX_MODE_ENABLE;
7268         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7269                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7270
7271         tw32_f(MAC_RX_MODE, tp->rx_mode);
7272         udelay(10);
7273
7274         tw32(MAC_LED_CTRL, tp->led_ctrl);
7275
7276         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7277         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7278                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7279                 udelay(10);
7280         }
7281         tw32_f(MAC_RX_MODE, tp->rx_mode);
7282         udelay(10);
7283
7284         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7285                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7286                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7287                         /* Set drive transmission level to 1.2V  */
7288                         /* only if the signal pre-emphasis bit is not set  */
7289                         val = tr32(MAC_SERDES_CFG);
7290                         val &= 0xfffff000;
7291                         val |= 0x880;
7292                         tw32(MAC_SERDES_CFG, val);
7293                 }
7294                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7295                         tw32(MAC_SERDES_CFG, 0x616000);
7296         }
7297
7298         /* Prevent chip from dropping frames when flow control
7299          * is enabled.
7300          */
7301         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7302
7303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7304             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7305                 /* Use hardware link auto-negotiation */
7306                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7307         }
7308
7309         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7310             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7311                 u32 tmp;
7312
7313                 tmp = tr32(SERDES_RX_CTRL);
7314                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7315                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7316                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7317                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7318         }
7319
7320         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7321                 if (tp->link_config.phy_is_low_power) {
7322                         tp->link_config.phy_is_low_power = 0;
7323                         tp->link_config.speed = tp->link_config.orig_speed;
7324                         tp->link_config.duplex = tp->link_config.orig_duplex;
7325                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7326                 }
7327
7328                 err = tg3_setup_phy(tp, 0);
7329                 if (err)
7330                         return err;
7331
7332                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7333                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7334                         u32 tmp;
7335
7336                         /* Clear CRC stats. */
7337                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7338                                 tg3_writephy(tp, MII_TG3_TEST1,
7339                                              tmp | MII_TG3_TEST1_CRC_EN);
7340                                 tg3_readphy(tp, 0x14, &tmp);
7341                         }
7342                 }
7343         }
7344
7345         __tg3_set_rx_mode(tp->dev);
7346
7347         /* Initialize receive rules. */
7348         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7349         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7350         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7351         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7352
7353         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7354             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7355                 limit = 8;
7356         else
7357                 limit = 16;
7358         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7359                 limit -= 4;
7360         switch (limit) {
7361         case 16:
7362                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7363         case 15:
7364                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7365         case 14:
7366                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7367         case 13:
7368                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7369         case 12:
7370                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7371         case 11:
7372                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7373         case 10:
7374                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7375         case 9:
7376                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7377         case 8:
7378                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7379         case 7:
7380                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7381         case 6:
7382                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7383         case 5:
7384                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7385         case 4:
7386                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7387         case 3:
7388                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7389         case 2:
7390         case 1:
7391
7392         default:
7393                 break;
7394         }
7395
7396         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7397                 /* Write our heartbeat update interval to APE. */
7398                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7399                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7400
7401         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7402
7403         return 0;
7404 }
7405
7406 /* Called at device open time to get the chip ready for
7407  * packet processing.  Invoked with tp->lock held.
7408  */
7409 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7410 {
7411         tg3_switch_clocks(tp);
7412
7413         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7414
7415         return tg3_reset_hw(tp, reset_phy);
7416 }
7417
7418 #define TG3_STAT_ADD32(PSTAT, REG) \
7419 do {    u32 __val = tr32(REG); \
7420         (PSTAT)->low += __val; \
7421         if ((PSTAT)->low < __val) \
7422                 (PSTAT)->high += 1; \
7423 } while (0)
7424
7425 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7426 {
7427         struct tg3_hw_stats *sp = tp->hw_stats;
7428
7429         if (!netif_carrier_ok(tp->dev))
7430                 return;
7431
7432         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7433         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7434         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7435         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7436         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7437         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7438         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7439         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7440         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7441         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7442         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7443         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7444         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7445
7446         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7447         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7448         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7449         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7450         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7451         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7452         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7453         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7454         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7455         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7456         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7457         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7458         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7459         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7460
7461         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7462         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7463         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7464 }
7465
7466 static void tg3_timer(unsigned long __opaque)
7467 {
7468         struct tg3 *tp = (struct tg3 *) __opaque;
7469
7470         if (tp->irq_sync)
7471                 goto restart_timer;
7472
7473         spin_lock(&tp->lock);
7474
7475         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7476                 /* All of this garbage is because when using non-tagged
7477                  * IRQ status the mailbox/status_block protocol the chip
7478                  * uses with the cpu is race prone.
7479                  */
7480                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7481                         tw32(GRC_LOCAL_CTRL,
7482                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7483                 } else {
7484                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7485                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7486                 }
7487
7488                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7489                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7490                         spin_unlock(&tp->lock);
7491                         schedule_work(&tp->reset_task);
7492                         return;
7493                 }
7494         }
7495
7496         /* This part only runs once per second. */
7497         if (!--tp->timer_counter) {
7498                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7499                         tg3_periodic_fetch_stats(tp);
7500
7501                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7502                         u32 mac_stat;
7503                         int phy_event;
7504
7505                         mac_stat = tr32(MAC_STATUS);
7506
7507                         phy_event = 0;
7508                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7509                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7510                                         phy_event = 1;
7511                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7512                                 phy_event = 1;
7513
7514                         if (phy_event)
7515                                 tg3_setup_phy(tp, 0);
7516                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7517                         u32 mac_stat = tr32(MAC_STATUS);
7518                         int need_setup = 0;
7519
7520                         if (netif_carrier_ok(tp->dev) &&
7521                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7522                                 need_setup = 1;
7523                         }
7524                         if (! netif_carrier_ok(tp->dev) &&
7525                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7526                                          MAC_STATUS_SIGNAL_DET))) {
7527                                 need_setup = 1;
7528                         }
7529                         if (need_setup) {
7530                                 if (!tp->serdes_counter) {
7531                                         tw32_f(MAC_MODE,
7532                                              (tp->mac_mode &
7533                                               ~MAC_MODE_PORT_MODE_MASK));
7534                                         udelay(40);
7535                                         tw32_f(MAC_MODE, tp->mac_mode);
7536                                         udelay(40);
7537                                 }
7538                                 tg3_setup_phy(tp, 0);
7539                         }
7540                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7541                         tg3_serdes_parallel_detect(tp);
7542
7543                 tp->timer_counter = tp->timer_multiplier;
7544         }
7545
7546         /* Heartbeat is only sent once every 2 seconds.
7547          *
7548          * The heartbeat is to tell the ASF firmware that the host
7549          * driver is still alive.  In the event that the OS crashes,
7550          * ASF needs to reset the hardware to free up the FIFO space
7551          * that may be filled with rx packets destined for the host.
7552          * If the FIFO is full, ASF will no longer function properly.
7553          *
7554          * Unintended resets have been reported on real time kernels
7555          * where the timer doesn't run on time.  Netpoll will also have
7556          * same problem.
7557          *
7558          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7559          * to check the ring condition when the heartbeat is expiring
7560          * before doing the reset.  This will prevent most unintended
7561          * resets.
7562          */
7563         if (!--tp->asf_counter) {
7564                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7565                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7566                         tg3_wait_for_event_ack(tp);
7567
7568                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7569                                       FWCMD_NICDRV_ALIVE3);
7570                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7571                         /* 5 seconds timeout */
7572                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7573
7574                         tg3_generate_fw_event(tp);
7575                 }
7576                 tp->asf_counter = tp->asf_multiplier;
7577         }
7578
7579         spin_unlock(&tp->lock);
7580
7581 restart_timer:
7582         tp->timer.expires = jiffies + tp->timer_offset;
7583         add_timer(&tp->timer);
7584 }
7585
7586 static int tg3_request_irq(struct tg3 *tp)
7587 {
7588         irq_handler_t fn;
7589         unsigned long flags;
7590         struct net_device *dev = tp->dev;
7591
7592         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7593                 fn = tg3_msi;
7594                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7595                         fn = tg3_msi_1shot;
7596                 flags = IRQF_SAMPLE_RANDOM;
7597         } else {
7598                 fn = tg3_interrupt;
7599                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7600                         fn = tg3_interrupt_tagged;
7601                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7602         }
7603         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7604 }
7605
7606 static int tg3_test_interrupt(struct tg3 *tp)
7607 {
7608         struct net_device *dev = tp->dev;
7609         int err, i, intr_ok = 0;
7610
7611         if (!netif_running(dev))
7612                 return -ENODEV;
7613
7614         tg3_disable_ints(tp);
7615
7616         free_irq(tp->pdev->irq, dev);
7617
7618         err = request_irq(tp->pdev->irq, tg3_test_isr,
7619                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7620         if (err)
7621                 return err;
7622
7623         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7624         tg3_enable_ints(tp);
7625
7626         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7627                HOSTCC_MODE_NOW);
7628
7629         for (i = 0; i < 5; i++) {
7630                 u32 int_mbox, misc_host_ctrl;
7631
7632                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7633                                         TG3_64BIT_REG_LOW);
7634                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7635
7636                 if ((int_mbox != 0) ||
7637                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7638                         intr_ok = 1;
7639                         break;
7640                 }
7641
7642                 msleep(10);
7643         }
7644
7645         tg3_disable_ints(tp);
7646
7647         free_irq(tp->pdev->irq, dev);
7648
7649         err = tg3_request_irq(tp);
7650
7651         if (err)
7652                 return err;
7653
7654         if (intr_ok)
7655                 return 0;
7656
7657         return -EIO;
7658 }
7659
7660 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7661  * successfully restored
7662  */
7663 static int tg3_test_msi(struct tg3 *tp)
7664 {
7665         struct net_device *dev = tp->dev;
7666         int err;
7667         u16 pci_cmd;
7668
7669         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7670                 return 0;
7671
7672         /* Turn off SERR reporting in case MSI terminates with Master
7673          * Abort.
7674          */
7675         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7676         pci_write_config_word(tp->pdev, PCI_COMMAND,
7677                               pci_cmd & ~PCI_COMMAND_SERR);
7678
7679         err = tg3_test_interrupt(tp);
7680
7681         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7682
7683         if (!err)
7684                 return 0;
7685
7686         /* other failures */
7687         if (err != -EIO)
7688                 return err;
7689
7690         /* MSI test failed, go back to INTx mode */
7691         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7692                "switching to INTx mode. Please report this failure to "
7693                "the PCI maintainer and include system chipset information.\n",
7694                        tp->dev->name);
7695
7696         free_irq(tp->pdev->irq, dev);
7697         pci_disable_msi(tp->pdev);
7698
7699         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7700
7701         err = tg3_request_irq(tp);
7702         if (err)
7703                 return err;
7704
7705         /* Need to reset the chip because the MSI cycle may have terminated
7706          * with Master Abort.
7707          */
7708         tg3_full_lock(tp, 1);
7709
7710         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7711         err = tg3_init_hw(tp, 1);
7712
7713         tg3_full_unlock(tp);
7714
7715         if (err)
7716                 free_irq(tp->pdev->irq, dev);
7717
7718         return err;
7719 }
7720
7721 static int tg3_request_firmware(struct tg3 *tp)
7722 {
7723         const __be32 *fw_data;
7724
7725         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7726                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7727                        tp->dev->name, tp->fw_needed);
7728                 return -ENOENT;
7729         }
7730
7731         fw_data = (void *)tp->fw->data;
7732
7733         /* Firmware blob starts with version numbers, followed by
7734          * start address and _full_ length including BSS sections
7735          * (which must be longer than the actual data, of course
7736          */
7737
7738         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7739         if (tp->fw_len < (tp->fw->size - 12)) {
7740                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7741                        tp->dev->name, tp->fw_len, tp->fw_needed);
7742                 release_firmware(tp->fw);
7743                 tp->fw = NULL;
7744                 return -EINVAL;
7745         }
7746
7747         /* We no longer need firmware; we have it. */
7748         tp->fw_needed = NULL;
7749         return 0;
7750 }
7751
7752 static int tg3_open(struct net_device *dev)
7753 {
7754         struct tg3 *tp = netdev_priv(dev);
7755         int err;
7756
7757         if (tp->fw_needed) {
7758                 err = tg3_request_firmware(tp);
7759                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7760                         if (err)
7761                                 return err;
7762                 } else if (err) {
7763                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7764                                tp->dev->name);
7765                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7766                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7767                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7768                                tp->dev->name);
7769                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7770                 }
7771         }
7772
7773         netif_carrier_off(tp->dev);
7774
7775         err = tg3_set_power_state(tp, PCI_D0);
7776         if (err)
7777                 return err;
7778
7779         tg3_full_lock(tp, 0);
7780
7781         tg3_disable_ints(tp);
7782         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7783
7784         tg3_full_unlock(tp);
7785
7786         /* The placement of this call is tied
7787          * to the setup and use of Host TX descriptors.
7788          */
7789         err = tg3_alloc_consistent(tp);
7790         if (err)
7791                 return err;
7792
7793         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7794                 /* All MSI supporting chips should support tagged
7795                  * status.  Assert that this is the case.
7796                  */
7797                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7798                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7799                                "Not using MSI.\n", tp->dev->name);
7800                 } else if (pci_enable_msi(tp->pdev) == 0) {
7801                         u32 msi_mode;
7802
7803                         msi_mode = tr32(MSGINT_MODE);
7804                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7805                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7806                 }
7807         }
7808         err = tg3_request_irq(tp);
7809
7810         if (err) {
7811                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7812                         pci_disable_msi(tp->pdev);
7813                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7814                 }
7815                 tg3_free_consistent(tp);
7816                 return err;
7817         }
7818
7819         napi_enable(&tp->napi);
7820
7821         tg3_full_lock(tp, 0);
7822
7823         err = tg3_init_hw(tp, 1);
7824         if (err) {
7825                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7826                 tg3_free_rings(tp);
7827         } else {
7828                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7829                         tp->timer_offset = HZ;
7830                 else
7831                         tp->timer_offset = HZ / 10;
7832
7833                 BUG_ON(tp->timer_offset > HZ);
7834                 tp->timer_counter = tp->timer_multiplier =
7835                         (HZ / tp->timer_offset);
7836                 tp->asf_counter = tp->asf_multiplier =
7837                         ((HZ / tp->timer_offset) * 2);
7838
7839                 init_timer(&tp->timer);
7840                 tp->timer.expires = jiffies + tp->timer_offset;
7841                 tp->timer.data = (unsigned long) tp;
7842                 tp->timer.function = tg3_timer;
7843         }
7844
7845         tg3_full_unlock(tp);
7846
7847         if (err) {
7848                 napi_disable(&tp->napi);
7849                 free_irq(tp->pdev->irq, dev);
7850                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7851                         pci_disable_msi(tp->pdev);
7852                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7853                 }
7854                 tg3_free_consistent(tp);
7855                 return err;
7856         }
7857
7858         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7859                 err = tg3_test_msi(tp);
7860
7861                 if (err) {
7862                         tg3_full_lock(tp, 0);
7863
7864                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7865                                 pci_disable_msi(tp->pdev);
7866                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7867                         }
7868                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7869                         tg3_free_rings(tp);
7870                         tg3_free_consistent(tp);
7871
7872                         tg3_full_unlock(tp);
7873
7874                         napi_disable(&tp->napi);
7875
7876                         return err;
7877                 }
7878
7879                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7880                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7881                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7882
7883                                 tw32(PCIE_TRANSACTION_CFG,
7884                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7885                         }
7886                 }
7887         }
7888
7889         tg3_phy_start(tp);
7890
7891         tg3_full_lock(tp, 0);
7892
7893         add_timer(&tp->timer);
7894         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7895         tg3_enable_ints(tp);
7896
7897         tg3_full_unlock(tp);
7898
7899         netif_start_queue(dev);
7900
7901         return 0;
7902 }
7903
7904 #if 0
7905 /*static*/ void tg3_dump_state(struct tg3 *tp)
7906 {
7907         u32 val32, val32_2, val32_3, val32_4, val32_5;
7908         u16 val16;
7909         int i;
7910
7911         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7912         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7913         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7914                val16, val32);
7915
7916         /* MAC block */
7917         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7918                tr32(MAC_MODE), tr32(MAC_STATUS));
7919         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7920                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7921         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7922                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7923         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7924                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7925
7926         /* Send data initiator control block */
7927         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7928                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7929         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7930                tr32(SNDDATAI_STATSCTRL));
7931
7932         /* Send data completion control block */
7933         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7934
7935         /* Send BD ring selector block */
7936         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7937                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7938
7939         /* Send BD initiator control block */
7940         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7941                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7942
7943         /* Send BD completion control block */
7944         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7945
7946         /* Receive list placement control block */
7947         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7948                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7949         printk("       RCVLPC_STATSCTRL[%08x]\n",
7950                tr32(RCVLPC_STATSCTRL));
7951
7952         /* Receive data and receive BD initiator control block */
7953         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7954                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7955
7956         /* Receive data completion control block */
7957         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7958                tr32(RCVDCC_MODE));
7959
7960         /* Receive BD initiator control block */
7961         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7962                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7963
7964         /* Receive BD completion control block */
7965         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7966                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7967
7968         /* Receive list selector control block */
7969         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7970                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7971
7972         /* Mbuf cluster free block */
7973         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7974                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7975
7976         /* Host coalescing control block */
7977         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7978                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7979         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7980                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7981                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7982         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7983                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7984                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7985         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7986                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7987         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7988                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7989
7990         /* Memory arbiter control block */
7991         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7992                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7993
7994         /* Buffer manager control block */
7995         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7996                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7997         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7998                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7999         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8000                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8001                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8002                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8003
8004         /* Read DMA control block */
8005         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8006                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8007
8008         /* Write DMA control block */
8009         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8010                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8011
8012         /* DMA completion block */
8013         printk("DEBUG: DMAC_MODE[%08x]\n",
8014                tr32(DMAC_MODE));
8015
8016         /* GRC block */
8017         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8018                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8019         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8020                tr32(GRC_LOCAL_CTRL));
8021
8022         /* TG3_BDINFOs */
8023         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8024                tr32(RCVDBDI_JUMBO_BD + 0x0),
8025                tr32(RCVDBDI_JUMBO_BD + 0x4),
8026                tr32(RCVDBDI_JUMBO_BD + 0x8),
8027                tr32(RCVDBDI_JUMBO_BD + 0xc));
8028         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8029                tr32(RCVDBDI_STD_BD + 0x0),
8030                tr32(RCVDBDI_STD_BD + 0x4),
8031                tr32(RCVDBDI_STD_BD + 0x8),
8032                tr32(RCVDBDI_STD_BD + 0xc));
8033         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8034                tr32(RCVDBDI_MINI_BD + 0x0),
8035                tr32(RCVDBDI_MINI_BD + 0x4),
8036                tr32(RCVDBDI_MINI_BD + 0x8),
8037                tr32(RCVDBDI_MINI_BD + 0xc));
8038
8039         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8040         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8041         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8042         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8043         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8044                val32, val32_2, val32_3, val32_4);
8045
8046         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8047         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8048         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8049         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8050         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8051                val32, val32_2, val32_3, val32_4);
8052
8053         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8054         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8055         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8056         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8057         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8058         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8059                val32, val32_2, val32_3, val32_4, val32_5);
8060
8061         /* SW status block */
8062         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8063                tp->hw_status->status,
8064                tp->hw_status->status_tag,
8065                tp->hw_status->rx_jumbo_consumer,
8066                tp->hw_status->rx_consumer,
8067                tp->hw_status->rx_mini_consumer,
8068                tp->hw_status->idx[0].rx_producer,
8069                tp->hw_status->idx[0].tx_consumer);
8070
8071         /* SW statistics block */
8072         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8073                ((u32 *)tp->hw_stats)[0],
8074                ((u32 *)tp->hw_stats)[1],
8075                ((u32 *)tp->hw_stats)[2],
8076                ((u32 *)tp->hw_stats)[3]);
8077
8078         /* Mailboxes */
8079         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8080                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8081                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8082                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8083                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8084
8085         /* NIC side send descriptors. */
8086         for (i = 0; i < 6; i++) {
8087                 unsigned long txd;
8088
8089                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8090                         + (i * sizeof(struct tg3_tx_buffer_desc));
8091                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8092                        i,
8093                        readl(txd + 0x0), readl(txd + 0x4),
8094                        readl(txd + 0x8), readl(txd + 0xc));
8095         }
8096
8097         /* NIC side RX descriptors. */
8098         for (i = 0; i < 6; i++) {
8099                 unsigned long rxd;
8100
8101                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8102                         + (i * sizeof(struct tg3_rx_buffer_desc));
8103                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8104                        i,
8105                        readl(rxd + 0x0), readl(rxd + 0x4),
8106                        readl(rxd + 0x8), readl(rxd + 0xc));
8107                 rxd += (4 * sizeof(u32));
8108                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8109                        i,
8110                        readl(rxd + 0x0), readl(rxd + 0x4),
8111                        readl(rxd + 0x8), readl(rxd + 0xc));
8112         }
8113
8114         for (i = 0; i < 6; i++) {
8115                 unsigned long rxd;
8116
8117                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8118                         + (i * sizeof(struct tg3_rx_buffer_desc));
8119                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8120                        i,
8121                        readl(rxd + 0x0), readl(rxd + 0x4),
8122                        readl(rxd + 0x8), readl(rxd + 0xc));
8123                 rxd += (4 * sizeof(u32));
8124                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8125                        i,
8126                        readl(rxd + 0x0), readl(rxd + 0x4),
8127                        readl(rxd + 0x8), readl(rxd + 0xc));
8128         }
8129 }
8130 #endif
8131
8132 static struct net_device_stats *tg3_get_stats(struct net_device *);
8133 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8134
8135 static int tg3_close(struct net_device *dev)
8136 {
8137         struct tg3 *tp = netdev_priv(dev);
8138
8139         napi_disable(&tp->napi);
8140         cancel_work_sync(&tp->reset_task);
8141
8142         netif_stop_queue(dev);
8143
8144         del_timer_sync(&tp->timer);
8145
8146         tg3_full_lock(tp, 1);
8147 #if 0
8148         tg3_dump_state(tp);
8149 #endif
8150
8151         tg3_disable_ints(tp);
8152
8153         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8154         tg3_free_rings(tp);
8155         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8156
8157         tg3_full_unlock(tp);
8158
8159         free_irq(tp->pdev->irq, dev);
8160         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8161                 pci_disable_msi(tp->pdev);
8162                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8163         }
8164
8165         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8166                sizeof(tp->net_stats_prev));
8167         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8168                sizeof(tp->estats_prev));
8169
8170         tg3_free_consistent(tp);
8171
8172         tg3_set_power_state(tp, PCI_D3hot);
8173
8174         netif_carrier_off(tp->dev);
8175
8176         return 0;
8177 }
8178
8179 static inline unsigned long get_stat64(tg3_stat64_t *val)
8180 {
8181         unsigned long ret;
8182
8183 #if (BITS_PER_LONG == 32)
8184         ret = val->low;
8185 #else
8186         ret = ((u64)val->high << 32) | ((u64)val->low);
8187 #endif
8188         return ret;
8189 }
8190
8191 static inline u64 get_estat64(tg3_stat64_t *val)
8192 {
8193        return ((u64)val->high << 32) | ((u64)val->low);
8194 }
8195
8196 static unsigned long calc_crc_errors(struct tg3 *tp)
8197 {
8198         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8199
8200         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8201             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8202              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8203                 u32 val;
8204
8205                 spin_lock_bh(&tp->lock);
8206                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8207                         tg3_writephy(tp, MII_TG3_TEST1,
8208                                      val | MII_TG3_TEST1_CRC_EN);
8209                         tg3_readphy(tp, 0x14, &val);
8210                 } else
8211                         val = 0;
8212                 spin_unlock_bh(&tp->lock);
8213
8214                 tp->phy_crc_errors += val;
8215
8216                 return tp->phy_crc_errors;
8217         }
8218
8219         return get_stat64(&hw_stats->rx_fcs_errors);
8220 }
8221
8222 #define ESTAT_ADD(member) \
8223         estats->member =        old_estats->member + \
8224                                 get_estat64(&hw_stats->member)
8225
8226 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8227 {
8228         struct tg3_ethtool_stats *estats = &tp->estats;
8229         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8230         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8231
8232         if (!hw_stats)
8233                 return old_estats;
8234
8235         ESTAT_ADD(rx_octets);
8236         ESTAT_ADD(rx_fragments);
8237         ESTAT_ADD(rx_ucast_packets);
8238         ESTAT_ADD(rx_mcast_packets);
8239         ESTAT_ADD(rx_bcast_packets);
8240         ESTAT_ADD(rx_fcs_errors);
8241         ESTAT_ADD(rx_align_errors);
8242         ESTAT_ADD(rx_xon_pause_rcvd);
8243         ESTAT_ADD(rx_xoff_pause_rcvd);
8244         ESTAT_ADD(rx_mac_ctrl_rcvd);
8245         ESTAT_ADD(rx_xoff_entered);
8246         ESTAT_ADD(rx_frame_too_long_errors);
8247         ESTAT_ADD(rx_jabbers);
8248         ESTAT_ADD(rx_undersize_packets);
8249         ESTAT_ADD(rx_in_length_errors);
8250         ESTAT_ADD(rx_out_length_errors);
8251         ESTAT_ADD(rx_64_or_less_octet_packets);
8252         ESTAT_ADD(rx_65_to_127_octet_packets);
8253         ESTAT_ADD(rx_128_to_255_octet_packets);
8254         ESTAT_ADD(rx_256_to_511_octet_packets);
8255         ESTAT_ADD(rx_512_to_1023_octet_packets);
8256         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8257         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8258         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8259         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8260         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8261
8262         ESTAT_ADD(tx_octets);
8263         ESTAT_ADD(tx_collisions);
8264         ESTAT_ADD(tx_xon_sent);
8265         ESTAT_ADD(tx_xoff_sent);
8266         ESTAT_ADD(tx_flow_control);
8267         ESTAT_ADD(tx_mac_errors);
8268         ESTAT_ADD(tx_single_collisions);
8269         ESTAT_ADD(tx_mult_collisions);
8270         ESTAT_ADD(tx_deferred);
8271         ESTAT_ADD(tx_excessive_collisions);
8272         ESTAT_ADD(tx_late_collisions);
8273         ESTAT_ADD(tx_collide_2times);
8274         ESTAT_ADD(tx_collide_3times);
8275         ESTAT_ADD(tx_collide_4times);
8276         ESTAT_ADD(tx_collide_5times);
8277         ESTAT_ADD(tx_collide_6times);
8278         ESTAT_ADD(tx_collide_7times);
8279         ESTAT_ADD(tx_collide_8times);
8280         ESTAT_ADD(tx_collide_9times);
8281         ESTAT_ADD(tx_collide_10times);
8282         ESTAT_ADD(tx_collide_11times);
8283         ESTAT_ADD(tx_collide_12times);
8284         ESTAT_ADD(tx_collide_13times);
8285         ESTAT_ADD(tx_collide_14times);
8286         ESTAT_ADD(tx_collide_15times);
8287         ESTAT_ADD(tx_ucast_packets);
8288         ESTAT_ADD(tx_mcast_packets);
8289         ESTAT_ADD(tx_bcast_packets);
8290         ESTAT_ADD(tx_carrier_sense_errors);
8291         ESTAT_ADD(tx_discards);
8292         ESTAT_ADD(tx_errors);
8293
8294         ESTAT_ADD(dma_writeq_full);
8295         ESTAT_ADD(dma_write_prioq_full);
8296         ESTAT_ADD(rxbds_empty);
8297         ESTAT_ADD(rx_discards);
8298         ESTAT_ADD(rx_errors);
8299         ESTAT_ADD(rx_threshold_hit);
8300
8301         ESTAT_ADD(dma_readq_full);
8302         ESTAT_ADD(dma_read_prioq_full);
8303         ESTAT_ADD(tx_comp_queue_full);
8304
8305         ESTAT_ADD(ring_set_send_prod_index);
8306         ESTAT_ADD(ring_status_update);
8307         ESTAT_ADD(nic_irqs);
8308         ESTAT_ADD(nic_avoided_irqs);
8309         ESTAT_ADD(nic_tx_threshold_hit);
8310
8311         return estats;
8312 }
8313
8314 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8315 {
8316         struct tg3 *tp = netdev_priv(dev);
8317         struct net_device_stats *stats = &tp->net_stats;
8318         struct net_device_stats *old_stats = &tp->net_stats_prev;
8319         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8320
8321         if (!hw_stats)
8322                 return old_stats;
8323
8324         stats->rx_packets = old_stats->rx_packets +
8325                 get_stat64(&hw_stats->rx_ucast_packets) +
8326                 get_stat64(&hw_stats->rx_mcast_packets) +
8327                 get_stat64(&hw_stats->rx_bcast_packets);
8328
8329         stats->tx_packets = old_stats->tx_packets +
8330                 get_stat64(&hw_stats->tx_ucast_packets) +
8331                 get_stat64(&hw_stats->tx_mcast_packets) +
8332                 get_stat64(&hw_stats->tx_bcast_packets);
8333
8334         stats->rx_bytes = old_stats->rx_bytes +
8335                 get_stat64(&hw_stats->rx_octets);
8336         stats->tx_bytes = old_stats->tx_bytes +
8337                 get_stat64(&hw_stats->tx_octets);
8338
8339         stats->rx_errors = old_stats->rx_errors +
8340                 get_stat64(&hw_stats->rx_errors);
8341         stats->tx_errors = old_stats->tx_errors +
8342                 get_stat64(&hw_stats->tx_errors) +
8343                 get_stat64(&hw_stats->tx_mac_errors) +
8344                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8345                 get_stat64(&hw_stats->tx_discards);
8346
8347         stats->multicast = old_stats->multicast +
8348                 get_stat64(&hw_stats->rx_mcast_packets);
8349         stats->collisions = old_stats->collisions +
8350                 get_stat64(&hw_stats->tx_collisions);
8351
8352         stats->rx_length_errors = old_stats->rx_length_errors +
8353                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8354                 get_stat64(&hw_stats->rx_undersize_packets);
8355
8356         stats->rx_over_errors = old_stats->rx_over_errors +
8357                 get_stat64(&hw_stats->rxbds_empty);
8358         stats->rx_frame_errors = old_stats->rx_frame_errors +
8359                 get_stat64(&hw_stats->rx_align_errors);
8360         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8361                 get_stat64(&hw_stats->tx_discards);
8362         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8363                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8364
8365         stats->rx_crc_errors = old_stats->rx_crc_errors +
8366                 calc_crc_errors(tp);
8367
8368         stats->rx_missed_errors = old_stats->rx_missed_errors +
8369                 get_stat64(&hw_stats->rx_discards);
8370
8371         return stats;
8372 }
8373
8374 static inline u32 calc_crc(unsigned char *buf, int len)
8375 {
8376         u32 reg;
8377         u32 tmp;
8378         int j, k;
8379
8380         reg = 0xffffffff;
8381
8382         for (j = 0; j < len; j++) {
8383                 reg ^= buf[j];
8384
8385                 for (k = 0; k < 8; k++) {
8386                         tmp = reg & 0x01;
8387
8388                         reg >>= 1;
8389
8390                         if (tmp) {
8391                                 reg ^= 0xedb88320;
8392                         }
8393                 }
8394         }
8395
8396         return ~reg;
8397 }
8398
8399 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8400 {
8401         /* accept or reject all multicast frames */
8402         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8403         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8404         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8405         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8406 }
8407
8408 static void __tg3_set_rx_mode(struct net_device *dev)
8409 {
8410         struct tg3 *tp = netdev_priv(dev);
8411         u32 rx_mode;
8412
8413         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8414                                   RX_MODE_KEEP_VLAN_TAG);
8415
8416         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8417          * flag clear.
8418          */
8419 #if TG3_VLAN_TAG_USED
8420         if (!tp->vlgrp &&
8421             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8422                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8423 #else
8424         /* By definition, VLAN is disabled always in this
8425          * case.
8426          */
8427         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8428                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8429 #endif
8430
8431         if (dev->flags & IFF_PROMISC) {
8432                 /* Promiscuous mode. */
8433                 rx_mode |= RX_MODE_PROMISC;
8434         } else if (dev->flags & IFF_ALLMULTI) {
8435                 /* Accept all multicast. */
8436                 tg3_set_multi (tp, 1);
8437         } else if (dev->mc_count < 1) {
8438                 /* Reject all multicast. */
8439                 tg3_set_multi (tp, 0);
8440         } else {
8441                 /* Accept one or more multicast(s). */
8442                 struct dev_mc_list *mclist;
8443                 unsigned int i;
8444                 u32 mc_filter[4] = { 0, };
8445                 u32 regidx;
8446                 u32 bit;
8447                 u32 crc;
8448
8449                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8450                      i++, mclist = mclist->next) {
8451
8452                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8453                         bit = ~crc & 0x7f;
8454                         regidx = (bit & 0x60) >> 5;
8455                         bit &= 0x1f;
8456                         mc_filter[regidx] |= (1 << bit);
8457                 }
8458
8459                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8460                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8461                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8462                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8463         }
8464
8465         if (rx_mode != tp->rx_mode) {
8466                 tp->rx_mode = rx_mode;
8467                 tw32_f(MAC_RX_MODE, rx_mode);
8468                 udelay(10);
8469         }
8470 }
8471
8472 static void tg3_set_rx_mode(struct net_device *dev)
8473 {
8474         struct tg3 *tp = netdev_priv(dev);
8475
8476         if (!netif_running(dev))
8477                 return;
8478
8479         tg3_full_lock(tp, 0);
8480         __tg3_set_rx_mode(dev);
8481         tg3_full_unlock(tp);
8482 }
8483
8484 #define TG3_REGDUMP_LEN         (32 * 1024)
8485
8486 static int tg3_get_regs_len(struct net_device *dev)
8487 {
8488         return TG3_REGDUMP_LEN;
8489 }
8490
8491 static void tg3_get_regs(struct net_device *dev,
8492                 struct ethtool_regs *regs, void *_p)
8493 {
8494         u32 *p = _p;
8495         struct tg3 *tp = netdev_priv(dev);
8496         u8 *orig_p = _p;
8497         int i;
8498
8499         regs->version = 0;
8500
8501         memset(p, 0, TG3_REGDUMP_LEN);
8502
8503         if (tp->link_config.phy_is_low_power)
8504                 return;
8505
8506         tg3_full_lock(tp, 0);
8507
8508 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8509 #define GET_REG32_LOOP(base,len)                \
8510 do {    p = (u32 *)(orig_p + (base));           \
8511         for (i = 0; i < len; i += 4)            \
8512                 __GET_REG32((base) + i);        \
8513 } while (0)
8514 #define GET_REG32_1(reg)                        \
8515 do {    p = (u32 *)(orig_p + (reg));            \
8516         __GET_REG32((reg));                     \
8517 } while (0)
8518
8519         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8520         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8521         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8522         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8523         GET_REG32_1(SNDDATAC_MODE);
8524         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8525         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8526         GET_REG32_1(SNDBDC_MODE);
8527         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8528         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8529         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8530         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8531         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8532         GET_REG32_1(RCVDCC_MODE);
8533         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8534         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8535         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8536         GET_REG32_1(MBFREE_MODE);
8537         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8538         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8539         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8540         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8541         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8542         GET_REG32_1(RX_CPU_MODE);
8543         GET_REG32_1(RX_CPU_STATE);
8544         GET_REG32_1(RX_CPU_PGMCTR);
8545         GET_REG32_1(RX_CPU_HWBKPT);
8546         GET_REG32_1(TX_CPU_MODE);
8547         GET_REG32_1(TX_CPU_STATE);
8548         GET_REG32_1(TX_CPU_PGMCTR);
8549         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8550         GET_REG32_LOOP(FTQ_RESET, 0x120);
8551         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8552         GET_REG32_1(DMAC_MODE);
8553         GET_REG32_LOOP(GRC_MODE, 0x4c);
8554         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8555                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8556
8557 #undef __GET_REG32
8558 #undef GET_REG32_LOOP
8559 #undef GET_REG32_1
8560
8561         tg3_full_unlock(tp);
8562 }
8563
8564 static int tg3_get_eeprom_len(struct net_device *dev)
8565 {
8566         struct tg3 *tp = netdev_priv(dev);
8567
8568         return tp->nvram_size;
8569 }
8570
8571 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8572 {
8573         struct tg3 *tp = netdev_priv(dev);
8574         int ret;
8575         u8  *pd;
8576         u32 i, offset, len, b_offset, b_count;
8577         __be32 val;
8578
8579         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8580                 return -EINVAL;
8581
8582         if (tp->link_config.phy_is_low_power)
8583                 return -EAGAIN;
8584
8585         offset = eeprom->offset;
8586         len = eeprom->len;
8587         eeprom->len = 0;
8588
8589         eeprom->magic = TG3_EEPROM_MAGIC;
8590
8591         if (offset & 3) {
8592                 /* adjustments to start on required 4 byte boundary */
8593                 b_offset = offset & 3;
8594                 b_count = 4 - b_offset;
8595                 if (b_count > len) {
8596                         /* i.e. offset=1 len=2 */
8597                         b_count = len;
8598                 }
8599                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8600                 if (ret)
8601                         return ret;
8602                 memcpy(data, ((char*)&val) + b_offset, b_count);
8603                 len -= b_count;
8604                 offset += b_count;
8605                 eeprom->len += b_count;
8606         }
8607
8608         /* read bytes upto the last 4 byte boundary */
8609         pd = &data[eeprom->len];
8610         for (i = 0; i < (len - (len & 3)); i += 4) {
8611                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8612                 if (ret) {
8613                         eeprom->len += i;
8614                         return ret;
8615                 }
8616                 memcpy(pd + i, &val, 4);
8617         }
8618         eeprom->len += i;
8619
8620         if (len & 3) {
8621                 /* read last bytes not ending on 4 byte boundary */
8622                 pd = &data[eeprom->len];
8623                 b_count = len & 3;
8624                 b_offset = offset + len - b_count;
8625                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8626                 if (ret)
8627                         return ret;
8628                 memcpy(pd, &val, b_count);
8629                 eeprom->len += b_count;
8630         }
8631         return 0;
8632 }
8633
8634 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8635
8636 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8637 {
8638         struct tg3 *tp = netdev_priv(dev);
8639         int ret;
8640         u32 offset, len, b_offset, odd_len;
8641         u8 *buf;
8642         __be32 start, end;
8643
8644         if (tp->link_config.phy_is_low_power)
8645                 return -EAGAIN;
8646
8647         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8648             eeprom->magic != TG3_EEPROM_MAGIC)
8649                 return -EINVAL;
8650
8651         offset = eeprom->offset;
8652         len = eeprom->len;
8653
8654         if ((b_offset = (offset & 3))) {
8655                 /* adjustments to start on required 4 byte boundary */
8656                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8657                 if (ret)
8658                         return ret;
8659                 len += b_offset;
8660                 offset &= ~3;
8661                 if (len < 4)
8662                         len = 4;
8663         }
8664
8665         odd_len = 0;
8666         if (len & 3) {
8667                 /* adjustments to end on required 4 byte boundary */
8668                 odd_len = 1;
8669                 len = (len + 3) & ~3;
8670                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8671                 if (ret)
8672                         return ret;
8673         }
8674
8675         buf = data;
8676         if (b_offset || odd_len) {
8677                 buf = kmalloc(len, GFP_KERNEL);
8678                 if (!buf)
8679                         return -ENOMEM;
8680                 if (b_offset)
8681                         memcpy(buf, &start, 4);
8682                 if (odd_len)
8683                         memcpy(buf+len-4, &end, 4);
8684                 memcpy(buf + b_offset, data, eeprom->len);
8685         }
8686
8687         ret = tg3_nvram_write_block(tp, offset, len, buf);
8688
8689         if (buf != data)
8690                 kfree(buf);
8691
8692         return ret;
8693 }
8694
8695 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8696 {
8697         struct tg3 *tp = netdev_priv(dev);
8698
8699         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8700                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8701                         return -EAGAIN;
8702                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8703         }
8704
8705         cmd->supported = (SUPPORTED_Autoneg);
8706
8707         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8708                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8709                                    SUPPORTED_1000baseT_Full);
8710
8711         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8712                 cmd->supported |= (SUPPORTED_100baseT_Half |
8713                                   SUPPORTED_100baseT_Full |
8714                                   SUPPORTED_10baseT_Half |
8715                                   SUPPORTED_10baseT_Full |
8716                                   SUPPORTED_TP);
8717                 cmd->port = PORT_TP;
8718         } else {
8719                 cmd->supported |= SUPPORTED_FIBRE;
8720                 cmd->port = PORT_FIBRE;
8721         }
8722
8723         cmd->advertising = tp->link_config.advertising;
8724         if (netif_running(dev)) {
8725                 cmd->speed = tp->link_config.active_speed;
8726                 cmd->duplex = tp->link_config.active_duplex;
8727         }
8728         cmd->phy_address = PHY_ADDR;
8729         cmd->transceiver = XCVR_INTERNAL;
8730         cmd->autoneg = tp->link_config.autoneg;
8731         cmd->maxtxpkt = 0;
8732         cmd->maxrxpkt = 0;
8733         return 0;
8734 }
8735
8736 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8737 {
8738         struct tg3 *tp = netdev_priv(dev);
8739
8740         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8741                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8742                         return -EAGAIN;
8743                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8744         }
8745
8746         if (cmd->autoneg != AUTONEG_ENABLE &&
8747             cmd->autoneg != AUTONEG_DISABLE)
8748                 return -EINVAL;
8749
8750         if (cmd->autoneg == AUTONEG_DISABLE &&
8751             cmd->duplex != DUPLEX_FULL &&
8752             cmd->duplex != DUPLEX_HALF)
8753                 return -EINVAL;
8754
8755         if (cmd->autoneg == AUTONEG_ENABLE) {
8756                 u32 mask = ADVERTISED_Autoneg |
8757                            ADVERTISED_Pause |
8758                            ADVERTISED_Asym_Pause;
8759
8760                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8761                         mask |= ADVERTISED_1000baseT_Half |
8762                                 ADVERTISED_1000baseT_Full;
8763
8764                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8765                         mask |= ADVERTISED_100baseT_Half |
8766                                 ADVERTISED_100baseT_Full |
8767                                 ADVERTISED_10baseT_Half |
8768                                 ADVERTISED_10baseT_Full |
8769                                 ADVERTISED_TP;
8770                 else
8771                         mask |= ADVERTISED_FIBRE;
8772
8773                 if (cmd->advertising & ~mask)
8774                         return -EINVAL;
8775
8776                 mask &= (ADVERTISED_1000baseT_Half |
8777                          ADVERTISED_1000baseT_Full |
8778                          ADVERTISED_100baseT_Half |
8779                          ADVERTISED_100baseT_Full |
8780                          ADVERTISED_10baseT_Half |
8781                          ADVERTISED_10baseT_Full);
8782
8783                 cmd->advertising &= mask;
8784         } else {
8785                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8786                         if (cmd->speed != SPEED_1000)
8787                                 return -EINVAL;
8788
8789                         if (cmd->duplex != DUPLEX_FULL)
8790                                 return -EINVAL;
8791                 } else {
8792                         if (cmd->speed != SPEED_100 &&
8793                             cmd->speed != SPEED_10)
8794                                 return -EINVAL;
8795                 }
8796         }
8797
8798         tg3_full_lock(tp, 0);
8799
8800         tp->link_config.autoneg = cmd->autoneg;
8801         if (cmd->autoneg == AUTONEG_ENABLE) {
8802                 tp->link_config.advertising = (cmd->advertising |
8803                                               ADVERTISED_Autoneg);
8804                 tp->link_config.speed = SPEED_INVALID;
8805                 tp->link_config.duplex = DUPLEX_INVALID;
8806         } else {
8807                 tp->link_config.advertising = 0;
8808                 tp->link_config.speed = cmd->speed;
8809                 tp->link_config.duplex = cmd->duplex;
8810         }
8811
8812         tp->link_config.orig_speed = tp->link_config.speed;
8813         tp->link_config.orig_duplex = tp->link_config.duplex;
8814         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8815
8816         if (netif_running(dev))
8817                 tg3_setup_phy(tp, 1);
8818
8819         tg3_full_unlock(tp);
8820
8821         return 0;
8822 }
8823
8824 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8825 {
8826         struct tg3 *tp = netdev_priv(dev);
8827
8828         strcpy(info->driver, DRV_MODULE_NAME);
8829         strcpy(info->version, DRV_MODULE_VERSION);
8830         strcpy(info->fw_version, tp->fw_ver);
8831         strcpy(info->bus_info, pci_name(tp->pdev));
8832 }
8833
8834 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8835 {
8836         struct tg3 *tp = netdev_priv(dev);
8837
8838         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8839             device_can_wakeup(&tp->pdev->dev))
8840                 wol->supported = WAKE_MAGIC;
8841         else
8842                 wol->supported = 0;
8843         wol->wolopts = 0;
8844         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8845             device_can_wakeup(&tp->pdev->dev))
8846                 wol->wolopts = WAKE_MAGIC;
8847         memset(&wol->sopass, 0, sizeof(wol->sopass));
8848 }
8849
8850 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8851 {
8852         struct tg3 *tp = netdev_priv(dev);
8853         struct device *dp = &tp->pdev->dev;
8854
8855         if (wol->wolopts & ~WAKE_MAGIC)
8856                 return -EINVAL;
8857         if ((wol->wolopts & WAKE_MAGIC) &&
8858             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8859                 return -EINVAL;
8860
8861         spin_lock_bh(&tp->lock);
8862         if (wol->wolopts & WAKE_MAGIC) {
8863                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8864                 device_set_wakeup_enable(dp, true);
8865         } else {
8866                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8867                 device_set_wakeup_enable(dp, false);
8868         }
8869         spin_unlock_bh(&tp->lock);
8870
8871         return 0;
8872 }
8873
8874 static u32 tg3_get_msglevel(struct net_device *dev)
8875 {
8876         struct tg3 *tp = netdev_priv(dev);
8877         return tp->msg_enable;
8878 }
8879
8880 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8881 {
8882         struct tg3 *tp = netdev_priv(dev);
8883         tp->msg_enable = value;
8884 }
8885
8886 static int tg3_set_tso(struct net_device *dev, u32 value)
8887 {
8888         struct tg3 *tp = netdev_priv(dev);
8889
8890         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8891                 if (value)
8892                         return -EINVAL;
8893                 return 0;
8894         }
8895         if ((dev->features & NETIF_F_IPV6_CSUM) &&
8896             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8897                 if (value) {
8898                         dev->features |= NETIF_F_TSO6;
8899                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8900                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8901                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8902                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8903                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8904                                 dev->features |= NETIF_F_TSO_ECN;
8905                 } else
8906                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8907         }
8908         return ethtool_op_set_tso(dev, value);
8909 }
8910
8911 static int tg3_nway_reset(struct net_device *dev)
8912 {
8913         struct tg3 *tp = netdev_priv(dev);
8914         int r;
8915
8916         if (!netif_running(dev))
8917                 return -EAGAIN;
8918
8919         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8920                 return -EINVAL;
8921
8922         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8923                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8924                         return -EAGAIN;
8925                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8926         } else {
8927                 u32 bmcr;
8928
8929                 spin_lock_bh(&tp->lock);
8930                 r = -EINVAL;
8931                 tg3_readphy(tp, MII_BMCR, &bmcr);
8932                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8933                     ((bmcr & BMCR_ANENABLE) ||
8934                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8935                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8936                                                    BMCR_ANENABLE);
8937                         r = 0;
8938                 }
8939                 spin_unlock_bh(&tp->lock);
8940         }
8941
8942         return r;
8943 }
8944
8945 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8946 {
8947         struct tg3 *tp = netdev_priv(dev);
8948
8949         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8950         ering->rx_mini_max_pending = 0;
8951         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8952                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8953         else
8954                 ering->rx_jumbo_max_pending = 0;
8955
8956         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8957
8958         ering->rx_pending = tp->rx_pending;
8959         ering->rx_mini_pending = 0;
8960         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8961                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8962         else
8963                 ering->rx_jumbo_pending = 0;
8964
8965         ering->tx_pending = tp->tx_pending;
8966 }
8967
8968 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8969 {
8970         struct tg3 *tp = netdev_priv(dev);
8971         int irq_sync = 0, err = 0;
8972
8973         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8974             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8975             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8976             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8977             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8978              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8979                 return -EINVAL;
8980
8981         if (netif_running(dev)) {
8982                 tg3_phy_stop(tp);
8983                 tg3_netif_stop(tp);
8984                 irq_sync = 1;
8985         }
8986
8987         tg3_full_lock(tp, irq_sync);
8988
8989         tp->rx_pending = ering->rx_pending;
8990
8991         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8992             tp->rx_pending > 63)
8993                 tp->rx_pending = 63;
8994         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8995         tp->tx_pending = ering->tx_pending;
8996
8997         if (netif_running(dev)) {
8998                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8999                 err = tg3_restart_hw(tp, 1);
9000                 if (!err)
9001                         tg3_netif_start(tp);
9002         }
9003
9004         tg3_full_unlock(tp);
9005
9006         if (irq_sync && !err)
9007                 tg3_phy_start(tp);
9008
9009         return err;
9010 }
9011
9012 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9013 {
9014         struct tg3 *tp = netdev_priv(dev);
9015
9016         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9017
9018         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9019                 epause->rx_pause = 1;
9020         else
9021                 epause->rx_pause = 0;
9022
9023         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9024                 epause->tx_pause = 1;
9025         else
9026                 epause->tx_pause = 0;
9027 }
9028
9029 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9030 {
9031         struct tg3 *tp = netdev_priv(dev);
9032         int err = 0;
9033
9034         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9035                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9036                         return -EAGAIN;
9037
9038                 if (epause->autoneg) {
9039                         u32 newadv;
9040                         struct phy_device *phydev;
9041
9042                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9043
9044                         if (epause->rx_pause) {
9045                                 if (epause->tx_pause)
9046                                         newadv = ADVERTISED_Pause;
9047                                 else
9048                                         newadv = ADVERTISED_Pause |
9049                                                  ADVERTISED_Asym_Pause;
9050                         } else if (epause->tx_pause) {
9051                                 newadv = ADVERTISED_Asym_Pause;
9052                         } else
9053                                 newadv = 0;
9054
9055                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9056                                 u32 oldadv = phydev->advertising &
9057                                              (ADVERTISED_Pause |
9058                                               ADVERTISED_Asym_Pause);
9059                                 if (oldadv != newadv) {
9060                                         phydev->advertising &=
9061                                                 ~(ADVERTISED_Pause |
9062                                                   ADVERTISED_Asym_Pause);
9063                                         phydev->advertising |= newadv;
9064                                         err = phy_start_aneg(phydev);
9065                                 }
9066                         } else {
9067                                 tp->link_config.advertising &=
9068                                                 ~(ADVERTISED_Pause |
9069                                                   ADVERTISED_Asym_Pause);
9070                                 tp->link_config.advertising |= newadv;
9071                         }
9072                 } else {
9073                         if (epause->rx_pause)
9074                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9075                         else
9076                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9077
9078                         if (epause->tx_pause)
9079                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9080                         else
9081                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9082
9083                         if (netif_running(dev))
9084                                 tg3_setup_flow_control(tp, 0, 0);
9085                 }
9086         } else {
9087                 int irq_sync = 0;
9088
9089                 if (netif_running(dev)) {
9090                         tg3_netif_stop(tp);
9091                         irq_sync = 1;
9092                 }
9093
9094                 tg3_full_lock(tp, irq_sync);
9095
9096                 if (epause->autoneg)
9097                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9098                 else
9099                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9100                 if (epause->rx_pause)
9101                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9102                 else
9103                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9104                 if (epause->tx_pause)
9105                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9106                 else
9107                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9108
9109                 if (netif_running(dev)) {
9110                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9111                         err = tg3_restart_hw(tp, 1);
9112                         if (!err)
9113                                 tg3_netif_start(tp);
9114                 }
9115
9116                 tg3_full_unlock(tp);
9117         }
9118
9119         return err;
9120 }
9121
9122 static u32 tg3_get_rx_csum(struct net_device *dev)
9123 {
9124         struct tg3 *tp = netdev_priv(dev);
9125         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9126 }
9127
9128 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9129 {
9130         struct tg3 *tp = netdev_priv(dev);
9131
9132         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9133                 if (data != 0)
9134                         return -EINVAL;
9135                 return 0;
9136         }
9137
9138         spin_lock_bh(&tp->lock);
9139         if (data)
9140                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9141         else
9142                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9143         spin_unlock_bh(&tp->lock);
9144
9145         return 0;
9146 }
9147
9148 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9149 {
9150         struct tg3 *tp = netdev_priv(dev);
9151
9152         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9153                 if (data != 0)
9154                         return -EINVAL;
9155                 return 0;
9156         }
9157
9158         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9159                 ethtool_op_set_tx_ipv6_csum(dev, data);
9160         else
9161                 ethtool_op_set_tx_csum(dev, data);
9162
9163         return 0;
9164 }
9165
9166 static int tg3_get_sset_count (struct net_device *dev, int sset)
9167 {
9168         switch (sset) {
9169         case ETH_SS_TEST:
9170                 return TG3_NUM_TEST;
9171         case ETH_SS_STATS:
9172                 return TG3_NUM_STATS;
9173         default:
9174                 return -EOPNOTSUPP;
9175         }
9176 }
9177
9178 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9179 {
9180         switch (stringset) {
9181         case ETH_SS_STATS:
9182                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9183                 break;
9184         case ETH_SS_TEST:
9185                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9186                 break;
9187         default:
9188                 WARN_ON(1);     /* we need a WARN() */
9189                 break;
9190         }
9191 }
9192
9193 static int tg3_phys_id(struct net_device *dev, u32 data)
9194 {
9195         struct tg3 *tp = netdev_priv(dev);
9196         int i;
9197
9198         if (!netif_running(tp->dev))
9199                 return -EAGAIN;
9200
9201         if (data == 0)
9202                 data = UINT_MAX / 2;
9203
9204         for (i = 0; i < (data * 2); i++) {
9205                 if ((i % 2) == 0)
9206                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9207                                            LED_CTRL_1000MBPS_ON |
9208                                            LED_CTRL_100MBPS_ON |
9209                                            LED_CTRL_10MBPS_ON |
9210                                            LED_CTRL_TRAFFIC_OVERRIDE |
9211                                            LED_CTRL_TRAFFIC_BLINK |
9212                                            LED_CTRL_TRAFFIC_LED);
9213
9214                 else
9215                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9216                                            LED_CTRL_TRAFFIC_OVERRIDE);
9217
9218                 if (msleep_interruptible(500))
9219                         break;
9220         }
9221         tw32(MAC_LED_CTRL, tp->led_ctrl);
9222         return 0;
9223 }
9224
9225 static void tg3_get_ethtool_stats (struct net_device *dev,
9226                                    struct ethtool_stats *estats, u64 *tmp_stats)
9227 {
9228         struct tg3 *tp = netdev_priv(dev);
9229         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9230 }
9231
9232 #define NVRAM_TEST_SIZE 0x100
9233 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9234 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9235 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9236 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9237 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9238
9239 static int tg3_test_nvram(struct tg3 *tp)
9240 {
9241         u32 csum, magic;
9242         __be32 *buf;
9243         int i, j, k, err = 0, size;
9244
9245         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9246                 return 0;
9247
9248         if (tg3_nvram_read(tp, 0, &magic) != 0)
9249                 return -EIO;
9250
9251         if (magic == TG3_EEPROM_MAGIC)
9252                 size = NVRAM_TEST_SIZE;
9253         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9254                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9255                     TG3_EEPROM_SB_FORMAT_1) {
9256                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9257                         case TG3_EEPROM_SB_REVISION_0:
9258                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9259                                 break;
9260                         case TG3_EEPROM_SB_REVISION_2:
9261                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9262                                 break;
9263                         case TG3_EEPROM_SB_REVISION_3:
9264                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9265                                 break;
9266                         default:
9267                                 return 0;
9268                         }
9269                 } else
9270                         return 0;
9271         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9272                 size = NVRAM_SELFBOOT_HW_SIZE;
9273         else
9274                 return -EIO;
9275
9276         buf = kmalloc(size, GFP_KERNEL);
9277         if (buf == NULL)
9278                 return -ENOMEM;
9279
9280         err = -EIO;
9281         for (i = 0, j = 0; i < size; i += 4, j++) {
9282                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9283                 if (err)
9284                         break;
9285         }
9286         if (i < size)
9287                 goto out;
9288
9289         /* Selfboot format */
9290         magic = be32_to_cpu(buf[0]);
9291         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9292             TG3_EEPROM_MAGIC_FW) {
9293                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9294
9295                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9296                     TG3_EEPROM_SB_REVISION_2) {
9297                         /* For rev 2, the csum doesn't include the MBA. */
9298                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9299                                 csum8 += buf8[i];
9300                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9301                                 csum8 += buf8[i];
9302                 } else {
9303                         for (i = 0; i < size; i++)
9304                                 csum8 += buf8[i];
9305                 }
9306
9307                 if (csum8 == 0) {
9308                         err = 0;
9309                         goto out;
9310                 }
9311
9312                 err = -EIO;
9313                 goto out;
9314         }
9315
9316         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9317             TG3_EEPROM_MAGIC_HW) {
9318                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9319                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9320                 u8 *buf8 = (u8 *) buf;
9321
9322                 /* Separate the parity bits and the data bytes.  */
9323                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9324                         if ((i == 0) || (i == 8)) {
9325                                 int l;
9326                                 u8 msk;
9327
9328                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9329                                         parity[k++] = buf8[i] & msk;
9330                                 i++;
9331                         }
9332                         else if (i == 16) {
9333                                 int l;
9334                                 u8 msk;
9335
9336                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9337                                         parity[k++] = buf8[i] & msk;
9338                                 i++;
9339
9340                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9341                                         parity[k++] = buf8[i] & msk;
9342                                 i++;
9343                         }
9344                         data[j++] = buf8[i];
9345                 }
9346
9347                 err = -EIO;
9348                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9349                         u8 hw8 = hweight8(data[i]);
9350
9351                         if ((hw8 & 0x1) && parity[i])
9352                                 goto out;
9353                         else if (!(hw8 & 0x1) && !parity[i])
9354                                 goto out;
9355                 }
9356                 err = 0;
9357                 goto out;
9358         }
9359
9360         /* Bootstrap checksum at offset 0x10 */
9361         csum = calc_crc((unsigned char *) buf, 0x10);
9362         if (csum != be32_to_cpu(buf[0x10/4]))
9363                 goto out;
9364
9365         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9366         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9367         if (csum != be32_to_cpu(buf[0xfc/4]))
9368                 goto out;
9369
9370         err = 0;
9371
9372 out:
9373         kfree(buf);
9374         return err;
9375 }
9376
9377 #define TG3_SERDES_TIMEOUT_SEC  2
9378 #define TG3_COPPER_TIMEOUT_SEC  6
9379
9380 static int tg3_test_link(struct tg3 *tp)
9381 {
9382         int i, max;
9383
9384         if (!netif_running(tp->dev))
9385                 return -ENODEV;
9386
9387         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9388                 max = TG3_SERDES_TIMEOUT_SEC;
9389         else
9390                 max = TG3_COPPER_TIMEOUT_SEC;
9391
9392         for (i = 0; i < max; i++) {
9393                 if (netif_carrier_ok(tp->dev))
9394                         return 0;
9395
9396                 if (msleep_interruptible(1000))
9397                         break;
9398         }
9399
9400         return -EIO;
9401 }
9402
9403 /* Only test the commonly used registers */
9404 static int tg3_test_registers(struct tg3 *tp)
9405 {
9406         int i, is_5705, is_5750;
9407         u32 offset, read_mask, write_mask, val, save_val, read_val;
9408         static struct {
9409                 u16 offset;
9410                 u16 flags;
9411 #define TG3_FL_5705     0x1
9412 #define TG3_FL_NOT_5705 0x2
9413 #define TG3_FL_NOT_5788 0x4
9414 #define TG3_FL_NOT_5750 0x8
9415                 u32 read_mask;
9416                 u32 write_mask;
9417         } reg_tbl[] = {
9418                 /* MAC Control Registers */
9419                 { MAC_MODE, TG3_FL_NOT_5705,
9420                         0x00000000, 0x00ef6f8c },
9421                 { MAC_MODE, TG3_FL_5705,
9422                         0x00000000, 0x01ef6b8c },
9423                 { MAC_STATUS, TG3_FL_NOT_5705,
9424                         0x03800107, 0x00000000 },
9425                 { MAC_STATUS, TG3_FL_5705,
9426                         0x03800100, 0x00000000 },
9427                 { MAC_ADDR_0_HIGH, 0x0000,
9428                         0x00000000, 0x0000ffff },
9429                 { MAC_ADDR_0_LOW, 0x0000,
9430                         0x00000000, 0xffffffff },
9431                 { MAC_RX_MTU_SIZE, 0x0000,
9432                         0x00000000, 0x0000ffff },
9433                 { MAC_TX_MODE, 0x0000,
9434                         0x00000000, 0x00000070 },
9435                 { MAC_TX_LENGTHS, 0x0000,
9436                         0x00000000, 0x00003fff },
9437                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9438                         0x00000000, 0x000007fc },
9439                 { MAC_RX_MODE, TG3_FL_5705,
9440                         0x00000000, 0x000007dc },
9441                 { MAC_HASH_REG_0, 0x0000,
9442                         0x00000000, 0xffffffff },
9443                 { MAC_HASH_REG_1, 0x0000,
9444                         0x00000000, 0xffffffff },
9445                 { MAC_HASH_REG_2, 0x0000,
9446                         0x00000000, 0xffffffff },
9447                 { MAC_HASH_REG_3, 0x0000,
9448                         0x00000000, 0xffffffff },
9449
9450                 /* Receive Data and Receive BD Initiator Control Registers. */
9451                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9452                         0x00000000, 0xffffffff },
9453                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9454                         0x00000000, 0xffffffff },
9455                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9456                         0x00000000, 0x00000003 },
9457                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9458                         0x00000000, 0xffffffff },
9459                 { RCVDBDI_STD_BD+0, 0x0000,
9460                         0x00000000, 0xffffffff },
9461                 { RCVDBDI_STD_BD+4, 0x0000,
9462                         0x00000000, 0xffffffff },
9463                 { RCVDBDI_STD_BD+8, 0x0000,
9464                         0x00000000, 0xffff0002 },
9465                 { RCVDBDI_STD_BD+0xc, 0x0000,
9466                         0x00000000, 0xffffffff },
9467
9468                 /* Receive BD Initiator Control Registers. */
9469                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9470                         0x00000000, 0xffffffff },
9471                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9472                         0x00000000, 0x000003ff },
9473                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9474                         0x00000000, 0xffffffff },
9475
9476                 /* Host Coalescing Control Registers. */
9477                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9478                         0x00000000, 0x00000004 },
9479                 { HOSTCC_MODE, TG3_FL_5705,
9480                         0x00000000, 0x000000f6 },
9481                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9482                         0x00000000, 0xffffffff },
9483                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9484                         0x00000000, 0x000003ff },
9485                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9486                         0x00000000, 0xffffffff },
9487                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9488                         0x00000000, 0x000003ff },
9489                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9490                         0x00000000, 0xffffffff },
9491                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9492                         0x00000000, 0x000000ff },
9493                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9494                         0x00000000, 0xffffffff },
9495                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9496                         0x00000000, 0x000000ff },
9497                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9498                         0x00000000, 0xffffffff },
9499                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9500                         0x00000000, 0xffffffff },
9501                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9502                         0x00000000, 0xffffffff },
9503                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9504                         0x00000000, 0x000000ff },
9505                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9506                         0x00000000, 0xffffffff },
9507                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9508                         0x00000000, 0x000000ff },
9509                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9510                         0x00000000, 0xffffffff },
9511                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9512                         0x00000000, 0xffffffff },
9513                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9514                         0x00000000, 0xffffffff },
9515                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9516                         0x00000000, 0xffffffff },
9517                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9518                         0x00000000, 0xffffffff },
9519                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9520                         0xffffffff, 0x00000000 },
9521                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9522                         0xffffffff, 0x00000000 },
9523
9524                 /* Buffer Manager Control Registers. */
9525                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9526                         0x00000000, 0x007fff80 },
9527                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9528                         0x00000000, 0x007fffff },
9529                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9530                         0x00000000, 0x0000003f },
9531                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9532                         0x00000000, 0x000001ff },
9533                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9534                         0x00000000, 0x000001ff },
9535                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9536                         0xffffffff, 0x00000000 },
9537                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9538                         0xffffffff, 0x00000000 },
9539
9540                 /* Mailbox Registers */
9541                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9542                         0x00000000, 0x000001ff },
9543                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9544                         0x00000000, 0x000001ff },
9545                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9546                         0x00000000, 0x000007ff },
9547                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9548                         0x00000000, 0x000001ff },
9549
9550                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9551         };
9552
9553         is_5705 = is_5750 = 0;
9554         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9555                 is_5705 = 1;
9556                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9557                         is_5750 = 1;
9558         }
9559
9560         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9561                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9562                         continue;
9563
9564                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9565                         continue;
9566
9567                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9568                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9569                         continue;
9570
9571                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9572                         continue;
9573
9574                 offset = (u32) reg_tbl[i].offset;
9575                 read_mask = reg_tbl[i].read_mask;
9576                 write_mask = reg_tbl[i].write_mask;
9577
9578                 /* Save the original register content */
9579                 save_val = tr32(offset);
9580
9581                 /* Determine the read-only value. */
9582                 read_val = save_val & read_mask;
9583
9584                 /* Write zero to the register, then make sure the read-only bits
9585                  * are not changed and the read/write bits are all zeros.
9586                  */
9587                 tw32(offset, 0);
9588
9589                 val = tr32(offset);
9590
9591                 /* Test the read-only and read/write bits. */
9592                 if (((val & read_mask) != read_val) || (val & write_mask))
9593                         goto out;
9594
9595                 /* Write ones to all the bits defined by RdMask and WrMask, then
9596                  * make sure the read-only bits are not changed and the
9597                  * read/write bits are all ones.
9598                  */
9599                 tw32(offset, read_mask | write_mask);
9600
9601                 val = tr32(offset);
9602
9603                 /* Test the read-only bits. */
9604                 if ((val & read_mask) != read_val)
9605                         goto out;
9606
9607                 /* Test the read/write bits. */
9608                 if ((val & write_mask) != write_mask)
9609                         goto out;
9610
9611                 tw32(offset, save_val);
9612         }
9613
9614         return 0;
9615
9616 out:
9617         if (netif_msg_hw(tp))
9618                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9619                        offset);
9620         tw32(offset, save_val);
9621         return -EIO;
9622 }
9623
9624 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9625 {
9626         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9627         int i;
9628         u32 j;
9629
9630         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9631                 for (j = 0; j < len; j += 4) {
9632                         u32 val;
9633
9634                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9635                         tg3_read_mem(tp, offset + j, &val);
9636                         if (val != test_pattern[i])
9637                                 return -EIO;
9638                 }
9639         }
9640         return 0;
9641 }
9642
9643 static int tg3_test_memory(struct tg3 *tp)
9644 {
9645         static struct mem_entry {
9646                 u32 offset;
9647                 u32 len;
9648         } mem_tbl_570x[] = {
9649                 { 0x00000000, 0x00b50},
9650                 { 0x00002000, 0x1c000},
9651                 { 0xffffffff, 0x00000}
9652         }, mem_tbl_5705[] = {
9653                 { 0x00000100, 0x0000c},
9654                 { 0x00000200, 0x00008},
9655                 { 0x00004000, 0x00800},
9656                 { 0x00006000, 0x01000},
9657                 { 0x00008000, 0x02000},
9658                 { 0x00010000, 0x0e000},
9659                 { 0xffffffff, 0x00000}
9660         }, mem_tbl_5755[] = {
9661                 { 0x00000200, 0x00008},
9662                 { 0x00004000, 0x00800},
9663                 { 0x00006000, 0x00800},
9664                 { 0x00008000, 0x02000},
9665                 { 0x00010000, 0x0c000},
9666                 { 0xffffffff, 0x00000}
9667         }, mem_tbl_5906[] = {
9668                 { 0x00000200, 0x00008},
9669                 { 0x00004000, 0x00400},
9670                 { 0x00006000, 0x00400},
9671                 { 0x00008000, 0x01000},
9672                 { 0x00010000, 0x01000},
9673                 { 0xffffffff, 0x00000}
9674         };
9675         struct mem_entry *mem_tbl;
9676         int err = 0;
9677         int i;
9678
9679         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9680                 mem_tbl = mem_tbl_5755;
9681         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9682                 mem_tbl = mem_tbl_5906;
9683         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9684                 mem_tbl = mem_tbl_5705;
9685         else
9686                 mem_tbl = mem_tbl_570x;
9687
9688         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9689                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9690                     mem_tbl[i].len)) != 0)
9691                         break;
9692         }
9693
9694         return err;
9695 }
9696
9697 #define TG3_MAC_LOOPBACK        0
9698 #define TG3_PHY_LOOPBACK        1
9699
9700 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9701 {
9702         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9703         u32 desc_idx;
9704         struct sk_buff *skb, *rx_skb;
9705         u8 *tx_data;
9706         dma_addr_t map;
9707         int num_pkts, tx_len, rx_len, i, err;
9708         struct tg3_rx_buffer_desc *desc;
9709
9710         if (loopback_mode == TG3_MAC_LOOPBACK) {
9711                 /* HW errata - mac loopback fails in some cases on 5780.
9712                  * Normal traffic and PHY loopback are not affected by
9713                  * errata.
9714                  */
9715                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9716                         return 0;
9717
9718                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9719                            MAC_MODE_PORT_INT_LPBACK;
9720                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9721                         mac_mode |= MAC_MODE_LINK_POLARITY;
9722                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9723                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9724                 else
9725                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9726                 tw32(MAC_MODE, mac_mode);
9727         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9728                 u32 val;
9729
9730                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9731                         u32 phytest;
9732
9733                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9734                                 u32 phy;
9735
9736                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9737                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9738                                 if (!tg3_readphy(tp, 0x1b, &phy))
9739                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9740                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9741                         }
9742                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9743                 } else
9744                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9745
9746                 tg3_phy_toggle_automdix(tp, 0);
9747
9748                 tg3_writephy(tp, MII_BMCR, val);
9749                 udelay(40);
9750
9751                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9752                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9753                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9754                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9755                 } else
9756                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9757
9758                 /* reset to prevent losing 1st rx packet intermittently */
9759                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9760                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9761                         udelay(10);
9762                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9763                 }
9764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9765                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9766                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9767                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9768                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9769                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9770                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9771                 }
9772                 tw32(MAC_MODE, mac_mode);
9773         }
9774         else
9775                 return -EINVAL;
9776
9777         err = -EIO;
9778
9779         tx_len = 1514;
9780         skb = netdev_alloc_skb(tp->dev, tx_len);
9781         if (!skb)
9782                 return -ENOMEM;
9783
9784         tx_data = skb_put(skb, tx_len);
9785         memcpy(tx_data, tp->dev->dev_addr, 6);
9786         memset(tx_data + 6, 0x0, 8);
9787
9788         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9789
9790         for (i = 14; i < tx_len; i++)
9791                 tx_data[i] = (u8) (i & 0xff);
9792
9793         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9794
9795         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9796              HOSTCC_MODE_NOW);
9797
9798         udelay(10);
9799
9800         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9801
9802         num_pkts = 0;
9803
9804         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9805
9806         tp->tx_prod++;
9807         num_pkts++;
9808
9809         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9810                      tp->tx_prod);
9811         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9812
9813         udelay(10);
9814
9815         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9816         for (i = 0; i < 25; i++) {
9817                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9818                        HOSTCC_MODE_NOW);
9819
9820                 udelay(10);
9821
9822                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9823                 rx_idx = tp->hw_status->idx[0].rx_producer;
9824                 if ((tx_idx == tp->tx_prod) &&
9825                     (rx_idx == (rx_start_idx + num_pkts)))
9826                         break;
9827         }
9828
9829         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9830         dev_kfree_skb(skb);
9831
9832         if (tx_idx != tp->tx_prod)
9833                 goto out;
9834
9835         if (rx_idx != rx_start_idx + num_pkts)
9836                 goto out;
9837
9838         desc = &tp->rx_rcb[rx_start_idx];
9839         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9840         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9841         if (opaque_key != RXD_OPAQUE_RING_STD)
9842                 goto out;
9843
9844         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9845             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9846                 goto out;
9847
9848         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9849         if (rx_len != tx_len)
9850                 goto out;
9851
9852         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9853
9854         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9855         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9856
9857         for (i = 14; i < tx_len; i++) {
9858                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9859                         goto out;
9860         }
9861         err = 0;
9862
9863         /* tg3_free_rings will unmap and free the rx_skb */
9864 out:
9865         return err;
9866 }
9867
9868 #define TG3_MAC_LOOPBACK_FAILED         1
9869 #define TG3_PHY_LOOPBACK_FAILED         2
9870 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9871                                          TG3_PHY_LOOPBACK_FAILED)
9872
9873 static int tg3_test_loopback(struct tg3 *tp)
9874 {
9875         int err = 0;
9876         u32 cpmuctrl = 0;
9877
9878         if (!netif_running(tp->dev))
9879                 return TG3_LOOPBACK_FAILED;
9880
9881         err = tg3_reset_hw(tp, 1);
9882         if (err)
9883                 return TG3_LOOPBACK_FAILED;
9884
9885         /* Turn off gphy autopowerdown. */
9886         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9887                 tg3_phy_toggle_apd(tp, false);
9888
9889         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9890                 int i;
9891                 u32 status;
9892
9893                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9894
9895                 /* Wait for up to 40 microseconds to acquire lock. */
9896                 for (i = 0; i < 4; i++) {
9897                         status = tr32(TG3_CPMU_MUTEX_GNT);
9898                         if (status == CPMU_MUTEX_GNT_DRIVER)
9899                                 break;
9900                         udelay(10);
9901                 }
9902
9903                 if (status != CPMU_MUTEX_GNT_DRIVER)
9904                         return TG3_LOOPBACK_FAILED;
9905
9906                 /* Turn off link-based power management. */
9907                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9908                 tw32(TG3_CPMU_CTRL,
9909                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9910                                   CPMU_CTRL_LINK_AWARE_MODE));
9911         }
9912
9913         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9914                 err |= TG3_MAC_LOOPBACK_FAILED;
9915
9916         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9917                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9918
9919                 /* Release the mutex */
9920                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9921         }
9922
9923         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9924             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9925                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9926                         err |= TG3_PHY_LOOPBACK_FAILED;
9927         }
9928
9929         /* Re-enable gphy autopowerdown. */
9930         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9931                 tg3_phy_toggle_apd(tp, true);
9932
9933         return err;
9934 }
9935
9936 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9937                           u64 *data)
9938 {
9939         struct tg3 *tp = netdev_priv(dev);
9940
9941         if (tp->link_config.phy_is_low_power)
9942                 tg3_set_power_state(tp, PCI_D0);
9943
9944         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9945
9946         if (tg3_test_nvram(tp) != 0) {
9947                 etest->flags |= ETH_TEST_FL_FAILED;
9948                 data[0] = 1;
9949         }
9950         if (tg3_test_link(tp) != 0) {
9951                 etest->flags |= ETH_TEST_FL_FAILED;
9952                 data[1] = 1;
9953         }
9954         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9955                 int err, err2 = 0, irq_sync = 0;
9956
9957                 if (netif_running(dev)) {
9958                         tg3_phy_stop(tp);
9959                         tg3_netif_stop(tp);
9960                         irq_sync = 1;
9961                 }
9962
9963                 tg3_full_lock(tp, irq_sync);
9964
9965                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9966                 err = tg3_nvram_lock(tp);
9967                 tg3_halt_cpu(tp, RX_CPU_BASE);
9968                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9969                         tg3_halt_cpu(tp, TX_CPU_BASE);
9970                 if (!err)
9971                         tg3_nvram_unlock(tp);
9972
9973                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9974                         tg3_phy_reset(tp);
9975
9976                 if (tg3_test_registers(tp) != 0) {
9977                         etest->flags |= ETH_TEST_FL_FAILED;
9978                         data[2] = 1;
9979                 }
9980                 if (tg3_test_memory(tp) != 0) {
9981                         etest->flags |= ETH_TEST_FL_FAILED;
9982                         data[3] = 1;
9983                 }
9984                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9985                         etest->flags |= ETH_TEST_FL_FAILED;
9986
9987                 tg3_full_unlock(tp);
9988
9989                 if (tg3_test_interrupt(tp) != 0) {
9990                         etest->flags |= ETH_TEST_FL_FAILED;
9991                         data[5] = 1;
9992                 }
9993
9994                 tg3_full_lock(tp, 0);
9995
9996                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9997                 if (netif_running(dev)) {
9998                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9999                         err2 = tg3_restart_hw(tp, 1);
10000                         if (!err2)
10001                                 tg3_netif_start(tp);
10002                 }
10003
10004                 tg3_full_unlock(tp);
10005
10006                 if (irq_sync && !err2)
10007                         tg3_phy_start(tp);
10008         }
10009         if (tp->link_config.phy_is_low_power)
10010                 tg3_set_power_state(tp, PCI_D3hot);
10011
10012 }
10013
10014 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10015 {
10016         struct mii_ioctl_data *data = if_mii(ifr);
10017         struct tg3 *tp = netdev_priv(dev);
10018         int err;
10019
10020         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10021                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10022                         return -EAGAIN;
10023                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10024         }
10025
10026         switch(cmd) {
10027         case SIOCGMIIPHY:
10028                 data->phy_id = PHY_ADDR;
10029
10030                 /* fallthru */
10031         case SIOCGMIIREG: {
10032                 u32 mii_regval;
10033
10034                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10035                         break;                  /* We have no PHY */
10036
10037                 if (tp->link_config.phy_is_low_power)
10038                         return -EAGAIN;
10039
10040                 spin_lock_bh(&tp->lock);
10041                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10042                 spin_unlock_bh(&tp->lock);
10043
10044                 data->val_out = mii_regval;
10045
10046                 return err;
10047         }
10048
10049         case SIOCSMIIREG:
10050                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10051                         break;                  /* We have no PHY */
10052
10053                 if (!capable(CAP_NET_ADMIN))
10054                         return -EPERM;
10055
10056                 if (tp->link_config.phy_is_low_power)
10057                         return -EAGAIN;
10058
10059                 spin_lock_bh(&tp->lock);
10060                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10061                 spin_unlock_bh(&tp->lock);
10062
10063                 return err;
10064
10065         default:
10066                 /* do nothing */
10067                 break;
10068         }
10069         return -EOPNOTSUPP;
10070 }
10071
10072 #if TG3_VLAN_TAG_USED
10073 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10074 {
10075         struct tg3 *tp = netdev_priv(dev);
10076
10077         if (!netif_running(dev)) {
10078                 tp->vlgrp = grp;
10079                 return;
10080         }
10081
10082         tg3_netif_stop(tp);
10083
10084         tg3_full_lock(tp, 0);
10085
10086         tp->vlgrp = grp;
10087
10088         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10089         __tg3_set_rx_mode(dev);
10090
10091         tg3_netif_start(tp);
10092
10093         tg3_full_unlock(tp);
10094 }
10095 #endif
10096
10097 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10098 {
10099         struct tg3 *tp = netdev_priv(dev);
10100
10101         memcpy(ec, &tp->coal, sizeof(*ec));
10102         return 0;
10103 }
10104
10105 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10106 {
10107         struct tg3 *tp = netdev_priv(dev);
10108         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10109         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10110
10111         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10112                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10113                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10114                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10115                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10116         }
10117
10118         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10119             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10120             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10121             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10122             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10123             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10124             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10125             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10126             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10127             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10128                 return -EINVAL;
10129
10130         /* No rx interrupts will be generated if both are zero */
10131         if ((ec->rx_coalesce_usecs == 0) &&
10132             (ec->rx_max_coalesced_frames == 0))
10133                 return -EINVAL;
10134
10135         /* No tx interrupts will be generated if both are zero */
10136         if ((ec->tx_coalesce_usecs == 0) &&
10137             (ec->tx_max_coalesced_frames == 0))
10138                 return -EINVAL;
10139
10140         /* Only copy relevant parameters, ignore all others. */
10141         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10142         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10143         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10144         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10145         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10146         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10147         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10148         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10149         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10150
10151         if (netif_running(dev)) {
10152                 tg3_full_lock(tp, 0);
10153                 __tg3_set_coalesce(tp, &tp->coal);
10154                 tg3_full_unlock(tp);
10155         }
10156         return 0;
10157 }
10158
10159 static const struct ethtool_ops tg3_ethtool_ops = {
10160         .get_settings           = tg3_get_settings,
10161         .set_settings           = tg3_set_settings,
10162         .get_drvinfo            = tg3_get_drvinfo,
10163         .get_regs_len           = tg3_get_regs_len,
10164         .get_regs               = tg3_get_regs,
10165         .get_wol                = tg3_get_wol,
10166         .set_wol                = tg3_set_wol,
10167         .get_msglevel           = tg3_get_msglevel,
10168         .set_msglevel           = tg3_set_msglevel,
10169         .nway_reset             = tg3_nway_reset,
10170         .get_link               = ethtool_op_get_link,
10171         .get_eeprom_len         = tg3_get_eeprom_len,
10172         .get_eeprom             = tg3_get_eeprom,
10173         .set_eeprom             = tg3_set_eeprom,
10174         .get_ringparam          = tg3_get_ringparam,
10175         .set_ringparam          = tg3_set_ringparam,
10176         .get_pauseparam         = tg3_get_pauseparam,
10177         .set_pauseparam         = tg3_set_pauseparam,
10178         .get_rx_csum            = tg3_get_rx_csum,
10179         .set_rx_csum            = tg3_set_rx_csum,
10180         .set_tx_csum            = tg3_set_tx_csum,
10181         .set_sg                 = ethtool_op_set_sg,
10182         .set_tso                = tg3_set_tso,
10183         .self_test              = tg3_self_test,
10184         .get_strings            = tg3_get_strings,
10185         .phys_id                = tg3_phys_id,
10186         .get_ethtool_stats      = tg3_get_ethtool_stats,
10187         .get_coalesce           = tg3_get_coalesce,
10188         .set_coalesce           = tg3_set_coalesce,
10189         .get_sset_count         = tg3_get_sset_count,
10190 };
10191
10192 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10193 {
10194         u32 cursize, val, magic;
10195
10196         tp->nvram_size = EEPROM_CHIP_SIZE;
10197
10198         if (tg3_nvram_read(tp, 0, &magic) != 0)
10199                 return;
10200
10201         if ((magic != TG3_EEPROM_MAGIC) &&
10202             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10203             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10204                 return;
10205
10206         /*
10207          * Size the chip by reading offsets at increasing powers of two.
10208          * When we encounter our validation signature, we know the addressing
10209          * has wrapped around, and thus have our chip size.
10210          */
10211         cursize = 0x10;
10212
10213         while (cursize < tp->nvram_size) {
10214                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10215                         return;
10216
10217                 if (val == magic)
10218                         break;
10219
10220                 cursize <<= 1;
10221         }
10222
10223         tp->nvram_size = cursize;
10224 }
10225
10226 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10227 {
10228         u32 val;
10229
10230         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10231             tg3_nvram_read(tp, 0, &val) != 0)
10232                 return;
10233
10234         /* Selfboot format */
10235         if (val != TG3_EEPROM_MAGIC) {
10236                 tg3_get_eeprom_size(tp);
10237                 return;
10238         }
10239
10240         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10241                 if (val != 0) {
10242                         /* This is confusing.  We want to operate on the
10243                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10244                          * call will read from NVRAM and byteswap the data
10245                          * according to the byteswapping settings for all
10246                          * other register accesses.  This ensures the data we
10247                          * want will always reside in the lower 16-bits.
10248                          * However, the data in NVRAM is in LE format, which
10249                          * means the data from the NVRAM read will always be
10250                          * opposite the endianness of the CPU.  The 16-bit
10251                          * byteswap then brings the data to CPU endianness.
10252                          */
10253                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10254                         return;
10255                 }
10256         }
10257         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10258 }
10259
10260 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10261 {
10262         u32 nvcfg1;
10263
10264         nvcfg1 = tr32(NVRAM_CFG1);
10265         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10266                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10267         }
10268         else {
10269                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10270                 tw32(NVRAM_CFG1, nvcfg1);
10271         }
10272
10273         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10274             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10275                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10276                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10277                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10278                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10279                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10280                                 break;
10281                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10282                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10283                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10284                                 break;
10285                         case FLASH_VENDOR_ATMEL_EEPROM:
10286                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10287                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10288                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10289                                 break;
10290                         case FLASH_VENDOR_ST:
10291                                 tp->nvram_jedecnum = JEDEC_ST;
10292                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10293                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10294                                 break;
10295                         case FLASH_VENDOR_SAIFUN:
10296                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10297                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10298                                 break;
10299                         case FLASH_VENDOR_SST_SMALL:
10300                         case FLASH_VENDOR_SST_LARGE:
10301                                 tp->nvram_jedecnum = JEDEC_SST;
10302                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10303                                 break;
10304                 }
10305         }
10306         else {
10307                 tp->nvram_jedecnum = JEDEC_ATMEL;
10308                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10309                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10310         }
10311 }
10312
10313 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10314 {
10315         u32 nvcfg1;
10316
10317         nvcfg1 = tr32(NVRAM_CFG1);
10318
10319         /* NVRAM protection for TPM */
10320         if (nvcfg1 & (1 << 27))
10321                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10322
10323         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10324                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10325                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10326                         tp->nvram_jedecnum = JEDEC_ATMEL;
10327                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10328                         break;
10329                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10330                         tp->nvram_jedecnum = JEDEC_ATMEL;
10331                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10332                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10333                         break;
10334                 case FLASH_5752VENDOR_ST_M45PE10:
10335                 case FLASH_5752VENDOR_ST_M45PE20:
10336                 case FLASH_5752VENDOR_ST_M45PE40:
10337                         tp->nvram_jedecnum = JEDEC_ST;
10338                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10339                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10340                         break;
10341         }
10342
10343         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10344                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10345                         case FLASH_5752PAGE_SIZE_256:
10346                                 tp->nvram_pagesize = 256;
10347                                 break;
10348                         case FLASH_5752PAGE_SIZE_512:
10349                                 tp->nvram_pagesize = 512;
10350                                 break;
10351                         case FLASH_5752PAGE_SIZE_1K:
10352                                 tp->nvram_pagesize = 1024;
10353                                 break;
10354                         case FLASH_5752PAGE_SIZE_2K:
10355                                 tp->nvram_pagesize = 2048;
10356                                 break;
10357                         case FLASH_5752PAGE_SIZE_4K:
10358                                 tp->nvram_pagesize = 4096;
10359                                 break;
10360                         case FLASH_5752PAGE_SIZE_264:
10361                                 tp->nvram_pagesize = 264;
10362                                 break;
10363                 }
10364         }
10365         else {
10366                 /* For eeprom, set pagesize to maximum eeprom size */
10367                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10368
10369                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10370                 tw32(NVRAM_CFG1, nvcfg1);
10371         }
10372 }
10373
10374 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10375 {
10376         u32 nvcfg1, protect = 0;
10377
10378         nvcfg1 = tr32(NVRAM_CFG1);
10379
10380         /* NVRAM protection for TPM */
10381         if (nvcfg1 & (1 << 27)) {
10382                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10383                 protect = 1;
10384         }
10385
10386         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10387         switch (nvcfg1) {
10388                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10389                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10390                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10391                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10392                         tp->nvram_jedecnum = JEDEC_ATMEL;
10393                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10394                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10395                         tp->nvram_pagesize = 264;
10396                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10397                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10398                                 tp->nvram_size = (protect ? 0x3e200 :
10399                                                   TG3_NVRAM_SIZE_512KB);
10400                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10401                                 tp->nvram_size = (protect ? 0x1f200 :
10402                                                   TG3_NVRAM_SIZE_256KB);
10403                         else
10404                                 tp->nvram_size = (protect ? 0x1f200 :
10405                                                   TG3_NVRAM_SIZE_128KB);
10406                         break;
10407                 case FLASH_5752VENDOR_ST_M45PE10:
10408                 case FLASH_5752VENDOR_ST_M45PE20:
10409                 case FLASH_5752VENDOR_ST_M45PE40:
10410                         tp->nvram_jedecnum = JEDEC_ST;
10411                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10412                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10413                         tp->nvram_pagesize = 256;
10414                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10415                                 tp->nvram_size = (protect ?
10416                                                   TG3_NVRAM_SIZE_64KB :
10417                                                   TG3_NVRAM_SIZE_128KB);
10418                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10419                                 tp->nvram_size = (protect ?
10420                                                   TG3_NVRAM_SIZE_64KB :
10421                                                   TG3_NVRAM_SIZE_256KB);
10422                         else
10423                                 tp->nvram_size = (protect ?
10424                                                   TG3_NVRAM_SIZE_128KB :
10425                                                   TG3_NVRAM_SIZE_512KB);
10426                         break;
10427         }
10428 }
10429
10430 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10431 {
10432         u32 nvcfg1;
10433
10434         nvcfg1 = tr32(NVRAM_CFG1);
10435
10436         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10437                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10438                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10439                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10440                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10441                         tp->nvram_jedecnum = JEDEC_ATMEL;
10442                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10443                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10444
10445                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10446                         tw32(NVRAM_CFG1, nvcfg1);
10447                         break;
10448                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10449                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10450                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10451                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10452                         tp->nvram_jedecnum = JEDEC_ATMEL;
10453                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10454                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10455                         tp->nvram_pagesize = 264;
10456                         break;
10457                 case FLASH_5752VENDOR_ST_M45PE10:
10458                 case FLASH_5752VENDOR_ST_M45PE20:
10459                 case FLASH_5752VENDOR_ST_M45PE40:
10460                         tp->nvram_jedecnum = JEDEC_ST;
10461                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10462                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10463                         tp->nvram_pagesize = 256;
10464                         break;
10465         }
10466 }
10467
10468 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10469 {
10470         u32 nvcfg1, protect = 0;
10471
10472         nvcfg1 = tr32(NVRAM_CFG1);
10473
10474         /* NVRAM protection for TPM */
10475         if (nvcfg1 & (1 << 27)) {
10476                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10477                 protect = 1;
10478         }
10479
10480         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10481         switch (nvcfg1) {
10482                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10483                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10484                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10485                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10486                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10487                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10488                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10489                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10490                         tp->nvram_jedecnum = JEDEC_ATMEL;
10491                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10492                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10493                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10494                         tp->nvram_pagesize = 256;
10495                         break;
10496                 case FLASH_5761VENDOR_ST_A_M45PE20:
10497                 case FLASH_5761VENDOR_ST_A_M45PE40:
10498                 case FLASH_5761VENDOR_ST_A_M45PE80:
10499                 case FLASH_5761VENDOR_ST_A_M45PE16:
10500                 case FLASH_5761VENDOR_ST_M_M45PE20:
10501                 case FLASH_5761VENDOR_ST_M_M45PE40:
10502                 case FLASH_5761VENDOR_ST_M_M45PE80:
10503                 case FLASH_5761VENDOR_ST_M_M45PE16:
10504                         tp->nvram_jedecnum = JEDEC_ST;
10505                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10506                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10507                         tp->nvram_pagesize = 256;
10508                         break;
10509         }
10510
10511         if (protect) {
10512                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10513         } else {
10514                 switch (nvcfg1) {
10515                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10516                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10517                         case FLASH_5761VENDOR_ST_A_M45PE16:
10518                         case FLASH_5761VENDOR_ST_M_M45PE16:
10519                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10520                                 break;
10521                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10522                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10523                         case FLASH_5761VENDOR_ST_A_M45PE80:
10524                         case FLASH_5761VENDOR_ST_M_M45PE80:
10525                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10526                                 break;
10527                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10528                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10529                         case FLASH_5761VENDOR_ST_A_M45PE40:
10530                         case FLASH_5761VENDOR_ST_M_M45PE40:
10531                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10532                                 break;
10533                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10534                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10535                         case FLASH_5761VENDOR_ST_A_M45PE20:
10536                         case FLASH_5761VENDOR_ST_M_M45PE20:
10537                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10538                                 break;
10539                 }
10540         }
10541 }
10542
10543 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10544 {
10545         tp->nvram_jedecnum = JEDEC_ATMEL;
10546         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10547         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10548 }
10549
10550 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10551 {
10552         u32 nvcfg1;
10553
10554         nvcfg1 = tr32(NVRAM_CFG1);
10555
10556         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10557         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10558         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10559                 tp->nvram_jedecnum = JEDEC_ATMEL;
10560                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10561                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10562
10563                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10564                 tw32(NVRAM_CFG1, nvcfg1);
10565                 return;
10566         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10567         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10568         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10569         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10570         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10571         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10572         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10573                 tp->nvram_jedecnum = JEDEC_ATMEL;
10574                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10575                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10576
10577                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10578                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10579                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10580                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10581                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10582                         break;
10583                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10584                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10585                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10586                         break;
10587                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10588                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10589                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10590                         break;
10591                 }
10592                 break;
10593         case FLASH_5752VENDOR_ST_M45PE10:
10594         case FLASH_5752VENDOR_ST_M45PE20:
10595         case FLASH_5752VENDOR_ST_M45PE40:
10596                 tp->nvram_jedecnum = JEDEC_ST;
10597                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10598                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10599
10600                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10601                 case FLASH_5752VENDOR_ST_M45PE10:
10602                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10603                         break;
10604                 case FLASH_5752VENDOR_ST_M45PE20:
10605                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10606                         break;
10607                 case FLASH_5752VENDOR_ST_M45PE40:
10608                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10609                         break;
10610                 }
10611                 break;
10612         default:
10613                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10614                 return;
10615         }
10616
10617         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10618         case FLASH_5752PAGE_SIZE_256:
10619                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10620                 tp->nvram_pagesize = 256;
10621                 break;
10622         case FLASH_5752PAGE_SIZE_512:
10623                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10624                 tp->nvram_pagesize = 512;
10625                 break;
10626         case FLASH_5752PAGE_SIZE_1K:
10627                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10628                 tp->nvram_pagesize = 1024;
10629                 break;
10630         case FLASH_5752PAGE_SIZE_2K:
10631                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10632                 tp->nvram_pagesize = 2048;
10633                 break;
10634         case FLASH_5752PAGE_SIZE_4K:
10635                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10636                 tp->nvram_pagesize = 4096;
10637                 break;
10638         case FLASH_5752PAGE_SIZE_264:
10639                 tp->nvram_pagesize = 264;
10640                 break;
10641         case FLASH_5752PAGE_SIZE_528:
10642                 tp->nvram_pagesize = 528;
10643                 break;
10644         }
10645 }
10646
10647 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10648 static void __devinit tg3_nvram_init(struct tg3 *tp)
10649 {
10650         tw32_f(GRC_EEPROM_ADDR,
10651              (EEPROM_ADDR_FSM_RESET |
10652               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10653                EEPROM_ADDR_CLKPERD_SHIFT)));
10654
10655         msleep(1);
10656
10657         /* Enable seeprom accesses. */
10658         tw32_f(GRC_LOCAL_CTRL,
10659              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10660         udelay(100);
10661
10662         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10663             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10664                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10665
10666                 if (tg3_nvram_lock(tp)) {
10667                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10668                                "tg3_nvram_init failed.\n", tp->dev->name);
10669                         return;
10670                 }
10671                 tg3_enable_nvram_access(tp);
10672
10673                 tp->nvram_size = 0;
10674
10675                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10676                         tg3_get_5752_nvram_info(tp);
10677                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10678                         tg3_get_5755_nvram_info(tp);
10679                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10680                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10681                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10682                         tg3_get_5787_nvram_info(tp);
10683                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10684                         tg3_get_5761_nvram_info(tp);
10685                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10686                         tg3_get_5906_nvram_info(tp);
10687                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10688                         tg3_get_57780_nvram_info(tp);
10689                 else
10690                         tg3_get_nvram_info(tp);
10691
10692                 if (tp->nvram_size == 0)
10693                         tg3_get_nvram_size(tp);
10694
10695                 tg3_disable_nvram_access(tp);
10696                 tg3_nvram_unlock(tp);
10697
10698         } else {
10699                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10700
10701                 tg3_get_eeprom_size(tp);
10702         }
10703 }
10704
10705 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10706                                     u32 offset, u32 len, u8 *buf)
10707 {
10708         int i, j, rc = 0;
10709         u32 val;
10710
10711         for (i = 0; i < len; i += 4) {
10712                 u32 addr;
10713                 __be32 data;
10714
10715                 addr = offset + i;
10716
10717                 memcpy(&data, buf + i, 4);
10718
10719                 /*
10720                  * The SEEPROM interface expects the data to always be opposite
10721                  * the native endian format.  We accomplish this by reversing
10722                  * all the operations that would have been performed on the
10723                  * data from a call to tg3_nvram_read_be32().
10724                  */
10725                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10726
10727                 val = tr32(GRC_EEPROM_ADDR);
10728                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10729
10730                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10731                         EEPROM_ADDR_READ);
10732                 tw32(GRC_EEPROM_ADDR, val |
10733                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10734                         (addr & EEPROM_ADDR_ADDR_MASK) |
10735                         EEPROM_ADDR_START |
10736                         EEPROM_ADDR_WRITE);
10737
10738                 for (j = 0; j < 1000; j++) {
10739                         val = tr32(GRC_EEPROM_ADDR);
10740
10741                         if (val & EEPROM_ADDR_COMPLETE)
10742                                 break;
10743                         msleep(1);
10744                 }
10745                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10746                         rc = -EBUSY;
10747                         break;
10748                 }
10749         }
10750
10751         return rc;
10752 }
10753
10754 /* offset and length are dword aligned */
10755 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10756                 u8 *buf)
10757 {
10758         int ret = 0;
10759         u32 pagesize = tp->nvram_pagesize;
10760         u32 pagemask = pagesize - 1;
10761         u32 nvram_cmd;
10762         u8 *tmp;
10763
10764         tmp = kmalloc(pagesize, GFP_KERNEL);
10765         if (tmp == NULL)
10766                 return -ENOMEM;
10767
10768         while (len) {
10769                 int j;
10770                 u32 phy_addr, page_off, size;
10771
10772                 phy_addr = offset & ~pagemask;
10773
10774                 for (j = 0; j < pagesize; j += 4) {
10775                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10776                                                   (__be32 *) (tmp + j));
10777                         if (ret)
10778                                 break;
10779                 }
10780                 if (ret)
10781                         break;
10782
10783                 page_off = offset & pagemask;
10784                 size = pagesize;
10785                 if (len < size)
10786                         size = len;
10787
10788                 len -= size;
10789
10790                 memcpy(tmp + page_off, buf, size);
10791
10792                 offset = offset + (pagesize - page_off);
10793
10794                 tg3_enable_nvram_access(tp);
10795
10796                 /*
10797                  * Before we can erase the flash page, we need
10798                  * to issue a special "write enable" command.
10799                  */
10800                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10801
10802                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10803                         break;
10804
10805                 /* Erase the target page */
10806                 tw32(NVRAM_ADDR, phy_addr);
10807
10808                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10809                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10810
10811                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10812                         break;
10813
10814                 /* Issue another write enable to start the write. */
10815                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10816
10817                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10818                         break;
10819
10820                 for (j = 0; j < pagesize; j += 4) {
10821                         __be32 data;
10822
10823                         data = *((__be32 *) (tmp + j));
10824
10825                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10826
10827                         tw32(NVRAM_ADDR, phy_addr + j);
10828
10829                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10830                                 NVRAM_CMD_WR;
10831
10832                         if (j == 0)
10833                                 nvram_cmd |= NVRAM_CMD_FIRST;
10834                         else if (j == (pagesize - 4))
10835                                 nvram_cmd |= NVRAM_CMD_LAST;
10836
10837                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10838                                 break;
10839                 }
10840                 if (ret)
10841                         break;
10842         }
10843
10844         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10845         tg3_nvram_exec_cmd(tp, nvram_cmd);
10846
10847         kfree(tmp);
10848
10849         return ret;
10850 }
10851
10852 /* offset and length are dword aligned */
10853 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10854                 u8 *buf)
10855 {
10856         int i, ret = 0;
10857
10858         for (i = 0; i < len; i += 4, offset += 4) {
10859                 u32 page_off, phy_addr, nvram_cmd;
10860                 __be32 data;
10861
10862                 memcpy(&data, buf + i, 4);
10863                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10864
10865                 page_off = offset % tp->nvram_pagesize;
10866
10867                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10868
10869                 tw32(NVRAM_ADDR, phy_addr);
10870
10871                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10872
10873                 if ((page_off == 0) || (i == 0))
10874                         nvram_cmd |= NVRAM_CMD_FIRST;
10875                 if (page_off == (tp->nvram_pagesize - 4))
10876                         nvram_cmd |= NVRAM_CMD_LAST;
10877
10878                 if (i == (len - 4))
10879                         nvram_cmd |= NVRAM_CMD_LAST;
10880
10881                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10882                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10883                     (tp->nvram_jedecnum == JEDEC_ST) &&
10884                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10885
10886                         if ((ret = tg3_nvram_exec_cmd(tp,
10887                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10888                                 NVRAM_CMD_DONE)))
10889
10890                                 break;
10891                 }
10892                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10893                         /* We always do complete word writes to eeprom. */
10894                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10895                 }
10896
10897                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10898                         break;
10899         }
10900         return ret;
10901 }
10902
10903 /* offset and length are dword aligned */
10904 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10905 {
10906         int ret;
10907
10908         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10909                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10910                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10911                 udelay(40);
10912         }
10913
10914         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10915                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10916         }
10917         else {
10918                 u32 grc_mode;
10919
10920                 ret = tg3_nvram_lock(tp);
10921                 if (ret)
10922                         return ret;
10923
10924                 tg3_enable_nvram_access(tp);
10925                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10926                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10927                         tw32(NVRAM_WRITE1, 0x406);
10928
10929                 grc_mode = tr32(GRC_MODE);
10930                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10931
10932                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10933                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10934
10935                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10936                                 buf);
10937                 }
10938                 else {
10939                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10940                                 buf);
10941                 }
10942
10943                 grc_mode = tr32(GRC_MODE);
10944                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10945
10946                 tg3_disable_nvram_access(tp);
10947                 tg3_nvram_unlock(tp);
10948         }
10949
10950         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10951                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10952                 udelay(40);
10953         }
10954
10955         return ret;
10956 }
10957
10958 struct subsys_tbl_ent {
10959         u16 subsys_vendor, subsys_devid;
10960         u32 phy_id;
10961 };
10962
10963 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10964         /* Broadcom boards. */
10965         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10966         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10967         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10968         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10969         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10970         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10971         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10972         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10973         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10974         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10975         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10976
10977         /* 3com boards. */
10978         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10979         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10980         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10981         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10982         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10983
10984         /* DELL boards. */
10985         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10986         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10987         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10988         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10989
10990         /* Compaq boards. */
10991         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10992         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10993         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
10994         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10995         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10996
10997         /* IBM boards. */
10998         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10999 };
11000
11001 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11002 {
11003         int i;
11004
11005         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11006                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11007                      tp->pdev->subsystem_vendor) &&
11008                     (subsys_id_to_phy_id[i].subsys_devid ==
11009                      tp->pdev->subsystem_device))
11010                         return &subsys_id_to_phy_id[i];
11011         }
11012         return NULL;
11013 }
11014
11015 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11016 {
11017         u32 val;
11018         u16 pmcsr;
11019
11020         /* On some early chips the SRAM cannot be accessed in D3hot state,
11021          * so need make sure we're in D0.
11022          */
11023         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11024         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11025         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11026         msleep(1);
11027
11028         /* Make sure register accesses (indirect or otherwise)
11029          * will function correctly.
11030          */
11031         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11032                                tp->misc_host_ctrl);
11033
11034         /* The memory arbiter has to be enabled in order for SRAM accesses
11035          * to succeed.  Normally on powerup the tg3 chip firmware will make
11036          * sure it is enabled, but other entities such as system netboot
11037          * code might disable it.
11038          */
11039         val = tr32(MEMARB_MODE);
11040         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11041
11042         tp->phy_id = PHY_ID_INVALID;
11043         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11044
11045         /* Assume an onboard device and WOL capable by default.  */
11046         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11047
11048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11049                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11050                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11051                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11052                 }
11053                 val = tr32(VCPU_CFGSHDW);
11054                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11055                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11056                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11057                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11058                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11059                 goto done;
11060         }
11061
11062         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11063         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11064                 u32 nic_cfg, led_cfg;
11065                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11066                 int eeprom_phy_serdes = 0;
11067
11068                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11069                 tp->nic_sram_data_cfg = nic_cfg;
11070
11071                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11072                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11073                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11074                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11075                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11076                     (ver > 0) && (ver < 0x100))
11077                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11078
11079                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11080                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11081
11082                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11083                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11084                         eeprom_phy_serdes = 1;
11085
11086                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11087                 if (nic_phy_id != 0) {
11088                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11089                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11090
11091                         eeprom_phy_id  = (id1 >> 16) << 10;
11092                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11093                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11094                 } else
11095                         eeprom_phy_id = 0;
11096
11097                 tp->phy_id = eeprom_phy_id;
11098                 if (eeprom_phy_serdes) {
11099                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11100                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11101                         else
11102                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11103                 }
11104
11105                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11106                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11107                                     SHASTA_EXT_LED_MODE_MASK);
11108                 else
11109                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11110
11111                 switch (led_cfg) {
11112                 default:
11113                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11114                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11115                         break;
11116
11117                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11118                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11119                         break;
11120
11121                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11122                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11123
11124                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11125                          * read on some older 5700/5701 bootcode.
11126                          */
11127                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11128                             ASIC_REV_5700 ||
11129                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11130                             ASIC_REV_5701)
11131                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11132
11133                         break;
11134
11135                 case SHASTA_EXT_LED_SHARED:
11136                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11137                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11138                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11139                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11140                                                  LED_CTRL_MODE_PHY_2);
11141                         break;
11142
11143                 case SHASTA_EXT_LED_MAC:
11144                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11145                         break;
11146
11147                 case SHASTA_EXT_LED_COMBO:
11148                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11149                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11150                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11151                                                  LED_CTRL_MODE_PHY_2);
11152                         break;
11153
11154                 }
11155
11156                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11157                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11158                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11159                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11160
11161                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11162                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11163
11164                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11165                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11166                         if ((tp->pdev->subsystem_vendor ==
11167                              PCI_VENDOR_ID_ARIMA) &&
11168                             (tp->pdev->subsystem_device == 0x205a ||
11169                              tp->pdev->subsystem_device == 0x2063))
11170                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11171                 } else {
11172                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11173                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11174                 }
11175
11176                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11177                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11178                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11179                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11180                 }
11181
11182                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11183                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11184                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11185
11186                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11187                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11188                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11189
11190                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11191                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11192                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11193
11194                 if (cfg2 & (1 << 17))
11195                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11196
11197                 /* serdes signal pre-emphasis in register 0x590 set by */
11198                 /* bootcode if bit 18 is set */
11199                 if (cfg2 & (1 << 18))
11200                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11201
11202                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11203                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11204                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11205                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11206
11207                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11208                         u32 cfg3;
11209
11210                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11211                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11212                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11213                 }
11214
11215                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11216                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11217                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11218                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11219                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11220                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11221         }
11222 done:
11223         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11224         device_set_wakeup_enable(&tp->pdev->dev,
11225                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11226 }
11227
11228 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11229 {
11230         int i;
11231         u32 val;
11232
11233         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11234         tw32(OTP_CTRL, cmd);
11235
11236         /* Wait for up to 1 ms for command to execute. */
11237         for (i = 0; i < 100; i++) {
11238                 val = tr32(OTP_STATUS);
11239                 if (val & OTP_STATUS_CMD_DONE)
11240                         break;
11241                 udelay(10);
11242         }
11243
11244         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11245 }
11246
11247 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11248  * configuration is a 32-bit value that straddles the alignment boundary.
11249  * We do two 32-bit reads and then shift and merge the results.
11250  */
11251 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11252 {
11253         u32 bhalf_otp, thalf_otp;
11254
11255         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11256
11257         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11258                 return 0;
11259
11260         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11261
11262         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11263                 return 0;
11264
11265         thalf_otp = tr32(OTP_READ_DATA);
11266
11267         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11268
11269         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11270                 return 0;
11271
11272         bhalf_otp = tr32(OTP_READ_DATA);
11273
11274         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11275 }
11276
11277 static int __devinit tg3_phy_probe(struct tg3 *tp)
11278 {
11279         u32 hw_phy_id_1, hw_phy_id_2;
11280         u32 hw_phy_id, hw_phy_id_masked;
11281         int err;
11282
11283         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11284                 return tg3_phy_init(tp);
11285
11286         /* Reading the PHY ID register can conflict with ASF
11287          * firmware access to the PHY hardware.
11288          */
11289         err = 0;
11290         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11291             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11292                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11293         } else {
11294                 /* Now read the physical PHY_ID from the chip and verify
11295                  * that it is sane.  If it doesn't look good, we fall back
11296                  * to either the hard-coded table based PHY_ID and failing
11297                  * that the value found in the eeprom area.
11298                  */
11299                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11300                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11301
11302                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11303                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11304                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11305
11306                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11307         }
11308
11309         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11310                 tp->phy_id = hw_phy_id;
11311                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11312                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11313                 else
11314                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11315         } else {
11316                 if (tp->phy_id != PHY_ID_INVALID) {
11317                         /* Do nothing, phy ID already set up in
11318                          * tg3_get_eeprom_hw_cfg().
11319                          */
11320                 } else {
11321                         struct subsys_tbl_ent *p;
11322
11323                         /* No eeprom signature?  Try the hardcoded
11324                          * subsys device table.
11325                          */
11326                         p = lookup_by_subsys(tp);
11327                         if (!p)
11328                                 return -ENODEV;
11329
11330                         tp->phy_id = p->phy_id;
11331                         if (!tp->phy_id ||
11332                             tp->phy_id == PHY_ID_BCM8002)
11333                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11334                 }
11335         }
11336
11337         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11338             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11339             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11340                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11341
11342                 tg3_readphy(tp, MII_BMSR, &bmsr);
11343                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11344                     (bmsr & BMSR_LSTATUS))
11345                         goto skip_phy_reset;
11346
11347                 err = tg3_phy_reset(tp);
11348                 if (err)
11349                         return err;
11350
11351                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11352                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11353                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11354                 tg3_ctrl = 0;
11355                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11356                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11357                                     MII_TG3_CTRL_ADV_1000_FULL);
11358                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11359                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11360                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11361                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11362                 }
11363
11364                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11365                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11366                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11367                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11368                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11369
11370                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11371                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11372
11373                         tg3_writephy(tp, MII_BMCR,
11374                                      BMCR_ANENABLE | BMCR_ANRESTART);
11375                 }
11376                 tg3_phy_set_wirespeed(tp);
11377
11378                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11379                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11380                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11381         }
11382
11383 skip_phy_reset:
11384         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11385                 err = tg3_init_5401phy_dsp(tp);
11386                 if (err)
11387                         return err;
11388         }
11389
11390         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11391                 err = tg3_init_5401phy_dsp(tp);
11392         }
11393
11394         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11395                 tp->link_config.advertising =
11396                         (ADVERTISED_1000baseT_Half |
11397                          ADVERTISED_1000baseT_Full |
11398                          ADVERTISED_Autoneg |
11399                          ADVERTISED_FIBRE);
11400         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11401                 tp->link_config.advertising &=
11402                         ~(ADVERTISED_1000baseT_Half |
11403                           ADVERTISED_1000baseT_Full);
11404
11405         return err;
11406 }
11407
11408 static void __devinit tg3_read_partno(struct tg3 *tp)
11409 {
11410         unsigned char vpd_data[256];   /* in little-endian format */
11411         unsigned int i;
11412         u32 magic;
11413
11414         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11415             tg3_nvram_read(tp, 0x0, &magic))
11416                 goto out_not_found;
11417
11418         if (magic == TG3_EEPROM_MAGIC) {
11419                 for (i = 0; i < 256; i += 4) {
11420                         u32 tmp;
11421
11422                         /* The data is in little-endian format in NVRAM.
11423                          * Use the big-endian read routines to preserve
11424                          * the byte order as it exists in NVRAM.
11425                          */
11426                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11427                                 goto out_not_found;
11428
11429                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11430                 }
11431         } else {
11432                 int vpd_cap;
11433
11434                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11435                 for (i = 0; i < 256; i += 4) {
11436                         u32 tmp, j = 0;
11437                         __le32 v;
11438                         u16 tmp16;
11439
11440                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11441                                               i);
11442                         while (j++ < 100) {
11443                                 pci_read_config_word(tp->pdev, vpd_cap +
11444                                                      PCI_VPD_ADDR, &tmp16);
11445                                 if (tmp16 & 0x8000)
11446                                         break;
11447                                 msleep(1);
11448                         }
11449                         if (!(tmp16 & 0x8000))
11450                                 goto out_not_found;
11451
11452                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11453                                               &tmp);
11454                         v = cpu_to_le32(tmp);
11455                         memcpy(&vpd_data[i], &v, sizeof(v));
11456                 }
11457         }
11458
11459         /* Now parse and find the part number. */
11460         for (i = 0; i < 254; ) {
11461                 unsigned char val = vpd_data[i];
11462                 unsigned int block_end;
11463
11464                 if (val == 0x82 || val == 0x91) {
11465                         i = (i + 3 +
11466                              (vpd_data[i + 1] +
11467                               (vpd_data[i + 2] << 8)));
11468                         continue;
11469                 }
11470
11471                 if (val != 0x90)
11472                         goto out_not_found;
11473
11474                 block_end = (i + 3 +
11475                              (vpd_data[i + 1] +
11476                               (vpd_data[i + 2] << 8)));
11477                 i += 3;
11478
11479                 if (block_end > 256)
11480                         goto out_not_found;
11481
11482                 while (i < (block_end - 2)) {
11483                         if (vpd_data[i + 0] == 'P' &&
11484                             vpd_data[i + 1] == 'N') {
11485                                 int partno_len = vpd_data[i + 2];
11486
11487                                 i += 3;
11488                                 if (partno_len > 24 || (partno_len + i) > 256)
11489                                         goto out_not_found;
11490
11491                                 memcpy(tp->board_part_number,
11492                                        &vpd_data[i], partno_len);
11493
11494                                 /* Success. */
11495                                 return;
11496                         }
11497                         i += 3 + vpd_data[i + 2];
11498                 }
11499
11500                 /* Part number not found. */
11501                 goto out_not_found;
11502         }
11503
11504 out_not_found:
11505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11506                 strcpy(tp->board_part_number, "BCM95906");
11507         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11508                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11509                 strcpy(tp->board_part_number, "BCM57780");
11510         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11511                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11512                 strcpy(tp->board_part_number, "BCM57760");
11513         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11514                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11515                 strcpy(tp->board_part_number, "BCM57790");
11516         else
11517                 strcpy(tp->board_part_number, "none");
11518 }
11519
11520 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11521 {
11522         u32 val;
11523
11524         if (tg3_nvram_read(tp, offset, &val) ||
11525             (val & 0xfc000000) != 0x0c000000 ||
11526             tg3_nvram_read(tp, offset + 4, &val) ||
11527             val != 0)
11528                 return 0;
11529
11530         return 1;
11531 }
11532
11533 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11534 {
11535         u32 val, offset, start, ver_offset;
11536         int i;
11537         bool newver = false;
11538
11539         if (tg3_nvram_read(tp, 0xc, &offset) ||
11540             tg3_nvram_read(tp, 0x4, &start))
11541                 return;
11542
11543         offset = tg3_nvram_logical_addr(tp, offset);
11544
11545         if (tg3_nvram_read(tp, offset, &val))
11546                 return;
11547
11548         if ((val & 0xfc000000) == 0x0c000000) {
11549                 if (tg3_nvram_read(tp, offset + 4, &val))
11550                         return;
11551
11552                 if (val == 0)
11553                         newver = true;
11554         }
11555
11556         if (newver) {
11557                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11558                         return;
11559
11560                 offset = offset + ver_offset - start;
11561                 for (i = 0; i < 16; i += 4) {
11562                         __be32 v;
11563                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11564                                 return;
11565
11566                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11567                 }
11568         } else {
11569                 u32 major, minor;
11570
11571                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11572                         return;
11573
11574                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11575                         TG3_NVM_BCVER_MAJSFT;
11576                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11577                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11578         }
11579 }
11580
11581 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11582 {
11583         u32 val, major, minor;
11584
11585         /* Use native endian representation */
11586         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11587                 return;
11588
11589         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11590                 TG3_NVM_HWSB_CFG1_MAJSFT;
11591         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11592                 TG3_NVM_HWSB_CFG1_MINSFT;
11593
11594         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11595 }
11596
11597 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11598 {
11599         u32 offset, major, minor, build;
11600
11601         tp->fw_ver[0] = 's';
11602         tp->fw_ver[1] = 'b';
11603         tp->fw_ver[2] = '\0';
11604
11605         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11606                 return;
11607
11608         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11609         case TG3_EEPROM_SB_REVISION_0:
11610                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11611                 break;
11612         case TG3_EEPROM_SB_REVISION_2:
11613                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11614                 break;
11615         case TG3_EEPROM_SB_REVISION_3:
11616                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11617                 break;
11618         default:
11619                 return;
11620         }
11621
11622         if (tg3_nvram_read(tp, offset, &val))
11623                 return;
11624
11625         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11626                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11627         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11628                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11629         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11630
11631         if (minor > 99 || build > 26)
11632                 return;
11633
11634         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11635
11636         if (build > 0) {
11637                 tp->fw_ver[8] = 'a' + build - 1;
11638                 tp->fw_ver[9] = '\0';
11639         }
11640 }
11641
11642 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11643 {
11644         u32 val, offset, start;
11645         int i, vlen;
11646
11647         for (offset = TG3_NVM_DIR_START;
11648              offset < TG3_NVM_DIR_END;
11649              offset += TG3_NVM_DIRENT_SIZE) {
11650                 if (tg3_nvram_read(tp, offset, &val))
11651                         return;
11652
11653                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11654                         break;
11655         }
11656
11657         if (offset == TG3_NVM_DIR_END)
11658                 return;
11659
11660         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11661                 start = 0x08000000;
11662         else if (tg3_nvram_read(tp, offset - 4, &start))
11663                 return;
11664
11665         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11666             !tg3_fw_img_is_valid(tp, offset) ||
11667             tg3_nvram_read(tp, offset + 8, &val))
11668                 return;
11669
11670         offset += val - start;
11671
11672         vlen = strlen(tp->fw_ver);
11673
11674         tp->fw_ver[vlen++] = ',';
11675         tp->fw_ver[vlen++] = ' ';
11676
11677         for (i = 0; i < 4; i++) {
11678                 __be32 v;
11679                 if (tg3_nvram_read_be32(tp, offset, &v))
11680                         return;
11681
11682                 offset += sizeof(v);
11683
11684                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11685                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11686                         break;
11687                 }
11688
11689                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11690                 vlen += sizeof(v);
11691         }
11692 }
11693
11694 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11695 {
11696         int vlen;
11697         u32 apedata;
11698
11699         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11700             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11701                 return;
11702
11703         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11704         if (apedata != APE_SEG_SIG_MAGIC)
11705                 return;
11706
11707         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11708         if (!(apedata & APE_FW_STATUS_READY))
11709                 return;
11710
11711         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11712
11713         vlen = strlen(tp->fw_ver);
11714
11715         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11716                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11717                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11718                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11719                  (apedata & APE_FW_VERSION_BLDMSK));
11720 }
11721
11722 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11723 {
11724         u32 val;
11725
11726         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11727                 tp->fw_ver[0] = 's';
11728                 tp->fw_ver[1] = 'b';
11729                 tp->fw_ver[2] = '\0';
11730
11731                 return;
11732         }
11733
11734         if (tg3_nvram_read(tp, 0, &val))
11735                 return;
11736
11737         if (val == TG3_EEPROM_MAGIC)
11738                 tg3_read_bc_ver(tp);
11739         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11740                 tg3_read_sb_ver(tp, val);
11741         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11742                 tg3_read_hwsb_ver(tp);
11743         else
11744                 return;
11745
11746         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11747              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11748                 return;
11749
11750         tg3_read_mgmtfw_ver(tp);
11751
11752         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11753 }
11754
11755 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11756
11757 static int __devinit tg3_get_invariants(struct tg3 *tp)
11758 {
11759         static struct pci_device_id write_reorder_chipsets[] = {
11760                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11761                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11762                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11763                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11764                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11765                              PCI_DEVICE_ID_VIA_8385_0) },
11766                 { },
11767         };
11768         u32 misc_ctrl_reg;
11769         u32 pci_state_reg, grc_misc_cfg;
11770         u32 val;
11771         u16 pci_cmd;
11772         int err;
11773
11774         /* Force memory write invalidate off.  If we leave it on,
11775          * then on 5700_BX chips we have to enable a workaround.
11776          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11777          * to match the cacheline size.  The Broadcom driver have this
11778          * workaround but turns MWI off all the times so never uses
11779          * it.  This seems to suggest that the workaround is insufficient.
11780          */
11781         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11782         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11783         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11784
11785         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11786          * has the register indirect write enable bit set before
11787          * we try to access any of the MMIO registers.  It is also
11788          * critical that the PCI-X hw workaround situation is decided
11789          * before that as well.
11790          */
11791         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11792                               &misc_ctrl_reg);
11793
11794         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11795                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11796         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11797                 u32 prod_id_asic_rev;
11798
11799                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11800                                       &prod_id_asic_rev);
11801                 tp->pci_chip_rev_id = prod_id_asic_rev;
11802         }
11803
11804         /* Wrong chip ID in 5752 A0. This code can be removed later
11805          * as A0 is not in production.
11806          */
11807         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11808                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11809
11810         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11811          * we need to disable memory and use config. cycles
11812          * only to access all registers. The 5702/03 chips
11813          * can mistakenly decode the special cycles from the
11814          * ICH chipsets as memory write cycles, causing corruption
11815          * of register and memory space. Only certain ICH bridges
11816          * will drive special cycles with non-zero data during the
11817          * address phase which can fall within the 5703's address
11818          * range. This is not an ICH bug as the PCI spec allows
11819          * non-zero address during special cycles. However, only
11820          * these ICH bridges are known to drive non-zero addresses
11821          * during special cycles.
11822          *
11823          * Since special cycles do not cross PCI bridges, we only
11824          * enable this workaround if the 5703 is on the secondary
11825          * bus of these ICH bridges.
11826          */
11827         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11828             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11829                 static struct tg3_dev_id {
11830                         u32     vendor;
11831                         u32     device;
11832                         u32     rev;
11833                 } ich_chipsets[] = {
11834                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11835                           PCI_ANY_ID },
11836                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11837                           PCI_ANY_ID },
11838                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11839                           0xa },
11840                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11841                           PCI_ANY_ID },
11842                         { },
11843                 };
11844                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11845                 struct pci_dev *bridge = NULL;
11846
11847                 while (pci_id->vendor != 0) {
11848                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11849                                                 bridge);
11850                         if (!bridge) {
11851                                 pci_id++;
11852                                 continue;
11853                         }
11854                         if (pci_id->rev != PCI_ANY_ID) {
11855                                 if (bridge->revision > pci_id->rev)
11856                                         continue;
11857                         }
11858                         if (bridge->subordinate &&
11859                             (bridge->subordinate->number ==
11860                              tp->pdev->bus->number)) {
11861
11862                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11863                                 pci_dev_put(bridge);
11864                                 break;
11865                         }
11866                 }
11867         }
11868
11869         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11870                 static struct tg3_dev_id {
11871                         u32     vendor;
11872                         u32     device;
11873                 } bridge_chipsets[] = {
11874                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11875                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11876                         { },
11877                 };
11878                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11879                 struct pci_dev *bridge = NULL;
11880
11881                 while (pci_id->vendor != 0) {
11882                         bridge = pci_get_device(pci_id->vendor,
11883                                                 pci_id->device,
11884                                                 bridge);
11885                         if (!bridge) {
11886                                 pci_id++;
11887                                 continue;
11888                         }
11889                         if (bridge->subordinate &&
11890                             (bridge->subordinate->number <=
11891                              tp->pdev->bus->number) &&
11892                             (bridge->subordinate->subordinate >=
11893                              tp->pdev->bus->number)) {
11894                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11895                                 pci_dev_put(bridge);
11896                                 break;
11897                         }
11898                 }
11899         }
11900
11901         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11902          * DMA addresses > 40-bit. This bridge may have other additional
11903          * 57xx devices behind it in some 4-port NIC designs for example.
11904          * Any tg3 device found behind the bridge will also need the 40-bit
11905          * DMA workaround.
11906          */
11907         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11908             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11909                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11910                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11911                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11912         }
11913         else {
11914                 struct pci_dev *bridge = NULL;
11915
11916                 do {
11917                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11918                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11919                                                 bridge);
11920                         if (bridge && bridge->subordinate &&
11921                             (bridge->subordinate->number <=
11922                              tp->pdev->bus->number) &&
11923                             (bridge->subordinate->subordinate >=
11924                              tp->pdev->bus->number)) {
11925                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11926                                 pci_dev_put(bridge);
11927                                 break;
11928                         }
11929                 } while (bridge);
11930         }
11931
11932         /* Initialize misc host control in PCI block. */
11933         tp->misc_host_ctrl |= (misc_ctrl_reg &
11934                                MISC_HOST_CTRL_CHIPREV);
11935         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11936                                tp->misc_host_ctrl);
11937
11938         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11939             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11940                 tp->pdev_peer = tg3_find_peer(tp);
11941
11942         /* Intentionally exclude ASIC_REV_5906 */
11943         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11944             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11945             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11946             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11947             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11948             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11949                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11950
11951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11952             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11954             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11955             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11956                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11957
11958         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11959             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11960                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11961
11962         /* 5700 B0 chips do not support checksumming correctly due
11963          * to hardware bugs.
11964          */
11965         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11966                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11967         else {
11968                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11969                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11970                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11971                         tp->dev->features |= NETIF_F_IPV6_CSUM;
11972         }
11973
11974         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11975                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11976                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11977                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11978                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11979                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11980                      tp->pdev_peer == tp->pdev))
11981                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11982
11983                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11984                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11985                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11986                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11987                 } else {
11988                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11989                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11990                                 ASIC_REV_5750 &&
11991                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11992                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11993                 }
11994         }
11995
11996         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11997              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11998                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11999
12000         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12001                               &pci_state_reg);
12002
12003         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12004         if (tp->pcie_cap != 0) {
12005                 u16 lnkctl;
12006
12007                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12008
12009                 pcie_set_readrq(tp->pdev, 4096);
12010
12011                 pci_read_config_word(tp->pdev,
12012                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12013                                      &lnkctl);
12014                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12015                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12016                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12017                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12018                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12019                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12020                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12021                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12022                 }
12023         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12024                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12025         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12026                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12027                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12028                 if (!tp->pcix_cap) {
12029                         printk(KERN_ERR PFX "Cannot find PCI-X "
12030                                             "capability, aborting.\n");
12031                         return -EIO;
12032                 }
12033
12034                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12035                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12036         }
12037
12038         /* If we have an AMD 762 or VIA K8T800 chipset, write
12039          * reordering to the mailbox registers done by the host
12040          * controller can cause major troubles.  We read back from
12041          * every mailbox register write to force the writes to be
12042          * posted to the chip in order.
12043          */
12044         if (pci_dev_present(write_reorder_chipsets) &&
12045             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12046                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12047
12048         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12049                              &tp->pci_cacheline_sz);
12050         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12051                              &tp->pci_lat_timer);
12052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12053             tp->pci_lat_timer < 64) {
12054                 tp->pci_lat_timer = 64;
12055                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12056                                       tp->pci_lat_timer);
12057         }
12058
12059         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12060                 /* 5700 BX chips need to have their TX producer index
12061                  * mailboxes written twice to workaround a bug.
12062                  */
12063                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12064
12065                 /* If we are in PCI-X mode, enable register write workaround.
12066                  *
12067                  * The workaround is to use indirect register accesses
12068                  * for all chip writes not to mailbox registers.
12069                  */
12070                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12071                         u32 pm_reg;
12072
12073                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12074
12075                         /* The chip can have it's power management PCI config
12076                          * space registers clobbered due to this bug.
12077                          * So explicitly force the chip into D0 here.
12078                          */
12079                         pci_read_config_dword(tp->pdev,
12080                                               tp->pm_cap + PCI_PM_CTRL,
12081                                               &pm_reg);
12082                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12083                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12084                         pci_write_config_dword(tp->pdev,
12085                                                tp->pm_cap + PCI_PM_CTRL,
12086                                                pm_reg);
12087
12088                         /* Also, force SERR#/PERR# in PCI command. */
12089                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12090                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12091                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12092                 }
12093         }
12094
12095         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12096                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12097         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12098                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12099
12100         /* Chip-specific fixup from Broadcom driver */
12101         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12102             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12103                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12104                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12105         }
12106
12107         /* Default fast path register access methods */
12108         tp->read32 = tg3_read32;
12109         tp->write32 = tg3_write32;
12110         tp->read32_mbox = tg3_read32;
12111         tp->write32_mbox = tg3_write32;
12112         tp->write32_tx_mbox = tg3_write32;
12113         tp->write32_rx_mbox = tg3_write32;
12114
12115         /* Various workaround register access methods */
12116         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12117                 tp->write32 = tg3_write_indirect_reg32;
12118         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12119                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12120                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12121                 /*
12122                  * Back to back register writes can cause problems on these
12123                  * chips, the workaround is to read back all reg writes
12124                  * except those to mailbox regs.
12125                  *
12126                  * See tg3_write_indirect_reg32().
12127                  */
12128                 tp->write32 = tg3_write_flush_reg32;
12129         }
12130
12131
12132         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12133             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12134                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12135                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12136                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12137         }
12138
12139         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12140                 tp->read32 = tg3_read_indirect_reg32;
12141                 tp->write32 = tg3_write_indirect_reg32;
12142                 tp->read32_mbox = tg3_read_indirect_mbox;
12143                 tp->write32_mbox = tg3_write_indirect_mbox;
12144                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12145                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12146
12147                 iounmap(tp->regs);
12148                 tp->regs = NULL;
12149
12150                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12151                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12152                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12153         }
12154         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12155                 tp->read32_mbox = tg3_read32_mbox_5906;
12156                 tp->write32_mbox = tg3_write32_mbox_5906;
12157                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12158                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12159         }
12160
12161         if (tp->write32 == tg3_write_indirect_reg32 ||
12162             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12163              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12164               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12165                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12166
12167         /* Get eeprom hw config before calling tg3_set_power_state().
12168          * In particular, the TG3_FLG2_IS_NIC flag must be
12169          * determined before calling tg3_set_power_state() so that
12170          * we know whether or not to switch out of Vaux power.
12171          * When the flag is set, it means that GPIO1 is used for eeprom
12172          * write protect and also implies that it is a LOM where GPIOs
12173          * are not used to switch power.
12174          */
12175         tg3_get_eeprom_hw_cfg(tp);
12176
12177         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12178                 /* Allow reads and writes to the
12179                  * APE register and memory space.
12180                  */
12181                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12182                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12183                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12184                                        pci_state_reg);
12185         }
12186
12187         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12188             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12189             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12190             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12191                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12192
12193         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12194          * GPIO1 driven high will bring 5700's external PHY out of reset.
12195          * It is also used as eeprom write protect on LOMs.
12196          */
12197         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12198         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12199             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12200                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12201                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12202         /* Unused GPIO3 must be driven as output on 5752 because there
12203          * are no pull-up resistors on unused GPIO pins.
12204          */
12205         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12206                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12207
12208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12210                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12211
12212         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12213             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12214                 /* Turn off the debug UART. */
12215                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12216                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12217                         /* Keep VMain power. */
12218                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12219                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12220         }
12221
12222         /* Force the chip into D0. */
12223         err = tg3_set_power_state(tp, PCI_D0);
12224         if (err) {
12225                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12226                        pci_name(tp->pdev));
12227                 return err;
12228         }
12229
12230         /* Derive initial jumbo mode from MTU assigned in
12231          * ether_setup() via the alloc_etherdev() call
12232          */
12233         if (tp->dev->mtu > ETH_DATA_LEN &&
12234             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12235                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12236
12237         /* Determine WakeOnLan speed to use. */
12238         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12239             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12240             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12241             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12242                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12243         } else {
12244                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12245         }
12246
12247         /* A few boards don't want Ethernet@WireSpeed phy feature */
12248         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12249             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12250              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12251              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12252             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12253             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12254                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12255
12256         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12257             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12258                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12259         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12260                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12261
12262         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12263             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12264             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12265             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12266                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12267                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12268                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12269                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12270                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12271                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12272                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12273                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12274                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12275                 } else
12276                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12277         }
12278
12279         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12280             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12281                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12282                 if (tp->phy_otp == 0)
12283                         tp->phy_otp = TG3_OTP_DEFAULT;
12284         }
12285
12286         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12287                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12288         else
12289                 tp->mi_mode = MAC_MI_MODE_BASE;
12290
12291         tp->coalesce_mode = 0;
12292         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12293             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12294                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12295
12296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12298                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12299
12300         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12301              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12302             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12303                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12304
12305         err = tg3_mdio_init(tp);
12306         if (err)
12307                 return err;
12308
12309         /* Initialize data/descriptor byte/word swapping. */
12310         val = tr32(GRC_MODE);
12311         val &= GRC_MODE_HOST_STACKUP;
12312         tw32(GRC_MODE, val | tp->grc_mode);
12313
12314         tg3_switch_clocks(tp);
12315
12316         /* Clear this out for sanity. */
12317         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12318
12319         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12320                               &pci_state_reg);
12321         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12322             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12323                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12324
12325                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12326                     chiprevid == CHIPREV_ID_5701_B0 ||
12327                     chiprevid == CHIPREV_ID_5701_B2 ||
12328                     chiprevid == CHIPREV_ID_5701_B5) {
12329                         void __iomem *sram_base;
12330
12331                         /* Write some dummy words into the SRAM status block
12332                          * area, see if it reads back correctly.  If the return
12333                          * value is bad, force enable the PCIX workaround.
12334                          */
12335                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12336
12337                         writel(0x00000000, sram_base);
12338                         writel(0x00000000, sram_base + 4);
12339                         writel(0xffffffff, sram_base + 4);
12340                         if (readl(sram_base) != 0x00000000)
12341                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12342                 }
12343         }
12344
12345         udelay(50);
12346         tg3_nvram_init(tp);
12347
12348         grc_misc_cfg = tr32(GRC_MISC_CFG);
12349         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12350
12351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12352             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12353              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12354                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12355
12356         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12357             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12358                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12359         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12360                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12361                                       HOSTCC_MODE_CLRTICK_TXBD);
12362
12363                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12364                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12365                                        tp->misc_host_ctrl);
12366         }
12367
12368         /* Preserve the APE MAC_MODE bits */
12369         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12370                 tp->mac_mode = tr32(MAC_MODE) |
12371                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12372         else
12373                 tp->mac_mode = TG3_DEF_MAC_MODE;
12374
12375         /* these are limited to 10/100 only */
12376         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12377              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12378             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12379              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12380              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12381               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12382               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12383             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12384              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12385               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12386               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12387             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12388             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12389                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12390
12391         err = tg3_phy_probe(tp);
12392         if (err) {
12393                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12394                        pci_name(tp->pdev), err);
12395                 /* ... but do not return immediately ... */
12396                 tg3_mdio_fini(tp);
12397         }
12398
12399         tg3_read_partno(tp);
12400         tg3_read_fw_ver(tp);
12401
12402         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12403                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12404         } else {
12405                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12406                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12407                 else
12408                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12409         }
12410
12411         /* 5700 {AX,BX} chips have a broken status block link
12412          * change bit implementation, so we must use the
12413          * status register in those cases.
12414          */
12415         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12416                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12417         else
12418                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12419
12420         /* The led_ctrl is set during tg3_phy_probe, here we might
12421          * have to force the link status polling mechanism based
12422          * upon subsystem IDs.
12423          */
12424         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12425             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12426             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12427                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12428                                   TG3_FLAG_USE_LINKCHG_REG);
12429         }
12430
12431         /* For all SERDES we poll the MAC status register. */
12432         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12433                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12434         else
12435                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12436
12437         tp->rx_offset = NET_IP_ALIGN;
12438         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12439             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12440                 tp->rx_offset = 0;
12441
12442         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12443
12444         /* Increment the rx prod index on the rx std ring by at most
12445          * 8 for these chips to workaround hw errata.
12446          */
12447         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12448             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12449             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12450                 tp->rx_std_max_post = 8;
12451
12452         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12453                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12454                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12455
12456         return err;
12457 }
12458
12459 #ifdef CONFIG_SPARC
12460 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12461 {
12462         struct net_device *dev = tp->dev;
12463         struct pci_dev *pdev = tp->pdev;
12464         struct device_node *dp = pci_device_to_OF_node(pdev);
12465         const unsigned char *addr;
12466         int len;
12467
12468         addr = of_get_property(dp, "local-mac-address", &len);
12469         if (addr && len == 6) {
12470                 memcpy(dev->dev_addr, addr, 6);
12471                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12472                 return 0;
12473         }
12474         return -ENODEV;
12475 }
12476
12477 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12478 {
12479         struct net_device *dev = tp->dev;
12480
12481         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12482         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12483         return 0;
12484 }
12485 #endif
12486
12487 static int __devinit tg3_get_device_address(struct tg3 *tp)
12488 {
12489         struct net_device *dev = tp->dev;
12490         u32 hi, lo, mac_offset;
12491         int addr_ok = 0;
12492
12493 #ifdef CONFIG_SPARC
12494         if (!tg3_get_macaddr_sparc(tp))
12495                 return 0;
12496 #endif
12497
12498         mac_offset = 0x7c;
12499         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12500             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12501                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12502                         mac_offset = 0xcc;
12503                 if (tg3_nvram_lock(tp))
12504                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12505                 else
12506                         tg3_nvram_unlock(tp);
12507         }
12508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12509                 mac_offset = 0x10;
12510
12511         /* First try to get it from MAC address mailbox. */
12512         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12513         if ((hi >> 16) == 0x484b) {
12514                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12515                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12516
12517                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12518                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12519                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12520                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12521                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12522
12523                 /* Some old bootcode may report a 0 MAC address in SRAM */
12524                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12525         }
12526         if (!addr_ok) {
12527                 /* Next, try NVRAM. */
12528                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12529                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12530                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12531                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12532                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12533                 }
12534                 /* Finally just fetch it out of the MAC control regs. */
12535                 else {
12536                         hi = tr32(MAC_ADDR_0_HIGH);
12537                         lo = tr32(MAC_ADDR_0_LOW);
12538
12539                         dev->dev_addr[5] = lo & 0xff;
12540                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12541                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12542                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12543                         dev->dev_addr[1] = hi & 0xff;
12544                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12545                 }
12546         }
12547
12548         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12549 #ifdef CONFIG_SPARC
12550                 if (!tg3_get_default_macaddr_sparc(tp))
12551                         return 0;
12552 #endif
12553                 return -EINVAL;
12554         }
12555         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12556         return 0;
12557 }
12558
12559 #define BOUNDARY_SINGLE_CACHELINE       1
12560 #define BOUNDARY_MULTI_CACHELINE        2
12561
12562 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12563 {
12564         int cacheline_size;
12565         u8 byte;
12566         int goal;
12567
12568         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12569         if (byte == 0)
12570                 cacheline_size = 1024;
12571         else
12572                 cacheline_size = (int) byte * 4;
12573
12574         /* On 5703 and later chips, the boundary bits have no
12575          * effect.
12576          */
12577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12578             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12579             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12580                 goto out;
12581
12582 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12583         goal = BOUNDARY_MULTI_CACHELINE;
12584 #else
12585 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12586         goal = BOUNDARY_SINGLE_CACHELINE;
12587 #else
12588         goal = 0;
12589 #endif
12590 #endif
12591
12592         if (!goal)
12593                 goto out;
12594
12595         /* PCI controllers on most RISC systems tend to disconnect
12596          * when a device tries to burst across a cache-line boundary.
12597          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12598          *
12599          * Unfortunately, for PCI-E there are only limited
12600          * write-side controls for this, and thus for reads
12601          * we will still get the disconnects.  We'll also waste
12602          * these PCI cycles for both read and write for chips
12603          * other than 5700 and 5701 which do not implement the
12604          * boundary bits.
12605          */
12606         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12607             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12608                 switch (cacheline_size) {
12609                 case 16:
12610                 case 32:
12611                 case 64:
12612                 case 128:
12613                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12614                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12615                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12616                         } else {
12617                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12618                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12619                         }
12620                         break;
12621
12622                 case 256:
12623                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12624                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12625                         break;
12626
12627                 default:
12628                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12629                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12630                         break;
12631                 }
12632         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12633                 switch (cacheline_size) {
12634                 case 16:
12635                 case 32:
12636                 case 64:
12637                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12638                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12639                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12640                                 break;
12641                         }
12642                         /* fallthrough */
12643                 case 128:
12644                 default:
12645                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12646                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12647                         break;
12648                 }
12649         } else {
12650                 switch (cacheline_size) {
12651                 case 16:
12652                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12653                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12654                                         DMA_RWCTRL_WRITE_BNDRY_16);
12655                                 break;
12656                         }
12657                         /* fallthrough */
12658                 case 32:
12659                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12660                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12661                                         DMA_RWCTRL_WRITE_BNDRY_32);
12662                                 break;
12663                         }
12664                         /* fallthrough */
12665                 case 64:
12666                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12667                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12668                                         DMA_RWCTRL_WRITE_BNDRY_64);
12669                                 break;
12670                         }
12671                         /* fallthrough */
12672                 case 128:
12673                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12674                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12675                                         DMA_RWCTRL_WRITE_BNDRY_128);
12676                                 break;
12677                         }
12678                         /* fallthrough */
12679                 case 256:
12680                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12681                                 DMA_RWCTRL_WRITE_BNDRY_256);
12682                         break;
12683                 case 512:
12684                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12685                                 DMA_RWCTRL_WRITE_BNDRY_512);
12686                         break;
12687                 case 1024:
12688                 default:
12689                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12690                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12691                         break;
12692                 }
12693         }
12694
12695 out:
12696         return val;
12697 }
12698
12699 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12700 {
12701         struct tg3_internal_buffer_desc test_desc;
12702         u32 sram_dma_descs;
12703         int i, ret;
12704
12705         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12706
12707         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12708         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12709         tw32(RDMAC_STATUS, 0);
12710         tw32(WDMAC_STATUS, 0);
12711
12712         tw32(BUFMGR_MODE, 0);
12713         tw32(FTQ_RESET, 0);
12714
12715         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12716         test_desc.addr_lo = buf_dma & 0xffffffff;
12717         test_desc.nic_mbuf = 0x00002100;
12718         test_desc.len = size;
12719
12720         /*
12721          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12722          * the *second* time the tg3 driver was getting loaded after an
12723          * initial scan.
12724          *
12725          * Broadcom tells me:
12726          *   ...the DMA engine is connected to the GRC block and a DMA
12727          *   reset may affect the GRC block in some unpredictable way...
12728          *   The behavior of resets to individual blocks has not been tested.
12729          *
12730          * Broadcom noted the GRC reset will also reset all sub-components.
12731          */
12732         if (to_device) {
12733                 test_desc.cqid_sqid = (13 << 8) | 2;
12734
12735                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12736                 udelay(40);
12737         } else {
12738                 test_desc.cqid_sqid = (16 << 8) | 7;
12739
12740                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12741                 udelay(40);
12742         }
12743         test_desc.flags = 0x00000005;
12744
12745         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12746                 u32 val;
12747
12748                 val = *(((u32 *)&test_desc) + i);
12749                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12750                                        sram_dma_descs + (i * sizeof(u32)));
12751                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12752         }
12753         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12754
12755         if (to_device) {
12756                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12757         } else {
12758                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12759         }
12760
12761         ret = -ENODEV;
12762         for (i = 0; i < 40; i++) {
12763                 u32 val;
12764
12765                 if (to_device)
12766                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12767                 else
12768                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12769                 if ((val & 0xffff) == sram_dma_descs) {
12770                         ret = 0;
12771                         break;
12772                 }
12773
12774                 udelay(100);
12775         }
12776
12777         return ret;
12778 }
12779
12780 #define TEST_BUFFER_SIZE        0x2000
12781
12782 static int __devinit tg3_test_dma(struct tg3 *tp)
12783 {
12784         dma_addr_t buf_dma;
12785         u32 *buf, saved_dma_rwctrl;
12786         int ret;
12787
12788         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12789         if (!buf) {
12790                 ret = -ENOMEM;
12791                 goto out_nofree;
12792         }
12793
12794         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12795                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12796
12797         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12798
12799         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12800                 /* DMA read watermark not used on PCIE */
12801                 tp->dma_rwctrl |= 0x00180000;
12802         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12803                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12804                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12805                         tp->dma_rwctrl |= 0x003f0000;
12806                 else
12807                         tp->dma_rwctrl |= 0x003f000f;
12808         } else {
12809                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12810                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12811                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12812                         u32 read_water = 0x7;
12813
12814                         /* If the 5704 is behind the EPB bridge, we can
12815                          * do the less restrictive ONE_DMA workaround for
12816                          * better performance.
12817                          */
12818                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12819                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12820                                 tp->dma_rwctrl |= 0x8000;
12821                         else if (ccval == 0x6 || ccval == 0x7)
12822                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12823
12824                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12825                                 read_water = 4;
12826                         /* Set bit 23 to enable PCIX hw bug fix */
12827                         tp->dma_rwctrl |=
12828                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12829                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12830                                 (1 << 23);
12831                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12832                         /* 5780 always in PCIX mode */
12833                         tp->dma_rwctrl |= 0x00144000;
12834                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12835                         /* 5714 always in PCIX mode */
12836                         tp->dma_rwctrl |= 0x00148000;
12837                 } else {
12838                         tp->dma_rwctrl |= 0x001b000f;
12839                 }
12840         }
12841
12842         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12843             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12844                 tp->dma_rwctrl &= 0xfffffff0;
12845
12846         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12847             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12848                 /* Remove this if it causes problems for some boards. */
12849                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12850
12851                 /* On 5700/5701 chips, we need to set this bit.
12852                  * Otherwise the chip will issue cacheline transactions
12853                  * to streamable DMA memory with not all the byte
12854                  * enables turned on.  This is an error on several
12855                  * RISC PCI controllers, in particular sparc64.
12856                  *
12857                  * On 5703/5704 chips, this bit has been reassigned
12858                  * a different meaning.  In particular, it is used
12859                  * on those chips to enable a PCI-X workaround.
12860                  */
12861                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12862         }
12863
12864         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12865
12866 #if 0
12867         /* Unneeded, already done by tg3_get_invariants.  */
12868         tg3_switch_clocks(tp);
12869 #endif
12870
12871         ret = 0;
12872         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12873             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12874                 goto out;
12875
12876         /* It is best to perform DMA test with maximum write burst size
12877          * to expose the 5700/5701 write DMA bug.
12878          */
12879         saved_dma_rwctrl = tp->dma_rwctrl;
12880         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12881         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12882
12883         while (1) {
12884                 u32 *p = buf, i;
12885
12886                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12887                         p[i] = i;
12888
12889                 /* Send the buffer to the chip. */
12890                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12891                 if (ret) {
12892                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12893                         break;
12894                 }
12895
12896 #if 0
12897                 /* validate data reached card RAM correctly. */
12898                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12899                         u32 val;
12900                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12901                         if (le32_to_cpu(val) != p[i]) {
12902                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12903                                 /* ret = -ENODEV here? */
12904                         }
12905                         p[i] = 0;
12906                 }
12907 #endif
12908                 /* Now read it back. */
12909                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12910                 if (ret) {
12911                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12912
12913                         break;
12914                 }
12915
12916                 /* Verify it. */
12917                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12918                         if (p[i] == i)
12919                                 continue;
12920
12921                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12922                             DMA_RWCTRL_WRITE_BNDRY_16) {
12923                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12924                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12925                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12926                                 break;
12927                         } else {
12928                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12929                                 ret = -ENODEV;
12930                                 goto out;
12931                         }
12932                 }
12933
12934                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12935                         /* Success. */
12936                         ret = 0;
12937                         break;
12938                 }
12939         }
12940         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12941             DMA_RWCTRL_WRITE_BNDRY_16) {
12942                 static struct pci_device_id dma_wait_state_chipsets[] = {
12943                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12944                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12945                         { },
12946                 };
12947
12948                 /* DMA test passed without adjusting DMA boundary,
12949                  * now look for chipsets that are known to expose the
12950                  * DMA bug without failing the test.
12951                  */
12952                 if (pci_dev_present(dma_wait_state_chipsets)) {
12953                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12954                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12955                 }
12956                 else
12957                         /* Safe to use the calculated DMA boundary. */
12958                         tp->dma_rwctrl = saved_dma_rwctrl;
12959
12960                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12961         }
12962
12963 out:
12964         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12965 out_nofree:
12966         return ret;
12967 }
12968
12969 static void __devinit tg3_init_link_config(struct tg3 *tp)
12970 {
12971         tp->link_config.advertising =
12972                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12973                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12974                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12975                  ADVERTISED_Autoneg | ADVERTISED_MII);
12976         tp->link_config.speed = SPEED_INVALID;
12977         tp->link_config.duplex = DUPLEX_INVALID;
12978         tp->link_config.autoneg = AUTONEG_ENABLE;
12979         tp->link_config.active_speed = SPEED_INVALID;
12980         tp->link_config.active_duplex = DUPLEX_INVALID;
12981         tp->link_config.phy_is_low_power = 0;
12982         tp->link_config.orig_speed = SPEED_INVALID;
12983         tp->link_config.orig_duplex = DUPLEX_INVALID;
12984         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12985 }
12986
12987 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12988 {
12989         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12990                 tp->bufmgr_config.mbuf_read_dma_low_water =
12991                         DEFAULT_MB_RDMA_LOW_WATER_5705;
12992                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12993                         DEFAULT_MB_MACRX_LOW_WATER_5705;
12994                 tp->bufmgr_config.mbuf_high_water =
12995                         DEFAULT_MB_HIGH_WATER_5705;
12996                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12997                         tp->bufmgr_config.mbuf_mac_rx_low_water =
12998                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
12999                         tp->bufmgr_config.mbuf_high_water =
13000                                 DEFAULT_MB_HIGH_WATER_5906;
13001                 }
13002
13003                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13004                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13005                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13006                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13007                 tp->bufmgr_config.mbuf_high_water_jumbo =
13008                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13009         } else {
13010                 tp->bufmgr_config.mbuf_read_dma_low_water =
13011                         DEFAULT_MB_RDMA_LOW_WATER;
13012                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13013                         DEFAULT_MB_MACRX_LOW_WATER;
13014                 tp->bufmgr_config.mbuf_high_water =
13015                         DEFAULT_MB_HIGH_WATER;
13016
13017                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13018                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13019                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13020                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13021                 tp->bufmgr_config.mbuf_high_water_jumbo =
13022                         DEFAULT_MB_HIGH_WATER_JUMBO;
13023         }
13024
13025         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13026         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13027 }
13028
13029 static char * __devinit tg3_phy_string(struct tg3 *tp)
13030 {
13031         switch (tp->phy_id & PHY_ID_MASK) {
13032         case PHY_ID_BCM5400:    return "5400";
13033         case PHY_ID_BCM5401:    return "5401";
13034         case PHY_ID_BCM5411:    return "5411";
13035         case PHY_ID_BCM5701:    return "5701";
13036         case PHY_ID_BCM5703:    return "5703";
13037         case PHY_ID_BCM5704:    return "5704";
13038         case PHY_ID_BCM5705:    return "5705";
13039         case PHY_ID_BCM5750:    return "5750";
13040         case PHY_ID_BCM5752:    return "5752";
13041         case PHY_ID_BCM5714:    return "5714";
13042         case PHY_ID_BCM5780:    return "5780";
13043         case PHY_ID_BCM5755:    return "5755";
13044         case PHY_ID_BCM5787:    return "5787";
13045         case PHY_ID_BCM5784:    return "5784";
13046         case PHY_ID_BCM5756:    return "5722/5756";
13047         case PHY_ID_BCM5906:    return "5906";
13048         case PHY_ID_BCM5761:    return "5761";
13049         case PHY_ID_BCM8002:    return "8002/serdes";
13050         case 0:                 return "serdes";
13051         default:                return "unknown";
13052         }
13053 }
13054
13055 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13056 {
13057         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13058                 strcpy(str, "PCI Express");
13059                 return str;
13060         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13061                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13062
13063                 strcpy(str, "PCIX:");
13064
13065                 if ((clock_ctrl == 7) ||
13066                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13067                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13068                         strcat(str, "133MHz");
13069                 else if (clock_ctrl == 0)
13070                         strcat(str, "33MHz");
13071                 else if (clock_ctrl == 2)
13072                         strcat(str, "50MHz");
13073                 else if (clock_ctrl == 4)
13074                         strcat(str, "66MHz");
13075                 else if (clock_ctrl == 6)
13076                         strcat(str, "100MHz");
13077         } else {
13078                 strcpy(str, "PCI:");
13079                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13080                         strcat(str, "66MHz");
13081                 else
13082                         strcat(str, "33MHz");
13083         }
13084         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13085                 strcat(str, ":32-bit");
13086         else
13087                 strcat(str, ":64-bit");
13088         return str;
13089 }
13090
13091 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13092 {
13093         struct pci_dev *peer;
13094         unsigned int func, devnr = tp->pdev->devfn & ~7;
13095
13096         for (func = 0; func < 8; func++) {
13097                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13098                 if (peer && peer != tp->pdev)
13099                         break;
13100                 pci_dev_put(peer);
13101         }
13102         /* 5704 can be configured in single-port mode, set peer to
13103          * tp->pdev in that case.
13104          */
13105         if (!peer) {
13106                 peer = tp->pdev;
13107                 return peer;
13108         }
13109
13110         /*
13111          * We don't need to keep the refcount elevated; there's no way
13112          * to remove one half of this device without removing the other
13113          */
13114         pci_dev_put(peer);
13115
13116         return peer;
13117 }
13118
13119 static void __devinit tg3_init_coal(struct tg3 *tp)
13120 {
13121         struct ethtool_coalesce *ec = &tp->coal;
13122
13123         memset(ec, 0, sizeof(*ec));
13124         ec->cmd = ETHTOOL_GCOALESCE;
13125         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13126         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13127         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13128         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13129         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13130         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13131         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13132         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13133         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13134
13135         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13136                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13137                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13138                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13139                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13140                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13141         }
13142
13143         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13144                 ec->rx_coalesce_usecs_irq = 0;
13145                 ec->tx_coalesce_usecs_irq = 0;
13146                 ec->stats_block_coalesce_usecs = 0;
13147         }
13148 }
13149
13150 static const struct net_device_ops tg3_netdev_ops = {
13151         .ndo_open               = tg3_open,
13152         .ndo_stop               = tg3_close,
13153         .ndo_start_xmit         = tg3_start_xmit,
13154         .ndo_get_stats          = tg3_get_stats,
13155         .ndo_validate_addr      = eth_validate_addr,
13156         .ndo_set_multicast_list = tg3_set_rx_mode,
13157         .ndo_set_mac_address    = tg3_set_mac_addr,
13158         .ndo_do_ioctl           = tg3_ioctl,
13159         .ndo_tx_timeout         = tg3_tx_timeout,
13160         .ndo_change_mtu         = tg3_change_mtu,
13161 #if TG3_VLAN_TAG_USED
13162         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13163 #endif
13164 #ifdef CONFIG_NET_POLL_CONTROLLER
13165         .ndo_poll_controller    = tg3_poll_controller,
13166 #endif
13167 };
13168
13169 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13170         .ndo_open               = tg3_open,
13171         .ndo_stop               = tg3_close,
13172         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13173         .ndo_get_stats          = tg3_get_stats,
13174         .ndo_validate_addr      = eth_validate_addr,
13175         .ndo_set_multicast_list = tg3_set_rx_mode,
13176         .ndo_set_mac_address    = tg3_set_mac_addr,
13177         .ndo_do_ioctl           = tg3_ioctl,
13178         .ndo_tx_timeout         = tg3_tx_timeout,
13179         .ndo_change_mtu         = tg3_change_mtu,
13180 #if TG3_VLAN_TAG_USED
13181         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13182 #endif
13183 #ifdef CONFIG_NET_POLL_CONTROLLER
13184         .ndo_poll_controller    = tg3_poll_controller,
13185 #endif
13186 };
13187
13188 static int __devinit tg3_init_one(struct pci_dev *pdev,
13189                                   const struct pci_device_id *ent)
13190 {
13191         static int tg3_version_printed = 0;
13192         struct net_device *dev;
13193         struct tg3 *tp;
13194         int err, pm_cap;
13195         char str[40];
13196         u64 dma_mask, persist_dma_mask;
13197
13198         if (tg3_version_printed++ == 0)
13199                 printk(KERN_INFO "%s", version);
13200
13201         err = pci_enable_device(pdev);
13202         if (err) {
13203                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13204                        "aborting.\n");
13205                 return err;
13206         }
13207
13208         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13209         if (err) {
13210                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13211                        "aborting.\n");
13212                 goto err_out_disable_pdev;
13213         }
13214
13215         pci_set_master(pdev);
13216
13217         /* Find power-management capability. */
13218         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13219         if (pm_cap == 0) {
13220                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13221                        "aborting.\n");
13222                 err = -EIO;
13223                 goto err_out_free_res;
13224         }
13225
13226         dev = alloc_etherdev(sizeof(*tp));
13227         if (!dev) {
13228                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13229                 err = -ENOMEM;
13230                 goto err_out_free_res;
13231         }
13232
13233         SET_NETDEV_DEV(dev, &pdev->dev);
13234
13235 #if TG3_VLAN_TAG_USED
13236         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13237 #endif
13238
13239         tp = netdev_priv(dev);
13240         tp->pdev = pdev;
13241         tp->dev = dev;
13242         tp->pm_cap = pm_cap;
13243         tp->rx_mode = TG3_DEF_RX_MODE;
13244         tp->tx_mode = TG3_DEF_TX_MODE;
13245
13246         if (tg3_debug > 0)
13247                 tp->msg_enable = tg3_debug;
13248         else
13249                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13250
13251         /* The word/byte swap controls here control register access byte
13252          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13253          * setting below.
13254          */
13255         tp->misc_host_ctrl =
13256                 MISC_HOST_CTRL_MASK_PCI_INT |
13257                 MISC_HOST_CTRL_WORD_SWAP |
13258                 MISC_HOST_CTRL_INDIR_ACCESS |
13259                 MISC_HOST_CTRL_PCISTATE_RW;
13260
13261         /* The NONFRM (non-frame) byte/word swap controls take effect
13262          * on descriptor entries, anything which isn't packet data.
13263          *
13264          * The StrongARM chips on the board (one for tx, one for rx)
13265          * are running in big-endian mode.
13266          */
13267         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13268                         GRC_MODE_WSWAP_NONFRM_DATA);
13269 #ifdef __BIG_ENDIAN
13270         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13271 #endif
13272         spin_lock_init(&tp->lock);
13273         spin_lock_init(&tp->indirect_lock);
13274         INIT_WORK(&tp->reset_task, tg3_reset_task);
13275
13276         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13277         if (!tp->regs) {
13278                 printk(KERN_ERR PFX "Cannot map device registers, "
13279                        "aborting.\n");
13280                 err = -ENOMEM;
13281                 goto err_out_free_dev;
13282         }
13283
13284         tg3_init_link_config(tp);
13285
13286         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13287         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13288         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13289
13290         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13291         dev->ethtool_ops = &tg3_ethtool_ops;
13292         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13293         dev->irq = pdev->irq;
13294
13295         err = tg3_get_invariants(tp);
13296         if (err) {
13297                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13298                        "aborting.\n");
13299                 goto err_out_iounmap;
13300         }
13301
13302         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13303             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13304                 dev->netdev_ops = &tg3_netdev_ops;
13305         else
13306                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13307
13308
13309         /* The EPB bridge inside 5714, 5715, and 5780 and any
13310          * device behind the EPB cannot support DMA addresses > 40-bit.
13311          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13312          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13313          * do DMA address check in tg3_start_xmit().
13314          */
13315         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13316                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13317         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13318                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13319 #ifdef CONFIG_HIGHMEM
13320                 dma_mask = DMA_BIT_MASK(64);
13321 #endif
13322         } else
13323                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13324
13325         /* Configure DMA attributes. */
13326         if (dma_mask > DMA_BIT_MASK(32)) {
13327                 err = pci_set_dma_mask(pdev, dma_mask);
13328                 if (!err) {
13329                         dev->features |= NETIF_F_HIGHDMA;
13330                         err = pci_set_consistent_dma_mask(pdev,
13331                                                           persist_dma_mask);
13332                         if (err < 0) {
13333                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13334                                        "DMA for consistent allocations\n");
13335                                 goto err_out_iounmap;
13336                         }
13337                 }
13338         }
13339         if (err || dma_mask == DMA_BIT_MASK(32)) {
13340                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13341                 if (err) {
13342                         printk(KERN_ERR PFX "No usable DMA configuration, "
13343                                "aborting.\n");
13344                         goto err_out_iounmap;
13345                 }
13346         }
13347
13348         tg3_init_bufmgr_config(tp);
13349
13350         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13351                 tp->fw_needed = FIRMWARE_TG3;
13352
13353         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13354                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13355         }
13356         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13357             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13358             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13359             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13360             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13361                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13362         } else {
13363                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13364                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13365                         tp->fw_needed = FIRMWARE_TG3TSO5;
13366                 else
13367                         tp->fw_needed = FIRMWARE_TG3TSO;
13368         }
13369
13370         /* TSO is on by default on chips that support hardware TSO.
13371          * Firmware TSO on older chips gives lower performance, so it
13372          * is off by default, but can be enabled using ethtool.
13373          */
13374         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13375                 if (dev->features & NETIF_F_IP_CSUM)
13376                         dev->features |= NETIF_F_TSO;
13377                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13378                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13379                         dev->features |= NETIF_F_TSO6;
13380                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13381                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13382                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13383                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13384                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13385                         dev->features |= NETIF_F_TSO_ECN;
13386         }
13387
13388
13389         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13390             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13391             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13392                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13393                 tp->rx_pending = 63;
13394         }
13395
13396         err = tg3_get_device_address(tp);
13397         if (err) {
13398                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13399                        "aborting.\n");
13400                 goto err_out_fw;
13401         }
13402
13403         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13404                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13405                 if (!tp->aperegs) {
13406                         printk(KERN_ERR PFX "Cannot map APE registers, "
13407                                "aborting.\n");
13408                         err = -ENOMEM;
13409                         goto err_out_fw;
13410                 }
13411
13412                 tg3_ape_lock_init(tp);
13413
13414                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13415                         tg3_read_dash_ver(tp);
13416         }
13417
13418         /*
13419          * Reset chip in case UNDI or EFI driver did not shutdown
13420          * DMA self test will enable WDMAC and we'll see (spurious)
13421          * pending DMA on the PCI bus at that point.
13422          */
13423         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13424             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13425                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13426                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13427         }
13428
13429         err = tg3_test_dma(tp);
13430         if (err) {
13431                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13432                 goto err_out_apeunmap;
13433         }
13434
13435         /* flow control autonegotiation is default behavior */
13436         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13437         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13438
13439         tg3_init_coal(tp);
13440
13441         pci_set_drvdata(pdev, dev);
13442
13443         err = register_netdev(dev);
13444         if (err) {
13445                 printk(KERN_ERR PFX "Cannot register net device, "
13446                        "aborting.\n");
13447                 goto err_out_apeunmap;
13448         }
13449
13450         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13451                dev->name,
13452                tp->board_part_number,
13453                tp->pci_chip_rev_id,
13454                tg3_bus_string(tp, str),
13455                dev->dev_addr);
13456
13457         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13458                 printk(KERN_INFO
13459                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13460                        tp->dev->name,
13461                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13462                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13463         else
13464                 printk(KERN_INFO
13465                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13466                        tp->dev->name, tg3_phy_string(tp),
13467                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13468                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13469                          "10/100/1000Base-T")),
13470                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13471
13472         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13473                dev->name,
13474                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13475                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13476                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13477                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13478                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13479         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13480                dev->name, tp->dma_rwctrl,
13481                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13482                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13483
13484         return 0;
13485
13486 err_out_apeunmap:
13487         if (tp->aperegs) {
13488                 iounmap(tp->aperegs);
13489                 tp->aperegs = NULL;
13490         }
13491
13492 err_out_fw:
13493         if (tp->fw)
13494                 release_firmware(tp->fw);
13495
13496 err_out_iounmap:
13497         if (tp->regs) {
13498                 iounmap(tp->regs);
13499                 tp->regs = NULL;
13500         }
13501
13502 err_out_free_dev:
13503         free_netdev(dev);
13504
13505 err_out_free_res:
13506         pci_release_regions(pdev);
13507
13508 err_out_disable_pdev:
13509         pci_disable_device(pdev);
13510         pci_set_drvdata(pdev, NULL);
13511         return err;
13512 }
13513
13514 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13515 {
13516         struct net_device *dev = pci_get_drvdata(pdev);
13517
13518         if (dev) {
13519                 struct tg3 *tp = netdev_priv(dev);
13520
13521                 if (tp->fw)
13522                         release_firmware(tp->fw);
13523
13524                 flush_scheduled_work();
13525
13526                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13527                         tg3_phy_fini(tp);
13528                         tg3_mdio_fini(tp);
13529                 }
13530
13531                 unregister_netdev(dev);
13532                 if (tp->aperegs) {
13533                         iounmap(tp->aperegs);
13534                         tp->aperegs = NULL;
13535                 }
13536                 if (tp->regs) {
13537                         iounmap(tp->regs);
13538                         tp->regs = NULL;
13539                 }
13540                 free_netdev(dev);
13541                 pci_release_regions(pdev);
13542                 pci_disable_device(pdev);
13543                 pci_set_drvdata(pdev, NULL);
13544         }
13545 }
13546
13547 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13548 {
13549         struct net_device *dev = pci_get_drvdata(pdev);
13550         struct tg3 *tp = netdev_priv(dev);
13551         pci_power_t target_state;
13552         int err;
13553
13554         /* PCI register 4 needs to be saved whether netif_running() or not.
13555          * MSI address and data need to be saved if using MSI and
13556          * netif_running().
13557          */
13558         pci_save_state(pdev);
13559
13560         if (!netif_running(dev))
13561                 return 0;
13562
13563         flush_scheduled_work();
13564         tg3_phy_stop(tp);
13565         tg3_netif_stop(tp);
13566
13567         del_timer_sync(&tp->timer);
13568
13569         tg3_full_lock(tp, 1);
13570         tg3_disable_ints(tp);
13571         tg3_full_unlock(tp);
13572
13573         netif_device_detach(dev);
13574
13575         tg3_full_lock(tp, 0);
13576         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13577         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13578         tg3_full_unlock(tp);
13579
13580         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13581
13582         err = tg3_set_power_state(tp, target_state);
13583         if (err) {
13584                 int err2;
13585
13586                 tg3_full_lock(tp, 0);
13587
13588                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13589                 err2 = tg3_restart_hw(tp, 1);
13590                 if (err2)
13591                         goto out;
13592
13593                 tp->timer.expires = jiffies + tp->timer_offset;
13594                 add_timer(&tp->timer);
13595
13596                 netif_device_attach(dev);
13597                 tg3_netif_start(tp);
13598
13599 out:
13600                 tg3_full_unlock(tp);
13601
13602                 if (!err2)
13603                         tg3_phy_start(tp);
13604         }
13605
13606         return err;
13607 }
13608
13609 static int tg3_resume(struct pci_dev *pdev)
13610 {
13611         struct net_device *dev = pci_get_drvdata(pdev);
13612         struct tg3 *tp = netdev_priv(dev);
13613         int err;
13614
13615         pci_restore_state(tp->pdev);
13616
13617         if (!netif_running(dev))
13618                 return 0;
13619
13620         err = tg3_set_power_state(tp, PCI_D0);
13621         if (err)
13622                 return err;
13623
13624         netif_device_attach(dev);
13625
13626         tg3_full_lock(tp, 0);
13627
13628         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13629         err = tg3_restart_hw(tp, 1);
13630         if (err)
13631                 goto out;
13632
13633         tp->timer.expires = jiffies + tp->timer_offset;
13634         add_timer(&tp->timer);
13635
13636         tg3_netif_start(tp);
13637
13638 out:
13639         tg3_full_unlock(tp);
13640
13641         if (!err)
13642                 tg3_phy_start(tp);
13643
13644         return err;
13645 }
13646
13647 static struct pci_driver tg3_driver = {
13648         .name           = DRV_MODULE_NAME,
13649         .id_table       = tg3_pci_tbl,
13650         .probe          = tg3_init_one,
13651         .remove         = __devexit_p(tg3_remove_one),
13652         .suspend        = tg3_suspend,
13653         .resume         = tg3_resume
13654 };
13655
13656 static int __init tg3_init(void)
13657 {
13658         return pci_register_driver(&tg3_driver);
13659 }
13660
13661 static void __exit tg3_cleanup(void)
13662 {
13663         pci_unregister_driver(&tg3_driver);
13664 }
13665
13666 module_init(tg3_init);
13667 module_exit(tg3_cleanup);