drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     114
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "September 30, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_STD_RING_SIZE(tp) \
 105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 107          RX_STD_MAX_SIZE_5717 : 512)
 108 #define TG3_DEF_RX_RING_PENDING         200
 109 #define TG3_RX_JMB_RING_SIZE(tp) \
 110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 112          1024 : 256)
 113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 114 #define TG3_RSS_INDIR_TBL_SIZE          128
 115
 116 /* Do not place this n-ring entries value into the tp struct itself,
 117  * we really want to expose these constants to GCC so that modulo et
 118  * al.  operations are done with shifts and masks instead of with
 119  * hw multiply/modulo instructions.  Another solution would be to
 120  * replace things like '% foo' with '& (foo - 1)'.
 121  */
 122
 123 #define TG3_TX_RING_SIZE                512
 124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 125
 126 #define TG3_RX_STD_RING_BYTES(tp) \
 127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 128 #define TG3_RX_JMB_RING_BYTES(tp) \
 129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 130 #define TG3_RX_RCB_RING_BYTES(tp) \
 131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 133                                  TG3_TX_RING_SIZE)
 134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 135
 136 #define TG3_RX_DMA_ALIGN                16
 137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 138
 139 #define TG3_DMA_BYTE_ENAB               64
 140
 141 #define TG3_RX_STD_DMA_SZ               1536
 142 #define TG3_RX_JMB_DMA_SZ               9046
 143
 144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 145
 146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 148
 149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 151
 152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 154
 155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 156  * that are at least dword aligned when used in PCIX mode.  The driver
 157  * works around this bug by double copying the packet.  This workaround
 158  * is built into the normal double copy length check for efficiency.
 159  *
 160  * However, the double copy is only necessary on those architectures
 161  * where unaligned memory accesses are inefficient.  For those architectures
 162  * where unaligned memory accesses incur little penalty, we can reintegrate
 163  * the 5701 in the normal rx path.  Doing so saves a device structure
 164  * dereference by hardcoding the double copy threshold in place.
 165  */
 166 #define TG3_RX_COPY_THRESHOLD           256
 167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 169 #else
 170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 171 #endif
 172
 173 /* minimum number of free TX descriptors required to wake up TX process */
 174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 175
 176 #define TG3_RAW_IP_ALIGN 2
 177
 178 /* number of ETHTOOL_GSTATS u64's */
 179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 180
 181 #define TG3_NUM_TEST            6
 182
 183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 184
 185 #define FIRMWARE_TG3            "tigon/tg3.bin"
 186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 188
 189 static char version[] __devinitdata =
 190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 191
 192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 194 MODULE_LICENSE("GPL");
 195 MODULE_VERSION(DRV_MODULE_VERSION);
 196 MODULE_FIRMWARE(FIRMWARE_TG3);
 197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 199
 200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 201 module_param(tg3_debug, int, 0);
 202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 203
 204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 284         {}
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 288
 289 static const struct {
 290         const char string[ETH_GSTRING_LEN];
 291 } ethtool_stats_keys[TG3_NUM_STATS] = {
 292         { "rx_octets" },
 293         { "rx_fragments" },
 294         { "rx_ucast_packets" },
 295         { "rx_mcast_packets" },
 296         { "rx_bcast_packets" },
 297         { "rx_fcs_errors" },
 298         { "rx_align_errors" },
 299         { "rx_xon_pause_rcvd" },
 300         { "rx_xoff_pause_rcvd" },
 301         { "rx_mac_ctrl_rcvd" },
 302         { "rx_xoff_entered" },
 303         { "rx_frame_too_long_errors" },
 304         { "rx_jabbers" },
 305         { "rx_undersize_packets" },
 306         { "rx_in_length_errors" },
 307         { "rx_out_length_errors" },
 308         { "rx_64_or_less_octet_packets" },
 309         { "rx_65_to_127_octet_packets" },
 310         { "rx_128_to_255_octet_packets" },
 311         { "rx_256_to_511_octet_packets" },
 312         { "rx_512_to_1023_octet_packets" },
 313         { "rx_1024_to_1522_octet_packets" },
 314         { "rx_1523_to_2047_octet_packets" },
 315         { "rx_2048_to_4095_octet_packets" },
 316         { "rx_4096_to_8191_octet_packets" },
 317         { "rx_8192_to_9022_octet_packets" },
 318
 319         { "tx_octets" },
 320         { "tx_collisions" },
 321
 322         { "tx_xon_sent" },
 323         { "tx_xoff_sent" },
 324         { "tx_flow_control" },
 325         { "tx_mac_errors" },
 326         { "tx_single_collisions" },
 327         { "tx_mult_collisions" },
 328         { "tx_deferred" },
 329         { "tx_excessive_collisions" },
 330         { "tx_late_collisions" },
 331         { "tx_collide_2times" },
 332         { "tx_collide_3times" },
 333         { "tx_collide_4times" },
 334         { "tx_collide_5times" },
 335         { "tx_collide_6times" },
 336         { "tx_collide_7times" },
 337         { "tx_collide_8times" },
 338         { "tx_collide_9times" },
 339         { "tx_collide_10times" },
 340         { "tx_collide_11times" },
 341         { "tx_collide_12times" },
 342         { "tx_collide_13times" },
 343         { "tx_collide_14times" },
 344         { "tx_collide_15times" },
 345         { "tx_ucast_packets" },
 346         { "tx_mcast_packets" },
 347         { "tx_bcast_packets" },
 348         { "tx_carrier_sense_errors" },
 349         { "tx_discards" },
 350         { "tx_errors" },
 351
 352         { "dma_writeq_full" },
 353         { "dma_write_prioq_full" },
 354         { "rxbds_empty" },
 355         { "rx_discards" },
 356         { "rx_errors" },
 357         { "rx_threshold_hit" },
 358
 359         { "dma_readq_full" },
 360         { "dma_read_prioq_full" },
 361         { "tx_comp_queue_full" },
 362
 363         { "ring_set_send_prod_index" },
 364         { "ring_status_update" },
 365         { "nic_irqs" },
 366         { "nic_avoided_irqs" },
 367         { "nic_tx_threshold_hit" }
 368 };
 369
 370 static const struct {
 371         const char string[ETH_GSTRING_LEN];
 372 } ethtool_test_keys[TG3_NUM_TEST] = {
 373         { "nvram test     (online) " },
 374         { "link test      (online) " },
 375         { "register test  (offline)" },
 376         { "memory test    (offline)" },
 377         { "loopback test  (offline)" },
 378         { "interrupt test (offline)" },
 379 };
 380
 381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384 }
 385
 386 static u32 tg3_read32(struct tg3 *tp, u32 off)
 387 {
 388         return readl(tp->regs + off);
 389 }
 390
 391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 392 {
 393         writel(val, tp->aperegs + off);
 394 }
 395
 396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 397 {
 398         return readl(tp->aperegs + off);
 399 }
 400
 401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409 }
 410
 411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         writel(val, tp->regs + off);
 414         readl(tp->regs + off);
 415 }
 416
 417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 430 {
 431         unsigned long flags;
 432
 433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 435                                        TG3_64BIT_REG_LOW, val);
 436                 return;
 437         }
 438         if (off == TG3_RX_STD_PROD_IDX_REG) {
 439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 440                                        TG3_64BIT_REG_LOW, val);
 441                 return;
 442         }
 443
 444         spin_lock_irqsave(&tp->indirect_lock, flags);
 445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 448
 449         /* In indirect mode when disabling interrupts, we also need
 450          * to clear the interrupt bit in the GRC local ctrl register.
 451          */
 452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 453             (val == 0x1)) {
 454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 456         }
 457 }
 458
 459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 460 {
 461         unsigned long flags;
 462         u32 val;
 463
 464         spin_lock_irqsave(&tp->indirect_lock, flags);
 465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 468         return val;
 469 }
 470
 471 /* usec_wait specifies the wait time in usec when writing to certain registers
 472  * where it is unsafe to read back the register without some delay.
 473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 475  */
 476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 477 {
 478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 480                 /* Non-posted methods */
 481                 tp->write32(tp, off, val);
 482         else {
 483                 /* Posted method */
 484                 tg3_write32(tp, off, val);
 485                 if (usec_wait)
 486                         udelay(usec_wait);
 487                 tp->read32(tp, off);
 488         }
 489         /* Wait again after the read for the posted method to guarantee that
 490          * the wait time is met.
 491          */
 492         if (usec_wait)
 493                 udelay(usec_wait);
 494 }
 495
 496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         tp->write32_mbox(tp, off, val);
 499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 501                 tp->read32_mbox(tp, off);
 502 }
 503
 504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 505 {
 506         void __iomem *mbox = tp->regs + off;
 507         writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 509                 writel(val, mbox);
 510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 511                 readl(mbox);
 512 }
 513
 514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 515 {
 516         return readl(tp->regs + off + GRCMBOX_BASE);
 517 }
 518
 519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 520 {
 521         writel(val, tp->regs + off + GRCMBOX_BASE);
 522 }
 523
 524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 529
 530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 533 #define tr32(reg)                       tp->read32(tp, reg)
 534
 535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 536 {
 537         unsigned long flags;
 538
 539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 541                 return;
 542
 543         spin_lock_irqsave(&tp->indirect_lock, flags);
 544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 547
 548                 /* Always leave this as zero. */
 549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 550         } else {
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 553
 554                 /* Always leave this as zero. */
 555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 556         }
 557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 558 }
 559
 560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 561 {
 562         unsigned long flags;
 563
 564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 566                 *val = 0;
 567                 return;
 568         }
 569
 570         spin_lock_irqsave(&tp->indirect_lock, flags);
 571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 574
 575                 /* Always leave this as zero. */
 576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 577         } else {
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 580
 581                 /* Always leave this as zero. */
 582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 583         }
 584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 585 }
 586
 587 static void tg3_ape_lock_init(struct tg3 *tp)
 588 {
 589         int i;
 590         u32 regbase;
 591
 592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 593                 regbase = TG3_APE_LOCK_GRANT;
 594         else
 595                 regbase = TG3_APE_PER_LOCK_GRANT;
 596
 597         /* Make sure the driver hasn't any stale locks. */
 598         for (i = 0; i < 8; i++)
 599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 600 }
 601
 602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 603 {
 604         int i, off;
 605         int ret = 0;
 606         u32 status, req, gnt;
 607
 608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 609                 return 0;
 610
 611         switch (locknum) {
 612         case TG3_APE_LOCK_GRC:
 613         case TG3_APE_LOCK_MEM:
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618
 619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 620                 req = TG3_APE_LOCK_REQ;
 621                 gnt = TG3_APE_LOCK_GRANT;
 622         } else {
 623                 req = TG3_APE_PER_LOCK_REQ;
 624                 gnt = TG3_APE_PER_LOCK_GRANT;
 625         }
 626
 627         off = 4 * locknum;
 628
 629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 630
 631         /* Wait for up to 1 millisecond to acquire lock. */
 632         for (i = 0; i < 100; i++) {
 633                 status = tg3_ape_read32(tp, gnt + off);
 634                 if (status == APE_LOCK_GRANT_DRIVER)
 635                         break;
 636                 udelay(10);
 637         }
 638
 639         if (status != APE_LOCK_GRANT_DRIVER) {
 640                 /* Revoke the lock request. */
 641                 tg3_ape_write32(tp, gnt + off,
 642                                 APE_LOCK_GRANT_DRIVER);
 643
 644                 ret = -EBUSY;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 651 {
 652         u32 gnt;
 653
 654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 655                 return;
 656
 657         switch (locknum) {
 658         case TG3_APE_LOCK_GRC:
 659         case TG3_APE_LOCK_MEM:
 660                 break;
 661         default:
 662                 return;
 663         }
 664
 665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 666                 gnt = TG3_APE_LOCK_GRANT;
 667         else
 668                 gnt = TG3_APE_PER_LOCK_GRANT;
 669
 670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 671 }
 672
 673 static void tg3_disable_ints(struct tg3 *tp)
 674 {
 675         int i;
 676
 677         tw32(TG3PCI_MISC_HOST_CTRL,
 678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 679         for (i = 0; i < tp->irq_max; i++)
 680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 681 }
 682
 683 static void tg3_enable_ints(struct tg3 *tp)
 684 {
 685         int i;
 686
 687         tp->irq_sync = 0;
 688         wmb();
 689
 690         tw32(TG3PCI_MISC_HOST_CTRL,
 691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 692
 693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 694         for (i = 0; i < tp->irq_cnt; i++) {
 695                 struct tg3_napi *tnapi = &tp->napi[i];
 696
 697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 700
 701                 tp->coal_now |= tnapi->coal_now;
 702         }
 703
 704         /* Force an initial interrupt */
 705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 708         else
 709                 tw32(HOSTCC_MODE, tp->coal_now);
 710
 711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 712 }
 713
 714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 715 {
 716         struct tg3 *tp = tnapi->tp;
 717         struct tg3_hw_status *sblk = tnapi->hw_status;
 718         unsigned int work_exists = 0;
 719
 720         /* check for phy events */
 721         if (!(tp->tg3_flags &
 722               (TG3_FLAG_USE_LINKCHG_REG |
 723                TG3_FLAG_POLL_SERDES))) {
 724                 if (sblk->status & SD_STATUS_LINK_CHG)
 725                         work_exists = 1;
 726         }
 727         /* check for RX/TX work to do */
 728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 730                 work_exists = 1;
 731
 732         return work_exists;
 733 }
 734
 735 /* tg3_int_reenable
 736  *  similar to tg3_enable_ints, but it accurately determines whether there
 737  *  is new work pending and can return without flushing the PIO write
 738  *  which reenables interrupts
 739  */
 740 static void tg3_int_reenable(struct tg3_napi *tnapi)
 741 {
 742         struct tg3 *tp = tnapi->tp;
 743
 744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 745         mmiowb();
 746
 747         /* When doing tagged status, this work check is unnecessary.
 748          * The last_tag we write above tells the chip which piece of
 749          * work we've completed.
 750          */
 751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 752             tg3_has_work(tnapi))
 753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 755 }
 756
 757 static void tg3_switch_clocks(struct tg3 *tp)
 758 {
 759         u32 clock_ctrl;
 760         u32 orig_clock_ctrl;
 761
 762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 764                 return;
 765
 766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 767
 768         orig_clock_ctrl = clock_ctrl;
 769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 770                        CLOCK_CTRL_CLKRUN_OENABLE |
 771                        0x1f);
 772         tp->pci_clock_ctrl = clock_ctrl;
 773
 774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 778                 }
 779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 781                             clock_ctrl |
 782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 783                             40);
 784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 786                             40);
 787         }
 788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 789 }
 790
 791 #define PHY_BUSY_LOOPS  5000
 792
 793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 794 {
 795         u32 frame_val;
 796         unsigned int loops;
 797         int ret;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE,
 801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 802                 udelay(80);
 803         }
 804
 805         *val = 0x0;
 806
 807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 808                       MI_COM_PHY_ADDR_MASK);
 809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 810                       MI_COM_REG_ADDR_MASK);
 811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 812
 813         tw32_f(MAC_MI_COM, frame_val);
 814
 815         loops = PHY_BUSY_LOOPS;
 816         while (loops != 0) {
 817                 udelay(10);
 818                 frame_val = tr32(MAC_MI_COM);
 819
 820                 if ((frame_val & MI_COM_BUSY) == 0) {
 821                         udelay(5);
 822                         frame_val = tr32(MAC_MI_COM);
 823                         break;
 824                 }
 825                 loops -= 1;
 826         }
 827
 828         ret = -EBUSY;
 829         if (loops != 0) {
 830                 *val = frame_val & MI_COM_DATA_MASK;
 831                 ret = 0;
 832         }
 833
 834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 836                 udelay(80);
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 843 {
 844         u32 frame_val;
 845         unsigned int loops;
 846         int ret;
 847
 848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 850                 return 0;
 851
 852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 853                 tw32_f(MAC_MI_MODE,
 854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 855                 udelay(80);
 856         }
 857
 858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 859                       MI_COM_PHY_ADDR_MASK);
 860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 861                       MI_COM_REG_ADDR_MASK);
 862         frame_val |= (val & MI_COM_DATA_MASK);
 863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 864
 865         tw32_f(MAC_MI_COM, frame_val);
 866
 867         loops = PHY_BUSY_LOOPS;
 868         while (loops != 0) {
 869                 udelay(10);
 870                 frame_val = tr32(MAC_MI_COM);
 871                 if ((frame_val & MI_COM_BUSY) == 0) {
 872                         udelay(5);
 873                         frame_val = tr32(MAC_MI_COM);
 874                         break;
 875                 }
 876                 loops -= 1;
 877         }
 878
 879         ret = -EBUSY;
 880         if (loops != 0)
 881                 ret = 0;
 882
 883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 885                 udelay(80);
 886         }
 887
 888         return ret;
 889 }
 890
 891 static int tg3_bmcr_reset(struct tg3 *tp)
 892 {
 893         u32 phy_control;
 894         int limit, err;
 895
 896         /* OK, reset it, and poll the BMCR_RESET bit until it
 897          * clears or we time out.
 898          */
 899         phy_control = BMCR_RESET;
 900         err = tg3_writephy(tp, MII_BMCR, phy_control);
 901         if (err != 0)
 902                 return -EBUSY;
 903
 904         limit = 5000;
 905         while (limit--) {
 906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 907                 if (err != 0)
 908                         return -EBUSY;
 909
 910                 if ((phy_control & BMCR_RESET) == 0) {
 911                         udelay(40);
 912                         break;
 913                 }
 914                 udelay(10);
 915         }
 916         if (limit < 0)
 917                 return -EBUSY;
 918
 919         return 0;
 920 }
 921
 922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 923 {
 924         struct tg3 *tp = bp->priv;
 925         u32 val;
 926
 927         spin_lock_bh(&tp->lock);
 928
 929         if (tg3_readphy(tp, reg, &val))
 930                 val = -EIO;
 931
 932         spin_unlock_bh(&tp->lock);
 933
 934         return val;
 935 }
 936
 937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 938 {
 939         struct tg3 *tp = bp->priv;
 940         u32 ret = 0;
 941
 942         spin_lock_bh(&tp->lock);
 943
 944         if (tg3_writephy(tp, reg, val))
 945                 ret = -EIO;
 946
 947         spin_unlock_bh(&tp->lock);
 948
 949         return ret;
 950 }
 951
 952 static int tg3_mdio_reset(struct mii_bus *bp)
 953 {
 954         return 0;
 955 }
 956
 957 static void tg3_mdio_config_5785(struct tg3 *tp)
 958 {
 959         u32 val;
 960         struct phy_device *phydev;
 961
 962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 964         case PHY_ID_BCM50610:
 965         case PHY_ID_BCM50610M:
 966                 val = MAC_PHYCFG2_50610_LED_MODES;
 967                 break;
 968         case PHY_ID_BCMAC131:
 969                 val = MAC_PHYCFG2_AC131_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8211C:
 972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 973                 break;
 974         case PHY_ID_RTL8201E:
 975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 976                 break;
 977         default:
 978                 return;
 979         }
 980
 981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 982                 tw32(MAC_PHYCFG2, val);
 983
 984                 val = tr32(MAC_PHYCFG1);
 985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 988                 tw32(MAC_PHYCFG1, val);
 989
 990                 return;
 991         }
 992
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 995                        MAC_PHYCFG2_FMODE_MASK_MASK |
 996                        MAC_PHYCFG2_GMODE_MASK_MASK |
 997                        MAC_PHYCFG2_ACT_MASK_MASK   |
 998                        MAC_PHYCFG2_QUAL_MASK_MASK |
 999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1599 {
1600         u32 phytest;
1601
1602         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1603                 u32 phy;
1604
1605                 tg3_writephy(tp, MII_TG3_FET_TEST,
1606                              phytest | MII_TG3_FET_SHADOW_EN);
1607                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1608                         if (enable)
1609                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1610                         else
1611                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1612                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1613                 }
1614                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1615         }
1616 }
1617
1618 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1619 {
1620         u32 reg;
1621
1622         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1623             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1624               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1625              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1626                 return;
1627
1628         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1629                 tg3_phy_fet_toggle_apd(tp, enable);
1630                 return;
1631         }
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_SCR5_SEL |
1635               MII_TG3_MISC_SHDW_SCR5_LPED |
1636               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1637               MII_TG3_MISC_SHDW_SCR5_SDTL |
1638               MII_TG3_MISC_SHDW_SCR5_C125OE;
1639         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1640                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1641
1642         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1643
1644
1645         reg = MII_TG3_MISC_SHDW_WREN |
1646               MII_TG3_MISC_SHDW_APD_SEL |
1647               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1648         if (enable)
1649                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1650
1651         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1652 }
1653
1654 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1655 {
1656         u32 phy;
1657
1658         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1659             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1660                 return;
1661
1662         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1663                 u32 ephy;
1664
1665                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1666                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1667
1668                         tg3_writephy(tp, MII_TG3_FET_TEST,
1669                                      ephy | MII_TG3_FET_SHADOW_EN);
1670                         if (!tg3_readphy(tp, reg, &phy)) {
1671                                 if (enable)
1672                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1673                                 else
1674                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1675                                 tg3_writephy(tp, reg, phy);
1676                         }
1677                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1678                 }
1679         } else {
1680                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1681                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1682                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1683                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1684                         if (enable)
1685                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1686                         else
1687                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1688                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1689                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1690                 }
1691         }
1692 }
1693
1694 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1695 {
1696         u32 val;
1697
1698         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1699                 return;
1700
1701         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1702             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1703                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1704                              (val | (1 << 15) | (1 << 4)));
1705 }
1706
1707 static void tg3_phy_apply_otp(struct tg3 *tp)
1708 {
1709         u32 otp, phy;
1710
1711         if (!tp->phy_otp)
1712                 return;
1713
1714         otp = tp->phy_otp;
1715
1716         /* Enable SM_DSP clock and tx 6dB coding. */
1717         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1718               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1719               MII_TG3_AUXCTL_ACTL_TX_6DB;
1720         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1721
1722         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1723         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1724         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1725
1726         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1727               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1728         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1729
1730         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1731         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1732         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1733
1734         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1735         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1736
1737         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1739
1740         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1741               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1742         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1743
1744         /* Turn off SM_DSP clock. */
1745         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1746               MII_TG3_AUXCTL_ACTL_TX_6DB;
1747         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1748 }
1749
1750 static int tg3_wait_macro_done(struct tg3 *tp)
1751 {
1752         int limit = 100;
1753
1754         while (limit--) {
1755                 u32 tmp32;
1756
1757                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1758                         if ((tmp32 & 0x1000) == 0)
1759                                 break;
1760                 }
1761         }
1762         if (limit < 0)
1763                 return -EBUSY;
1764
1765         return 0;
1766 }
1767
1768 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1769 {
1770         static const u32 test_pat[4][6] = {
1771         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1772         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1773         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1774         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1775         };
1776         int chan;
1777
1778         for (chan = 0; chan < 4; chan++) {
1779                 int i;
1780
1781                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782                              (chan * 0x2000) | 0x0200);
1783                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1784
1785                 for (i = 0; i < 6; i++)
1786                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1787                                      test_pat[chan][i]);
1788
1789                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1790                 if (tg3_wait_macro_done(tp)) {
1791                         *resetp = 1;
1792                         return -EBUSY;
1793                 }
1794
1795                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1796                              (chan * 0x2000) | 0x0200);
1797                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1798                 if (tg3_wait_macro_done(tp)) {
1799                         *resetp = 1;
1800                         return -EBUSY;
1801                 }
1802
1803                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1804                 if (tg3_wait_macro_done(tp)) {
1805                         *resetp = 1;
1806                         return -EBUSY;
1807                 }
1808
1809                 for (i = 0; i < 6; i += 2) {
1810                         u32 low, high;
1811
1812                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1813                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1814                             tg3_wait_macro_done(tp)) {
1815                                 *resetp = 1;
1816                                 return -EBUSY;
1817                         }
1818                         low &= 0x7fff;
1819                         high &= 0x000f;
1820                         if (low != test_pat[chan][i] ||
1821                             high != test_pat[chan][i+1]) {
1822                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1823                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1824                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1825
1826                                 return -EBUSY;
1827                         }
1828                 }
1829         }
1830
1831         return 0;
1832 }
1833
1834 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1835 {
1836         int chan;
1837
1838         for (chan = 0; chan < 4; chan++) {
1839                 int i;
1840
1841                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1842                              (chan * 0x2000) | 0x0200);
1843                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1844                 for (i = 0; i < 6; i++)
1845                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1846                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1847                 if (tg3_wait_macro_done(tp))
1848                         return -EBUSY;
1849         }
1850
1851         return 0;
1852 }
1853
1854 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1855 {
1856         u32 reg32, phy9_orig;
1857         int retries, do_phy_reset, err;
1858
1859         retries = 10;
1860         do_phy_reset = 1;
1861         do {
1862                 if (do_phy_reset) {
1863                         err = tg3_bmcr_reset(tp);
1864                         if (err)
1865                                 return err;
1866                         do_phy_reset = 0;
1867                 }
1868
1869                 /* Disable transmitter and interrupt.  */
1870                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1871                         continue;
1872
1873                 reg32 |= 0x3000;
1874                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1875
1876                 /* Set full-duplex, 1000 mbps.  */
1877                 tg3_writephy(tp, MII_BMCR,
1878                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1879
1880                 /* Set to master mode.  */
1881                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1882                         continue;
1883
1884                 tg3_writephy(tp, MII_TG3_CTRL,
1885                              (MII_TG3_CTRL_AS_MASTER |
1886                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1887
1888                 /* Enable SM_DSP_CLOCK and 6dB.  */
1889                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1890
1891                 /* Block the PHY control access.  */
1892                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1893
1894                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1895                 if (!err)
1896                         break;
1897         } while (--retries);
1898
1899         err = tg3_phy_reset_chanpat(tp);
1900         if (err)
1901                 return err;
1902
1903         tg3_phydsp_write(tp, 0x8005, 0x0000);
1904
1905         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1906         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1907
1908         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1909             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1910                 /* Set Extended packet length bit for jumbo frames */
1911                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1912         } else {
1913                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1914         }
1915
1916         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1917
1918         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1919                 reg32 &= ~0x3000;
1920                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1921         } else if (!err)
1922                 err = -EBUSY;
1923
1924         return err;
1925 }
1926
1927 /* This will reset the tigon3 PHY if there is no valid
1928  * link unless the FORCE argument is non-zero.
1929  */
1930 static int tg3_phy_reset(struct tg3 *tp)
1931 {
1932         u32 val, cpmuctrl;
1933         int err;
1934
1935         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1936                 val = tr32(GRC_MISC_CFG);
1937                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1938                 udelay(40);
1939         }
1940         err  = tg3_readphy(tp, MII_BMSR, &val);
1941         err |= tg3_readphy(tp, MII_BMSR, &val);
1942         if (err != 0)
1943                 return -EBUSY;
1944
1945         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1946                 netif_carrier_off(tp->dev);
1947                 tg3_link_report(tp);
1948         }
1949
1950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1951             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1952             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1953                 err = tg3_phy_reset_5703_4_5(tp);
1954                 if (err)
1955                         return err;
1956                 goto out;
1957         }
1958
1959         cpmuctrl = 0;
1960         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1961             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1962                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1963                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1964                         tw32(TG3_CPMU_CTRL,
1965                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1966         }
1967
1968         err = tg3_bmcr_reset(tp);
1969         if (err)
1970                 return err;
1971
1972         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1973                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1974                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1975
1976                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1977         }
1978
1979         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1980             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1981                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1982                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1983                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1984                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1985                         udelay(40);
1986                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1987                 }
1988         }
1989
1990         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1991              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1992             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1993                 return 0;
1994
1995         tg3_phy_apply_otp(tp);
1996
1997         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1998                 tg3_phy_toggle_apd(tp, true);
1999         else
2000                 tg3_phy_toggle_apd(tp, false);
2001
2002 out:
2003         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2004                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2005                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2006                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2007                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2008         }
2009         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2010                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2011                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2012         }
2013         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2015                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2016                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2017                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2019         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2021                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2022                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2024                         tg3_writephy(tp, MII_TG3_TEST1,
2025                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2026                 } else
2027                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2028                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2029         }
2030         /* Set Extended packet length bit (bit 14) on all chips that */
2031         /* support jumbo frames */
2032         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2033                 /* Cannot do read-modify-write on 5401 */
2034                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2035         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2036                 /* Set bit 14 with read-modify-write to preserve other bits */
2037                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2038                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2039                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2040         }
2041
2042         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2043          * jumbo frames transmission.
2044          */
2045         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2046                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2047                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2048                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2049         }
2050
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2052                 /* adjust output voltage */
2053                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2054         }
2055
2056         tg3_phy_toggle_automdix(tp, 1);
2057         tg3_phy_set_wirespeed(tp);
2058         return 0;
2059 }
2060
2061 static void tg3_frob_aux_power(struct tg3 *tp)
2062 {
2063         struct tg3 *tp_peer = tp;
2064
2065         /* The GPIOs do something completely different on 57765. */
2066         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2069                 return;
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2074                 struct net_device *dev_peer;
2075
2076                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2077                 /* remove_one() may have been run on the peer. */
2078                 if (!dev_peer)
2079                         tp_peer = tp;
2080                 else
2081                         tp_peer = netdev_priv(dev_peer);
2082         }
2083
2084         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2085             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2087             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2088                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2089                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2090                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2091                                     (GRC_LCLCTRL_GPIO_OE0 |
2092                                      GRC_LCLCTRL_GPIO_OE1 |
2093                                      GRC_LCLCTRL_GPIO_OE2 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2096                                     100);
2097                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2098                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2099                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2100                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2101                                              GRC_LCLCTRL_GPIO_OE1 |
2102                                              GRC_LCLCTRL_GPIO_OE2 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2104                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2105                                              tp->grc_local_ctrl;
2106                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2107
2108                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2109                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2110
2111                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2112                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2113                 } else {
2114                         u32 no_gpio2;
2115                         u32 grc_local_ctrl = 0;
2116
2117                         if (tp_peer != tp &&
2118                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2119                                 return;
2120
2121                         /* Workaround to prevent overdrawing Amps. */
2122                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2123                             ASIC_REV_5714) {
2124                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2125                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126                                             grc_local_ctrl, 100);
2127                         }
2128
2129                         /* On 5753 and variants, GPIO2 cannot be used. */
2130                         no_gpio2 = tp->nic_sram_data_cfg &
2131                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2134                                          GRC_LCLCTRL_GPIO_OE1 |
2135                                          GRC_LCLCTRL_GPIO_OE2 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2137                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2138                         if (no_gpio2) {
2139                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2140                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2141                         }
2142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2143                                                     grc_local_ctrl, 100);
2144
2145                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2146
2147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2148                                                     grc_local_ctrl, 100);
2149
2150                         if (!no_gpio2) {
2151                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2152                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2153                                             grc_local_ctrl, 100);
2154                         }
2155                 }
2156         } else {
2157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2158                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2159                         if (tp_peer != tp &&
2160                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2161                                 return;
2162
2163                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2164                                     (GRC_LCLCTRL_GPIO_OE1 |
2165                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2166
2167                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2168                                     GRC_LCLCTRL_GPIO_OE1, 100);
2169
2170                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2171                                     (GRC_LCLCTRL_GPIO_OE1 |
2172                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2173                 }
2174         }
2175 }
2176
2177 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2178 {
2179         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2180                 return 1;
2181         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2182                 if (speed != SPEED_10)
2183                         return 1;
2184         } else if (speed == SPEED_10)
2185                 return 1;
2186
2187         return 0;
2188 }
2189
2190 static int tg3_setup_phy(struct tg3 *, int);
2191
2192 #define RESET_KIND_SHUTDOWN     0
2193 #define RESET_KIND_INIT         1
2194 #define RESET_KIND_SUSPEND      2
2195
2196 static void tg3_write_sig_post_reset(struct tg3 *, int);
2197 static int tg3_halt_cpu(struct tg3 *, u32);
2198
2199 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2200 {
2201         u32 val;
2202
2203         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2205                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2206                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2207
2208                         sg_dig_ctrl |=
2209                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2210                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2211                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2212                 }
2213                 return;
2214         }
2215
2216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2217                 tg3_bmcr_reset(tp);
2218                 val = tr32(GRC_MISC_CFG);
2219                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2220                 udelay(40);
2221                 return;
2222         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2223                 u32 phytest;
2224                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2225                         u32 phy;
2226
2227                         tg3_writephy(tp, MII_ADVERTISE, 0);
2228                         tg3_writephy(tp, MII_BMCR,
2229                                      BMCR_ANENABLE | BMCR_ANRESTART);
2230
2231                         tg3_writephy(tp, MII_TG3_FET_TEST,
2232                                      phytest | MII_TG3_FET_SHADOW_EN);
2233                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2234                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2235                                 tg3_writephy(tp,
2236                                              MII_TG3_FET_SHDW_AUXMODE4,
2237                                              phy);
2238                         }
2239                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2240                 }
2241                 return;
2242         } else if (do_low_power) {
2243                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2244                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2245
2246                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2247                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2248                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2249                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2250                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2251         }
2252
2253         /* The PHY should not be powered down on some chips because
2254          * of bugs.
2255          */
2256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2258             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2259              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2260                 return;
2261
2262         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2263             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2264                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2265                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2266                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2267                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2268         }
2269
2270         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2271 }
2272
2273 /* tp->lock is held. */
2274 static int tg3_nvram_lock(struct tg3 *tp)
2275 {
2276         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2277                 int i;
2278
2279                 if (tp->nvram_lock_cnt == 0) {
2280                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2281                         for (i = 0; i < 8000; i++) {
2282                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2283                                         break;
2284                                 udelay(20);
2285                         }
2286                         if (i == 8000) {
2287                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2288                                 return -ENODEV;
2289                         }
2290                 }
2291                 tp->nvram_lock_cnt++;
2292         }
2293         return 0;
2294 }
2295
2296 /* tp->lock is held. */
2297 static void tg3_nvram_unlock(struct tg3 *tp)
2298 {
2299         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2300                 if (tp->nvram_lock_cnt > 0)
2301                         tp->nvram_lock_cnt--;
2302                 if (tp->nvram_lock_cnt == 0)
2303                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2304         }
2305 }
2306
2307 /* tp->lock is held. */
2308 static void tg3_enable_nvram_access(struct tg3 *tp)
2309 {
2310         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2311             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2312                 u32 nvaccess = tr32(NVRAM_ACCESS);
2313
2314                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2315         }
2316 }
2317
2318 /* tp->lock is held. */
2319 static void tg3_disable_nvram_access(struct tg3 *tp)
2320 {
2321         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2322             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2323                 u32 nvaccess = tr32(NVRAM_ACCESS);
2324
2325                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2326         }
2327 }
2328
2329 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2330                                         u32 offset, u32 *val)
2331 {
2332         u32 tmp;
2333         int i;
2334
2335         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2336                 return -EINVAL;
2337
2338         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2339                                         EEPROM_ADDR_DEVID_MASK |
2340                                         EEPROM_ADDR_READ);
2341         tw32(GRC_EEPROM_ADDR,
2342              tmp |
2343              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2344              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2345               EEPROM_ADDR_ADDR_MASK) |
2346              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2347
2348         for (i = 0; i < 1000; i++) {
2349                 tmp = tr32(GRC_EEPROM_ADDR);
2350
2351                 if (tmp & EEPROM_ADDR_COMPLETE)
2352                         break;
2353                 msleep(1);
2354         }
2355         if (!(tmp & EEPROM_ADDR_COMPLETE))
2356                 return -EBUSY;
2357
2358         tmp = tr32(GRC_EEPROM_DATA);
2359
2360         /*
2361          * The data will always be opposite the native endian
2362          * format.  Perform a blind byteswap to compensate.
2363          */
2364         *val = swab32(tmp);
2365
2366         return 0;
2367 }
2368
2369 #define NVRAM_CMD_TIMEOUT 10000
2370
2371 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2372 {
2373         int i;
2374
2375         tw32(NVRAM_CMD, nvram_cmd);
2376         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2377                 udelay(10);
2378                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2379                         udelay(10);
2380                         break;
2381                 }
2382         }
2383
2384         if (i == NVRAM_CMD_TIMEOUT)
2385                 return -EBUSY;
2386
2387         return 0;
2388 }
2389
2390 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2391 {
2392         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2393             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2394             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2395            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2396             (tp->nvram_jedecnum == JEDEC_ATMEL))
2397
2398                 addr = ((addr / tp->nvram_pagesize) <<
2399                         ATMEL_AT45DB0X1B_PAGE_POS) +
2400                        (addr % tp->nvram_pagesize);
2401
2402         return addr;
2403 }
2404
2405 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2406 {
2407         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2408             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2409             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2410            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2411             (tp->nvram_jedecnum == JEDEC_ATMEL))
2412
2413                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2414                         tp->nvram_pagesize) +
2415                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2416
2417         return addr;
2418 }
2419
2420 /* NOTE: Data read in from NVRAM is byteswapped according to
2421  * the byteswapping settings for all other register accesses.
2422  * tg3 devices are BE devices, so on a BE machine, the data
2423  * returned will be exactly as it is seen in NVRAM.  On a LE
2424  * machine, the 32-bit value will be byteswapped.
2425  */
2426 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2427 {
2428         int ret;
2429
2430         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2431                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2432
2433         offset = tg3_nvram_phys_addr(tp, offset);
2434
2435         if (offset > NVRAM_ADDR_MSK)
2436                 return -EINVAL;
2437
2438         ret = tg3_nvram_lock(tp);
2439         if (ret)
2440                 return ret;
2441
2442         tg3_enable_nvram_access(tp);
2443
2444         tw32(NVRAM_ADDR, offset);
2445         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2446                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2447
2448         if (ret == 0)
2449                 *val = tr32(NVRAM_RDDATA);
2450
2451         tg3_disable_nvram_access(tp);
2452
2453         tg3_nvram_unlock(tp);
2454
2455         return ret;
2456 }
2457
2458 /* Ensures NVRAM data is in bytestream format. */
2459 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2460 {
2461         u32 v;
2462         int res = tg3_nvram_read(tp, offset, &v);
2463         if (!res)
2464                 *val = cpu_to_be32(v);
2465         return res;
2466 }
2467
2468 /* tp->lock is held. */
2469 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2470 {
2471         u32 addr_high, addr_low;
2472         int i;
2473
2474         addr_high = ((tp->dev->dev_addr[0] << 8) |
2475                      tp->dev->dev_addr[1]);
2476         addr_low = ((tp->dev->dev_addr[2] << 24) |
2477                     (tp->dev->dev_addr[3] << 16) |
2478                     (tp->dev->dev_addr[4] <<  8) |
2479                     (tp->dev->dev_addr[5] <<  0));
2480         for (i = 0; i < 4; i++) {
2481                 if (i == 1 && skip_mac_1)
2482                         continue;
2483                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2484                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2485         }
2486
2487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2489                 for (i = 0; i < 12; i++) {
2490                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2491                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2492                 }
2493         }
2494
2495         addr_high = (tp->dev->dev_addr[0] +
2496                      tp->dev->dev_addr[1] +
2497                      tp->dev->dev_addr[2] +
2498                      tp->dev->dev_addr[3] +
2499                      tp->dev->dev_addr[4] +
2500                      tp->dev->dev_addr[5]) &
2501                 TX_BACKOFF_SEED_MASK;
2502         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2503 }
2504
2505 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2506 {
2507         u32 misc_host_ctrl;
2508         bool device_should_wake, do_low_power;
2509
2510         /* Make sure register accesses (indirect or otherwise)
2511          * will function correctly.
2512          */
2513         pci_write_config_dword(tp->pdev,
2514                                TG3PCI_MISC_HOST_CTRL,
2515                                tp->misc_host_ctrl);
2516
2517         switch (state) {
2518         case PCI_D0:
2519                 pci_enable_wake(tp->pdev, state, false);
2520                 pci_set_power_state(tp->pdev, PCI_D0);
2521
2522                 /* Switch out of Vaux if it is a NIC */
2523                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2524                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2525
2526                 return 0;
2527
2528         case PCI_D1:
2529         case PCI_D2:
2530         case PCI_D3hot:
2531                 break;
2532
2533         default:
2534                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2535                            state);
2536                 return -EINVAL;
2537         }
2538
2539         /* Restore the CLKREQ setting. */
2540         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2541                 u16 lnkctl;
2542
2543                 pci_read_config_word(tp->pdev,
2544                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2545                                      &lnkctl);
2546                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2547                 pci_write_config_word(tp->pdev,
2548                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2549                                       lnkctl);
2550         }
2551
2552         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2553         tw32(TG3PCI_MISC_HOST_CTRL,
2554              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2555
2556         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2557                              device_may_wakeup(&tp->pdev->dev) &&
2558                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2559
2560         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2561                 do_low_power = false;
2562                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2563                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2564                         struct phy_device *phydev;
2565                         u32 phyid, advertising;
2566
2567                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2568
2569                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2570
2571                         tp->link_config.orig_speed = phydev->speed;
2572                         tp->link_config.orig_duplex = phydev->duplex;
2573                         tp->link_config.orig_autoneg = phydev->autoneg;
2574                         tp->link_config.orig_advertising = phydev->advertising;
2575
2576                         advertising = ADVERTISED_TP |
2577                                       ADVERTISED_Pause |
2578                                       ADVERTISED_Autoneg |
2579                                       ADVERTISED_10baseT_Half;
2580
2581                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2582                             device_should_wake) {
2583                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2584                                         advertising |=
2585                                                 ADVERTISED_100baseT_Half |
2586                                                 ADVERTISED_100baseT_Full |
2587                                                 ADVERTISED_10baseT_Full;
2588                                 else
2589                                         advertising |= ADVERTISED_10baseT_Full;
2590                         }
2591
2592                         phydev->advertising = advertising;
2593
2594                         phy_start_aneg(phydev);
2595
2596                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2597                         if (phyid != PHY_ID_BCMAC131) {
2598                                 phyid &= PHY_BCM_OUI_MASK;
2599                                 if (phyid == PHY_BCM_OUI_1 ||
2600                                     phyid == PHY_BCM_OUI_2 ||
2601                                     phyid == PHY_BCM_OUI_3)
2602                                         do_low_power = true;
2603                         }
2604                 }
2605         } else {
2606                 do_low_power = true;
2607
2608                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2609                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2610                         tp->link_config.orig_speed = tp->link_config.speed;
2611                         tp->link_config.orig_duplex = tp->link_config.duplex;
2612                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2613                 }
2614
2615                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2616                         tp->link_config.speed = SPEED_10;
2617                         tp->link_config.duplex = DUPLEX_HALF;
2618                         tp->link_config.autoneg = AUTONEG_ENABLE;
2619                         tg3_setup_phy(tp, 0);
2620                 }
2621         }
2622
2623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2624                 u32 val;
2625
2626                 val = tr32(GRC_VCPU_EXT_CTRL);
2627                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2628         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2629                 int i;
2630                 u32 val;
2631
2632                 for (i = 0; i < 200; i++) {
2633                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2634                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2635                                 break;
2636                         msleep(1);
2637                 }
2638         }
2639         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2640                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2641                                                      WOL_DRV_STATE_SHUTDOWN |
2642                                                      WOL_DRV_WOL |
2643                                                      WOL_SET_MAGIC_PKT);
2644
2645         if (device_should_wake) {
2646                 u32 mac_mode;
2647
2648                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2649                         if (do_low_power) {
2650                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2651                                 udelay(40);
2652                         }
2653
2654                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2655                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2656                         else
2657                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2658
2659                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2660                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2661                             ASIC_REV_5700) {
2662                                 u32 speed = (tp->tg3_flags &
2663                                              TG3_FLAG_WOL_SPEED_100MB) ?
2664                                              SPEED_100 : SPEED_10;
2665                                 if (tg3_5700_link_polarity(tp, speed))
2666                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2667                                 else
2668                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2669                         }
2670                 } else {
2671                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2672                 }
2673
2674                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2675                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2676
2677                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2678                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2679                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2680                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2681                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2682                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2683
2684                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2685                         mac_mode |= tp->mac_mode &
2686                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2687                         if (mac_mode & MAC_MODE_APE_TX_EN)
2688                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2689                 }
2690
2691                 tw32_f(MAC_MODE, mac_mode);
2692                 udelay(100);
2693
2694                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2695                 udelay(10);
2696         }
2697
2698         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2699             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2700              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2701                 u32 base_val;
2702
2703                 base_val = tp->pci_clock_ctrl;
2704                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2705                              CLOCK_CTRL_TXCLK_DISABLE);
2706
2707                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2708                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2709         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2710                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2711                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2712                 /* do nothing */
2713         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2714                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2715                 u32 newbits1, newbits2;
2716
2717                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2718                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2719                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2720                                     CLOCK_CTRL_TXCLK_DISABLE |
2721                                     CLOCK_CTRL_ALTCLK);
2722                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2723                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2724                         newbits1 = CLOCK_CTRL_625_CORE;
2725                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2726                 } else {
2727                         newbits1 = CLOCK_CTRL_ALTCLK;
2728                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2729                 }
2730
2731                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2732                             40);
2733
2734                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2735                             40);
2736
2737                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2738                         u32 newbits3;
2739
2740                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2741                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2742                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2743                                             CLOCK_CTRL_TXCLK_DISABLE |
2744                                             CLOCK_CTRL_44MHZ_CORE);
2745                         } else {
2746                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2747                         }
2748
2749                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2750                                     tp->pci_clock_ctrl | newbits3, 40);
2751                 }
2752         }
2753
2754         if (!(device_should_wake) &&
2755             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2756                 tg3_power_down_phy(tp, do_low_power);
2757
2758         tg3_frob_aux_power(tp);
2759
2760         /* Workaround for unstable PLL clock */
2761         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2762             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2763                 u32 val = tr32(0x7d00);
2764
2765                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2766                 tw32(0x7d00, val);
2767                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2768                         int err;
2769
2770                         err = tg3_nvram_lock(tp);
2771                         tg3_halt_cpu(tp, RX_CPU_BASE);
2772                         if (!err)
2773                                 tg3_nvram_unlock(tp);
2774                 }
2775         }
2776
2777         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2778
2779         if (device_should_wake)
2780                 pci_enable_wake(tp->pdev, state, true);
2781
2782         /* Finally, set the new power state. */
2783         pci_set_power_state(tp->pdev, state);
2784
2785         return 0;
2786 }
2787
2788 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2789 {
2790         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2791         case MII_TG3_AUX_STAT_10HALF:
2792                 *speed = SPEED_10;
2793                 *duplex = DUPLEX_HALF;
2794                 break;
2795
2796         case MII_TG3_AUX_STAT_10FULL:
2797                 *speed = SPEED_10;
2798                 *duplex = DUPLEX_FULL;
2799                 break;
2800
2801         case MII_TG3_AUX_STAT_100HALF:
2802                 *speed = SPEED_100;
2803                 *duplex = DUPLEX_HALF;
2804                 break;
2805
2806         case MII_TG3_AUX_STAT_100FULL:
2807                 *speed = SPEED_100;
2808                 *duplex = DUPLEX_FULL;
2809                 break;
2810
2811         case MII_TG3_AUX_STAT_1000HALF:
2812                 *speed = SPEED_1000;
2813                 *duplex = DUPLEX_HALF;
2814                 break;
2815
2816         case MII_TG3_AUX_STAT_1000FULL:
2817                 *speed = SPEED_1000;
2818                 *duplex = DUPLEX_FULL;
2819                 break;
2820
2821         default:
2822                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2823                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2824                                  SPEED_10;
2825                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2826                                   DUPLEX_HALF;
2827                         break;
2828                 }
2829                 *speed = SPEED_INVALID;
2830                 *duplex = DUPLEX_INVALID;
2831                 break;
2832         }
2833 }
2834
2835 static void tg3_phy_copper_begin(struct tg3 *tp)
2836 {
2837         u32 new_adv;
2838         int i;
2839
2840         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2841                 /* Entering low power mode.  Disable gigabit and
2842                  * 100baseT advertisements.
2843                  */
2844                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845
2846                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2847                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2848                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2849                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2850
2851                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852         } else if (tp->link_config.speed == SPEED_INVALID) {
2853                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2854                         tp->link_config.advertising &=
2855                                 ~(ADVERTISED_1000baseT_Half |
2856                                   ADVERTISED_1000baseT_Full);
2857
2858                 new_adv = ADVERTISE_CSMA;
2859                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2860                         new_adv |= ADVERTISE_10HALF;
2861                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2862                         new_adv |= ADVERTISE_10FULL;
2863                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2864                         new_adv |= ADVERTISE_100HALF;
2865                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2866                         new_adv |= ADVERTISE_100FULL;
2867
2868                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2869
2870                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871
2872                 if (tp->link_config.advertising &
2873                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2874                         new_adv = 0;
2875                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2876                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2877                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2878                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2879                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2880                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2881                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2882                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2883                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2884                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2885                 } else {
2886                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2887                 }
2888         } else {
2889                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2890                 new_adv |= ADVERTISE_CSMA;
2891
2892                 /* Asking for a specific link mode. */
2893                 if (tp->link_config.speed == SPEED_1000) {
2894                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2895
2896                         if (tp->link_config.duplex == DUPLEX_FULL)
2897                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2898                         else
2899                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2900                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2901                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2902                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2903                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2904                 } else {
2905                         if (tp->link_config.speed == SPEED_100) {
2906                                 if (tp->link_config.duplex == DUPLEX_FULL)
2907                                         new_adv |= ADVERTISE_100FULL;
2908                                 else
2909                                         new_adv |= ADVERTISE_100HALF;
2910                         } else {
2911                                 if (tp->link_config.duplex == DUPLEX_FULL)
2912                                         new_adv |= ADVERTISE_10FULL;
2913                                 else
2914                                         new_adv |= ADVERTISE_10HALF;
2915                         }
2916                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2917
2918                         new_adv = 0;
2919                 }
2920
2921                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2922         }
2923
2924         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2925             tp->link_config.speed != SPEED_INVALID) {
2926                 u32 bmcr, orig_bmcr;
2927
2928                 tp->link_config.active_speed = tp->link_config.speed;
2929                 tp->link_config.active_duplex = tp->link_config.duplex;
2930
2931                 bmcr = 0;
2932                 switch (tp->link_config.speed) {
2933                 default:
2934                 case SPEED_10:
2935                         break;
2936
2937                 case SPEED_100:
2938                         bmcr |= BMCR_SPEED100;
2939                         break;
2940
2941                 case SPEED_1000:
2942                         bmcr |= TG3_BMCR_SPEED1000;
2943                         break;
2944                 }
2945
2946                 if (tp->link_config.duplex == DUPLEX_FULL)
2947                         bmcr |= BMCR_FULLDPLX;
2948
2949                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2950                     (bmcr != orig_bmcr)) {
2951                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2952                         for (i = 0; i < 1500; i++) {
2953                                 u32 tmp;
2954
2955                                 udelay(10);
2956                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2957                                     tg3_readphy(tp, MII_BMSR, &tmp))
2958                                         continue;
2959                                 if (!(tmp & BMSR_LSTATUS)) {
2960                                         udelay(40);
2961                                         break;
2962                                 }
2963                         }
2964                         tg3_writephy(tp, MII_BMCR, bmcr);
2965                         udelay(40);
2966                 }
2967         } else {
2968                 tg3_writephy(tp, MII_BMCR,
2969                              BMCR_ANENABLE | BMCR_ANRESTART);
2970         }
2971 }
2972
2973 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2974 {
2975         int err;
2976
2977         /* Turn off tap power management. */
2978         /* Set Extended packet length bit */
2979         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2980
2981         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2982         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2983         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2984         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2985         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2986
2987         udelay(40);
2988
2989         return err;
2990 }
2991
2992 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2993 {
2994         u32 adv_reg, all_mask = 0;
2995
2996         if (mask & ADVERTISED_10baseT_Half)
2997                 all_mask |= ADVERTISE_10HALF;
2998         if (mask & ADVERTISED_10baseT_Full)
2999                 all_mask |= ADVERTISE_10FULL;
3000         if (mask & ADVERTISED_100baseT_Half)
3001                 all_mask |= ADVERTISE_100HALF;
3002         if (mask & ADVERTISED_100baseT_Full)
3003                 all_mask |= ADVERTISE_100FULL;
3004
3005         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3006                 return 0;
3007
3008         if ((adv_reg & all_mask) != all_mask)
3009                 return 0;
3010         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3011                 u32 tg3_ctrl;
3012
3013                 all_mask = 0;
3014                 if (mask & ADVERTISED_1000baseT_Half)
3015                         all_mask |= ADVERTISE_1000HALF;
3016                 if (mask & ADVERTISED_1000baseT_Full)
3017                         all_mask |= ADVERTISE_1000FULL;
3018
3019                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3020                         return 0;
3021
3022                 if ((tg3_ctrl & all_mask) != all_mask)
3023                         return 0;
3024         }
3025         return 1;
3026 }
3027
3028 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3029 {
3030         u32 curadv, reqadv;
3031
3032         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3033                 return 1;
3034
3035         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3036         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3037
3038         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3039                 if (curadv != reqadv)
3040                         return 0;
3041
3042                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3043                         tg3_readphy(tp, MII_LPA, rmtadv);
3044         } else {
3045                 /* Reprogram the advertisement register, even if it
3046                  * does not affect the current link.  If the link
3047                  * gets renegotiated in the future, we can save an
3048                  * additional renegotiation cycle by advertising
3049                  * it correctly in the first place.
3050                  */
3051                 if (curadv != reqadv) {
3052                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3053                                      ADVERTISE_PAUSE_ASYM);
3054                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3055                 }
3056         }
3057
3058         return 1;
3059 }
3060
3061 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3062 {
3063         int current_link_up;
3064         u32 bmsr, val;
3065         u32 lcl_adv, rmt_adv;
3066         u16 current_speed;
3067         u8 current_duplex;
3068         int i, err;
3069
3070         tw32(MAC_EVENT, 0);
3071
3072         tw32_f(MAC_STATUS,
3073              (MAC_STATUS_SYNC_CHANGED |
3074               MAC_STATUS_CFG_CHANGED |
3075               MAC_STATUS_MI_COMPLETION |
3076               MAC_STATUS_LNKSTATE_CHANGED));
3077         udelay(40);
3078
3079         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3080                 tw32_f(MAC_MI_MODE,
3081                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3082                 udelay(80);
3083         }
3084
3085         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3086
3087         /* Some third-party PHYs need to be reset on link going
3088          * down.
3089          */
3090         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3091              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3092              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3093             netif_carrier_ok(tp->dev)) {
3094                 tg3_readphy(tp, MII_BMSR, &bmsr);
3095                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3096                     !(bmsr & BMSR_LSTATUS))
3097                         force_reset = 1;
3098         }
3099         if (force_reset)
3100                 tg3_phy_reset(tp);
3101
3102         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3103                 tg3_readphy(tp, MII_BMSR, &bmsr);
3104                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3105                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3106                         bmsr = 0;
3107
3108                 if (!(bmsr & BMSR_LSTATUS)) {
3109                         err = tg3_init_5401phy_dsp(tp);
3110                         if (err)
3111                                 return err;
3112
3113                         tg3_readphy(tp, MII_BMSR, &bmsr);
3114                         for (i = 0; i < 1000; i++) {
3115                                 udelay(10);
3116                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3117                                     (bmsr & BMSR_LSTATUS)) {
3118                                         udelay(40);
3119                                         break;
3120                                 }
3121                         }
3122
3123                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3124                             TG3_PHY_REV_BCM5401_B0 &&
3125                             !(bmsr & BMSR_LSTATUS) &&
3126                             tp->link_config.active_speed == SPEED_1000) {
3127                                 err = tg3_phy_reset(tp);
3128                                 if (!err)
3129                                         err = tg3_init_5401phy_dsp(tp);
3130                                 if (err)
3131                                         return err;
3132                         }
3133                 }
3134         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3135                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3136                 /* 5701 {A0,B0} CRC bug workaround */
3137                 tg3_writephy(tp, 0x15, 0x0a75);
3138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3139                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3140                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3141         }
3142
3143         /* Clear pending interrupts... */
3144         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3145         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3146
3147         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3148                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3149         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3150                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3151
3152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3153             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3154                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3155                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3156                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3157                 else
3158                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3159         }
3160
3161         current_link_up = 0;
3162         current_speed = SPEED_INVALID;
3163         current_duplex = DUPLEX_INVALID;
3164
3165         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3166                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3167                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3168                 if (!(val & (1 << 10))) {
3169                         val |= (1 << 10);
3170                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3171                         goto relink;
3172                 }
3173         }
3174
3175         bmsr = 0;
3176         for (i = 0; i < 100; i++) {
3177                 tg3_readphy(tp, MII_BMSR, &bmsr);
3178                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3179                     (bmsr & BMSR_LSTATUS))
3180                         break;
3181                 udelay(40);
3182         }
3183
3184         if (bmsr & BMSR_LSTATUS) {
3185                 u32 aux_stat, bmcr;
3186
3187                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3188                 for (i = 0; i < 2000; i++) {
3189                         udelay(10);
3190                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3191                             aux_stat)
3192                                 break;
3193                 }
3194
3195                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3196                                              &current_speed,
3197                                              &current_duplex);
3198
3199                 bmcr = 0;
3200                 for (i = 0; i < 200; i++) {
3201                         tg3_readphy(tp, MII_BMCR, &bmcr);
3202                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3203                                 continue;
3204                         if (bmcr && bmcr != 0x7fff)
3205                                 break;
3206                         udelay(10);
3207                 }
3208
3209                 lcl_adv = 0;
3210                 rmt_adv = 0;
3211
3212                 tp->link_config.active_speed = current_speed;
3213                 tp->link_config.active_duplex = current_duplex;
3214
3215                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3216                         if ((bmcr & BMCR_ANENABLE) &&
3217                             tg3_copper_is_advertising_all(tp,
3218                                                 tp->link_config.advertising)) {
3219                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3220                                                                   &rmt_adv))
3221                                         current_link_up = 1;
3222                         }
3223                 } else {
3224                         if (!(bmcr & BMCR_ANENABLE) &&
3225                             tp->link_config.speed == current_speed &&
3226                             tp->link_config.duplex == current_duplex &&
3227                             tp->link_config.flowctrl ==
3228                             tp->link_config.active_flowctrl) {
3229                                 current_link_up = 1;
3230                         }
3231                 }
3232
3233                 if (current_link_up == 1 &&
3234                     tp->link_config.active_duplex == DUPLEX_FULL)
3235                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3236         }
3237
3238 relink:
3239         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3240                 tg3_phy_copper_begin(tp);
3241
3242                 tg3_readphy(tp, MII_BMSR, &bmsr);
3243                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3244                     (bmsr & BMSR_LSTATUS))
3245                         current_link_up = 1;
3246         }
3247
3248         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3249         if (current_link_up == 1) {
3250                 if (tp->link_config.active_speed == SPEED_100 ||
3251                     tp->link_config.active_speed == SPEED_10)
3252                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3253                 else
3254                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3255         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3256                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3257         else
3258                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3259
3260         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3261         if (tp->link_config.active_duplex == DUPLEX_HALF)
3262                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3263
3264         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3265                 if (current_link_up == 1 &&
3266                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3267                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3268                 else
3269                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3270         }
3271
3272         /* ??? Without this setting Netgear GA302T PHY does not
3273          * ??? send/receive packets...
3274          */
3275         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3276             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3277                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3278                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3279                 udelay(80);
3280         }
3281
3282         tw32_f(MAC_MODE, tp->mac_mode);
3283         udelay(40);
3284
3285         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3286                 /* Polled via timer. */
3287                 tw32_f(MAC_EVENT, 0);
3288         } else {
3289                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3290         }
3291         udelay(40);
3292
3293         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3294             current_link_up == 1 &&
3295             tp->link_config.active_speed == SPEED_1000 &&
3296             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3297              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3298                 udelay(120);
3299                 tw32_f(MAC_STATUS,
3300                      (MAC_STATUS_SYNC_CHANGED |
3301                       MAC_STATUS_CFG_CHANGED));
3302                 udelay(40);
3303                 tg3_write_mem(tp,
3304                               NIC_SRAM_FIRMWARE_MBOX,
3305                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3306         }
3307
3308         /* Prevent send BD corruption. */
3309         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3310                 u16 oldlnkctl, newlnkctl;
3311
3312                 pci_read_config_word(tp->pdev,
3313                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3314                                      &oldlnkctl);
3315                 if (tp->link_config.active_speed == SPEED_100 ||
3316                     tp->link_config.active_speed == SPEED_10)
3317                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3318                 else
3319                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3320                 if (newlnkctl != oldlnkctl)
3321                         pci_write_config_word(tp->pdev,
3322                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3323                                               newlnkctl);
3324         }
3325
3326         if (current_link_up != netif_carrier_ok(tp->dev)) {
3327                 if (current_link_up)
3328                         netif_carrier_on(tp->dev);
3329                 else
3330                         netif_carrier_off(tp->dev);
3331                 tg3_link_report(tp);
3332         }
3333
3334         return 0;
3335 }
3336
3337 struct tg3_fiber_aneginfo {
3338         int state;
3339 #define ANEG_STATE_UNKNOWN              0
3340 #define ANEG_STATE_AN_ENABLE            1
3341 #define ANEG_STATE_RESTART_INIT         2
3342 #define ANEG_STATE_RESTART              3
3343 #define ANEG_STATE_DISABLE_LINK_OK      4
3344 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3345 #define ANEG_STATE_ABILITY_DETECT       6
3346 #define ANEG_STATE_ACK_DETECT_INIT      7
3347 #define ANEG_STATE_ACK_DETECT           8
3348 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3349 #define ANEG_STATE_COMPLETE_ACK         10
3350 #define ANEG_STATE_IDLE_DETECT_INIT     11
3351 #define ANEG_STATE_IDLE_DETECT          12
3352 #define ANEG_STATE_LINK_OK              13
3353 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3354 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3355
3356         u32 flags;
3357 #define MR_AN_ENABLE            0x00000001
3358 #define MR_RESTART_AN           0x00000002
3359 #define MR_AN_COMPLETE          0x00000004
3360 #define MR_PAGE_RX              0x00000008
3361 #define MR_NP_LOADED            0x00000010
3362 #define MR_TOGGLE_TX            0x00000020
3363 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3364 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3365 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3366 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3367 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3368 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3369 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3370 #define MR_TOGGLE_RX            0x00002000
3371 #define MR_NP_RX                0x00004000
3372
3373 #define MR_LINK_OK              0x80000000
3374
3375         unsigned long link_time, cur_time;
3376
3377         u32 ability_match_cfg;
3378         int ability_match_count;
3379
3380         char ability_match, idle_match, ack_match;
3381
3382         u32 txconfig, rxconfig;
3383 #define ANEG_CFG_NP             0x00000080
3384 #define ANEG_CFG_ACK            0x00000040
3385 #define ANEG_CFG_RF2            0x00000020
3386 #define ANEG_CFG_RF1            0x00000010
3387 #define ANEG_CFG_PS2            0x00000001
3388 #define ANEG_CFG_PS1            0x00008000
3389 #define ANEG_CFG_HD             0x00004000
3390 #define ANEG_CFG_FD             0x00002000
3391 #define ANEG_CFG_INVAL          0x00001f06
3392
3393 };
3394 #define ANEG_OK         0
3395 #define ANEG_DONE       1
3396 #define ANEG_TIMER_ENAB 2
3397 #define ANEG_FAILED     -1
3398
3399 #define ANEG_STATE_SETTLE_TIME  10000
3400
3401 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3402                                    struct tg3_fiber_aneginfo *ap)
3403 {
3404         u16 flowctrl;
3405         unsigned long delta;
3406         u32 rx_cfg_reg;
3407         int ret;
3408
3409         if (ap->state == ANEG_STATE_UNKNOWN) {
3410                 ap->rxconfig = 0;
3411                 ap->link_time = 0;
3412                 ap->cur_time = 0;
3413                 ap->ability_match_cfg = 0;
3414                 ap->ability_match_count = 0;
3415                 ap->ability_match = 0;
3416                 ap->idle_match = 0;
3417                 ap->ack_match = 0;
3418         }
3419         ap->cur_time++;
3420
3421         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3422                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3423
3424                 if (rx_cfg_reg != ap->ability_match_cfg) {
3425                         ap->ability_match_cfg = rx_cfg_reg;
3426                         ap->ability_match = 0;
3427                         ap->ability_match_count = 0;
3428                 } else {
3429                         if (++ap->ability_match_count > 1) {
3430                                 ap->ability_match = 1;
3431                                 ap->ability_match_cfg = rx_cfg_reg;
3432                         }
3433                 }
3434                 if (rx_cfg_reg & ANEG_CFG_ACK)
3435                         ap->ack_match = 1;
3436                 else
3437                         ap->ack_match = 0;
3438
3439                 ap->idle_match = 0;
3440         } else {
3441                 ap->idle_match = 1;
3442                 ap->ability_match_cfg = 0;
3443                 ap->ability_match_count = 0;
3444                 ap->ability_match = 0;
3445                 ap->ack_match = 0;
3446
3447                 rx_cfg_reg = 0;
3448         }
3449
3450         ap->rxconfig = rx_cfg_reg;
3451         ret = ANEG_OK;
3452
3453         switch (ap->state) {
3454         case ANEG_STATE_UNKNOWN:
3455                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3456                         ap->state = ANEG_STATE_AN_ENABLE;
3457
3458                 /* fallthru */
3459         case ANEG_STATE_AN_ENABLE:
3460                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3461                 if (ap->flags & MR_AN_ENABLE) {
3462                         ap->link_time = 0;
3463                         ap->cur_time = 0;
3464                         ap->ability_match_cfg = 0;
3465                         ap->ability_match_count = 0;
3466                         ap->ability_match = 0;
3467                         ap->idle_match = 0;
3468                         ap->ack_match = 0;
3469
3470                         ap->state = ANEG_STATE_RESTART_INIT;
3471                 } else {
3472                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3473                 }
3474                 break;
3475
3476         case ANEG_STATE_RESTART_INIT:
3477                 ap->link_time = ap->cur_time;
3478                 ap->flags &= ~(MR_NP_LOADED);
3479                 ap->txconfig = 0;
3480                 tw32(MAC_TX_AUTO_NEG, 0);
3481                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3482                 tw32_f(MAC_MODE, tp->mac_mode);
3483                 udelay(40);
3484
3485                 ret = ANEG_TIMER_ENAB;
3486                 ap->state = ANEG_STATE_RESTART;
3487
3488                 /* fallthru */
3489         case ANEG_STATE_RESTART:
3490                 delta = ap->cur_time - ap->link_time;
3491                 if (delta > ANEG_STATE_SETTLE_TIME)
3492                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3493                 else
3494                         ret = ANEG_TIMER_ENAB;
3495                 break;
3496
3497         case ANEG_STATE_DISABLE_LINK_OK:
3498                 ret = ANEG_DONE;
3499                 break;
3500
3501         case ANEG_STATE_ABILITY_DETECT_INIT:
3502                 ap->flags &= ~(MR_TOGGLE_TX);
3503                 ap->txconfig = ANEG_CFG_FD;
3504                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3505                 if (flowctrl & ADVERTISE_1000XPAUSE)
3506                         ap->txconfig |= ANEG_CFG_PS1;
3507                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3508                         ap->txconfig |= ANEG_CFG_PS2;
3509                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3510                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3511                 tw32_f(MAC_MODE, tp->mac_mode);
3512                 udelay(40);
3513
3514                 ap->state = ANEG_STATE_ABILITY_DETECT;
3515                 break;
3516
3517         case ANEG_STATE_ABILITY_DETECT:
3518                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3519                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3520                 break;
3521
3522         case ANEG_STATE_ACK_DETECT_INIT:
3523                 ap->txconfig |= ANEG_CFG_ACK;
3524                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3525                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3526                 tw32_f(MAC_MODE, tp->mac_mode);
3527                 udelay(40);
3528
3529                 ap->state = ANEG_STATE_ACK_DETECT;
3530
3531                 /* fallthru */
3532         case ANEG_STATE_ACK_DETECT:
3533                 if (ap->ack_match != 0) {
3534                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3535                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3536                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3537                         } else {
3538                                 ap->state = ANEG_STATE_AN_ENABLE;
3539                         }
3540                 } else if (ap->ability_match != 0 &&
3541                            ap->rxconfig == 0) {
3542                         ap->state = ANEG_STATE_AN_ENABLE;
3543                 }
3544                 break;
3545
3546         case ANEG_STATE_COMPLETE_ACK_INIT:
3547                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3548                         ret = ANEG_FAILED;
3549                         break;
3550                 }
3551                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3552                                MR_LP_ADV_HALF_DUPLEX |
3553                                MR_LP_ADV_SYM_PAUSE |
3554                                MR_LP_ADV_ASYM_PAUSE |
3555                                MR_LP_ADV_REMOTE_FAULT1 |
3556                                MR_LP_ADV_REMOTE_FAULT2 |
3557                                MR_LP_ADV_NEXT_PAGE |
3558                                MR_TOGGLE_RX |
3559                                MR_NP_RX);
3560                 if (ap->rxconfig & ANEG_CFG_FD)
3561                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3562                 if (ap->rxconfig & ANEG_CFG_HD)
3563                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3564                 if (ap->rxconfig & ANEG_CFG_PS1)
3565                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3566                 if (ap->rxconfig & ANEG_CFG_PS2)
3567                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3568                 if (ap->rxconfig & ANEG_CFG_RF1)
3569                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3570                 if (ap->rxconfig & ANEG_CFG_RF2)
3571                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3572                 if (ap->rxconfig & ANEG_CFG_NP)
3573                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3574
3575                 ap->link_time = ap->cur_time;
3576
3577                 ap->flags ^= (MR_TOGGLE_TX);
3578                 if (ap->rxconfig & 0x0008)
3579                         ap->flags |= MR_TOGGLE_RX;
3580                 if (ap->rxconfig & ANEG_CFG_NP)
3581                         ap->flags |= MR_NP_RX;
3582                 ap->flags |= MR_PAGE_RX;
3583
3584                 ap->state = ANEG_STATE_COMPLETE_ACK;
3585                 ret = ANEG_TIMER_ENAB;
3586                 break;
3587
3588         case ANEG_STATE_COMPLETE_ACK:
3589                 if (ap->ability_match != 0 &&
3590                     ap->rxconfig == 0) {
3591                         ap->state = ANEG_STATE_AN_ENABLE;
3592                         break;
3593                 }
3594                 delta = ap->cur_time - ap->link_time;
3595                 if (delta > ANEG_STATE_SETTLE_TIME) {
3596                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3597                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3598                         } else {
3599                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3600                                     !(ap->flags & MR_NP_RX)) {
3601                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3602                                 } else {
3603                                         ret = ANEG_FAILED;
3604                                 }
3605                         }
3606                 }
3607                 break;
3608
3609         case ANEG_STATE_IDLE_DETECT_INIT:
3610                 ap->link_time = ap->cur_time;
3611                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3612                 tw32_f(MAC_MODE, tp->mac_mode);
3613                 udelay(40);
3614
3615                 ap->state = ANEG_STATE_IDLE_DETECT;
3616                 ret = ANEG_TIMER_ENAB;
3617                 break;
3618
3619         case ANEG_STATE_IDLE_DETECT:
3620                 if (ap->ability_match != 0 &&
3621                     ap->rxconfig == 0) {
3622                         ap->state = ANEG_STATE_AN_ENABLE;
3623                         break;
3624                 }
3625                 delta = ap->cur_time - ap->link_time;
3626                 if (delta > ANEG_STATE_SETTLE_TIME) {
3627                         /* XXX another gem from the Broadcom driver :( */
3628                         ap->state = ANEG_STATE_LINK_OK;
3629                 }
3630                 break;
3631
3632         case ANEG_STATE_LINK_OK:
3633                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3634                 ret = ANEG_DONE;
3635                 break;
3636
3637         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3638                 /* ??? unimplemented */
3639                 break;
3640
3641         case ANEG_STATE_NEXT_PAGE_WAIT:
3642                 /* ??? unimplemented */
3643                 break;
3644
3645         default:
3646                 ret = ANEG_FAILED;
3647                 break;
3648         }
3649
3650         return ret;
3651 }
3652
3653 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3654 {
3655         int res = 0;
3656         struct tg3_fiber_aneginfo aninfo;
3657         int status = ANEG_FAILED;
3658         unsigned int tick;
3659         u32 tmp;
3660
3661         tw32_f(MAC_TX_AUTO_NEG, 0);
3662
3663         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3664         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3665         udelay(40);
3666
3667         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3668         udelay(40);
3669
3670         memset(&aninfo, 0, sizeof(aninfo));
3671         aninfo.flags |= MR_AN_ENABLE;
3672         aninfo.state = ANEG_STATE_UNKNOWN;
3673         aninfo.cur_time = 0;
3674         tick = 0;
3675         while (++tick < 195000) {
3676                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3677                 if (status == ANEG_DONE || status == ANEG_FAILED)
3678                         break;
3679
3680                 udelay(1);
3681         }
3682
3683         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3684         tw32_f(MAC_MODE, tp->mac_mode);
3685         udelay(40);
3686
3687         *txflags = aninfo.txconfig;
3688         *rxflags = aninfo.flags;
3689
3690         if (status == ANEG_DONE &&
3691             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3692                              MR_LP_ADV_FULL_DUPLEX)))
3693                 res = 1;
3694
3695         return res;
3696 }
3697
3698 static void tg3_init_bcm8002(struct tg3 *tp)
3699 {
3700         u32 mac_status = tr32(MAC_STATUS);
3701         int i;
3702
3703         /* Reset when initting first time or we have a link. */
3704         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3705             !(mac_status & MAC_STATUS_PCS_SYNCED))
3706                 return;
3707
3708         /* Set PLL lock range. */
3709         tg3_writephy(tp, 0x16, 0x8007);
3710
3711         /* SW reset */
3712         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3713
3714         /* Wait for reset to complete. */
3715         /* XXX schedule_timeout() ... */
3716         for (i = 0; i < 500; i++)
3717                 udelay(10);
3718
3719         /* Config mode; select PMA/Ch 1 regs. */
3720         tg3_writephy(tp, 0x10, 0x8411);
3721
3722         /* Enable auto-lock and comdet, select txclk for tx. */
3723         tg3_writephy(tp, 0x11, 0x0a10);
3724
3725         tg3_writephy(tp, 0x18, 0x00a0);
3726         tg3_writephy(tp, 0x16, 0x41ff);
3727
3728         /* Assert and deassert POR. */
3729         tg3_writephy(tp, 0x13, 0x0400);
3730         udelay(40);
3731         tg3_writephy(tp, 0x13, 0x0000);
3732
3733         tg3_writephy(tp, 0x11, 0x0a50);
3734         udelay(40);
3735         tg3_writephy(tp, 0x11, 0x0a10);
3736
3737         /* Wait for signal to stabilize */
3738         /* XXX schedule_timeout() ... */
3739         for (i = 0; i < 15000; i++)
3740                 udelay(10);
3741
3742         /* Deselect the channel register so we can read the PHYID
3743          * later.
3744          */
3745         tg3_writephy(tp, 0x10, 0x8011);
3746 }
3747
3748 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3749 {
3750         u16 flowctrl;
3751         u32 sg_dig_ctrl, sg_dig_status;
3752         u32 serdes_cfg, expected_sg_dig_ctrl;
3753         int workaround, port_a;
3754         int current_link_up;
3755
3756         serdes_cfg = 0;
3757         expected_sg_dig_ctrl = 0;
3758         workaround = 0;
3759         port_a = 1;
3760         current_link_up = 0;
3761
3762         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3763             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3764                 workaround = 1;
3765                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3766                         port_a = 0;
3767
3768                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3769                 /* preserve bits 20-23 for voltage regulator */
3770                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3771         }
3772
3773         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3774
3775         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3776                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3777                         if (workaround) {
3778                                 u32 val = serdes_cfg;
3779
3780                                 if (port_a)
3781                                         val |= 0xc010000;
3782                                 else
3783                                         val |= 0x4010000;
3784                                 tw32_f(MAC_SERDES_CFG, val);
3785                         }
3786
3787                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3788                 }
3789                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3790                         tg3_setup_flow_control(tp, 0, 0);
3791                         current_link_up = 1;
3792                 }
3793                 goto out;
3794         }
3795
3796         /* Want auto-negotiation.  */
3797         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3798
3799         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3800         if (flowctrl & ADVERTISE_1000XPAUSE)
3801                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3802         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3803                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3804
3805         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3806                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3807                     tp->serdes_counter &&
3808                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3809                                     MAC_STATUS_RCVD_CFG)) ==
3810                      MAC_STATUS_PCS_SYNCED)) {
3811                         tp->serdes_counter--;
3812                         current_link_up = 1;
3813                         goto out;
3814                 }
3815 restart_autoneg:
3816                 if (workaround)
3817                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3818                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3819                 udelay(5);
3820                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3821
3822                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3823                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3824         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3825                                  MAC_STATUS_SIGNAL_DET)) {
3826                 sg_dig_status = tr32(SG_DIG_STATUS);
3827                 mac_status = tr32(MAC_STATUS);
3828
3829                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3830                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3831                         u32 local_adv = 0, remote_adv = 0;
3832
3833                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3834                                 local_adv |= ADVERTISE_1000XPAUSE;
3835                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3836                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3837
3838                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3839                                 remote_adv |= LPA_1000XPAUSE;
3840                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3841                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3842
3843                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3844                         current_link_up = 1;
3845                         tp->serdes_counter = 0;
3846                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3847                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3848                         if (tp->serdes_counter)
3849                                 tp->serdes_counter--;
3850                         else {
3851                                 if (workaround) {
3852                                         u32 val = serdes_cfg;
3853
3854                                         if (port_a)
3855                                                 val |= 0xc010000;
3856                                         else
3857                                                 val |= 0x4010000;
3858
3859                                         tw32_f(MAC_SERDES_CFG, val);
3860                                 }
3861
3862                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3863                                 udelay(40);
3864
3865                                 /* Link parallel detection - link is up */
3866                                 /* only if we have PCS_SYNC and not */
3867                                 /* receiving config code words */
3868                                 mac_status = tr32(MAC_STATUS);
3869                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3870                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3871                                         tg3_setup_flow_control(tp, 0, 0);
3872                                         current_link_up = 1;
3873                                         tp->phy_flags |=
3874                                                 TG3_PHYFLG_PARALLEL_DETECT;
3875                                         tp->serdes_counter =
3876                                                 SERDES_PARALLEL_DET_TIMEOUT;
3877                                 } else
3878                                         goto restart_autoneg;
3879                         }
3880                 }
3881         } else {
3882                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3883                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3884         }
3885
3886 out:
3887         return current_link_up;
3888 }
3889
3890 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3891 {
3892         int current_link_up = 0;
3893
3894         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3895                 goto out;
3896
3897         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3898                 u32 txflags, rxflags;
3899                 int i;
3900
3901                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3902                         u32 local_adv = 0, remote_adv = 0;
3903
3904                         if (txflags & ANEG_CFG_PS1)
3905                                 local_adv |= ADVERTISE_1000XPAUSE;
3906                         if (txflags & ANEG_CFG_PS2)
3907                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3908
3909                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3910                                 remote_adv |= LPA_1000XPAUSE;
3911                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3912                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3913
3914                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3915
3916                         current_link_up = 1;
3917                 }
3918                 for (i = 0; i < 30; i++) {
3919                         udelay(20);
3920                         tw32_f(MAC_STATUS,
3921                                (MAC_STATUS_SYNC_CHANGED |
3922                                 MAC_STATUS_CFG_CHANGED));
3923                         udelay(40);
3924                         if ((tr32(MAC_STATUS) &
3925                              (MAC_STATUS_SYNC_CHANGED |
3926                               MAC_STATUS_CFG_CHANGED)) == 0)
3927                                 break;
3928                 }
3929
3930                 mac_status = tr32(MAC_STATUS);
3931                 if (current_link_up == 0 &&
3932                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3933                     !(mac_status & MAC_STATUS_RCVD_CFG))
3934                         current_link_up = 1;
3935         } else {
3936                 tg3_setup_flow_control(tp, 0, 0);
3937
3938                 /* Forcing 1000FD link up. */
3939                 current_link_up = 1;
3940
3941                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3942                 udelay(40);
3943
3944                 tw32_f(MAC_MODE, tp->mac_mode);
3945                 udelay(40);
3946         }
3947
3948 out:
3949         return current_link_up;
3950 }
3951
3952 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3953 {
3954         u32 orig_pause_cfg;
3955         u16 orig_active_speed;
3956         u8 orig_active_duplex;
3957         u32 mac_status;
3958         int current_link_up;
3959         int i;
3960
3961         orig_pause_cfg = tp->link_config.active_flowctrl;
3962         orig_active_speed = tp->link_config.active_speed;
3963         orig_active_duplex = tp->link_config.active_duplex;
3964
3965         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3966             netif_carrier_ok(tp->dev) &&
3967             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3968                 mac_status = tr32(MAC_STATUS);
3969                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3970                                MAC_STATUS_SIGNAL_DET |
3971                                MAC_STATUS_CFG_CHANGED |
3972                                MAC_STATUS_RCVD_CFG);
3973                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3974                                    MAC_STATUS_SIGNAL_DET)) {
3975                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3976                                             MAC_STATUS_CFG_CHANGED));
3977                         return 0;
3978                 }
3979         }
3980
3981         tw32_f(MAC_TX_AUTO_NEG, 0);
3982
3983         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3984         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3985         tw32_f(MAC_MODE, tp->mac_mode);
3986         udelay(40);
3987
3988         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3989                 tg3_init_bcm8002(tp);
3990
3991         /* Enable link change event even when serdes polling.  */
3992         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3993         udelay(40);
3994
3995         current_link_up = 0;
3996         mac_status = tr32(MAC_STATUS);
3997
3998         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3999                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4000         else
4001                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4002
4003         tp->napi[0].hw_status->status =
4004                 (SD_STATUS_UPDATED |
4005                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4006
4007         for (i = 0; i < 100; i++) {
4008                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4009                                     MAC_STATUS_CFG_CHANGED));
4010                 udelay(5);
4011                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4012                                          MAC_STATUS_CFG_CHANGED |
4013                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4014                         break;
4015         }
4016
4017         mac_status = tr32(MAC_STATUS);
4018         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4019                 current_link_up = 0;
4020                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4021                     tp->serdes_counter == 0) {
4022                         tw32_f(MAC_MODE, (tp->mac_mode |
4023                                           MAC_MODE_SEND_CONFIGS));
4024                         udelay(1);
4025                         tw32_f(MAC_MODE, tp->mac_mode);
4026                 }
4027         }
4028
4029         if (current_link_up == 1) {
4030                 tp->link_config.active_speed = SPEED_1000;
4031                 tp->link_config.active_duplex = DUPLEX_FULL;
4032                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4033                                     LED_CTRL_LNKLED_OVERRIDE |
4034                                     LED_CTRL_1000MBPS_ON));
4035         } else {
4036                 tp->link_config.active_speed = SPEED_INVALID;
4037                 tp->link_config.active_duplex = DUPLEX_INVALID;
4038                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4039                                     LED_CTRL_LNKLED_OVERRIDE |
4040                                     LED_CTRL_TRAFFIC_OVERRIDE));
4041         }
4042
4043         if (current_link_up != netif_carrier_ok(tp->dev)) {
4044                 if (current_link_up)
4045                         netif_carrier_on(tp->dev);
4046                 else
4047                         netif_carrier_off(tp->dev);
4048                 tg3_link_report(tp);
4049         } else {
4050                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4051                 if (orig_pause_cfg != now_pause_cfg ||
4052                     orig_active_speed != tp->link_config.active_speed ||
4053                     orig_active_duplex != tp->link_config.active_duplex)
4054                         tg3_link_report(tp);
4055         }
4056
4057         return 0;
4058 }
4059
4060 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4061 {
4062         int current_link_up, err = 0;
4063         u32 bmsr, bmcr;
4064         u16 current_speed;
4065         u8 current_duplex;
4066         u32 local_adv, remote_adv;
4067
4068         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4069         tw32_f(MAC_MODE, tp->mac_mode);
4070         udelay(40);
4071
4072         tw32(MAC_EVENT, 0);
4073
4074         tw32_f(MAC_STATUS,
4075              (MAC_STATUS_SYNC_CHANGED |
4076               MAC_STATUS_CFG_CHANGED |
4077               MAC_STATUS_MI_COMPLETION |
4078               MAC_STATUS_LNKSTATE_CHANGED));
4079         udelay(40);
4080
4081         if (force_reset)
4082                 tg3_phy_reset(tp);
4083
4084         current_link_up = 0;
4085         current_speed = SPEED_INVALID;
4086         current_duplex = DUPLEX_INVALID;
4087
4088         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4089         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4090         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4091                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4092                         bmsr |= BMSR_LSTATUS;
4093                 else
4094                         bmsr &= ~BMSR_LSTATUS;
4095         }
4096
4097         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4098
4099         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4100             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4101                 /* do nothing, just check for link up at the end */
4102         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4103                 u32 adv, new_adv;
4104
4105                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4106                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4107                                   ADVERTISE_1000XPAUSE |
4108                                   ADVERTISE_1000XPSE_ASYM |
4109                                   ADVERTISE_SLCT);
4110
4111                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4112
4113                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4114                         new_adv |= ADVERTISE_1000XHALF;
4115                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4116                         new_adv |= ADVERTISE_1000XFULL;
4117
4118                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4119                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4120                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4121                         tg3_writephy(tp, MII_BMCR, bmcr);
4122
4123                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4124                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4125                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4126
4127                         return err;
4128                 }
4129         } else {
4130                 u32 new_bmcr;
4131
4132                 bmcr &= ~BMCR_SPEED1000;
4133                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4134
4135                 if (tp->link_config.duplex == DUPLEX_FULL)
4136                         new_bmcr |= BMCR_FULLDPLX;
4137
4138                 if (new_bmcr != bmcr) {
4139                         /* BMCR_SPEED1000 is a reserved bit that needs
4140                          * to be set on write.
4141                          */
4142                         new_bmcr |= BMCR_SPEED1000;
4143
4144                         /* Force a linkdown */
4145                         if (netif_carrier_ok(tp->dev)) {
4146                                 u32 adv;
4147
4148                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4149                                 adv &= ~(ADVERTISE_1000XFULL |
4150                                          ADVERTISE_1000XHALF |
4151                                          ADVERTISE_SLCT);
4152                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4153                                 tg3_writephy(tp, MII_BMCR, bmcr |
4154                                                            BMCR_ANRESTART |
4155                                                            BMCR_ANENABLE);
4156                                 udelay(10);
4157                                 netif_carrier_off(tp->dev);
4158                         }
4159                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4160                         bmcr = new_bmcr;
4161                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4162                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4163                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4164                             ASIC_REV_5714) {
4165                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4166                                         bmsr |= BMSR_LSTATUS;
4167                                 else
4168                                         bmsr &= ~BMSR_LSTATUS;
4169                         }
4170                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4171                 }
4172         }
4173
4174         if (bmsr & BMSR_LSTATUS) {
4175                 current_speed = SPEED_1000;
4176                 current_link_up = 1;
4177                 if (bmcr & BMCR_FULLDPLX)
4178                         current_duplex = DUPLEX_FULL;
4179                 else
4180                         current_duplex = DUPLEX_HALF;
4181
4182                 local_adv = 0;
4183                 remote_adv = 0;
4184
4185                 if (bmcr & BMCR_ANENABLE) {
4186                         u32 common;
4187
4188                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4189                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4190                         common = local_adv & remote_adv;
4191                         if (common & (ADVERTISE_1000XHALF |
4192                                       ADVERTISE_1000XFULL)) {
4193                                 if (common & ADVERTISE_1000XFULL)
4194                                         current_duplex = DUPLEX_FULL;
4195                                 else
4196                                         current_duplex = DUPLEX_HALF;
4197                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4198                                 /* Link is up via parallel detect */
4199                         } else {
4200                                 current_link_up = 0;
4201                         }
4202                 }
4203         }
4204
4205         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4206                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4207
4208         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4209         if (tp->link_config.active_duplex == DUPLEX_HALF)
4210                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4211
4212         tw32_f(MAC_MODE, tp->mac_mode);
4213         udelay(40);
4214
4215         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4216
4217         tp->link_config.active_speed = current_speed;
4218         tp->link_config.active_duplex = current_duplex;
4219
4220         if (current_link_up != netif_carrier_ok(tp->dev)) {
4221                 if (current_link_up)
4222                         netif_carrier_on(tp->dev);
4223                 else {
4224                         netif_carrier_off(tp->dev);
4225                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4226                 }
4227                 tg3_link_report(tp);
4228         }
4229         return err;
4230 }
4231
4232 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4233 {
4234         if (tp->serdes_counter) {
4235                 /* Give autoneg time to complete. */
4236                 tp->serdes_counter--;
4237                 return;
4238         }
4239
4240         if (!netif_carrier_ok(tp->dev) &&
4241             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4242                 u32 bmcr;
4243
4244                 tg3_readphy(tp, MII_BMCR, &bmcr);
4245                 if (bmcr & BMCR_ANENABLE) {
4246                         u32 phy1, phy2;
4247
4248                         /* Select shadow register 0x1f */
4249                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4250                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4251
4252                         /* Select expansion interrupt status register */
4253                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4254                                          MII_TG3_DSP_EXP1_INT_STAT);
4255                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4256                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4257
4258                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4259                                 /* We have signal detect and not receiving
4260                                  * config code words, link is up by parallel
4261                                  * detection.
4262                                  */
4263
4264                                 bmcr &= ~BMCR_ANENABLE;
4265                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4266                                 tg3_writephy(tp, MII_BMCR, bmcr);
4267                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4268                         }
4269                 }
4270         } else if (netif_carrier_ok(tp->dev) &&
4271                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4272                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4273                 u32 phy2;
4274
4275                 /* Select expansion interrupt status register */
4276                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4277                                  MII_TG3_DSP_EXP1_INT_STAT);
4278                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4279                 if (phy2 & 0x20) {
4280                         u32 bmcr;
4281
4282                         /* Config code words received, turn on autoneg. */
4283                         tg3_readphy(tp, MII_BMCR, &bmcr);
4284                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4285
4286                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4287
4288                 }
4289         }
4290 }
4291
4292 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4293 {
4294         int err;
4295
4296         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4297                 err = tg3_setup_fiber_phy(tp, force_reset);
4298         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4299                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4300         else
4301                 err = tg3_setup_copper_phy(tp, force_reset);
4302
4303         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4304                 u32 val, scale;
4305
4306                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4307                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4308                         scale = 65;
4309                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4310                         scale = 6;
4311                 else
4312                         scale = 12;
4313
4314                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4315                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4316                 tw32(GRC_MISC_CFG, val);
4317         }
4318
4319         if (tp->link_config.active_speed == SPEED_1000 &&
4320             tp->link_config.active_duplex == DUPLEX_HALF)
4321                 tw32(MAC_TX_LENGTHS,
4322                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4323                       (6 << TX_LENGTHS_IPG_SHIFT) |
4324                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4325         else
4326                 tw32(MAC_TX_LENGTHS,
4327                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4328                       (6 << TX_LENGTHS_IPG_SHIFT) |
4329                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4330
4331         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4332                 if (netif_carrier_ok(tp->dev)) {
4333                         tw32(HOSTCC_STAT_COAL_TICKS,
4334                              tp->coal.stats_block_coalesce_usecs);
4335                 } else {
4336                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4337                 }
4338         }
4339
4340         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4341                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4342                 if (!netif_carrier_ok(tp->dev))
4343                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4344                               tp->pwrmgmt_thresh;
4345                 else
4346                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4347                 tw32(PCIE_PWR_MGMT_THRESH, val);
4348         }
4349
4350         return err;
4351 }
4352
4353 static inline int tg3_irq_sync(struct tg3 *tp)
4354 {
4355         return tp->irq_sync;
4356 }
4357
4358 /* This is called whenever we suspect that the system chipset is re-
4359  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4360  * is bogus tx completions. We try to recover by setting the
4361  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4362  * in the workqueue.
4363  */
4364 static void tg3_tx_recover(struct tg3 *tp)
4365 {
4366         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4367                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4368
4369         netdev_warn(tp->dev,
4370                     "The system may be re-ordering memory-mapped I/O "
4371                     "cycles to the network device, attempting to recover. "
4372                     "Please report the problem to the driver maintainer "
4373                     "and include system chipset information.\n");
4374
4375         spin_lock(&tp->lock);
4376         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4377         spin_unlock(&tp->lock);
4378 }
4379
4380 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4381 {
4382         /* Tell compiler to fetch tx indices from memory. */
4383         barrier();
4384         return tnapi->tx_pending -
4385                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4386 }
4387
4388 /* Tigon3 never reports partial packet sends.  So we do not
4389  * need special logic to handle SKBs that have not had all
4390  * of their frags sent yet, like SunGEM does.
4391  */
4392 static void tg3_tx(struct tg3_napi *tnapi)
4393 {
4394         struct tg3 *tp = tnapi->tp;
4395         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4396         u32 sw_idx = tnapi->tx_cons;
4397         struct netdev_queue *txq;
4398         int index = tnapi - tp->napi;
4399
4400         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4401                 index--;
4402
4403         txq = netdev_get_tx_queue(tp->dev, index);
4404
4405         while (sw_idx != hw_idx) {
4406                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4407                 struct sk_buff *skb = ri->skb;
4408                 int i, tx_bug = 0;
4409
4410                 if (unlikely(skb == NULL)) {
4411                         tg3_tx_recover(tp);
4412                         return;
4413                 }
4414
4415                 pci_unmap_single(tp->pdev,
4416                                  dma_unmap_addr(ri, mapping),
4417                                  skb_headlen(skb),
4418                                  PCI_DMA_TODEVICE);
4419
4420                 ri->skb = NULL;
4421
4422                 sw_idx = NEXT_TX(sw_idx);
4423
4424                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4425                         ri = &tnapi->tx_buffers[sw_idx];
4426                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4427                                 tx_bug = 1;
4428
4429                         pci_unmap_page(tp->pdev,
4430                                        dma_unmap_addr(ri, mapping),
4431                                        skb_shinfo(skb)->frags[i].size,
4432                                        PCI_DMA_TODEVICE);
4433                         sw_idx = NEXT_TX(sw_idx);
4434                 }
4435
4436                 dev_kfree_skb(skb);
4437
4438                 if (unlikely(tx_bug)) {
4439                         tg3_tx_recover(tp);
4440                         return;
4441                 }
4442         }
4443
4444         tnapi->tx_cons = sw_idx;
4445
4446         /* Need to make the tx_cons update visible to tg3_start_xmit()
4447          * before checking for netif_queue_stopped().  Without the
4448          * memory barrier, there is a small possibility that tg3_start_xmit()
4449          * will miss it and cause the queue to be stopped forever.
4450          */
4451         smp_mb();
4452
4453         if (unlikely(netif_tx_queue_stopped(txq) &&
4454                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4455                 __netif_tx_lock(txq, smp_processor_id());
4456                 if (netif_tx_queue_stopped(txq) &&
4457                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4458                         netif_tx_wake_queue(txq);
4459                 __netif_tx_unlock(txq);
4460         }
4461 }
4462
4463 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4464 {
4465         if (!ri->skb)
4466                 return;
4467
4468         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4469                          map_sz, PCI_DMA_FROMDEVICE);
4470         dev_kfree_skb_any(ri->skb);
4471         ri->skb = NULL;
4472 }
4473
4474 /* Returns size of skb allocated or < 0 on error.
4475  *
4476  * We only need to fill in the address because the other members
4477  * of the RX descriptor are invariant, see tg3_init_rings.
4478  *
4479  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4480  * posting buffers we only dirty the first cache line of the RX
4481  * descriptor (containing the address).  Whereas for the RX status
4482  * buffers the cpu only reads the last cacheline of the RX descriptor
4483  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4484  */
4485 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4486                             u32 opaque_key, u32 dest_idx_unmasked)
4487 {
4488         struct tg3_rx_buffer_desc *desc;
4489         struct ring_info *map, *src_map;
4490         struct sk_buff *skb;
4491         dma_addr_t mapping;
4492         int skb_size, dest_idx;
4493
4494         src_map = NULL;
4495         switch (opaque_key) {
4496         case RXD_OPAQUE_RING_STD:
4497                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4498                 desc = &tpr->rx_std[dest_idx];
4499                 map = &tpr->rx_std_buffers[dest_idx];
4500                 skb_size = tp->rx_pkt_map_sz;
4501                 break;
4502
4503         case RXD_OPAQUE_RING_JUMBO:
4504                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4505                 desc = &tpr->rx_jmb[dest_idx].std;
4506                 map = &tpr->rx_jmb_buffers[dest_idx];
4507                 skb_size = TG3_RX_JMB_MAP_SZ;
4508                 break;
4509
4510         default:
4511                 return -EINVAL;
4512         }
4513
4514         /* Do not overwrite any of the map or rp information
4515          * until we are sure we can commit to a new buffer.
4516          *
4517          * Callers depend upon this behavior and assume that
4518          * we leave everything unchanged if we fail.
4519          */
4520         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4521         if (skb == NULL)
4522                 return -ENOMEM;
4523
4524         skb_reserve(skb, tp->rx_offset);
4525
4526         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4527                                  PCI_DMA_FROMDEVICE);
4528         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4529                 dev_kfree_skb(skb);
4530                 return -EIO;
4531         }
4532
4533         map->skb = skb;
4534         dma_unmap_addr_set(map, mapping, mapping);
4535
4536         desc->addr_hi = ((u64)mapping >> 32);
4537         desc->addr_lo = ((u64)mapping & 0xffffffff);
4538
4539         return skb_size;
4540 }
4541
4542 /* We only need to move over in the address because the other
4543  * members of the RX descriptor are invariant.  See notes above
4544  * tg3_alloc_rx_skb for full details.
4545  */
4546 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4547                            struct tg3_rx_prodring_set *dpr,
4548                            u32 opaque_key, int src_idx,
4549                            u32 dest_idx_unmasked)
4550 {
4551         struct tg3 *tp = tnapi->tp;
4552         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4553         struct ring_info *src_map, *dest_map;
4554         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4555         int dest_idx;
4556
4557         switch (opaque_key) {
4558         case RXD_OPAQUE_RING_STD:
4559                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4560                 dest_desc = &dpr->rx_std[dest_idx];
4561                 dest_map = &dpr->rx_std_buffers[dest_idx];
4562                 src_desc = &spr->rx_std[src_idx];
4563                 src_map = &spr->rx_std_buffers[src_idx];
4564                 break;
4565
4566         case RXD_OPAQUE_RING_JUMBO:
4567                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4568                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4569                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4570                 src_desc = &spr->rx_jmb[src_idx].std;
4571                 src_map = &spr->rx_jmb_buffers[src_idx];
4572                 break;
4573
4574         default:
4575                 return;
4576         }
4577
4578         dest_map->skb = src_map->skb;
4579         dma_unmap_addr_set(dest_map, mapping,
4580                            dma_unmap_addr(src_map, mapping));
4581         dest_desc->addr_hi = src_desc->addr_hi;
4582         dest_desc->addr_lo = src_desc->addr_lo;
4583
4584         /* Ensure that the update to the skb happens after the physical
4585          * addresses have been transferred to the new BD location.
4586          */
4587         smp_wmb();
4588
4589         src_map->skb = NULL;
4590 }
4591
4592 /* The RX ring scheme is composed of multiple rings which post fresh
4593  * buffers to the chip, and one special ring the chip uses to report
4594  * status back to the host.
4595  *
4596  * The special ring reports the status of received packets to the
4597  * host.  The chip does not write into the original descriptor the
4598  * RX buffer was obtained from.  The chip simply takes the original
4599  * descriptor as provided by the host, updates the status and length
4600  * field, then writes this into the next status ring entry.
4601  *
4602  * Each ring the host uses to post buffers to the chip is described
4603  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4604  * it is first placed into the on-chip ram.  When the packet's length
4605  * is known, it walks down the TG3_BDINFO entries to select the ring.
4606  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4607  * which is within the range of the new packet's length is chosen.
4608  *
4609  * The "separate ring for rx status" scheme may sound queer, but it makes
4610  * sense from a cache coherency perspective.  If only the host writes
4611  * to the buffer post rings, and only the chip writes to the rx status
4612  * rings, then cache lines never move beyond shared-modified state.
4613  * If both the host and chip were to write into the same ring, cache line
4614  * eviction could occur since both entities want it in an exclusive state.
4615  */
4616 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4617 {
4618         struct tg3 *tp = tnapi->tp;
4619         u32 work_mask, rx_std_posted = 0;
4620         u32 std_prod_idx, jmb_prod_idx;
4621         u32 sw_idx = tnapi->rx_rcb_ptr;
4622         u16 hw_idx;
4623         int received;
4624         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4625
4626         hw_idx = *(tnapi->rx_rcb_prod_idx);
4627         /*
4628          * We need to order the read of hw_idx and the read of
4629          * the opaque cookie.
4630          */
4631         rmb();
4632         work_mask = 0;
4633         received = 0;
4634         std_prod_idx = tpr->rx_std_prod_idx;
4635         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4636         while (sw_idx != hw_idx && budget > 0) {
4637                 struct ring_info *ri;
4638                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4639                 unsigned int len;
4640                 struct sk_buff *skb;
4641                 dma_addr_t dma_addr;
4642                 u32 opaque_key, desc_idx, *post_ptr;
4643                 bool hw_vlan __maybe_unused = false;
4644                 u16 vtag __maybe_unused = 0;
4645
4646                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4647                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4648                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4649                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4650                         dma_addr = dma_unmap_addr(ri, mapping);
4651                         skb = ri->skb;
4652                         post_ptr = &std_prod_idx;
4653                         rx_std_posted++;
4654                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4655                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4656                         dma_addr = dma_unmap_addr(ri, mapping);
4657                         skb = ri->skb;
4658                         post_ptr = &jmb_prod_idx;
4659                 } else
4660                         goto next_pkt_nopost;
4661
4662                 work_mask |= opaque_key;
4663
4664                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4665                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4666                 drop_it:
4667                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4668                                        desc_idx, *post_ptr);
4669                 drop_it_no_recycle:
4670                         /* Other statistics kept track of by card. */
4671                         tp->net_stats.rx_dropped++;
4672                         goto next_pkt;
4673                 }
4674
4675                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4676                       ETH_FCS_LEN;
4677
4678                 if (len > TG3_RX_COPY_THRESH(tp)) {
4679                         int skb_size;
4680
4681                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4682                                                     *post_ptr);
4683                         if (skb_size < 0)
4684                                 goto drop_it;
4685
4686                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4687                                          PCI_DMA_FROMDEVICE);
4688
4689                         /* Ensure that the update to the skb happens
4690                          * after the usage of the old DMA mapping.
4691                          */
4692                         smp_wmb();
4693
4694                         ri->skb = NULL;
4695
4696                         skb_put(skb, len);
4697                 } else {
4698                         struct sk_buff *copy_skb;
4699
4700                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4701                                        desc_idx, *post_ptr);
4702
4703                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4704                                                     TG3_RAW_IP_ALIGN);
4705                         if (copy_skb == NULL)
4706                                 goto drop_it_no_recycle;
4707
4708                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4709                         skb_put(copy_skb, len);
4710                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4712                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4713
4714                         /* We'll reuse the original ring buffer. */
4715                         skb = copy_skb;
4716                 }
4717
4718                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4719                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4720                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4721                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4722                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4723                 else
4724                         skb_checksum_none_assert(skb);
4725
4726                 skb->protocol = eth_type_trans(skb, tp->dev);
4727
4728                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4729                     skb->protocol != htons(ETH_P_8021Q)) {
4730                         dev_kfree_skb(skb);
4731                         goto next_pkt;
4732                 }
4733
4734                 if (desc->type_flags & RXD_FLAG_VLAN &&
4735                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4736                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4737 #if TG3_VLAN_TAG_USED
4738                         if (tp->vlgrp)
4739                                 hw_vlan = true;
4740                         else
4741 #endif
4742                         {
4743                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4744                                                     __skb_push(skb, VLAN_HLEN);
4745
4746                                 memmove(ve, skb->data + VLAN_HLEN,
4747                                         ETH_ALEN * 2);
4748                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4749                                 ve->h_vlan_TCI = htons(vtag);
4750                         }
4751                 }
4752
4753 #if TG3_VLAN_TAG_USED
4754                 if (hw_vlan)
4755                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4756                 else
4757 #endif
4758                         napi_gro_receive(&tnapi->napi, skb);
4759
4760                 received++;
4761                 budget--;
4762
4763 next_pkt:
4764                 (*post_ptr)++;
4765
4766                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4767                         tpr->rx_std_prod_idx = std_prod_idx &
4768                                                tp->rx_std_ring_mask;
4769                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4770                                      tpr->rx_std_prod_idx);
4771                         work_mask &= ~RXD_OPAQUE_RING_STD;
4772                         rx_std_posted = 0;
4773                 }
4774 next_pkt_nopost:
4775                 sw_idx++;
4776                 sw_idx &= tp->rx_ret_ring_mask;
4777
4778                 /* Refresh hw_idx to see if there is new work */
4779                 if (sw_idx == hw_idx) {
4780                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4781                         rmb();
4782                 }
4783         }
4784
4785         /* ACK the status ring. */
4786         tnapi->rx_rcb_ptr = sw_idx;
4787         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4788
4789         /* Refill RX ring(s). */
4790         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4791                 if (work_mask & RXD_OPAQUE_RING_STD) {
4792                         tpr->rx_std_prod_idx = std_prod_idx &
4793                                                tp->rx_std_ring_mask;
4794                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4795                                      tpr->rx_std_prod_idx);
4796                 }
4797                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4798                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4799                                                tp->rx_jmb_ring_mask;
4800                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4801                                      tpr->rx_jmb_prod_idx);
4802                 }
4803                 mmiowb();
4804         } else if (work_mask) {
4805                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4806                  * updated before the producer indices can be updated.
4807                  */
4808                 smp_wmb();
4809
4810                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4811                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4812
4813                 if (tnapi != &tp->napi[1])
4814                         napi_schedule(&tp->napi[1].napi);
4815         }
4816
4817         return received;
4818 }
4819
4820 static void tg3_poll_link(struct tg3 *tp)
4821 {
4822         /* handle link change and other phy events */
4823         if (!(tp->tg3_flags &
4824               (TG3_FLAG_USE_LINKCHG_REG |
4825                TG3_FLAG_POLL_SERDES))) {
4826                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4827
4828                 if (sblk->status & SD_STATUS_LINK_CHG) {
4829                         sblk->status = SD_STATUS_UPDATED |
4830                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4831                         spin_lock(&tp->lock);
4832                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4833                                 tw32_f(MAC_STATUS,
4834                                      (MAC_STATUS_SYNC_CHANGED |
4835                                       MAC_STATUS_CFG_CHANGED |
4836                                       MAC_STATUS_MI_COMPLETION |
4837                                       MAC_STATUS_LNKSTATE_CHANGED));
4838                                 udelay(40);
4839                         } else
4840                                 tg3_setup_phy(tp, 0);
4841                         spin_unlock(&tp->lock);
4842                 }
4843         }
4844 }
4845
4846 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4847                                 struct tg3_rx_prodring_set *dpr,
4848                                 struct tg3_rx_prodring_set *spr)
4849 {
4850         u32 si, di, cpycnt, src_prod_idx;
4851         int i, err = 0;
4852
4853         while (1) {
4854                 src_prod_idx = spr->rx_std_prod_idx;
4855
4856                 /* Make sure updates to the rx_std_buffers[] entries and the
4857                  * standard producer index are seen in the correct order.
4858                  */
4859                 smp_rmb();
4860
4861                 if (spr->rx_std_cons_idx == src_prod_idx)
4862                         break;
4863
4864                 if (spr->rx_std_cons_idx < src_prod_idx)
4865                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4866                 else
4867                         cpycnt = tp->rx_std_ring_mask + 1 -
4868                                  spr->rx_std_cons_idx;
4869
4870                 cpycnt = min(cpycnt,
4871                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4872
4873                 si = spr->rx_std_cons_idx;
4874                 di = dpr->rx_std_prod_idx;
4875
4876                 for (i = di; i < di + cpycnt; i++) {
4877                         if (dpr->rx_std_buffers[i].skb) {
4878                                 cpycnt = i - di;
4879                                 err = -ENOSPC;
4880                                 break;
4881                         }
4882                 }
4883
4884                 if (!cpycnt)
4885                         break;
4886
4887                 /* Ensure that updates to the rx_std_buffers ring and the
4888                  * shadowed hardware producer ring from tg3_recycle_skb() are
4889                  * ordered correctly WRT the skb check above.
4890                  */
4891                 smp_rmb();
4892
4893                 memcpy(&dpr->rx_std_buffers[di],
4894                        &spr->rx_std_buffers[si],
4895                        cpycnt * sizeof(struct ring_info));
4896
4897                 for (i = 0; i < cpycnt; i++, di++, si++) {
4898                         struct tg3_rx_buffer_desc *sbd, *dbd;
4899                         sbd = &spr->rx_std[si];
4900                         dbd = &dpr->rx_std[di];
4901                         dbd->addr_hi = sbd->addr_hi;
4902                         dbd->addr_lo = sbd->addr_lo;
4903                 }
4904
4905                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4906                                        tp->rx_std_ring_mask;
4907                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4908                                        tp->rx_std_ring_mask;
4909         }
4910
4911         while (1) {
4912                 src_prod_idx = spr->rx_jmb_prod_idx;
4913
4914                 /* Make sure updates to the rx_jmb_buffers[] entries and
4915                  * the jumbo producer index are seen in the correct order.
4916                  */
4917                 smp_rmb();
4918
4919                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4920                         break;
4921
4922                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4923                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4924                 else
4925                         cpycnt = tp->rx_jmb_ring_mask + 1 -
4926                                  spr->rx_jmb_cons_idx;
4927
4928                 cpycnt = min(cpycnt,
4929                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
4930
4931                 si = spr->rx_jmb_cons_idx;
4932                 di = dpr->rx_jmb_prod_idx;
4933
4934                 for (i = di; i < di + cpycnt; i++) {
4935                         if (dpr->rx_jmb_buffers[i].skb) {
4936                                 cpycnt = i - di;
4937                                 err = -ENOSPC;
4938                                 break;
4939                         }
4940                 }
4941
4942                 if (!cpycnt)
4943                         break;
4944
4945                 /* Ensure that updates to the rx_jmb_buffers ring and the
4946                  * shadowed hardware producer ring from tg3_recycle_skb() are
4947                  * ordered correctly WRT the skb check above.
4948                  */
4949                 smp_rmb();
4950
4951                 memcpy(&dpr->rx_jmb_buffers[di],
4952                        &spr->rx_jmb_buffers[si],
4953                        cpycnt * sizeof(struct ring_info));
4954
4955                 for (i = 0; i < cpycnt; i++, di++, si++) {
4956                         struct tg3_rx_buffer_desc *sbd, *dbd;
4957                         sbd = &spr->rx_jmb[si].std;
4958                         dbd = &dpr->rx_jmb[di].std;
4959                         dbd->addr_hi = sbd->addr_hi;
4960                         dbd->addr_lo = sbd->addr_lo;
4961                 }
4962
4963                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
4964                                        tp->rx_jmb_ring_mask;
4965                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
4966                                        tp->rx_jmb_ring_mask;
4967         }
4968
4969         return err;
4970 }
4971
4972 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4973 {
4974         struct tg3 *tp = tnapi->tp;
4975
4976         /* run TX completion thread */
4977         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4978                 tg3_tx(tnapi);
4979                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4980                         return work_done;
4981         }
4982
4983         /* run RX thread, within the bounds set by NAPI.
4984          * All RX "locking" is done by ensuring outside
4985          * code synchronizes with tg3->napi.poll()
4986          */
4987         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4988                 work_done += tg3_rx(tnapi, budget - work_done);
4989
4990         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4991                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4992                 int i, err = 0;
4993                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4994                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4995
4996                 for (i = 1; i < tp->irq_cnt; i++)
4997                         err |= tg3_rx_prodring_xfer(tp, dpr,
4998                                                     &tp->napi[i].prodring);
4999
5000                 wmb();
5001
5002                 if (std_prod_idx != dpr->rx_std_prod_idx)
5003                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5004                                      dpr->rx_std_prod_idx);
5005
5006                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5007                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5008                                      dpr->rx_jmb_prod_idx);
5009
5010                 mmiowb();
5011
5012                 if (err)
5013                         tw32_f(HOSTCC_MODE, tp->coal_now);
5014         }
5015
5016         return work_done;
5017 }
5018
5019 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5020 {
5021         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5022         struct tg3 *tp = tnapi->tp;
5023         int work_done = 0;
5024         struct tg3_hw_status *sblk = tnapi->hw_status;
5025
5026         while (1) {
5027                 work_done = tg3_poll_work(tnapi, work_done, budget);
5028
5029                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5030                         goto tx_recovery;
5031
5032                 if (unlikely(work_done >= budget))
5033                         break;
5034
5035                 /* tp->last_tag is used in tg3_int_reenable() below
5036                  * to tell the hw how much work has been processed,
5037                  * so we must read it before checking for more work.
5038                  */
5039                 tnapi->last_tag = sblk->status_tag;
5040                 tnapi->last_irq_tag = tnapi->last_tag;
5041                 rmb();
5042
5043                 /* check for RX/TX work to do */
5044                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5045                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5046                         napi_complete(napi);
5047                         /* Reenable interrupts. */
5048                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5049                         mmiowb();
5050                         break;
5051                 }
5052         }
5053
5054         return work_done;
5055
5056 tx_recovery:
5057         /* work_done is guaranteed to be less than budget. */
5058         napi_complete(napi);
5059         schedule_work(&tp->reset_task);
5060         return work_done;
5061 }
5062
5063 static int tg3_poll(struct napi_struct *napi, int budget)
5064 {
5065         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5066         struct tg3 *tp = tnapi->tp;
5067         int work_done = 0;
5068         struct tg3_hw_status *sblk = tnapi->hw_status;
5069
5070         while (1) {
5071                 tg3_poll_link(tp);
5072
5073                 work_done = tg3_poll_work(tnapi, work_done, budget);
5074
5075                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5076                         goto tx_recovery;
5077
5078                 if (unlikely(work_done >= budget))
5079                         break;
5080
5081                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5082                         /* tp->last_tag is used in tg3_int_reenable() below
5083                          * to tell the hw how much work has been processed,
5084                          * so we must read it before checking for more work.
5085                          */
5086                         tnapi->last_tag = sblk->status_tag;
5087                         tnapi->last_irq_tag = tnapi->last_tag;
5088                         rmb();
5089                 } else
5090                         sblk->status &= ~SD_STATUS_UPDATED;
5091
5092                 if (likely(!tg3_has_work(tnapi))) {
5093                         napi_complete(napi);
5094                         tg3_int_reenable(tnapi);
5095                         break;
5096                 }
5097         }
5098
5099         return work_done;
5100
5101 tx_recovery:
5102         /* work_done is guaranteed to be less than budget. */
5103         napi_complete(napi);
5104         schedule_work(&tp->reset_task);
5105         return work_done;
5106 }
5107
5108 static void tg3_napi_disable(struct tg3 *tp)
5109 {
5110         int i;
5111
5112         for (i = tp->irq_cnt - 1; i >= 0; i--)
5113                 napi_disable(&tp->napi[i].napi);
5114 }
5115
5116 static void tg3_napi_enable(struct tg3 *tp)
5117 {
5118         int i;
5119
5120         for (i = 0; i < tp->irq_cnt; i++)
5121                 napi_enable(&tp->napi[i].napi);
5122 }
5123
5124 static void tg3_napi_init(struct tg3 *tp)
5125 {
5126         int i;
5127
5128         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5129         for (i = 1; i < tp->irq_cnt; i++)
5130                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5131 }
5132
5133 static void tg3_napi_fini(struct tg3 *tp)
5134 {
5135         int i;
5136
5137         for (i = 0; i < tp->irq_cnt; i++)
5138                 netif_napi_del(&tp->napi[i].napi);
5139 }
5140
5141 static inline void tg3_netif_stop(struct tg3 *tp)
5142 {
5143         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5144         tg3_napi_disable(tp);
5145         netif_tx_disable(tp->dev);
5146 }
5147
5148 static inline void tg3_netif_start(struct tg3 *tp)
5149 {
5150         /* NOTE: unconditional netif_tx_wake_all_queues is only
5151          * appropriate so long as all callers are assured to
5152          * have free tx slots (such as after tg3_init_hw)
5153          */
5154         netif_tx_wake_all_queues(tp->dev);
5155
5156         tg3_napi_enable(tp);
5157         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5158         tg3_enable_ints(tp);
5159 }
5160
5161 static void tg3_irq_quiesce(struct tg3 *tp)
5162 {
5163         int i;
5164
5165         BUG_ON(tp->irq_sync);
5166
5167         tp->irq_sync = 1;
5168         smp_mb();
5169
5170         for (i = 0; i < tp->irq_cnt; i++)
5171                 synchronize_irq(tp->napi[i].irq_vec);
5172 }
5173
5174 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5175  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5176  * with as well.  Most of the time, this is not necessary except when
5177  * shutting down the device.
5178  */
5179 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5180 {
5181         spin_lock_bh(&tp->lock);
5182         if (irq_sync)
5183                 tg3_irq_quiesce(tp);
5184 }
5185
5186 static inline void tg3_full_unlock(struct tg3 *tp)
5187 {
5188         spin_unlock_bh(&tp->lock);
5189 }
5190
5191 /* One-shot MSI handler - Chip automatically disables interrupt
5192  * after sending MSI so driver doesn't have to do it.
5193  */
5194 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5195 {
5196         struct tg3_napi *tnapi = dev_id;
5197         struct tg3 *tp = tnapi->tp;
5198
5199         prefetch(tnapi->hw_status);
5200         if (tnapi->rx_rcb)
5201                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5202
5203         if (likely(!tg3_irq_sync(tp)))
5204                 napi_schedule(&tnapi->napi);
5205
5206         return IRQ_HANDLED;
5207 }
5208
5209 /* MSI ISR - No need to check for interrupt sharing and no need to
5210  * flush status block and interrupt mailbox. PCI ordering rules
5211  * guarantee that MSI will arrive after the status block.
5212  */
5213 static irqreturn_t tg3_msi(int irq, void *dev_id)
5214 {
5215         struct tg3_napi *tnapi = dev_id;
5216         struct tg3 *tp = tnapi->tp;
5217
5218         prefetch(tnapi->hw_status);
5219         if (tnapi->rx_rcb)
5220                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5221         /*
5222          * Writing any value to intr-mbox-0 clears PCI INTA# and
5223          * chip-internal interrupt pending events.
5224          * Writing non-zero to intr-mbox-0 additional tells the
5225          * NIC to stop sending us irqs, engaging "in-intr-handler"
5226          * event coalescing.
5227          */
5228         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5229         if (likely(!tg3_irq_sync(tp)))
5230                 napi_schedule(&tnapi->napi);
5231
5232         return IRQ_RETVAL(1);
5233 }
5234
5235 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5236 {
5237         struct tg3_napi *tnapi = dev_id;
5238         struct tg3 *tp = tnapi->tp;
5239         struct tg3_hw_status *sblk = tnapi->hw_status;
5240         unsigned int handled = 1;
5241
5242         /* In INTx mode, it is possible for the interrupt to arrive at
5243          * the CPU before the status block posted prior to the interrupt.
5244          * Reading the PCI State register will confirm whether the
5245          * interrupt is ours and will flush the status block.
5246          */
5247         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5248                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5249                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5250                         handled = 0;
5251                         goto out;
5252                 }
5253         }
5254
5255         /*
5256          * Writing any value to intr-mbox-0 clears PCI INTA# and
5257          * chip-internal interrupt pending events.
5258          * Writing non-zero to intr-mbox-0 additional tells the
5259          * NIC to stop sending us irqs, engaging "in-intr-handler"
5260          * event coalescing.
5261          *
5262          * Flush the mailbox to de-assert the IRQ immediately to prevent
5263          * spurious interrupts.  The flush impacts performance but
5264          * excessive spurious interrupts can be worse in some cases.
5265          */
5266         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5267         if (tg3_irq_sync(tp))
5268                 goto out;
5269         sblk->status &= ~SD_STATUS_UPDATED;
5270         if (likely(tg3_has_work(tnapi))) {
5271                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5272                 napi_schedule(&tnapi->napi);
5273         } else {
5274                 /* No work, shared interrupt perhaps?  re-enable
5275                  * interrupts, and flush that PCI write
5276                  */
5277                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5278                                0x00000000);
5279         }
5280 out:
5281         return IRQ_RETVAL(handled);
5282 }
5283
5284 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5285 {
5286         struct tg3_napi *tnapi = dev_id;
5287         struct tg3 *tp = tnapi->tp;
5288         struct tg3_hw_status *sblk = tnapi->hw_status;
5289         unsigned int handled = 1;
5290
5291         /* In INTx mode, it is possible for the interrupt to arrive at
5292          * the CPU before the status block posted prior to the interrupt.
5293          * Reading the PCI State register will confirm whether the
5294          * interrupt is ours and will flush the status block.
5295          */
5296         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5297                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5298                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5299                         handled = 0;
5300                         goto out;
5301                 }
5302         }
5303
5304         /*
5305          * writing any value to intr-mbox-0 clears PCI INTA# and
5306          * chip-internal interrupt pending events.
5307          * writing non-zero to intr-mbox-0 additional tells the
5308          * NIC to stop sending us irqs, engaging "in-intr-handler"
5309          * event coalescing.
5310          *
5311          * Flush the mailbox to de-assert the IRQ immediately to prevent
5312          * spurious interrupts.  The flush impacts performance but
5313          * excessive spurious interrupts can be worse in some cases.
5314          */
5315         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5316
5317         /*
5318          * In a shared interrupt configuration, sometimes other devices'
5319          * interrupts will scream.  We record the current status tag here
5320          * so that the above check can report that the screaming interrupts
5321          * are unhandled.  Eventually they will be silenced.
5322          */
5323         tnapi->last_irq_tag = sblk->status_tag;
5324
5325         if (tg3_irq_sync(tp))
5326                 goto out;
5327
5328         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5329
5330         napi_schedule(&tnapi->napi);
5331
5332 out:
5333         return IRQ_RETVAL(handled);
5334 }
5335
5336 /* ISR for interrupt test */
5337 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5338 {
5339         struct tg3_napi *tnapi = dev_id;
5340         struct tg3 *tp = tnapi->tp;
5341         struct tg3_hw_status *sblk = tnapi->hw_status;
5342
5343         if ((sblk->status & SD_STATUS_UPDATED) ||
5344             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5345                 tg3_disable_ints(tp);
5346                 return IRQ_RETVAL(1);
5347         }
5348         return IRQ_RETVAL(0);
5349 }
5350
5351 static int tg3_init_hw(struct tg3 *, int);
5352 static int tg3_halt(struct tg3 *, int, int);
5353
5354 /* Restart hardware after configuration changes, self-test, etc.
5355  * Invoked with tp->lock held.
5356  */
5357 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5358         __releases(tp->lock)
5359         __acquires(tp->lock)
5360 {
5361         int err;
5362
5363         err = tg3_init_hw(tp, reset_phy);
5364         if (err) {
5365                 netdev_err(tp->dev,
5366                            "Failed to re-initialize device, aborting\n");
5367                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5368                 tg3_full_unlock(tp);
5369                 del_timer_sync(&tp->timer);
5370                 tp->irq_sync = 0;
5371                 tg3_napi_enable(tp);
5372                 dev_close(tp->dev);
5373                 tg3_full_lock(tp, 0);
5374         }
5375         return err;
5376 }
5377
5378 #ifdef CONFIG_NET_POLL_CONTROLLER
5379 static void tg3_poll_controller(struct net_device *dev)
5380 {
5381         int i;
5382         struct tg3 *tp = netdev_priv(dev);
5383
5384         for (i = 0; i < tp->irq_cnt; i++)
5385                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5386 }
5387 #endif
5388
5389 static void tg3_reset_task(struct work_struct *work)
5390 {
5391         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5392         int err;
5393         unsigned int restart_timer;
5394
5395         tg3_full_lock(tp, 0);
5396
5397         if (!netif_running(tp->dev)) {
5398                 tg3_full_unlock(tp);
5399                 return;
5400         }
5401
5402         tg3_full_unlock(tp);
5403
5404         tg3_phy_stop(tp);
5405
5406         tg3_netif_stop(tp);
5407
5408         tg3_full_lock(tp, 1);
5409
5410         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5411         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5412
5413         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5414                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5415                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5416                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5417                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5418         }
5419
5420         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5421         err = tg3_init_hw(tp, 1);
5422         if (err)
5423                 goto out;
5424
5425         tg3_netif_start(tp);
5426
5427         if (restart_timer)
5428                 mod_timer(&tp->timer, jiffies + 1);
5429
5430 out:
5431         tg3_full_unlock(tp);
5432
5433         if (!err)
5434                 tg3_phy_start(tp);
5435 }
5436
5437 static void tg3_dump_short_state(struct tg3 *tp)
5438 {
5439         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5440                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5441         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5442                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5443 }
5444
5445 static void tg3_tx_timeout(struct net_device *dev)
5446 {
5447         struct tg3 *tp = netdev_priv(dev);
5448
5449         if (netif_msg_tx_err(tp)) {
5450                 netdev_err(dev, "transmit timed out, resetting\n");
5451                 tg3_dump_short_state(tp);
5452         }
5453
5454         schedule_work(&tp->reset_task);
5455 }
5456
5457 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5458 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5459 {
5460         u32 base = (u32) mapping & 0xffffffff;
5461
5462         return (base > 0xffffdcc0) && (base + len + 8 < base);
5463 }
5464
5465 /* Test for DMA addresses > 40-bit */
5466 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5467                                           int len)
5468 {
5469 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5470         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5471                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5472         return 0;
5473 #else
5474         return 0;
5475 #endif
5476 }
5477
5478 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5479
5480 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5481 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5482                                        struct sk_buff *skb, u32 last_plus_one,
5483                                        u32 *start, u32 base_flags, u32 mss)
5484 {
5485         struct tg3 *tp = tnapi->tp;
5486         struct sk_buff *new_skb;
5487         dma_addr_t new_addr = 0;
5488         u32 entry = *start;
5489         int i, ret = 0;
5490
5491         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5492                 new_skb = skb_copy(skb, GFP_ATOMIC);
5493         else {
5494                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5495
5496                 new_skb = skb_copy_expand(skb,
5497                                           skb_headroom(skb) + more_headroom,
5498                                           skb_tailroom(skb), GFP_ATOMIC);
5499         }
5500
5501         if (!new_skb) {
5502                 ret = -1;
5503         } else {
5504                 /* New SKB is guaranteed to be linear. */
5505                 entry = *start;
5506                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5507                                           PCI_DMA_TODEVICE);
5508                 /* Make sure the mapping succeeded */
5509                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5510                         ret = -1;
5511                         dev_kfree_skb(new_skb);
5512                         new_skb = NULL;
5513
5514                 /* Make sure new skb does not cross any 4G boundaries.
5515                  * Drop the packet if it does.
5516                  */
5517                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5518                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5519                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5520                                          PCI_DMA_TODEVICE);
5521                         ret = -1;
5522                         dev_kfree_skb(new_skb);
5523                         new_skb = NULL;
5524                 } else {
5525                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5526                                     base_flags, 1 | (mss << 1));
5527                         *start = NEXT_TX(entry);
5528                 }
5529         }
5530
5531         /* Now clean up the sw ring entries. */
5532         i = 0;
5533         while (entry != last_plus_one) {
5534                 int len;
5535
5536                 if (i == 0)
5537                         len = skb_headlen(skb);
5538                 else
5539                         len = skb_shinfo(skb)->frags[i-1].size;
5540
5541                 pci_unmap_single(tp->pdev,
5542                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5543                                                 mapping),
5544                                  len, PCI_DMA_TODEVICE);
5545                 if (i == 0) {
5546                         tnapi->tx_buffers[entry].skb = new_skb;
5547                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5548                                            new_addr);
5549                 } else {
5550                         tnapi->tx_buffers[entry].skb = NULL;
5551                 }
5552                 entry = NEXT_TX(entry);
5553                 i++;
5554         }
5555
5556         dev_kfree_skb(skb);
5557
5558         return ret;
5559 }
5560
5561 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5562                         dma_addr_t mapping, int len, u32 flags,
5563                         u32 mss_and_is_end)
5564 {
5565         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5566         int is_end = (mss_and_is_end & 0x1);
5567         u32 mss = (mss_and_is_end >> 1);
5568         u32 vlan_tag = 0;
5569
5570         if (is_end)
5571                 flags |= TXD_FLAG_END;
5572         if (flags & TXD_FLAG_VLAN) {
5573                 vlan_tag = flags >> 16;
5574                 flags &= 0xffff;
5575         }
5576         vlan_tag |= (mss << TXD_MSS_SHIFT);
5577
5578         txd->addr_hi = ((u64) mapping >> 32);
5579         txd->addr_lo = ((u64) mapping & 0xffffffff);
5580         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5581         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5582 }
5583
5584 /* hard_start_xmit for devices that don't have any bugs and
5585  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5586  */
5587 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5588                                   struct net_device *dev)
5589 {
5590         struct tg3 *tp = netdev_priv(dev);
5591         u32 len, entry, base_flags, mss;
5592         dma_addr_t mapping;
5593         struct tg3_napi *tnapi;
5594         struct netdev_queue *txq;
5595         unsigned int i, last;
5596
5597         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5598         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5599         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5600                 tnapi++;
5601
5602         /* We are running in BH disabled context with netif_tx_lock
5603          * and TX reclaim runs via tp->napi.poll inside of a software
5604          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5605          * no IRQ context deadlocks to worry about either.  Rejoice!
5606          */
5607         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5608                 if (!netif_tx_queue_stopped(txq)) {
5609                         netif_tx_stop_queue(txq);
5610
5611                         /* This is a hard error, log it. */
5612                         netdev_err(dev,
5613                                    "BUG! Tx Ring full when queue awake!\n");
5614                 }
5615                 return NETDEV_TX_BUSY;
5616         }
5617
5618         entry = tnapi->tx_prod;
5619         base_flags = 0;
5620         mss = skb_shinfo(skb)->gso_size;
5621         if (mss) {
5622                 int tcp_opt_len, ip_tcp_len;
5623                 u32 hdrlen;
5624
5625                 if (skb_header_cloned(skb) &&
5626                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5627                         dev_kfree_skb(skb);
5628                         goto out_unlock;
5629                 }
5630
5631                 if (skb_is_gso_v6(skb)) {
5632                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5633                 } else {
5634                         struct iphdr *iph = ip_hdr(skb);
5635
5636                         tcp_opt_len = tcp_optlen(skb);
5637                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5638
5639                         iph->check = 0;
5640                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5641                         hdrlen = ip_tcp_len + tcp_opt_len;
5642                 }
5643
5644                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5645                         mss |= (hdrlen & 0xc) << 12;
5646                         if (hdrlen & 0x10)
5647                                 base_flags |= 0x00000010;
5648                         base_flags |= (hdrlen & 0x3e0) << 5;
5649                 } else
5650                         mss |= hdrlen << 9;
5651
5652                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5653                                TXD_FLAG_CPU_POST_DMA);
5654
5655                 tcp_hdr(skb)->check = 0;
5656
5657         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5658                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5659         }
5660
5661 #if TG3_VLAN_TAG_USED
5662         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5663                 base_flags |= (TXD_FLAG_VLAN |
5664                                (vlan_tx_tag_get(skb) << 16));
5665 #endif
5666
5667         len = skb_headlen(skb);
5668
5669         /* Queue skb data, a.k.a. the main skb fragment. */
5670         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5671         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5672                 dev_kfree_skb(skb);
5673                 goto out_unlock;
5674         }
5675
5676         tnapi->tx_buffers[entry].skb = skb;
5677         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5678
5679         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5680             !mss && skb->len > ETH_DATA_LEN)
5681                 base_flags |= TXD_FLAG_JMB_PKT;
5682
5683         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5684                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5685
5686         entry = NEXT_TX(entry);
5687
5688         /* Now loop through additional data fragments, and queue them. */
5689         if (skb_shinfo(skb)->nr_frags > 0) {
5690                 last = skb_shinfo(skb)->nr_frags - 1;
5691                 for (i = 0; i <= last; i++) {
5692                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5693
5694                         len = frag->size;
5695                         mapping = pci_map_page(tp->pdev,
5696                                                frag->page,
5697                                                frag->page_offset,
5698                                                len, PCI_DMA_TODEVICE);
5699                         if (pci_dma_mapping_error(tp->pdev, mapping))
5700                                 goto dma_error;
5701
5702                         tnapi->tx_buffers[entry].skb = NULL;
5703                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5704                                            mapping);
5705
5706                         tg3_set_txd(tnapi, entry, mapping, len,
5707                                     base_flags, (i == last) | (mss << 1));
5708
5709                         entry = NEXT_TX(entry);
5710                 }
5711         }
5712
5713         /* Packets are ready, update Tx producer idx local and on card. */
5714         tw32_tx_mbox(tnapi->prodmbox, entry);
5715
5716         tnapi->tx_prod = entry;
5717         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5718                 netif_tx_stop_queue(txq);
5719
5720                 /* netif_tx_stop_queue() must be done before checking
5721                  * checking tx index in tg3_tx_avail() below, because in
5722                  * tg3_tx(), we update tx index before checking for
5723                  * netif_tx_queue_stopped().
5724                  */
5725                 smp_mb();
5726                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5727                         netif_tx_wake_queue(txq);
5728         }
5729
5730 out_unlock:
5731         mmiowb();
5732
5733         return NETDEV_TX_OK;
5734
5735 dma_error:
5736         last = i;
5737         entry = tnapi->tx_prod;
5738         tnapi->tx_buffers[entry].skb = NULL;
5739         pci_unmap_single(tp->pdev,
5740                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5741                          skb_headlen(skb),
5742                          PCI_DMA_TODEVICE);
5743         for (i = 0; i <= last; i++) {
5744                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5745                 entry = NEXT_TX(entry);
5746
5747                 pci_unmap_page(tp->pdev,
5748                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5749                                               mapping),
5750                                frag->size, PCI_DMA_TODEVICE);
5751         }
5752
5753         dev_kfree_skb(skb);
5754         return NETDEV_TX_OK;
5755 }
5756
5757 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5758                                           struct net_device *);
5759
5760 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5761  * TSO header is greater than 80 bytes.
5762  */
5763 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5764 {
5765         struct sk_buff *segs, *nskb;
5766         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5767
5768         /* Estimate the number of fragments in the worst case */
5769         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5770                 netif_stop_queue(tp->dev);
5771
5772                 /* netif_tx_stop_queue() must be done before checking
5773                  * checking tx index in tg3_tx_avail() below, because in
5774                  * tg3_tx(), we update tx index before checking for
5775                  * netif_tx_queue_stopped().
5776                  */
5777                 smp_mb();
5778                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5779                         return NETDEV_TX_BUSY;
5780
5781                 netif_wake_queue(tp->dev);
5782         }
5783
5784         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5785         if (IS_ERR(segs))
5786                 goto tg3_tso_bug_end;
5787
5788         do {
5789                 nskb = segs;
5790                 segs = segs->next;
5791                 nskb->next = NULL;
5792                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5793         } while (segs);
5794
5795 tg3_tso_bug_end:
5796         dev_kfree_skb(skb);
5797
5798         return NETDEV_TX_OK;
5799 }
5800
5801 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5802  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5803  */
5804 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5805                                           struct net_device *dev)
5806 {
5807         struct tg3 *tp = netdev_priv(dev);
5808         u32 len, entry, base_flags, mss;
5809         int would_hit_hwbug;
5810         dma_addr_t mapping;
5811         struct tg3_napi *tnapi;
5812         struct netdev_queue *txq;
5813         unsigned int i, last;
5814
5815         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5816         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5817         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5818                 tnapi++;
5819
5820         /* We are running in BH disabled context with netif_tx_lock
5821          * and TX reclaim runs via tp->napi.poll inside of a software
5822          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5823          * no IRQ context deadlocks to worry about either.  Rejoice!
5824          */
5825         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5826                 if (!netif_tx_queue_stopped(txq)) {
5827                         netif_tx_stop_queue(txq);
5828
5829                         /* This is a hard error, log it. */
5830                         netdev_err(dev,
5831                                    "BUG! Tx Ring full when queue awake!\n");
5832                 }
5833                 return NETDEV_TX_BUSY;
5834         }
5835
5836         entry = tnapi->tx_prod;
5837         base_flags = 0;
5838         if (skb->ip_summed == CHECKSUM_PARTIAL)
5839                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5840
5841         mss = skb_shinfo(skb)->gso_size;
5842         if (mss) {
5843                 struct iphdr *iph;
5844                 u32 tcp_opt_len, hdr_len;
5845
5846                 if (skb_header_cloned(skb) &&
5847                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5848                         dev_kfree_skb(skb);
5849                         goto out_unlock;
5850                 }
5851
5852                 iph = ip_hdr(skb);
5853                 tcp_opt_len = tcp_optlen(skb);
5854
5855                 if (skb_is_gso_v6(skb)) {
5856                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5857                 } else {
5858                         u32 ip_tcp_len;
5859
5860                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5861                         hdr_len = ip_tcp_len + tcp_opt_len;
5862
5863                         iph->check = 0;
5864                         iph->tot_len = htons(mss + hdr_len);
5865                 }
5866
5867                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5868                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5869                         return tg3_tso_bug(tp, skb);
5870
5871                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5872                                TXD_FLAG_CPU_POST_DMA);
5873
5874                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5875                         tcp_hdr(skb)->check = 0;
5876                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5877                 } else
5878                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5879                                                                  iph->daddr, 0,
5880                                                                  IPPROTO_TCP,
5881                                                                  0);
5882
5883                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5884                         mss |= (hdr_len & 0xc) << 12;
5885                         if (hdr_len & 0x10)
5886                                 base_flags |= 0x00000010;
5887                         base_flags |= (hdr_len & 0x3e0) << 5;
5888                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5889                         mss |= hdr_len << 9;
5890                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5891                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5892                         if (tcp_opt_len || iph->ihl > 5) {
5893                                 int tsflags;
5894
5895                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5896                                 mss |= (tsflags << 11);
5897                         }
5898                 } else {
5899                         if (tcp_opt_len || iph->ihl > 5) {
5900                                 int tsflags;
5901
5902                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5903                                 base_flags |= tsflags << 12;
5904                         }
5905                 }
5906         }
5907 #if TG3_VLAN_TAG_USED
5908         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5909                 base_flags |= (TXD_FLAG_VLAN |
5910                                (vlan_tx_tag_get(skb) << 16));
5911 #endif
5912
5913         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5914             !mss && skb->len > ETH_DATA_LEN)
5915                 base_flags |= TXD_FLAG_JMB_PKT;
5916
5917         len = skb_headlen(skb);
5918
5919         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5920         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5921                 dev_kfree_skb(skb);
5922                 goto out_unlock;
5923         }
5924
5925         tnapi->tx_buffers[entry].skb = skb;
5926         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5927
5928         would_hit_hwbug = 0;
5929
5930         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5931                 would_hit_hwbug = 1;
5932
5933         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5934             tg3_4g_overflow_test(mapping, len))
5935                 would_hit_hwbug = 1;
5936
5937         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5938             tg3_40bit_overflow_test(tp, mapping, len))
5939                 would_hit_hwbug = 1;
5940
5941         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5942                 would_hit_hwbug = 1;
5943
5944         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5945                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5946
5947         entry = NEXT_TX(entry);
5948
5949         /* Now loop through additional data fragments, and queue them. */
5950         if (skb_shinfo(skb)->nr_frags > 0) {
5951                 last = skb_shinfo(skb)->nr_frags - 1;
5952                 for (i = 0; i <= last; i++) {
5953                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5954
5955                         len = frag->size;
5956                         mapping = pci_map_page(tp->pdev,
5957                                                frag->page,
5958                                                frag->page_offset,
5959                                                len, PCI_DMA_TODEVICE);
5960
5961                         tnapi->tx_buffers[entry].skb = NULL;
5962                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5963                                            mapping);
5964                         if (pci_dma_mapping_error(tp->pdev, mapping))
5965                                 goto dma_error;
5966
5967                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5968                             len <= 8)
5969                                 would_hit_hwbug = 1;
5970
5971                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5972                             tg3_4g_overflow_test(mapping, len))
5973                                 would_hit_hwbug = 1;
5974
5975                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5976                             tg3_40bit_overflow_test(tp, mapping, len))
5977                                 would_hit_hwbug = 1;
5978
5979                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5980                                 tg3_set_txd(tnapi, entry, mapping, len,
5981                                             base_flags, (i == last)|(mss << 1));
5982                         else
5983                                 tg3_set_txd(tnapi, entry, mapping, len,
5984                                             base_flags, (i == last));
5985
5986                         entry = NEXT_TX(entry);
5987                 }
5988         }
5989
5990         if (would_hit_hwbug) {
5991                 u32 last_plus_one = entry;
5992                 u32 start;
5993
5994                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5995                 start &= (TG3_TX_RING_SIZE - 1);
5996
5997                 /* If the workaround fails due to memory/mapping
5998                  * failure, silently drop this packet.
5999                  */
6000                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6001                                                 &start, base_flags, mss))
6002                         goto out_unlock;
6003
6004                 entry = start;
6005         }
6006
6007         /* Packets are ready, update Tx producer idx local and on card. */
6008         tw32_tx_mbox(tnapi->prodmbox, entry);
6009
6010         tnapi->tx_prod = entry;
6011         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6012                 netif_tx_stop_queue(txq);
6013
6014                 /* netif_tx_stop_queue() must be done before checking
6015                  * checking tx index in tg3_tx_avail() below, because in
6016                  * tg3_tx(), we update tx index before checking for
6017                  * netif_tx_queue_stopped().
6018                  */
6019                 smp_mb();
6020                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6021                         netif_tx_wake_queue(txq);
6022         }
6023
6024 out_unlock:
6025         mmiowb();
6026
6027         return NETDEV_TX_OK;
6028
6029 dma_error:
6030         last = i;
6031         entry = tnapi->tx_prod;
6032         tnapi->tx_buffers[entry].skb = NULL;
6033         pci_unmap_single(tp->pdev,
6034                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6035                          skb_headlen(skb),
6036                          PCI_DMA_TODEVICE);
6037         for (i = 0; i <= last; i++) {
6038                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6039                 entry = NEXT_TX(entry);
6040
6041                 pci_unmap_page(tp->pdev,
6042                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6043                                               mapping),
6044                                frag->size, PCI_DMA_TODEVICE);
6045         }
6046
6047         dev_kfree_skb(skb);
6048         return NETDEV_TX_OK;
6049 }
6050
6051 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6052                                int new_mtu)
6053 {
6054         dev->mtu = new_mtu;
6055
6056         if (new_mtu > ETH_DATA_LEN) {
6057                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6058                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6059                         ethtool_op_set_tso(dev, 0);
6060                 } else {
6061                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6062                 }
6063         } else {
6064                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6065                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6066                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6067         }
6068 }
6069
6070 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6071 {
6072         struct tg3 *tp = netdev_priv(dev);
6073         int err;
6074
6075         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6076                 return -EINVAL;
6077
6078         if (!netif_running(dev)) {
6079                 /* We'll just catch it later when the
6080                  * device is up'd.
6081                  */
6082                 tg3_set_mtu(dev, tp, new_mtu);
6083                 return 0;
6084         }
6085
6086         tg3_phy_stop(tp);
6087
6088         tg3_netif_stop(tp);
6089
6090         tg3_full_lock(tp, 1);
6091
6092         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6093
6094         tg3_set_mtu(dev, tp, new_mtu);
6095
6096         err = tg3_restart_hw(tp, 0);
6097
6098         if (!err)
6099                 tg3_netif_start(tp);
6100
6101         tg3_full_unlock(tp);
6102
6103         if (!err)
6104                 tg3_phy_start(tp);
6105
6106         return err;
6107 }
6108
6109 static void tg3_rx_prodring_free(struct tg3 *tp,
6110                                  struct tg3_rx_prodring_set *tpr)
6111 {
6112         int i;
6113
6114         if (tpr != &tp->napi[0].prodring) {
6115                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6116                      i = (i + 1) & tp->rx_std_ring_mask)
6117                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6118                                         tp->rx_pkt_map_sz);
6119
6120                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6121                         for (i = tpr->rx_jmb_cons_idx;
6122                              i != tpr->rx_jmb_prod_idx;
6123                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6124                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6125                                                 TG3_RX_JMB_MAP_SZ);
6126                         }
6127                 }
6128
6129                 return;
6130         }
6131
6132         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6133                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6134                                 tp->rx_pkt_map_sz);
6135
6136         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6137                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6138                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6139                                         TG3_RX_JMB_MAP_SZ);
6140         }
6141 }
6142
6143 /* Initialize rx rings for packet processing.
6144  *
6145  * The chip has been shut down and the driver detached from
6146  * the networking, so no interrupts or new tx packets will
6147  * end up in the driver.  tp->{tx,}lock are held and thus
6148  * we may not sleep.
6149  */
6150 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6151                                  struct tg3_rx_prodring_set *tpr)
6152 {
6153         u32 i, rx_pkt_dma_sz;
6154
6155         tpr->rx_std_cons_idx = 0;
6156         tpr->rx_std_prod_idx = 0;
6157         tpr->rx_jmb_cons_idx = 0;
6158         tpr->rx_jmb_prod_idx = 0;
6159
6160         if (tpr != &tp->napi[0].prodring) {
6161                 memset(&tpr->rx_std_buffers[0], 0,
6162                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6163                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6164                         memset(&tpr->rx_jmb_buffers[0], 0,
6165                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6166                 goto done;
6167         }
6168
6169         /* Zero out all descriptors. */
6170         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6171
6172         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6173         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6174             tp->dev->mtu > ETH_DATA_LEN)
6175                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6176         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6177
6178         /* Initialize invariants of the rings, we only set this
6179          * stuff once.  This works because the card does not
6180          * write into the rx buffer posting rings.
6181          */
6182         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6183                 struct tg3_rx_buffer_desc *rxd;
6184
6185                 rxd = &tpr->rx_std[i];
6186                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6187                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6188                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6189                                (i << RXD_OPAQUE_INDEX_SHIFT));
6190         }
6191
6192         /* Now allocate fresh SKBs for each rx ring. */
6193         for (i = 0; i < tp->rx_pending; i++) {
6194                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6195                         netdev_warn(tp->dev,
6196                                     "Using a smaller RX standard ring. Only "
6197                                     "%d out of %d buffers were allocated "
6198                                     "successfully\n", i, tp->rx_pending);
6199                         if (i == 0)
6200                                 goto initfail;
6201                         tp->rx_pending = i;
6202                         break;
6203                 }
6204         }
6205
6206         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6207                 goto done;
6208
6209         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6210
6211         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6212                 goto done;
6213
6214         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6215                 struct tg3_rx_buffer_desc *rxd;
6216
6217                 rxd = &tpr->rx_jmb[i].std;
6218                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6219                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6220                                   RXD_FLAG_JUMBO;
6221                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6222                        (i << RXD_OPAQUE_INDEX_SHIFT));
6223         }
6224
6225         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6226                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6227                         netdev_warn(tp->dev,
6228                                     "Using a smaller RX jumbo ring. Only %d "
6229                                     "out of %d buffers were allocated "
6230                                     "successfully\n", i, tp->rx_jumbo_pending);
6231                         if (i == 0)
6232                                 goto initfail;
6233                         tp->rx_jumbo_pending = i;
6234                         break;
6235                 }
6236         }
6237
6238 done:
6239         return 0;
6240
6241 initfail:
6242         tg3_rx_prodring_free(tp, tpr);
6243         return -ENOMEM;
6244 }
6245
6246 static void tg3_rx_prodring_fini(struct tg3 *tp,
6247                                  struct tg3_rx_prodring_set *tpr)
6248 {
6249         kfree(tpr->rx_std_buffers);
6250         tpr->rx_std_buffers = NULL;
6251         kfree(tpr->rx_jmb_buffers);
6252         tpr->rx_jmb_buffers = NULL;
6253         if (tpr->rx_std) {
6254                 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6255                                     tpr->rx_std, tpr->rx_std_mapping);
6256                 tpr->rx_std = NULL;
6257         }
6258         if (tpr->rx_jmb) {
6259                 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6260                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6261                 tpr->rx_jmb = NULL;
6262         }
6263 }
6264
6265 static int tg3_rx_prodring_init(struct tg3 *tp,
6266                                 struct tg3_rx_prodring_set *tpr)
6267 {
6268         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6269                                       GFP_KERNEL);
6270         if (!tpr->rx_std_buffers)
6271                 return -ENOMEM;
6272
6273         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6274                                            &tpr->rx_std_mapping);
6275         if (!tpr->rx_std)
6276                 goto err_out;
6277
6278         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6279                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6280                                               GFP_KERNEL);
6281                 if (!tpr->rx_jmb_buffers)
6282                         goto err_out;
6283
6284                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6285                                                    TG3_RX_JMB_RING_BYTES(tp),
6286                                                    &tpr->rx_jmb_mapping);
6287                 if (!tpr->rx_jmb)
6288                         goto err_out;
6289         }
6290
6291         return 0;
6292
6293 err_out:
6294         tg3_rx_prodring_fini(tp, tpr);
6295         return -ENOMEM;
6296 }
6297
6298 /* Free up pending packets in all rx/tx rings.
6299  *
6300  * The chip has been shut down and the driver detached from
6301  * the networking, so no interrupts or new tx packets will
6302  * end up in the driver.  tp->{tx,}lock is not held and we are not
6303  * in an interrupt context and thus may sleep.
6304  */
6305 static void tg3_free_rings(struct tg3 *tp)
6306 {
6307         int i, j;
6308
6309         for (j = 0; j < tp->irq_cnt; j++) {
6310                 struct tg3_napi *tnapi = &tp->napi[j];
6311
6312                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6313
6314                 if (!tnapi->tx_buffers)
6315                         continue;
6316
6317                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6318                         struct ring_info *txp;
6319                         struct sk_buff *skb;
6320                         unsigned int k;
6321
6322                         txp = &tnapi->tx_buffers[i];
6323                         skb = txp->skb;
6324
6325                         if (skb == NULL) {
6326                                 i++;
6327                                 continue;
6328                         }
6329
6330                         pci_unmap_single(tp->pdev,
6331                                          dma_unmap_addr(txp, mapping),
6332                                          skb_headlen(skb),
6333                                          PCI_DMA_TODEVICE);
6334                         txp->skb = NULL;
6335
6336                         i++;
6337
6338                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6339                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6340                                 pci_unmap_page(tp->pdev,
6341                                                dma_unmap_addr(txp, mapping),
6342                                                skb_shinfo(skb)->frags[k].size,
6343                                                PCI_DMA_TODEVICE);
6344                                 i++;
6345                         }
6346
6347                         dev_kfree_skb_any(skb);
6348                 }
6349         }
6350 }
6351
6352 /* Initialize tx/rx rings for packet processing.
6353  *
6354  * The chip has been shut down and the driver detached from
6355  * the networking, so no interrupts or new tx packets will
6356  * end up in the driver.  tp->{tx,}lock are held and thus
6357  * we may not sleep.
6358  */
6359 static int tg3_init_rings(struct tg3 *tp)
6360 {
6361         int i;
6362
6363         /* Free up all the SKBs. */
6364         tg3_free_rings(tp);
6365
6366         for (i = 0; i < tp->irq_cnt; i++) {
6367                 struct tg3_napi *tnapi = &tp->napi[i];
6368
6369                 tnapi->last_tag = 0;
6370                 tnapi->last_irq_tag = 0;
6371                 tnapi->hw_status->status = 0;
6372                 tnapi->hw_status->status_tag = 0;
6373                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6374
6375                 tnapi->tx_prod = 0;
6376                 tnapi->tx_cons = 0;
6377                 if (tnapi->tx_ring)
6378                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6379
6380                 tnapi->rx_rcb_ptr = 0;
6381                 if (tnapi->rx_rcb)
6382                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6383
6384                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6385                         tg3_free_rings(tp);
6386                         return -ENOMEM;
6387                 }
6388         }
6389
6390         return 0;
6391 }
6392
6393 /*
6394  * Must not be invoked with interrupt sources disabled and
6395  * the hardware shutdown down.
6396  */
6397 static void tg3_free_consistent(struct tg3 *tp)
6398 {
6399         int i;
6400
6401         for (i = 0; i < tp->irq_cnt; i++) {
6402                 struct tg3_napi *tnapi = &tp->napi[i];
6403
6404                 if (tnapi->tx_ring) {
6405                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6406                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6407                         tnapi->tx_ring = NULL;
6408                 }
6409
6410                 kfree(tnapi->tx_buffers);
6411                 tnapi->tx_buffers = NULL;
6412
6413                 if (tnapi->rx_rcb) {
6414                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6415                                             tnapi->rx_rcb,
6416                                             tnapi->rx_rcb_mapping);
6417                         tnapi->rx_rcb = NULL;
6418                 }
6419
6420                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6421
6422                 if (tnapi->hw_status) {
6423                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6424                                             tnapi->hw_status,
6425                                             tnapi->status_mapping);
6426                         tnapi->hw_status = NULL;
6427                 }
6428         }
6429
6430         if (tp->hw_stats) {
6431                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6432                                     tp->hw_stats, tp->stats_mapping);
6433                 tp->hw_stats = NULL;
6434         }
6435 }
6436
6437 /*
6438  * Must not be invoked with interrupt sources disabled and
6439  * the hardware shutdown down.  Can sleep.
6440  */
6441 static int tg3_alloc_consistent(struct tg3 *tp)
6442 {
6443         int i;
6444
6445         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6446                                             sizeof(struct tg3_hw_stats),
6447                                             &tp->stats_mapping);
6448         if (!tp->hw_stats)
6449                 goto err_out;
6450
6451         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6452
6453         for (i = 0; i < tp->irq_cnt; i++) {
6454                 struct tg3_napi *tnapi = &tp->napi[i];
6455                 struct tg3_hw_status *sblk;
6456
6457                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6458                                                         TG3_HW_STATUS_SIZE,
6459                                                         &tnapi->status_mapping);
6460                 if (!tnapi->hw_status)
6461                         goto err_out;
6462
6463                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6464                 sblk = tnapi->hw_status;
6465
6466                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6467                         goto err_out;
6468
6469                 /* If multivector TSS is enabled, vector 0 does not handle
6470                  * tx interrupts.  Don't allocate any resources for it.
6471                  */
6472                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6473                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6474                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6475                                                     TG3_TX_RING_SIZE,
6476                                                     GFP_KERNEL);
6477                         if (!tnapi->tx_buffers)
6478                                 goto err_out;
6479
6480                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6481                                                               TG3_TX_RING_BYTES,
6482                                                        &tnapi->tx_desc_mapping);
6483                         if (!tnapi->tx_ring)
6484                                 goto err_out;
6485                 }
6486
6487                 /*
6488                  * When RSS is enabled, the status block format changes
6489                  * slightly.  The "rx_jumbo_consumer", "reserved",
6490                  * and "rx_mini_consumer" members get mapped to the
6491                  * other three rx return ring producer indexes.
6492                  */
6493                 switch (i) {
6494                 default:
6495                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6496                         break;
6497                 case 2:
6498                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6499                         break;
6500                 case 3:
6501                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6502                         break;
6503                 case 4:
6504                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6505                         break;
6506                 }
6507
6508                 /*
6509                  * If multivector RSS is enabled, vector 0 does not handle
6510                  * rx or tx interrupts.  Don't allocate any resources for it.
6511                  */
6512                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6513                         continue;
6514
6515                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6516                                                      TG3_RX_RCB_RING_BYTES(tp),
6517                                                      &tnapi->rx_rcb_mapping);
6518                 if (!tnapi->rx_rcb)
6519                         goto err_out;
6520
6521                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6522         }
6523
6524         return 0;
6525
6526 err_out:
6527         tg3_free_consistent(tp);
6528         return -ENOMEM;
6529 }
6530
6531 #define MAX_WAIT_CNT 1000
6532
6533 /* To stop a block, clear the enable bit and poll till it
6534  * clears.  tp->lock is held.
6535  */
6536 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6537 {
6538         unsigned int i;
6539         u32 val;
6540
6541         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6542                 switch (ofs) {
6543                 case RCVLSC_MODE:
6544                 case DMAC_MODE:
6545                 case MBFREE_MODE:
6546                 case BUFMGR_MODE:
6547                 case MEMARB_MODE:
6548                         /* We can't enable/disable these bits of the
6549                          * 5705/5750, just say success.
6550                          */
6551                         return 0;
6552
6553                 default:
6554                         break;
6555                 }
6556         }
6557
6558         val = tr32(ofs);
6559         val &= ~enable_bit;
6560         tw32_f(ofs, val);
6561
6562         for (i = 0; i < MAX_WAIT_CNT; i++) {
6563                 udelay(100);
6564                 val = tr32(ofs);
6565                 if ((val & enable_bit) == 0)
6566                         break;
6567         }
6568
6569         if (i == MAX_WAIT_CNT && !silent) {
6570                 dev_err(&tp->pdev->dev,
6571                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6572                         ofs, enable_bit);
6573                 return -ENODEV;
6574         }
6575
6576         return 0;
6577 }
6578
6579 /* tp->lock is held. */
6580 static int tg3_abort_hw(struct tg3 *tp, int silent)
6581 {
6582         int i, err;
6583
6584         tg3_disable_ints(tp);
6585
6586         tp->rx_mode &= ~RX_MODE_ENABLE;
6587         tw32_f(MAC_RX_MODE, tp->rx_mode);
6588         udelay(10);
6589
6590         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6591         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6592         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6593         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6594         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6595         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6596
6597         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6598         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6599         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6600         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6601         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6602         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6603         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6604
6605         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6606         tw32_f(MAC_MODE, tp->mac_mode);
6607         udelay(40);
6608
6609         tp->tx_mode &= ~TX_MODE_ENABLE;
6610         tw32_f(MAC_TX_MODE, tp->tx_mode);
6611
6612         for (i = 0; i < MAX_WAIT_CNT; i++) {
6613                 udelay(100);
6614                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6615                         break;
6616         }
6617         if (i >= MAX_WAIT_CNT) {
6618                 dev_err(&tp->pdev->dev,
6619                         "%s timed out, TX_MODE_ENABLE will not clear "
6620                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6621                 err |= -ENODEV;
6622         }
6623
6624         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6625         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6626         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6627
6628         tw32(FTQ_RESET, 0xffffffff);
6629         tw32(FTQ_RESET, 0x00000000);
6630
6631         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6632         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6633
6634         for (i = 0; i < tp->irq_cnt; i++) {
6635                 struct tg3_napi *tnapi = &tp->napi[i];
6636                 if (tnapi->hw_status)
6637                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6638         }
6639         if (tp->hw_stats)
6640                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6641
6642         return err;
6643 }
6644
6645 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6646 {
6647         int i;
6648         u32 apedata;
6649
6650         /* NCSI does not support APE events */
6651         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6652                 return;
6653
6654         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6655         if (apedata != APE_SEG_SIG_MAGIC)
6656                 return;
6657
6658         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6659         if (!(apedata & APE_FW_STATUS_READY))
6660                 return;
6661
6662         /* Wait for up to 1 millisecond for APE to service previous event. */
6663         for (i = 0; i < 10; i++) {
6664                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6665                         return;
6666
6667                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6668
6669                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6670                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6671                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6672
6673                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6674
6675                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6676                         break;
6677
6678                 udelay(100);
6679         }
6680
6681         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6682                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6683 }
6684
6685 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6686 {
6687         u32 event;
6688         u32 apedata;
6689
6690         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6691                 return;
6692
6693         switch (kind) {
6694         case RESET_KIND_INIT:
6695                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6696                                 APE_HOST_SEG_SIG_MAGIC);
6697                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6698                                 APE_HOST_SEG_LEN_MAGIC);
6699                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6700                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6701                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6702                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6703                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6704                                 APE_HOST_BEHAV_NO_PHYLOCK);
6705                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6706                                     TG3_APE_HOST_DRVR_STATE_START);
6707
6708                 event = APE_EVENT_STATUS_STATE_START;
6709                 break;
6710         case RESET_KIND_SHUTDOWN:
6711                 /* With the interface we are currently using,
6712                  * APE does not track driver state.  Wiping
6713                  * out the HOST SEGMENT SIGNATURE forces
6714                  * the APE to assume OS absent status.
6715                  */
6716                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6717
6718                 if (device_may_wakeup(&tp->pdev->dev) &&
6719                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6720                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6721                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6722                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6723                 } else
6724                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6725
6726                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6727
6728                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6729                 break;
6730         case RESET_KIND_SUSPEND:
6731                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6732                 break;
6733         default:
6734                 return;
6735         }
6736
6737         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6738
6739         tg3_ape_send_event(tp, event);
6740 }
6741
6742 /* tp->lock is held. */
6743 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6744 {
6745         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6746                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6747
6748         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6749                 switch (kind) {
6750                 case RESET_KIND_INIT:
6751                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6752                                       DRV_STATE_START);
6753                         break;
6754
6755                 case RESET_KIND_SHUTDOWN:
6756                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6757                                       DRV_STATE_UNLOAD);
6758                         break;
6759
6760                 case RESET_KIND_SUSPEND:
6761                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6762                                       DRV_STATE_SUSPEND);
6763                         break;
6764
6765                 default:
6766                         break;
6767                 }
6768         }
6769
6770         if (kind == RESET_KIND_INIT ||
6771             kind == RESET_KIND_SUSPEND)
6772                 tg3_ape_driver_state_change(tp, kind);
6773 }
6774
6775 /* tp->lock is held. */
6776 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6777 {
6778         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6779                 switch (kind) {
6780                 case RESET_KIND_INIT:
6781                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6782                                       DRV_STATE_START_DONE);
6783                         break;
6784
6785                 case RESET_KIND_SHUTDOWN:
6786                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6787                                       DRV_STATE_UNLOAD_DONE);
6788                         break;
6789
6790                 default:
6791                         break;
6792                 }
6793         }
6794
6795         if (kind == RESET_KIND_SHUTDOWN)
6796                 tg3_ape_driver_state_change(tp, kind);
6797 }
6798
6799 /* tp->lock is held. */
6800 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6801 {
6802         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6803                 switch (kind) {
6804                 case RESET_KIND_INIT:
6805                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6806                                       DRV_STATE_START);
6807                         break;
6808
6809                 case RESET_KIND_SHUTDOWN:
6810                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6811                                       DRV_STATE_UNLOAD);
6812                         break;
6813
6814                 case RESET_KIND_SUSPEND:
6815                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6816                                       DRV_STATE_SUSPEND);
6817                         break;
6818
6819                 default:
6820                         break;
6821                 }
6822         }
6823 }
6824
6825 static int tg3_poll_fw(struct tg3 *tp)
6826 {
6827         int i;
6828         u32 val;
6829
6830         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6831                 /* Wait up to 20ms for init done. */
6832                 for (i = 0; i < 200; i++) {
6833                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6834                                 return 0;
6835                         udelay(100);
6836                 }
6837                 return -ENODEV;
6838         }
6839
6840         /* Wait for firmware initialization to complete. */
6841         for (i = 0; i < 100000; i++) {
6842                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6843                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6844                         break;
6845                 udelay(10);
6846         }
6847
6848         /* Chip might not be fitted with firmware.  Some Sun onboard
6849          * parts are configured like that.  So don't signal the timeout
6850          * of the above loop as an error, but do report the lack of
6851          * running firmware once.
6852          */
6853         if (i >= 100000 &&
6854             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6855                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6856
6857                 netdev_info(tp->dev, "No firmware running\n");
6858         }
6859
6860         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6861                 /* The 57765 A0 needs a little more
6862                  * time to do some important work.
6863                  */
6864                 mdelay(10);
6865         }
6866
6867         return 0;
6868 }
6869
6870 /* Save PCI command register before chip reset */
6871 static void tg3_save_pci_state(struct tg3 *tp)
6872 {
6873         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6874 }
6875
6876 /* Restore PCI state after chip reset */
6877 static void tg3_restore_pci_state(struct tg3 *tp)
6878 {
6879         u32 val;
6880
6881         /* Re-enable indirect register accesses. */
6882         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6883                                tp->misc_host_ctrl);
6884
6885         /* Set MAX PCI retry to zero. */
6886         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6887         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6888             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6889                 val |= PCISTATE_RETRY_SAME_DMA;
6890         /* Allow reads and writes to the APE register and memory space. */
6891         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6892                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6893                        PCISTATE_ALLOW_APE_SHMEM_WR |
6894                        PCISTATE_ALLOW_APE_PSPACE_WR;
6895         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6896
6897         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6898
6899         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6900                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6901                         pcie_set_readrq(tp->pdev, 4096);
6902                 else {
6903                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6904                                               tp->pci_cacheline_sz);
6905                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6906                                               tp->pci_lat_timer);
6907                 }
6908         }
6909
6910         /* Make sure PCI-X relaxed ordering bit is clear. */
6911         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6912                 u16 pcix_cmd;
6913
6914                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6915                                      &pcix_cmd);
6916                 pcix_cmd &= ~PCI_X_CMD_ERO;
6917                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6918                                       pcix_cmd);
6919         }
6920
6921         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6922
6923                 /* Chip reset on 5780 will reset MSI enable bit,
6924                  * so need to restore it.
6925                  */
6926                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6927                         u16 ctrl;
6928
6929                         pci_read_config_word(tp->pdev,
6930                                              tp->msi_cap + PCI_MSI_FLAGS,
6931                                              &ctrl);
6932                         pci_write_config_word(tp->pdev,
6933                                               tp->msi_cap + PCI_MSI_FLAGS,
6934                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6935                         val = tr32(MSGINT_MODE);
6936                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6937                 }
6938         }
6939 }
6940
6941 static void tg3_stop_fw(struct tg3 *);
6942
6943 /* tp->lock is held. */
6944 static int tg3_chip_reset(struct tg3 *tp)
6945 {
6946         u32 val;
6947         void (*write_op)(struct tg3 *, u32, u32);
6948         int i, err;
6949
6950         tg3_nvram_lock(tp);
6951
6952         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6953
6954         /* No matching tg3_nvram_unlock() after this because
6955          * chip reset below will undo the nvram lock.
6956          */
6957         tp->nvram_lock_cnt = 0;
6958
6959         /* GRC_MISC_CFG core clock reset will clear the memory
6960          * enable bit in PCI register 4 and the MSI enable bit
6961          * on some chips, so we save relevant registers here.
6962          */
6963         tg3_save_pci_state(tp);
6964
6965         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6966             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6967                 tw32(GRC_FASTBOOT_PC, 0);
6968
6969         /*
6970          * We must avoid the readl() that normally takes place.
6971          * It locks machines, causes machine checks, and other
6972          * fun things.  So, temporarily disable the 5701
6973          * hardware workaround, while we do the reset.
6974          */
6975         write_op = tp->write32;
6976         if (write_op == tg3_write_flush_reg32)
6977                 tp->write32 = tg3_write32;
6978
6979         /* Prevent the irq handler from reading or writing PCI registers
6980          * during chip reset when the memory enable bit in the PCI command
6981          * register may be cleared.  The chip does not generate interrupt
6982          * at this time, but the irq handler may still be called due to irq
6983          * sharing or irqpoll.
6984          */
6985         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6986         for (i = 0; i < tp->irq_cnt; i++) {
6987                 struct tg3_napi *tnapi = &tp->napi[i];
6988                 if (tnapi->hw_status) {
6989                         tnapi->hw_status->status = 0;
6990                         tnapi->hw_status->status_tag = 0;
6991                 }
6992                 tnapi->last_tag = 0;
6993                 tnapi->last_irq_tag = 0;
6994         }
6995         smp_mb();
6996
6997         for (i = 0; i < tp->irq_cnt; i++)
6998                 synchronize_irq(tp->napi[i].irq_vec);
6999
7000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7001                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7002                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7003         }
7004
7005         /* do the reset */
7006         val = GRC_MISC_CFG_CORECLK_RESET;
7007
7008         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7009                 /* Force PCIe 1.0a mode */
7010                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7011                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7012                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7013                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7014                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7015
7016                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7017                         tw32(GRC_MISC_CFG, (1 << 29));
7018                         val |= (1 << 29);
7019                 }
7020         }
7021
7022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7023                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7024                 tw32(GRC_VCPU_EXT_CTRL,
7025                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7026         }
7027
7028         /* Manage gphy power for all CPMU absent PCIe devices. */
7029         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7030             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7031                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7032
7033         tw32(GRC_MISC_CFG, val);
7034
7035         /* restore 5701 hardware bug workaround write method */
7036         tp->write32 = write_op;
7037
7038         /* Unfortunately, we have to delay before the PCI read back.
7039          * Some 575X chips even will not respond to a PCI cfg access
7040          * when the reset command is given to the chip.
7041          *
7042          * How do these hardware designers expect things to work
7043          * properly if the PCI write is posted for a long period
7044          * of time?  It is always necessary to have some method by
7045          * which a register read back can occur to push the write
7046          * out which does the reset.
7047          *
7048          * For most tg3 variants the trick below was working.
7049          * Ho hum...
7050          */
7051         udelay(120);
7052
7053         /* Flush PCI posted writes.  The normal MMIO registers
7054          * are inaccessible at this time so this is the only
7055          * way to make this reliably (actually, this is no longer
7056          * the case, see above).  I tried to use indirect
7057          * register read/write but this upset some 5701 variants.
7058          */
7059         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7060
7061         udelay(120);
7062
7063         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7064                 u16 val16;
7065
7066                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7067                         int i;
7068                         u32 cfg_val;
7069
7070                         /* Wait for link training to complete.  */
7071                         for (i = 0; i < 5000; i++)
7072                                 udelay(100);
7073
7074                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7075                         pci_write_config_dword(tp->pdev, 0xc4,
7076                                                cfg_val | (1 << 15));
7077                 }
7078
7079                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7080                 pci_read_config_word(tp->pdev,
7081                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7082                                      &val16);
7083                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7084                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7085                 /*
7086                  * Older PCIe devices only support the 128 byte
7087                  * MPS setting.  Enforce the restriction.
7088                  */
7089                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7090                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7091                 pci_write_config_word(tp->pdev,
7092                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7093                                       val16);
7094
7095                 pcie_set_readrq(tp->pdev, 4096);
7096
7097                 /* Clear error status */
7098                 pci_write_config_word(tp->pdev,
7099                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7100                                       PCI_EXP_DEVSTA_CED |
7101                                       PCI_EXP_DEVSTA_NFED |
7102                                       PCI_EXP_DEVSTA_FED |
7103                                       PCI_EXP_DEVSTA_URD);
7104         }
7105
7106         tg3_restore_pci_state(tp);
7107
7108         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7109
7110         val = 0;
7111         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7112                 val = tr32(MEMARB_MODE);
7113         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7114
7115         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7116                 tg3_stop_fw(tp);
7117                 tw32(0x5000, 0x400);
7118         }
7119
7120         tw32(GRC_MODE, tp->grc_mode);
7121
7122         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7123                 val = tr32(0xc4);
7124
7125                 tw32(0xc4, val | (1 << 15));
7126         }
7127
7128         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7129             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7130                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7131                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7132                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7133                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7134         }
7135
7136         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7137                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7138                 tw32_f(MAC_MODE, tp->mac_mode);
7139         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7140                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7141                 tw32_f(MAC_MODE, tp->mac_mode);
7142         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7143                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7144                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7145                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7146                 tw32_f(MAC_MODE, tp->mac_mode);
7147         } else
7148                 tw32_f(MAC_MODE, 0);
7149         udelay(40);
7150
7151         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7152
7153         err = tg3_poll_fw(tp);
7154         if (err)
7155                 return err;
7156
7157         tg3_mdio_start(tp);
7158
7159         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7160             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7161             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7162             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7163                 val = tr32(0x7c00);
7164
7165                 tw32(0x7c00, val | (1 << 25));
7166         }
7167
7168         /* Reprobe ASF enable state.  */
7169         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7170         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7171         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7172         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7173                 u32 nic_cfg;
7174
7175                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7176                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7177                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7178                         tp->last_event_jiffies = jiffies;
7179                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7180                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7181                 }
7182         }
7183
7184         return 0;
7185 }
7186
7187 /* tp->lock is held. */
7188 static void tg3_stop_fw(struct tg3 *tp)
7189 {
7190         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7191            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7192                 /* Wait for RX cpu to ACK the previous event. */
7193                 tg3_wait_for_event_ack(tp);
7194
7195                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7196
7197                 tg3_generate_fw_event(tp);
7198
7199                 /* Wait for RX cpu to ACK this event. */
7200                 tg3_wait_for_event_ack(tp);
7201         }
7202 }
7203
7204 /* tp->lock is held. */
7205 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7206 {
7207         int err;
7208
7209         tg3_stop_fw(tp);
7210
7211         tg3_write_sig_pre_reset(tp, kind);
7212
7213         tg3_abort_hw(tp, silent);
7214         err = tg3_chip_reset(tp);
7215
7216         __tg3_set_mac_addr(tp, 0);
7217
7218         tg3_write_sig_legacy(tp, kind);
7219         tg3_write_sig_post_reset(tp, kind);
7220
7221         if (err)
7222                 return err;
7223
7224         return 0;
7225 }
7226
7227 #define RX_CPU_SCRATCH_BASE     0x30000
7228 #define RX_CPU_SCRATCH_SIZE     0x04000
7229 #define TX_CPU_SCRATCH_BASE     0x34000
7230 #define TX_CPU_SCRATCH_SIZE     0x04000
7231
7232 /* tp->lock is held. */
7233 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7234 {
7235         int i;
7236
7237         BUG_ON(offset == TX_CPU_BASE &&
7238             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7239
7240         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7241                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7242
7243                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7244                 return 0;
7245         }
7246         if (offset == RX_CPU_BASE) {
7247                 for (i = 0; i < 10000; i++) {
7248                         tw32(offset + CPU_STATE, 0xffffffff);
7249                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7250                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7251                                 break;
7252                 }
7253
7254                 tw32(offset + CPU_STATE, 0xffffffff);
7255                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7256                 udelay(10);
7257         } else {
7258                 for (i = 0; i < 10000; i++) {
7259                         tw32(offset + CPU_STATE, 0xffffffff);
7260                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7261                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7262                                 break;
7263                 }
7264         }
7265
7266         if (i >= 10000) {
7267                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7268                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7269                 return -ENODEV;
7270         }
7271
7272         /* Clear firmware's nvram arbitration. */
7273         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7274                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7275         return 0;
7276 }
7277
7278 struct fw_info {
7279         unsigned int fw_base;
7280         unsigned int fw_len;
7281         const __be32 *fw_data;
7282 };
7283
7284 /* tp->lock is held. */
7285 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7286                                  int cpu_scratch_size, struct fw_info *info)
7287 {
7288         int err, lock_err, i;
7289         void (*write_op)(struct tg3 *, u32, u32);
7290
7291         if (cpu_base == TX_CPU_BASE &&
7292             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7293                 netdev_err(tp->dev,
7294                            "%s: Trying to load TX cpu firmware which is 5705\n",
7295                            __func__);
7296                 return -EINVAL;
7297         }
7298
7299         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7300                 write_op = tg3_write_mem;
7301         else
7302                 write_op = tg3_write_indirect_reg32;
7303
7304         /* It is possible that bootcode is still loading at this point.
7305          * Get the nvram lock first before halting the cpu.
7306          */
7307         lock_err = tg3_nvram_lock(tp);
7308         err = tg3_halt_cpu(tp, cpu_base);
7309         if (!lock_err)
7310                 tg3_nvram_unlock(tp);
7311         if (err)
7312                 goto out;
7313
7314         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7315                 write_op(tp, cpu_scratch_base + i, 0);
7316         tw32(cpu_base + CPU_STATE, 0xffffffff);
7317         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7318         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7319                 write_op(tp, (cpu_scratch_base +
7320                               (info->fw_base & 0xffff) +
7321                               (i * sizeof(u32))),
7322                               be32_to_cpu(info->fw_data[i]));
7323
7324         err = 0;
7325
7326 out:
7327         return err;
7328 }
7329
7330 /* tp->lock is held. */
7331 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7332 {
7333         struct fw_info info;
7334         const __be32 *fw_data;
7335         int err, i;
7336
7337         fw_data = (void *)tp->fw->data;
7338
7339         /* Firmware blob starts with version numbers, followed by
7340            start address and length. We are setting complete length.
7341            length = end_address_of_bss - start_address_of_text.
7342            Remainder is the blob to be loaded contiguously
7343            from start address. */
7344
7345         info.fw_base = be32_to_cpu(fw_data[1]);
7346         info.fw_len = tp->fw->size - 12;
7347         info.fw_data = &fw_data[3];
7348
7349         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7350                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7351                                     &info);
7352         if (err)
7353                 return err;
7354
7355         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7356                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7357                                     &info);
7358         if (err)
7359                 return err;
7360
7361         /* Now startup only the RX cpu. */
7362         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7363         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7364
7365         for (i = 0; i < 5; i++) {
7366                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7367                         break;
7368                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7369                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7370                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7371                 udelay(1000);
7372         }
7373         if (i >= 5) {
7374                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7375                            "should be %08x\n", __func__,
7376                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7377                 return -ENODEV;
7378         }
7379         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7380         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7381
7382         return 0;
7383 }
7384
7385 /* 5705 needs a special version of the TSO firmware.  */
7386
7387 /* tp->lock is held. */
7388 static int tg3_load_tso_firmware(struct tg3 *tp)
7389 {
7390         struct fw_info info;
7391         const __be32 *fw_data;
7392         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7393         int err, i;
7394
7395         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7396                 return 0;
7397
7398         fw_data = (void *)tp->fw->data;
7399
7400         /* Firmware blob starts with version numbers, followed by
7401            start address and length. We are setting complete length.
7402            length = end_address_of_bss - start_address_of_text.
7403            Remainder is the blob to be loaded contiguously
7404            from start address. */
7405
7406         info.fw_base = be32_to_cpu(fw_data[1]);
7407         cpu_scratch_size = tp->fw_len;
7408         info.fw_len = tp->fw->size - 12;
7409         info.fw_data = &fw_data[3];
7410
7411         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7412                 cpu_base = RX_CPU_BASE;
7413                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7414         } else {
7415                 cpu_base = TX_CPU_BASE;
7416                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7417                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7418         }
7419
7420         err = tg3_load_firmware_cpu(tp, cpu_base,
7421                                     cpu_scratch_base, cpu_scratch_size,
7422                                     &info);
7423         if (err)
7424                 return err;
7425
7426         /* Now startup the cpu. */
7427         tw32(cpu_base + CPU_STATE, 0xffffffff);
7428         tw32_f(cpu_base + CPU_PC, info.fw_base);
7429
7430         for (i = 0; i < 5; i++) {
7431                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7432                         break;
7433                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7434                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7435                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7436                 udelay(1000);
7437         }
7438         if (i >= 5) {
7439                 netdev_err(tp->dev,
7440                            "%s fails to set CPU PC, is %08x should be %08x\n",
7441                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7442                 return -ENODEV;
7443         }
7444         tw32(cpu_base + CPU_STATE, 0xffffffff);
7445         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7446         return 0;
7447 }
7448
7449
7450 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7451 {
7452         struct tg3 *tp = netdev_priv(dev);
7453         struct sockaddr *addr = p;
7454         int err = 0, skip_mac_1 = 0;
7455
7456         if (!is_valid_ether_addr(addr->sa_data))
7457                 return -EINVAL;
7458
7459         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7460
7461         if (!netif_running(dev))
7462                 return 0;
7463
7464         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7465                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7466
7467                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7468                 addr0_low = tr32(MAC_ADDR_0_LOW);
7469                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7470                 addr1_low = tr32(MAC_ADDR_1_LOW);
7471
7472                 /* Skip MAC addr 1 if ASF is using it. */
7473                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7474                     !(addr1_high == 0 && addr1_low == 0))
7475                         skip_mac_1 = 1;
7476         }
7477         spin_lock_bh(&tp->lock);
7478         __tg3_set_mac_addr(tp, skip_mac_1);
7479         spin_unlock_bh(&tp->lock);
7480
7481         return err;
7482 }
7483
7484 /* tp->lock is held. */
7485 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7486                            dma_addr_t mapping, u32 maxlen_flags,
7487                            u32 nic_addr)
7488 {
7489         tg3_write_mem(tp,
7490                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7491                       ((u64) mapping >> 32));
7492         tg3_write_mem(tp,
7493                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7494                       ((u64) mapping & 0xffffffff));
7495         tg3_write_mem(tp,
7496                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7497                        maxlen_flags);
7498
7499         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7500                 tg3_write_mem(tp,
7501                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7502                               nic_addr);
7503 }
7504
7505 static void __tg3_set_rx_mode(struct net_device *);
7506 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7507 {
7508         int i;
7509
7510         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7511                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7512                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7513                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7514         } else {
7515                 tw32(HOSTCC_TXCOL_TICKS, 0);
7516                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7517                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7518         }
7519
7520         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7521                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7522                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7523                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7524         } else {
7525                 tw32(HOSTCC_RXCOL_TICKS, 0);
7526                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7527                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7528         }
7529
7530         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7531                 u32 val = ec->stats_block_coalesce_usecs;
7532
7533                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7534                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7535
7536                 if (!netif_carrier_ok(tp->dev))
7537                         val = 0;
7538
7539                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7540         }
7541
7542         for (i = 0; i < tp->irq_cnt - 1; i++) {
7543                 u32 reg;
7544
7545                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7546                 tw32(reg, ec->rx_coalesce_usecs);
7547                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7548                 tw32(reg, ec->rx_max_coalesced_frames);
7549                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7550                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7551
7552                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7553                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7554                         tw32(reg, ec->tx_coalesce_usecs);
7555                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7556                         tw32(reg, ec->tx_max_coalesced_frames);
7557                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7558                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7559                 }
7560         }
7561
7562         for (; i < tp->irq_max - 1; i++) {
7563                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7564                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7565                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7566
7567                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7568                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7569                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7570                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7571                 }
7572         }
7573 }
7574
7575 /* tp->lock is held. */
7576 static void tg3_rings_reset(struct tg3 *tp)
7577 {
7578         int i;
7579         u32 stblk, txrcb, rxrcb, limit;
7580         struct tg3_napi *tnapi = &tp->napi[0];
7581
7582         /* Disable all transmit rings but the first. */
7583         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7584                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7585         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7586                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7587                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7588         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7589                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7590         else
7591                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7592
7593         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7594              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7595                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7596                               BDINFO_FLAGS_DISABLED);
7597
7598
7599         /* Disable all receive return rings but the first. */
7600         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7601             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7602                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7603         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7604                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7605         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7606                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7607                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7608         else
7609                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7610
7611         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7612              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7613                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7614                               BDINFO_FLAGS_DISABLED);
7615
7616         /* Disable interrupts */
7617         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7618
7619         /* Zero mailbox registers. */
7620         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7621                 for (i = 1; i < tp->irq_max; i++) {
7622                         tp->napi[i].tx_prod = 0;
7623                         tp->napi[i].tx_cons = 0;
7624                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7625                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7626                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7627                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7628                 }
7629                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7630                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7631         } else {
7632                 tp->napi[0].tx_prod = 0;
7633                 tp->napi[0].tx_cons = 0;
7634                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7635                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7636         }
7637
7638         /* Make sure the NIC-based send BD rings are disabled. */
7639         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7640                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7641                 for (i = 0; i < 16; i++)
7642                         tw32_tx_mbox(mbox + i * 8, 0);
7643         }
7644
7645         txrcb = NIC_SRAM_SEND_RCB;
7646         rxrcb = NIC_SRAM_RCV_RET_RCB;
7647
7648         /* Clear status block in ram. */
7649         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7650
7651         /* Set status block DMA address */
7652         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7653              ((u64) tnapi->status_mapping >> 32));
7654         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7655              ((u64) tnapi->status_mapping & 0xffffffff));
7656
7657         if (tnapi->tx_ring) {
7658                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7659                                (TG3_TX_RING_SIZE <<
7660                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7661                                NIC_SRAM_TX_BUFFER_DESC);
7662                 txrcb += TG3_BDINFO_SIZE;
7663         }
7664
7665         if (tnapi->rx_rcb) {
7666                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7667                                (tp->rx_ret_ring_mask + 1) <<
7668                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7669                 rxrcb += TG3_BDINFO_SIZE;
7670         }
7671
7672         stblk = HOSTCC_STATBLCK_RING1;
7673
7674         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7675                 u64 mapping = (u64)tnapi->status_mapping;
7676                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7677                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7678
7679                 /* Clear status block in ram. */
7680                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7681
7682                 if (tnapi->tx_ring) {
7683                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7684                                        (TG3_TX_RING_SIZE <<
7685                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7686                                        NIC_SRAM_TX_BUFFER_DESC);
7687                         txrcb += TG3_BDINFO_SIZE;
7688                 }
7689
7690                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7691                                ((tp->rx_ret_ring_mask + 1) <<
7692                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7693
7694                 stblk += 8;
7695                 rxrcb += TG3_BDINFO_SIZE;
7696         }
7697 }
7698
7699 /* tp->lock is held. */
7700 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7701 {
7702         u32 val, rdmac_mode;
7703         int i, err, limit;
7704         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7705
7706         tg3_disable_ints(tp);
7707
7708         tg3_stop_fw(tp);
7709
7710         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7711
7712         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7713                 tg3_abort_hw(tp, 1);
7714
7715         if (reset_phy)
7716                 tg3_phy_reset(tp);
7717
7718         err = tg3_chip_reset(tp);
7719         if (err)
7720                 return err;
7721
7722         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7723
7724         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7725                 val = tr32(TG3_CPMU_CTRL);
7726                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7727                 tw32(TG3_CPMU_CTRL, val);
7728
7729                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7730                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7731                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7732                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7733
7734                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7735                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7736                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7737                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7738
7739                 val = tr32(TG3_CPMU_HST_ACC);
7740                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7741                 val |= CPMU_HST_ACC_MACCLK_6_25;
7742                 tw32(TG3_CPMU_HST_ACC, val);
7743         }
7744
7745         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7746                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7747                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7748                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7749                 tw32(PCIE_PWR_MGMT_THRESH, val);
7750
7751                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7752                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7753
7754                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7755
7756                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7757                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7758         }
7759
7760         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7761                 u32 grc_mode = tr32(GRC_MODE);
7762
7763                 /* Access the lower 1K of PL PCIE block registers. */
7764                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7765                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7766
7767                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7768                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7769                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7770
7771                 tw32(GRC_MODE, grc_mode);
7772         }
7773
7774         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7775                 u32 grc_mode = tr32(GRC_MODE);
7776
7777                 /* Access the lower 1K of PL PCIE block registers. */
7778                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7779                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7780
7781                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7782                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7783                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7784
7785                 tw32(GRC_MODE, grc_mode);
7786
7787                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7788                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7789                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7790                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7791         }
7792
7793         /* This works around an issue with Athlon chipsets on
7794          * B3 tigon3 silicon.  This bit has no effect on any
7795          * other revision.  But do not set this on PCI Express
7796          * chips and don't even touch the clocks if the CPMU is present.
7797          */
7798         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7799                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7800                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7801                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7802         }
7803
7804         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7805             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7806                 val = tr32(TG3PCI_PCISTATE);
7807                 val |= PCISTATE_RETRY_SAME_DMA;
7808                 tw32(TG3PCI_PCISTATE, val);
7809         }
7810
7811         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7812                 /* Allow reads and writes to the
7813                  * APE register and memory space.
7814                  */
7815                 val = tr32(TG3PCI_PCISTATE);
7816                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7817                        PCISTATE_ALLOW_APE_SHMEM_WR |
7818                        PCISTATE_ALLOW_APE_PSPACE_WR;
7819                 tw32(TG3PCI_PCISTATE, val);
7820         }
7821
7822         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7823                 /* Enable some hw fixes.  */
7824                 val = tr32(TG3PCI_MSI_DATA);
7825                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7826                 tw32(TG3PCI_MSI_DATA, val);
7827         }
7828
7829         /* Descriptor ring init may make accesses to the
7830          * NIC SRAM area to setup the TX descriptors, so we
7831          * can only do this after the hardware has been
7832          * successfully reset.
7833          */
7834         err = tg3_init_rings(tp);
7835         if (err)
7836                 return err;
7837
7838         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7839                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7840                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7841                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7842                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7843                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7844         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7845                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7846                 /* This value is determined during the probe time DMA
7847                  * engine test, tg3_test_dma.
7848                  */
7849                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7850         }
7851
7852         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7853                           GRC_MODE_4X_NIC_SEND_RINGS |
7854                           GRC_MODE_NO_TX_PHDR_CSUM |
7855                           GRC_MODE_NO_RX_PHDR_CSUM);
7856         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7857
7858         /* Pseudo-header checksum is done by hardware logic and not
7859          * the offload processers, so make the chip do the pseudo-
7860          * header checksums on receive.  For transmit it is more
7861          * convenient to do the pseudo-header checksum in software
7862          * as Linux does that on transmit for us in all cases.
7863          */
7864         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7865
7866         tw32(GRC_MODE,
7867              tp->grc_mode |
7868              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7869
7870         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7871         val = tr32(GRC_MISC_CFG);
7872         val &= ~0xff;
7873         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7874         tw32(GRC_MISC_CFG, val);
7875
7876         /* Initialize MBUF/DESC pool. */
7877         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7878                 /* Do nothing.  */
7879         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7880                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7881                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7882                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7883                 else
7884                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7885                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7886                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7887         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7888                 int fw_len;
7889
7890                 fw_len = tp->fw_len;
7891                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7892                 tw32(BUFMGR_MB_POOL_ADDR,
7893                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7894                 tw32(BUFMGR_MB_POOL_SIZE,
7895                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7896         }
7897
7898         if (tp->dev->mtu <= ETH_DATA_LEN) {
7899                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7900                      tp->bufmgr_config.mbuf_read_dma_low_water);
7901                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7902                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7903                 tw32(BUFMGR_MB_HIGH_WATER,
7904                      tp->bufmgr_config.mbuf_high_water);
7905         } else {
7906                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7907                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7908                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7909                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7910                 tw32(BUFMGR_MB_HIGH_WATER,
7911                      tp->bufmgr_config.mbuf_high_water_jumbo);
7912         }
7913         tw32(BUFMGR_DMA_LOW_WATER,
7914              tp->bufmgr_config.dma_low_water);
7915         tw32(BUFMGR_DMA_HIGH_WATER,
7916              tp->bufmgr_config.dma_high_water);
7917
7918         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
7919         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7920                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
7921         tw32(BUFMGR_MODE, val);
7922         for (i = 0; i < 2000; i++) {
7923                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7924                         break;
7925                 udelay(10);
7926         }
7927         if (i >= 2000) {
7928                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7929                 return -ENODEV;
7930         }
7931
7932         /* Setup replenish threshold. */
7933         val = tp->rx_pending / 8;
7934         if (val == 0)
7935                 val = 1;
7936         else if (val > tp->rx_std_max_post)
7937                 val = tp->rx_std_max_post;
7938         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7939                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7940                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7941
7942                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7943                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7944         }
7945
7946         tw32(RCVBDI_STD_THRESH, val);
7947
7948         /* Initialize TG3_BDINFO's at:
7949          *  RCVDBDI_STD_BD:     standard eth size rx ring
7950          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7951          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7952          *
7953          * like so:
7954          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7955          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7956          *                              ring attribute flags
7957          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7958          *
7959          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7960          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7961          *
7962          * The size of each ring is fixed in the firmware, but the location is
7963          * configurable.
7964          */
7965         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7966              ((u64) tpr->rx_std_mapping >> 32));
7967         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7968              ((u64) tpr->rx_std_mapping & 0xffffffff));
7969         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7970             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7971                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7972                      NIC_SRAM_RX_BUFFER_DESC);
7973
7974         /* Disable the mini ring */
7975         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7976                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7977                      BDINFO_FLAGS_DISABLED);
7978
7979         /* Program the jumbo buffer descriptor ring control
7980          * blocks on those devices that have them.
7981          */
7982         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7983             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7984                 /* Setup replenish threshold. */
7985                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7986
7987                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7988                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7989                              ((u64) tpr->rx_jmb_mapping >> 32));
7990                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7991                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7992                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7993                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7994                              BDINFO_FLAGS_USE_EXT_RECV);
7995                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7996                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7997                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7998                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7999                 } else {
8000                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8001                              BDINFO_FLAGS_DISABLED);
8002                 }
8003
8004                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8005                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8006                                 val = RX_STD_MAX_SIZE_5705;
8007                         else
8008                                 val = RX_STD_MAX_SIZE_5717;
8009                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8010                         val |= (TG3_RX_STD_DMA_SZ << 2);
8011                 } else
8012                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8013         } else
8014                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8015
8016         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8017
8018         tpr->rx_std_prod_idx = tp->rx_pending;
8019         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8020
8021         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8022                           tp->rx_jumbo_pending : 0;
8023         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8024
8025         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8026                 tw32(STD_REPLENISH_LWM, 32);
8027                 tw32(JMB_REPLENISH_LWM, 16);
8028         }
8029
8030         tg3_rings_reset(tp);
8031
8032         /* Initialize MAC address and backoff seed. */
8033         __tg3_set_mac_addr(tp, 0);
8034
8035         /* MTU + ethernet header + FCS + optional VLAN tag */
8036         tw32(MAC_RX_MTU_SIZE,
8037              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8038
8039         /* The slot time is changed by tg3_setup_phy if we
8040          * run at gigabit with half duplex.
8041          */
8042         tw32(MAC_TX_LENGTHS,
8043              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8044              (6 << TX_LENGTHS_IPG_SHIFT) |
8045              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8046
8047         /* Receive rules. */
8048         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8049         tw32(RCVLPC_CONFIG, 0x0181);
8050
8051         /* Calculate RDMAC_MODE setting early, we need it to determine
8052          * the RCVLPC_STATE_ENABLE mask.
8053          */
8054         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8055                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8056                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8057                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8058                       RDMAC_MODE_LNGREAD_ENAB);
8059
8060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8062                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8063
8064         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8065             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8066             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8067                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8068                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8069                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8070
8071         /* If statement applies to 5705 and 5750 PCI devices only */
8072         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8073              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8074             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8075                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8076                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8077                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8078                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8079                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8080                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8081                 }
8082         }
8083
8084         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8085                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8086
8087         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8088                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8089
8090         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8091             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8092             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8093                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8094
8095         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8096             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8097             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8098             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8099             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8100                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8101                 tw32(TG3_RDMA_RSRVCTRL_REG,
8102                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8103         }
8104
8105         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8106                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8107                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8108                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8109                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8110         }
8111
8112         /* Receive/send statistics. */
8113         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8114                 val = tr32(RCVLPC_STATS_ENABLE);
8115                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8116                 tw32(RCVLPC_STATS_ENABLE, val);
8117         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8118                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8119                 val = tr32(RCVLPC_STATS_ENABLE);
8120                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8121                 tw32(RCVLPC_STATS_ENABLE, val);
8122         } else {
8123                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8124         }
8125         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8126         tw32(SNDDATAI_STATSENAB, 0xffffff);
8127         tw32(SNDDATAI_STATSCTRL,
8128              (SNDDATAI_SCTRL_ENABLE |
8129               SNDDATAI_SCTRL_FASTUPD));
8130
8131         /* Setup host coalescing engine. */
8132         tw32(HOSTCC_MODE, 0);
8133         for (i = 0; i < 2000; i++) {
8134                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8135                         break;
8136                 udelay(10);
8137         }
8138
8139         __tg3_set_coalesce(tp, &tp->coal);
8140
8141         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8142                 /* Status/statistics block address.  See tg3_timer,
8143                  * the tg3_periodic_fetch_stats call there, and
8144                  * tg3_get_stats to see how this works for 5705/5750 chips.
8145                  */
8146                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8147                      ((u64) tp->stats_mapping >> 32));
8148                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8149                      ((u64) tp->stats_mapping & 0xffffffff));
8150                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8151
8152                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8153
8154                 /* Clear statistics and status block memory areas */
8155                 for (i = NIC_SRAM_STATS_BLK;
8156                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8157                      i += sizeof(u32)) {
8158                         tg3_write_mem(tp, i, 0);
8159                         udelay(40);
8160                 }
8161         }
8162
8163         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8164
8165         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8166         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8167         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8168                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8169
8170         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8171                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8172                 /* reset to prevent losing 1st rx packet intermittently */
8173                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8174                 udelay(10);
8175         }
8176
8177         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8178                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8179         else
8180                 tp->mac_mode = 0;
8181         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8182                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8183         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8184             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8185             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8186                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8187         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8188         udelay(40);
8189
8190         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8191          * If TG3_FLG2_IS_NIC is zero, we should read the
8192          * register to preserve the GPIO settings for LOMs. The GPIOs,
8193          * whether used as inputs or outputs, are set by boot code after
8194          * reset.
8195          */
8196         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8197                 u32 gpio_mask;
8198
8199                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8200                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8201                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8202
8203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8204                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8205                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8206
8207                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8208                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8209
8210                 tp->grc_local_ctrl &= ~gpio_mask;
8211                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8212
8213                 /* GPIO1 must be driven high for eeprom write protect */
8214                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8215                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8216                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8217         }
8218         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8219         udelay(100);
8220
8221         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8222                 val = tr32(MSGINT_MODE);
8223                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8224                 tw32(MSGINT_MODE, val);
8225         }
8226
8227         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8228                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8229                 udelay(40);
8230         }
8231
8232         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8233                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8234                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8235                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8236                WDMAC_MODE_LNGREAD_ENAB);
8237
8238         /* If statement applies to 5705 and 5750 PCI devices only */
8239         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8240              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8241             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8242                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8243                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8244                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8245                         /* nothing */
8246                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8247                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8248                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8249                         val |= WDMAC_MODE_RX_ACCEL;
8250                 }
8251         }
8252
8253         /* Enable host coalescing bug fix */
8254         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8255                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8256
8257         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8258                 val |= WDMAC_MODE_BURST_ALL_DATA;
8259
8260         tw32_f(WDMAC_MODE, val);
8261         udelay(40);
8262
8263         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8264                 u16 pcix_cmd;
8265
8266                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8267                                      &pcix_cmd);
8268                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8269                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8270                         pcix_cmd |= PCI_X_CMD_READ_2K;
8271                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8272                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8273                         pcix_cmd |= PCI_X_CMD_READ_2K;
8274                 }
8275                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8276                                       pcix_cmd);
8277         }
8278
8279         tw32_f(RDMAC_MODE, rdmac_mode);
8280         udelay(40);
8281
8282         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8284                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8285
8286         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8287                 tw32(SNDDATAC_MODE,
8288                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8289         else
8290                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8291
8292         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8293         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8294         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8295         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8296             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8297                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8298         tw32(RCVDBDI_MODE, val);
8299         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8300         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8301                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8302         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8303         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8304                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8305         tw32(SNDBDI_MODE, val);
8306         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8307
8308         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8309                 err = tg3_load_5701_a0_firmware_fix(tp);
8310                 if (err)
8311                         return err;
8312         }
8313
8314         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8315                 err = tg3_load_tso_firmware(tp);
8316                 if (err)
8317                         return err;
8318         }
8319
8320         tp->tx_mode = TX_MODE_ENABLE;
8321         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8323                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8324         tw32_f(MAC_TX_MODE, tp->tx_mode);
8325         udelay(100);
8326
8327         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8328                 u32 reg = MAC_RSS_INDIR_TBL_0;
8329                 u8 *ent = (u8 *)&val;
8330
8331                 /* Setup the indirection table */
8332                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8333                         int idx = i % sizeof(val);
8334
8335                         ent[idx] = i % (tp->irq_cnt - 1);
8336                         if (idx == sizeof(val) - 1) {
8337                                 tw32(reg, val);
8338                                 reg += 4;
8339                         }
8340                 }
8341
8342                 /* Setup the "secret" hash key. */
8343                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8344                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8345                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8346                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8347                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8348                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8349                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8350                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8351                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8352                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8353         }
8354
8355         tp->rx_mode = RX_MODE_ENABLE;
8356         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8357                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8358
8359         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8360                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8361                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8362                                RX_MODE_RSS_IPV6_HASH_EN |
8363                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8364                                RX_MODE_RSS_IPV4_HASH_EN |
8365                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8366
8367         tw32_f(MAC_RX_MODE, tp->rx_mode);
8368         udelay(10);
8369
8370         tw32(MAC_LED_CTRL, tp->led_ctrl);
8371
8372         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8373         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8374                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8375                 udelay(10);
8376         }
8377         tw32_f(MAC_RX_MODE, tp->rx_mode);
8378         udelay(10);
8379
8380         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8381                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8382                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8383                         /* Set drive transmission level to 1.2V  */
8384                         /* only if the signal pre-emphasis bit is not set  */
8385                         val = tr32(MAC_SERDES_CFG);
8386                         val &= 0xfffff000;
8387                         val |= 0x880;
8388                         tw32(MAC_SERDES_CFG, val);
8389                 }
8390                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8391                         tw32(MAC_SERDES_CFG, 0x616000);
8392         }
8393
8394         /* Prevent chip from dropping frames when flow control
8395          * is enabled.
8396          */
8397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8398                 val = 1;
8399         else
8400                 val = 2;
8401         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8402
8403         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8404             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8405                 /* Use hardware link auto-negotiation */
8406                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8407         }
8408
8409         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8410             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8411                 u32 tmp;
8412
8413                 tmp = tr32(SERDES_RX_CTRL);
8414                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8415                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8416                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8417                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8418         }
8419
8420         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8421                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8422                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8423                         tp->link_config.speed = tp->link_config.orig_speed;
8424                         tp->link_config.duplex = tp->link_config.orig_duplex;
8425                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8426                 }
8427
8428                 err = tg3_setup_phy(tp, 0);
8429                 if (err)
8430                         return err;
8431
8432                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8433                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8434                         u32 tmp;
8435
8436                         /* Clear CRC stats. */
8437                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8438                                 tg3_writephy(tp, MII_TG3_TEST1,
8439                                              tmp | MII_TG3_TEST1_CRC_EN);
8440                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8441                         }
8442                 }
8443         }
8444
8445         __tg3_set_rx_mode(tp->dev);
8446
8447         /* Initialize receive rules. */
8448         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8449         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8450         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8451         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8452
8453         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8454             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8455                 limit = 8;
8456         else
8457                 limit = 16;
8458         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8459                 limit -= 4;
8460         switch (limit) {
8461         case 16:
8462                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8463         case 15:
8464                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8465         case 14:
8466                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8467         case 13:
8468                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8469         case 12:
8470                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8471         case 11:
8472                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8473         case 10:
8474                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8475         case 9:
8476                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8477         case 8:
8478                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8479         case 7:
8480                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8481         case 6:
8482                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8483         case 5:
8484                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8485         case 4:
8486                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8487         case 3:
8488                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8489         case 2:
8490         case 1:
8491
8492         default:
8493                 break;
8494         }
8495
8496         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8497                 /* Write our heartbeat update interval to APE. */
8498                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8499                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8500
8501         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8502
8503         return 0;
8504 }
8505
8506 /* Called at device open time to get the chip ready for
8507  * packet processing.  Invoked with tp->lock held.
8508  */
8509 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8510 {
8511         tg3_switch_clocks(tp);
8512
8513         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8514
8515         return tg3_reset_hw(tp, reset_phy);
8516 }
8517
8518 #define TG3_STAT_ADD32(PSTAT, REG) \
8519 do {    u32 __val = tr32(REG); \
8520         (PSTAT)->low += __val; \
8521         if ((PSTAT)->low < __val) \
8522                 (PSTAT)->high += 1; \
8523 } while (0)
8524
8525 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8526 {
8527         struct tg3_hw_stats *sp = tp->hw_stats;
8528
8529         if (!netif_carrier_ok(tp->dev))
8530                 return;
8531
8532         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8533         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8534         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8535         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8536         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8537         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8538         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8539         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8540         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8541         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8542         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8543         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8544         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8545
8546         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8547         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8548         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8549         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8550         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8551         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8552         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8553         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8554         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8555         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8556         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8557         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8558         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8559         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8560
8561         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8562         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8563         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8564 }
8565
8566 static void tg3_timer(unsigned long __opaque)
8567 {
8568         struct tg3 *tp = (struct tg3 *) __opaque;
8569
8570         if (tp->irq_sync)
8571                 goto restart_timer;
8572
8573         spin_lock(&tp->lock);
8574
8575         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8576                 /* All of this garbage is because when using non-tagged
8577                  * IRQ status the mailbox/status_block protocol the chip
8578                  * uses with the cpu is race prone.
8579                  */
8580                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8581                         tw32(GRC_LOCAL_CTRL,
8582                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8583                 } else {
8584                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8585                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8586                 }
8587
8588                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8589                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8590                         spin_unlock(&tp->lock);
8591                         schedule_work(&tp->reset_task);
8592                         return;
8593                 }
8594         }
8595
8596         /* This part only runs once per second. */
8597         if (!--tp->timer_counter) {
8598                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8599                         tg3_periodic_fetch_stats(tp);
8600
8601                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8602                         u32 mac_stat;
8603                         int phy_event;
8604
8605                         mac_stat = tr32(MAC_STATUS);
8606
8607                         phy_event = 0;
8608                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8609                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8610                                         phy_event = 1;
8611                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8612                                 phy_event = 1;
8613
8614                         if (phy_event)
8615                                 tg3_setup_phy(tp, 0);
8616                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8617                         u32 mac_stat = tr32(MAC_STATUS);
8618                         int need_setup = 0;
8619
8620                         if (netif_carrier_ok(tp->dev) &&
8621                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8622                                 need_setup = 1;
8623                         }
8624                         if (!netif_carrier_ok(tp->dev) &&
8625                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8626                                          MAC_STATUS_SIGNAL_DET))) {
8627                                 need_setup = 1;
8628                         }
8629                         if (need_setup) {
8630                                 if (!tp->serdes_counter) {
8631                                         tw32_f(MAC_MODE,
8632                                              (tp->mac_mode &
8633                                               ~MAC_MODE_PORT_MODE_MASK));
8634                                         udelay(40);
8635                                         tw32_f(MAC_MODE, tp->mac_mode);
8636                                         udelay(40);
8637                                 }
8638                                 tg3_setup_phy(tp, 0);
8639                         }
8640                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8641                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8642                         tg3_serdes_parallel_detect(tp);
8643                 }
8644
8645                 tp->timer_counter = tp->timer_multiplier;
8646         }
8647
8648         /* Heartbeat is only sent once every 2 seconds.
8649          *
8650          * The heartbeat is to tell the ASF firmware that the host
8651          * driver is still alive.  In the event that the OS crashes,
8652          * ASF needs to reset the hardware to free up the FIFO space
8653          * that may be filled with rx packets destined for the host.
8654          * If the FIFO is full, ASF will no longer function properly.
8655          *
8656          * Unintended resets have been reported on real time kernels
8657          * where the timer doesn't run on time.  Netpoll will also have
8658          * same problem.
8659          *
8660          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8661          * to check the ring condition when the heartbeat is expiring
8662          * before doing the reset.  This will prevent most unintended
8663          * resets.
8664          */
8665         if (!--tp->asf_counter) {
8666                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8667                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8668                         tg3_wait_for_event_ack(tp);
8669
8670                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8671                                       FWCMD_NICDRV_ALIVE3);
8672                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8673                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8674                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8675
8676                         tg3_generate_fw_event(tp);
8677                 }
8678                 tp->asf_counter = tp->asf_multiplier;
8679         }
8680
8681         spin_unlock(&tp->lock);
8682
8683 restart_timer:
8684         tp->timer.expires = jiffies + tp->timer_offset;
8685         add_timer(&tp->timer);
8686 }
8687
8688 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8689 {
8690         irq_handler_t fn;
8691         unsigned long flags;
8692         char *name;
8693         struct tg3_napi *tnapi = &tp->napi[irq_num];
8694
8695         if (tp->irq_cnt == 1)
8696                 name = tp->dev->name;
8697         else {
8698                 name = &tnapi->irq_lbl[0];
8699                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8700                 name[IFNAMSIZ-1] = 0;
8701         }
8702
8703         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8704                 fn = tg3_msi;
8705                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8706                         fn = tg3_msi_1shot;
8707                 flags = IRQF_SAMPLE_RANDOM;
8708         } else {
8709                 fn = tg3_interrupt;
8710                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8711                         fn = tg3_interrupt_tagged;
8712                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8713         }
8714
8715         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8716 }
8717
8718 static int tg3_test_interrupt(struct tg3 *tp)
8719 {
8720         struct tg3_napi *tnapi = &tp->napi[0];
8721         struct net_device *dev = tp->dev;
8722         int err, i, intr_ok = 0;
8723         u32 val;
8724
8725         if (!netif_running(dev))
8726                 return -ENODEV;
8727
8728         tg3_disable_ints(tp);
8729
8730         free_irq(tnapi->irq_vec, tnapi);
8731
8732         /*
8733          * Turn off MSI one shot mode.  Otherwise this test has no
8734          * observable way to know whether the interrupt was delivered.
8735          */
8736         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8737             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8738                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8739                 tw32(MSGINT_MODE, val);
8740         }
8741
8742         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8743                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8744         if (err)
8745                 return err;
8746
8747         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8748         tg3_enable_ints(tp);
8749
8750         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8751                tnapi->coal_now);
8752
8753         for (i = 0; i < 5; i++) {
8754                 u32 int_mbox, misc_host_ctrl;
8755
8756                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8757                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8758
8759                 if ((int_mbox != 0) ||
8760                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8761                         intr_ok = 1;
8762                         break;
8763                 }
8764
8765                 msleep(10);
8766         }
8767
8768         tg3_disable_ints(tp);
8769
8770         free_irq(tnapi->irq_vec, tnapi);
8771
8772         err = tg3_request_irq(tp, 0);
8773
8774         if (err)
8775                 return err;
8776
8777         if (intr_ok) {
8778                 /* Reenable MSI one shot mode. */
8779                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8780                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8781                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8782                         tw32(MSGINT_MODE, val);
8783                 }
8784                 return 0;
8785         }
8786
8787         return -EIO;
8788 }
8789
8790 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8791  * successfully restored
8792  */
8793 static int tg3_test_msi(struct tg3 *tp)
8794 {
8795         int err;
8796         u16 pci_cmd;
8797
8798         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8799                 return 0;
8800
8801         /* Turn off SERR reporting in case MSI terminates with Master
8802          * Abort.
8803          */
8804         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8805         pci_write_config_word(tp->pdev, PCI_COMMAND,
8806                               pci_cmd & ~PCI_COMMAND_SERR);
8807
8808         err = tg3_test_interrupt(tp);
8809
8810         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8811
8812         if (!err)
8813                 return 0;
8814
8815         /* other failures */
8816         if (err != -EIO)
8817                 return err;
8818
8819         /* MSI test failed, go back to INTx mode */
8820         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8821                     "to INTx mode. Please report this failure to the PCI "
8822                     "maintainer and include system chipset information\n");
8823
8824         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8825
8826         pci_disable_msi(tp->pdev);
8827
8828         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8829         tp->napi[0].irq_vec = tp->pdev->irq;
8830
8831         err = tg3_request_irq(tp, 0);
8832         if (err)
8833                 return err;
8834
8835         /* Need to reset the chip because the MSI cycle may have terminated
8836          * with Master Abort.
8837          */
8838         tg3_full_lock(tp, 1);
8839
8840         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8841         err = tg3_init_hw(tp, 1);
8842
8843         tg3_full_unlock(tp);
8844
8845         if (err)
8846                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8847
8848         return err;
8849 }
8850
8851 static int tg3_request_firmware(struct tg3 *tp)
8852 {
8853         const __be32 *fw_data;
8854
8855         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8856                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8857                            tp->fw_needed);
8858                 return -ENOENT;
8859         }
8860
8861         fw_data = (void *)tp->fw->data;
8862
8863         /* Firmware blob starts with version numbers, followed by
8864          * start address and _full_ length including BSS sections
8865          * (which must be longer than the actual data, of course
8866          */
8867
8868         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8869         if (tp->fw_len < (tp->fw->size - 12)) {
8870                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8871                            tp->fw_len, tp->fw_needed);
8872                 release_firmware(tp->fw);
8873                 tp->fw = NULL;
8874                 return -EINVAL;
8875         }
8876
8877         /* We no longer need firmware; we have it. */
8878         tp->fw_needed = NULL;
8879         return 0;
8880 }
8881
8882 static bool tg3_enable_msix(struct tg3 *tp)
8883 {
8884         int i, rc, cpus = num_online_cpus();
8885         struct msix_entry msix_ent[tp->irq_max];
8886
8887         if (cpus == 1)
8888                 /* Just fallback to the simpler MSI mode. */
8889                 return false;
8890
8891         /*
8892          * We want as many rx rings enabled as there are cpus.
8893          * The first MSIX vector only deals with link interrupts, etc,
8894          * so we add one to the number of vectors we are requesting.
8895          */
8896         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8897
8898         for (i = 0; i < tp->irq_max; i++) {
8899                 msix_ent[i].entry  = i;
8900                 msix_ent[i].vector = 0;
8901         }
8902
8903         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8904         if (rc < 0) {
8905                 return false;
8906         } else if (rc != 0) {
8907                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8908                         return false;
8909                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8910                               tp->irq_cnt, rc);
8911                 tp->irq_cnt = rc;
8912         }
8913
8914         for (i = 0; i < tp->irq_max; i++)
8915                 tp->napi[i].irq_vec = msix_ent[i].vector;
8916
8917         netif_set_real_num_tx_queues(tp->dev, 1);
8918         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
8919         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
8920                 pci_disable_msix(tp->pdev);
8921                 return false;
8922         }
8923         if (tp->irq_cnt > 1)
8924                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8925
8926         return true;
8927 }
8928
8929 static void tg3_ints_init(struct tg3 *tp)
8930 {
8931         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8932             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8933                 /* All MSI supporting chips should support tagged
8934                  * status.  Assert that this is the case.
8935                  */
8936                 netdev_warn(tp->dev,
8937                             "MSI without TAGGED_STATUS? Not using MSI\n");
8938                 goto defcfg;
8939         }
8940
8941         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8942                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8943         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8944                  pci_enable_msi(tp->pdev) == 0)
8945                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8946
8947         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8948                 u32 msi_mode = tr32(MSGINT_MODE);
8949                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8950                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8951                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8952         }
8953 defcfg:
8954         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8955                 tp->irq_cnt = 1;
8956                 tp->napi[0].irq_vec = tp->pdev->irq;
8957                 netif_set_real_num_tx_queues(tp->dev, 1);
8958                 netif_set_real_num_rx_queues(tp->dev, 1);
8959         }
8960 }
8961
8962 static void tg3_ints_fini(struct tg3 *tp)
8963 {
8964         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8965                 pci_disable_msix(tp->pdev);
8966         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8967                 pci_disable_msi(tp->pdev);
8968         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8969         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8970 }
8971
8972 static int tg3_open(struct net_device *dev)
8973 {
8974         struct tg3 *tp = netdev_priv(dev);
8975         int i, err;
8976
8977         if (tp->fw_needed) {
8978                 err = tg3_request_firmware(tp);
8979                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8980                         if (err)
8981                                 return err;
8982                 } else if (err) {
8983                         netdev_warn(tp->dev, "TSO capability disabled\n");
8984                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8985                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8986                         netdev_notice(tp->dev, "TSO capability restored\n");
8987                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8988                 }
8989         }
8990
8991         netif_carrier_off(tp->dev);
8992
8993         err = tg3_set_power_state(tp, PCI_D0);
8994         if (err)
8995                 return err;
8996
8997         tg3_full_lock(tp, 0);
8998
8999         tg3_disable_ints(tp);
9000         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9001
9002         tg3_full_unlock(tp);
9003
9004         /*
9005          * Setup interrupts first so we know how
9006          * many NAPI resources to allocate
9007          */
9008         tg3_ints_init(tp);
9009
9010         /* The placement of this call is tied
9011          * to the setup and use of Host TX descriptors.
9012          */
9013         err = tg3_alloc_consistent(tp);
9014         if (err)
9015                 goto err_out1;
9016
9017         tg3_napi_init(tp);
9018
9019         tg3_napi_enable(tp);
9020
9021         for (i = 0; i < tp->irq_cnt; i++) {
9022                 struct tg3_napi *tnapi = &tp->napi[i];
9023                 err = tg3_request_irq(tp, i);
9024                 if (err) {
9025                         for (i--; i >= 0; i--)
9026                                 free_irq(tnapi->irq_vec, tnapi);
9027                         break;
9028                 }
9029         }
9030
9031         if (err)
9032                 goto err_out2;
9033
9034         tg3_full_lock(tp, 0);
9035
9036         err = tg3_init_hw(tp, 1);
9037         if (err) {
9038                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9039                 tg3_free_rings(tp);
9040         } else {
9041                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9042                         tp->timer_offset = HZ;
9043                 else
9044                         tp->timer_offset = HZ / 10;
9045
9046                 BUG_ON(tp->timer_offset > HZ);
9047                 tp->timer_counter = tp->timer_multiplier =
9048                         (HZ / tp->timer_offset);
9049                 tp->asf_counter = tp->asf_multiplier =
9050                         ((HZ / tp->timer_offset) * 2);
9051
9052                 init_timer(&tp->timer);
9053                 tp->timer.expires = jiffies + tp->timer_offset;
9054                 tp->timer.data = (unsigned long) tp;
9055                 tp->timer.function = tg3_timer;
9056         }
9057
9058         tg3_full_unlock(tp);
9059
9060         if (err)
9061                 goto err_out3;
9062
9063         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9064                 err = tg3_test_msi(tp);
9065
9066                 if (err) {
9067                         tg3_full_lock(tp, 0);
9068                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9069                         tg3_free_rings(tp);
9070                         tg3_full_unlock(tp);
9071
9072                         goto err_out2;
9073                 }
9074
9075                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9076                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9077                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9078
9079                         tw32(PCIE_TRANSACTION_CFG,
9080                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9081                 }
9082         }
9083
9084         tg3_phy_start(tp);
9085
9086         tg3_full_lock(tp, 0);
9087
9088         add_timer(&tp->timer);
9089         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9090         tg3_enable_ints(tp);
9091
9092         tg3_full_unlock(tp);
9093
9094         netif_tx_start_all_queues(dev);
9095
9096         return 0;
9097
9098 err_out3:
9099         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9100                 struct tg3_napi *tnapi = &tp->napi[i];
9101                 free_irq(tnapi->irq_vec, tnapi);
9102         }
9103
9104 err_out2:
9105         tg3_napi_disable(tp);
9106         tg3_napi_fini(tp);
9107         tg3_free_consistent(tp);
9108
9109 err_out1:
9110         tg3_ints_fini(tp);
9111         return err;
9112 }
9113
9114 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9115                                                  struct rtnl_link_stats64 *);
9116 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9117
9118 static int tg3_close(struct net_device *dev)
9119 {
9120         int i;
9121         struct tg3 *tp = netdev_priv(dev);
9122
9123         tg3_napi_disable(tp);
9124         cancel_work_sync(&tp->reset_task);
9125
9126         netif_tx_stop_all_queues(dev);
9127
9128         del_timer_sync(&tp->timer);
9129
9130         tg3_phy_stop(tp);
9131
9132         tg3_full_lock(tp, 1);
9133
9134         tg3_disable_ints(tp);
9135
9136         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9137         tg3_free_rings(tp);
9138         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9139
9140         tg3_full_unlock(tp);
9141
9142         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9143                 struct tg3_napi *tnapi = &tp->napi[i];
9144                 free_irq(tnapi->irq_vec, tnapi);
9145         }
9146
9147         tg3_ints_fini(tp);
9148
9149         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9150
9151         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9152                sizeof(tp->estats_prev));
9153
9154         tg3_napi_fini(tp);
9155
9156         tg3_free_consistent(tp);
9157
9158         tg3_set_power_state(tp, PCI_D3hot);
9159
9160         netif_carrier_off(tp->dev);
9161
9162         return 0;
9163 }
9164
9165 static inline u64 get_stat64(tg3_stat64_t *val)
9166 {
9167        return ((u64)val->high << 32) | ((u64)val->low);
9168 }
9169
9170 static u64 calc_crc_errors(struct tg3 *tp)
9171 {
9172         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9173
9174         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9175             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9176              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9177                 u32 val;
9178
9179                 spin_lock_bh(&tp->lock);
9180                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9181                         tg3_writephy(tp, MII_TG3_TEST1,
9182                                      val | MII_TG3_TEST1_CRC_EN);
9183                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9184                 } else
9185                         val = 0;
9186                 spin_unlock_bh(&tp->lock);
9187
9188                 tp->phy_crc_errors += val;
9189
9190                 return tp->phy_crc_errors;
9191         }
9192
9193         return get_stat64(&hw_stats->rx_fcs_errors);
9194 }
9195
9196 #define ESTAT_ADD(member) \
9197         estats->member =        old_estats->member + \
9198                                 get_stat64(&hw_stats->member)
9199
9200 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9201 {
9202         struct tg3_ethtool_stats *estats = &tp->estats;
9203         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9204         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9205
9206         if (!hw_stats)
9207                 return old_estats;
9208
9209         ESTAT_ADD(rx_octets);
9210         ESTAT_ADD(rx_fragments);
9211         ESTAT_ADD(rx_ucast_packets);
9212         ESTAT_ADD(rx_mcast_packets);
9213         ESTAT_ADD(rx_bcast_packets);
9214         ESTAT_ADD(rx_fcs_errors);
9215         ESTAT_ADD(rx_align_errors);
9216         ESTAT_ADD(rx_xon_pause_rcvd);
9217         ESTAT_ADD(rx_xoff_pause_rcvd);
9218         ESTAT_ADD(rx_mac_ctrl_rcvd);
9219         ESTAT_ADD(rx_xoff_entered);
9220         ESTAT_ADD(rx_frame_too_long_errors);
9221         ESTAT_ADD(rx_jabbers);
9222         ESTAT_ADD(rx_undersize_packets);
9223         ESTAT_ADD(rx_in_length_errors);
9224         ESTAT_ADD(rx_out_length_errors);
9225         ESTAT_ADD(rx_64_or_less_octet_packets);
9226         ESTAT_ADD(rx_65_to_127_octet_packets);
9227         ESTAT_ADD(rx_128_to_255_octet_packets);
9228         ESTAT_ADD(rx_256_to_511_octet_packets);
9229         ESTAT_ADD(rx_512_to_1023_octet_packets);
9230         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9231         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9232         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9233         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9234         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9235
9236         ESTAT_ADD(tx_octets);
9237         ESTAT_ADD(tx_collisions);
9238         ESTAT_ADD(tx_xon_sent);
9239         ESTAT_ADD(tx_xoff_sent);
9240         ESTAT_ADD(tx_flow_control);
9241         ESTAT_ADD(tx_mac_errors);
9242         ESTAT_ADD(tx_single_collisions);
9243         ESTAT_ADD(tx_mult_collisions);
9244         ESTAT_ADD(tx_deferred);
9245         ESTAT_ADD(tx_excessive_collisions);
9246         ESTAT_ADD(tx_late_collisions);
9247         ESTAT_ADD(tx_collide_2times);
9248         ESTAT_ADD(tx_collide_3times);
9249         ESTAT_ADD(tx_collide_4times);
9250         ESTAT_ADD(tx_collide_5times);
9251         ESTAT_ADD(tx_collide_6times);
9252         ESTAT_ADD(tx_collide_7times);
9253         ESTAT_ADD(tx_collide_8times);
9254         ESTAT_ADD(tx_collide_9times);
9255         ESTAT_ADD(tx_collide_10times);
9256         ESTAT_ADD(tx_collide_11times);
9257         ESTAT_ADD(tx_collide_12times);
9258         ESTAT_ADD(tx_collide_13times);
9259         ESTAT_ADD(tx_collide_14times);
9260         ESTAT_ADD(tx_collide_15times);
9261         ESTAT_ADD(tx_ucast_packets);
9262         ESTAT_ADD(tx_mcast_packets);
9263         ESTAT_ADD(tx_bcast_packets);
9264         ESTAT_ADD(tx_carrier_sense_errors);
9265         ESTAT_ADD(tx_discards);
9266         ESTAT_ADD(tx_errors);
9267
9268         ESTAT_ADD(dma_writeq_full);
9269         ESTAT_ADD(dma_write_prioq_full);
9270         ESTAT_ADD(rxbds_empty);
9271         ESTAT_ADD(rx_discards);
9272         ESTAT_ADD(rx_errors);
9273         ESTAT_ADD(rx_threshold_hit);
9274
9275         ESTAT_ADD(dma_readq_full);
9276         ESTAT_ADD(dma_read_prioq_full);
9277         ESTAT_ADD(tx_comp_queue_full);
9278
9279         ESTAT_ADD(ring_set_send_prod_index);
9280         ESTAT_ADD(ring_status_update);
9281         ESTAT_ADD(nic_irqs);
9282         ESTAT_ADD(nic_avoided_irqs);
9283         ESTAT_ADD(nic_tx_threshold_hit);
9284
9285         return estats;
9286 }
9287
9288 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9289                                                  struct rtnl_link_stats64 *stats)
9290 {
9291         struct tg3 *tp = netdev_priv(dev);
9292         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9293         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9294
9295         if (!hw_stats)
9296                 return old_stats;
9297
9298         stats->rx_packets = old_stats->rx_packets +
9299                 get_stat64(&hw_stats->rx_ucast_packets) +
9300                 get_stat64(&hw_stats->rx_mcast_packets) +
9301                 get_stat64(&hw_stats->rx_bcast_packets);
9302
9303         stats->tx_packets = old_stats->tx_packets +
9304                 get_stat64(&hw_stats->tx_ucast_packets) +
9305                 get_stat64(&hw_stats->tx_mcast_packets) +
9306                 get_stat64(&hw_stats->tx_bcast_packets);
9307
9308         stats->rx_bytes = old_stats->rx_bytes +
9309                 get_stat64(&hw_stats->rx_octets);
9310         stats->tx_bytes = old_stats->tx_bytes +
9311                 get_stat64(&hw_stats->tx_octets);
9312
9313         stats->rx_errors = old_stats->rx_errors +
9314                 get_stat64(&hw_stats->rx_errors);
9315         stats->tx_errors = old_stats->tx_errors +
9316                 get_stat64(&hw_stats->tx_errors) +
9317                 get_stat64(&hw_stats->tx_mac_errors) +
9318                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9319                 get_stat64(&hw_stats->tx_discards);
9320
9321         stats->multicast = old_stats->multicast +
9322                 get_stat64(&hw_stats->rx_mcast_packets);
9323         stats->collisions = old_stats->collisions +
9324                 get_stat64(&hw_stats->tx_collisions);
9325
9326         stats->rx_length_errors = old_stats->rx_length_errors +
9327                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9328                 get_stat64(&hw_stats->rx_undersize_packets);
9329
9330         stats->rx_over_errors = old_stats->rx_over_errors +
9331                 get_stat64(&hw_stats->rxbds_empty);
9332         stats->rx_frame_errors = old_stats->rx_frame_errors +
9333                 get_stat64(&hw_stats->rx_align_errors);
9334         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9335                 get_stat64(&hw_stats->tx_discards);
9336         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9337                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9338
9339         stats->rx_crc_errors = old_stats->rx_crc_errors +
9340                 calc_crc_errors(tp);
9341
9342         stats->rx_missed_errors = old_stats->rx_missed_errors +
9343                 get_stat64(&hw_stats->rx_discards);
9344
9345         return stats;
9346 }
9347
9348 static inline u32 calc_crc(unsigned char *buf, int len)
9349 {
9350         u32 reg;
9351         u32 tmp;
9352         int j, k;
9353
9354         reg = 0xffffffff;
9355
9356         for (j = 0; j < len; j++) {
9357                 reg ^= buf[j];
9358
9359                 for (k = 0; k < 8; k++) {
9360                         tmp = reg & 0x01;
9361
9362                         reg >>= 1;
9363
9364                         if (tmp)
9365                                 reg ^= 0xedb88320;
9366                 }
9367         }
9368
9369         return ~reg;
9370 }
9371
9372 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9373 {
9374         /* accept or reject all multicast frames */
9375         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9376         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9377         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9378         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9379 }
9380
9381 static void __tg3_set_rx_mode(struct net_device *dev)
9382 {
9383         struct tg3 *tp = netdev_priv(dev);
9384         u32 rx_mode;
9385
9386         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9387                                   RX_MODE_KEEP_VLAN_TAG);
9388
9389         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9390          * flag clear.
9391          */
9392 #if TG3_VLAN_TAG_USED
9393         if (!tp->vlgrp &&
9394             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9395                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9396 #else
9397         /* By definition, VLAN is disabled always in this
9398          * case.
9399          */
9400         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9401                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9402 #endif
9403
9404         if (dev->flags & IFF_PROMISC) {
9405                 /* Promiscuous mode. */
9406                 rx_mode |= RX_MODE_PROMISC;
9407         } else if (dev->flags & IFF_ALLMULTI) {
9408                 /* Accept all multicast. */
9409                 tg3_set_multi(tp, 1);
9410         } else if (netdev_mc_empty(dev)) {
9411                 /* Reject all multicast. */
9412                 tg3_set_multi(tp, 0);
9413         } else {
9414                 /* Accept one or more multicast(s). */
9415                 struct netdev_hw_addr *ha;
9416                 u32 mc_filter[4] = { 0, };
9417                 u32 regidx;
9418                 u32 bit;
9419                 u32 crc;
9420
9421                 netdev_for_each_mc_addr(ha, dev) {
9422                         crc = calc_crc(ha->addr, ETH_ALEN);
9423                         bit = ~crc & 0x7f;
9424                         regidx = (bit & 0x60) >> 5;
9425                         bit &= 0x1f;
9426                         mc_filter[regidx] |= (1 << bit);
9427                 }
9428
9429                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9430                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9431                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9432                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9433         }
9434
9435         if (rx_mode != tp->rx_mode) {
9436                 tp->rx_mode = rx_mode;
9437                 tw32_f(MAC_RX_MODE, rx_mode);
9438                 udelay(10);
9439         }
9440 }
9441
9442 static void tg3_set_rx_mode(struct net_device *dev)
9443 {
9444         struct tg3 *tp = netdev_priv(dev);
9445
9446         if (!netif_running(dev))
9447                 return;
9448
9449         tg3_full_lock(tp, 0);
9450         __tg3_set_rx_mode(dev);
9451         tg3_full_unlock(tp);
9452 }
9453
9454 #define TG3_REGDUMP_LEN         (32 * 1024)
9455
9456 static int tg3_get_regs_len(struct net_device *dev)
9457 {
9458         return TG3_REGDUMP_LEN;
9459 }
9460
9461 static void tg3_get_regs(struct net_device *dev,
9462                 struct ethtool_regs *regs, void *_p)
9463 {
9464         u32 *p = _p;
9465         struct tg3 *tp = netdev_priv(dev);
9466         u8 *orig_p = _p;
9467         int i;
9468
9469         regs->version = 0;
9470
9471         memset(p, 0, TG3_REGDUMP_LEN);
9472
9473         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9474                 return;
9475
9476         tg3_full_lock(tp, 0);
9477
9478 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9479 #define GET_REG32_LOOP(base, len)               \
9480 do {    p = (u32 *)(orig_p + (base));           \
9481         for (i = 0; i < len; i += 4)            \
9482                 __GET_REG32((base) + i);        \
9483 } while (0)
9484 #define GET_REG32_1(reg)                        \
9485 do {    p = (u32 *)(orig_p + (reg));            \
9486         __GET_REG32((reg));                     \
9487 } while (0)
9488
9489         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9490         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9491         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9492         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9493         GET_REG32_1(SNDDATAC_MODE);
9494         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9495         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9496         GET_REG32_1(SNDBDC_MODE);
9497         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9498         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9499         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9500         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9501         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9502         GET_REG32_1(RCVDCC_MODE);
9503         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9504         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9505         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9506         GET_REG32_1(MBFREE_MODE);
9507         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9508         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9509         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9510         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9511         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9512         GET_REG32_1(RX_CPU_MODE);
9513         GET_REG32_1(RX_CPU_STATE);
9514         GET_REG32_1(RX_CPU_PGMCTR);
9515         GET_REG32_1(RX_CPU_HWBKPT);
9516         GET_REG32_1(TX_CPU_MODE);
9517         GET_REG32_1(TX_CPU_STATE);
9518         GET_REG32_1(TX_CPU_PGMCTR);
9519         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9520         GET_REG32_LOOP(FTQ_RESET, 0x120);
9521         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9522         GET_REG32_1(DMAC_MODE);
9523         GET_REG32_LOOP(GRC_MODE, 0x4c);
9524         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9525                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9526
9527 #undef __GET_REG32
9528 #undef GET_REG32_LOOP
9529 #undef GET_REG32_1
9530
9531         tg3_full_unlock(tp);
9532 }
9533
9534 static int tg3_get_eeprom_len(struct net_device *dev)
9535 {
9536         struct tg3 *tp = netdev_priv(dev);
9537
9538         return tp->nvram_size;
9539 }
9540
9541 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9542 {
9543         struct tg3 *tp = netdev_priv(dev);
9544         int ret;
9545         u8  *pd;
9546         u32 i, offset, len, b_offset, b_count;
9547         __be32 val;
9548
9549         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9550                 return -EINVAL;
9551
9552         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9553                 return -EAGAIN;
9554
9555         offset = eeprom->offset;
9556         len = eeprom->len;
9557         eeprom->len = 0;
9558
9559         eeprom->magic = TG3_EEPROM_MAGIC;
9560
9561         if (offset & 3) {
9562                 /* adjustments to start on required 4 byte boundary */
9563                 b_offset = offset & 3;
9564                 b_count = 4 - b_offset;
9565                 if (b_count > len) {
9566                         /* i.e. offset=1 len=2 */
9567                         b_count = len;
9568                 }
9569                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9570                 if (ret)
9571                         return ret;
9572                 memcpy(data, ((char *)&val) + b_offset, b_count);
9573                 len -= b_count;
9574                 offset += b_count;
9575                 eeprom->len += b_count;
9576         }
9577
9578         /* read bytes upto the last 4 byte boundary */
9579         pd = &data[eeprom->len];
9580         for (i = 0; i < (len - (len & 3)); i += 4) {
9581                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9582                 if (ret) {
9583                         eeprom->len += i;
9584                         return ret;
9585                 }
9586                 memcpy(pd + i, &val, 4);
9587         }
9588         eeprom->len += i;
9589
9590         if (len & 3) {
9591                 /* read last bytes not ending on 4 byte boundary */
9592                 pd = &data[eeprom->len];
9593                 b_count = len & 3;
9594                 b_offset = offset + len - b_count;
9595                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9596                 if (ret)
9597                         return ret;
9598                 memcpy(pd, &val, b_count);
9599                 eeprom->len += b_count;
9600         }
9601         return 0;
9602 }
9603
9604 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9605
9606 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9607 {
9608         struct tg3 *tp = netdev_priv(dev);
9609         int ret;
9610         u32 offset, len, b_offset, odd_len;
9611         u8 *buf;
9612         __be32 start, end;
9613
9614         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9615                 return -EAGAIN;
9616
9617         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9618             eeprom->magic != TG3_EEPROM_MAGIC)
9619                 return -EINVAL;
9620
9621         offset = eeprom->offset;
9622         len = eeprom->len;
9623
9624         if ((b_offset = (offset & 3))) {
9625                 /* adjustments to start on required 4 byte boundary */
9626                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9627                 if (ret)
9628                         return ret;
9629                 len += b_offset;
9630                 offset &= ~3;
9631                 if (len < 4)
9632                         len = 4;
9633         }
9634
9635         odd_len = 0;
9636         if (len & 3) {
9637                 /* adjustments to end on required 4 byte boundary */
9638                 odd_len = 1;
9639                 len = (len + 3) & ~3;
9640                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9641                 if (ret)
9642                         return ret;
9643         }
9644
9645         buf = data;
9646         if (b_offset || odd_len) {
9647                 buf = kmalloc(len, GFP_KERNEL);
9648                 if (!buf)
9649                         return -ENOMEM;
9650                 if (b_offset)
9651                         memcpy(buf, &start, 4);
9652                 if (odd_len)
9653                         memcpy(buf+len-4, &end, 4);
9654                 memcpy(buf + b_offset, data, eeprom->len);
9655         }
9656
9657         ret = tg3_nvram_write_block(tp, offset, len, buf);
9658
9659         if (buf != data)
9660                 kfree(buf);
9661
9662         return ret;
9663 }
9664
9665 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9666 {
9667         struct tg3 *tp = netdev_priv(dev);
9668
9669         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9670                 struct phy_device *phydev;
9671                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9672                         return -EAGAIN;
9673                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9674                 return phy_ethtool_gset(phydev, cmd);
9675         }
9676
9677         cmd->supported = (SUPPORTED_Autoneg);
9678
9679         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9680                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9681                                    SUPPORTED_1000baseT_Full);
9682
9683         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9684                 cmd->supported |= (SUPPORTED_100baseT_Half |
9685                                   SUPPORTED_100baseT_Full |
9686                                   SUPPORTED_10baseT_Half |
9687                                   SUPPORTED_10baseT_Full |
9688                                   SUPPORTED_TP);
9689                 cmd->port = PORT_TP;
9690         } else {
9691                 cmd->supported |= SUPPORTED_FIBRE;
9692                 cmd->port = PORT_FIBRE;
9693         }
9694
9695         cmd->advertising = tp->link_config.advertising;
9696         if (netif_running(dev)) {
9697                 cmd->speed = tp->link_config.active_speed;
9698                 cmd->duplex = tp->link_config.active_duplex;
9699         }
9700         cmd->phy_address = tp->phy_addr;
9701         cmd->transceiver = XCVR_INTERNAL;
9702         cmd->autoneg = tp->link_config.autoneg;
9703         cmd->maxtxpkt = 0;
9704         cmd->maxrxpkt = 0;
9705         return 0;
9706 }
9707
9708 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9709 {
9710         struct tg3 *tp = netdev_priv(dev);
9711
9712         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9713                 struct phy_device *phydev;
9714                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9715                         return -EAGAIN;
9716                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9717                 return phy_ethtool_sset(phydev, cmd);
9718         }
9719
9720         if (cmd->autoneg != AUTONEG_ENABLE &&
9721             cmd->autoneg != AUTONEG_DISABLE)
9722                 return -EINVAL;
9723
9724         if (cmd->autoneg == AUTONEG_DISABLE &&
9725             cmd->duplex != DUPLEX_FULL &&
9726             cmd->duplex != DUPLEX_HALF)
9727                 return -EINVAL;
9728
9729         if (cmd->autoneg == AUTONEG_ENABLE) {
9730                 u32 mask = ADVERTISED_Autoneg |
9731                            ADVERTISED_Pause |
9732                            ADVERTISED_Asym_Pause;
9733
9734                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9735                         mask |= ADVERTISED_1000baseT_Half |
9736                                 ADVERTISED_1000baseT_Full;
9737
9738                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9739                         mask |= ADVERTISED_100baseT_Half |
9740                                 ADVERTISED_100baseT_Full |
9741                                 ADVERTISED_10baseT_Half |
9742                                 ADVERTISED_10baseT_Full |
9743                                 ADVERTISED_TP;
9744                 else
9745                         mask |= ADVERTISED_FIBRE;
9746
9747                 if (cmd->advertising & ~mask)
9748                         return -EINVAL;
9749
9750                 mask &= (ADVERTISED_1000baseT_Half |
9751                          ADVERTISED_1000baseT_Full |
9752                          ADVERTISED_100baseT_Half |
9753                          ADVERTISED_100baseT_Full |
9754                          ADVERTISED_10baseT_Half |
9755                          ADVERTISED_10baseT_Full);
9756
9757                 cmd->advertising &= mask;
9758         } else {
9759                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9760                         if (cmd->speed != SPEED_1000)
9761                                 return -EINVAL;
9762
9763                         if (cmd->duplex != DUPLEX_FULL)
9764                                 return -EINVAL;
9765                 } else {
9766                         if (cmd->speed != SPEED_100 &&
9767                             cmd->speed != SPEED_10)
9768                                 return -EINVAL;
9769                 }
9770         }
9771
9772         tg3_full_lock(tp, 0);
9773
9774         tp->link_config.autoneg = cmd->autoneg;
9775         if (cmd->autoneg == AUTONEG_ENABLE) {
9776                 tp->link_config.advertising = (cmd->advertising |
9777                                               ADVERTISED_Autoneg);
9778                 tp->link_config.speed = SPEED_INVALID;
9779                 tp->link_config.duplex = DUPLEX_INVALID;
9780         } else {
9781                 tp->link_config.advertising = 0;
9782                 tp->link_config.speed = cmd->speed;
9783                 tp->link_config.duplex = cmd->duplex;
9784         }
9785
9786         tp->link_config.orig_speed = tp->link_config.speed;
9787         tp->link_config.orig_duplex = tp->link_config.duplex;
9788         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9789
9790         if (netif_running(dev))
9791                 tg3_setup_phy(tp, 1);
9792
9793         tg3_full_unlock(tp);
9794
9795         return 0;
9796 }
9797
9798 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9799 {
9800         struct tg3 *tp = netdev_priv(dev);
9801
9802         strcpy(info->driver, DRV_MODULE_NAME);
9803         strcpy(info->version, DRV_MODULE_VERSION);
9804         strcpy(info->fw_version, tp->fw_ver);
9805         strcpy(info->bus_info, pci_name(tp->pdev));
9806 }
9807
9808 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9809 {
9810         struct tg3 *tp = netdev_priv(dev);
9811
9812         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9813             device_can_wakeup(&tp->pdev->dev))
9814                 wol->supported = WAKE_MAGIC;
9815         else
9816                 wol->supported = 0;
9817         wol->wolopts = 0;
9818         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9819             device_can_wakeup(&tp->pdev->dev))
9820                 wol->wolopts = WAKE_MAGIC;
9821         memset(&wol->sopass, 0, sizeof(wol->sopass));
9822 }
9823
9824 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9825 {
9826         struct tg3 *tp = netdev_priv(dev);
9827         struct device *dp = &tp->pdev->dev;
9828
9829         if (wol->wolopts & ~WAKE_MAGIC)
9830                 return -EINVAL;
9831         if ((wol->wolopts & WAKE_MAGIC) &&
9832             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9833                 return -EINVAL;
9834
9835         spin_lock_bh(&tp->lock);
9836         if (wol->wolopts & WAKE_MAGIC) {
9837                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9838                 device_set_wakeup_enable(dp, true);
9839         } else {
9840                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9841                 device_set_wakeup_enable(dp, false);
9842         }
9843         spin_unlock_bh(&tp->lock);
9844
9845         return 0;
9846 }
9847
9848 static u32 tg3_get_msglevel(struct net_device *dev)
9849 {
9850         struct tg3 *tp = netdev_priv(dev);
9851         return tp->msg_enable;
9852 }
9853
9854 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9855 {
9856         struct tg3 *tp = netdev_priv(dev);
9857         tp->msg_enable = value;
9858 }
9859
9860 static int tg3_set_tso(struct net_device *dev, u32 value)
9861 {
9862         struct tg3 *tp = netdev_priv(dev);
9863
9864         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9865                 if (value)
9866                         return -EINVAL;
9867                 return 0;
9868         }
9869         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9870             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9871              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9872                 if (value) {
9873                         dev->features |= NETIF_F_TSO6;
9874                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9875                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9876                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9877                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9878                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9879                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9880                                 dev->features |= NETIF_F_TSO_ECN;
9881                 } else
9882                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9883         }
9884         return ethtool_op_set_tso(dev, value);
9885 }
9886
9887 static int tg3_nway_reset(struct net_device *dev)
9888 {
9889         struct tg3 *tp = netdev_priv(dev);
9890         int r;
9891
9892         if (!netif_running(dev))
9893                 return -EAGAIN;
9894
9895         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9896                 return -EINVAL;
9897
9898         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9899                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9900                         return -EAGAIN;
9901                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9902         } else {
9903                 u32 bmcr;
9904
9905                 spin_lock_bh(&tp->lock);
9906                 r = -EINVAL;
9907                 tg3_readphy(tp, MII_BMCR, &bmcr);
9908                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9909                     ((bmcr & BMCR_ANENABLE) ||
9910                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9911                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9912                                                    BMCR_ANENABLE);
9913                         r = 0;
9914                 }
9915                 spin_unlock_bh(&tp->lock);
9916         }
9917
9918         return r;
9919 }
9920
9921 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9922 {
9923         struct tg3 *tp = netdev_priv(dev);
9924
9925         ering->rx_max_pending = tp->rx_std_ring_mask;
9926         ering->rx_mini_max_pending = 0;
9927         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9928                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
9929         else
9930                 ering->rx_jumbo_max_pending = 0;
9931
9932         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9933
9934         ering->rx_pending = tp->rx_pending;
9935         ering->rx_mini_pending = 0;
9936         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9937                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9938         else
9939                 ering->rx_jumbo_pending = 0;
9940
9941         ering->tx_pending = tp->napi[0].tx_pending;
9942 }
9943
9944 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9945 {
9946         struct tg3 *tp = netdev_priv(dev);
9947         int i, irq_sync = 0, err = 0;
9948
9949         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
9950             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
9951             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9952             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9953             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9954              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9955                 return -EINVAL;
9956
9957         if (netif_running(dev)) {
9958                 tg3_phy_stop(tp);
9959                 tg3_netif_stop(tp);
9960                 irq_sync = 1;
9961         }
9962
9963         tg3_full_lock(tp, irq_sync);
9964
9965         tp->rx_pending = ering->rx_pending;
9966
9967         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9968             tp->rx_pending > 63)
9969                 tp->rx_pending = 63;
9970         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9971
9972         for (i = 0; i < tp->irq_max; i++)
9973                 tp->napi[i].tx_pending = ering->tx_pending;
9974
9975         if (netif_running(dev)) {
9976                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9977                 err = tg3_restart_hw(tp, 1);
9978                 if (!err)
9979                         tg3_netif_start(tp);
9980         }
9981
9982         tg3_full_unlock(tp);
9983
9984         if (irq_sync && !err)
9985                 tg3_phy_start(tp);
9986
9987         return err;
9988 }
9989
9990 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9991 {
9992         struct tg3 *tp = netdev_priv(dev);
9993
9994         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9995
9996         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9997                 epause->rx_pause = 1;
9998         else
9999                 epause->rx_pause = 0;
10000
10001         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10002                 epause->tx_pause = 1;
10003         else
10004                 epause->tx_pause = 0;
10005 }
10006
10007 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10008 {
10009         struct tg3 *tp = netdev_priv(dev);
10010         int err = 0;
10011
10012         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10013                 u32 newadv;
10014                 struct phy_device *phydev;
10015
10016                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10017
10018                 if (!(phydev->supported & SUPPORTED_Pause) ||
10019                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10020                      (epause->rx_pause != epause->tx_pause)))
10021                         return -EINVAL;
10022
10023                 tp->link_config.flowctrl = 0;
10024                 if (epause->rx_pause) {
10025                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10026
10027                         if (epause->tx_pause) {
10028                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10029                                 newadv = ADVERTISED_Pause;
10030                         } else
10031                                 newadv = ADVERTISED_Pause |
10032                                          ADVERTISED_Asym_Pause;
10033                 } else if (epause->tx_pause) {
10034                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10035                         newadv = ADVERTISED_Asym_Pause;
10036                 } else
10037                         newadv = 0;
10038
10039                 if (epause->autoneg)
10040                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10041                 else
10042                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10043
10044                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10045                         u32 oldadv = phydev->advertising &
10046                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10047                         if (oldadv != newadv) {
10048                                 phydev->advertising &=
10049                                         ~(ADVERTISED_Pause |
10050                                           ADVERTISED_Asym_Pause);
10051                                 phydev->advertising |= newadv;
10052                                 if (phydev->autoneg) {
10053                                         /*
10054                                          * Always renegotiate the link to
10055                                          * inform our link partner of our
10056                                          * flow control settings, even if the
10057                                          * flow control is forced.  Let
10058                                          * tg3_adjust_link() do the final
10059                                          * flow control setup.
10060                                          */
10061                                         return phy_start_aneg(phydev);
10062                                 }
10063                         }
10064
10065                         if (!epause->autoneg)
10066                                 tg3_setup_flow_control(tp, 0, 0);
10067                 } else {
10068                         tp->link_config.orig_advertising &=
10069                                         ~(ADVERTISED_Pause |
10070                                           ADVERTISED_Asym_Pause);
10071                         tp->link_config.orig_advertising |= newadv;
10072                 }
10073         } else {
10074                 int irq_sync = 0;
10075
10076                 if (netif_running(dev)) {
10077                         tg3_netif_stop(tp);
10078                         irq_sync = 1;
10079                 }
10080
10081                 tg3_full_lock(tp, irq_sync);
10082
10083                 if (epause->autoneg)
10084                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10085                 else
10086                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10087                 if (epause->rx_pause)
10088                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10089                 else
10090                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10091                 if (epause->tx_pause)
10092                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10093                 else
10094                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10095
10096                 if (netif_running(dev)) {
10097                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10098                         err = tg3_restart_hw(tp, 1);
10099                         if (!err)
10100                                 tg3_netif_start(tp);
10101                 }
10102
10103                 tg3_full_unlock(tp);
10104         }
10105
10106         return err;
10107 }
10108
10109 static u32 tg3_get_rx_csum(struct net_device *dev)
10110 {
10111         struct tg3 *tp = netdev_priv(dev);
10112         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10113 }
10114
10115 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10116 {
10117         struct tg3 *tp = netdev_priv(dev);
10118
10119         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10120                 if (data != 0)
10121                         return -EINVAL;
10122                 return 0;
10123         }
10124
10125         spin_lock_bh(&tp->lock);
10126         if (data)
10127                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10128         else
10129                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10130         spin_unlock_bh(&tp->lock);
10131
10132         return 0;
10133 }
10134
10135 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10136 {
10137         struct tg3 *tp = netdev_priv(dev);
10138
10139         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10140                 if (data != 0)
10141                         return -EINVAL;
10142                 return 0;
10143         }
10144
10145         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10146                 ethtool_op_set_tx_ipv6_csum(dev, data);
10147         else
10148                 ethtool_op_set_tx_csum(dev, data);
10149
10150         return 0;
10151 }
10152
10153 static int tg3_get_sset_count(struct net_device *dev, int sset)
10154 {
10155         switch (sset) {
10156         case ETH_SS_TEST:
10157                 return TG3_NUM_TEST;
10158         case ETH_SS_STATS:
10159                 return TG3_NUM_STATS;
10160         default:
10161                 return -EOPNOTSUPP;
10162         }
10163 }
10164
10165 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10166 {
10167         switch (stringset) {
10168         case ETH_SS_STATS:
10169                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10170                 break;
10171         case ETH_SS_TEST:
10172                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10173                 break;
10174         default:
10175                 WARN_ON(1);     /* we need a WARN() */
10176                 break;
10177         }
10178 }
10179
10180 static int tg3_phys_id(struct net_device *dev, u32 data)
10181 {
10182         struct tg3 *tp = netdev_priv(dev);
10183         int i;
10184
10185         if (!netif_running(tp->dev))
10186                 return -EAGAIN;
10187
10188         if (data == 0)
10189                 data = UINT_MAX / 2;
10190
10191         for (i = 0; i < (data * 2); i++) {
10192                 if ((i % 2) == 0)
10193                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10194                                            LED_CTRL_1000MBPS_ON |
10195                                            LED_CTRL_100MBPS_ON |
10196                                            LED_CTRL_10MBPS_ON |
10197                                            LED_CTRL_TRAFFIC_OVERRIDE |
10198                                            LED_CTRL_TRAFFIC_BLINK |
10199                                            LED_CTRL_TRAFFIC_LED);
10200
10201                 else
10202                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10203                                            LED_CTRL_TRAFFIC_OVERRIDE);
10204
10205                 if (msleep_interruptible(500))
10206                         break;
10207         }
10208         tw32(MAC_LED_CTRL, tp->led_ctrl);
10209         return 0;
10210 }
10211
10212 static void tg3_get_ethtool_stats(struct net_device *dev,
10213                                    struct ethtool_stats *estats, u64 *tmp_stats)
10214 {
10215         struct tg3 *tp = netdev_priv(dev);
10216         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10217 }
10218
10219 #define NVRAM_TEST_SIZE 0x100
10220 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10221 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10222 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10223 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10224 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10225
10226 static int tg3_test_nvram(struct tg3 *tp)
10227 {
10228         u32 csum, magic;
10229         __be32 *buf;
10230         int i, j, k, err = 0, size;
10231
10232         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10233                 return 0;
10234
10235         if (tg3_nvram_read(tp, 0, &magic) != 0)
10236                 return -EIO;
10237
10238         if (magic == TG3_EEPROM_MAGIC)
10239                 size = NVRAM_TEST_SIZE;
10240         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10241                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10242                     TG3_EEPROM_SB_FORMAT_1) {
10243                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10244                         case TG3_EEPROM_SB_REVISION_0:
10245                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10246                                 break;
10247                         case TG3_EEPROM_SB_REVISION_2:
10248                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10249                                 break;
10250                         case TG3_EEPROM_SB_REVISION_3:
10251                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10252                                 break;
10253                         default:
10254                                 return 0;
10255                         }
10256                 } else
10257                         return 0;
10258         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10259                 size = NVRAM_SELFBOOT_HW_SIZE;
10260         else
10261                 return -EIO;
10262
10263         buf = kmalloc(size, GFP_KERNEL);
10264         if (buf == NULL)
10265                 return -ENOMEM;
10266
10267         err = -EIO;
10268         for (i = 0, j = 0; i < size; i += 4, j++) {
10269                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10270                 if (err)
10271                         break;
10272         }
10273         if (i < size)
10274                 goto out;
10275
10276         /* Selfboot format */
10277         magic = be32_to_cpu(buf[0]);
10278         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10279             TG3_EEPROM_MAGIC_FW) {
10280                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10281
10282                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10283                     TG3_EEPROM_SB_REVISION_2) {
10284                         /* For rev 2, the csum doesn't include the MBA. */
10285                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10286                                 csum8 += buf8[i];
10287                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10288                                 csum8 += buf8[i];
10289                 } else {
10290                         for (i = 0; i < size; i++)
10291                                 csum8 += buf8[i];
10292                 }
10293
10294                 if (csum8 == 0) {
10295                         err = 0;
10296                         goto out;
10297                 }
10298
10299                 err = -EIO;
10300                 goto out;
10301         }
10302
10303         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10304             TG3_EEPROM_MAGIC_HW) {
10305                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10306                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10307                 u8 *buf8 = (u8 *) buf;
10308
10309                 /* Separate the parity bits and the data bytes.  */
10310                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10311                         if ((i == 0) || (i == 8)) {
10312                                 int l;
10313                                 u8 msk;
10314
10315                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10316                                         parity[k++] = buf8[i] & msk;
10317                                 i++;
10318                         } else if (i == 16) {
10319                                 int l;
10320                                 u8 msk;
10321
10322                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10323                                         parity[k++] = buf8[i] & msk;
10324                                 i++;
10325
10326                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10327                                         parity[k++] = buf8[i] & msk;
10328                                 i++;
10329                         }
10330                         data[j++] = buf8[i];
10331                 }
10332
10333                 err = -EIO;
10334                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10335                         u8 hw8 = hweight8(data[i]);
10336
10337                         if ((hw8 & 0x1) && parity[i])
10338                                 goto out;
10339                         else if (!(hw8 & 0x1) && !parity[i])
10340                                 goto out;
10341                 }
10342                 err = 0;
10343                 goto out;
10344         }
10345
10346         /* Bootstrap checksum at offset 0x10 */
10347         csum = calc_crc((unsigned char *) buf, 0x10);
10348         if (csum != be32_to_cpu(buf[0x10/4]))
10349                 goto out;
10350
10351         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10352         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10353         if (csum != be32_to_cpu(buf[0xfc/4]))
10354                 goto out;
10355
10356         err = 0;
10357
10358 out:
10359         kfree(buf);
10360         return err;
10361 }
10362
10363 #define TG3_SERDES_TIMEOUT_SEC  2
10364 #define TG3_COPPER_TIMEOUT_SEC  6
10365
10366 static int tg3_test_link(struct tg3 *tp)
10367 {
10368         int i, max;
10369
10370         if (!netif_running(tp->dev))
10371                 return -ENODEV;
10372
10373         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10374                 max = TG3_SERDES_TIMEOUT_SEC;
10375         else
10376                 max = TG3_COPPER_TIMEOUT_SEC;
10377
10378         for (i = 0; i < max; i++) {
10379                 if (netif_carrier_ok(tp->dev))
10380                         return 0;
10381
10382                 if (msleep_interruptible(1000))
10383                         break;
10384         }
10385
10386         return -EIO;
10387 }
10388
10389 /* Only test the commonly used registers */
10390 static int tg3_test_registers(struct tg3 *tp)
10391 {
10392         int i, is_5705, is_5750;
10393         u32 offset, read_mask, write_mask, val, save_val, read_val;
10394         static struct {
10395                 u16 offset;
10396                 u16 flags;
10397 #define TG3_FL_5705     0x1
10398 #define TG3_FL_NOT_5705 0x2
10399 #define TG3_FL_NOT_5788 0x4
10400 #define TG3_FL_NOT_5750 0x8
10401                 u32 read_mask;
10402                 u32 write_mask;
10403         } reg_tbl[] = {
10404                 /* MAC Control Registers */
10405                 { MAC_MODE, TG3_FL_NOT_5705,
10406                         0x00000000, 0x00ef6f8c },
10407                 { MAC_MODE, TG3_FL_5705,
10408                         0x00000000, 0x01ef6b8c },
10409                 { MAC_STATUS, TG3_FL_NOT_5705,
10410                         0x03800107, 0x00000000 },
10411                 { MAC_STATUS, TG3_FL_5705,
10412                         0x03800100, 0x00000000 },
10413                 { MAC_ADDR_0_HIGH, 0x0000,
10414                         0x00000000, 0x0000ffff },
10415                 { MAC_ADDR_0_LOW, 0x0000,
10416                         0x00000000, 0xffffffff },
10417                 { MAC_RX_MTU_SIZE, 0x0000,
10418                         0x00000000, 0x0000ffff },
10419                 { MAC_TX_MODE, 0x0000,
10420                         0x00000000, 0x00000070 },
10421                 { MAC_TX_LENGTHS, 0x0000,
10422                         0x00000000, 0x00003fff },
10423                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10424                         0x00000000, 0x000007fc },
10425                 { MAC_RX_MODE, TG3_FL_5705,
10426                         0x00000000, 0x000007dc },
10427                 { MAC_HASH_REG_0, 0x0000,
10428                         0x00000000, 0xffffffff },
10429                 { MAC_HASH_REG_1, 0x0000,
10430                         0x00000000, 0xffffffff },
10431                 { MAC_HASH_REG_2, 0x0000,
10432                         0x00000000, 0xffffffff },
10433                 { MAC_HASH_REG_3, 0x0000,
10434                         0x00000000, 0xffffffff },
10435
10436                 /* Receive Data and Receive BD Initiator Control Registers. */
10437                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10438                         0x00000000, 0xffffffff },
10439                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10440                         0x00000000, 0xffffffff },
10441                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10442                         0x00000000, 0x00000003 },
10443                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10444                         0x00000000, 0xffffffff },
10445                 { RCVDBDI_STD_BD+0, 0x0000,
10446                         0x00000000, 0xffffffff },
10447                 { RCVDBDI_STD_BD+4, 0x0000,
10448                         0x00000000, 0xffffffff },
10449                 { RCVDBDI_STD_BD+8, 0x0000,
10450                         0x00000000, 0xffff0002 },
10451                 { RCVDBDI_STD_BD+0xc, 0x0000,
10452                         0x00000000, 0xffffffff },
10453
10454                 /* Receive BD Initiator Control Registers. */
10455                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10456                         0x00000000, 0xffffffff },
10457                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10458                         0x00000000, 0x000003ff },
10459                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10460                         0x00000000, 0xffffffff },
10461
10462                 /* Host Coalescing Control Registers. */
10463                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10464                         0x00000000, 0x00000004 },
10465                 { HOSTCC_MODE, TG3_FL_5705,
10466                         0x00000000, 0x000000f6 },
10467                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10468                         0x00000000, 0xffffffff },
10469                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10470                         0x00000000, 0x000003ff },
10471                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10472                         0x00000000, 0xffffffff },
10473                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10474                         0x00000000, 0x000003ff },
10475                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10476                         0x00000000, 0xffffffff },
10477                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10478                         0x00000000, 0x000000ff },
10479                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10480                         0x00000000, 0xffffffff },
10481                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10482                         0x00000000, 0x000000ff },
10483                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10484                         0x00000000, 0xffffffff },
10485                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10486                         0x00000000, 0xffffffff },
10487                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10488                         0x00000000, 0xffffffff },
10489                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10490                         0x00000000, 0x000000ff },
10491                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10492                         0x00000000, 0xffffffff },
10493                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10494                         0x00000000, 0x000000ff },
10495                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10496                         0x00000000, 0xffffffff },
10497                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10498                         0x00000000, 0xffffffff },
10499                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10500                         0x00000000, 0xffffffff },
10501                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10502                         0x00000000, 0xffffffff },
10503                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10504                         0x00000000, 0xffffffff },
10505                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10506                         0xffffffff, 0x00000000 },
10507                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10508                         0xffffffff, 0x00000000 },
10509
10510                 /* Buffer Manager Control Registers. */
10511                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10512                         0x00000000, 0x007fff80 },
10513                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10514                         0x00000000, 0x007fffff },
10515                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10516                         0x00000000, 0x0000003f },
10517                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10518                         0x00000000, 0x000001ff },
10519                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10520                         0x00000000, 0x000001ff },
10521                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10522                         0xffffffff, 0x00000000 },
10523                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10524                         0xffffffff, 0x00000000 },
10525
10526                 /* Mailbox Registers */
10527                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10528                         0x00000000, 0x000001ff },
10529                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10530                         0x00000000, 0x000001ff },
10531                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10532                         0x00000000, 0x000007ff },
10533                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10534                         0x00000000, 0x000001ff },
10535
10536                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10537         };
10538
10539         is_5705 = is_5750 = 0;
10540         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10541                 is_5705 = 1;
10542                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10543                         is_5750 = 1;
10544         }
10545
10546         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10547                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10548                         continue;
10549
10550                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10551                         continue;
10552
10553                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10554                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10555                         continue;
10556
10557                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10558                         continue;
10559
10560                 offset = (u32) reg_tbl[i].offset;
10561                 read_mask = reg_tbl[i].read_mask;
10562                 write_mask = reg_tbl[i].write_mask;
10563
10564                 /* Save the original register content */
10565                 save_val = tr32(offset);
10566
10567                 /* Determine the read-only value. */
10568                 read_val = save_val & read_mask;
10569
10570                 /* Write zero to the register, then make sure the read-only bits
10571                  * are not changed and the read/write bits are all zeros.
10572                  */
10573                 tw32(offset, 0);
10574
10575                 val = tr32(offset);
10576
10577                 /* Test the read-only and read/write bits. */
10578                 if (((val & read_mask) != read_val) || (val & write_mask))
10579                         goto out;
10580
10581                 /* Write ones to all the bits defined by RdMask and WrMask, then
10582                  * make sure the read-only bits are not changed and the
10583                  * read/write bits are all ones.
10584                  */
10585                 tw32(offset, read_mask | write_mask);
10586
10587                 val = tr32(offset);
10588
10589                 /* Test the read-only bits. */
10590                 if ((val & read_mask) != read_val)
10591                         goto out;
10592
10593                 /* Test the read/write bits. */
10594                 if ((val & write_mask) != write_mask)
10595                         goto out;
10596
10597                 tw32(offset, save_val);
10598         }
10599
10600         return 0;
10601
10602 out:
10603         if (netif_msg_hw(tp))
10604                 netdev_err(tp->dev,
10605                            "Register test failed at offset %x\n", offset);
10606         tw32(offset, save_val);
10607         return -EIO;
10608 }
10609
10610 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10611 {
10612         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10613         int i;
10614         u32 j;
10615
10616         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10617                 for (j = 0; j < len; j += 4) {
10618                         u32 val;
10619
10620                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10621                         tg3_read_mem(tp, offset + j, &val);
10622                         if (val != test_pattern[i])
10623                                 return -EIO;
10624                 }
10625         }
10626         return 0;
10627 }
10628
10629 static int tg3_test_memory(struct tg3 *tp)
10630 {
10631         static struct mem_entry {
10632                 u32 offset;
10633                 u32 len;
10634         } mem_tbl_570x[] = {
10635                 { 0x00000000, 0x00b50},
10636                 { 0x00002000, 0x1c000},
10637                 { 0xffffffff, 0x00000}
10638         }, mem_tbl_5705[] = {
10639                 { 0x00000100, 0x0000c},
10640                 { 0x00000200, 0x00008},
10641                 { 0x00004000, 0x00800},
10642                 { 0x00006000, 0x01000},
10643                 { 0x00008000, 0x02000},
10644                 { 0x00010000, 0x0e000},
10645                 { 0xffffffff, 0x00000}
10646         }, mem_tbl_5755[] = {
10647                 { 0x00000200, 0x00008},
10648                 { 0x00004000, 0x00800},
10649                 { 0x00006000, 0x00800},
10650                 { 0x00008000, 0x02000},
10651                 { 0x00010000, 0x0c000},
10652                 { 0xffffffff, 0x00000}
10653         }, mem_tbl_5906[] = {
10654                 { 0x00000200, 0x00008},
10655                 { 0x00004000, 0x00400},
10656                 { 0x00006000, 0x00400},
10657                 { 0x00008000, 0x01000},
10658                 { 0x00010000, 0x01000},
10659                 { 0xffffffff, 0x00000}
10660         }, mem_tbl_5717[] = {
10661                 { 0x00000200, 0x00008},
10662                 { 0x00010000, 0x0a000},
10663                 { 0x00020000, 0x13c00},
10664                 { 0xffffffff, 0x00000}
10665         }, mem_tbl_57765[] = {
10666                 { 0x00000200, 0x00008},
10667                 { 0x00004000, 0x00800},
10668                 { 0x00006000, 0x09800},
10669                 { 0x00010000, 0x0a000},
10670                 { 0xffffffff, 0x00000}
10671         };
10672         struct mem_entry *mem_tbl;
10673         int err = 0;
10674         int i;
10675
10676         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10677             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10678                 mem_tbl = mem_tbl_5717;
10679         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10680                 mem_tbl = mem_tbl_57765;
10681         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10682                 mem_tbl = mem_tbl_5755;
10683         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10684                 mem_tbl = mem_tbl_5906;
10685         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10686                 mem_tbl = mem_tbl_5705;
10687         else
10688                 mem_tbl = mem_tbl_570x;
10689
10690         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10691                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10692                 if (err)
10693                         break;
10694         }
10695
10696         return err;
10697 }
10698
10699 #define TG3_MAC_LOOPBACK        0
10700 #define TG3_PHY_LOOPBACK        1
10701
10702 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10703 {
10704         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10705         u32 desc_idx, coal_now;
10706         struct sk_buff *skb, *rx_skb;
10707         u8 *tx_data;
10708         dma_addr_t map;
10709         int num_pkts, tx_len, rx_len, i, err;
10710         struct tg3_rx_buffer_desc *desc;
10711         struct tg3_napi *tnapi, *rnapi;
10712         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10713
10714         tnapi = &tp->napi[0];
10715         rnapi = &tp->napi[0];
10716         if (tp->irq_cnt > 1) {
10717                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10718                         rnapi = &tp->napi[1];
10719                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10720                         tnapi = &tp->napi[1];
10721         }
10722         coal_now = tnapi->coal_now | rnapi->coal_now;
10723
10724         if (loopback_mode == TG3_MAC_LOOPBACK) {
10725                 /* HW errata - mac loopback fails in some cases on 5780.
10726                  * Normal traffic and PHY loopback are not affected by
10727                  * errata.
10728                  */
10729                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10730                         return 0;
10731
10732                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10733                            MAC_MODE_PORT_INT_LPBACK;
10734                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10735                         mac_mode |= MAC_MODE_LINK_POLARITY;
10736                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10737                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10738                 else
10739                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10740                 tw32(MAC_MODE, mac_mode);
10741         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10742                 u32 val;
10743
10744                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10745                         tg3_phy_fet_toggle_apd(tp, false);
10746                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10747                 } else
10748                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10749
10750                 tg3_phy_toggle_automdix(tp, 0);
10751
10752                 tg3_writephy(tp, MII_BMCR, val);
10753                 udelay(40);
10754
10755                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10756                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10757                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10758                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10759                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10760                         /* The write needs to be flushed for the AC131 */
10761                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10762                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10763                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10764                 } else
10765                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10766
10767                 /* reset to prevent losing 1st rx packet intermittently */
10768                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10769                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10770                         udelay(10);
10771                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10772                 }
10773                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10774                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10775                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10776                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10777                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10778                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10779                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10780                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10781                 }
10782                 tw32(MAC_MODE, mac_mode);
10783         } else {
10784                 return -EINVAL;
10785         }
10786
10787         err = -EIO;
10788
10789         tx_len = 1514;
10790         skb = netdev_alloc_skb(tp->dev, tx_len);
10791         if (!skb)
10792                 return -ENOMEM;
10793
10794         tx_data = skb_put(skb, tx_len);
10795         memcpy(tx_data, tp->dev->dev_addr, 6);
10796         memset(tx_data + 6, 0x0, 8);
10797
10798         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10799
10800         for (i = 14; i < tx_len; i++)
10801                 tx_data[i] = (u8) (i & 0xff);
10802
10803         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10804         if (pci_dma_mapping_error(tp->pdev, map)) {
10805                 dev_kfree_skb(skb);
10806                 return -EIO;
10807         }
10808
10809         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10810                rnapi->coal_now);
10811
10812         udelay(10);
10813
10814         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10815
10816         num_pkts = 0;
10817
10818         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10819
10820         tnapi->tx_prod++;
10821         num_pkts++;
10822
10823         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10824         tr32_mailbox(tnapi->prodmbox);
10825
10826         udelay(10);
10827
10828         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10829         for (i = 0; i < 35; i++) {
10830                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10831                        coal_now);
10832
10833                 udelay(10);
10834
10835                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10836                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10837                 if ((tx_idx == tnapi->tx_prod) &&
10838                     (rx_idx == (rx_start_idx + num_pkts)))
10839                         break;
10840         }
10841
10842         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10843         dev_kfree_skb(skb);
10844
10845         if (tx_idx != tnapi->tx_prod)
10846                 goto out;
10847
10848         if (rx_idx != rx_start_idx + num_pkts)
10849                 goto out;
10850
10851         desc = &rnapi->rx_rcb[rx_start_idx];
10852         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10853         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10854         if (opaque_key != RXD_OPAQUE_RING_STD)
10855                 goto out;
10856
10857         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10858             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10859                 goto out;
10860
10861         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10862         if (rx_len != tx_len)
10863                 goto out;
10864
10865         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10866
10867         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10868         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10869
10870         for (i = 14; i < tx_len; i++) {
10871                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10872                         goto out;
10873         }
10874         err = 0;
10875
10876         /* tg3_free_rings will unmap and free the rx_skb */
10877 out:
10878         return err;
10879 }
10880
10881 #define TG3_MAC_LOOPBACK_FAILED         1
10882 #define TG3_PHY_LOOPBACK_FAILED         2
10883 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10884                                          TG3_PHY_LOOPBACK_FAILED)
10885
10886 static int tg3_test_loopback(struct tg3 *tp)
10887 {
10888         int err = 0;
10889         u32 cpmuctrl = 0;
10890
10891         if (!netif_running(tp->dev))
10892                 return TG3_LOOPBACK_FAILED;
10893
10894         err = tg3_reset_hw(tp, 1);
10895         if (err)
10896                 return TG3_LOOPBACK_FAILED;
10897
10898         /* Turn off gphy autopowerdown. */
10899         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10900                 tg3_phy_toggle_apd(tp, false);
10901
10902         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10903                 int i;
10904                 u32 status;
10905
10906                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10907
10908                 /* Wait for up to 40 microseconds to acquire lock. */
10909                 for (i = 0; i < 4; i++) {
10910                         status = tr32(TG3_CPMU_MUTEX_GNT);
10911                         if (status == CPMU_MUTEX_GNT_DRIVER)
10912                                 break;
10913                         udelay(10);
10914                 }
10915
10916                 if (status != CPMU_MUTEX_GNT_DRIVER)
10917                         return TG3_LOOPBACK_FAILED;
10918
10919                 /* Turn off link-based power management. */
10920                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10921                 tw32(TG3_CPMU_CTRL,
10922                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10923                                   CPMU_CTRL_LINK_AWARE_MODE));
10924         }
10925
10926         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10927                 err |= TG3_MAC_LOOPBACK_FAILED;
10928
10929         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10930                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10931
10932                 /* Release the mutex */
10933                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10934         }
10935
10936         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10937             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10938                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10939                         err |= TG3_PHY_LOOPBACK_FAILED;
10940         }
10941
10942         /* Re-enable gphy autopowerdown. */
10943         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10944                 tg3_phy_toggle_apd(tp, true);
10945
10946         return err;
10947 }
10948
10949 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10950                           u64 *data)
10951 {
10952         struct tg3 *tp = netdev_priv(dev);
10953
10954         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10955                 tg3_set_power_state(tp, PCI_D0);
10956
10957         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10958
10959         if (tg3_test_nvram(tp) != 0) {
10960                 etest->flags |= ETH_TEST_FL_FAILED;
10961                 data[0] = 1;
10962         }
10963         if (tg3_test_link(tp) != 0) {
10964                 etest->flags |= ETH_TEST_FL_FAILED;
10965                 data[1] = 1;
10966         }
10967         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10968                 int err, err2 = 0, irq_sync = 0;
10969
10970                 if (netif_running(dev)) {
10971                         tg3_phy_stop(tp);
10972                         tg3_netif_stop(tp);
10973                         irq_sync = 1;
10974                 }
10975
10976                 tg3_full_lock(tp, irq_sync);
10977
10978                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10979                 err = tg3_nvram_lock(tp);
10980                 tg3_halt_cpu(tp, RX_CPU_BASE);
10981                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10982                         tg3_halt_cpu(tp, TX_CPU_BASE);
10983                 if (!err)
10984                         tg3_nvram_unlock(tp);
10985
10986                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10987                         tg3_phy_reset(tp);
10988
10989                 if (tg3_test_registers(tp) != 0) {
10990                         etest->flags |= ETH_TEST_FL_FAILED;
10991                         data[2] = 1;
10992                 }
10993                 if (tg3_test_memory(tp) != 0) {
10994                         etest->flags |= ETH_TEST_FL_FAILED;
10995                         data[3] = 1;
10996                 }
10997                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10998                         etest->flags |= ETH_TEST_FL_FAILED;
10999
11000                 tg3_full_unlock(tp);
11001
11002                 if (tg3_test_interrupt(tp) != 0) {
11003                         etest->flags |= ETH_TEST_FL_FAILED;
11004                         data[5] = 1;
11005                 }
11006
11007                 tg3_full_lock(tp, 0);
11008
11009                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11010                 if (netif_running(dev)) {
11011                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11012                         err2 = tg3_restart_hw(tp, 1);
11013                         if (!err2)
11014                                 tg3_netif_start(tp);
11015                 }
11016
11017                 tg3_full_unlock(tp);
11018
11019                 if (irq_sync && !err2)
11020                         tg3_phy_start(tp);
11021         }
11022         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11023                 tg3_set_power_state(tp, PCI_D3hot);
11024
11025 }
11026
11027 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11028 {
11029         struct mii_ioctl_data *data = if_mii(ifr);
11030         struct tg3 *tp = netdev_priv(dev);
11031         int err;
11032
11033         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11034                 struct phy_device *phydev;
11035                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11036                         return -EAGAIN;
11037                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11038                 return phy_mii_ioctl(phydev, ifr, cmd);
11039         }
11040
11041         switch (cmd) {
11042         case SIOCGMIIPHY:
11043                 data->phy_id = tp->phy_addr;
11044
11045                 /* fallthru */
11046         case SIOCGMIIREG: {
11047                 u32 mii_regval;
11048
11049                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11050                         break;                  /* We have no PHY */
11051
11052                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11053                         return -EAGAIN;
11054
11055                 spin_lock_bh(&tp->lock);
11056                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11057                 spin_unlock_bh(&tp->lock);
11058
11059                 data->val_out = mii_regval;
11060
11061                 return err;
11062         }
11063
11064         case SIOCSMIIREG:
11065                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11066                         break;                  /* We have no PHY */
11067
11068                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11069                         return -EAGAIN;
11070
11071                 spin_lock_bh(&tp->lock);
11072                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11073                 spin_unlock_bh(&tp->lock);
11074
11075                 return err;
11076
11077         default:
11078                 /* do nothing */
11079                 break;
11080         }
11081         return -EOPNOTSUPP;
11082 }
11083
11084 #if TG3_VLAN_TAG_USED
11085 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11086 {
11087         struct tg3 *tp = netdev_priv(dev);
11088
11089         if (!netif_running(dev)) {
11090                 tp->vlgrp = grp;
11091                 return;
11092         }
11093
11094         tg3_netif_stop(tp);
11095
11096         tg3_full_lock(tp, 0);
11097
11098         tp->vlgrp = grp;
11099
11100         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11101         __tg3_set_rx_mode(dev);
11102
11103         tg3_netif_start(tp);
11104
11105         tg3_full_unlock(tp);
11106 }
11107 #endif
11108
11109 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11110 {
11111         struct tg3 *tp = netdev_priv(dev);
11112
11113         memcpy(ec, &tp->coal, sizeof(*ec));
11114         return 0;
11115 }
11116
11117 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11118 {
11119         struct tg3 *tp = netdev_priv(dev);
11120         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11121         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11122
11123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11124                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11125                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11126                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11127                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11128         }
11129
11130         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11131             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11132             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11133             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11134             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11135             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11136             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11137             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11138             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11139             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11140                 return -EINVAL;
11141
11142         /* No rx interrupts will be generated if both are zero */
11143         if ((ec->rx_coalesce_usecs == 0) &&
11144             (ec->rx_max_coalesced_frames == 0))
11145                 return -EINVAL;
11146
11147         /* No tx interrupts will be generated if both are zero */
11148         if ((ec->tx_coalesce_usecs == 0) &&
11149             (ec->tx_max_coalesced_frames == 0))
11150                 return -EINVAL;
11151
11152         /* Only copy relevant parameters, ignore all others. */
11153         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11154         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11155         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11156         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11157         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11158         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11159         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11160         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11161         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11162
11163         if (netif_running(dev)) {
11164                 tg3_full_lock(tp, 0);
11165                 __tg3_set_coalesce(tp, &tp->coal);
11166                 tg3_full_unlock(tp);
11167         }
11168         return 0;
11169 }
11170
11171 static const struct ethtool_ops tg3_ethtool_ops = {
11172         .get_settings           = tg3_get_settings,
11173         .set_settings           = tg3_set_settings,
11174         .get_drvinfo            = tg3_get_drvinfo,
11175         .get_regs_len           = tg3_get_regs_len,
11176         .get_regs               = tg3_get_regs,
11177         .get_wol                = tg3_get_wol,
11178         .set_wol                = tg3_set_wol,
11179         .get_msglevel           = tg3_get_msglevel,
11180         .set_msglevel           = tg3_set_msglevel,
11181         .nway_reset             = tg3_nway_reset,
11182         .get_link               = ethtool_op_get_link,
11183         .get_eeprom_len         = tg3_get_eeprom_len,
11184         .get_eeprom             = tg3_get_eeprom,
11185         .set_eeprom             = tg3_set_eeprom,
11186         .get_ringparam          = tg3_get_ringparam,
11187         .set_ringparam          = tg3_set_ringparam,
11188         .get_pauseparam         = tg3_get_pauseparam,
11189         .set_pauseparam         = tg3_set_pauseparam,
11190         .get_rx_csum            = tg3_get_rx_csum,
11191         .set_rx_csum            = tg3_set_rx_csum,
11192         .set_tx_csum            = tg3_set_tx_csum,
11193         .set_sg                 = ethtool_op_set_sg,
11194         .set_tso                = tg3_set_tso,
11195         .self_test              = tg3_self_test,
11196         .get_strings            = tg3_get_strings,
11197         .phys_id                = tg3_phys_id,
11198         .get_ethtool_stats      = tg3_get_ethtool_stats,
11199         .get_coalesce           = tg3_get_coalesce,
11200         .set_coalesce           = tg3_set_coalesce,
11201         .get_sset_count         = tg3_get_sset_count,
11202 };
11203
11204 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11205 {
11206         u32 cursize, val, magic;
11207
11208         tp->nvram_size = EEPROM_CHIP_SIZE;
11209
11210         if (tg3_nvram_read(tp, 0, &magic) != 0)
11211                 return;
11212
11213         if ((magic != TG3_EEPROM_MAGIC) &&
11214             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11215             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11216                 return;
11217
11218         /*
11219          * Size the chip by reading offsets at increasing powers of two.
11220          * When we encounter our validation signature, we know the addressing
11221          * has wrapped around, and thus have our chip size.
11222          */
11223         cursize = 0x10;
11224
11225         while (cursize < tp->nvram_size) {
11226                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11227                         return;
11228
11229                 if (val == magic)
11230                         break;
11231
11232                 cursize <<= 1;
11233         }
11234
11235         tp->nvram_size = cursize;
11236 }
11237
11238 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11239 {
11240         u32 val;
11241
11242         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11243             tg3_nvram_read(tp, 0, &val) != 0)
11244                 return;
11245
11246         /* Selfboot format */
11247         if (val != TG3_EEPROM_MAGIC) {
11248                 tg3_get_eeprom_size(tp);
11249                 return;
11250         }
11251
11252         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11253                 if (val != 0) {
11254                         /* This is confusing.  We want to operate on the
11255                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11256                          * call will read from NVRAM and byteswap the data
11257                          * according to the byteswapping settings for all
11258                          * other register accesses.  This ensures the data we
11259                          * want will always reside in the lower 16-bits.
11260                          * However, the data in NVRAM is in LE format, which
11261                          * means the data from the NVRAM read will always be
11262                          * opposite the endianness of the CPU.  The 16-bit
11263                          * byteswap then brings the data to CPU endianness.
11264                          */
11265                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11266                         return;
11267                 }
11268         }
11269         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11270 }
11271
11272 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11273 {
11274         u32 nvcfg1;
11275
11276         nvcfg1 = tr32(NVRAM_CFG1);
11277         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11278                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11279         } else {
11280                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11281                 tw32(NVRAM_CFG1, nvcfg1);
11282         }
11283
11284         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11285             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11286                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11287                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11288                         tp->nvram_jedecnum = JEDEC_ATMEL;
11289                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11290                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11291                         break;
11292                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11293                         tp->nvram_jedecnum = JEDEC_ATMEL;
11294                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11295                         break;
11296                 case FLASH_VENDOR_ATMEL_EEPROM:
11297                         tp->nvram_jedecnum = JEDEC_ATMEL;
11298                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11299                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11300                         break;
11301                 case FLASH_VENDOR_ST:
11302                         tp->nvram_jedecnum = JEDEC_ST;
11303                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11304                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11305                         break;
11306                 case FLASH_VENDOR_SAIFUN:
11307                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11308                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11309                         break;
11310                 case FLASH_VENDOR_SST_SMALL:
11311                 case FLASH_VENDOR_SST_LARGE:
11312                         tp->nvram_jedecnum = JEDEC_SST;
11313                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11314                         break;
11315                 }
11316         } else {
11317                 tp->nvram_jedecnum = JEDEC_ATMEL;
11318                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11319                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11320         }
11321 }
11322
11323 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11324 {
11325         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11326         case FLASH_5752PAGE_SIZE_256:
11327                 tp->nvram_pagesize = 256;
11328                 break;
11329         case FLASH_5752PAGE_SIZE_512:
11330                 tp->nvram_pagesize = 512;
11331                 break;
11332         case FLASH_5752PAGE_SIZE_1K:
11333                 tp->nvram_pagesize = 1024;
11334                 break;
11335         case FLASH_5752PAGE_SIZE_2K:
11336                 tp->nvram_pagesize = 2048;
11337                 break;
11338         case FLASH_5752PAGE_SIZE_4K:
11339                 tp->nvram_pagesize = 4096;
11340                 break;
11341         case FLASH_5752PAGE_SIZE_264:
11342                 tp->nvram_pagesize = 264;
11343                 break;
11344         case FLASH_5752PAGE_SIZE_528:
11345                 tp->nvram_pagesize = 528;
11346                 break;
11347         }
11348 }
11349
11350 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11351 {
11352         u32 nvcfg1;
11353
11354         nvcfg1 = tr32(NVRAM_CFG1);
11355
11356         /* NVRAM protection for TPM */
11357         if (nvcfg1 & (1 << 27))
11358                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11359
11360         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11361         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11362         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11363                 tp->nvram_jedecnum = JEDEC_ATMEL;
11364                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365                 break;
11366         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11367                 tp->nvram_jedecnum = JEDEC_ATMEL;
11368                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11369                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11370                 break;
11371         case FLASH_5752VENDOR_ST_M45PE10:
11372         case FLASH_5752VENDOR_ST_M45PE20:
11373         case FLASH_5752VENDOR_ST_M45PE40:
11374                 tp->nvram_jedecnum = JEDEC_ST;
11375                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11377                 break;
11378         }
11379
11380         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11381                 tg3_nvram_get_pagesize(tp, nvcfg1);
11382         } else {
11383                 /* For eeprom, set pagesize to maximum eeprom size */
11384                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11385
11386                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11387                 tw32(NVRAM_CFG1, nvcfg1);
11388         }
11389 }
11390
11391 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11392 {
11393         u32 nvcfg1, protect = 0;
11394
11395         nvcfg1 = tr32(NVRAM_CFG1);
11396
11397         /* NVRAM protection for TPM */
11398         if (nvcfg1 & (1 << 27)) {
11399                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11400                 protect = 1;
11401         }
11402
11403         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11404         switch (nvcfg1) {
11405         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11406         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11407         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11408         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11409                 tp->nvram_jedecnum = JEDEC_ATMEL;
11410                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11411                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11412                 tp->nvram_pagesize = 264;
11413                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11414                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11415                         tp->nvram_size = (protect ? 0x3e200 :
11416                                           TG3_NVRAM_SIZE_512KB);
11417                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11418                         tp->nvram_size = (protect ? 0x1f200 :
11419                                           TG3_NVRAM_SIZE_256KB);
11420                 else
11421                         tp->nvram_size = (protect ? 0x1f200 :
11422                                           TG3_NVRAM_SIZE_128KB);
11423                 break;
11424         case FLASH_5752VENDOR_ST_M45PE10:
11425         case FLASH_5752VENDOR_ST_M45PE20:
11426         case FLASH_5752VENDOR_ST_M45PE40:
11427                 tp->nvram_jedecnum = JEDEC_ST;
11428                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11429                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11430                 tp->nvram_pagesize = 256;
11431                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11432                         tp->nvram_size = (protect ?
11433                                           TG3_NVRAM_SIZE_64KB :
11434                                           TG3_NVRAM_SIZE_128KB);
11435                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11436                         tp->nvram_size = (protect ?
11437                                           TG3_NVRAM_SIZE_64KB :
11438                                           TG3_NVRAM_SIZE_256KB);
11439                 else
11440                         tp->nvram_size = (protect ?
11441                                           TG3_NVRAM_SIZE_128KB :
11442                                           TG3_NVRAM_SIZE_512KB);
11443                 break;
11444         }
11445 }
11446
11447 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11448 {
11449         u32 nvcfg1;
11450
11451         nvcfg1 = tr32(NVRAM_CFG1);
11452
11453         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11454         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11455         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11456         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11457         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11458                 tp->nvram_jedecnum = JEDEC_ATMEL;
11459                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11461
11462                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11463                 tw32(NVRAM_CFG1, nvcfg1);
11464                 break;
11465         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11466         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11467         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11468         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11469                 tp->nvram_jedecnum = JEDEC_ATMEL;
11470                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11471                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11472                 tp->nvram_pagesize = 264;
11473                 break;
11474         case FLASH_5752VENDOR_ST_M45PE10:
11475         case FLASH_5752VENDOR_ST_M45PE20:
11476         case FLASH_5752VENDOR_ST_M45PE40:
11477                 tp->nvram_jedecnum = JEDEC_ST;
11478                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11479                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11480                 tp->nvram_pagesize = 256;
11481                 break;
11482         }
11483 }
11484
11485 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11486 {
11487         u32 nvcfg1, protect = 0;
11488
11489         nvcfg1 = tr32(NVRAM_CFG1);
11490
11491         /* NVRAM protection for TPM */
11492         if (nvcfg1 & (1 << 27)) {
11493                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11494                 protect = 1;
11495         }
11496
11497         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11498         switch (nvcfg1) {
11499         case FLASH_5761VENDOR_ATMEL_ADB021D:
11500         case FLASH_5761VENDOR_ATMEL_ADB041D:
11501         case FLASH_5761VENDOR_ATMEL_ADB081D:
11502         case FLASH_5761VENDOR_ATMEL_ADB161D:
11503         case FLASH_5761VENDOR_ATMEL_MDB021D:
11504         case FLASH_5761VENDOR_ATMEL_MDB041D:
11505         case FLASH_5761VENDOR_ATMEL_MDB081D:
11506         case FLASH_5761VENDOR_ATMEL_MDB161D:
11507                 tp->nvram_jedecnum = JEDEC_ATMEL;
11508                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11509                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11510                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11511                 tp->nvram_pagesize = 256;
11512                 break;
11513         case FLASH_5761VENDOR_ST_A_M45PE20:
11514         case FLASH_5761VENDOR_ST_A_M45PE40:
11515         case FLASH_5761VENDOR_ST_A_M45PE80:
11516         case FLASH_5761VENDOR_ST_A_M45PE16:
11517         case FLASH_5761VENDOR_ST_M_M45PE20:
11518         case FLASH_5761VENDOR_ST_M_M45PE40:
11519         case FLASH_5761VENDOR_ST_M_M45PE80:
11520         case FLASH_5761VENDOR_ST_M_M45PE16:
11521                 tp->nvram_jedecnum = JEDEC_ST;
11522                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11523                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11524                 tp->nvram_pagesize = 256;
11525                 break;
11526         }
11527
11528         if (protect) {
11529                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11530         } else {
11531                 switch (nvcfg1) {
11532                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11533                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11534                 case FLASH_5761VENDOR_ST_A_M45PE16:
11535                 case FLASH_5761VENDOR_ST_M_M45PE16:
11536                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11537                         break;
11538                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11539                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11540                 case FLASH_5761VENDOR_ST_A_M45PE80:
11541                 case FLASH_5761VENDOR_ST_M_M45PE80:
11542                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11543                         break;
11544                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11545                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11546                 case FLASH_5761VENDOR_ST_A_M45PE40:
11547                 case FLASH_5761VENDOR_ST_M_M45PE40:
11548                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11549                         break;
11550                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11551                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11552                 case FLASH_5761VENDOR_ST_A_M45PE20:
11553                 case FLASH_5761VENDOR_ST_M_M45PE20:
11554                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11555                         break;
11556                 }
11557         }
11558 }
11559
11560 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11561 {
11562         tp->nvram_jedecnum = JEDEC_ATMEL;
11563         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11564         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11565 }
11566
11567 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11568 {
11569         u32 nvcfg1;
11570
11571         nvcfg1 = tr32(NVRAM_CFG1);
11572
11573         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11574         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11575         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11576                 tp->nvram_jedecnum = JEDEC_ATMEL;
11577                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11578                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11579
11580                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11581                 tw32(NVRAM_CFG1, nvcfg1);
11582                 return;
11583         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11584         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11585         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11586         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11587         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11588         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11589         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11590                 tp->nvram_jedecnum = JEDEC_ATMEL;
11591                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11592                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11593
11594                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11595                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11596                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11597                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11598                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11599                         break;
11600                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11601                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11602                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11603                         break;
11604                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11605                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11606                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11607                         break;
11608                 }
11609                 break;
11610         case FLASH_5752VENDOR_ST_M45PE10:
11611         case FLASH_5752VENDOR_ST_M45PE20:
11612         case FLASH_5752VENDOR_ST_M45PE40:
11613                 tp->nvram_jedecnum = JEDEC_ST;
11614                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11615                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11616
11617                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11618                 case FLASH_5752VENDOR_ST_M45PE10:
11619                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11620                         break;
11621                 case FLASH_5752VENDOR_ST_M45PE20:
11622                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11623                         break;
11624                 case FLASH_5752VENDOR_ST_M45PE40:
11625                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11626                         break;
11627                 }
11628                 break;
11629         default:
11630                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11631                 return;
11632         }
11633
11634         tg3_nvram_get_pagesize(tp, nvcfg1);
11635         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11636                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11637 }
11638
11639
11640 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11641 {
11642         u32 nvcfg1;
11643
11644         nvcfg1 = tr32(NVRAM_CFG1);
11645
11646         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11647         case FLASH_5717VENDOR_ATMEL_EEPROM:
11648         case FLASH_5717VENDOR_MICRO_EEPROM:
11649                 tp->nvram_jedecnum = JEDEC_ATMEL;
11650                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11651                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11652
11653                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11654                 tw32(NVRAM_CFG1, nvcfg1);
11655                 return;
11656         case FLASH_5717VENDOR_ATMEL_MDB011D:
11657         case FLASH_5717VENDOR_ATMEL_ADB011B:
11658         case FLASH_5717VENDOR_ATMEL_ADB011D:
11659         case FLASH_5717VENDOR_ATMEL_MDB021D:
11660         case FLASH_5717VENDOR_ATMEL_ADB021B:
11661         case FLASH_5717VENDOR_ATMEL_ADB021D:
11662         case FLASH_5717VENDOR_ATMEL_45USPT:
11663                 tp->nvram_jedecnum = JEDEC_ATMEL;
11664                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11665                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11666
11667                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11668                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11669                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11670                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11671                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11672                         break;
11673                 default:
11674                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11675                         break;
11676                 }
11677                 break;
11678         case FLASH_5717VENDOR_ST_M_M25PE10:
11679         case FLASH_5717VENDOR_ST_A_M25PE10:
11680         case FLASH_5717VENDOR_ST_M_M45PE10:
11681         case FLASH_5717VENDOR_ST_A_M45PE10:
11682         case FLASH_5717VENDOR_ST_M_M25PE20:
11683         case FLASH_5717VENDOR_ST_A_M25PE20:
11684         case FLASH_5717VENDOR_ST_M_M45PE20:
11685         case FLASH_5717VENDOR_ST_A_M45PE20:
11686         case FLASH_5717VENDOR_ST_25USPT:
11687         case FLASH_5717VENDOR_ST_45USPT:
11688                 tp->nvram_jedecnum = JEDEC_ST;
11689                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11690                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11691
11692                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11693                 case FLASH_5717VENDOR_ST_M_M25PE20:
11694                 case FLASH_5717VENDOR_ST_A_M25PE20:
11695                 case FLASH_5717VENDOR_ST_M_M45PE20:
11696                 case FLASH_5717VENDOR_ST_A_M45PE20:
11697                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11698                         break;
11699                 default:
11700                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11701                         break;
11702                 }
11703                 break;
11704         default:
11705                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11706                 return;
11707         }
11708
11709         tg3_nvram_get_pagesize(tp, nvcfg1);
11710         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11711                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11712 }
11713
11714 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11715 static void __devinit tg3_nvram_init(struct tg3 *tp)
11716 {
11717         tw32_f(GRC_EEPROM_ADDR,
11718              (EEPROM_ADDR_FSM_RESET |
11719               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11720                EEPROM_ADDR_CLKPERD_SHIFT)));
11721
11722         msleep(1);
11723
11724         /* Enable seeprom accesses. */
11725         tw32_f(GRC_LOCAL_CTRL,
11726              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11727         udelay(100);
11728
11729         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11730             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11731                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11732
11733                 if (tg3_nvram_lock(tp)) {
11734                         netdev_warn(tp->dev,
11735                                     "Cannot get nvram lock, %s failed\n",
11736                                     __func__);
11737                         return;
11738                 }
11739                 tg3_enable_nvram_access(tp);
11740
11741                 tp->nvram_size = 0;
11742
11743                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11744                         tg3_get_5752_nvram_info(tp);
11745                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11746                         tg3_get_5755_nvram_info(tp);
11747                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11748                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11749                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11750                         tg3_get_5787_nvram_info(tp);
11751                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11752                         tg3_get_5761_nvram_info(tp);
11753                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11754                         tg3_get_5906_nvram_info(tp);
11755                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11756                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11757                         tg3_get_57780_nvram_info(tp);
11758                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11759                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11760                         tg3_get_5717_nvram_info(tp);
11761                 else
11762                         tg3_get_nvram_info(tp);
11763
11764                 if (tp->nvram_size == 0)
11765                         tg3_get_nvram_size(tp);
11766
11767                 tg3_disable_nvram_access(tp);
11768                 tg3_nvram_unlock(tp);
11769
11770         } else {
11771                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11772
11773                 tg3_get_eeprom_size(tp);
11774         }
11775 }
11776
11777 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11778                                     u32 offset, u32 len, u8 *buf)
11779 {
11780         int i, j, rc = 0;
11781         u32 val;
11782
11783         for (i = 0; i < len; i += 4) {
11784                 u32 addr;
11785                 __be32 data;
11786
11787                 addr = offset + i;
11788
11789                 memcpy(&data, buf + i, 4);
11790
11791                 /*
11792                  * The SEEPROM interface expects the data to always be opposite
11793                  * the native endian format.  We accomplish this by reversing
11794                  * all the operations that would have been performed on the
11795                  * data from a call to tg3_nvram_read_be32().
11796                  */
11797                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11798
11799                 val = tr32(GRC_EEPROM_ADDR);
11800                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11801
11802                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11803                         EEPROM_ADDR_READ);
11804                 tw32(GRC_EEPROM_ADDR, val |
11805                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11806                         (addr & EEPROM_ADDR_ADDR_MASK) |
11807                         EEPROM_ADDR_START |
11808                         EEPROM_ADDR_WRITE);
11809
11810                 for (j = 0; j < 1000; j++) {
11811                         val = tr32(GRC_EEPROM_ADDR);
11812
11813                         if (val & EEPROM_ADDR_COMPLETE)
11814                                 break;
11815                         msleep(1);
11816                 }
11817                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11818                         rc = -EBUSY;
11819                         break;
11820                 }
11821         }
11822
11823         return rc;
11824 }
11825
11826 /* offset and length are dword aligned */
11827 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11828                 u8 *buf)
11829 {
11830         int ret = 0;
11831         u32 pagesize = tp->nvram_pagesize;
11832         u32 pagemask = pagesize - 1;
11833         u32 nvram_cmd;
11834         u8 *tmp;
11835
11836         tmp = kmalloc(pagesize, GFP_KERNEL);
11837         if (tmp == NULL)
11838                 return -ENOMEM;
11839
11840         while (len) {
11841                 int j;
11842                 u32 phy_addr, page_off, size;
11843
11844                 phy_addr = offset & ~pagemask;
11845
11846                 for (j = 0; j < pagesize; j += 4) {
11847                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11848                                                   (__be32 *) (tmp + j));
11849                         if (ret)
11850                                 break;
11851                 }
11852                 if (ret)
11853                         break;
11854
11855                 page_off = offset & pagemask;
11856                 size = pagesize;
11857                 if (len < size)
11858                         size = len;
11859
11860                 len -= size;
11861
11862                 memcpy(tmp + page_off, buf, size);
11863
11864                 offset = offset + (pagesize - page_off);
11865
11866                 tg3_enable_nvram_access(tp);
11867
11868                 /*
11869                  * Before we can erase the flash page, we need
11870                  * to issue a special "write enable" command.
11871                  */
11872                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11873
11874                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11875                         break;
11876
11877                 /* Erase the target page */
11878                 tw32(NVRAM_ADDR, phy_addr);
11879
11880                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11881                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11882
11883                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11884                         break;
11885
11886                 /* Issue another write enable to start the write. */
11887                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11888
11889                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11890                         break;
11891
11892                 for (j = 0; j < pagesize; j += 4) {
11893                         __be32 data;
11894
11895                         data = *((__be32 *) (tmp + j));
11896
11897                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11898
11899                         tw32(NVRAM_ADDR, phy_addr + j);
11900
11901                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11902                                 NVRAM_CMD_WR;
11903
11904                         if (j == 0)
11905                                 nvram_cmd |= NVRAM_CMD_FIRST;
11906                         else if (j == (pagesize - 4))
11907                                 nvram_cmd |= NVRAM_CMD_LAST;
11908
11909                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11910                                 break;
11911                 }
11912                 if (ret)
11913                         break;
11914         }
11915
11916         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11917         tg3_nvram_exec_cmd(tp, nvram_cmd);
11918
11919         kfree(tmp);
11920
11921         return ret;
11922 }
11923
11924 /* offset and length are dword aligned */
11925 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11926                 u8 *buf)
11927 {
11928         int i, ret = 0;
11929
11930         for (i = 0; i < len; i += 4, offset += 4) {
11931                 u32 page_off, phy_addr, nvram_cmd;
11932                 __be32 data;
11933
11934                 memcpy(&data, buf + i, 4);
11935                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11936
11937                 page_off = offset % tp->nvram_pagesize;
11938
11939                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11940
11941                 tw32(NVRAM_ADDR, phy_addr);
11942
11943                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11944
11945                 if (page_off == 0 || i == 0)
11946                         nvram_cmd |= NVRAM_CMD_FIRST;
11947                 if (page_off == (tp->nvram_pagesize - 4))
11948                         nvram_cmd |= NVRAM_CMD_LAST;
11949
11950                 if (i == (len - 4))
11951                         nvram_cmd |= NVRAM_CMD_LAST;
11952
11953                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11954                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11955                     (tp->nvram_jedecnum == JEDEC_ST) &&
11956                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11957
11958                         if ((ret = tg3_nvram_exec_cmd(tp,
11959                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11960                                 NVRAM_CMD_DONE)))
11961
11962                                 break;
11963                 }
11964                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11965                         /* We always do complete word writes to eeprom. */
11966                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11967                 }
11968
11969                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11970                         break;
11971         }
11972         return ret;
11973 }
11974
11975 /* offset and length are dword aligned */
11976 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11977 {
11978         int ret;
11979
11980         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11981                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11982                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11983                 udelay(40);
11984         }
11985
11986         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11987                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11988         } else {
11989                 u32 grc_mode;
11990
11991                 ret = tg3_nvram_lock(tp);
11992                 if (ret)
11993                         return ret;
11994
11995                 tg3_enable_nvram_access(tp);
11996                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11997                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11998                         tw32(NVRAM_WRITE1, 0x406);
11999
12000                 grc_mode = tr32(GRC_MODE);
12001                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12002
12003                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12004                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12005
12006                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12007                                 buf);
12008                 } else {
12009                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12010                                 buf);
12011                 }
12012
12013                 grc_mode = tr32(GRC_MODE);
12014                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12015
12016                 tg3_disable_nvram_access(tp);
12017                 tg3_nvram_unlock(tp);
12018         }
12019
12020         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12021                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12022                 udelay(40);
12023         }
12024
12025         return ret;
12026 }
12027
12028 struct subsys_tbl_ent {
12029         u16 subsys_vendor, subsys_devid;
12030         u32 phy_id;
12031 };
12032
12033 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12034         /* Broadcom boards. */
12035         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12036           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12037         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12038           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12039         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12040           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12041         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12042           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12043         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12044           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12045         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12046           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12047         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12048           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12049         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12050           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12051         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12052           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12053         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12054           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12055         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12056           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12057
12058         /* 3com boards. */
12059         { TG3PCI_SUBVENDOR_ID_3COM,
12060           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12061         { TG3PCI_SUBVENDOR_ID_3COM,
12062           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12063         { TG3PCI_SUBVENDOR_ID_3COM,
12064           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12065         { TG3PCI_SUBVENDOR_ID_3COM,
12066           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12067         { TG3PCI_SUBVENDOR_ID_3COM,
12068           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12069
12070         /* DELL boards. */
12071         { TG3PCI_SUBVENDOR_ID_DELL,
12072           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12073         { TG3PCI_SUBVENDOR_ID_DELL,
12074           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12075         { TG3PCI_SUBVENDOR_ID_DELL,
12076           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12077         { TG3PCI_SUBVENDOR_ID_DELL,
12078           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12079
12080         /* Compaq boards. */
12081         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12082           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12083         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12084           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12085         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12086           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12087         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12088           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12089         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12090           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12091
12092         /* IBM boards. */
12093         { TG3PCI_SUBVENDOR_ID_IBM,
12094           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12095 };
12096
12097 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12098 {
12099         int i;
12100
12101         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12102                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12103                      tp->pdev->subsystem_vendor) &&
12104                     (subsys_id_to_phy_id[i].subsys_devid ==
12105                      tp->pdev->subsystem_device))
12106                         return &subsys_id_to_phy_id[i];
12107         }
12108         return NULL;
12109 }
12110
12111 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12112 {
12113         u32 val;
12114         u16 pmcsr;
12115
12116         /* On some early chips the SRAM cannot be accessed in D3hot state,
12117          * so need make sure we're in D0.
12118          */
12119         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12120         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12121         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12122         msleep(1);
12123
12124         /* Make sure register accesses (indirect or otherwise)
12125          * will function correctly.
12126          */
12127         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12128                                tp->misc_host_ctrl);
12129
12130         /* The memory arbiter has to be enabled in order for SRAM accesses
12131          * to succeed.  Normally on powerup the tg3 chip firmware will make
12132          * sure it is enabled, but other entities such as system netboot
12133          * code might disable it.
12134          */
12135         val = tr32(MEMARB_MODE);
12136         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12137
12138         tp->phy_id = TG3_PHY_ID_INVALID;
12139         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12140
12141         /* Assume an onboard device and WOL capable by default.  */
12142         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12143
12144         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12145                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12146                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12147                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12148                 }
12149                 val = tr32(VCPU_CFGSHDW);
12150                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12151                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12152                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12153                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12154                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12155                 goto done;
12156         }
12157
12158         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12159         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12160                 u32 nic_cfg, led_cfg;
12161                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12162                 int eeprom_phy_serdes = 0;
12163
12164                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12165                 tp->nic_sram_data_cfg = nic_cfg;
12166
12167                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12168                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12169                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12170                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12171                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12172                     (ver > 0) && (ver < 0x100))
12173                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12174
12175                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12176                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12177
12178                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12179                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12180                         eeprom_phy_serdes = 1;
12181
12182                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12183                 if (nic_phy_id != 0) {
12184                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12185                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12186
12187                         eeprom_phy_id  = (id1 >> 16) << 10;
12188                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12189                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12190                 } else
12191                         eeprom_phy_id = 0;
12192
12193                 tp->phy_id = eeprom_phy_id;
12194                 if (eeprom_phy_serdes) {
12195                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12196                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12197                         else
12198                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12199                 }
12200
12201                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12202                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12203                                     SHASTA_EXT_LED_MODE_MASK);
12204                 else
12205                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12206
12207                 switch (led_cfg) {
12208                 default:
12209                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12210                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12211                         break;
12212
12213                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12214                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12215                         break;
12216
12217                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12218                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12219
12220                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12221                          * read on some older 5700/5701 bootcode.
12222                          */
12223                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12224                             ASIC_REV_5700 ||
12225                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12226                             ASIC_REV_5701)
12227                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12228
12229                         break;
12230
12231                 case SHASTA_EXT_LED_SHARED:
12232                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12233                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12234                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12235                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12236                                                  LED_CTRL_MODE_PHY_2);
12237                         break;
12238
12239                 case SHASTA_EXT_LED_MAC:
12240                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12241                         break;
12242
12243                 case SHASTA_EXT_LED_COMBO:
12244                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12245                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12246                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12247                                                  LED_CTRL_MODE_PHY_2);
12248                         break;
12249
12250                 }
12251
12252                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12253                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12254                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12255                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12256
12257                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12258                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12259
12260                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12261                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12262                         if ((tp->pdev->subsystem_vendor ==
12263                              PCI_VENDOR_ID_ARIMA) &&
12264                             (tp->pdev->subsystem_device == 0x205a ||
12265                              tp->pdev->subsystem_device == 0x2063))
12266                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12267                 } else {
12268                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12269                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12270                 }
12271
12272                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12273                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12274                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12275                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12276                 }
12277
12278                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12279                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12280                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12281
12282                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12283                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12284                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12285
12286                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12287                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12288                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12289
12290                 if (cfg2 & (1 << 17))
12291                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12292
12293                 /* serdes signal pre-emphasis in register 0x590 set by */
12294                 /* bootcode if bit 18 is set */
12295                 if (cfg2 & (1 << 18))
12296                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12297
12298                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12299                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12300                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12301                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12302
12303                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12304                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12305                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12306                         u32 cfg3;
12307
12308                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12309                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12310                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12311                 }
12312
12313                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12314                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12315                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12316                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12317                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12318                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12319         }
12320 done:
12321         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12322         device_set_wakeup_enable(&tp->pdev->dev,
12323                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12324 }
12325
12326 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12327 {
12328         int i;
12329         u32 val;
12330
12331         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12332         tw32(OTP_CTRL, cmd);
12333
12334         /* Wait for up to 1 ms for command to execute. */
12335         for (i = 0; i < 100; i++) {
12336                 val = tr32(OTP_STATUS);
12337                 if (val & OTP_STATUS_CMD_DONE)
12338                         break;
12339                 udelay(10);
12340         }
12341
12342         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12343 }
12344
12345 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12346  * configuration is a 32-bit value that straddles the alignment boundary.
12347  * We do two 32-bit reads and then shift and merge the results.
12348  */
12349 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12350 {
12351         u32 bhalf_otp, thalf_otp;
12352
12353         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12354
12355         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12356                 return 0;
12357
12358         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12359
12360         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12361                 return 0;
12362
12363         thalf_otp = tr32(OTP_READ_DATA);
12364
12365         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12366
12367         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12368                 return 0;
12369
12370         bhalf_otp = tr32(OTP_READ_DATA);
12371
12372         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12373 }
12374
12375 static int __devinit tg3_phy_probe(struct tg3 *tp)
12376 {
12377         u32 hw_phy_id_1, hw_phy_id_2;
12378         u32 hw_phy_id, hw_phy_id_masked;
12379         int err;
12380
12381         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12382                 return tg3_phy_init(tp);
12383
12384         /* Reading the PHY ID register can conflict with ASF
12385          * firmware access to the PHY hardware.
12386          */
12387         err = 0;
12388         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12389             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12390                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12391         } else {
12392                 /* Now read the physical PHY_ID from the chip and verify
12393                  * that it is sane.  If it doesn't look good, we fall back
12394                  * to either the hard-coded table based PHY_ID and failing
12395                  * that the value found in the eeprom area.
12396                  */
12397                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12398                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12399
12400                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12401                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12402                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12403
12404                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12405         }
12406
12407         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12408                 tp->phy_id = hw_phy_id;
12409                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12410                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12411                 else
12412                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12413         } else {
12414                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12415                         /* Do nothing, phy ID already set up in
12416                          * tg3_get_eeprom_hw_cfg().
12417                          */
12418                 } else {
12419                         struct subsys_tbl_ent *p;
12420
12421                         /* No eeprom signature?  Try the hardcoded
12422                          * subsys device table.
12423                          */
12424                         p = tg3_lookup_by_subsys(tp);
12425                         if (!p)
12426                                 return -ENODEV;
12427
12428                         tp->phy_id = p->phy_id;
12429                         if (!tp->phy_id ||
12430                             tp->phy_id == TG3_PHY_ID_BCM8002)
12431                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12432                 }
12433         }
12434
12435         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12436             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12437             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12438                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12439
12440                 tg3_readphy(tp, MII_BMSR, &bmsr);
12441                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12442                     (bmsr & BMSR_LSTATUS))
12443                         goto skip_phy_reset;
12444
12445                 err = tg3_phy_reset(tp);
12446                 if (err)
12447                         return err;
12448
12449                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12450                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12451                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12452                 tg3_ctrl = 0;
12453                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12454                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12455                                     MII_TG3_CTRL_ADV_1000_FULL);
12456                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12457                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12458                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12459                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12460                 }
12461
12462                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12463                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12464                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12465                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12466                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12467
12468                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12469                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12470
12471                         tg3_writephy(tp, MII_BMCR,
12472                                      BMCR_ANENABLE | BMCR_ANRESTART);
12473                 }
12474                 tg3_phy_set_wirespeed(tp);
12475
12476                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12477                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12478                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12479         }
12480
12481 skip_phy_reset:
12482         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12483                 err = tg3_init_5401phy_dsp(tp);
12484                 if (err)
12485                         return err;
12486
12487                 err = tg3_init_5401phy_dsp(tp);
12488         }
12489
12490         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12491                 tp->link_config.advertising =
12492                         (ADVERTISED_1000baseT_Half |
12493                          ADVERTISED_1000baseT_Full |
12494                          ADVERTISED_Autoneg |
12495                          ADVERTISED_FIBRE);
12496         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12497                 tp->link_config.advertising &=
12498                         ~(ADVERTISED_1000baseT_Half |
12499                           ADVERTISED_1000baseT_Full);
12500
12501         return err;
12502 }
12503
12504 static void __devinit tg3_read_vpd(struct tg3 *tp)
12505 {
12506         u8 *vpd_data;
12507         unsigned int block_end, rosize, len;
12508         int j, i = 0;
12509         u32 magic;
12510
12511         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12512             tg3_nvram_read(tp, 0x0, &magic))
12513                 goto out_no_vpd;
12514
12515         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12516         if (!vpd_data)
12517                 goto out_no_vpd;
12518
12519         if (magic == TG3_EEPROM_MAGIC) {
12520                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12521                         u32 tmp;
12522
12523                         /* The data is in little-endian format in NVRAM.
12524                          * Use the big-endian read routines to preserve
12525                          * the byte order as it exists in NVRAM.
12526                          */
12527                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12528                                 goto out_not_found;
12529
12530                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12531                 }
12532         } else {
12533                 ssize_t cnt;
12534                 unsigned int pos = 0;
12535
12536                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12537                         cnt = pci_read_vpd(tp->pdev, pos,
12538                                            TG3_NVM_VPD_LEN - pos,
12539                                            &vpd_data[pos]);
12540                         if (cnt == -ETIMEDOUT || -EINTR)
12541                                 cnt = 0;
12542                         else if (cnt < 0)
12543                                 goto out_not_found;
12544                 }
12545                 if (pos != TG3_NVM_VPD_LEN)
12546                         goto out_not_found;
12547         }
12548
12549         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12550                              PCI_VPD_LRDT_RO_DATA);
12551         if (i < 0)
12552                 goto out_not_found;
12553
12554         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12555         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12556         i += PCI_VPD_LRDT_TAG_SIZE;
12557
12558         if (block_end > TG3_NVM_VPD_LEN)
12559                 goto out_not_found;
12560
12561         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12562                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12563         if (j > 0) {
12564                 len = pci_vpd_info_field_size(&vpd_data[j]);
12565
12566                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12567                 if (j + len > block_end || len != 4 ||
12568                     memcmp(&vpd_data[j], "1028", 4))
12569                         goto partno;
12570
12571                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12572                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12573                 if (j < 0)
12574                         goto partno;
12575
12576                 len = pci_vpd_info_field_size(&vpd_data[j]);
12577
12578                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12579                 if (j + len > block_end)
12580                         goto partno;
12581
12582                 memcpy(tp->fw_ver, &vpd_data[j], len);
12583                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12584         }
12585
12586 partno:
12587         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12588                                       PCI_VPD_RO_KEYWORD_PARTNO);
12589         if (i < 0)
12590                 goto out_not_found;
12591
12592         len = pci_vpd_info_field_size(&vpd_data[i]);
12593
12594         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12595         if (len > TG3_BPN_SIZE ||
12596             (len + i) > TG3_NVM_VPD_LEN)
12597                 goto out_not_found;
12598
12599         memcpy(tp->board_part_number, &vpd_data[i], len);
12600
12601 out_not_found:
12602         kfree(vpd_data);
12603         if (tp->board_part_number[0])
12604                 return;
12605
12606 out_no_vpd:
12607         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12608                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12609                         strcpy(tp->board_part_number, "BCM5717");
12610                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12611                         strcpy(tp->board_part_number, "BCM5718");
12612                 else
12613                         goto nomatch;
12614         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12615                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12616                         strcpy(tp->board_part_number, "BCM57780");
12617                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12618                         strcpy(tp->board_part_number, "BCM57760");
12619                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12620                         strcpy(tp->board_part_number, "BCM57790");
12621                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12622                         strcpy(tp->board_part_number, "BCM57788");
12623                 else
12624                         goto nomatch;
12625         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12626                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12627                         strcpy(tp->board_part_number, "BCM57761");
12628                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12629                         strcpy(tp->board_part_number, "BCM57765");
12630                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12631                         strcpy(tp->board_part_number, "BCM57781");
12632                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12633                         strcpy(tp->board_part_number, "BCM57785");
12634                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12635                         strcpy(tp->board_part_number, "BCM57791");
12636                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12637                         strcpy(tp->board_part_number, "BCM57795");
12638                 else
12639                         goto nomatch;
12640         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12641                 strcpy(tp->board_part_number, "BCM95906");
12642         } else {
12643 nomatch:
12644                 strcpy(tp->board_part_number, "none");
12645         }
12646 }
12647
12648 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12649 {
12650         u32 val;
12651
12652         if (tg3_nvram_read(tp, offset, &val) ||
12653             (val & 0xfc000000) != 0x0c000000 ||
12654             tg3_nvram_read(tp, offset + 4, &val) ||
12655             val != 0)
12656                 return 0;
12657
12658         return 1;
12659 }
12660
12661 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12662 {
12663         u32 val, offset, start, ver_offset;
12664         int i, dst_off;
12665         bool newver = false;
12666
12667         if (tg3_nvram_read(tp, 0xc, &offset) ||
12668             tg3_nvram_read(tp, 0x4, &start))
12669                 return;
12670
12671         offset = tg3_nvram_logical_addr(tp, offset);
12672
12673         if (tg3_nvram_read(tp, offset, &val))
12674                 return;
12675
12676         if ((val & 0xfc000000) == 0x0c000000) {
12677                 if (tg3_nvram_read(tp, offset + 4, &val))
12678                         return;
12679
12680                 if (val == 0)
12681                         newver = true;
12682         }
12683
12684         dst_off = strlen(tp->fw_ver);
12685
12686         if (newver) {
12687                 if (TG3_VER_SIZE - dst_off < 16 ||
12688                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12689                         return;
12690
12691                 offset = offset + ver_offset - start;
12692                 for (i = 0; i < 16; i += 4) {
12693                         __be32 v;
12694                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12695                                 return;
12696
12697                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12698                 }
12699         } else {
12700                 u32 major, minor;
12701
12702                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12703                         return;
12704
12705                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12706                         TG3_NVM_BCVER_MAJSFT;
12707                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12708                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12709                          "v%d.%02d", major, minor);
12710         }
12711 }
12712
12713 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12714 {
12715         u32 val, major, minor;
12716
12717         /* Use native endian representation */
12718         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12719                 return;
12720
12721         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12722                 TG3_NVM_HWSB_CFG1_MAJSFT;
12723         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12724                 TG3_NVM_HWSB_CFG1_MINSFT;
12725
12726         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12727 }
12728
12729 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12730 {
12731         u32 offset, major, minor, build;
12732
12733         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12734
12735         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12736                 return;
12737
12738         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12739         case TG3_EEPROM_SB_REVISION_0:
12740                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12741                 break;
12742         case TG3_EEPROM_SB_REVISION_2:
12743                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12744                 break;
12745         case TG3_EEPROM_SB_REVISION_3:
12746                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12747                 break;
12748         case TG3_EEPROM_SB_REVISION_4:
12749                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12750                 break;
12751         case TG3_EEPROM_SB_REVISION_5:
12752                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12753                 break;
12754         case TG3_EEPROM_SB_REVISION_6:
12755                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12756                 break;
12757         default:
12758                 return;
12759         }
12760
12761         if (tg3_nvram_read(tp, offset, &val))
12762                 return;
12763
12764         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12765                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12766         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12767                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12768         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12769
12770         if (minor > 99 || build > 26)
12771                 return;
12772
12773         offset = strlen(tp->fw_ver);
12774         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12775                  " v%d.%02d", major, minor);
12776
12777         if (build > 0) {
12778                 offset = strlen(tp->fw_ver);
12779                 if (offset < TG3_VER_SIZE - 1)
12780                         tp->fw_ver[offset] = 'a' + build - 1;
12781         }
12782 }
12783
12784 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12785 {
12786         u32 val, offset, start;
12787         int i, vlen;
12788
12789         for (offset = TG3_NVM_DIR_START;
12790              offset < TG3_NVM_DIR_END;
12791              offset += TG3_NVM_DIRENT_SIZE) {
12792                 if (tg3_nvram_read(tp, offset, &val))
12793                         return;
12794
12795                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12796                         break;
12797         }
12798
12799         if (offset == TG3_NVM_DIR_END)
12800                 return;
12801
12802         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12803                 start = 0x08000000;
12804         else if (tg3_nvram_read(tp, offset - 4, &start))
12805                 return;
12806
12807         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12808             !tg3_fw_img_is_valid(tp, offset) ||
12809             tg3_nvram_read(tp, offset + 8, &val))
12810                 return;
12811
12812         offset += val - start;
12813
12814         vlen = strlen(tp->fw_ver);
12815
12816         tp->fw_ver[vlen++] = ',';
12817         tp->fw_ver[vlen++] = ' ';
12818
12819         for (i = 0; i < 4; i++) {
12820                 __be32 v;
12821                 if (tg3_nvram_read_be32(tp, offset, &v))
12822                         return;
12823
12824                 offset += sizeof(v);
12825
12826                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12827                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12828                         break;
12829                 }
12830
12831                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12832                 vlen += sizeof(v);
12833         }
12834 }
12835
12836 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12837 {
12838         int vlen;
12839         u32 apedata;
12840         char *fwtype;
12841
12842         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12843             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12844                 return;
12845
12846         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12847         if (apedata != APE_SEG_SIG_MAGIC)
12848                 return;
12849
12850         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12851         if (!(apedata & APE_FW_STATUS_READY))
12852                 return;
12853
12854         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12855
12856         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12857                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12858                 fwtype = "NCSI";
12859         } else {
12860                 fwtype = "DASH";
12861         }
12862
12863         vlen = strlen(tp->fw_ver);
12864
12865         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12866                  fwtype,
12867                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12868                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12869                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12870                  (apedata & APE_FW_VERSION_BLDMSK));
12871 }
12872
12873 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12874 {
12875         u32 val;
12876         bool vpd_vers = false;
12877
12878         if (tp->fw_ver[0] != 0)
12879                 vpd_vers = true;
12880
12881         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12882                 strcat(tp->fw_ver, "sb");
12883                 return;
12884         }
12885
12886         if (tg3_nvram_read(tp, 0, &val))
12887                 return;
12888
12889         if (val == TG3_EEPROM_MAGIC)
12890                 tg3_read_bc_ver(tp);
12891         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12892                 tg3_read_sb_ver(tp, val);
12893         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12894                 tg3_read_hwsb_ver(tp);
12895         else
12896                 return;
12897
12898         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12899              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12900                 goto done;
12901
12902         tg3_read_mgmtfw_ver(tp);
12903
12904 done:
12905         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12906 }
12907
12908 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12909
12910 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12911 {
12912 #if TG3_VLAN_TAG_USED
12913         dev->vlan_features |= flags;
12914 #endif
12915 }
12916
12917 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
12918 {
12919         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12920             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12921                 return 4096;
12922         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
12923                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12924                 return 1024;
12925         else
12926                 return 512;
12927 }
12928
12929 static int __devinit tg3_get_invariants(struct tg3 *tp)
12930 {
12931         static struct pci_device_id write_reorder_chipsets[] = {
12932                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12933                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12934                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12935                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12936                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12937                              PCI_DEVICE_ID_VIA_8385_0) },
12938                 { },
12939         };
12940         u32 misc_ctrl_reg;
12941         u32 pci_state_reg, grc_misc_cfg;
12942         u32 val;
12943         u16 pci_cmd;
12944         int err;
12945
12946         /* Force memory write invalidate off.  If we leave it on,
12947          * then on 5700_BX chips we have to enable a workaround.
12948          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12949          * to match the cacheline size.  The Broadcom driver have this
12950          * workaround but turns MWI off all the times so never uses
12951          * it.  This seems to suggest that the workaround is insufficient.
12952          */
12953         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12954         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12955         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12956
12957         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12958          * has the register indirect write enable bit set before
12959          * we try to access any of the MMIO registers.  It is also
12960          * critical that the PCI-X hw workaround situation is decided
12961          * before that as well.
12962          */
12963         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12964                               &misc_ctrl_reg);
12965
12966         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12967                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12969                 u32 prod_id_asic_rev;
12970
12971                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12972                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12973                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12974                         pci_read_config_dword(tp->pdev,
12975                                               TG3PCI_GEN2_PRODID_ASICREV,
12976                                               &prod_id_asic_rev);
12977                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12978                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12979                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12980                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12981                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12982                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12983                         pci_read_config_dword(tp->pdev,
12984                                               TG3PCI_GEN15_PRODID_ASICREV,
12985                                               &prod_id_asic_rev);
12986                 else
12987                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12988                                               &prod_id_asic_rev);
12989
12990                 tp->pci_chip_rev_id = prod_id_asic_rev;
12991         }
12992
12993         /* Wrong chip ID in 5752 A0. This code can be removed later
12994          * as A0 is not in production.
12995          */
12996         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12997                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12998
12999         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13000          * we need to disable memory and use config. cycles
13001          * only to access all registers. The 5702/03 chips
13002          * can mistakenly decode the special cycles from the
13003          * ICH chipsets as memory write cycles, causing corruption
13004          * of register and memory space. Only certain ICH bridges
13005          * will drive special cycles with non-zero data during the
13006          * address phase which can fall within the 5703's address
13007          * range. This is not an ICH bug as the PCI spec allows
13008          * non-zero address during special cycles. However, only
13009          * these ICH bridges are known to drive non-zero addresses
13010          * during special cycles.
13011          *
13012          * Since special cycles do not cross PCI bridges, we only
13013          * enable this workaround if the 5703 is on the secondary
13014          * bus of these ICH bridges.
13015          */
13016         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13017             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13018                 static struct tg3_dev_id {
13019                         u32     vendor;
13020                         u32     device;
13021                         u32     rev;
13022                 } ich_chipsets[] = {
13023                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13024                           PCI_ANY_ID },
13025                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13026                           PCI_ANY_ID },
13027                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13028                           0xa },
13029                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13030                           PCI_ANY_ID },
13031                         { },
13032                 };
13033                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13034                 struct pci_dev *bridge = NULL;
13035
13036                 while (pci_id->vendor != 0) {
13037                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13038                                                 bridge);
13039                         if (!bridge) {
13040                                 pci_id++;
13041                                 continue;
13042                         }
13043                         if (pci_id->rev != PCI_ANY_ID) {
13044                                 if (bridge->revision > pci_id->rev)
13045                                         continue;
13046                         }
13047                         if (bridge->subordinate &&
13048                             (bridge->subordinate->number ==
13049                              tp->pdev->bus->number)) {
13050
13051                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13052                                 pci_dev_put(bridge);
13053                                 break;
13054                         }
13055                 }
13056         }
13057
13058         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13059                 static struct tg3_dev_id {
13060                         u32     vendor;
13061                         u32     device;
13062                 } bridge_chipsets[] = {
13063                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13064                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13065                         { },
13066                 };
13067                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13068                 struct pci_dev *bridge = NULL;
13069
13070                 while (pci_id->vendor != 0) {
13071                         bridge = pci_get_device(pci_id->vendor,
13072                                                 pci_id->device,
13073                                                 bridge);
13074                         if (!bridge) {
13075                                 pci_id++;
13076                                 continue;
13077                         }
13078                         if (bridge->subordinate &&
13079                             (bridge->subordinate->number <=
13080                              tp->pdev->bus->number) &&
13081                             (bridge->subordinate->subordinate >=
13082                              tp->pdev->bus->number)) {
13083                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13084                                 pci_dev_put(bridge);
13085                                 break;
13086                         }
13087                 }
13088         }
13089
13090         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13091          * DMA addresses > 40-bit. This bridge may have other additional
13092          * 57xx devices behind it in some 4-port NIC designs for example.
13093          * Any tg3 device found behind the bridge will also need the 40-bit
13094          * DMA workaround.
13095          */
13096         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13097             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13098                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13099                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13100                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13101         } else {
13102                 struct pci_dev *bridge = NULL;
13103
13104                 do {
13105                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13106                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13107                                                 bridge);
13108                         if (bridge && bridge->subordinate &&
13109                             (bridge->subordinate->number <=
13110                              tp->pdev->bus->number) &&
13111                             (bridge->subordinate->subordinate >=
13112                              tp->pdev->bus->number)) {
13113                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13114                                 pci_dev_put(bridge);
13115                                 break;
13116                         }
13117                 } while (bridge);
13118         }
13119
13120         /* Initialize misc host control in PCI block. */
13121         tp->misc_host_ctrl |= (misc_ctrl_reg &
13122                                MISC_HOST_CTRL_CHIPREV);
13123         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13124                                tp->misc_host_ctrl);
13125
13126         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13127             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13128             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13129                 tp->pdev_peer = tg3_find_peer(tp);
13130
13131         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13132             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13133             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13134                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13135
13136         /* Intentionally exclude ASIC_REV_5906 */
13137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13138             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13139             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13140             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13142             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13143             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13144                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13145
13146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13147             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13148             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13149             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13150             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13151                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13152
13153         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13154             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13155                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13156
13157         /* 5700 B0 chips do not support checksumming correctly due
13158          * to hardware bugs.
13159          */
13160         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13161                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13162         else {
13163                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13164
13165                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13166                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13167                         features |= NETIF_F_IPV6_CSUM;
13168                 tp->dev->features |= features;
13169                 vlan_features_add(tp->dev, features);
13170         }
13171
13172         /* Determine TSO capabilities */
13173         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13174                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13175         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13176                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13177                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13178         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13179                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13180                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13181                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13182                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13183         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13184                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13185                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13186                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13187                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13188                         tp->fw_needed = FIRMWARE_TG3TSO5;
13189                 else
13190                         tp->fw_needed = FIRMWARE_TG3TSO;
13191         }
13192
13193         tp->irq_max = 1;
13194
13195         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13196                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13197                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13198                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13199                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13200                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13201                      tp->pdev_peer == tp->pdev))
13202                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13203
13204                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13205                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13206                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13207                 }
13208
13209                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13210                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13211                         tp->irq_max = TG3_IRQ_MAX_VECS;
13212                 }
13213         }
13214
13215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13217             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13218                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13219         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13220                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13221                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13222         }
13223
13224         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13225                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13226
13227         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13228             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13229             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13230                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13231
13232         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13233                               &pci_state_reg);
13234
13235         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13236         if (tp->pcie_cap != 0) {
13237                 u16 lnkctl;
13238
13239                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13240
13241                 pcie_set_readrq(tp->pdev, 4096);
13242
13243                 pci_read_config_word(tp->pdev,
13244                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13245                                      &lnkctl);
13246                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13247                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13248                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13249                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13250                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13251                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13252                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13253                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13254                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13255                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13256                 }
13257         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13258                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13259         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13260                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13261                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13262                 if (!tp->pcix_cap) {
13263                         dev_err(&tp->pdev->dev,
13264                                 "Cannot find PCI-X capability, aborting\n");
13265                         return -EIO;
13266                 }
13267
13268                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13269                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13270         }
13271
13272         /* If we have an AMD 762 or VIA K8T800 chipset, write
13273          * reordering to the mailbox registers done by the host
13274          * controller can cause major troubles.  We read back from
13275          * every mailbox register write to force the writes to be
13276          * posted to the chip in order.
13277          */
13278         if (pci_dev_present(write_reorder_chipsets) &&
13279             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13280                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13281
13282         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13283                              &tp->pci_cacheline_sz);
13284         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13285                              &tp->pci_lat_timer);
13286         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13287             tp->pci_lat_timer < 64) {
13288                 tp->pci_lat_timer = 64;
13289                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13290                                       tp->pci_lat_timer);
13291         }
13292
13293         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13294                 /* 5700 BX chips need to have their TX producer index
13295                  * mailboxes written twice to workaround a bug.
13296                  */
13297                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13298
13299                 /* If we are in PCI-X mode, enable register write workaround.
13300                  *
13301                  * The workaround is to use indirect register accesses
13302                  * for all chip writes not to mailbox registers.
13303                  */
13304                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13305                         u32 pm_reg;
13306
13307                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13308
13309                         /* The chip can have it's power management PCI config
13310                          * space registers clobbered due to this bug.
13311                          * So explicitly force the chip into D0 here.
13312                          */
13313                         pci_read_config_dword(tp->pdev,
13314                                               tp->pm_cap + PCI_PM_CTRL,
13315                                               &pm_reg);
13316                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13317                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13318                         pci_write_config_dword(tp->pdev,
13319                                                tp->pm_cap + PCI_PM_CTRL,
13320                                                pm_reg);
13321
13322                         /* Also, force SERR#/PERR# in PCI command. */
13323                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13324                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13325                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13326                 }
13327         }
13328
13329         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13330                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13331         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13332                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13333
13334         /* Chip-specific fixup from Broadcom driver */
13335         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13336             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13337                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13338                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13339         }
13340
13341         /* Default fast path register access methods */
13342         tp->read32 = tg3_read32;
13343         tp->write32 = tg3_write32;
13344         tp->read32_mbox = tg3_read32;
13345         tp->write32_mbox = tg3_write32;
13346         tp->write32_tx_mbox = tg3_write32;
13347         tp->write32_rx_mbox = tg3_write32;
13348
13349         /* Various workaround register access methods */
13350         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13351                 tp->write32 = tg3_write_indirect_reg32;
13352         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13353                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13354                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13355                 /*
13356                  * Back to back register writes can cause problems on these
13357                  * chips, the workaround is to read back all reg writes
13358                  * except those to mailbox regs.
13359                  *
13360                  * See tg3_write_indirect_reg32().
13361                  */
13362                 tp->write32 = tg3_write_flush_reg32;
13363         }
13364
13365         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13366             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13367                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13368                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13369                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13370         }
13371
13372         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13373                 tp->read32 = tg3_read_indirect_reg32;
13374                 tp->write32 = tg3_write_indirect_reg32;
13375                 tp->read32_mbox = tg3_read_indirect_mbox;
13376                 tp->write32_mbox = tg3_write_indirect_mbox;
13377                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13378                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13379
13380                 iounmap(tp->regs);
13381                 tp->regs = NULL;
13382
13383                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13384                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13385                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13386         }
13387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13388                 tp->read32_mbox = tg3_read32_mbox_5906;
13389                 tp->write32_mbox = tg3_write32_mbox_5906;
13390                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13391                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13392         }
13393
13394         if (tp->write32 == tg3_write_indirect_reg32 ||
13395             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13396              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13397               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13398                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13399
13400         /* Get eeprom hw config before calling tg3_set_power_state().
13401          * In particular, the TG3_FLG2_IS_NIC flag must be
13402          * determined before calling tg3_set_power_state() so that
13403          * we know whether or not to switch out of Vaux power.
13404          * When the flag is set, it means that GPIO1 is used for eeprom
13405          * write protect and also implies that it is a LOM where GPIOs
13406          * are not used to switch power.
13407          */
13408         tg3_get_eeprom_hw_cfg(tp);
13409
13410         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13411                 /* Allow reads and writes to the
13412                  * APE register and memory space.
13413                  */
13414                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13415                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13416                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13417                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13418                                        pci_state_reg);
13419         }
13420
13421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13422             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13423             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13424             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13425             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13426                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13427
13428         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13429          * GPIO1 driven high will bring 5700's external PHY out of reset.
13430          * It is also used as eeprom write protect on LOMs.
13431          */
13432         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13433         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13434             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13435                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13436                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13437         /* Unused GPIO3 must be driven as output on 5752 because there
13438          * are no pull-up resistors on unused GPIO pins.
13439          */
13440         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13441                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13442
13443         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13444             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13445             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13446                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13447
13448         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13449             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13450                 /* Turn off the debug UART. */
13451                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13452                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13453                         /* Keep VMain power. */
13454                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13455                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13456         }
13457
13458         /* Force the chip into D0. */
13459         err = tg3_set_power_state(tp, PCI_D0);
13460         if (err) {
13461                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13462                 return err;
13463         }
13464
13465         /* Derive initial jumbo mode from MTU assigned in
13466          * ether_setup() via the alloc_etherdev() call
13467          */
13468         if (tp->dev->mtu > ETH_DATA_LEN &&
13469             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13470                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13471
13472         /* Determine WakeOnLan speed to use. */
13473         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13474             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13475             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13476             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13477                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13478         } else {
13479                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13480         }
13481
13482         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13483                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13484
13485         /* A few boards don't want Ethernet@WireSpeed phy feature */
13486         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13487             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13488              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13489              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13490             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13491             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13492                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13493
13494         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13495             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13496                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13497         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13498                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13499
13500         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13501             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13502             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13503             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13504             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13505                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13506                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13507                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13508                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13509                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13510                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13511                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13512                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13513                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13514                 } else
13515                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13516         }
13517
13518         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13519             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13520                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13521                 if (tp->phy_otp == 0)
13522                         tp->phy_otp = TG3_OTP_DEFAULT;
13523         }
13524
13525         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13526                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13527         else
13528                 tp->mi_mode = MAC_MI_MODE_BASE;
13529
13530         tp->coalesce_mode = 0;
13531         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13532             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13533                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13534
13535         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13536             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13537                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13538
13539         err = tg3_mdio_init(tp);
13540         if (err)
13541                 return err;
13542
13543         /* Initialize data/descriptor byte/word swapping. */
13544         val = tr32(GRC_MODE);
13545         val &= GRC_MODE_HOST_STACKUP;
13546         tw32(GRC_MODE, val | tp->grc_mode);
13547
13548         tg3_switch_clocks(tp);
13549
13550         /* Clear this out for sanity. */
13551         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13552
13553         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13554                               &pci_state_reg);
13555         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13556             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13557                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13558
13559                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13560                     chiprevid == CHIPREV_ID_5701_B0 ||
13561                     chiprevid == CHIPREV_ID_5701_B2 ||
13562                     chiprevid == CHIPREV_ID_5701_B5) {
13563                         void __iomem *sram_base;
13564
13565                         /* Write some dummy words into the SRAM status block
13566                          * area, see if it reads back correctly.  If the return
13567                          * value is bad, force enable the PCIX workaround.
13568                          */
13569                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13570
13571                         writel(0x00000000, sram_base);
13572                         writel(0x00000000, sram_base + 4);
13573                         writel(0xffffffff, sram_base + 4);
13574                         if (readl(sram_base) != 0x00000000)
13575                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13576                 }
13577         }
13578
13579         udelay(50);
13580         tg3_nvram_init(tp);
13581
13582         grc_misc_cfg = tr32(GRC_MISC_CFG);
13583         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13584
13585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13586             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13587              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13588                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13589
13590         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13591             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13592                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13593         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13594                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13595                                       HOSTCC_MODE_CLRTICK_TXBD);
13596
13597                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13598                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13599                                        tp->misc_host_ctrl);
13600         }
13601
13602         /* Preserve the APE MAC_MODE bits */
13603         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13604                 tp->mac_mode = tr32(MAC_MODE) |
13605                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13606         else
13607                 tp->mac_mode = TG3_DEF_MAC_MODE;
13608
13609         /* these are limited to 10/100 only */
13610         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13611              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13612             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13613              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13614              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13615               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13616               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13617             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13618              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13619               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13620               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13621             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13622             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13623             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13624             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13625                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13626
13627         err = tg3_phy_probe(tp);
13628         if (err) {
13629                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13630                 /* ... but do not return immediately ... */
13631                 tg3_mdio_fini(tp);
13632         }
13633
13634         tg3_read_vpd(tp);
13635         tg3_read_fw_ver(tp);
13636
13637         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13638                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13639         } else {
13640                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13641                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13642                 else
13643                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13644         }
13645
13646         /* 5700 {AX,BX} chips have a broken status block link
13647          * change bit implementation, so we must use the
13648          * status register in those cases.
13649          */
13650         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13651                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13652         else
13653                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13654
13655         /* The led_ctrl is set during tg3_phy_probe, here we might
13656          * have to force the link status polling mechanism based
13657          * upon subsystem IDs.
13658          */
13659         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13660             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13661             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13662                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13663                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13664         }
13665
13666         /* For all SERDES we poll the MAC status register. */
13667         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13668                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13669         else
13670                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13671
13672         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13673         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13674         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13675             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13676                 tp->rx_offset -= NET_IP_ALIGN;
13677 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13678                 tp->rx_copy_thresh = ~(u16)0;
13679 #endif
13680         }
13681
13682         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13683         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13684         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13685
13686         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13687
13688         /* Increment the rx prod index on the rx std ring by at most
13689          * 8 for these chips to workaround hw errata.
13690          */
13691         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13692             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13693             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13694                 tp->rx_std_max_post = 8;
13695
13696         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13697                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13698                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13699
13700         return err;
13701 }
13702
13703 #ifdef CONFIG_SPARC
13704 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13705 {
13706         struct net_device *dev = tp->dev;
13707         struct pci_dev *pdev = tp->pdev;
13708         struct device_node *dp = pci_device_to_OF_node(pdev);
13709         const unsigned char *addr;
13710         int len;
13711
13712         addr = of_get_property(dp, "local-mac-address", &len);
13713         if (addr && len == 6) {
13714                 memcpy(dev->dev_addr, addr, 6);
13715                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13716                 return 0;
13717         }
13718         return -ENODEV;
13719 }
13720
13721 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13722 {
13723         struct net_device *dev = tp->dev;
13724
13725         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13726         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13727         return 0;
13728 }
13729 #endif
13730
13731 static int __devinit tg3_get_device_address(struct tg3 *tp)
13732 {
13733         struct net_device *dev = tp->dev;
13734         u32 hi, lo, mac_offset;
13735         int addr_ok = 0;
13736
13737 #ifdef CONFIG_SPARC
13738         if (!tg3_get_macaddr_sparc(tp))
13739                 return 0;
13740 #endif
13741
13742         mac_offset = 0x7c;
13743         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13744             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13745                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13746                         mac_offset = 0xcc;
13747                 if (tg3_nvram_lock(tp))
13748                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13749                 else
13750                         tg3_nvram_unlock(tp);
13751         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13752                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13753                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13754                         mac_offset = 0xcc;
13755                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13756                         mac_offset += 0x18c;
13757         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13758                 mac_offset = 0x10;
13759
13760         /* First try to get it from MAC address mailbox. */
13761         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13762         if ((hi >> 16) == 0x484b) {
13763                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13764                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13765
13766                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13767                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13768                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13769                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13770                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13771
13772                 /* Some old bootcode may report a 0 MAC address in SRAM */
13773                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13774         }
13775         if (!addr_ok) {
13776                 /* Next, try NVRAM. */
13777                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13778                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13779                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13780                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13781                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13782                 }
13783                 /* Finally just fetch it out of the MAC control regs. */
13784                 else {
13785                         hi = tr32(MAC_ADDR_0_HIGH);
13786                         lo = tr32(MAC_ADDR_0_LOW);
13787
13788                         dev->dev_addr[5] = lo & 0xff;
13789                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13790                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13791                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13792                         dev->dev_addr[1] = hi & 0xff;
13793                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13794                 }
13795         }
13796
13797         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13798 #ifdef CONFIG_SPARC
13799                 if (!tg3_get_default_macaddr_sparc(tp))
13800                         return 0;
13801 #endif
13802                 return -EINVAL;
13803         }
13804         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13805         return 0;
13806 }
13807
13808 #define BOUNDARY_SINGLE_CACHELINE       1
13809 #define BOUNDARY_MULTI_CACHELINE        2
13810
13811 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13812 {
13813         int cacheline_size;
13814         u8 byte;
13815         int goal;
13816
13817         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13818         if (byte == 0)
13819                 cacheline_size = 1024;
13820         else
13821                 cacheline_size = (int) byte * 4;
13822
13823         /* On 5703 and later chips, the boundary bits have no
13824          * effect.
13825          */
13826         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13827             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13828             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13829                 goto out;
13830
13831 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13832         goal = BOUNDARY_MULTI_CACHELINE;
13833 #else
13834 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13835         goal = BOUNDARY_SINGLE_CACHELINE;
13836 #else
13837         goal = 0;
13838 #endif
13839 #endif
13840
13841         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13842                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13843                 goto out;
13844         }
13845
13846         if (!goal)
13847                 goto out;
13848
13849         /* PCI controllers on most RISC systems tend to disconnect
13850          * when a device tries to burst across a cache-line boundary.
13851          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13852          *
13853          * Unfortunately, for PCI-E there are only limited
13854          * write-side controls for this, and thus for reads
13855          * we will still get the disconnects.  We'll also waste
13856          * these PCI cycles for both read and write for chips
13857          * other than 5700 and 5701 which do not implement the
13858          * boundary bits.
13859          */
13860         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13861             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13862                 switch (cacheline_size) {
13863                 case 16:
13864                 case 32:
13865                 case 64:
13866                 case 128:
13867                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13868                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13869                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13870                         } else {
13871                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13872                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13873                         }
13874                         break;
13875
13876                 case 256:
13877                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13878                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13879                         break;
13880
13881                 default:
13882                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13883                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13884                         break;
13885                 }
13886         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13887                 switch (cacheline_size) {
13888                 case 16:
13889                 case 32:
13890                 case 64:
13891                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13892                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13893                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13894                                 break;
13895                         }
13896                         /* fallthrough */
13897                 case 128:
13898                 default:
13899                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13900                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13901                         break;
13902                 }
13903         } else {
13904                 switch (cacheline_size) {
13905                 case 16:
13906                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13907                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13908                                         DMA_RWCTRL_WRITE_BNDRY_16);
13909                                 break;
13910                         }
13911                         /* fallthrough */
13912                 case 32:
13913                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13914                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13915                                         DMA_RWCTRL_WRITE_BNDRY_32);
13916                                 break;
13917                         }
13918                         /* fallthrough */
13919                 case 64:
13920                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13921                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13922                                         DMA_RWCTRL_WRITE_BNDRY_64);
13923                                 break;
13924                         }
13925                         /* fallthrough */
13926                 case 128:
13927                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13928                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13929                                         DMA_RWCTRL_WRITE_BNDRY_128);
13930                                 break;
13931                         }
13932                         /* fallthrough */
13933                 case 256:
13934                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13935                                 DMA_RWCTRL_WRITE_BNDRY_256);
13936                         break;
13937                 case 512:
13938                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13939                                 DMA_RWCTRL_WRITE_BNDRY_512);
13940                         break;
13941                 case 1024:
13942                 default:
13943                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13944                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13945                         break;
13946                 }
13947         }
13948
13949 out:
13950         return val;
13951 }
13952
13953 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13954 {
13955         struct tg3_internal_buffer_desc test_desc;
13956         u32 sram_dma_descs;
13957         int i, ret;
13958
13959         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13960
13961         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13962         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13963         tw32(RDMAC_STATUS, 0);
13964         tw32(WDMAC_STATUS, 0);
13965
13966         tw32(BUFMGR_MODE, 0);
13967         tw32(FTQ_RESET, 0);
13968
13969         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13970         test_desc.addr_lo = buf_dma & 0xffffffff;
13971         test_desc.nic_mbuf = 0x00002100;
13972         test_desc.len = size;
13973
13974         /*
13975          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13976          * the *second* time the tg3 driver was getting loaded after an
13977          * initial scan.
13978          *
13979          * Broadcom tells me:
13980          *   ...the DMA engine is connected to the GRC block and a DMA
13981          *   reset may affect the GRC block in some unpredictable way...
13982          *   The behavior of resets to individual blocks has not been tested.
13983          *
13984          * Broadcom noted the GRC reset will also reset all sub-components.
13985          */
13986         if (to_device) {
13987                 test_desc.cqid_sqid = (13 << 8) | 2;
13988
13989                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13990                 udelay(40);
13991         } else {
13992                 test_desc.cqid_sqid = (16 << 8) | 7;
13993
13994                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13995                 udelay(40);
13996         }
13997         test_desc.flags = 0x00000005;
13998
13999         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14000                 u32 val;
14001
14002                 val = *(((u32 *)&test_desc) + i);
14003                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14004                                        sram_dma_descs + (i * sizeof(u32)));
14005                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14006         }
14007         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14008
14009         if (to_device)
14010                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14011         else
14012                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14013
14014         ret = -ENODEV;
14015         for (i = 0; i < 40; i++) {
14016                 u32 val;
14017
14018                 if (to_device)
14019                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14020                 else
14021                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14022                 if ((val & 0xffff) == sram_dma_descs) {
14023                         ret = 0;
14024                         break;
14025                 }
14026
14027                 udelay(100);
14028         }
14029
14030         return ret;
14031 }
14032
14033 #define TEST_BUFFER_SIZE        0x2000
14034
14035 static int __devinit tg3_test_dma(struct tg3 *tp)
14036 {
14037         dma_addr_t buf_dma;
14038         u32 *buf, saved_dma_rwctrl;
14039         int ret = 0;
14040
14041         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14042         if (!buf) {
14043                 ret = -ENOMEM;
14044                 goto out_nofree;
14045         }
14046
14047         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14048                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14049
14050         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14051
14052         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14053                 goto out;
14054
14055         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14056                 /* DMA read watermark not used on PCIE */
14057                 tp->dma_rwctrl |= 0x00180000;
14058         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14059                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14060                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14061                         tp->dma_rwctrl |= 0x003f0000;
14062                 else
14063                         tp->dma_rwctrl |= 0x003f000f;
14064         } else {
14065                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14066                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14067                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14068                         u32 read_water = 0x7;
14069
14070                         /* If the 5704 is behind the EPB bridge, we can
14071                          * do the less restrictive ONE_DMA workaround for
14072                          * better performance.
14073                          */
14074                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14075                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14076                                 tp->dma_rwctrl |= 0x8000;
14077                         else if (ccval == 0x6 || ccval == 0x7)
14078                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14079
14080                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14081                                 read_water = 4;
14082                         /* Set bit 23 to enable PCIX hw bug fix */
14083                         tp->dma_rwctrl |=
14084                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14085                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14086                                 (1 << 23);
14087                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14088                         /* 5780 always in PCIX mode */
14089                         tp->dma_rwctrl |= 0x00144000;
14090                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14091                         /* 5714 always in PCIX mode */
14092                         tp->dma_rwctrl |= 0x00148000;
14093                 } else {
14094                         tp->dma_rwctrl |= 0x001b000f;
14095                 }
14096         }
14097
14098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14099             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14100                 tp->dma_rwctrl &= 0xfffffff0;
14101
14102         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14103             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14104                 /* Remove this if it causes problems for some boards. */
14105                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14106
14107                 /* On 5700/5701 chips, we need to set this bit.
14108                  * Otherwise the chip will issue cacheline transactions
14109                  * to streamable DMA memory with not all the byte
14110                  * enables turned on.  This is an error on several
14111                  * RISC PCI controllers, in particular sparc64.
14112                  *
14113                  * On 5703/5704 chips, this bit has been reassigned
14114                  * a different meaning.  In particular, it is used
14115                  * on those chips to enable a PCI-X workaround.
14116                  */
14117                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14118         }
14119
14120         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14121
14122 #if 0
14123         /* Unneeded, already done by tg3_get_invariants.  */
14124         tg3_switch_clocks(tp);
14125 #endif
14126
14127         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14128             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14129                 goto out;
14130
14131         /* It is best to perform DMA test with maximum write burst size
14132          * to expose the 5700/5701 write DMA bug.
14133          */
14134         saved_dma_rwctrl = tp->dma_rwctrl;
14135         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14136         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14137
14138         while (1) {
14139                 u32 *p = buf, i;
14140
14141                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14142                         p[i] = i;
14143
14144                 /* Send the buffer to the chip. */
14145                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14146                 if (ret) {
14147                         dev_err(&tp->pdev->dev,
14148                                 "%s: Buffer write failed. err = %d\n",
14149                                 __func__, ret);
14150                         break;
14151                 }
14152
14153 #if 0
14154                 /* validate data reached card RAM correctly. */
14155                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14156                         u32 val;
14157                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14158                         if (le32_to_cpu(val) != p[i]) {
14159                                 dev_err(&tp->pdev->dev,
14160                                         "%s: Buffer corrupted on device! "
14161                                         "(%d != %d)\n", __func__, val, i);
14162                                 /* ret = -ENODEV here? */
14163                         }
14164                         p[i] = 0;
14165                 }
14166 #endif
14167                 /* Now read it back. */
14168                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14169                 if (ret) {
14170                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14171                                 "err = %d\n", __func__, ret);
14172                         break;
14173                 }
14174
14175                 /* Verify it. */
14176                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14177                         if (p[i] == i)
14178                                 continue;
14179
14180                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14181                             DMA_RWCTRL_WRITE_BNDRY_16) {
14182                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14183                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14184                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14185                                 break;
14186                         } else {
14187                                 dev_err(&tp->pdev->dev,
14188                                         "%s: Buffer corrupted on read back! "
14189                                         "(%d != %d)\n", __func__, p[i], i);
14190                                 ret = -ENODEV;
14191                                 goto out;
14192                         }
14193                 }
14194
14195                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14196                         /* Success. */
14197                         ret = 0;
14198                         break;
14199                 }
14200         }
14201         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14202             DMA_RWCTRL_WRITE_BNDRY_16) {
14203                 static struct pci_device_id dma_wait_state_chipsets[] = {
14204                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14205                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14206                         { },
14207                 };
14208
14209                 /* DMA test passed without adjusting DMA boundary,
14210                  * now look for chipsets that are known to expose the
14211                  * DMA bug without failing the test.
14212                  */
14213                 if (pci_dev_present(dma_wait_state_chipsets)) {
14214                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14215                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14216                 } else {
14217                         /* Safe to use the calculated DMA boundary. */
14218                         tp->dma_rwctrl = saved_dma_rwctrl;
14219                 }
14220
14221                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14222         }
14223
14224 out:
14225         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14226 out_nofree:
14227         return ret;
14228 }
14229
14230 static void __devinit tg3_init_link_config(struct tg3 *tp)
14231 {
14232         tp->link_config.advertising =
14233                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14234                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14235                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14236                  ADVERTISED_Autoneg | ADVERTISED_MII);
14237         tp->link_config.speed = SPEED_INVALID;
14238         tp->link_config.duplex = DUPLEX_INVALID;
14239         tp->link_config.autoneg = AUTONEG_ENABLE;
14240         tp->link_config.active_speed = SPEED_INVALID;
14241         tp->link_config.active_duplex = DUPLEX_INVALID;
14242         tp->link_config.orig_speed = SPEED_INVALID;
14243         tp->link_config.orig_duplex = DUPLEX_INVALID;
14244         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14245 }
14246
14247 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14248 {
14249         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14250                 tp->bufmgr_config.mbuf_read_dma_low_water =
14251                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14252                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14253                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14254                 tp->bufmgr_config.mbuf_high_water =
14255                         DEFAULT_MB_HIGH_WATER_57765;
14256
14257                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14258                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14259                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14260                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14261                 tp->bufmgr_config.mbuf_high_water_jumbo =
14262                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14263         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14264                 tp->bufmgr_config.mbuf_read_dma_low_water =
14265                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14266                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14267                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14268                 tp->bufmgr_config.mbuf_high_water =
14269                         DEFAULT_MB_HIGH_WATER_5705;
14270                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14271                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14272                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14273                         tp->bufmgr_config.mbuf_high_water =
14274                                 DEFAULT_MB_HIGH_WATER_5906;
14275                 }
14276
14277                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14278                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14279                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14280                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14281                 tp->bufmgr_config.mbuf_high_water_jumbo =
14282                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14283         } else {
14284                 tp->bufmgr_config.mbuf_read_dma_low_water =
14285                         DEFAULT_MB_RDMA_LOW_WATER;
14286                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14287                         DEFAULT_MB_MACRX_LOW_WATER;
14288                 tp->bufmgr_config.mbuf_high_water =
14289                         DEFAULT_MB_HIGH_WATER;
14290
14291                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14292                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14293                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14294                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14295                 tp->bufmgr_config.mbuf_high_water_jumbo =
14296                         DEFAULT_MB_HIGH_WATER_JUMBO;
14297         }
14298
14299         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14300         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14301 }
14302
14303 static char * __devinit tg3_phy_string(struct tg3 *tp)
14304 {
14305         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14306         case TG3_PHY_ID_BCM5400:        return "5400";
14307         case TG3_PHY_ID_BCM5401:        return "5401";
14308         case TG3_PHY_ID_BCM5411:        return "5411";
14309         case TG3_PHY_ID_BCM5701:        return "5701";
14310         case TG3_PHY_ID_BCM5703:        return "5703";
14311         case TG3_PHY_ID_BCM5704:        return "5704";
14312         case TG3_PHY_ID_BCM5705:        return "5705";
14313         case TG3_PHY_ID_BCM5750:        return "5750";
14314         case TG3_PHY_ID_BCM5752:        return "5752";
14315         case TG3_PHY_ID_BCM5714:        return "5714";
14316         case TG3_PHY_ID_BCM5780:        return "5780";
14317         case TG3_PHY_ID_BCM5755:        return "5755";
14318         case TG3_PHY_ID_BCM5787:        return "5787";
14319         case TG3_PHY_ID_BCM5784:        return "5784";
14320         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14321         case TG3_PHY_ID_BCM5906:        return "5906";
14322         case TG3_PHY_ID_BCM5761:        return "5761";
14323         case TG3_PHY_ID_BCM5718C:       return "5718C";
14324         case TG3_PHY_ID_BCM5718S:       return "5718S";
14325         case TG3_PHY_ID_BCM57765:       return "57765";
14326         case TG3_PHY_ID_BCM5719C:       return "5719C";
14327         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14328         case 0:                 return "serdes";
14329         default:                return "unknown";
14330         }
14331 }
14332
14333 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14334 {
14335         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14336                 strcpy(str, "PCI Express");
14337                 return str;
14338         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14339                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14340
14341                 strcpy(str, "PCIX:");
14342
14343                 if ((clock_ctrl == 7) ||
14344                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14345                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14346                         strcat(str, "133MHz");
14347                 else if (clock_ctrl == 0)
14348                         strcat(str, "33MHz");
14349                 else if (clock_ctrl == 2)
14350                         strcat(str, "50MHz");
14351                 else if (clock_ctrl == 4)
14352                         strcat(str, "66MHz");
14353                 else if (clock_ctrl == 6)
14354                         strcat(str, "100MHz");
14355         } else {
14356                 strcpy(str, "PCI:");
14357                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14358                         strcat(str, "66MHz");
14359                 else
14360                         strcat(str, "33MHz");
14361         }
14362         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14363                 strcat(str, ":32-bit");
14364         else
14365                 strcat(str, ":64-bit");
14366         return str;
14367 }
14368
14369 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14370 {
14371         struct pci_dev *peer;
14372         unsigned int func, devnr = tp->pdev->devfn & ~7;
14373
14374         for (func = 0; func < 8; func++) {
14375                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14376                 if (peer && peer != tp->pdev)
14377                         break;
14378                 pci_dev_put(peer);
14379         }
14380         /* 5704 can be configured in single-port mode, set peer to
14381          * tp->pdev in that case.
14382          */
14383         if (!peer) {
14384                 peer = tp->pdev;
14385                 return peer;
14386         }
14387
14388         /*
14389          * We don't need to keep the refcount elevated; there's no way
14390          * to remove one half of this device without removing the other
14391          */
14392         pci_dev_put(peer);
14393
14394         return peer;
14395 }
14396
14397 static void __devinit tg3_init_coal(struct tg3 *tp)
14398 {
14399         struct ethtool_coalesce *ec = &tp->coal;
14400
14401         memset(ec, 0, sizeof(*ec));
14402         ec->cmd = ETHTOOL_GCOALESCE;
14403         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14404         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14405         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14406         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14407         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14408         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14409         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14410         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14411         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14412
14413         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14414                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14415                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14416                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14417                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14418                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14419         }
14420
14421         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14422                 ec->rx_coalesce_usecs_irq = 0;
14423                 ec->tx_coalesce_usecs_irq = 0;
14424                 ec->stats_block_coalesce_usecs = 0;
14425         }
14426 }
14427
14428 static const struct net_device_ops tg3_netdev_ops = {
14429         .ndo_open               = tg3_open,
14430         .ndo_stop               = tg3_close,
14431         .ndo_start_xmit         = tg3_start_xmit,
14432         .ndo_get_stats64        = tg3_get_stats64,
14433         .ndo_validate_addr      = eth_validate_addr,
14434         .ndo_set_multicast_list = tg3_set_rx_mode,
14435         .ndo_set_mac_address    = tg3_set_mac_addr,
14436         .ndo_do_ioctl           = tg3_ioctl,
14437         .ndo_tx_timeout         = tg3_tx_timeout,
14438         .ndo_change_mtu         = tg3_change_mtu,
14439 #if TG3_VLAN_TAG_USED
14440         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14441 #endif
14442 #ifdef CONFIG_NET_POLL_CONTROLLER
14443         .ndo_poll_controller    = tg3_poll_controller,
14444 #endif
14445 };
14446
14447 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14448         .ndo_open               = tg3_open,
14449         .ndo_stop               = tg3_close,
14450         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14451         .ndo_get_stats64        = tg3_get_stats64,
14452         .ndo_validate_addr      = eth_validate_addr,
14453         .ndo_set_multicast_list = tg3_set_rx_mode,
14454         .ndo_set_mac_address    = tg3_set_mac_addr,
14455         .ndo_do_ioctl           = tg3_ioctl,
14456         .ndo_tx_timeout         = tg3_tx_timeout,
14457         .ndo_change_mtu         = tg3_change_mtu,
14458 #if TG3_VLAN_TAG_USED
14459         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14460 #endif
14461 #ifdef CONFIG_NET_POLL_CONTROLLER
14462         .ndo_poll_controller    = tg3_poll_controller,
14463 #endif
14464 };
14465
14466 static int __devinit tg3_init_one(struct pci_dev *pdev,
14467                                   const struct pci_device_id *ent)
14468 {
14469         struct net_device *dev;
14470         struct tg3 *tp;
14471         int i, err, pm_cap;
14472         u32 sndmbx, rcvmbx, intmbx;
14473         char str[40];
14474         u64 dma_mask, persist_dma_mask;
14475
14476         printk_once(KERN_INFO "%s\n", version);
14477
14478         err = pci_enable_device(pdev);
14479         if (err) {
14480                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14481                 return err;
14482         }
14483
14484         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14485         if (err) {
14486                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14487                 goto err_out_disable_pdev;
14488         }
14489
14490         pci_set_master(pdev);
14491
14492         /* Find power-management capability. */
14493         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14494         if (pm_cap == 0) {
14495                 dev_err(&pdev->dev,
14496                         "Cannot find Power Management capability, aborting\n");
14497                 err = -EIO;
14498                 goto err_out_free_res;
14499         }
14500
14501         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14502         if (!dev) {
14503                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14504                 err = -ENOMEM;
14505                 goto err_out_free_res;
14506         }
14507
14508         SET_NETDEV_DEV(dev, &pdev->dev);
14509
14510 #if TG3_VLAN_TAG_USED
14511         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14512 #endif
14513
14514         tp = netdev_priv(dev);
14515         tp->pdev = pdev;
14516         tp->dev = dev;
14517         tp->pm_cap = pm_cap;
14518         tp->rx_mode = TG3_DEF_RX_MODE;
14519         tp->tx_mode = TG3_DEF_TX_MODE;
14520
14521         if (tg3_debug > 0)
14522                 tp->msg_enable = tg3_debug;
14523         else
14524                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14525
14526         /* The word/byte swap controls here control register access byte
14527          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14528          * setting below.
14529          */
14530         tp->misc_host_ctrl =
14531                 MISC_HOST_CTRL_MASK_PCI_INT |
14532                 MISC_HOST_CTRL_WORD_SWAP |
14533                 MISC_HOST_CTRL_INDIR_ACCESS |
14534                 MISC_HOST_CTRL_PCISTATE_RW;
14535
14536         /* The NONFRM (non-frame) byte/word swap controls take effect
14537          * on descriptor entries, anything which isn't packet data.
14538          *
14539          * The StrongARM chips on the board (one for tx, one for rx)
14540          * are running in big-endian mode.
14541          */
14542         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14543                         GRC_MODE_WSWAP_NONFRM_DATA);
14544 #ifdef __BIG_ENDIAN
14545         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14546 #endif
14547         spin_lock_init(&tp->lock);
14548         spin_lock_init(&tp->indirect_lock);
14549         INIT_WORK(&tp->reset_task, tg3_reset_task);
14550
14551         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14552         if (!tp->regs) {
14553                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14554                 err = -ENOMEM;
14555                 goto err_out_free_dev;
14556         }
14557
14558         tg3_init_link_config(tp);
14559
14560         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14561         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14562
14563         dev->ethtool_ops = &tg3_ethtool_ops;
14564         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14565         dev->irq = pdev->irq;
14566
14567         err = tg3_get_invariants(tp);
14568         if (err) {
14569                 dev_err(&pdev->dev,
14570                         "Problem fetching invariants of chip, aborting\n");
14571                 goto err_out_iounmap;
14572         }
14573
14574         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14575             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14576             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14577                 dev->netdev_ops = &tg3_netdev_ops;
14578         else
14579                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14580
14581
14582         /* The EPB bridge inside 5714, 5715, and 5780 and any
14583          * device behind the EPB cannot support DMA addresses > 40-bit.
14584          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14585          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14586          * do DMA address check in tg3_start_xmit().
14587          */
14588         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14589                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14590         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14591                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14592 #ifdef CONFIG_HIGHMEM
14593                 dma_mask = DMA_BIT_MASK(64);
14594 #endif
14595         } else
14596                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14597
14598         /* Configure DMA attributes. */
14599         if (dma_mask > DMA_BIT_MASK(32)) {
14600                 err = pci_set_dma_mask(pdev, dma_mask);
14601                 if (!err) {
14602                         dev->features |= NETIF_F_HIGHDMA;
14603                         err = pci_set_consistent_dma_mask(pdev,
14604                                                           persist_dma_mask);
14605                         if (err < 0) {
14606                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14607                                         "DMA for consistent allocations\n");
14608                                 goto err_out_iounmap;
14609                         }
14610                 }
14611         }
14612         if (err || dma_mask == DMA_BIT_MASK(32)) {
14613                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14614                 if (err) {
14615                         dev_err(&pdev->dev,
14616                                 "No usable DMA configuration, aborting\n");
14617                         goto err_out_iounmap;
14618                 }
14619         }
14620
14621         tg3_init_bufmgr_config(tp);
14622
14623         /* Selectively allow TSO based on operating conditions */
14624         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14625             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14626                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14627         else {
14628                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14629                 tp->fw_needed = NULL;
14630         }
14631
14632         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14633                 tp->fw_needed = FIRMWARE_TG3;
14634
14635         /* TSO is on by default on chips that support hardware TSO.
14636          * Firmware TSO on older chips gives lower performance, so it
14637          * is off by default, but can be enabled using ethtool.
14638          */
14639         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14640             (dev->features & NETIF_F_IP_CSUM)) {
14641                 dev->features |= NETIF_F_TSO;
14642                 vlan_features_add(dev, NETIF_F_TSO);
14643         }
14644         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14645             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14646                 if (dev->features & NETIF_F_IPV6_CSUM) {
14647                         dev->features |= NETIF_F_TSO6;
14648                         vlan_features_add(dev, NETIF_F_TSO6);
14649                 }
14650                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14651                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14652                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14653                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14654                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14655                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14656                         dev->features |= NETIF_F_TSO_ECN;
14657                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14658                 }
14659         }
14660
14661         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14662             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14663             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14664                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14665                 tp->rx_pending = 63;
14666         }
14667
14668         err = tg3_get_device_address(tp);
14669         if (err) {
14670                 dev_err(&pdev->dev,
14671                         "Could not obtain valid ethernet address, aborting\n");
14672                 goto err_out_iounmap;
14673         }
14674
14675         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14676                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14677                 if (!tp->aperegs) {
14678                         dev_err(&pdev->dev,
14679                                 "Cannot map APE registers, aborting\n");
14680                         err = -ENOMEM;
14681                         goto err_out_iounmap;
14682                 }
14683
14684                 tg3_ape_lock_init(tp);
14685
14686                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14687                         tg3_read_dash_ver(tp);
14688         }
14689
14690         /*
14691          * Reset chip in case UNDI or EFI driver did not shutdown
14692          * DMA self test will enable WDMAC and we'll see (spurious)
14693          * pending DMA on the PCI bus at that point.
14694          */
14695         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14696             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14697                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14698                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14699         }
14700
14701         err = tg3_test_dma(tp);
14702         if (err) {
14703                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14704                 goto err_out_apeunmap;
14705         }
14706
14707         /* flow control autonegotiation is default behavior */
14708         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14709         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14710
14711         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14712         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14713         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14714         for (i = 0; i < tp->irq_max; i++) {
14715                 struct tg3_napi *tnapi = &tp->napi[i];
14716
14717                 tnapi->tp = tp;
14718                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14719
14720                 tnapi->int_mbox = intmbx;
14721                 if (i < 4)
14722                         intmbx += 0x8;
14723                 else
14724                         intmbx += 0x4;
14725
14726                 tnapi->consmbox = rcvmbx;
14727                 tnapi->prodmbox = sndmbx;
14728
14729                 if (i)
14730                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14731                 else
14732                         tnapi->coal_now = HOSTCC_MODE_NOW;
14733
14734                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14735                         break;
14736
14737                 /*
14738                  * If we support MSIX, we'll be using RSS.  If we're using
14739                  * RSS, the first vector only handles link interrupts and the
14740                  * remaining vectors handle rx and tx interrupts.  Reuse the
14741                  * mailbox values for the next iteration.  The values we setup
14742                  * above are still useful for the single vectored mode.
14743                  */
14744                 if (!i)
14745                         continue;
14746
14747                 rcvmbx += 0x8;
14748
14749                 if (sndmbx & 0x4)
14750                         sndmbx -= 0x4;
14751                 else
14752                         sndmbx += 0xc;
14753         }
14754
14755         tg3_init_coal(tp);
14756
14757         pci_set_drvdata(pdev, dev);
14758
14759         err = register_netdev(dev);
14760         if (err) {
14761                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14762                 goto err_out_apeunmap;
14763         }
14764
14765         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14766                     tp->board_part_number,
14767                     tp->pci_chip_rev_id,
14768                     tg3_bus_string(tp, str),
14769                     dev->dev_addr);
14770
14771         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14772                 struct phy_device *phydev;
14773                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14774                 netdev_info(dev,
14775                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14776                             phydev->drv->name, dev_name(&phydev->dev));
14777         } else {
14778                 char *ethtype;
14779
14780                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14781                         ethtype = "10/100Base-TX";
14782                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14783                         ethtype = "1000Base-SX";
14784                 else
14785                         ethtype = "10/100/1000Base-T";
14786
14787                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14788                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14789                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14790         }
14791
14792         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14793                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14794                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14795                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14796                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14797                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14798         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14799                     tp->dma_rwctrl,
14800                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14801                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14802
14803         return 0;
14804
14805 err_out_apeunmap:
14806         if (tp->aperegs) {
14807                 iounmap(tp->aperegs);
14808                 tp->aperegs = NULL;
14809         }
14810
14811 err_out_iounmap:
14812         if (tp->regs) {
14813                 iounmap(tp->regs);
14814                 tp->regs = NULL;
14815         }
14816
14817 err_out_free_dev:
14818         free_netdev(dev);
14819
14820 err_out_free_res:
14821         pci_release_regions(pdev);
14822
14823 err_out_disable_pdev:
14824         pci_disable_device(pdev);
14825         pci_set_drvdata(pdev, NULL);
14826         return err;
14827 }
14828
14829 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14830 {
14831         struct net_device *dev = pci_get_drvdata(pdev);
14832
14833         if (dev) {
14834                 struct tg3 *tp = netdev_priv(dev);
14835
14836                 if (tp->fw)
14837                         release_firmware(tp->fw);
14838
14839                 flush_scheduled_work();
14840
14841                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14842                         tg3_phy_fini(tp);
14843                         tg3_mdio_fini(tp);
14844                 }
14845
14846                 unregister_netdev(dev);
14847                 if (tp->aperegs) {
14848                         iounmap(tp->aperegs);
14849                         tp->aperegs = NULL;
14850                 }
14851                 if (tp->regs) {
14852                         iounmap(tp->regs);
14853                         tp->regs = NULL;
14854                 }
14855                 free_netdev(dev);
14856                 pci_release_regions(pdev);
14857                 pci_disable_device(pdev);
14858                 pci_set_drvdata(pdev, NULL);
14859         }
14860 }
14861
14862 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14863 {
14864         struct net_device *dev = pci_get_drvdata(pdev);
14865         struct tg3 *tp = netdev_priv(dev);
14866         pci_power_t target_state;
14867         int err;
14868
14869         /* PCI register 4 needs to be saved whether netif_running() or not.
14870          * MSI address and data need to be saved if using MSI and
14871          * netif_running().
14872          */
14873         pci_save_state(pdev);
14874
14875         if (!netif_running(dev))
14876                 return 0;
14877
14878         flush_scheduled_work();
14879         tg3_phy_stop(tp);
14880         tg3_netif_stop(tp);
14881
14882         del_timer_sync(&tp->timer);
14883
14884         tg3_full_lock(tp, 1);
14885         tg3_disable_ints(tp);
14886         tg3_full_unlock(tp);
14887
14888         netif_device_detach(dev);
14889
14890         tg3_full_lock(tp, 0);
14891         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14892         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14893         tg3_full_unlock(tp);
14894
14895         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14896
14897         err = tg3_set_power_state(tp, target_state);
14898         if (err) {
14899                 int err2;
14900
14901                 tg3_full_lock(tp, 0);
14902
14903                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14904                 err2 = tg3_restart_hw(tp, 1);
14905                 if (err2)
14906                         goto out;
14907
14908                 tp->timer.expires = jiffies + tp->timer_offset;
14909                 add_timer(&tp->timer);
14910
14911                 netif_device_attach(dev);
14912                 tg3_netif_start(tp);
14913
14914 out:
14915                 tg3_full_unlock(tp);
14916
14917                 if (!err2)
14918                         tg3_phy_start(tp);
14919         }
14920
14921         return err;
14922 }
14923
14924 static int tg3_resume(struct pci_dev *pdev)
14925 {
14926         struct net_device *dev = pci_get_drvdata(pdev);
14927         struct tg3 *tp = netdev_priv(dev);
14928         int err;
14929
14930         pci_restore_state(tp->pdev);
14931
14932         if (!netif_running(dev))
14933                 return 0;
14934
14935         err = tg3_set_power_state(tp, PCI_D0);
14936         if (err)
14937                 return err;
14938
14939         netif_device_attach(dev);
14940
14941         tg3_full_lock(tp, 0);
14942
14943         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14944         err = tg3_restart_hw(tp, 1);
14945         if (err)
14946                 goto out;
14947
14948         tp->timer.expires = jiffies + tp->timer_offset;
14949         add_timer(&tp->timer);
14950
14951         tg3_netif_start(tp);
14952
14953 out:
14954         tg3_full_unlock(tp);
14955
14956         if (!err)
14957                 tg3_phy_start(tp);
14958
14959         return err;
14960 }
14961
14962 static struct pci_driver tg3_driver = {
14963         .name           = DRV_MODULE_NAME,
14964         .id_table       = tg3_pci_tbl,
14965         .probe          = tg3_init_one,
14966         .remove         = __devexit_p(tg3_remove_one),
14967         .suspend        = tg3_suspend,
14968         .resume         = tg3_resume
14969 };
14970
14971 static int __init tg3_init(void)
14972 {
14973         return pci_register_driver(&tg3_driver);
14974 }
14975
14976 static void __exit tg3_cleanup(void)
14977 {
14978         pci_unregister_driver(&tg3_driver);
14979 }
14980
14981 module_init(tg3_init);
14982 module_exit(tg3_cleanup);