drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mdio.h>
  36 #include <linux/mii.h>
  37 #include <linux/phy.h>
  38 #include <linux/brcmphy.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/ip.h>
  41 #include <linux/tcp.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/firmware.h>
  46
  47 #include <net/checksum.h>
  48 #include <net/ip.h>
  49
  50 #include <asm/system.h>
  51 #include <asm/io.h>
  52 #include <asm/byteorder.h>
  53 #include <asm/uaccess.h>
  54
  55 #ifdef CONFIG_SPARC
  56 #include <asm/idprom.h>
  57 #include <asm/prom.h>
  58 #endif
  59
  60 #define BAR_0   0
  61 #define BAR_2   2
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define TG3_MAJ_NUM                     3
  67 #define TG3_MIN_NUM                     116
  68 #define DRV_MODULE_VERSION      \
  69         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  70 #define DRV_MODULE_RELDATE      "December 3, 2010"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_STD_RING_SIZE(tp) \
 100         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 101           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 102          RX_STD_MAX_SIZE_5717 : 512)
 103 #define TG3_DEF_RX_RING_PENDING         200
 104 #define TG3_RX_JMB_RING_SIZE(tp) \
 105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 107          1024 : 256)
 108 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 109 #define TG3_RSS_INDIR_TBL_SIZE          128
 110
 111 /* Do not place this n-ring entries value into the tp struct itself,
 112  * we really want to expose these constants to GCC so that modulo et
 113  * al.  operations are done with shifts and masks instead of with
 114  * hw multiply/modulo instructions.  Another solution would be to
 115  * replace things like '% foo' with '& (foo - 1)'.
 116  */
 117
 118 #define TG3_TX_RING_SIZE                512
 119 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 120
 121 #define TG3_RX_STD_RING_BYTES(tp) \
 122         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 123 #define TG3_RX_JMB_RING_BYTES(tp) \
 124         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 125 #define TG3_RX_RCB_RING_BYTES(tp) \
 126         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 127 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 128                                  TG3_TX_RING_SIZE)
 129 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 130
 131 #define TG3_DMA_BYTE_ENAB               64
 132
 133 #define TG3_RX_STD_DMA_SZ               1536
 134 #define TG3_RX_JMB_DMA_SZ               9046
 135
 136 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 137
 138 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 139 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 140
 141 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 142         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 143
 144 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 145         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 146
 147 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 148  * that are at least dword aligned when used in PCIX mode.  The driver
 149  * works around this bug by double copying the packet.  This workaround
 150  * is built into the normal double copy length check for efficiency.
 151  *
 152  * However, the double copy is only necessary on those architectures
 153  * where unaligned memory accesses are inefficient.  For those architectures
 154  * where unaligned memory accesses incur little penalty, we can reintegrate
 155  * the 5701 in the normal rx path.  Doing so saves a device structure
 156  * dereference by hardcoding the double copy threshold in place.
 157  */
 158 #define TG3_RX_COPY_THRESHOLD           256
 159 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 160         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 161 #else
 162         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 163 #endif
 164
 165 /* minimum number of free TX descriptors required to wake up TX process */
 166 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 167
 168 #define TG3_RAW_IP_ALIGN 2
 169
 170 /* number of ETHTOOL_GSTATS u64's */
 171 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 172
 173 #define TG3_NUM_TEST            6
 174
 175 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 176
 177 #define FIRMWARE_TG3            "tigon/tg3.bin"
 178 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 179 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 180
 181 static char version[] __devinitdata =
 182         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 183
 184 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 185 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 186 MODULE_LICENSE("GPL");
 187 MODULE_VERSION(DRV_MODULE_VERSION);
 188 MODULE_FIRMWARE(FIRMWARE_TG3);
 189 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 190 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 191
 192 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 193 module_param(tg3_debug, int, 0);
 194 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 195
 196 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 276         {}
 277 };
 278
 279 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 280
 281 static const struct {
 282         const char string[ETH_GSTRING_LEN];
 283 } ethtool_stats_keys[TG3_NUM_STATS] = {
 284         { "rx_octets" },
 285         { "rx_fragments" },
 286         { "rx_ucast_packets" },
 287         { "rx_mcast_packets" },
 288         { "rx_bcast_packets" },
 289         { "rx_fcs_errors" },
 290         { "rx_align_errors" },
 291         { "rx_xon_pause_rcvd" },
 292         { "rx_xoff_pause_rcvd" },
 293         { "rx_mac_ctrl_rcvd" },
 294         { "rx_xoff_entered" },
 295         { "rx_frame_too_long_errors" },
 296         { "rx_jabbers" },
 297         { "rx_undersize_packets" },
 298         { "rx_in_length_errors" },
 299         { "rx_out_length_errors" },
 300         { "rx_64_or_less_octet_packets" },
 301         { "rx_65_to_127_octet_packets" },
 302         { "rx_128_to_255_octet_packets" },
 303         { "rx_256_to_511_octet_packets" },
 304         { "rx_512_to_1023_octet_packets" },
 305         { "rx_1024_to_1522_octet_packets" },
 306         { "rx_1523_to_2047_octet_packets" },
 307         { "rx_2048_to_4095_octet_packets" },
 308         { "rx_4096_to_8191_octet_packets" },
 309         { "rx_8192_to_9022_octet_packets" },
 310
 311         { "tx_octets" },
 312         { "tx_collisions" },
 313
 314         { "tx_xon_sent" },
 315         { "tx_xoff_sent" },
 316         { "tx_flow_control" },
 317         { "tx_mac_errors" },
 318         { "tx_single_collisions" },
 319         { "tx_mult_collisions" },
 320         { "tx_deferred" },
 321         { "tx_excessive_collisions" },
 322         { "tx_late_collisions" },
 323         { "tx_collide_2times" },
 324         { "tx_collide_3times" },
 325         { "tx_collide_4times" },
 326         { "tx_collide_5times" },
 327         { "tx_collide_6times" },
 328         { "tx_collide_7times" },
 329         { "tx_collide_8times" },
 330         { "tx_collide_9times" },
 331         { "tx_collide_10times" },
 332         { "tx_collide_11times" },
 333         { "tx_collide_12times" },
 334         { "tx_collide_13times" },
 335         { "tx_collide_14times" },
 336         { "tx_collide_15times" },
 337         { "tx_ucast_packets" },
 338         { "tx_mcast_packets" },
 339         { "tx_bcast_packets" },
 340         { "tx_carrier_sense_errors" },
 341         { "tx_discards" },
 342         { "tx_errors" },
 343
 344         { "dma_writeq_full" },
 345         { "dma_write_prioq_full" },
 346         { "rxbds_empty" },
 347         { "rx_discards" },
 348         { "rx_errors" },
 349         { "rx_threshold_hit" },
 350
 351         { "dma_readq_full" },
 352         { "dma_read_prioq_full" },
 353         { "tx_comp_queue_full" },
 354
 355         { "ring_set_send_prod_index" },
 356         { "ring_status_update" },
 357         { "nic_irqs" },
 358         { "nic_avoided_irqs" },
 359         { "nic_tx_threshold_hit" }
 360 };
 361
 362 static const struct {
 363         const char string[ETH_GSTRING_LEN];
 364 } ethtool_test_keys[TG3_NUM_TEST] = {
 365         { "nvram test     (online) " },
 366         { "link test      (online) " },
 367         { "register test  (offline)" },
 368         { "memory test    (offline)" },
 369         { "loopback test  (offline)" },
 370         { "interrupt test (offline)" },
 371 };
 372
 373 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 374 {
 375         writel(val, tp->regs + off);
 376 }
 377
 378 static u32 tg3_read32(struct tg3 *tp, u32 off)
 379 {
 380         return readl(tp->regs + off);
 381 }
 382
 383 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 384 {
 385         writel(val, tp->aperegs + off);
 386 }
 387
 388 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 389 {
 390         return readl(tp->aperegs + off);
 391 }
 392
 393 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 394 {
 395         unsigned long flags;
 396
 397         spin_lock_irqsave(&tp->indirect_lock, flags);
 398         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 399         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 400         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 401 }
 402
 403 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 404 {
 405         writel(val, tp->regs + off);
 406         readl(tp->regs + off);
 407 }
 408
 409 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 422 {
 423         unsigned long flags;
 424
 425         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 426                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 427                                        TG3_64BIT_REG_LOW, val);
 428                 return;
 429         }
 430         if (off == TG3_RX_STD_PROD_IDX_REG) {
 431                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 432                                        TG3_64BIT_REG_LOW, val);
 433                 return;
 434         }
 435
 436         spin_lock_irqsave(&tp->indirect_lock, flags);
 437         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 438         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 439         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 440
 441         /* In indirect mode when disabling interrupts, we also need
 442          * to clear the interrupt bit in the GRC local ctrl register.
 443          */
 444         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 445             (val == 0x1)) {
 446                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 447                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 448         }
 449 }
 450
 451 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 452 {
 453         unsigned long flags;
 454         u32 val;
 455
 456         spin_lock_irqsave(&tp->indirect_lock, flags);
 457         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 458         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 459         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 460         return val;
 461 }
 462
 463 /* usec_wait specifies the wait time in usec when writing to certain registers
 464  * where it is unsafe to read back the register without some delay.
 465  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 466  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 467  */
 468 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 469 {
 470         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 471             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 472                 /* Non-posted methods */
 473                 tp->write32(tp, off, val);
 474         else {
 475                 /* Posted method */
 476                 tg3_write32(tp, off, val);
 477                 if (usec_wait)
 478                         udelay(usec_wait);
 479                 tp->read32(tp, off);
 480         }
 481         /* Wait again after the read for the posted method to guarantee that
 482          * the wait time is met.
 483          */
 484         if (usec_wait)
 485                 udelay(usec_wait);
 486 }
 487
 488 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 489 {
 490         tp->write32_mbox(tp, off, val);
 491         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 492             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 493                 tp->read32_mbox(tp, off);
 494 }
 495
 496 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         void __iomem *mbox = tp->regs + off;
 499         writel(val, mbox);
 500         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 501                 writel(val, mbox);
 502         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 503                 readl(mbox);
 504 }
 505
 506 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 507 {
 508         return readl(tp->regs + off + GRCMBOX_BASE);
 509 }
 510
 511 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 512 {
 513         writel(val, tp->regs + off + GRCMBOX_BASE);
 514 }
 515
 516 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 517 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 518 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 519 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 520 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 521
 522 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 523 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 524 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 525 #define tr32(reg)                       tp->read32(tp, reg)
 526
 527 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 528 {
 529         unsigned long flags;
 530
 531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 532             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 533                 return;
 534
 535         spin_lock_irqsave(&tp->indirect_lock, flags);
 536         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 537                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 538                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 539
 540                 /* Always leave this as zero. */
 541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 542         } else {
 543                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         }
 549         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 550 }
 551
 552 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 553 {
 554         unsigned long flags;
 555
 556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 557             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 558                 *val = 0;
 559                 return;
 560         }
 561
 562         spin_lock_irqsave(&tp->indirect_lock, flags);
 563         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 564                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 565                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 566
 567                 /* Always leave this as zero. */
 568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 569         } else {
 570                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 572
 573                 /* Always leave this as zero. */
 574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         }
 576         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 577 }
 578
 579 static void tg3_ape_lock_init(struct tg3 *tp)
 580 {
 581         int i;
 582         u32 regbase;
 583
 584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 585                 regbase = TG3_APE_LOCK_GRANT;
 586         else
 587                 regbase = TG3_APE_PER_LOCK_GRANT;
 588
 589         /* Make sure the driver hasn't any stale locks. */
 590         for (i = 0; i < 8; i++)
 591                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 592 }
 593
 594 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 595 {
 596         int i, off;
 597         int ret = 0;
 598         u32 status, req, gnt;
 599
 600         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 601                 return 0;
 602
 603         switch (locknum) {
 604         case TG3_APE_LOCK_GRC:
 605         case TG3_APE_LOCK_MEM:
 606                 break;
 607         default:
 608                 return -EINVAL;
 609         }
 610
 611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 612                 req = TG3_APE_LOCK_REQ;
 613                 gnt = TG3_APE_LOCK_GRANT;
 614         } else {
 615                 req = TG3_APE_PER_LOCK_REQ;
 616                 gnt = TG3_APE_PER_LOCK_GRANT;
 617         }
 618
 619         off = 4 * locknum;
 620
 621         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 622
 623         /* Wait for up to 1 millisecond to acquire lock. */
 624         for (i = 0; i < 100; i++) {
 625                 status = tg3_ape_read32(tp, gnt + off);
 626                 if (status == APE_LOCK_GRANT_DRIVER)
 627                         break;
 628                 udelay(10);
 629         }
 630
 631         if (status != APE_LOCK_GRANT_DRIVER) {
 632                 /* Revoke the lock request. */
 633                 tg3_ape_write32(tp, gnt + off,
 634                                 APE_LOCK_GRANT_DRIVER);
 635
 636                 ret = -EBUSY;
 637         }
 638
 639         return ret;
 640 }
 641
 642 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 643 {
 644         u32 gnt;
 645
 646         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 647                 return;
 648
 649         switch (locknum) {
 650         case TG3_APE_LOCK_GRC:
 651         case TG3_APE_LOCK_MEM:
 652                 break;
 653         default:
 654                 return;
 655         }
 656
 657         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 658                 gnt = TG3_APE_LOCK_GRANT;
 659         else
 660                 gnt = TG3_APE_PER_LOCK_GRANT;
 661
 662         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 663 }
 664
 665 static void tg3_disable_ints(struct tg3 *tp)
 666 {
 667         int i;
 668
 669         tw32(TG3PCI_MISC_HOST_CTRL,
 670              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 671         for (i = 0; i < tp->irq_max; i++)
 672                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 673 }
 674
 675 static void tg3_enable_ints(struct tg3 *tp)
 676 {
 677         int i;
 678
 679         tp->irq_sync = 0;
 680         wmb();
 681
 682         tw32(TG3PCI_MISC_HOST_CTRL,
 683              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 684
 685         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 686         for (i = 0; i < tp->irq_cnt; i++) {
 687                 struct tg3_napi *tnapi = &tp->napi[i];
 688
 689                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 690                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 691                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 692
 693                 tp->coal_now |= tnapi->coal_now;
 694         }
 695
 696         /* Force an initial interrupt */
 697         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 698             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 699                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 700         else
 701                 tw32(HOSTCC_MODE, tp->coal_now);
 702
 703         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 704 }
 705
 706 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 707 {
 708         struct tg3 *tp = tnapi->tp;
 709         struct tg3_hw_status *sblk = tnapi->hw_status;
 710         unsigned int work_exists = 0;
 711
 712         /* check for phy events */
 713         if (!(tp->tg3_flags &
 714               (TG3_FLAG_USE_LINKCHG_REG |
 715                TG3_FLAG_POLL_SERDES))) {
 716                 if (sblk->status & SD_STATUS_LINK_CHG)
 717                         work_exists = 1;
 718         }
 719         /* check for RX/TX work to do */
 720         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 721             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 722                 work_exists = 1;
 723
 724         return work_exists;
 725 }
 726
 727 /* tg3_int_reenable
 728  *  similar to tg3_enable_ints, but it accurately determines whether there
 729  *  is new work pending and can return without flushing the PIO write
 730  *  which reenables interrupts
 731  */
 732 static void tg3_int_reenable(struct tg3_napi *tnapi)
 733 {
 734         struct tg3 *tp = tnapi->tp;
 735
 736         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 737         mmiowb();
 738
 739         /* When doing tagged status, this work check is unnecessary.
 740          * The last_tag we write above tells the chip which piece of
 741          * work we've completed.
 742          */
 743         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 744             tg3_has_work(tnapi))
 745                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 746                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 747 }
 748
 749 static void tg3_switch_clocks(struct tg3 *tp)
 750 {
 751         u32 clock_ctrl;
 752         u32 orig_clock_ctrl;
 753
 754         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 755             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 756                 return;
 757
 758         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 759
 760         orig_clock_ctrl = clock_ctrl;
 761         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 762                        CLOCK_CTRL_CLKRUN_OENABLE |
 763                        0x1f);
 764         tp->pci_clock_ctrl = clock_ctrl;
 765
 766         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 767                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 768                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 769                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 770                 }
 771         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 772                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 773                             clock_ctrl |
 774                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 775                             40);
 776                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 778                             40);
 779         }
 780         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 781 }
 782
 783 #define PHY_BUSY_LOOPS  5000
 784
 785 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 786 {
 787         u32 frame_val;
 788         unsigned int loops;
 789         int ret;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         *val = 0x0;
 798
 799         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 800                       MI_COM_PHY_ADDR_MASK);
 801         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 802                       MI_COM_REG_ADDR_MASK);
 803         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 804
 805         tw32_f(MAC_MI_COM, frame_val);
 806
 807         loops = PHY_BUSY_LOOPS;
 808         while (loops != 0) {
 809                 udelay(10);
 810                 frame_val = tr32(MAC_MI_COM);
 811
 812                 if ((frame_val & MI_COM_BUSY) == 0) {
 813                         udelay(5);
 814                         frame_val = tr32(MAC_MI_COM);
 815                         break;
 816                 }
 817                 loops -= 1;
 818         }
 819
 820         ret = -EBUSY;
 821         if (loops != 0) {
 822                 *val = frame_val & MI_COM_DATA_MASK;
 823                 ret = 0;
 824         }
 825
 826         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 827                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 828                 udelay(80);
 829         }
 830
 831         return ret;
 832 }
 833
 834 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 835 {
 836         u32 frame_val;
 837         unsigned int loops;
 838         int ret;
 839
 840         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 841             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 842                 return 0;
 843
 844         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 845                 tw32_f(MAC_MI_MODE,
 846                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 847                 udelay(80);
 848         }
 849
 850         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 851                       MI_COM_PHY_ADDR_MASK);
 852         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 853                       MI_COM_REG_ADDR_MASK);
 854         frame_val |= (val & MI_COM_DATA_MASK);
 855         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 856
 857         tw32_f(MAC_MI_COM, frame_val);
 858
 859         loops = PHY_BUSY_LOOPS;
 860         while (loops != 0) {
 861                 udelay(10);
 862                 frame_val = tr32(MAC_MI_COM);
 863                 if ((frame_val & MI_COM_BUSY) == 0) {
 864                         udelay(5);
 865                         frame_val = tr32(MAC_MI_COM);
 866                         break;
 867                 }
 868                 loops -= 1;
 869         }
 870
 871         ret = -EBUSY;
 872         if (loops != 0)
 873                 ret = 0;
 874
 875         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 876                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 877                 udelay(80);
 878         }
 879
 880         return ret;
 881 }
 882
 883 static int tg3_bmcr_reset(struct tg3 *tp)
 884 {
 885         u32 phy_control;
 886         int limit, err;
 887
 888         /* OK, reset it, and poll the BMCR_RESET bit until it
 889          * clears or we time out.
 890          */
 891         phy_control = BMCR_RESET;
 892         err = tg3_writephy(tp, MII_BMCR, phy_control);
 893         if (err != 0)
 894                 return -EBUSY;
 895
 896         limit = 5000;
 897         while (limit--) {
 898                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 899                 if (err != 0)
 900                         return -EBUSY;
 901
 902                 if ((phy_control & BMCR_RESET) == 0) {
 903                         udelay(40);
 904                         break;
 905                 }
 906                 udelay(10);
 907         }
 908         if (limit < 0)
 909                 return -EBUSY;
 910
 911         return 0;
 912 }
 913
 914 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 915 {
 916         struct tg3 *tp = bp->priv;
 917         u32 val;
 918
 919         spin_lock_bh(&tp->lock);
 920
 921         if (tg3_readphy(tp, reg, &val))
 922                 val = -EIO;
 923
 924         spin_unlock_bh(&tp->lock);
 925
 926         return val;
 927 }
 928
 929 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 930 {
 931         struct tg3 *tp = bp->priv;
 932         u32 ret = 0;
 933
 934         spin_lock_bh(&tp->lock);
 935
 936         if (tg3_writephy(tp, reg, val))
 937                 ret = -EIO;
 938
 939         spin_unlock_bh(&tp->lock);
 940
 941         return ret;
 942 }
 943
 944 static int tg3_mdio_reset(struct mii_bus *bp)
 945 {
 946         return 0;
 947 }
 948
 949 static void tg3_mdio_config_5785(struct tg3 *tp)
 950 {
 951         u32 val;
 952         struct phy_device *phydev;
 953
 954         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 955         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 956         case PHY_ID_BCM50610:
 957         case PHY_ID_BCM50610M:
 958                 val = MAC_PHYCFG2_50610_LED_MODES;
 959                 break;
 960         case PHY_ID_BCMAC131:
 961                 val = MAC_PHYCFG2_AC131_LED_MODES;
 962                 break;
 963         case PHY_ID_RTL8211C:
 964                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 965                 break;
 966         case PHY_ID_RTL8201E:
 967                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 968                 break;
 969         default:
 970                 return;
 971         }
 972
 973         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 974                 tw32(MAC_PHYCFG2, val);
 975
 976                 val = tr32(MAC_PHYCFG1);
 977                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 978                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 979                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 980                 tw32(MAC_PHYCFG1, val);
 981
 982                 return;
 983         }
 984
 985         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 986                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 987                        MAC_PHYCFG2_FMODE_MASK_MASK |
 988                        MAC_PHYCFG2_GMODE_MASK_MASK |
 989                        MAC_PHYCFG2_ACT_MASK_MASK   |
 990                        MAC_PHYCFG2_QUAL_MASK_MASK |
 991                        MAC_PHYCFG2_INBAND_ENABLE;
 992
 993         tw32(MAC_PHYCFG2, val);
 994
 995         val = tr32(MAC_PHYCFG1);
 996         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 997                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 998         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
 999                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1000                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1001                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1002                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1003         }
1004         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1005                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1006         tw32(MAC_PHYCFG1, val);
1007
1008         val = tr32(MAC_EXT_RGMII_MODE);
1009         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1010                  MAC_RGMII_MODE_RX_QUALITY |
1011                  MAC_RGMII_MODE_RX_ACTIVITY |
1012                  MAC_RGMII_MODE_RX_ENG_DET |
1013                  MAC_RGMII_MODE_TX_ENABLE |
1014                  MAC_RGMII_MODE_TX_LOWPWR |
1015                  MAC_RGMII_MODE_TX_RESET);
1016         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1017                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1018                         val |= MAC_RGMII_MODE_RX_INT_B |
1019                                MAC_RGMII_MODE_RX_QUALITY |
1020                                MAC_RGMII_MODE_RX_ACTIVITY |
1021                                MAC_RGMII_MODE_RX_ENG_DET;
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1023                         val |= MAC_RGMII_MODE_TX_ENABLE |
1024                                MAC_RGMII_MODE_TX_LOWPWR |
1025                                MAC_RGMII_MODE_TX_RESET;
1026         }
1027         tw32(MAC_EXT_RGMII_MODE, val);
1028 }
1029
1030 static void tg3_mdio_start(struct tg3 *tp)
1031 {
1032         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1033         tw32_f(MAC_MI_MODE, tp->mi_mode);
1034         udelay(80);
1035
1036         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038                 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043         int i;
1044         u32 reg;
1045         struct phy_device *phydev;
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1048             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1049                 u32 is_serdes;
1050
1051                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1052
1053                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1054                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1055                 else
1056                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1057                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1058                 if (is_serdes)
1059                         tp->phy_addr += 7;
1060         } else
1061                 tp->phy_addr = TG3_PHY_MII_ADDR;
1062
1063         tg3_mdio_start(tp);
1064
1065         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1066             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1067                 return 0;
1068
1069         tp->mdio_bus = mdiobus_alloc();
1070         if (tp->mdio_bus == NULL)
1071                 return -ENOMEM;
1072
1073         tp->mdio_bus->name     = "tg3 mdio bus";
1074         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1075                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1076         tp->mdio_bus->priv     = tp;
1077         tp->mdio_bus->parent   = &tp->pdev->dev;
1078         tp->mdio_bus->read     = &tg3_mdio_read;
1079         tp->mdio_bus->write    = &tg3_mdio_write;
1080         tp->mdio_bus->reset    = &tg3_mdio_reset;
1081         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1082         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1083
1084         for (i = 0; i < PHY_MAX_ADDR; i++)
1085                 tp->mdio_bus->irq[i] = PHY_POLL;
1086
1087         /* The bus registration will look for all the PHYs on the mdio bus.
1088          * Unfortunately, it does not ensure the PHY is powered up before
1089          * accessing the PHY ID registers.  A chip reset is the
1090          * quickest way to bring the device back to an operational state..
1091          */
1092         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1093                 tg3_bmcr_reset(tp);
1094
1095         i = mdiobus_register(tp->mdio_bus);
1096         if (i) {
1097                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1098                 mdiobus_free(tp->mdio_bus);
1099                 return i;
1100         }
1101
1102         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1103
1104         if (!phydev || !phydev->drv) {
1105                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1106                 mdiobus_unregister(tp->mdio_bus);
1107                 mdiobus_free(tp->mdio_bus);
1108                 return -ENODEV;
1109         }
1110
1111         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1112         case PHY_ID_BCM57780:
1113                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1114                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1115                 break;
1116         case PHY_ID_BCM50610:
1117         case PHY_ID_BCM50610M:
1118                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1119                                      PHY_BRCM_RX_REFCLK_UNUSED |
1120                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1121                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1122                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1123                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1124                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1125                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1126                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1127                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1128                 /* fallthru */
1129         case PHY_ID_RTL8211C:
1130                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1131                 break;
1132         case PHY_ID_RTL8201E:
1133         case PHY_ID_BCMAC131:
1134                 phydev->interface = PHY_INTERFACE_MODE_MII;
1135                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1136                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1137                 break;
1138         }
1139
1140         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1141
1142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1143                 tg3_mdio_config_5785(tp);
1144
1145         return 0;
1146 }
1147
1148 static void tg3_mdio_fini(struct tg3 *tp)
1149 {
1150         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1151                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1152                 mdiobus_unregister(tp->mdio_bus);
1153                 mdiobus_free(tp->mdio_bus);
1154         }
1155 }
1156
1157 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1158 {
1159         int err;
1160
1161         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1162         if (err)
1163                 goto done;
1164
1165         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1166         if (err)
1167                 goto done;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1170                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1171         if (err)
1172                 goto done;
1173
1174         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1175
1176 done:
1177         return err;
1178 }
1179
1180 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1181 {
1182         int err;
1183
1184         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1185         if (err)
1186                 goto done;
1187
1188         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1189         if (err)
1190                 goto done;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1193                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1194         if (err)
1195                 goto done;
1196
1197         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1198
1199 done:
1200         return err;
1201 }
1202
1203 /* tp->lock is held. */
1204 static inline void tg3_generate_fw_event(struct tg3 *tp)
1205 {
1206         u32 val;
1207
1208         val = tr32(GRC_RX_CPU_EVENT);
1209         val |= GRC_RX_CPU_DRIVER_EVENT;
1210         tw32_f(GRC_RX_CPU_EVENT, val);
1211
1212         tp->last_event_jiffies = jiffies;
1213 }
1214
1215 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1216
1217 /* tp->lock is held. */
1218 static void tg3_wait_for_event_ack(struct tg3 *tp)
1219 {
1220         int i;
1221         unsigned int delay_cnt;
1222         long time_remain;
1223
1224         /* If enough time has passed, no wait is necessary. */
1225         time_remain = (long)(tp->last_event_jiffies + 1 +
1226                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1227                       (long)jiffies;
1228         if (time_remain < 0)
1229                 return;
1230
1231         /* Check if we can shorten the wait time. */
1232         delay_cnt = jiffies_to_usecs(time_remain);
1233         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1234                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1235         delay_cnt = (delay_cnt >> 3) + 1;
1236
1237         for (i = 0; i < delay_cnt; i++) {
1238                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1239                         break;
1240                 udelay(8);
1241         }
1242 }
1243
1244 /* tp->lock is held. */
1245 static void tg3_ump_link_report(struct tg3 *tp)
1246 {
1247         u32 reg;
1248         u32 val;
1249
1250         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1251             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1252                 return;
1253
1254         tg3_wait_for_event_ack(tp);
1255
1256         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1257
1258         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1259
1260         val = 0;
1261         if (!tg3_readphy(tp, MII_BMCR, &reg))
1262                 val = reg << 16;
1263         if (!tg3_readphy(tp, MII_BMSR, &reg))
1264                 val |= (reg & 0xffff);
1265         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1266
1267         val = 0;
1268         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1269                 val = reg << 16;
1270         if (!tg3_readphy(tp, MII_LPA, &reg))
1271                 val |= (reg & 0xffff);
1272         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1273
1274         val = 0;
1275         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1276                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1277                         val = reg << 16;
1278                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1279                         val |= (reg & 0xffff);
1280         }
1281         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1282
1283         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1284                 val = reg << 16;
1285         else
1286                 val = 0;
1287         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1288
1289         tg3_generate_fw_event(tp);
1290 }
1291
1292 static void tg3_link_report(struct tg3 *tp)
1293 {
1294         if (!netif_carrier_ok(tp->dev)) {
1295                 netif_info(tp, link, tp->dev, "Link is down\n");
1296                 tg3_ump_link_report(tp);
1297         } else if (netif_msg_link(tp)) {
1298                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1299                             (tp->link_config.active_speed == SPEED_1000 ?
1300                              1000 :
1301                              (tp->link_config.active_speed == SPEED_100 ?
1302                               100 : 10)),
1303                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1304                              "full" : "half"));
1305
1306                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1307                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1308                             "on" : "off",
1309                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1310                             "on" : "off");
1311                 tg3_ump_link_report(tp);
1312         }
1313 }
1314
1315 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1316 {
1317         u16 miireg;
1318
1319         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1320                 miireg = ADVERTISE_PAUSE_CAP;
1321         else if (flow_ctrl & FLOW_CTRL_TX)
1322                 miireg = ADVERTISE_PAUSE_ASYM;
1323         else if (flow_ctrl & FLOW_CTRL_RX)
1324                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1325         else
1326                 miireg = 0;
1327
1328         return miireg;
1329 }
1330
1331 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1332 {
1333         u16 miireg;
1334
1335         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1336                 miireg = ADVERTISE_1000XPAUSE;
1337         else if (flow_ctrl & FLOW_CTRL_TX)
1338                 miireg = ADVERTISE_1000XPSE_ASYM;
1339         else if (flow_ctrl & FLOW_CTRL_RX)
1340                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1341         else
1342                 miireg = 0;
1343
1344         return miireg;
1345 }
1346
1347 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1348 {
1349         u8 cap = 0;
1350
1351         if (lcladv & ADVERTISE_1000XPAUSE) {
1352                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1353                         if (rmtadv & LPA_1000XPAUSE)
1354                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1355                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1356                                 cap = FLOW_CTRL_RX;
1357                 } else {
1358                         if (rmtadv & LPA_1000XPAUSE)
1359                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1360                 }
1361         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1362                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1363                         cap = FLOW_CTRL_TX;
1364         }
1365
1366         return cap;
1367 }
1368
1369 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1370 {
1371         u8 autoneg;
1372         u8 flowctrl = 0;
1373         u32 old_rx_mode = tp->rx_mode;
1374         u32 old_tx_mode = tp->tx_mode;
1375
1376         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1377                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1378         else
1379                 autoneg = tp->link_config.autoneg;
1380
1381         if (autoneg == AUTONEG_ENABLE &&
1382             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1383                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1384                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1385                 else
1386                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1387         } else
1388                 flowctrl = tp->link_config.flowctrl;
1389
1390         tp->link_config.active_flowctrl = flowctrl;
1391
1392         if (flowctrl & FLOW_CTRL_RX)
1393                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1394         else
1395                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1396
1397         if (old_rx_mode != tp->rx_mode)
1398                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1399
1400         if (flowctrl & FLOW_CTRL_TX)
1401                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_tx_mode != tp->tx_mode)
1406                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1407 }
1408
1409 static void tg3_adjust_link(struct net_device *dev)
1410 {
1411         u8 oldflowctrl, linkmesg = 0;
1412         u32 mac_mode, lcl_adv, rmt_adv;
1413         struct tg3 *tp = netdev_priv(dev);
1414         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1415
1416         spin_lock_bh(&tp->lock);
1417
1418         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1419                                     MAC_MODE_HALF_DUPLEX);
1420
1421         oldflowctrl = tp->link_config.active_flowctrl;
1422
1423         if (phydev->link) {
1424                 lcl_adv = 0;
1425                 rmt_adv = 0;
1426
1427                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1428                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1429                 else if (phydev->speed == SPEED_1000 ||
1430                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1431                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1432                 else
1433                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1434
1435                 if (phydev->duplex == DUPLEX_HALF)
1436                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1437                 else {
1438                         lcl_adv = tg3_advert_flowctrl_1000T(
1439                                   tp->link_config.flowctrl);
1440
1441                         if (phydev->pause)
1442                                 rmt_adv = LPA_PAUSE_CAP;
1443                         if (phydev->asym_pause)
1444                                 rmt_adv |= LPA_PAUSE_ASYM;
1445                 }
1446
1447                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1448         } else
1449                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1450
1451         if (mac_mode != tp->mac_mode) {
1452                 tp->mac_mode = mac_mode;
1453                 tw32_f(MAC_MODE, tp->mac_mode);
1454                 udelay(40);
1455         }
1456
1457         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1458                 if (phydev->speed == SPEED_10)
1459                         tw32(MAC_MI_STAT,
1460                              MAC_MI_STAT_10MBPS_MODE |
1461                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462                 else
1463                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1464         }
1465
1466         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1467                 tw32(MAC_TX_LENGTHS,
1468                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1469                       (6 << TX_LENGTHS_IPG_SHIFT) |
1470                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1471         else
1472                 tw32(MAC_TX_LENGTHS,
1473                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1474                       (6 << TX_LENGTHS_IPG_SHIFT) |
1475                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1476
1477         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1478             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1479             phydev->speed != tp->link_config.active_speed ||
1480             phydev->duplex != tp->link_config.active_duplex ||
1481             oldflowctrl != tp->link_config.active_flowctrl)
1482                 linkmesg = 1;
1483
1484         tp->link_config.active_speed = phydev->speed;
1485         tp->link_config.active_duplex = phydev->duplex;
1486
1487         spin_unlock_bh(&tp->lock);
1488
1489         if (linkmesg)
1490                 tg3_link_report(tp);
1491 }
1492
1493 static int tg3_phy_init(struct tg3 *tp)
1494 {
1495         struct phy_device *phydev;
1496
1497         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1498                 return 0;
1499
1500         /* Bring the PHY back to a known state. */
1501         tg3_bmcr_reset(tp);
1502
1503         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504
1505         /* Attach the MAC to the PHY. */
1506         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1507                              phydev->dev_flags, phydev->interface);
1508         if (IS_ERR(phydev)) {
1509                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1510                 return PTR_ERR(phydev);
1511         }
1512
1513         /* Mask with MAC supported features. */
1514         switch (phydev->interface) {
1515         case PHY_INTERFACE_MODE_GMII:
1516         case PHY_INTERFACE_MODE_RGMII:
1517                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1518                         phydev->supported &= (PHY_GBIT_FEATURES |
1519                                               SUPPORTED_Pause |
1520                                               SUPPORTED_Asym_Pause);
1521                         break;
1522                 }
1523                 /* fallthru */
1524         case PHY_INTERFACE_MODE_MII:
1525                 phydev->supported &= (PHY_BASIC_FEATURES |
1526                                       SUPPORTED_Pause |
1527                                       SUPPORTED_Asym_Pause);
1528                 break;
1529         default:
1530                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1531                 return -EINVAL;
1532         }
1533
1534         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1535
1536         phydev->advertising = phydev->supported;
1537
1538         return 0;
1539 }
1540
1541 static void tg3_phy_start(struct tg3 *tp)
1542 {
1543         struct phy_device *phydev;
1544
1545         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1546                 return;
1547
1548         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1549
1550         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1551                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1552                 phydev->speed = tp->link_config.orig_speed;
1553                 phydev->duplex = tp->link_config.orig_duplex;
1554                 phydev->autoneg = tp->link_config.orig_autoneg;
1555                 phydev->advertising = tp->link_config.orig_advertising;
1556         }
1557
1558         phy_start(phydev);
1559
1560         phy_start_aneg(phydev);
1561 }
1562
1563 static void tg3_phy_stop(struct tg3 *tp)
1564 {
1565         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1566                 return;
1567
1568         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569 }
1570
1571 static void tg3_phy_fini(struct tg3 *tp)
1572 {
1573         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1574                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1575                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1576         }
1577 }
1578
1579 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1580 {
1581         int err;
1582
1583         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1584         if (!err)
1585                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1586
1587         return err;
1588 }
1589
1590 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1591 {
1592         int err;
1593
1594         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1595         if (!err)
1596                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1597
1598         return err;
1599 }
1600
1601 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1602 {
1603         u32 phytest;
1604
1605         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1606                 u32 phy;
1607
1608                 tg3_writephy(tp, MII_TG3_FET_TEST,
1609                              phytest | MII_TG3_FET_SHADOW_EN);
1610                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1611                         if (enable)
1612                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1613                         else
1614                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1615                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1616                 }
1617                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1618         }
1619 }
1620
1621 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1622 {
1623         u32 reg;
1624
1625         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1626             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1627               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1628              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1629                 return;
1630
1631         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1632                 tg3_phy_fet_toggle_apd(tp, enable);
1633                 return;
1634         }
1635
1636         reg = MII_TG3_MISC_SHDW_WREN |
1637               MII_TG3_MISC_SHDW_SCR5_SEL |
1638               MII_TG3_MISC_SHDW_SCR5_LPED |
1639               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1640               MII_TG3_MISC_SHDW_SCR5_SDTL |
1641               MII_TG3_MISC_SHDW_SCR5_C125OE;
1642         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1643                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1644
1645         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1646
1647
1648         reg = MII_TG3_MISC_SHDW_WREN |
1649               MII_TG3_MISC_SHDW_APD_SEL |
1650               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1651         if (enable)
1652                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1653
1654         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1655 }
1656
1657 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1658 {
1659         u32 phy;
1660
1661         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1662             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1663                 return;
1664
1665         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1666                 u32 ephy;
1667
1668                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1669                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1670
1671                         tg3_writephy(tp, MII_TG3_FET_TEST,
1672                                      ephy | MII_TG3_FET_SHADOW_EN);
1673                         if (!tg3_readphy(tp, reg, &phy)) {
1674                                 if (enable)
1675                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1676                                 else
1677                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1678                                 tg3_writephy(tp, reg, phy);
1679                         }
1680                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1681                 }
1682         } else {
1683                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1684                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1685                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1686                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1687                         if (enable)
1688                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1689                         else
1690                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1691                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1692                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1693                 }
1694         }
1695 }
1696
1697 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1698 {
1699         u32 val;
1700
1701         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1702                 return;
1703
1704         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1705             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1706                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1707                              (val | (1 << 15) | (1 << 4)));
1708 }
1709
1710 static void tg3_phy_apply_otp(struct tg3 *tp)
1711 {
1712         u32 otp, phy;
1713
1714         if (!tp->phy_otp)
1715                 return;
1716
1717         otp = tp->phy_otp;
1718
1719         /* Enable SM_DSP clock and tx 6dB coding. */
1720         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1721               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1722               MII_TG3_AUXCTL_ACTL_TX_6DB;
1723         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1724
1725         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1726         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1727         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1728
1729         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1730               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1731         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1732
1733         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1734         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1736
1737         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1738         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1739
1740         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1741         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1742
1743         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1744               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1745         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1746
1747         /* Turn off SM_DSP clock. */
1748         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1749               MII_TG3_AUXCTL_ACTL_TX_6DB;
1750         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1751 }
1752
1753 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1754 {
1755         u32 val;
1756
1757         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1758                 return;
1759
1760         tp->setlpicnt = 0;
1761
1762         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1763             current_link_up == 1 &&
1764             tp->link_config.active_duplex == DUPLEX_FULL &&
1765             (tp->link_config.active_speed == SPEED_100 ||
1766              tp->link_config.active_speed == SPEED_1000)) {
1767                 u32 eeectl;
1768
1769                 if (tp->link_config.active_speed == SPEED_1000)
1770                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1771                 else
1772                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1773
1774                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1775
1776                 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1777                                   TG3_CL45_D7_EEERES_STAT, &val);
1778
1779                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1780                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1781                         tp->setlpicnt = 2;
1782         }
1783
1784         if (!tp->setlpicnt) {
1785                 val = tr32(TG3_CPMU_EEE_MODE);
1786                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1787         }
1788 }
1789
1790 static int tg3_wait_macro_done(struct tg3 *tp)
1791 {
1792         int limit = 100;
1793
1794         while (limit--) {
1795                 u32 tmp32;
1796
1797                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1798                         if ((tmp32 & 0x1000) == 0)
1799                                 break;
1800                 }
1801         }
1802         if (limit < 0)
1803                 return -EBUSY;
1804
1805         return 0;
1806 }
1807
1808 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1809 {
1810         static const u32 test_pat[4][6] = {
1811         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1812         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1813         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1814         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1815         };
1816         int chan;
1817
1818         for (chan = 0; chan < 4; chan++) {
1819                 int i;
1820
1821                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1822                              (chan * 0x2000) | 0x0200);
1823                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1824
1825                 for (i = 0; i < 6; i++)
1826                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1827                                      test_pat[chan][i]);
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1830                 if (tg3_wait_macro_done(tp)) {
1831                         *resetp = 1;
1832                         return -EBUSY;
1833                 }
1834
1835                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1836                              (chan * 0x2000) | 0x0200);
1837                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1838                 if (tg3_wait_macro_done(tp)) {
1839                         *resetp = 1;
1840                         return -EBUSY;
1841                 }
1842
1843                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1844                 if (tg3_wait_macro_done(tp)) {
1845                         *resetp = 1;
1846                         return -EBUSY;
1847                 }
1848
1849                 for (i = 0; i < 6; i += 2) {
1850                         u32 low, high;
1851
1852                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1853                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1854                             tg3_wait_macro_done(tp)) {
1855                                 *resetp = 1;
1856                                 return -EBUSY;
1857                         }
1858                         low &= 0x7fff;
1859                         high &= 0x000f;
1860                         if (low != test_pat[chan][i] ||
1861                             high != test_pat[chan][i+1]) {
1862                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1863                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1864                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1865
1866                                 return -EBUSY;
1867                         }
1868                 }
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1875 {
1876         int chan;
1877
1878         for (chan = 0; chan < 4; chan++) {
1879                 int i;
1880
1881                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1882                              (chan * 0x2000) | 0x0200);
1883                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1884                 for (i = 0; i < 6; i++)
1885                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1886                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1887                 if (tg3_wait_macro_done(tp))
1888                         return -EBUSY;
1889         }
1890
1891         return 0;
1892 }
1893
1894 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1895 {
1896         u32 reg32, phy9_orig;
1897         int retries, do_phy_reset, err;
1898
1899         retries = 10;
1900         do_phy_reset = 1;
1901         do {
1902                 if (do_phy_reset) {
1903                         err = tg3_bmcr_reset(tp);
1904                         if (err)
1905                                 return err;
1906                         do_phy_reset = 0;
1907                 }
1908
1909                 /* Disable transmitter and interrupt.  */
1910                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1911                         continue;
1912
1913                 reg32 |= 0x3000;
1914                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1915
1916                 /* Set full-duplex, 1000 mbps.  */
1917                 tg3_writephy(tp, MII_BMCR,
1918                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1919
1920                 /* Set to master mode.  */
1921                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1922                         continue;
1923
1924                 tg3_writephy(tp, MII_TG3_CTRL,
1925                              (MII_TG3_CTRL_AS_MASTER |
1926                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1927
1928                 /* Enable SM_DSP_CLOCK and 6dB.  */
1929                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1930
1931                 /* Block the PHY control access.  */
1932                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1933
1934                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1935                 if (!err)
1936                         break;
1937         } while (--retries);
1938
1939         err = tg3_phy_reset_chanpat(tp);
1940         if (err)
1941                 return err;
1942
1943         tg3_phydsp_write(tp, 0x8005, 0x0000);
1944
1945         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1946         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1947
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1949             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1950                 /* Set Extended packet length bit for jumbo frames */
1951                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1952         } else {
1953                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1954         }
1955
1956         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1957
1958         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1959                 reg32 &= ~0x3000;
1960                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1961         } else if (!err)
1962                 err = -EBUSY;
1963
1964         return err;
1965 }
1966
1967 /* This will reset the tigon3 PHY if there is no valid
1968  * link unless the FORCE argument is non-zero.
1969  */
1970 static int tg3_phy_reset(struct tg3 *tp)
1971 {
1972         u32 val, cpmuctrl;
1973         int err;
1974
1975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1976                 val = tr32(GRC_MISC_CFG);
1977                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1978                 udelay(40);
1979         }
1980         err  = tg3_readphy(tp, MII_BMSR, &val);
1981         err |= tg3_readphy(tp, MII_BMSR, &val);
1982         if (err != 0)
1983                 return -EBUSY;
1984
1985         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1986                 netif_carrier_off(tp->dev);
1987                 tg3_link_report(tp);
1988         }
1989
1990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1992             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1993                 err = tg3_phy_reset_5703_4_5(tp);
1994                 if (err)
1995                         return err;
1996                 goto out;
1997         }
1998
1999         cpmuctrl = 0;
2000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2001             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2002                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2003                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2004                         tw32(TG3_CPMU_CTRL,
2005                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2006         }
2007
2008         err = tg3_bmcr_reset(tp);
2009         if (err)
2010                 return err;
2011
2012         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2013                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2014                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2015
2016                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2017         }
2018
2019         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2020             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2021                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2022                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2023                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2024                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2025                         udelay(40);
2026                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2027                 }
2028         }
2029
2030         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2031              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2032             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2033                 return 0;
2034
2035         tg3_phy_apply_otp(tp);
2036
2037         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2038                 tg3_phy_toggle_apd(tp, true);
2039         else
2040                 tg3_phy_toggle_apd(tp, false);
2041
2042 out:
2043         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2044                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2045                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2046                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2047                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2048         }
2049         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2050                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2051                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2052         }
2053         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2055                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2056                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2057                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2058                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2059         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2060                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2061                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2062                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2063                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2064                         tg3_writephy(tp, MII_TG3_TEST1,
2065                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2066                 } else
2067                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2068                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2069         }
2070         /* Set Extended packet length bit (bit 14) on all chips that */
2071         /* support jumbo frames */
2072         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2073                 /* Cannot do read-modify-write on 5401 */
2074                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2075         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2076                 /* Set bit 14 with read-modify-write to preserve other bits */
2077                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2078                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2079                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2080         }
2081
2082         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2083          * jumbo frames transmission.
2084          */
2085         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2086                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2087                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2088                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2089         }
2090
2091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2092                 /* adjust output voltage */
2093                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2094         }
2095
2096         tg3_phy_toggle_automdix(tp, 1);
2097         tg3_phy_set_wirespeed(tp);
2098         return 0;
2099 }
2100
2101 static void tg3_frob_aux_power(struct tg3 *tp)
2102 {
2103         struct tg3 *tp_peer = tp;
2104
2105         /* The GPIOs do something completely different on 57765. */
2106         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2107             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2109                 return;
2110
2111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2112             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2113             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2114                 struct net_device *dev_peer;
2115
2116                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2117                 /* remove_one() may have been run on the peer. */
2118                 if (!dev_peer)
2119                         tp_peer = tp;
2120                 else
2121                         tp_peer = netdev_priv(dev_peer);
2122         }
2123
2124         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2125             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2126             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2127             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2128                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2129                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131                                     (GRC_LCLCTRL_GPIO_OE0 |
2132                                      GRC_LCLCTRL_GPIO_OE1 |
2133                                      GRC_LCLCTRL_GPIO_OE2 |
2134                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2135                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2136                                     100);
2137                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2138                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2139                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2140                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2141                                              GRC_LCLCTRL_GPIO_OE1 |
2142                                              GRC_LCLCTRL_GPIO_OE2 |
2143                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2144                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2145                                              tp->grc_local_ctrl;
2146                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2147
2148                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2149                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2150
2151                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2152                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2153                 } else {
2154                         u32 no_gpio2;
2155                         u32 grc_local_ctrl = 0;
2156
2157                         if (tp_peer != tp &&
2158                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2159                                 return;
2160
2161                         /* Workaround to prevent overdrawing Amps. */
2162                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2163                             ASIC_REV_5714) {
2164                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2165                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2166                                             grc_local_ctrl, 100);
2167                         }
2168
2169                         /* On 5753 and variants, GPIO2 cannot be used. */
2170                         no_gpio2 = tp->nic_sram_data_cfg &
2171                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2172
2173                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2174                                          GRC_LCLCTRL_GPIO_OE1 |
2175                                          GRC_LCLCTRL_GPIO_OE2 |
2176                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2177                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2178                         if (no_gpio2) {
2179                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2180                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2181                         }
2182                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2183                                                     grc_local_ctrl, 100);
2184
2185                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2186
2187                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2188                                                     grc_local_ctrl, 100);
2189
2190                         if (!no_gpio2) {
2191                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2192                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2193                                             grc_local_ctrl, 100);
2194                         }
2195                 }
2196         } else {
2197                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2198                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2199                         if (tp_peer != tp &&
2200                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2201                                 return;
2202
2203                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2204                                     (GRC_LCLCTRL_GPIO_OE1 |
2205                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2206
2207                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2208                                     GRC_LCLCTRL_GPIO_OE1, 100);
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213                 }
2214         }
2215 }
2216
2217 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2218 {
2219         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2220                 return 1;
2221         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2222                 if (speed != SPEED_10)
2223                         return 1;
2224         } else if (speed == SPEED_10)
2225                 return 1;
2226
2227         return 0;
2228 }
2229
2230 static int tg3_setup_phy(struct tg3 *, int);
2231
2232 #define RESET_KIND_SHUTDOWN     0
2233 #define RESET_KIND_INIT         1
2234 #define RESET_KIND_SUSPEND      2
2235
2236 static void tg3_write_sig_post_reset(struct tg3 *, int);
2237 static int tg3_halt_cpu(struct tg3 *, u32);
2238
2239 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2240 {
2241         u32 val;
2242
2243         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2244                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2245                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2246                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2247
2248                         sg_dig_ctrl |=
2249                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2250                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2251                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2252                 }
2253                 return;
2254         }
2255
2256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2257                 tg3_bmcr_reset(tp);
2258                 val = tr32(GRC_MISC_CFG);
2259                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2260                 udelay(40);
2261                 return;
2262         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2263                 u32 phytest;
2264                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2265                         u32 phy;
2266
2267                         tg3_writephy(tp, MII_ADVERTISE, 0);
2268                         tg3_writephy(tp, MII_BMCR,
2269                                      BMCR_ANENABLE | BMCR_ANRESTART);
2270
2271                         tg3_writephy(tp, MII_TG3_FET_TEST,
2272                                      phytest | MII_TG3_FET_SHADOW_EN);
2273                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2274                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2275                                 tg3_writephy(tp,
2276                                              MII_TG3_FET_SHDW_AUXMODE4,
2277                                              phy);
2278                         }
2279                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2280                 }
2281                 return;
2282         } else if (do_low_power) {
2283                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2284                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2285
2286                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2287                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2288                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2289                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2290                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2291         }
2292
2293         /* The PHY should not be powered down on some chips because
2294          * of bugs.
2295          */
2296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2298             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2299              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2300                 return;
2301
2302         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2303             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2304                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2305                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2306                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2307                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2308         }
2309
2310         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2311 }
2312
2313 /* tp->lock is held. */
2314 static int tg3_nvram_lock(struct tg3 *tp)
2315 {
2316         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2317                 int i;
2318
2319                 if (tp->nvram_lock_cnt == 0) {
2320                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2321                         for (i = 0; i < 8000; i++) {
2322                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2323                                         break;
2324                                 udelay(20);
2325                         }
2326                         if (i == 8000) {
2327                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2328                                 return -ENODEV;
2329                         }
2330                 }
2331                 tp->nvram_lock_cnt++;
2332         }
2333         return 0;
2334 }
2335
2336 /* tp->lock is held. */
2337 static void tg3_nvram_unlock(struct tg3 *tp)
2338 {
2339         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2340                 if (tp->nvram_lock_cnt > 0)
2341                         tp->nvram_lock_cnt--;
2342                 if (tp->nvram_lock_cnt == 0)
2343                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2344         }
2345 }
2346
2347 /* tp->lock is held. */
2348 static void tg3_enable_nvram_access(struct tg3 *tp)
2349 {
2350         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2351             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2352                 u32 nvaccess = tr32(NVRAM_ACCESS);
2353
2354                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2355         }
2356 }
2357
2358 /* tp->lock is held. */
2359 static void tg3_disable_nvram_access(struct tg3 *tp)
2360 {
2361         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2362             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2363                 u32 nvaccess = tr32(NVRAM_ACCESS);
2364
2365                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2366         }
2367 }
2368
2369 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2370                                         u32 offset, u32 *val)
2371 {
2372         u32 tmp;
2373         int i;
2374
2375         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2376                 return -EINVAL;
2377
2378         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2379                                         EEPROM_ADDR_DEVID_MASK |
2380                                         EEPROM_ADDR_READ);
2381         tw32(GRC_EEPROM_ADDR,
2382              tmp |
2383              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2384              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2385               EEPROM_ADDR_ADDR_MASK) |
2386              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2387
2388         for (i = 0; i < 1000; i++) {
2389                 tmp = tr32(GRC_EEPROM_ADDR);
2390
2391                 if (tmp & EEPROM_ADDR_COMPLETE)
2392                         break;
2393                 msleep(1);
2394         }
2395         if (!(tmp & EEPROM_ADDR_COMPLETE))
2396                 return -EBUSY;
2397
2398         tmp = tr32(GRC_EEPROM_DATA);
2399
2400         /*
2401          * The data will always be opposite the native endian
2402          * format.  Perform a blind byteswap to compensate.
2403          */
2404         *val = swab32(tmp);
2405
2406         return 0;
2407 }
2408
2409 #define NVRAM_CMD_TIMEOUT 10000
2410
2411 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2412 {
2413         int i;
2414
2415         tw32(NVRAM_CMD, nvram_cmd);
2416         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2417                 udelay(10);
2418                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2419                         udelay(10);
2420                         break;
2421                 }
2422         }
2423
2424         if (i == NVRAM_CMD_TIMEOUT)
2425                 return -EBUSY;
2426
2427         return 0;
2428 }
2429
2430 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2431 {
2432         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2433             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2434             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2435            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2436             (tp->nvram_jedecnum == JEDEC_ATMEL))
2437
2438                 addr = ((addr / tp->nvram_pagesize) <<
2439                         ATMEL_AT45DB0X1B_PAGE_POS) +
2440                        (addr % tp->nvram_pagesize);
2441
2442         return addr;
2443 }
2444
2445 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2446 {
2447         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2448             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2449             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2450            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2451             (tp->nvram_jedecnum == JEDEC_ATMEL))
2452
2453                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2454                         tp->nvram_pagesize) +
2455                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2456
2457         return addr;
2458 }
2459
2460 /* NOTE: Data read in from NVRAM is byteswapped according to
2461  * the byteswapping settings for all other register accesses.
2462  * tg3 devices are BE devices, so on a BE machine, the data
2463  * returned will be exactly as it is seen in NVRAM.  On a LE
2464  * machine, the 32-bit value will be byteswapped.
2465  */
2466 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2467 {
2468         int ret;
2469
2470         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2471                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2472
2473         offset = tg3_nvram_phys_addr(tp, offset);
2474
2475         if (offset > NVRAM_ADDR_MSK)
2476                 return -EINVAL;
2477
2478         ret = tg3_nvram_lock(tp);
2479         if (ret)
2480                 return ret;
2481
2482         tg3_enable_nvram_access(tp);
2483
2484         tw32(NVRAM_ADDR, offset);
2485         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2486                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2487
2488         if (ret == 0)
2489                 *val = tr32(NVRAM_RDDATA);
2490
2491         tg3_disable_nvram_access(tp);
2492
2493         tg3_nvram_unlock(tp);
2494
2495         return ret;
2496 }
2497
2498 /* Ensures NVRAM data is in bytestream format. */
2499 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2500 {
2501         u32 v;
2502         int res = tg3_nvram_read(tp, offset, &v);
2503         if (!res)
2504                 *val = cpu_to_be32(v);
2505         return res;
2506 }
2507
2508 /* tp->lock is held. */
2509 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2510 {
2511         u32 addr_high, addr_low;
2512         int i;
2513
2514         addr_high = ((tp->dev->dev_addr[0] << 8) |
2515                      tp->dev->dev_addr[1]);
2516         addr_low = ((tp->dev->dev_addr[2] << 24) |
2517                     (tp->dev->dev_addr[3] << 16) |
2518                     (tp->dev->dev_addr[4] <<  8) |
2519                     (tp->dev->dev_addr[5] <<  0));
2520         for (i = 0; i < 4; i++) {
2521                 if (i == 1 && skip_mac_1)
2522                         continue;
2523                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2524                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2525         }
2526
2527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2528             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2529                 for (i = 0; i < 12; i++) {
2530                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2531                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2532                 }
2533         }
2534
2535         addr_high = (tp->dev->dev_addr[0] +
2536                      tp->dev->dev_addr[1] +
2537                      tp->dev->dev_addr[2] +
2538                      tp->dev->dev_addr[3] +
2539                      tp->dev->dev_addr[4] +
2540                      tp->dev->dev_addr[5]) &
2541                 TX_BACKOFF_SEED_MASK;
2542         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2543 }
2544
2545 static void tg3_enable_register_access(struct tg3 *tp)
2546 {
2547         /*
2548          * Make sure register accesses (indirect or otherwise) will function
2549          * correctly.
2550          */
2551         pci_write_config_dword(tp->pdev,
2552                                TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2553 }
2554
2555 static int tg3_power_up(struct tg3 *tp)
2556 {
2557         tg3_enable_register_access(tp);
2558
2559         pci_set_power_state(tp->pdev, PCI_D0);
2560
2561         /* Switch out of Vaux if it is a NIC */
2562         if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2563                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2564
2565         return 0;
2566 }
2567
2568 static int tg3_power_down_prepare(struct tg3 *tp)
2569 {
2570         u32 misc_host_ctrl;
2571         bool device_should_wake, do_low_power;
2572
2573         tg3_enable_register_access(tp);
2574
2575         /* Restore the CLKREQ setting. */
2576         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2577                 u16 lnkctl;
2578
2579                 pci_read_config_word(tp->pdev,
2580                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2581                                      &lnkctl);
2582                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2583                 pci_write_config_word(tp->pdev,
2584                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2585                                       lnkctl);
2586         }
2587
2588         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2589         tw32(TG3PCI_MISC_HOST_CTRL,
2590              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2591
2592         device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2593                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2594
2595         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2596                 do_low_power = false;
2597                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2598                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2599                         struct phy_device *phydev;
2600                         u32 phyid, advertising;
2601
2602                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2603
2604                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2605
2606                         tp->link_config.orig_speed = phydev->speed;
2607                         tp->link_config.orig_duplex = phydev->duplex;
2608                         tp->link_config.orig_autoneg = phydev->autoneg;
2609                         tp->link_config.orig_advertising = phydev->advertising;
2610
2611                         advertising = ADVERTISED_TP |
2612                                       ADVERTISED_Pause |
2613                                       ADVERTISED_Autoneg |
2614                                       ADVERTISED_10baseT_Half;
2615
2616                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2617                             device_should_wake) {
2618                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2619                                         advertising |=
2620                                                 ADVERTISED_100baseT_Half |
2621                                                 ADVERTISED_100baseT_Full |
2622                                                 ADVERTISED_10baseT_Full;
2623                                 else
2624                                         advertising |= ADVERTISED_10baseT_Full;
2625                         }
2626
2627                         phydev->advertising = advertising;
2628
2629                         phy_start_aneg(phydev);
2630
2631                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2632                         if (phyid != PHY_ID_BCMAC131) {
2633                                 phyid &= PHY_BCM_OUI_MASK;
2634                                 if (phyid == PHY_BCM_OUI_1 ||
2635                                     phyid == PHY_BCM_OUI_2 ||
2636                                     phyid == PHY_BCM_OUI_3)
2637                                         do_low_power = true;
2638                         }
2639                 }
2640         } else {
2641                 do_low_power = true;
2642
2643                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2644                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2645                         tp->link_config.orig_speed = tp->link_config.speed;
2646                         tp->link_config.orig_duplex = tp->link_config.duplex;
2647                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2648                 }
2649
2650                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2651                         tp->link_config.speed = SPEED_10;
2652                         tp->link_config.duplex = DUPLEX_HALF;
2653                         tp->link_config.autoneg = AUTONEG_ENABLE;
2654                         tg3_setup_phy(tp, 0);
2655                 }
2656         }
2657
2658         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2659                 u32 val;
2660
2661                 val = tr32(GRC_VCPU_EXT_CTRL);
2662                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2663         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2664                 int i;
2665                 u32 val;
2666
2667                 for (i = 0; i < 200; i++) {
2668                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2669                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2670                                 break;
2671                         msleep(1);
2672                 }
2673         }
2674         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2675                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2676                                                      WOL_DRV_STATE_SHUTDOWN |
2677                                                      WOL_DRV_WOL |
2678                                                      WOL_SET_MAGIC_PKT);
2679
2680         if (device_should_wake) {
2681                 u32 mac_mode;
2682
2683                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2684                         if (do_low_power) {
2685                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2686                                 udelay(40);
2687                         }
2688
2689                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2690                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2691                         else
2692                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2693
2694                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2695                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2696                             ASIC_REV_5700) {
2697                                 u32 speed = (tp->tg3_flags &
2698                                              TG3_FLAG_WOL_SPEED_100MB) ?
2699                                              SPEED_100 : SPEED_10;
2700                                 if (tg3_5700_link_polarity(tp, speed))
2701                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2702                                 else
2703                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704                         }
2705                 } else {
2706                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2707                 }
2708
2709                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2710                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2711
2712                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2713                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2714                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2715                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2716                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2717                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2718
2719                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2720                         mac_mode |= MAC_MODE_APE_TX_EN |
2721                                     MAC_MODE_APE_RX_EN |
2722                                     MAC_MODE_TDE_ENABLE;
2723
2724                 tw32_f(MAC_MODE, mac_mode);
2725                 udelay(100);
2726
2727                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2728                 udelay(10);
2729         }
2730
2731         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2732             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2733              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2734                 u32 base_val;
2735
2736                 base_val = tp->pci_clock_ctrl;
2737                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2738                              CLOCK_CTRL_TXCLK_DISABLE);
2739
2740                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2741                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2742         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2743                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2744                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2745                 /* do nothing */
2746         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2747                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2748                 u32 newbits1, newbits2;
2749
2750                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2751                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2752                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2753                                     CLOCK_CTRL_TXCLK_DISABLE |
2754                                     CLOCK_CTRL_ALTCLK);
2755                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2756                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2757                         newbits1 = CLOCK_CTRL_625_CORE;
2758                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2759                 } else {
2760                         newbits1 = CLOCK_CTRL_ALTCLK;
2761                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2762                 }
2763
2764                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2765                             40);
2766
2767                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2768                             40);
2769
2770                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2771                         u32 newbits3;
2772
2773                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2774                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2775                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2776                                             CLOCK_CTRL_TXCLK_DISABLE |
2777                                             CLOCK_CTRL_44MHZ_CORE);
2778                         } else {
2779                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2780                         }
2781
2782                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2783                                     tp->pci_clock_ctrl | newbits3, 40);
2784                 }
2785         }
2786
2787         if (!(device_should_wake) &&
2788             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2789                 tg3_power_down_phy(tp, do_low_power);
2790
2791         tg3_frob_aux_power(tp);
2792
2793         /* Workaround for unstable PLL clock */
2794         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2795             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2796                 u32 val = tr32(0x7d00);
2797
2798                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2799                 tw32(0x7d00, val);
2800                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2801                         int err;
2802
2803                         err = tg3_nvram_lock(tp);
2804                         tg3_halt_cpu(tp, RX_CPU_BASE);
2805                         if (!err)
2806                                 tg3_nvram_unlock(tp);
2807                 }
2808         }
2809
2810         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2811
2812         return 0;
2813 }
2814
2815 static void tg3_power_down(struct tg3 *tp)
2816 {
2817         tg3_power_down_prepare(tp);
2818
2819         pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2820         pci_set_power_state(tp->pdev, PCI_D3hot);
2821 }
2822
2823 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2824 {
2825         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2826         case MII_TG3_AUX_STAT_10HALF:
2827                 *speed = SPEED_10;
2828                 *duplex = DUPLEX_HALF;
2829                 break;
2830
2831         case MII_TG3_AUX_STAT_10FULL:
2832                 *speed = SPEED_10;
2833                 *duplex = DUPLEX_FULL;
2834                 break;
2835
2836         case MII_TG3_AUX_STAT_100HALF:
2837                 *speed = SPEED_100;
2838                 *duplex = DUPLEX_HALF;
2839                 break;
2840
2841         case MII_TG3_AUX_STAT_100FULL:
2842                 *speed = SPEED_100;
2843                 *duplex = DUPLEX_FULL;
2844                 break;
2845
2846         case MII_TG3_AUX_STAT_1000HALF:
2847                 *speed = SPEED_1000;
2848                 *duplex = DUPLEX_HALF;
2849                 break;
2850
2851         case MII_TG3_AUX_STAT_1000FULL:
2852                 *speed = SPEED_1000;
2853                 *duplex = DUPLEX_FULL;
2854                 break;
2855
2856         default:
2857                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2858                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2859                                  SPEED_10;
2860                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2861                                   DUPLEX_HALF;
2862                         break;
2863                 }
2864                 *speed = SPEED_INVALID;
2865                 *duplex = DUPLEX_INVALID;
2866                 break;
2867         }
2868 }
2869
2870 static void tg3_phy_copper_begin(struct tg3 *tp)
2871 {
2872         u32 new_adv;
2873         int i;
2874
2875         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2876                 /* Entering low power mode.  Disable gigabit and
2877                  * 100baseT advertisements.
2878                  */
2879                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2880
2881                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2882                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2883                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2884                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2885
2886                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2887         } else if (tp->link_config.speed == SPEED_INVALID) {
2888                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2889                         tp->link_config.advertising &=
2890                                 ~(ADVERTISED_1000baseT_Half |
2891                                   ADVERTISED_1000baseT_Full);
2892
2893                 new_adv = ADVERTISE_CSMA;
2894                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2895                         new_adv |= ADVERTISE_10HALF;
2896                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2897                         new_adv |= ADVERTISE_10FULL;
2898                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2899                         new_adv |= ADVERTISE_100HALF;
2900                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2901                         new_adv |= ADVERTISE_100FULL;
2902
2903                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2904
2905                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2906
2907                 if (tp->link_config.advertising &
2908                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2909                         new_adv = 0;
2910                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2911                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2912                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2913                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2914                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2915                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2916                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2917                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2918                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2919                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2920                 } else {
2921                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2922                 }
2923         } else {
2924                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2925                 new_adv |= ADVERTISE_CSMA;
2926
2927                 /* Asking for a specific link mode. */
2928                 if (tp->link_config.speed == SPEED_1000) {
2929                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2930
2931                         if (tp->link_config.duplex == DUPLEX_FULL)
2932                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2933                         else
2934                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2935                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2936                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2937                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2938                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2939                 } else {
2940                         if (tp->link_config.speed == SPEED_100) {
2941                                 if (tp->link_config.duplex == DUPLEX_FULL)
2942                                         new_adv |= ADVERTISE_100FULL;
2943                                 else
2944                                         new_adv |= ADVERTISE_100HALF;
2945                         } else {
2946                                 if (tp->link_config.duplex == DUPLEX_FULL)
2947                                         new_adv |= ADVERTISE_10FULL;
2948                                 else
2949                                         new_adv |= ADVERTISE_10HALF;
2950                         }
2951                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2952
2953                         new_adv = 0;
2954                 }
2955
2956                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2957         }
2958
2959         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2960                 u32 val;
2961
2962                 tw32(TG3_CPMU_EEE_MODE,
2963                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2964
2965                 /* Enable SM_DSP clock and tx 6dB coding. */
2966                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2967                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2968                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2970
2971                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2972                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2973                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2974                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2975                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2976
2977                 val = 0;
2978                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2979                         /* Advertise 100-BaseTX EEE ability */
2980                         if (tp->link_config.advertising &
2981                             ADVERTISED_100baseT_Full)
2982                                 val |= MDIO_AN_EEE_ADV_100TX;
2983                         /* Advertise 1000-BaseT EEE ability */
2984                         if (tp->link_config.advertising &
2985                             ADVERTISED_1000baseT_Full)
2986                                 val |= MDIO_AN_EEE_ADV_1000T;
2987                 }
2988                 tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2989
2990                 /* Turn off SM_DSP clock. */
2991                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2992                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2993                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2994         }
2995
2996         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2997             tp->link_config.speed != SPEED_INVALID) {
2998                 u32 bmcr, orig_bmcr;
2999
3000                 tp->link_config.active_speed = tp->link_config.speed;
3001                 tp->link_config.active_duplex = tp->link_config.duplex;
3002
3003                 bmcr = 0;
3004                 switch (tp->link_config.speed) {
3005                 default:
3006                 case SPEED_10:
3007                         break;
3008
3009                 case SPEED_100:
3010                         bmcr |= BMCR_SPEED100;
3011                         break;
3012
3013                 case SPEED_1000:
3014                         bmcr |= TG3_BMCR_SPEED1000;
3015                         break;
3016                 }
3017
3018                 if (tp->link_config.duplex == DUPLEX_FULL)
3019                         bmcr |= BMCR_FULLDPLX;
3020
3021                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3022                     (bmcr != orig_bmcr)) {
3023                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3024                         for (i = 0; i < 1500; i++) {
3025                                 u32 tmp;
3026
3027                                 udelay(10);
3028                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3029                                     tg3_readphy(tp, MII_BMSR, &tmp))
3030                                         continue;
3031                                 if (!(tmp & BMSR_LSTATUS)) {
3032                                         udelay(40);
3033                                         break;
3034                                 }
3035                         }
3036                         tg3_writephy(tp, MII_BMCR, bmcr);
3037                         udelay(40);
3038                 }
3039         } else {
3040                 tg3_writephy(tp, MII_BMCR,
3041                              BMCR_ANENABLE | BMCR_ANRESTART);
3042         }
3043 }
3044
3045 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3046 {
3047         int err;
3048
3049         /* Turn off tap power management. */
3050         /* Set Extended packet length bit */
3051         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3052
3053         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3054         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3055         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3056         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3057         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3058
3059         udelay(40);
3060
3061         return err;
3062 }
3063
3064 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3065 {
3066         u32 adv_reg, all_mask = 0;
3067
3068         if (mask & ADVERTISED_10baseT_Half)
3069                 all_mask |= ADVERTISE_10HALF;
3070         if (mask & ADVERTISED_10baseT_Full)
3071                 all_mask |= ADVERTISE_10FULL;
3072         if (mask & ADVERTISED_100baseT_Half)
3073                 all_mask |= ADVERTISE_100HALF;
3074         if (mask & ADVERTISED_100baseT_Full)
3075                 all_mask |= ADVERTISE_100FULL;
3076
3077         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3078                 return 0;
3079
3080         if ((adv_reg & all_mask) != all_mask)
3081                 return 0;
3082         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3083                 u32 tg3_ctrl;
3084
3085                 all_mask = 0;
3086                 if (mask & ADVERTISED_1000baseT_Half)
3087                         all_mask |= ADVERTISE_1000HALF;
3088                 if (mask & ADVERTISED_1000baseT_Full)
3089                         all_mask |= ADVERTISE_1000FULL;
3090
3091                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3092                         return 0;
3093
3094                 if ((tg3_ctrl & all_mask) != all_mask)
3095                         return 0;
3096         }
3097         return 1;
3098 }
3099
3100 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3101 {
3102         u32 curadv, reqadv;
3103
3104         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3105                 return 1;
3106
3107         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3108         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3109
3110         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3111                 if (curadv != reqadv)
3112                         return 0;
3113
3114                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3115                         tg3_readphy(tp, MII_LPA, rmtadv);
3116         } else {
3117                 /* Reprogram the advertisement register, even if it
3118                  * does not affect the current link.  If the link
3119                  * gets renegotiated in the future, we can save an
3120                  * additional renegotiation cycle by advertising
3121                  * it correctly in the first place.
3122                  */
3123                 if (curadv != reqadv) {
3124                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3125                                      ADVERTISE_PAUSE_ASYM);
3126                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3127                 }
3128         }
3129
3130         return 1;
3131 }
3132
3133 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3134 {
3135         int current_link_up;
3136         u32 bmsr, val;
3137         u32 lcl_adv, rmt_adv;
3138         u16 current_speed;
3139         u8 current_duplex;
3140         int i, err;
3141
3142         tw32(MAC_EVENT, 0);
3143
3144         tw32_f(MAC_STATUS,
3145              (MAC_STATUS_SYNC_CHANGED |
3146               MAC_STATUS_CFG_CHANGED |
3147               MAC_STATUS_MI_COMPLETION |
3148               MAC_STATUS_LNKSTATE_CHANGED));
3149         udelay(40);
3150
3151         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3152                 tw32_f(MAC_MI_MODE,
3153                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3154                 udelay(80);
3155         }
3156
3157         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3158
3159         /* Some third-party PHYs need to be reset on link going
3160          * down.
3161          */
3162         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3163              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3164              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3165             netif_carrier_ok(tp->dev)) {
3166                 tg3_readphy(tp, MII_BMSR, &bmsr);
3167                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3168                     !(bmsr & BMSR_LSTATUS))
3169                         force_reset = 1;
3170         }
3171         if (force_reset)
3172                 tg3_phy_reset(tp);
3173
3174         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3175                 tg3_readphy(tp, MII_BMSR, &bmsr);
3176                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3177                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3178                         bmsr = 0;
3179
3180                 if (!(bmsr & BMSR_LSTATUS)) {
3181                         err = tg3_init_5401phy_dsp(tp);
3182                         if (err)
3183                                 return err;
3184
3185                         tg3_readphy(tp, MII_BMSR, &bmsr);
3186                         for (i = 0; i < 1000; i++) {
3187                                 udelay(10);
3188                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3189                                     (bmsr & BMSR_LSTATUS)) {
3190                                         udelay(40);
3191                                         break;
3192                                 }
3193                         }
3194
3195                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3196                             TG3_PHY_REV_BCM5401_B0 &&
3197                             !(bmsr & BMSR_LSTATUS) &&
3198                             tp->link_config.active_speed == SPEED_1000) {
3199                                 err = tg3_phy_reset(tp);
3200                                 if (!err)
3201                                         err = tg3_init_5401phy_dsp(tp);
3202                                 if (err)
3203                                         return err;
3204                         }
3205                 }
3206         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3207                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3208                 /* 5701 {A0,B0} CRC bug workaround */
3209                 tg3_writephy(tp, 0x15, 0x0a75);
3210                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3211                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3212                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3213         }
3214
3215         /* Clear pending interrupts... */
3216         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3217         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3218
3219         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3220                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3221         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3222                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3223
3224         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3225             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3226                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3227                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3228                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3229                 else
3230                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3231         }
3232
3233         current_link_up = 0;
3234         current_speed = SPEED_INVALID;
3235         current_duplex = DUPLEX_INVALID;
3236
3237         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3238                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3239                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3240                 if (!(val & (1 << 10))) {
3241                         val |= (1 << 10);
3242                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3243                         goto relink;
3244                 }
3245         }
3246
3247         bmsr = 0;
3248         for (i = 0; i < 100; i++) {
3249                 tg3_readphy(tp, MII_BMSR, &bmsr);
3250                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3251                     (bmsr & BMSR_LSTATUS))
3252                         break;
3253                 udelay(40);
3254         }
3255
3256         if (bmsr & BMSR_LSTATUS) {
3257                 u32 aux_stat, bmcr;
3258
3259                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3260                 for (i = 0; i < 2000; i++) {
3261                         udelay(10);
3262                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3263                             aux_stat)
3264                                 break;
3265                 }
3266
3267                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3268                                              &current_speed,
3269                                              &current_duplex);
3270
3271                 bmcr = 0;
3272                 for (i = 0; i < 200; i++) {
3273                         tg3_readphy(tp, MII_BMCR, &bmcr);
3274                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3275                                 continue;
3276                         if (bmcr && bmcr != 0x7fff)
3277                                 break;
3278                         udelay(10);
3279                 }
3280
3281                 lcl_adv = 0;
3282                 rmt_adv = 0;
3283
3284                 tp->link_config.active_speed = current_speed;
3285                 tp->link_config.active_duplex = current_duplex;
3286
3287                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3288                         if ((bmcr & BMCR_ANENABLE) &&
3289                             tg3_copper_is_advertising_all(tp,
3290                                                 tp->link_config.advertising)) {
3291                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3292                                                                   &rmt_adv))
3293                                         current_link_up = 1;
3294                         }
3295                 } else {
3296                         if (!(bmcr & BMCR_ANENABLE) &&
3297                             tp->link_config.speed == current_speed &&
3298                             tp->link_config.duplex == current_duplex &&
3299                             tp->link_config.flowctrl ==
3300                             tp->link_config.active_flowctrl) {
3301                                 current_link_up = 1;
3302                         }
3303                 }
3304
3305                 if (current_link_up == 1 &&
3306                     tp->link_config.active_duplex == DUPLEX_FULL)
3307                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3308         }
3309
3310 relink:
3311         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3312                 tg3_phy_copper_begin(tp);
3313
3314                 tg3_readphy(tp, MII_BMSR, &bmsr);
3315                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3316                     (bmsr & BMSR_LSTATUS))
3317                         current_link_up = 1;
3318         }
3319
3320         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3321         if (current_link_up == 1) {
3322                 if (tp->link_config.active_speed == SPEED_100 ||
3323                     tp->link_config.active_speed == SPEED_10)
3324                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3325                 else
3326                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3327         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3328                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3329         else
3330                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3331
3332         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3333         if (tp->link_config.active_duplex == DUPLEX_HALF)
3334                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3335
3336         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3337                 if (current_link_up == 1 &&
3338                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3339                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3340                 else
3341                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3342         }
3343
3344         /* ??? Without this setting Netgear GA302T PHY does not
3345          * ??? send/receive packets...
3346          */
3347         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3348             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3349                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3350                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3351                 udelay(80);
3352         }
3353
3354         tw32_f(MAC_MODE, tp->mac_mode);
3355         udelay(40);
3356
3357         tg3_phy_eee_adjust(tp, current_link_up);
3358
3359         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3360                 /* Polled via timer. */
3361                 tw32_f(MAC_EVENT, 0);
3362         } else {
3363                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3364         }
3365         udelay(40);
3366
3367         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3368             current_link_up == 1 &&
3369             tp->link_config.active_speed == SPEED_1000 &&
3370             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3371              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3372                 udelay(120);
3373                 tw32_f(MAC_STATUS,
3374                      (MAC_STATUS_SYNC_CHANGED |
3375                       MAC_STATUS_CFG_CHANGED));
3376                 udelay(40);
3377                 tg3_write_mem(tp,
3378                               NIC_SRAM_FIRMWARE_MBOX,
3379                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3380         }
3381
3382         /* Prevent send BD corruption. */
3383         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3384                 u16 oldlnkctl, newlnkctl;
3385
3386                 pci_read_config_word(tp->pdev,
3387                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3388                                      &oldlnkctl);
3389                 if (tp->link_config.active_speed == SPEED_100 ||
3390                     tp->link_config.active_speed == SPEED_10)
3391                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3392                 else
3393                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3394                 if (newlnkctl != oldlnkctl)
3395                         pci_write_config_word(tp->pdev,
3396                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3397                                               newlnkctl);
3398         }
3399
3400         if (current_link_up != netif_carrier_ok(tp->dev)) {
3401                 if (current_link_up)
3402                         netif_carrier_on(tp->dev);
3403                 else
3404                         netif_carrier_off(tp->dev);
3405                 tg3_link_report(tp);
3406         }
3407
3408         return 0;
3409 }
3410
3411 struct tg3_fiber_aneginfo {
3412         int state;
3413 #define ANEG_STATE_UNKNOWN              0
3414 #define ANEG_STATE_AN_ENABLE            1
3415 #define ANEG_STATE_RESTART_INIT         2
3416 #define ANEG_STATE_RESTART              3
3417 #define ANEG_STATE_DISABLE_LINK_OK      4
3418 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3419 #define ANEG_STATE_ABILITY_DETECT       6
3420 #define ANEG_STATE_ACK_DETECT_INIT      7
3421 #define ANEG_STATE_ACK_DETECT           8
3422 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3423 #define ANEG_STATE_COMPLETE_ACK         10
3424 #define ANEG_STATE_IDLE_DETECT_INIT     11
3425 #define ANEG_STATE_IDLE_DETECT          12
3426 #define ANEG_STATE_LINK_OK              13
3427 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3428 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3429
3430         u32 flags;
3431 #define MR_AN_ENABLE            0x00000001
3432 #define MR_RESTART_AN           0x00000002
3433 #define MR_AN_COMPLETE          0x00000004
3434 #define MR_PAGE_RX              0x00000008
3435 #define MR_NP_LOADED            0x00000010
3436 #define MR_TOGGLE_TX            0x00000020
3437 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3438 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3439 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3440 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3441 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3442 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3443 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3444 #define MR_TOGGLE_RX            0x00002000
3445 #define MR_NP_RX                0x00004000
3446
3447 #define MR_LINK_OK              0x80000000
3448
3449         unsigned long link_time, cur_time;
3450
3451         u32 ability_match_cfg;
3452         int ability_match_count;
3453
3454         char ability_match, idle_match, ack_match;
3455
3456         u32 txconfig, rxconfig;
3457 #define ANEG_CFG_NP             0x00000080
3458 #define ANEG_CFG_ACK            0x00000040
3459 #define ANEG_CFG_RF2            0x00000020
3460 #define ANEG_CFG_RF1            0x00000010
3461 #define ANEG_CFG_PS2            0x00000001
3462 #define ANEG_CFG_PS1            0x00008000
3463 #define ANEG_CFG_HD             0x00004000
3464 #define ANEG_CFG_FD             0x00002000
3465 #define ANEG_CFG_INVAL          0x00001f06
3466
3467 };
3468 #define ANEG_OK         0
3469 #define ANEG_DONE       1
3470 #define ANEG_TIMER_ENAB 2
3471 #define ANEG_FAILED     -1
3472
3473 #define ANEG_STATE_SETTLE_TIME  10000
3474
3475 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3476                                    struct tg3_fiber_aneginfo *ap)
3477 {
3478         u16 flowctrl;
3479         unsigned long delta;
3480         u32 rx_cfg_reg;
3481         int ret;
3482
3483         if (ap->state == ANEG_STATE_UNKNOWN) {
3484                 ap->rxconfig = 0;
3485                 ap->link_time = 0;
3486                 ap->cur_time = 0;
3487                 ap->ability_match_cfg = 0;
3488                 ap->ability_match_count = 0;
3489                 ap->ability_match = 0;
3490                 ap->idle_match = 0;
3491                 ap->ack_match = 0;
3492         }
3493         ap->cur_time++;
3494
3495         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3496                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3497
3498                 if (rx_cfg_reg != ap->ability_match_cfg) {
3499                         ap->ability_match_cfg = rx_cfg_reg;
3500                         ap->ability_match = 0;
3501                         ap->ability_match_count = 0;
3502                 } else {
3503                         if (++ap->ability_match_count > 1) {
3504                                 ap->ability_match = 1;
3505                                 ap->ability_match_cfg = rx_cfg_reg;
3506                         }
3507                 }
3508                 if (rx_cfg_reg & ANEG_CFG_ACK)
3509                         ap->ack_match = 1;
3510                 else
3511                         ap->ack_match = 0;
3512
3513                 ap->idle_match = 0;
3514         } else {
3515                 ap->idle_match = 1;
3516                 ap->ability_match_cfg = 0;
3517                 ap->ability_match_count = 0;
3518                 ap->ability_match = 0;
3519                 ap->ack_match = 0;
3520
3521                 rx_cfg_reg = 0;
3522         }
3523
3524         ap->rxconfig = rx_cfg_reg;
3525         ret = ANEG_OK;
3526
3527         switch (ap->state) {
3528         case ANEG_STATE_UNKNOWN:
3529                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3530                         ap->state = ANEG_STATE_AN_ENABLE;
3531
3532                 /* fallthru */
3533         case ANEG_STATE_AN_ENABLE:
3534                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3535                 if (ap->flags & MR_AN_ENABLE) {
3536                         ap->link_time = 0;
3537                         ap->cur_time = 0;
3538                         ap->ability_match_cfg = 0;
3539                         ap->ability_match_count = 0;
3540                         ap->ability_match = 0;
3541                         ap->idle_match = 0;
3542                         ap->ack_match = 0;
3543
3544                         ap->state = ANEG_STATE_RESTART_INIT;
3545                 } else {
3546                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3547                 }
3548                 break;
3549
3550         case ANEG_STATE_RESTART_INIT:
3551                 ap->link_time = ap->cur_time;
3552                 ap->flags &= ~(MR_NP_LOADED);
3553                 ap->txconfig = 0;
3554                 tw32(MAC_TX_AUTO_NEG, 0);
3555                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3556                 tw32_f(MAC_MODE, tp->mac_mode);
3557                 udelay(40);
3558
3559                 ret = ANEG_TIMER_ENAB;
3560                 ap->state = ANEG_STATE_RESTART;
3561
3562                 /* fallthru */
3563         case ANEG_STATE_RESTART:
3564                 delta = ap->cur_time - ap->link_time;
3565                 if (delta > ANEG_STATE_SETTLE_TIME)
3566                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3567                 else
3568                         ret = ANEG_TIMER_ENAB;
3569                 break;
3570
3571         case ANEG_STATE_DISABLE_LINK_OK:
3572                 ret = ANEG_DONE;
3573                 break;
3574
3575         case ANEG_STATE_ABILITY_DETECT_INIT:
3576                 ap->flags &= ~(MR_TOGGLE_TX);
3577                 ap->txconfig = ANEG_CFG_FD;
3578                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3579                 if (flowctrl & ADVERTISE_1000XPAUSE)
3580                         ap->txconfig |= ANEG_CFG_PS1;
3581                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3582                         ap->txconfig |= ANEG_CFG_PS2;
3583                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3584                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3585                 tw32_f(MAC_MODE, tp->mac_mode);
3586                 udelay(40);
3587
3588                 ap->state = ANEG_STATE_ABILITY_DETECT;
3589                 break;
3590
3591         case ANEG_STATE_ABILITY_DETECT:
3592                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3593                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3594                 break;
3595
3596         case ANEG_STATE_ACK_DETECT_INIT:
3597                 ap->txconfig |= ANEG_CFG_ACK;
3598                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3599                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3600                 tw32_f(MAC_MODE, tp->mac_mode);
3601                 udelay(40);
3602
3603                 ap->state = ANEG_STATE_ACK_DETECT;
3604
3605                 /* fallthru */
3606         case ANEG_STATE_ACK_DETECT:
3607                 if (ap->ack_match != 0) {
3608                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3609                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3610                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3611                         } else {
3612                                 ap->state = ANEG_STATE_AN_ENABLE;
3613                         }
3614                 } else if (ap->ability_match != 0 &&
3615                            ap->rxconfig == 0) {
3616                         ap->state = ANEG_STATE_AN_ENABLE;
3617                 }
3618                 break;
3619
3620         case ANEG_STATE_COMPLETE_ACK_INIT:
3621                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3622                         ret = ANEG_FAILED;
3623                         break;
3624                 }
3625                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3626                                MR_LP_ADV_HALF_DUPLEX |
3627                                MR_LP_ADV_SYM_PAUSE |
3628                                MR_LP_ADV_ASYM_PAUSE |
3629                                MR_LP_ADV_REMOTE_FAULT1 |
3630                                MR_LP_ADV_REMOTE_FAULT2 |
3631                                MR_LP_ADV_NEXT_PAGE |
3632                                MR_TOGGLE_RX |
3633                                MR_NP_RX);
3634                 if (ap->rxconfig & ANEG_CFG_FD)
3635                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3636                 if (ap->rxconfig & ANEG_CFG_HD)
3637                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3638                 if (ap->rxconfig & ANEG_CFG_PS1)
3639                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3640                 if (ap->rxconfig & ANEG_CFG_PS2)
3641                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3642                 if (ap->rxconfig & ANEG_CFG_RF1)
3643                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3644                 if (ap->rxconfig & ANEG_CFG_RF2)
3645                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3646                 if (ap->rxconfig & ANEG_CFG_NP)
3647                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3648
3649                 ap->link_time = ap->cur_time;
3650
3651                 ap->flags ^= (MR_TOGGLE_TX);
3652                 if (ap->rxconfig & 0x0008)
3653                         ap->flags |= MR_TOGGLE_RX;
3654                 if (ap->rxconfig & ANEG_CFG_NP)
3655                         ap->flags |= MR_NP_RX;
3656                 ap->flags |= MR_PAGE_RX;
3657
3658                 ap->state = ANEG_STATE_COMPLETE_ACK;
3659                 ret = ANEG_TIMER_ENAB;
3660                 break;
3661
3662         case ANEG_STATE_COMPLETE_ACK:
3663                 if (ap->ability_match != 0 &&
3664                     ap->rxconfig == 0) {
3665                         ap->state = ANEG_STATE_AN_ENABLE;
3666                         break;
3667                 }
3668                 delta = ap->cur_time - ap->link_time;
3669                 if (delta > ANEG_STATE_SETTLE_TIME) {
3670                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3671                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3672                         } else {
3673                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3674                                     !(ap->flags & MR_NP_RX)) {
3675                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3676                                 } else {
3677                                         ret = ANEG_FAILED;
3678                                 }
3679                         }
3680                 }
3681                 break;
3682
3683         case ANEG_STATE_IDLE_DETECT_INIT:
3684                 ap->link_time = ap->cur_time;
3685                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3686                 tw32_f(MAC_MODE, tp->mac_mode);
3687                 udelay(40);
3688
3689                 ap->state = ANEG_STATE_IDLE_DETECT;
3690                 ret = ANEG_TIMER_ENAB;
3691                 break;
3692
3693         case ANEG_STATE_IDLE_DETECT:
3694                 if (ap->ability_match != 0 &&
3695                     ap->rxconfig == 0) {
3696                         ap->state = ANEG_STATE_AN_ENABLE;
3697                         break;
3698                 }
3699                 delta = ap->cur_time - ap->link_time;
3700                 if (delta > ANEG_STATE_SETTLE_TIME) {
3701                         /* XXX another gem from the Broadcom driver :( */
3702                         ap->state = ANEG_STATE_LINK_OK;
3703                 }
3704                 break;
3705
3706         case ANEG_STATE_LINK_OK:
3707                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3708                 ret = ANEG_DONE;
3709                 break;
3710
3711         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3712                 /* ??? unimplemented */
3713                 break;
3714
3715         case ANEG_STATE_NEXT_PAGE_WAIT:
3716                 /* ??? unimplemented */
3717                 break;
3718
3719         default:
3720                 ret = ANEG_FAILED;
3721                 break;
3722         }
3723
3724         return ret;
3725 }
3726
3727 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3728 {
3729         int res = 0;
3730         struct tg3_fiber_aneginfo aninfo;
3731         int status = ANEG_FAILED;
3732         unsigned int tick;
3733         u32 tmp;
3734
3735         tw32_f(MAC_TX_AUTO_NEG, 0);
3736
3737         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3738         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3739         udelay(40);
3740
3741         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3742         udelay(40);
3743
3744         memset(&aninfo, 0, sizeof(aninfo));
3745         aninfo.flags |= MR_AN_ENABLE;
3746         aninfo.state = ANEG_STATE_UNKNOWN;
3747         aninfo.cur_time = 0;
3748         tick = 0;
3749         while (++tick < 195000) {
3750                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3751                 if (status == ANEG_DONE || status == ANEG_FAILED)
3752                         break;
3753
3754                 udelay(1);
3755         }
3756
3757         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3758         tw32_f(MAC_MODE, tp->mac_mode);
3759         udelay(40);
3760
3761         *txflags = aninfo.txconfig;
3762         *rxflags = aninfo.flags;
3763
3764         if (status == ANEG_DONE &&
3765             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3766                              MR_LP_ADV_FULL_DUPLEX)))
3767                 res = 1;
3768
3769         return res;
3770 }
3771
3772 static void tg3_init_bcm8002(struct tg3 *tp)
3773 {
3774         u32 mac_status = tr32(MAC_STATUS);
3775         int i;
3776
3777         /* Reset when initting first time or we have a link. */
3778         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3779             !(mac_status & MAC_STATUS_PCS_SYNCED))
3780                 return;
3781
3782         /* Set PLL lock range. */
3783         tg3_writephy(tp, 0x16, 0x8007);
3784
3785         /* SW reset */
3786         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3787
3788         /* Wait for reset to complete. */
3789         /* XXX schedule_timeout() ... */
3790         for (i = 0; i < 500; i++)
3791                 udelay(10);
3792
3793         /* Config mode; select PMA/Ch 1 regs. */
3794         tg3_writephy(tp, 0x10, 0x8411);
3795
3796         /* Enable auto-lock and comdet, select txclk for tx. */
3797         tg3_writephy(tp, 0x11, 0x0a10);
3798
3799         tg3_writephy(tp, 0x18, 0x00a0);
3800         tg3_writephy(tp, 0x16, 0x41ff);
3801
3802         /* Assert and deassert POR. */
3803         tg3_writephy(tp, 0x13, 0x0400);
3804         udelay(40);
3805         tg3_writephy(tp, 0x13, 0x0000);
3806
3807         tg3_writephy(tp, 0x11, 0x0a50);
3808         udelay(40);
3809         tg3_writephy(tp, 0x11, 0x0a10);
3810
3811         /* Wait for signal to stabilize */
3812         /* XXX schedule_timeout() ... */
3813         for (i = 0; i < 15000; i++)
3814                 udelay(10);
3815
3816         /* Deselect the channel register so we can read the PHYID
3817          * later.
3818          */
3819         tg3_writephy(tp, 0x10, 0x8011);
3820 }
3821
3822 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3823 {
3824         u16 flowctrl;
3825         u32 sg_dig_ctrl, sg_dig_status;
3826         u32 serdes_cfg, expected_sg_dig_ctrl;
3827         int workaround, port_a;
3828         int current_link_up;
3829
3830         serdes_cfg = 0;
3831         expected_sg_dig_ctrl = 0;
3832         workaround = 0;
3833         port_a = 1;
3834         current_link_up = 0;
3835
3836         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3837             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3838                 workaround = 1;
3839                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3840                         port_a = 0;
3841
3842                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3843                 /* preserve bits 20-23 for voltage regulator */
3844                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3845         }
3846
3847         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3848
3849         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3850                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3851                         if (workaround) {
3852                                 u32 val = serdes_cfg;
3853
3854                                 if (port_a)
3855                                         val |= 0xc010000;
3856                                 else
3857                                         val |= 0x4010000;
3858                                 tw32_f(MAC_SERDES_CFG, val);
3859                         }
3860
3861                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3862                 }
3863                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3864                         tg3_setup_flow_control(tp, 0, 0);
3865                         current_link_up = 1;
3866                 }
3867                 goto out;
3868         }
3869
3870         /* Want auto-negotiation.  */
3871         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3872
3873         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3874         if (flowctrl & ADVERTISE_1000XPAUSE)
3875                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3876         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3877                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3878
3879         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3880                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3881                     tp->serdes_counter &&
3882                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3883                                     MAC_STATUS_RCVD_CFG)) ==
3884                      MAC_STATUS_PCS_SYNCED)) {
3885                         tp->serdes_counter--;
3886                         current_link_up = 1;
3887                         goto out;
3888                 }
3889 restart_autoneg:
3890                 if (workaround)
3891                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3892                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3893                 udelay(5);
3894                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3895
3896                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3897                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3898         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3899                                  MAC_STATUS_SIGNAL_DET)) {
3900                 sg_dig_status = tr32(SG_DIG_STATUS);
3901                 mac_status = tr32(MAC_STATUS);
3902
3903                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3904                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3905                         u32 local_adv = 0, remote_adv = 0;
3906
3907                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3908                                 local_adv |= ADVERTISE_1000XPAUSE;
3909                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3910                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3911
3912                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3913                                 remote_adv |= LPA_1000XPAUSE;
3914                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3915                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3916
3917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3918                         current_link_up = 1;
3919                         tp->serdes_counter = 0;
3920                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3921                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3922                         if (tp->serdes_counter)
3923                                 tp->serdes_counter--;
3924                         else {
3925                                 if (workaround) {
3926                                         u32 val = serdes_cfg;
3927
3928                                         if (port_a)
3929                                                 val |= 0xc010000;
3930                                         else
3931                                                 val |= 0x4010000;
3932
3933                                         tw32_f(MAC_SERDES_CFG, val);
3934                                 }
3935
3936                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3937                                 udelay(40);
3938
3939                                 /* Link parallel detection - link is up */
3940                                 /* only if we have PCS_SYNC and not */
3941                                 /* receiving config code words */
3942                                 mac_status = tr32(MAC_STATUS);
3943                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3944                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3945                                         tg3_setup_flow_control(tp, 0, 0);
3946                                         current_link_up = 1;
3947                                         tp->phy_flags |=
3948                                                 TG3_PHYFLG_PARALLEL_DETECT;
3949                                         tp->serdes_counter =
3950                                                 SERDES_PARALLEL_DET_TIMEOUT;
3951                                 } else
3952                                         goto restart_autoneg;
3953                         }
3954                 }
3955         } else {
3956                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3957                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3958         }
3959
3960 out:
3961         return current_link_up;
3962 }
3963
3964 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3965 {
3966         int current_link_up = 0;
3967
3968         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3969                 goto out;
3970
3971         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3972                 u32 txflags, rxflags;
3973                 int i;
3974
3975                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3976                         u32 local_adv = 0, remote_adv = 0;
3977
3978                         if (txflags & ANEG_CFG_PS1)
3979                                 local_adv |= ADVERTISE_1000XPAUSE;
3980                         if (txflags & ANEG_CFG_PS2)
3981                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3982
3983                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3984                                 remote_adv |= LPA_1000XPAUSE;
3985                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3986                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3987
3988                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3989
3990                         current_link_up = 1;
3991                 }
3992                 for (i = 0; i < 30; i++) {
3993                         udelay(20);
3994                         tw32_f(MAC_STATUS,
3995                                (MAC_STATUS_SYNC_CHANGED |
3996                                 MAC_STATUS_CFG_CHANGED));
3997                         udelay(40);
3998                         if ((tr32(MAC_STATUS) &
3999                              (MAC_STATUS_SYNC_CHANGED |
4000                               MAC_STATUS_CFG_CHANGED)) == 0)
4001                                 break;
4002                 }
4003
4004                 mac_status = tr32(MAC_STATUS);
4005                 if (current_link_up == 0 &&
4006                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4007                     !(mac_status & MAC_STATUS_RCVD_CFG))
4008                         current_link_up = 1;
4009         } else {
4010                 tg3_setup_flow_control(tp, 0, 0);
4011
4012                 /* Forcing 1000FD link up. */
4013                 current_link_up = 1;
4014
4015                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4016                 udelay(40);
4017
4018                 tw32_f(MAC_MODE, tp->mac_mode);
4019                 udelay(40);
4020         }
4021
4022 out:
4023         return current_link_up;
4024 }
4025
4026 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4027 {
4028         u32 orig_pause_cfg;
4029         u16 orig_active_speed;
4030         u8 orig_active_duplex;
4031         u32 mac_status;
4032         int current_link_up;
4033         int i;
4034
4035         orig_pause_cfg = tp->link_config.active_flowctrl;
4036         orig_active_speed = tp->link_config.active_speed;
4037         orig_active_duplex = tp->link_config.active_duplex;
4038
4039         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4040             netif_carrier_ok(tp->dev) &&
4041             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4042                 mac_status = tr32(MAC_STATUS);
4043                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4044                                MAC_STATUS_SIGNAL_DET |
4045                                MAC_STATUS_CFG_CHANGED |
4046                                MAC_STATUS_RCVD_CFG);
4047                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4048                                    MAC_STATUS_SIGNAL_DET)) {
4049                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4050                                             MAC_STATUS_CFG_CHANGED));
4051                         return 0;
4052                 }
4053         }
4054
4055         tw32_f(MAC_TX_AUTO_NEG, 0);
4056
4057         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4058         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4059         tw32_f(MAC_MODE, tp->mac_mode);
4060         udelay(40);
4061
4062         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4063                 tg3_init_bcm8002(tp);
4064
4065         /* Enable link change event even when serdes polling.  */
4066         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4067         udelay(40);
4068
4069         current_link_up = 0;
4070         mac_status = tr32(MAC_STATUS);
4071
4072         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4073                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4074         else
4075                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4076
4077         tp->napi[0].hw_status->status =
4078                 (SD_STATUS_UPDATED |
4079                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4080
4081         for (i = 0; i < 100; i++) {
4082                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4083                                     MAC_STATUS_CFG_CHANGED));
4084                 udelay(5);
4085                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4086                                          MAC_STATUS_CFG_CHANGED |
4087                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4088                         break;
4089         }
4090
4091         mac_status = tr32(MAC_STATUS);
4092         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4093                 current_link_up = 0;
4094                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4095                     tp->serdes_counter == 0) {
4096                         tw32_f(MAC_MODE, (tp->mac_mode |
4097                                           MAC_MODE_SEND_CONFIGS));
4098                         udelay(1);
4099                         tw32_f(MAC_MODE, tp->mac_mode);
4100                 }
4101         }
4102
4103         if (current_link_up == 1) {
4104                 tp->link_config.active_speed = SPEED_1000;
4105                 tp->link_config.active_duplex = DUPLEX_FULL;
4106                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4107                                     LED_CTRL_LNKLED_OVERRIDE |
4108                                     LED_CTRL_1000MBPS_ON));
4109         } else {
4110                 tp->link_config.active_speed = SPEED_INVALID;
4111                 tp->link_config.active_duplex = DUPLEX_INVALID;
4112                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4113                                     LED_CTRL_LNKLED_OVERRIDE |
4114                                     LED_CTRL_TRAFFIC_OVERRIDE));
4115         }
4116
4117         if (current_link_up != netif_carrier_ok(tp->dev)) {
4118                 if (current_link_up)
4119                         netif_carrier_on(tp->dev);
4120                 else
4121                         netif_carrier_off(tp->dev);
4122                 tg3_link_report(tp);
4123         } else {
4124                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4125                 if (orig_pause_cfg != now_pause_cfg ||
4126                     orig_active_speed != tp->link_config.active_speed ||
4127                     orig_active_duplex != tp->link_config.active_duplex)
4128                         tg3_link_report(tp);
4129         }
4130
4131         return 0;
4132 }
4133
4134 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4135 {
4136         int current_link_up, err = 0;
4137         u32 bmsr, bmcr;
4138         u16 current_speed;
4139         u8 current_duplex;
4140         u32 local_adv, remote_adv;
4141
4142         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4143         tw32_f(MAC_MODE, tp->mac_mode);
4144         udelay(40);
4145
4146         tw32(MAC_EVENT, 0);
4147
4148         tw32_f(MAC_STATUS,
4149              (MAC_STATUS_SYNC_CHANGED |
4150               MAC_STATUS_CFG_CHANGED |
4151               MAC_STATUS_MI_COMPLETION |
4152               MAC_STATUS_LNKSTATE_CHANGED));
4153         udelay(40);
4154
4155         if (force_reset)
4156                 tg3_phy_reset(tp);
4157
4158         current_link_up = 0;
4159         current_speed = SPEED_INVALID;
4160         current_duplex = DUPLEX_INVALID;
4161
4162         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4163         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4165                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4166                         bmsr |= BMSR_LSTATUS;
4167                 else
4168                         bmsr &= ~BMSR_LSTATUS;
4169         }
4170
4171         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4172
4173         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4174             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4175                 /* do nothing, just check for link up at the end */
4176         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4177                 u32 adv, new_adv;
4178
4179                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4180                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4181                                   ADVERTISE_1000XPAUSE |
4182                                   ADVERTISE_1000XPSE_ASYM |
4183                                   ADVERTISE_SLCT);
4184
4185                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4186
4187                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4188                         new_adv |= ADVERTISE_1000XHALF;
4189                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4190                         new_adv |= ADVERTISE_1000XFULL;
4191
4192                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4193                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4194                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4195                         tg3_writephy(tp, MII_BMCR, bmcr);
4196
4197                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4198                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4199                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4200
4201                         return err;
4202                 }
4203         } else {
4204                 u32 new_bmcr;
4205
4206                 bmcr &= ~BMCR_SPEED1000;
4207                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4208
4209                 if (tp->link_config.duplex == DUPLEX_FULL)
4210                         new_bmcr |= BMCR_FULLDPLX;
4211
4212                 if (new_bmcr != bmcr) {
4213                         /* BMCR_SPEED1000 is a reserved bit that needs
4214                          * to be set on write.
4215                          */
4216                         new_bmcr |= BMCR_SPEED1000;
4217
4218                         /* Force a linkdown */
4219                         if (netif_carrier_ok(tp->dev)) {
4220                                 u32 adv;
4221
4222                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4223                                 adv &= ~(ADVERTISE_1000XFULL |
4224                                          ADVERTISE_1000XHALF |
4225                                          ADVERTISE_SLCT);
4226                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4227                                 tg3_writephy(tp, MII_BMCR, bmcr |
4228                                                            BMCR_ANRESTART |
4229                                                            BMCR_ANENABLE);
4230                                 udelay(10);
4231                                 netif_carrier_off(tp->dev);
4232                         }
4233                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4234                         bmcr = new_bmcr;
4235                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4236                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4237                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4238                             ASIC_REV_5714) {
4239                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4240                                         bmsr |= BMSR_LSTATUS;
4241                                 else
4242                                         bmsr &= ~BMSR_LSTATUS;
4243                         }
4244                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4245                 }
4246         }
4247
4248         if (bmsr & BMSR_LSTATUS) {
4249                 current_speed = SPEED_1000;
4250                 current_link_up = 1;
4251                 if (bmcr & BMCR_FULLDPLX)
4252                         current_duplex = DUPLEX_FULL;
4253                 else
4254                         current_duplex = DUPLEX_HALF;
4255
4256                 local_adv = 0;
4257                 remote_adv = 0;
4258
4259                 if (bmcr & BMCR_ANENABLE) {
4260                         u32 common;
4261
4262                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4263                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4264                         common = local_adv & remote_adv;
4265                         if (common & (ADVERTISE_1000XHALF |
4266                                       ADVERTISE_1000XFULL)) {
4267                                 if (common & ADVERTISE_1000XFULL)
4268                                         current_duplex = DUPLEX_FULL;
4269                                 else
4270                                         current_duplex = DUPLEX_HALF;
4271                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4272                                 /* Link is up via parallel detect */
4273                         } else {
4274                                 current_link_up = 0;
4275                         }
4276                 }
4277         }
4278
4279         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4280                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4281
4282         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4283         if (tp->link_config.active_duplex == DUPLEX_HALF)
4284                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4285
4286         tw32_f(MAC_MODE, tp->mac_mode);
4287         udelay(40);
4288
4289         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4290
4291         tp->link_config.active_speed = current_speed;
4292         tp->link_config.active_duplex = current_duplex;
4293
4294         if (current_link_up != netif_carrier_ok(tp->dev)) {
4295                 if (current_link_up)
4296                         netif_carrier_on(tp->dev);
4297                 else {
4298                         netif_carrier_off(tp->dev);
4299                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4300                 }
4301                 tg3_link_report(tp);
4302         }
4303         return err;
4304 }
4305
4306 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4307 {
4308         if (tp->serdes_counter) {
4309                 /* Give autoneg time to complete. */
4310                 tp->serdes_counter--;
4311                 return;
4312         }
4313
4314         if (!netif_carrier_ok(tp->dev) &&
4315             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4316                 u32 bmcr;
4317
4318                 tg3_readphy(tp, MII_BMCR, &bmcr);
4319                 if (bmcr & BMCR_ANENABLE) {
4320                         u32 phy1, phy2;
4321
4322                         /* Select shadow register 0x1f */
4323                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4324                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4325
4326                         /* Select expansion interrupt status register */
4327                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4328                                          MII_TG3_DSP_EXP1_INT_STAT);
4329                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4330                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4331
4332                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4333                                 /* We have signal detect and not receiving
4334                                  * config code words, link is up by parallel
4335                                  * detection.
4336                                  */
4337
4338                                 bmcr &= ~BMCR_ANENABLE;
4339                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4340                                 tg3_writephy(tp, MII_BMCR, bmcr);
4341                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4342                         }
4343                 }
4344         } else if (netif_carrier_ok(tp->dev) &&
4345                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4346                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4347                 u32 phy2;
4348
4349                 /* Select expansion interrupt status register */
4350                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4351                                  MII_TG3_DSP_EXP1_INT_STAT);
4352                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4353                 if (phy2 & 0x20) {
4354                         u32 bmcr;
4355
4356                         /* Config code words received, turn on autoneg. */
4357                         tg3_readphy(tp, MII_BMCR, &bmcr);
4358                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4359
4360                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4361
4362                 }
4363         }
4364 }
4365
4366 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4367 {
4368         int err;
4369
4370         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4371                 err = tg3_setup_fiber_phy(tp, force_reset);
4372         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4373                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4374         else
4375                 err = tg3_setup_copper_phy(tp, force_reset);
4376
4377         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4378                 u32 val, scale;
4379
4380                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4381                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4382                         scale = 65;
4383                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4384                         scale = 6;
4385                 else
4386                         scale = 12;
4387
4388                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4389                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4390                 tw32(GRC_MISC_CFG, val);
4391         }
4392
4393         if (tp->link_config.active_speed == SPEED_1000 &&
4394             tp->link_config.active_duplex == DUPLEX_HALF)
4395                 tw32(MAC_TX_LENGTHS,
4396                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4397                       (6 << TX_LENGTHS_IPG_SHIFT) |
4398                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4399         else
4400                 tw32(MAC_TX_LENGTHS,
4401                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4402                       (6 << TX_LENGTHS_IPG_SHIFT) |
4403                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4404
4405         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4406                 if (netif_carrier_ok(tp->dev)) {
4407                         tw32(HOSTCC_STAT_COAL_TICKS,
4408                              tp->coal.stats_block_coalesce_usecs);
4409                 } else {
4410                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4411                 }
4412         }
4413
4414         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4415                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4416                 if (!netif_carrier_ok(tp->dev))
4417                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4418                               tp->pwrmgmt_thresh;
4419                 else
4420                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4421                 tw32(PCIE_PWR_MGMT_THRESH, val);
4422         }
4423
4424         return err;
4425 }
4426
4427 static inline int tg3_irq_sync(struct tg3 *tp)
4428 {
4429         return tp->irq_sync;
4430 }
4431
4432 /* This is called whenever we suspect that the system chipset is re-
4433  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4434  * is bogus tx completions. We try to recover by setting the
4435  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4436  * in the workqueue.
4437  */
4438 static void tg3_tx_recover(struct tg3 *tp)
4439 {
4440         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4441                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4442
4443         netdev_warn(tp->dev,
4444                     "The system may be re-ordering memory-mapped I/O "
4445                     "cycles to the network device, attempting to recover. "
4446                     "Please report the problem to the driver maintainer "
4447                     "and include system chipset information.\n");
4448
4449         spin_lock(&tp->lock);
4450         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4451         spin_unlock(&tp->lock);
4452 }
4453
4454 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4455 {
4456         /* Tell compiler to fetch tx indices from memory. */
4457         barrier();
4458         return tnapi->tx_pending -
4459                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4460 }
4461
4462 /* Tigon3 never reports partial packet sends.  So we do not
4463  * need special logic to handle SKBs that have not had all
4464  * of their frags sent yet, like SunGEM does.
4465  */
4466 static void tg3_tx(struct tg3_napi *tnapi)
4467 {
4468         struct tg3 *tp = tnapi->tp;
4469         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4470         u32 sw_idx = tnapi->tx_cons;
4471         struct netdev_queue *txq;
4472         int index = tnapi - tp->napi;
4473
4474         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4475                 index--;
4476
4477         txq = netdev_get_tx_queue(tp->dev, index);
4478
4479         while (sw_idx != hw_idx) {
4480                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4481                 struct sk_buff *skb = ri->skb;
4482                 int i, tx_bug = 0;
4483
4484                 if (unlikely(skb == NULL)) {
4485                         tg3_tx_recover(tp);
4486                         return;
4487                 }
4488
4489                 pci_unmap_single(tp->pdev,
4490                                  dma_unmap_addr(ri, mapping),
4491                                  skb_headlen(skb),
4492                                  PCI_DMA_TODEVICE);
4493
4494                 ri->skb = NULL;
4495
4496                 sw_idx = NEXT_TX(sw_idx);
4497
4498                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4499                         ri = &tnapi->tx_buffers[sw_idx];
4500                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4501                                 tx_bug = 1;
4502
4503                         pci_unmap_page(tp->pdev,
4504                                        dma_unmap_addr(ri, mapping),
4505                                        skb_shinfo(skb)->frags[i].size,
4506                                        PCI_DMA_TODEVICE);
4507                         sw_idx = NEXT_TX(sw_idx);
4508                 }
4509
4510                 dev_kfree_skb(skb);
4511
4512                 if (unlikely(tx_bug)) {
4513                         tg3_tx_recover(tp);
4514                         return;
4515                 }
4516         }
4517
4518         tnapi->tx_cons = sw_idx;
4519
4520         /* Need to make the tx_cons update visible to tg3_start_xmit()
4521          * before checking for netif_queue_stopped().  Without the
4522          * memory barrier, there is a small possibility that tg3_start_xmit()
4523          * will miss it and cause the queue to be stopped forever.
4524          */
4525         smp_mb();
4526
4527         if (unlikely(netif_tx_queue_stopped(txq) &&
4528                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4529                 __netif_tx_lock(txq, smp_processor_id());
4530                 if (netif_tx_queue_stopped(txq) &&
4531                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4532                         netif_tx_wake_queue(txq);
4533                 __netif_tx_unlock(txq);
4534         }
4535 }
4536
4537 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4538 {
4539         if (!ri->skb)
4540                 return;
4541
4542         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4543                          map_sz, PCI_DMA_FROMDEVICE);
4544         dev_kfree_skb_any(ri->skb);
4545         ri->skb = NULL;
4546 }
4547
4548 /* Returns size of skb allocated or < 0 on error.
4549  *
4550  * We only need to fill in the address because the other members
4551  * of the RX descriptor are invariant, see tg3_init_rings.
4552  *
4553  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4554  * posting buffers we only dirty the first cache line of the RX
4555  * descriptor (containing the address).  Whereas for the RX status
4556  * buffers the cpu only reads the last cacheline of the RX descriptor
4557  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4558  */
4559 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4560                             u32 opaque_key, u32 dest_idx_unmasked)
4561 {
4562         struct tg3_rx_buffer_desc *desc;
4563         struct ring_info *map;
4564         struct sk_buff *skb;
4565         dma_addr_t mapping;
4566         int skb_size, dest_idx;
4567
4568         switch (opaque_key) {
4569         case RXD_OPAQUE_RING_STD:
4570                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4571                 desc = &tpr->rx_std[dest_idx];
4572                 map = &tpr->rx_std_buffers[dest_idx];
4573                 skb_size = tp->rx_pkt_map_sz;
4574                 break;
4575
4576         case RXD_OPAQUE_RING_JUMBO:
4577                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4578                 desc = &tpr->rx_jmb[dest_idx].std;
4579                 map = &tpr->rx_jmb_buffers[dest_idx];
4580                 skb_size = TG3_RX_JMB_MAP_SZ;
4581                 break;
4582
4583         default:
4584                 return -EINVAL;
4585         }
4586
4587         /* Do not overwrite any of the map or rp information
4588          * until we are sure we can commit to a new buffer.
4589          *
4590          * Callers depend upon this behavior and assume that
4591          * we leave everything unchanged if we fail.
4592          */
4593         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4594         if (skb == NULL)
4595                 return -ENOMEM;
4596
4597         skb_reserve(skb, tp->rx_offset);
4598
4599         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4600                                  PCI_DMA_FROMDEVICE);
4601         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4602                 dev_kfree_skb(skb);
4603                 return -EIO;
4604         }
4605
4606         map->skb = skb;
4607         dma_unmap_addr_set(map, mapping, mapping);
4608
4609         desc->addr_hi = ((u64)mapping >> 32);
4610         desc->addr_lo = ((u64)mapping & 0xffffffff);
4611
4612         return skb_size;
4613 }
4614
4615 /* We only need to move over in the address because the other
4616  * members of the RX descriptor are invariant.  See notes above
4617  * tg3_alloc_rx_skb for full details.
4618  */
4619 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4620                            struct tg3_rx_prodring_set *dpr,
4621                            u32 opaque_key, int src_idx,
4622                            u32 dest_idx_unmasked)
4623 {
4624         struct tg3 *tp = tnapi->tp;
4625         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4626         struct ring_info *src_map, *dest_map;
4627         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4628         int dest_idx;
4629
4630         switch (opaque_key) {
4631         case RXD_OPAQUE_RING_STD:
4632                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4633                 dest_desc = &dpr->rx_std[dest_idx];
4634                 dest_map = &dpr->rx_std_buffers[dest_idx];
4635                 src_desc = &spr->rx_std[src_idx];
4636                 src_map = &spr->rx_std_buffers[src_idx];
4637                 break;
4638
4639         case RXD_OPAQUE_RING_JUMBO:
4640                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4641                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4642                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4643                 src_desc = &spr->rx_jmb[src_idx].std;
4644                 src_map = &spr->rx_jmb_buffers[src_idx];
4645                 break;
4646
4647         default:
4648                 return;
4649         }
4650
4651         dest_map->skb = src_map->skb;
4652         dma_unmap_addr_set(dest_map, mapping,
4653                            dma_unmap_addr(src_map, mapping));
4654         dest_desc->addr_hi = src_desc->addr_hi;
4655         dest_desc->addr_lo = src_desc->addr_lo;
4656
4657         /* Ensure that the update to the skb happens after the physical
4658          * addresses have been transferred to the new BD location.
4659          */
4660         smp_wmb();
4661
4662         src_map->skb = NULL;
4663 }
4664
4665 /* The RX ring scheme is composed of multiple rings which post fresh
4666  * buffers to the chip, and one special ring the chip uses to report
4667  * status back to the host.
4668  *
4669  * The special ring reports the status of received packets to the
4670  * host.  The chip does not write into the original descriptor the
4671  * RX buffer was obtained from.  The chip simply takes the original
4672  * descriptor as provided by the host, updates the status and length
4673  * field, then writes this into the next status ring entry.
4674  *
4675  * Each ring the host uses to post buffers to the chip is described
4676  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4677  * it is first placed into the on-chip ram.  When the packet's length
4678  * is known, it walks down the TG3_BDINFO entries to select the ring.
4679  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4680  * which is within the range of the new packet's length is chosen.
4681  *
4682  * The "separate ring for rx status" scheme may sound queer, but it makes
4683  * sense from a cache coherency perspective.  If only the host writes
4684  * to the buffer post rings, and only the chip writes to the rx status
4685  * rings, then cache lines never move beyond shared-modified state.
4686  * If both the host and chip were to write into the same ring, cache line
4687  * eviction could occur since both entities want it in an exclusive state.
4688  */
4689 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4690 {
4691         struct tg3 *tp = tnapi->tp;
4692         u32 work_mask, rx_std_posted = 0;
4693         u32 std_prod_idx, jmb_prod_idx;
4694         u32 sw_idx = tnapi->rx_rcb_ptr;
4695         u16 hw_idx;
4696         int received;
4697         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4698
4699         hw_idx = *(tnapi->rx_rcb_prod_idx);
4700         /*
4701          * We need to order the read of hw_idx and the read of
4702          * the opaque cookie.
4703          */
4704         rmb();
4705         work_mask = 0;
4706         received = 0;
4707         std_prod_idx = tpr->rx_std_prod_idx;
4708         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4709         while (sw_idx != hw_idx && budget > 0) {
4710                 struct ring_info *ri;
4711                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4712                 unsigned int len;
4713                 struct sk_buff *skb;
4714                 dma_addr_t dma_addr;
4715                 u32 opaque_key, desc_idx, *post_ptr;
4716
4717                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4718                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4719                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4720                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4721                         dma_addr = dma_unmap_addr(ri, mapping);
4722                         skb = ri->skb;
4723                         post_ptr = &std_prod_idx;
4724                         rx_std_posted++;
4725                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4726                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4727                         dma_addr = dma_unmap_addr(ri, mapping);
4728                         skb = ri->skb;
4729                         post_ptr = &jmb_prod_idx;
4730                 } else
4731                         goto next_pkt_nopost;
4732
4733                 work_mask |= opaque_key;
4734
4735                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4736                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4737                 drop_it:
4738                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4739                                        desc_idx, *post_ptr);
4740                 drop_it_no_recycle:
4741                         /* Other statistics kept track of by card. */
4742                         tp->rx_dropped++;
4743                         goto next_pkt;
4744                 }
4745
4746                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4747                       ETH_FCS_LEN;
4748
4749                 if (len > TG3_RX_COPY_THRESH(tp)) {
4750                         int skb_size;
4751
4752                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4753                                                     *post_ptr);
4754                         if (skb_size < 0)
4755                                 goto drop_it;
4756
4757                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4758                                          PCI_DMA_FROMDEVICE);
4759
4760                         /* Ensure that the update to the skb happens
4761                          * after the usage of the old DMA mapping.
4762                          */
4763                         smp_wmb();
4764
4765                         ri->skb = NULL;
4766
4767                         skb_put(skb, len);
4768                 } else {
4769                         struct sk_buff *copy_skb;
4770
4771                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4772                                        desc_idx, *post_ptr);
4773
4774                         copy_skb = netdev_alloc_skb(tp->dev, len +
4775                                                     TG3_RAW_IP_ALIGN);
4776                         if (copy_skb == NULL)
4777                                 goto drop_it_no_recycle;
4778
4779                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4780                         skb_put(copy_skb, len);
4781                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4782                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4783                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4784
4785                         /* We'll reuse the original ring buffer. */
4786                         skb = copy_skb;
4787                 }
4788
4789                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4790                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4791                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4792                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4793                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4794                 else
4795                         skb_checksum_none_assert(skb);
4796
4797                 skb->protocol = eth_type_trans(skb, tp->dev);
4798
4799                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4800                     skb->protocol != htons(ETH_P_8021Q)) {
4801                         dev_kfree_skb(skb);
4802                         goto drop_it_no_recycle;
4803                 }
4804
4805                 if (desc->type_flags & RXD_FLAG_VLAN &&
4806                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4807                         __vlan_hwaccel_put_tag(skb,
4808                                                desc->err_vlan & RXD_VLAN_MASK);
4809
4810                 napi_gro_receive(&tnapi->napi, skb);
4811
4812                 received++;
4813                 budget--;
4814
4815 next_pkt:
4816                 (*post_ptr)++;
4817
4818                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4819                         tpr->rx_std_prod_idx = std_prod_idx &
4820                                                tp->rx_std_ring_mask;
4821                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4822                                      tpr->rx_std_prod_idx);
4823                         work_mask &= ~RXD_OPAQUE_RING_STD;
4824                         rx_std_posted = 0;
4825                 }
4826 next_pkt_nopost:
4827                 sw_idx++;
4828                 sw_idx &= tp->rx_ret_ring_mask;
4829
4830                 /* Refresh hw_idx to see if there is new work */
4831                 if (sw_idx == hw_idx) {
4832                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4833                         rmb();
4834                 }
4835         }
4836
4837         /* ACK the status ring. */
4838         tnapi->rx_rcb_ptr = sw_idx;
4839         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4840
4841         /* Refill RX ring(s). */
4842         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4843                 if (work_mask & RXD_OPAQUE_RING_STD) {
4844                         tpr->rx_std_prod_idx = std_prod_idx &
4845                                                tp->rx_std_ring_mask;
4846                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4847                                      tpr->rx_std_prod_idx);
4848                 }
4849                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4850                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4851                                                tp->rx_jmb_ring_mask;
4852                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4853                                      tpr->rx_jmb_prod_idx);
4854                 }
4855                 mmiowb();
4856         } else if (work_mask) {
4857                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4858                  * updated before the producer indices can be updated.
4859                  */
4860                 smp_wmb();
4861
4862                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4863                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4864
4865                 if (tnapi != &tp->napi[1])
4866                         napi_schedule(&tp->napi[1].napi);
4867         }
4868
4869         return received;
4870 }
4871
4872 static void tg3_poll_link(struct tg3 *tp)
4873 {
4874         /* handle link change and other phy events */
4875         if (!(tp->tg3_flags &
4876               (TG3_FLAG_USE_LINKCHG_REG |
4877                TG3_FLAG_POLL_SERDES))) {
4878                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4879
4880                 if (sblk->status & SD_STATUS_LINK_CHG) {
4881                         sblk->status = SD_STATUS_UPDATED |
4882                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4883                         spin_lock(&tp->lock);
4884                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4885                                 tw32_f(MAC_STATUS,
4886                                      (MAC_STATUS_SYNC_CHANGED |
4887                                       MAC_STATUS_CFG_CHANGED |
4888                                       MAC_STATUS_MI_COMPLETION |
4889                                       MAC_STATUS_LNKSTATE_CHANGED));
4890                                 udelay(40);
4891                         } else
4892                                 tg3_setup_phy(tp, 0);
4893                         spin_unlock(&tp->lock);
4894                 }
4895         }
4896 }
4897
4898 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4899                                 struct tg3_rx_prodring_set *dpr,
4900                                 struct tg3_rx_prodring_set *spr)
4901 {
4902         u32 si, di, cpycnt, src_prod_idx;
4903         int i, err = 0;
4904
4905         while (1) {
4906                 src_prod_idx = spr->rx_std_prod_idx;
4907
4908                 /* Make sure updates to the rx_std_buffers[] entries and the
4909                  * standard producer index are seen in the correct order.
4910                  */
4911                 smp_rmb();
4912
4913                 if (spr->rx_std_cons_idx == src_prod_idx)
4914                         break;
4915
4916                 if (spr->rx_std_cons_idx < src_prod_idx)
4917                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4918                 else
4919                         cpycnt = tp->rx_std_ring_mask + 1 -
4920                                  spr->rx_std_cons_idx;
4921
4922                 cpycnt = min(cpycnt,
4923                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4924
4925                 si = spr->rx_std_cons_idx;
4926                 di = dpr->rx_std_prod_idx;
4927
4928                 for (i = di; i < di + cpycnt; i++) {
4929                         if (dpr->rx_std_buffers[i].skb) {
4930                                 cpycnt = i - di;
4931                                 err = -ENOSPC;
4932                                 break;
4933                         }
4934                 }
4935
4936                 if (!cpycnt)
4937                         break;
4938
4939                 /* Ensure that updates to the rx_std_buffers ring and the
4940                  * shadowed hardware producer ring from tg3_recycle_skb() are
4941                  * ordered correctly WRT the skb check above.
4942                  */
4943                 smp_rmb();
4944
4945                 memcpy(&dpr->rx_std_buffers[di],
4946                        &spr->rx_std_buffers[si],
4947                        cpycnt * sizeof(struct ring_info));
4948
4949                 for (i = 0; i < cpycnt; i++, di++, si++) {
4950                         struct tg3_rx_buffer_desc *sbd, *dbd;
4951                         sbd = &spr->rx_std[si];
4952                         dbd = &dpr->rx_std[di];
4953                         dbd->addr_hi = sbd->addr_hi;
4954                         dbd->addr_lo = sbd->addr_lo;
4955                 }
4956
4957                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4958                                        tp->rx_std_ring_mask;
4959                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4960                                        tp->rx_std_ring_mask;
4961         }
4962
4963         while (1) {
4964                 src_prod_idx = spr->rx_jmb_prod_idx;
4965
4966                 /* Make sure updates to the rx_jmb_buffers[] entries and
4967                  * the jumbo producer index are seen in the correct order.
4968                  */
4969                 smp_rmb();
4970
4971                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4972                         break;
4973
4974                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4975                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4976                 else
4977                         cpycnt = tp->rx_jmb_ring_mask + 1 -
4978                                  spr->rx_jmb_cons_idx;
4979
4980                 cpycnt = min(cpycnt,
4981                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
4982
4983                 si = spr->rx_jmb_cons_idx;
4984                 di = dpr->rx_jmb_prod_idx;
4985
4986                 for (i = di; i < di + cpycnt; i++) {
4987                         if (dpr->rx_jmb_buffers[i].skb) {
4988                                 cpycnt = i - di;
4989                                 err = -ENOSPC;
4990                                 break;
4991                         }
4992                 }
4993
4994                 if (!cpycnt)
4995                         break;
4996
4997                 /* Ensure that updates to the rx_jmb_buffers ring and the
4998                  * shadowed hardware producer ring from tg3_recycle_skb() are
4999                  * ordered correctly WRT the skb check above.
5000                  */
5001                 smp_rmb();
5002
5003                 memcpy(&dpr->rx_jmb_buffers[di],
5004                        &spr->rx_jmb_buffers[si],
5005                        cpycnt * sizeof(struct ring_info));
5006
5007                 for (i = 0; i < cpycnt; i++, di++, si++) {
5008                         struct tg3_rx_buffer_desc *sbd, *dbd;
5009                         sbd = &spr->rx_jmb[si].std;
5010                         dbd = &dpr->rx_jmb[di].std;
5011                         dbd->addr_hi = sbd->addr_hi;
5012                         dbd->addr_lo = sbd->addr_lo;
5013                 }
5014
5015                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5016                                        tp->rx_jmb_ring_mask;
5017                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5018                                        tp->rx_jmb_ring_mask;
5019         }
5020
5021         return err;
5022 }
5023
5024 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5025 {
5026         struct tg3 *tp = tnapi->tp;
5027
5028         /* run TX completion thread */
5029         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5030                 tg3_tx(tnapi);
5031                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5032                         return work_done;
5033         }
5034
5035         /* run RX thread, within the bounds set by NAPI.
5036          * All RX "locking" is done by ensuring outside
5037          * code synchronizes with tg3->napi.poll()
5038          */
5039         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5040                 work_done += tg3_rx(tnapi, budget - work_done);
5041
5042         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5043                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5044                 int i, err = 0;
5045                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5046                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5047
5048                 for (i = 1; i < tp->irq_cnt; i++)
5049                         err |= tg3_rx_prodring_xfer(tp, dpr,
5050                                                     &tp->napi[i].prodring);
5051
5052                 wmb();
5053
5054                 if (std_prod_idx != dpr->rx_std_prod_idx)
5055                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5056                                      dpr->rx_std_prod_idx);
5057
5058                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5059                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5060                                      dpr->rx_jmb_prod_idx);
5061
5062                 mmiowb();
5063
5064                 if (err)
5065                         tw32_f(HOSTCC_MODE, tp->coal_now);
5066         }
5067
5068         return work_done;
5069 }
5070
5071 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5072 {
5073         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5074         struct tg3 *tp = tnapi->tp;
5075         int work_done = 0;
5076         struct tg3_hw_status *sblk = tnapi->hw_status;
5077
5078         while (1) {
5079                 work_done = tg3_poll_work(tnapi, work_done, budget);
5080
5081                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5082                         goto tx_recovery;
5083
5084                 if (unlikely(work_done >= budget))
5085                         break;
5086
5087                 /* tp->last_tag is used in tg3_int_reenable() below
5088                  * to tell the hw how much work has been processed,
5089                  * so we must read it before checking for more work.
5090                  */
5091                 tnapi->last_tag = sblk->status_tag;
5092                 tnapi->last_irq_tag = tnapi->last_tag;
5093                 rmb();
5094
5095                 /* check for RX/TX work to do */
5096                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5097                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5098                         napi_complete(napi);
5099                         /* Reenable interrupts. */
5100                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5101                         mmiowb();
5102                         break;
5103                 }
5104         }
5105
5106         return work_done;
5107
5108 tx_recovery:
5109         /* work_done is guaranteed to be less than budget. */
5110         napi_complete(napi);
5111         schedule_work(&tp->reset_task);
5112         return work_done;
5113 }
5114
5115 static int tg3_poll(struct napi_struct *napi, int budget)
5116 {
5117         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5118         struct tg3 *tp = tnapi->tp;
5119         int work_done = 0;
5120         struct tg3_hw_status *sblk = tnapi->hw_status;
5121
5122         while (1) {
5123                 tg3_poll_link(tp);
5124
5125                 work_done = tg3_poll_work(tnapi, work_done, budget);
5126
5127                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5128                         goto tx_recovery;
5129
5130                 if (unlikely(work_done >= budget))
5131                         break;
5132
5133                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5134                         /* tp->last_tag is used in tg3_int_reenable() below
5135                          * to tell the hw how much work has been processed,
5136                          * so we must read it before checking for more work.
5137                          */
5138                         tnapi->last_tag = sblk->status_tag;
5139                         tnapi->last_irq_tag = tnapi->last_tag;
5140                         rmb();
5141                 } else
5142                         sblk->status &= ~SD_STATUS_UPDATED;
5143
5144                 if (likely(!tg3_has_work(tnapi))) {
5145                         napi_complete(napi);
5146                         tg3_int_reenable(tnapi);
5147                         break;
5148                 }
5149         }
5150
5151         return work_done;
5152
5153 tx_recovery:
5154         /* work_done is guaranteed to be less than budget. */
5155         napi_complete(napi);
5156         schedule_work(&tp->reset_task);
5157         return work_done;
5158 }
5159
5160 static void tg3_napi_disable(struct tg3 *tp)
5161 {
5162         int i;
5163
5164         for (i = tp->irq_cnt - 1; i >= 0; i--)
5165                 napi_disable(&tp->napi[i].napi);
5166 }
5167
5168 static void tg3_napi_enable(struct tg3 *tp)
5169 {
5170         int i;
5171
5172         for (i = 0; i < tp->irq_cnt; i++)
5173                 napi_enable(&tp->napi[i].napi);
5174 }
5175
5176 static void tg3_napi_init(struct tg3 *tp)
5177 {
5178         int i;
5179
5180         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5181         for (i = 1; i < tp->irq_cnt; i++)
5182                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5183 }
5184
5185 static void tg3_napi_fini(struct tg3 *tp)
5186 {
5187         int i;
5188
5189         for (i = 0; i < tp->irq_cnt; i++)
5190                 netif_napi_del(&tp->napi[i].napi);
5191 }
5192
5193 static inline void tg3_netif_stop(struct tg3 *tp)
5194 {
5195         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5196         tg3_napi_disable(tp);
5197         netif_tx_disable(tp->dev);
5198 }
5199
5200 static inline void tg3_netif_start(struct tg3 *tp)
5201 {
5202         /* NOTE: unconditional netif_tx_wake_all_queues is only
5203          * appropriate so long as all callers are assured to
5204          * have free tx slots (such as after tg3_init_hw)
5205          */
5206         netif_tx_wake_all_queues(tp->dev);
5207
5208         tg3_napi_enable(tp);
5209         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5210         tg3_enable_ints(tp);
5211 }
5212
5213 static void tg3_irq_quiesce(struct tg3 *tp)
5214 {
5215         int i;
5216
5217         BUG_ON(tp->irq_sync);
5218
5219         tp->irq_sync = 1;
5220         smp_mb();
5221
5222         for (i = 0; i < tp->irq_cnt; i++)
5223                 synchronize_irq(tp->napi[i].irq_vec);
5224 }
5225
5226 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5227  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5228  * with as well.  Most of the time, this is not necessary except when
5229  * shutting down the device.
5230  */
5231 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5232 {
5233         spin_lock_bh(&tp->lock);
5234         if (irq_sync)
5235                 tg3_irq_quiesce(tp);
5236 }
5237
5238 static inline void tg3_full_unlock(struct tg3 *tp)
5239 {
5240         spin_unlock_bh(&tp->lock);
5241 }
5242
5243 /* One-shot MSI handler - Chip automatically disables interrupt
5244  * after sending MSI so driver doesn't have to do it.
5245  */
5246 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5247 {
5248         struct tg3_napi *tnapi = dev_id;
5249         struct tg3 *tp = tnapi->tp;
5250
5251         prefetch(tnapi->hw_status);
5252         if (tnapi->rx_rcb)
5253                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5254
5255         if (likely(!tg3_irq_sync(tp)))
5256                 napi_schedule(&tnapi->napi);
5257
5258         return IRQ_HANDLED;
5259 }
5260
5261 /* MSI ISR - No need to check for interrupt sharing and no need to
5262  * flush status block and interrupt mailbox. PCI ordering rules
5263  * guarantee that MSI will arrive after the status block.
5264  */
5265 static irqreturn_t tg3_msi(int irq, void *dev_id)
5266 {
5267         struct tg3_napi *tnapi = dev_id;
5268         struct tg3 *tp = tnapi->tp;
5269
5270         prefetch(tnapi->hw_status);
5271         if (tnapi->rx_rcb)
5272                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5273         /*
5274          * Writing any value to intr-mbox-0 clears PCI INTA# and
5275          * chip-internal interrupt pending events.
5276          * Writing non-zero to intr-mbox-0 additional tells the
5277          * NIC to stop sending us irqs, engaging "in-intr-handler"
5278          * event coalescing.
5279          */
5280         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5281         if (likely(!tg3_irq_sync(tp)))
5282                 napi_schedule(&tnapi->napi);
5283
5284         return IRQ_RETVAL(1);
5285 }
5286
5287 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5288 {
5289         struct tg3_napi *tnapi = dev_id;
5290         struct tg3 *tp = tnapi->tp;
5291         struct tg3_hw_status *sblk = tnapi->hw_status;
5292         unsigned int handled = 1;
5293
5294         /* In INTx mode, it is possible for the interrupt to arrive at
5295          * the CPU before the status block posted prior to the interrupt.
5296          * Reading the PCI State register will confirm whether the
5297          * interrupt is ours and will flush the status block.
5298          */
5299         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5300                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5301                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5302                         handled = 0;
5303                         goto out;
5304                 }
5305         }
5306
5307         /*
5308          * Writing any value to intr-mbox-0 clears PCI INTA# and
5309          * chip-internal interrupt pending events.
5310          * Writing non-zero to intr-mbox-0 additional tells the
5311          * NIC to stop sending us irqs, engaging "in-intr-handler"
5312          * event coalescing.
5313          *
5314          * Flush the mailbox to de-assert the IRQ immediately to prevent
5315          * spurious interrupts.  The flush impacts performance but
5316          * excessive spurious interrupts can be worse in some cases.
5317          */
5318         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5319         if (tg3_irq_sync(tp))
5320                 goto out;
5321         sblk->status &= ~SD_STATUS_UPDATED;
5322         if (likely(tg3_has_work(tnapi))) {
5323                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5324                 napi_schedule(&tnapi->napi);
5325         } else {
5326                 /* No work, shared interrupt perhaps?  re-enable
5327                  * interrupts, and flush that PCI write
5328                  */
5329                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5330                                0x00000000);
5331         }
5332 out:
5333         return IRQ_RETVAL(handled);
5334 }
5335
5336 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5337 {
5338         struct tg3_napi *tnapi = dev_id;
5339         struct tg3 *tp = tnapi->tp;
5340         struct tg3_hw_status *sblk = tnapi->hw_status;
5341         unsigned int handled = 1;
5342
5343         /* In INTx mode, it is possible for the interrupt to arrive at
5344          * the CPU before the status block posted prior to the interrupt.
5345          * Reading the PCI State register will confirm whether the
5346          * interrupt is ours and will flush the status block.
5347          */
5348         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5349                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5350                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5351                         handled = 0;
5352                         goto out;
5353                 }
5354         }
5355
5356         /*
5357          * writing any value to intr-mbox-0 clears PCI INTA# and
5358          * chip-internal interrupt pending events.
5359          * writing non-zero to intr-mbox-0 additional tells the
5360          * NIC to stop sending us irqs, engaging "in-intr-handler"
5361          * event coalescing.
5362          *
5363          * Flush the mailbox to de-assert the IRQ immediately to prevent
5364          * spurious interrupts.  The flush impacts performance but
5365          * excessive spurious interrupts can be worse in some cases.
5366          */
5367         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5368
5369         /*
5370          * In a shared interrupt configuration, sometimes other devices'
5371          * interrupts will scream.  We record the current status tag here
5372          * so that the above check can report that the screaming interrupts
5373          * are unhandled.  Eventually they will be silenced.
5374          */
5375         tnapi->last_irq_tag = sblk->status_tag;
5376
5377         if (tg3_irq_sync(tp))
5378                 goto out;
5379
5380         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5381
5382         napi_schedule(&tnapi->napi);
5383
5384 out:
5385         return IRQ_RETVAL(handled);
5386 }
5387
5388 /* ISR for interrupt test */
5389 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5390 {
5391         struct tg3_napi *tnapi = dev_id;
5392         struct tg3 *tp = tnapi->tp;
5393         struct tg3_hw_status *sblk = tnapi->hw_status;
5394
5395         if ((sblk->status & SD_STATUS_UPDATED) ||
5396             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5397                 tg3_disable_ints(tp);
5398                 return IRQ_RETVAL(1);
5399         }
5400         return IRQ_RETVAL(0);
5401 }
5402
5403 static int tg3_init_hw(struct tg3 *, int);
5404 static int tg3_halt(struct tg3 *, int, int);
5405
5406 /* Restart hardware after configuration changes, self-test, etc.
5407  * Invoked with tp->lock held.
5408  */
5409 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5410         __releases(tp->lock)
5411         __acquires(tp->lock)
5412 {
5413         int err;
5414
5415         err = tg3_init_hw(tp, reset_phy);
5416         if (err) {
5417                 netdev_err(tp->dev,
5418                            "Failed to re-initialize device, aborting\n");
5419                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5420                 tg3_full_unlock(tp);
5421                 del_timer_sync(&tp->timer);
5422                 tp->irq_sync = 0;
5423                 tg3_napi_enable(tp);
5424                 dev_close(tp->dev);
5425                 tg3_full_lock(tp, 0);
5426         }
5427         return err;
5428 }
5429
5430 #ifdef CONFIG_NET_POLL_CONTROLLER
5431 static void tg3_poll_controller(struct net_device *dev)
5432 {
5433         int i;
5434         struct tg3 *tp = netdev_priv(dev);
5435
5436         for (i = 0; i < tp->irq_cnt; i++)
5437                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5438 }
5439 #endif
5440
5441 static void tg3_reset_task(struct work_struct *work)
5442 {
5443         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5444         int err;
5445         unsigned int restart_timer;
5446
5447         tg3_full_lock(tp, 0);
5448
5449         if (!netif_running(tp->dev)) {
5450                 tg3_full_unlock(tp);
5451                 return;
5452         }
5453
5454         tg3_full_unlock(tp);
5455
5456         tg3_phy_stop(tp);
5457
5458         tg3_netif_stop(tp);
5459
5460         tg3_full_lock(tp, 1);
5461
5462         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5463         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5464
5465         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5466                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5467                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5468                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5469                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5470         }
5471
5472         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5473         err = tg3_init_hw(tp, 1);
5474         if (err)
5475                 goto out;
5476
5477         tg3_netif_start(tp);
5478
5479         if (restart_timer)
5480                 mod_timer(&tp->timer, jiffies + 1);
5481
5482 out:
5483         tg3_full_unlock(tp);
5484
5485         if (!err)
5486                 tg3_phy_start(tp);
5487 }
5488
5489 static void tg3_dump_short_state(struct tg3 *tp)
5490 {
5491         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5492                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5493         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5494                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5495 }
5496
5497 static void tg3_tx_timeout(struct net_device *dev)
5498 {
5499         struct tg3 *tp = netdev_priv(dev);
5500
5501         if (netif_msg_tx_err(tp)) {
5502                 netdev_err(dev, "transmit timed out, resetting\n");
5503                 tg3_dump_short_state(tp);
5504         }
5505
5506         schedule_work(&tp->reset_task);
5507 }
5508
5509 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5510 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5511 {
5512         u32 base = (u32) mapping & 0xffffffff;
5513
5514         return (base > 0xffffdcc0) && (base + len + 8 < base);
5515 }
5516
5517 /* Test for DMA addresses > 40-bit */
5518 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5519                                           int len)
5520 {
5521 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5522         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5523                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5524         return 0;
5525 #else
5526         return 0;
5527 #endif
5528 }
5529
5530 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5531
5532 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5533 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5534                                        struct sk_buff *skb, u32 last_plus_one,
5535                                        u32 *start, u32 base_flags, u32 mss)
5536 {
5537         struct tg3 *tp = tnapi->tp;
5538         struct sk_buff *new_skb;
5539         dma_addr_t new_addr = 0;
5540         u32 entry = *start;
5541         int i, ret = 0;
5542
5543         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5544                 new_skb = skb_copy(skb, GFP_ATOMIC);
5545         else {
5546                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5547
5548                 new_skb = skb_copy_expand(skb,
5549                                           skb_headroom(skb) + more_headroom,
5550                                           skb_tailroom(skb), GFP_ATOMIC);
5551         }
5552
5553         if (!new_skb) {
5554                 ret = -1;
5555         } else {
5556                 /* New SKB is guaranteed to be linear. */
5557                 entry = *start;
5558                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5559                                           PCI_DMA_TODEVICE);
5560                 /* Make sure the mapping succeeded */
5561                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5562                         ret = -1;
5563                         dev_kfree_skb(new_skb);
5564                         new_skb = NULL;
5565
5566                 /* Make sure new skb does not cross any 4G boundaries.
5567                  * Drop the packet if it does.
5568                  */
5569                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5570                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5571                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5572                                          PCI_DMA_TODEVICE);
5573                         ret = -1;
5574                         dev_kfree_skb(new_skb);
5575                         new_skb = NULL;
5576                 } else {
5577                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5578                                     base_flags, 1 | (mss << 1));
5579                         *start = NEXT_TX(entry);
5580                 }
5581         }
5582
5583         /* Now clean up the sw ring entries. */
5584         i = 0;
5585         while (entry != last_plus_one) {
5586                 int len;
5587
5588                 if (i == 0)
5589                         len = skb_headlen(skb);
5590                 else
5591                         len = skb_shinfo(skb)->frags[i-1].size;
5592
5593                 pci_unmap_single(tp->pdev,
5594                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5595                                                 mapping),
5596                                  len, PCI_DMA_TODEVICE);
5597                 if (i == 0) {
5598                         tnapi->tx_buffers[entry].skb = new_skb;
5599                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5600                                            new_addr);
5601                 } else {
5602                         tnapi->tx_buffers[entry].skb = NULL;
5603                 }
5604                 entry = NEXT_TX(entry);
5605                 i++;
5606         }
5607
5608         dev_kfree_skb(skb);
5609
5610         return ret;
5611 }
5612
5613 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5614                         dma_addr_t mapping, int len, u32 flags,
5615                         u32 mss_and_is_end)
5616 {
5617         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5618         int is_end = (mss_and_is_end & 0x1);
5619         u32 mss = (mss_and_is_end >> 1);
5620         u32 vlan_tag = 0;
5621
5622         if (is_end)
5623                 flags |= TXD_FLAG_END;
5624         if (flags & TXD_FLAG_VLAN) {
5625                 vlan_tag = flags >> 16;
5626                 flags &= 0xffff;
5627         }
5628         vlan_tag |= (mss << TXD_MSS_SHIFT);
5629
5630         txd->addr_hi = ((u64) mapping >> 32);
5631         txd->addr_lo = ((u64) mapping & 0xffffffff);
5632         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5633         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5634 }
5635
5636 /* hard_start_xmit for devices that don't have any bugs and
5637  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5638  */
5639 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5640                                   struct net_device *dev)
5641 {
5642         struct tg3 *tp = netdev_priv(dev);
5643         u32 len, entry, base_flags, mss;
5644         dma_addr_t mapping;
5645         struct tg3_napi *tnapi;
5646         struct netdev_queue *txq;
5647         unsigned int i, last;
5648
5649         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5650         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5651         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5652                 tnapi++;
5653
5654         /* We are running in BH disabled context with netif_tx_lock
5655          * and TX reclaim runs via tp->napi.poll inside of a software
5656          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5657          * no IRQ context deadlocks to worry about either.  Rejoice!
5658          */
5659         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5660                 if (!netif_tx_queue_stopped(txq)) {
5661                         netif_tx_stop_queue(txq);
5662
5663                         /* This is a hard error, log it. */
5664                         netdev_err(dev,
5665                                    "BUG! Tx Ring full when queue awake!\n");
5666                 }
5667                 return NETDEV_TX_BUSY;
5668         }
5669
5670         entry = tnapi->tx_prod;
5671         base_flags = 0;
5672         mss = skb_shinfo(skb)->gso_size;
5673         if (mss) {
5674                 int tcp_opt_len, ip_tcp_len;
5675                 u32 hdrlen;
5676
5677                 if (skb_header_cloned(skb) &&
5678                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5679                         dev_kfree_skb(skb);
5680                         goto out_unlock;
5681                 }
5682
5683                 if (skb_is_gso_v6(skb)) {
5684                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5685                 } else {
5686                         struct iphdr *iph = ip_hdr(skb);
5687
5688                         tcp_opt_len = tcp_optlen(skb);
5689                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5690
5691                         iph->check = 0;
5692                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5693                         hdrlen = ip_tcp_len + tcp_opt_len;
5694                 }
5695
5696                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5697                         mss |= (hdrlen & 0xc) << 12;
5698                         if (hdrlen & 0x10)
5699                                 base_flags |= 0x00000010;
5700                         base_flags |= (hdrlen & 0x3e0) << 5;
5701                 } else
5702                         mss |= hdrlen << 9;
5703
5704                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5705                                TXD_FLAG_CPU_POST_DMA);
5706
5707                 tcp_hdr(skb)->check = 0;
5708
5709         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5710                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5711         }
5712
5713         if (vlan_tx_tag_present(skb))
5714                 base_flags |= (TXD_FLAG_VLAN |
5715                                (vlan_tx_tag_get(skb) << 16));
5716
5717         len = skb_headlen(skb);
5718
5719         /* Queue skb data, a.k.a. the main skb fragment. */
5720         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5721         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5722                 dev_kfree_skb(skb);
5723                 goto out_unlock;
5724         }
5725
5726         tnapi->tx_buffers[entry].skb = skb;
5727         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5728
5729         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5730             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5731                 base_flags |= TXD_FLAG_JMB_PKT;
5732
5733         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5734                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5735
5736         entry = NEXT_TX(entry);
5737
5738         /* Now loop through additional data fragments, and queue them. */
5739         if (skb_shinfo(skb)->nr_frags > 0) {
5740                 last = skb_shinfo(skb)->nr_frags - 1;
5741                 for (i = 0; i <= last; i++) {
5742                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5743
5744                         len = frag->size;
5745                         mapping = pci_map_page(tp->pdev,
5746                                                frag->page,
5747                                                frag->page_offset,
5748                                                len, PCI_DMA_TODEVICE);
5749                         if (pci_dma_mapping_error(tp->pdev, mapping))
5750                                 goto dma_error;
5751
5752                         tnapi->tx_buffers[entry].skb = NULL;
5753                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5754                                            mapping);
5755
5756                         tg3_set_txd(tnapi, entry, mapping, len,
5757                                     base_flags, (i == last) | (mss << 1));
5758
5759                         entry = NEXT_TX(entry);
5760                 }
5761         }
5762
5763         /* Packets are ready, update Tx producer idx local and on card. */
5764         tw32_tx_mbox(tnapi->prodmbox, entry);
5765
5766         tnapi->tx_prod = entry;
5767         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5768                 netif_tx_stop_queue(txq);
5769
5770                 /* netif_tx_stop_queue() must be done before checking
5771                  * checking tx index in tg3_tx_avail() below, because in
5772                  * tg3_tx(), we update tx index before checking for
5773                  * netif_tx_queue_stopped().
5774                  */
5775                 smp_mb();
5776                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5777                         netif_tx_wake_queue(txq);
5778         }
5779
5780 out_unlock:
5781         mmiowb();
5782
5783         return NETDEV_TX_OK;
5784
5785 dma_error:
5786         last = i;
5787         entry = tnapi->tx_prod;
5788         tnapi->tx_buffers[entry].skb = NULL;
5789         pci_unmap_single(tp->pdev,
5790                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5791                          skb_headlen(skb),
5792                          PCI_DMA_TODEVICE);
5793         for (i = 0; i <= last; i++) {
5794                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5795                 entry = NEXT_TX(entry);
5796
5797                 pci_unmap_page(tp->pdev,
5798                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5799                                               mapping),
5800                                frag->size, PCI_DMA_TODEVICE);
5801         }
5802
5803         dev_kfree_skb(skb);
5804         return NETDEV_TX_OK;
5805 }
5806
5807 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5808                                           struct net_device *);
5809
5810 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5811  * TSO header is greater than 80 bytes.
5812  */
5813 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5814 {
5815         struct sk_buff *segs, *nskb;
5816         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5817
5818         /* Estimate the number of fragments in the worst case */
5819         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5820                 netif_stop_queue(tp->dev);
5821
5822                 /* netif_tx_stop_queue() must be done before checking
5823                  * checking tx index in tg3_tx_avail() below, because in
5824                  * tg3_tx(), we update tx index before checking for
5825                  * netif_tx_queue_stopped().
5826                  */
5827                 smp_mb();
5828                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5829                         return NETDEV_TX_BUSY;
5830
5831                 netif_wake_queue(tp->dev);
5832         }
5833
5834         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5835         if (IS_ERR(segs))
5836                 goto tg3_tso_bug_end;
5837
5838         do {
5839                 nskb = segs;
5840                 segs = segs->next;
5841                 nskb->next = NULL;
5842                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5843         } while (segs);
5844
5845 tg3_tso_bug_end:
5846         dev_kfree_skb(skb);
5847
5848         return NETDEV_TX_OK;
5849 }
5850
5851 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5852  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5853  */
5854 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5855                                           struct net_device *dev)
5856 {
5857         struct tg3 *tp = netdev_priv(dev);
5858         u32 len, entry, base_flags, mss;
5859         int would_hit_hwbug;
5860         dma_addr_t mapping;
5861         struct tg3_napi *tnapi;
5862         struct netdev_queue *txq;
5863         unsigned int i, last;
5864
5865         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5866         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5867         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5868                 tnapi++;
5869
5870         /* We are running in BH disabled context with netif_tx_lock
5871          * and TX reclaim runs via tp->napi.poll inside of a software
5872          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5873          * no IRQ context deadlocks to worry about either.  Rejoice!
5874          */
5875         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5876                 if (!netif_tx_queue_stopped(txq)) {
5877                         netif_tx_stop_queue(txq);
5878
5879                         /* This is a hard error, log it. */
5880                         netdev_err(dev,
5881                                    "BUG! Tx Ring full when queue awake!\n");
5882                 }
5883                 return NETDEV_TX_BUSY;
5884         }
5885
5886         entry = tnapi->tx_prod;
5887         base_flags = 0;
5888         if (skb->ip_summed == CHECKSUM_PARTIAL)
5889                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5890
5891         mss = skb_shinfo(skb)->gso_size;
5892         if (mss) {
5893                 struct iphdr *iph;
5894                 u32 tcp_opt_len, hdr_len;
5895
5896                 if (skb_header_cloned(skb) &&
5897                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5898                         dev_kfree_skb(skb);
5899                         goto out_unlock;
5900                 }
5901
5902                 iph = ip_hdr(skb);
5903                 tcp_opt_len = tcp_optlen(skb);
5904
5905                 if (skb_is_gso_v6(skb)) {
5906                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5907                 } else {
5908                         u32 ip_tcp_len;
5909
5910                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5911                         hdr_len = ip_tcp_len + tcp_opt_len;
5912
5913                         iph->check = 0;
5914                         iph->tot_len = htons(mss + hdr_len);
5915                 }
5916
5917                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5918                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5919                         return tg3_tso_bug(tp, skb);
5920
5921                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5922                                TXD_FLAG_CPU_POST_DMA);
5923
5924                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5925                         tcp_hdr(skb)->check = 0;
5926                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5927                 } else
5928                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5929                                                                  iph->daddr, 0,
5930                                                                  IPPROTO_TCP,
5931                                                                  0);
5932
5933                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5934                         mss |= (hdr_len & 0xc) << 12;
5935                         if (hdr_len & 0x10)
5936                                 base_flags |= 0x00000010;
5937                         base_flags |= (hdr_len & 0x3e0) << 5;
5938                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5939                         mss |= hdr_len << 9;
5940                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5941                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5942                         if (tcp_opt_len || iph->ihl > 5) {
5943                                 int tsflags;
5944
5945                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5946                                 mss |= (tsflags << 11);
5947                         }
5948                 } else {
5949                         if (tcp_opt_len || iph->ihl > 5) {
5950                                 int tsflags;
5951
5952                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5953                                 base_flags |= tsflags << 12;
5954                         }
5955                 }
5956         }
5957
5958         if (vlan_tx_tag_present(skb))
5959                 base_flags |= (TXD_FLAG_VLAN |
5960                                (vlan_tx_tag_get(skb) << 16));
5961
5962         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5963             !mss && skb->len > VLAN_ETH_FRAME_LEN)
5964                 base_flags |= TXD_FLAG_JMB_PKT;
5965
5966         len = skb_headlen(skb);
5967
5968         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5969         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5970                 dev_kfree_skb(skb);
5971                 goto out_unlock;
5972         }
5973
5974         tnapi->tx_buffers[entry].skb = skb;
5975         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5976
5977         would_hit_hwbug = 0;
5978
5979         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5980                 would_hit_hwbug = 1;
5981
5982         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5983             tg3_4g_overflow_test(mapping, len))
5984                 would_hit_hwbug = 1;
5985
5986         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5987             tg3_40bit_overflow_test(tp, mapping, len))
5988                 would_hit_hwbug = 1;
5989
5990         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5991                 would_hit_hwbug = 1;
5992
5993         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5994                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5995
5996         entry = NEXT_TX(entry);
5997
5998         /* Now loop through additional data fragments, and queue them. */
5999         if (skb_shinfo(skb)->nr_frags > 0) {
6000                 last = skb_shinfo(skb)->nr_frags - 1;
6001                 for (i = 0; i <= last; i++) {
6002                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6003
6004                         len = frag->size;
6005                         mapping = pci_map_page(tp->pdev,
6006                                                frag->page,
6007                                                frag->page_offset,
6008                                                len, PCI_DMA_TODEVICE);
6009
6010                         tnapi->tx_buffers[entry].skb = NULL;
6011                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6012                                            mapping);
6013                         if (pci_dma_mapping_error(tp->pdev, mapping))
6014                                 goto dma_error;
6015
6016                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6017                             len <= 8)
6018                                 would_hit_hwbug = 1;
6019
6020                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6021                             tg3_4g_overflow_test(mapping, len))
6022                                 would_hit_hwbug = 1;
6023
6024                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6025                             tg3_40bit_overflow_test(tp, mapping, len))
6026                                 would_hit_hwbug = 1;
6027
6028                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6029                                 tg3_set_txd(tnapi, entry, mapping, len,
6030                                             base_flags, (i == last)|(mss << 1));
6031                         else
6032                                 tg3_set_txd(tnapi, entry, mapping, len,
6033                                             base_flags, (i == last));
6034
6035                         entry = NEXT_TX(entry);
6036                 }
6037         }
6038
6039         if (would_hit_hwbug) {
6040                 u32 last_plus_one = entry;
6041                 u32 start;
6042
6043                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6044                 start &= (TG3_TX_RING_SIZE - 1);
6045
6046                 /* If the workaround fails due to memory/mapping
6047                  * failure, silently drop this packet.
6048                  */
6049                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6050                                                 &start, base_flags, mss))
6051                         goto out_unlock;
6052
6053                 entry = start;
6054         }
6055
6056         /* Packets are ready, update Tx producer idx local and on card. */
6057         tw32_tx_mbox(tnapi->prodmbox, entry);
6058
6059         tnapi->tx_prod = entry;
6060         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6061                 netif_tx_stop_queue(txq);
6062
6063                 /* netif_tx_stop_queue() must be done before checking
6064                  * checking tx index in tg3_tx_avail() below, because in
6065                  * tg3_tx(), we update tx index before checking for
6066                  * netif_tx_queue_stopped().
6067                  */
6068                 smp_mb();
6069                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6070                         netif_tx_wake_queue(txq);
6071         }
6072
6073 out_unlock:
6074         mmiowb();
6075
6076         return NETDEV_TX_OK;
6077
6078 dma_error:
6079         last = i;
6080         entry = tnapi->tx_prod;
6081         tnapi->tx_buffers[entry].skb = NULL;
6082         pci_unmap_single(tp->pdev,
6083                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6084                          skb_headlen(skb),
6085                          PCI_DMA_TODEVICE);
6086         for (i = 0; i <= last; i++) {
6087                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6088                 entry = NEXT_TX(entry);
6089
6090                 pci_unmap_page(tp->pdev,
6091                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6092                                               mapping),
6093                                frag->size, PCI_DMA_TODEVICE);
6094         }
6095
6096         dev_kfree_skb(skb);
6097         return NETDEV_TX_OK;
6098 }
6099
6100 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6101                                int new_mtu)
6102 {
6103         dev->mtu = new_mtu;
6104
6105         if (new_mtu > ETH_DATA_LEN) {
6106                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6107                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6108                         ethtool_op_set_tso(dev, 0);
6109                 } else {
6110                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6111                 }
6112         } else {
6113                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6114                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6115                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6116         }
6117 }
6118
6119 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6120 {
6121         struct tg3 *tp = netdev_priv(dev);
6122         int err;
6123
6124         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6125                 return -EINVAL;
6126
6127         if (!netif_running(dev)) {
6128                 /* We'll just catch it later when the
6129                  * device is up'd.
6130                  */
6131                 tg3_set_mtu(dev, tp, new_mtu);
6132                 return 0;
6133         }
6134
6135         tg3_phy_stop(tp);
6136
6137         tg3_netif_stop(tp);
6138
6139         tg3_full_lock(tp, 1);
6140
6141         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6142
6143         tg3_set_mtu(dev, tp, new_mtu);
6144
6145         err = tg3_restart_hw(tp, 0);
6146
6147         if (!err)
6148                 tg3_netif_start(tp);
6149
6150         tg3_full_unlock(tp);
6151
6152         if (!err)
6153                 tg3_phy_start(tp);
6154
6155         return err;
6156 }
6157
6158 static void tg3_rx_prodring_free(struct tg3 *tp,
6159                                  struct tg3_rx_prodring_set *tpr)
6160 {
6161         int i;
6162
6163         if (tpr != &tp->napi[0].prodring) {
6164                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6165                      i = (i + 1) & tp->rx_std_ring_mask)
6166                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6167                                         tp->rx_pkt_map_sz);
6168
6169                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6170                         for (i = tpr->rx_jmb_cons_idx;
6171                              i != tpr->rx_jmb_prod_idx;
6172                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6173                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6174                                                 TG3_RX_JMB_MAP_SZ);
6175                         }
6176                 }
6177
6178                 return;
6179         }
6180
6181         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6182                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6183                                 tp->rx_pkt_map_sz);
6184
6185         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6186             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6187                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6188                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6189                                         TG3_RX_JMB_MAP_SZ);
6190         }
6191 }
6192
6193 /* Initialize rx rings for packet processing.
6194  *
6195  * The chip has been shut down and the driver detached from
6196  * the networking, so no interrupts or new tx packets will
6197  * end up in the driver.  tp->{tx,}lock are held and thus
6198  * we may not sleep.
6199  */
6200 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6201                                  struct tg3_rx_prodring_set *tpr)
6202 {
6203         u32 i, rx_pkt_dma_sz;
6204
6205         tpr->rx_std_cons_idx = 0;
6206         tpr->rx_std_prod_idx = 0;
6207         tpr->rx_jmb_cons_idx = 0;
6208         tpr->rx_jmb_prod_idx = 0;
6209
6210         if (tpr != &tp->napi[0].prodring) {
6211                 memset(&tpr->rx_std_buffers[0], 0,
6212                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6213                 if (tpr->rx_jmb_buffers)
6214                         memset(&tpr->rx_jmb_buffers[0], 0,
6215                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6216                 goto done;
6217         }
6218
6219         /* Zero out all descriptors. */
6220         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6221
6222         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6223         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6224             tp->dev->mtu > ETH_DATA_LEN)
6225                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6226         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6227
6228         /* Initialize invariants of the rings, we only set this
6229          * stuff once.  This works because the card does not
6230          * write into the rx buffer posting rings.
6231          */
6232         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6233                 struct tg3_rx_buffer_desc *rxd;
6234
6235                 rxd = &tpr->rx_std[i];
6236                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6237                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6238                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6239                                (i << RXD_OPAQUE_INDEX_SHIFT));
6240         }
6241
6242         /* Now allocate fresh SKBs for each rx ring. */
6243         for (i = 0; i < tp->rx_pending; i++) {
6244                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6245                         netdev_warn(tp->dev,
6246                                     "Using a smaller RX standard ring. Only "
6247                                     "%d out of %d buffers were allocated "
6248                                     "successfully\n", i, tp->rx_pending);
6249                         if (i == 0)
6250                                 goto initfail;
6251                         tp->rx_pending = i;
6252                         break;
6253                 }
6254         }
6255
6256         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6257             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6258                 goto done;
6259
6260         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6261
6262         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6263                 goto done;
6264
6265         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6266                 struct tg3_rx_buffer_desc *rxd;
6267
6268                 rxd = &tpr->rx_jmb[i].std;
6269                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6270                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6271                                   RXD_FLAG_JUMBO;
6272                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6273                        (i << RXD_OPAQUE_INDEX_SHIFT));
6274         }
6275
6276         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6277                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6278                         netdev_warn(tp->dev,
6279                                     "Using a smaller RX jumbo ring. Only %d "
6280                                     "out of %d buffers were allocated "
6281                                     "successfully\n", i, tp->rx_jumbo_pending);
6282                         if (i == 0)
6283                                 goto initfail;
6284                         tp->rx_jumbo_pending = i;
6285                         break;
6286                 }
6287         }
6288
6289 done:
6290         return 0;
6291
6292 initfail:
6293         tg3_rx_prodring_free(tp, tpr);
6294         return -ENOMEM;
6295 }
6296
6297 static void tg3_rx_prodring_fini(struct tg3 *tp,
6298                                  struct tg3_rx_prodring_set *tpr)
6299 {
6300         kfree(tpr->rx_std_buffers);
6301         tpr->rx_std_buffers = NULL;
6302         kfree(tpr->rx_jmb_buffers);
6303         tpr->rx_jmb_buffers = NULL;
6304         if (tpr->rx_std) {
6305                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6306                                   tpr->rx_std, tpr->rx_std_mapping);
6307                 tpr->rx_std = NULL;
6308         }
6309         if (tpr->rx_jmb) {
6310                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6311                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6312                 tpr->rx_jmb = NULL;
6313         }
6314 }
6315
6316 static int tg3_rx_prodring_init(struct tg3 *tp,
6317                                 struct tg3_rx_prodring_set *tpr)
6318 {
6319         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6320                                       GFP_KERNEL);
6321         if (!tpr->rx_std_buffers)
6322                 return -ENOMEM;
6323
6324         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6325                                          TG3_RX_STD_RING_BYTES(tp),
6326                                          &tpr->rx_std_mapping,
6327                                          GFP_KERNEL);
6328         if (!tpr->rx_std)
6329                 goto err_out;
6330
6331         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6332             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6333                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6334                                               GFP_KERNEL);
6335                 if (!tpr->rx_jmb_buffers)
6336                         goto err_out;
6337
6338                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6339                                                  TG3_RX_JMB_RING_BYTES(tp),
6340                                                  &tpr->rx_jmb_mapping,
6341                                                  GFP_KERNEL);
6342                 if (!tpr->rx_jmb)
6343                         goto err_out;
6344         }
6345
6346         return 0;
6347
6348 err_out:
6349         tg3_rx_prodring_fini(tp, tpr);
6350         return -ENOMEM;
6351 }
6352
6353 /* Free up pending packets in all rx/tx rings.
6354  *
6355  * The chip has been shut down and the driver detached from
6356  * the networking, so no interrupts or new tx packets will
6357  * end up in the driver.  tp->{tx,}lock is not held and we are not
6358  * in an interrupt context and thus may sleep.
6359  */
6360 static void tg3_free_rings(struct tg3 *tp)
6361 {
6362         int i, j;
6363
6364         for (j = 0; j < tp->irq_cnt; j++) {
6365                 struct tg3_napi *tnapi = &tp->napi[j];
6366
6367                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6368
6369                 if (!tnapi->tx_buffers)
6370                         continue;
6371
6372                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6373                         struct ring_info *txp;
6374                         struct sk_buff *skb;
6375                         unsigned int k;
6376
6377                         txp = &tnapi->tx_buffers[i];
6378                         skb = txp->skb;
6379
6380                         if (skb == NULL) {
6381                                 i++;
6382                                 continue;
6383                         }
6384
6385                         pci_unmap_single(tp->pdev,
6386                                          dma_unmap_addr(txp, mapping),
6387                                          skb_headlen(skb),
6388                                          PCI_DMA_TODEVICE);
6389                         txp->skb = NULL;
6390
6391                         i++;
6392
6393                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6394                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6395                                 pci_unmap_page(tp->pdev,
6396                                                dma_unmap_addr(txp, mapping),
6397                                                skb_shinfo(skb)->frags[k].size,
6398                                                PCI_DMA_TODEVICE);
6399                                 i++;
6400                         }
6401
6402                         dev_kfree_skb_any(skb);
6403                 }
6404         }
6405 }
6406
6407 /* Initialize tx/rx rings for packet processing.
6408  *
6409  * The chip has been shut down and the driver detached from
6410  * the networking, so no interrupts or new tx packets will
6411  * end up in the driver.  tp->{tx,}lock are held and thus
6412  * we may not sleep.
6413  */
6414 static int tg3_init_rings(struct tg3 *tp)
6415 {
6416         int i;
6417
6418         /* Free up all the SKBs. */
6419         tg3_free_rings(tp);
6420
6421         for (i = 0; i < tp->irq_cnt; i++) {
6422                 struct tg3_napi *tnapi = &tp->napi[i];
6423
6424                 tnapi->last_tag = 0;
6425                 tnapi->last_irq_tag = 0;
6426                 tnapi->hw_status->status = 0;
6427                 tnapi->hw_status->status_tag = 0;
6428                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6429
6430                 tnapi->tx_prod = 0;
6431                 tnapi->tx_cons = 0;
6432                 if (tnapi->tx_ring)
6433                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6434
6435                 tnapi->rx_rcb_ptr = 0;
6436                 if (tnapi->rx_rcb)
6437                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6438
6439                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6440                         tg3_free_rings(tp);
6441                         return -ENOMEM;
6442                 }
6443         }
6444
6445         return 0;
6446 }
6447
6448 /*
6449  * Must not be invoked with interrupt sources disabled and
6450  * the hardware shutdown down.
6451  */
6452 static void tg3_free_consistent(struct tg3 *tp)
6453 {
6454         int i;
6455
6456         for (i = 0; i < tp->irq_cnt; i++) {
6457                 struct tg3_napi *tnapi = &tp->napi[i];
6458
6459                 if (tnapi->tx_ring) {
6460                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6461                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6462                         tnapi->tx_ring = NULL;
6463                 }
6464
6465                 kfree(tnapi->tx_buffers);
6466                 tnapi->tx_buffers = NULL;
6467
6468                 if (tnapi->rx_rcb) {
6469                         dma_free_coherent(&tp->pdev->dev,
6470                                           TG3_RX_RCB_RING_BYTES(tp),
6471                                           tnapi->rx_rcb,
6472                                           tnapi->rx_rcb_mapping);
6473                         tnapi->rx_rcb = NULL;
6474                 }
6475
6476                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6477
6478                 if (tnapi->hw_status) {
6479                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6480                                           tnapi->hw_status,
6481                                           tnapi->status_mapping);
6482                         tnapi->hw_status = NULL;
6483                 }
6484         }
6485
6486         if (tp->hw_stats) {
6487                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6488                                   tp->hw_stats, tp->stats_mapping);
6489                 tp->hw_stats = NULL;
6490         }
6491 }
6492
6493 /*
6494  * Must not be invoked with interrupt sources disabled and
6495  * the hardware shutdown down.  Can sleep.
6496  */
6497 static int tg3_alloc_consistent(struct tg3 *tp)
6498 {
6499         int i;
6500
6501         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6502                                           sizeof(struct tg3_hw_stats),
6503                                           &tp->stats_mapping,
6504                                           GFP_KERNEL);
6505         if (!tp->hw_stats)
6506                 goto err_out;
6507
6508         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6509
6510         for (i = 0; i < tp->irq_cnt; i++) {
6511                 struct tg3_napi *tnapi = &tp->napi[i];
6512                 struct tg3_hw_status *sblk;
6513
6514                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6515                                                       TG3_HW_STATUS_SIZE,
6516                                                       &tnapi->status_mapping,
6517                                                       GFP_KERNEL);
6518                 if (!tnapi->hw_status)
6519                         goto err_out;
6520
6521                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6522                 sblk = tnapi->hw_status;
6523
6524                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6525                         goto err_out;
6526
6527                 /* If multivector TSS is enabled, vector 0 does not handle
6528                  * tx interrupts.  Don't allocate any resources for it.
6529                  */
6530                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6531                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6532                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6533                                                     TG3_TX_RING_SIZE,
6534                                                     GFP_KERNEL);
6535                         if (!tnapi->tx_buffers)
6536                                 goto err_out;
6537
6538                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6539                                                             TG3_TX_RING_BYTES,
6540                                                         &tnapi->tx_desc_mapping,
6541                                                             GFP_KERNEL);
6542                         if (!tnapi->tx_ring)
6543                                 goto err_out;
6544                 }
6545
6546                 /*
6547                  * When RSS is enabled, the status block format changes
6548                  * slightly.  The "rx_jumbo_consumer", "reserved",
6549                  * and "rx_mini_consumer" members get mapped to the
6550                  * other three rx return ring producer indexes.
6551                  */
6552                 switch (i) {
6553                 default:
6554                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6555                         break;
6556                 case 2:
6557                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6558                         break;
6559                 case 3:
6560                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6561                         break;
6562                 case 4:
6563                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6564                         break;
6565                 }
6566
6567                 /*
6568                  * If multivector RSS is enabled, vector 0 does not handle
6569                  * rx or tx interrupts.  Don't allocate any resources for it.
6570                  */
6571                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6572                         continue;
6573
6574                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6575                                                    TG3_RX_RCB_RING_BYTES(tp),
6576                                                    &tnapi->rx_rcb_mapping,
6577                                                    GFP_KERNEL);
6578                 if (!tnapi->rx_rcb)
6579                         goto err_out;
6580
6581                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6582         }
6583
6584         return 0;
6585
6586 err_out:
6587         tg3_free_consistent(tp);
6588         return -ENOMEM;
6589 }
6590
6591 #define MAX_WAIT_CNT 1000
6592
6593 /* To stop a block, clear the enable bit and poll till it
6594  * clears.  tp->lock is held.
6595  */
6596 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6597 {
6598         unsigned int i;
6599         u32 val;
6600
6601         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6602                 switch (ofs) {
6603                 case RCVLSC_MODE:
6604                 case DMAC_MODE:
6605                 case MBFREE_MODE:
6606                 case BUFMGR_MODE:
6607                 case MEMARB_MODE:
6608                         /* We can't enable/disable these bits of the
6609                          * 5705/5750, just say success.
6610                          */
6611                         return 0;
6612
6613                 default:
6614                         break;
6615                 }
6616         }
6617
6618         val = tr32(ofs);
6619         val &= ~enable_bit;
6620         tw32_f(ofs, val);
6621
6622         for (i = 0; i < MAX_WAIT_CNT; i++) {
6623                 udelay(100);
6624                 val = tr32(ofs);
6625                 if ((val & enable_bit) == 0)
6626                         break;
6627         }
6628
6629         if (i == MAX_WAIT_CNT && !silent) {
6630                 dev_err(&tp->pdev->dev,
6631                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6632                         ofs, enable_bit);
6633                 return -ENODEV;
6634         }
6635
6636         return 0;
6637 }
6638
6639 /* tp->lock is held. */
6640 static int tg3_abort_hw(struct tg3 *tp, int silent)
6641 {
6642         int i, err;
6643
6644         tg3_disable_ints(tp);
6645
6646         tp->rx_mode &= ~RX_MODE_ENABLE;
6647         tw32_f(MAC_RX_MODE, tp->rx_mode);
6648         udelay(10);
6649
6650         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6651         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6652         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6653         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6654         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6655         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6656
6657         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6658         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6659         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6660         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6661         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6662         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6663         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6664
6665         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6666         tw32_f(MAC_MODE, tp->mac_mode);
6667         udelay(40);
6668
6669         tp->tx_mode &= ~TX_MODE_ENABLE;
6670         tw32_f(MAC_TX_MODE, tp->tx_mode);
6671
6672         for (i = 0; i < MAX_WAIT_CNT; i++) {
6673                 udelay(100);
6674                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6675                         break;
6676         }
6677         if (i >= MAX_WAIT_CNT) {
6678                 dev_err(&tp->pdev->dev,
6679                         "%s timed out, TX_MODE_ENABLE will not clear "
6680                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6681                 err |= -ENODEV;
6682         }
6683
6684         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6685         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6686         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6687
6688         tw32(FTQ_RESET, 0xffffffff);
6689         tw32(FTQ_RESET, 0x00000000);
6690
6691         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6692         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6693
6694         for (i = 0; i < tp->irq_cnt; i++) {
6695                 struct tg3_napi *tnapi = &tp->napi[i];
6696                 if (tnapi->hw_status)
6697                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6698         }
6699         if (tp->hw_stats)
6700                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6701
6702         return err;
6703 }
6704
6705 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6706 {
6707         int i;
6708         u32 apedata;
6709
6710         /* NCSI does not support APE events */
6711         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6712                 return;
6713
6714         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6715         if (apedata != APE_SEG_SIG_MAGIC)
6716                 return;
6717
6718         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6719         if (!(apedata & APE_FW_STATUS_READY))
6720                 return;
6721
6722         /* Wait for up to 1 millisecond for APE to service previous event. */
6723         for (i = 0; i < 10; i++) {
6724                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6725                         return;
6726
6727                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6728
6729                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6730                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6731                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6732
6733                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6734
6735                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6736                         break;
6737
6738                 udelay(100);
6739         }
6740
6741         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6742                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6743 }
6744
6745 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6746 {
6747         u32 event;
6748         u32 apedata;
6749
6750         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6751                 return;
6752
6753         switch (kind) {
6754         case RESET_KIND_INIT:
6755                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6756                                 APE_HOST_SEG_SIG_MAGIC);
6757                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6758                                 APE_HOST_SEG_LEN_MAGIC);
6759                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6760                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6761                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6762                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6763                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6764                                 APE_HOST_BEHAV_NO_PHYLOCK);
6765                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6766                                     TG3_APE_HOST_DRVR_STATE_START);
6767
6768                 event = APE_EVENT_STATUS_STATE_START;
6769                 break;
6770         case RESET_KIND_SHUTDOWN:
6771                 /* With the interface we are currently using,
6772                  * APE does not track driver state.  Wiping
6773                  * out the HOST SEGMENT SIGNATURE forces
6774                  * the APE to assume OS absent status.
6775                  */
6776                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6777
6778                 if (device_may_wakeup(&tp->pdev->dev) &&
6779                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6780                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6781                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6782                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6783                 } else
6784                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6785
6786                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6787
6788                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6789                 break;
6790         case RESET_KIND_SUSPEND:
6791                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6792                 break;
6793         default:
6794                 return;
6795         }
6796
6797         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6798
6799         tg3_ape_send_event(tp, event);
6800 }
6801
6802 /* tp->lock is held. */
6803 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6804 {
6805         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6806                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6807
6808         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6809                 switch (kind) {
6810                 case RESET_KIND_INIT:
6811                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6812                                       DRV_STATE_START);
6813                         break;
6814
6815                 case RESET_KIND_SHUTDOWN:
6816                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6817                                       DRV_STATE_UNLOAD);
6818                         break;
6819
6820                 case RESET_KIND_SUSPEND:
6821                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6822                                       DRV_STATE_SUSPEND);
6823                         break;
6824
6825                 default:
6826                         break;
6827                 }
6828         }
6829
6830         if (kind == RESET_KIND_INIT ||
6831             kind == RESET_KIND_SUSPEND)
6832                 tg3_ape_driver_state_change(tp, kind);
6833 }
6834
6835 /* tp->lock is held. */
6836 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6837 {
6838         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6839                 switch (kind) {
6840                 case RESET_KIND_INIT:
6841                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6842                                       DRV_STATE_START_DONE);
6843                         break;
6844
6845                 case RESET_KIND_SHUTDOWN:
6846                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6847                                       DRV_STATE_UNLOAD_DONE);
6848                         break;
6849
6850                 default:
6851                         break;
6852                 }
6853         }
6854
6855         if (kind == RESET_KIND_SHUTDOWN)
6856                 tg3_ape_driver_state_change(tp, kind);
6857 }
6858
6859 /* tp->lock is held. */
6860 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6861 {
6862         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6863                 switch (kind) {
6864                 case RESET_KIND_INIT:
6865                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6866                                       DRV_STATE_START);
6867                         break;
6868
6869                 case RESET_KIND_SHUTDOWN:
6870                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6871                                       DRV_STATE_UNLOAD);
6872                         break;
6873
6874                 case RESET_KIND_SUSPEND:
6875                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6876                                       DRV_STATE_SUSPEND);
6877                         break;
6878
6879                 default:
6880                         break;
6881                 }
6882         }
6883 }
6884
6885 static int tg3_poll_fw(struct tg3 *tp)
6886 {
6887         int i;
6888         u32 val;
6889
6890         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6891                 /* Wait up to 20ms for init done. */
6892                 for (i = 0; i < 200; i++) {
6893                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6894                                 return 0;
6895                         udelay(100);
6896                 }
6897                 return -ENODEV;
6898         }
6899
6900         /* Wait for firmware initialization to complete. */
6901         for (i = 0; i < 100000; i++) {
6902                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6903                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6904                         break;
6905                 udelay(10);
6906         }
6907
6908         /* Chip might not be fitted with firmware.  Some Sun onboard
6909          * parts are configured like that.  So don't signal the timeout
6910          * of the above loop as an error, but do report the lack of
6911          * running firmware once.
6912          */
6913         if (i >= 100000 &&
6914             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6915                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6916
6917                 netdev_info(tp->dev, "No firmware running\n");
6918         }
6919
6920         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6921                 /* The 57765 A0 needs a little more
6922                  * time to do some important work.
6923                  */
6924                 mdelay(10);
6925         }
6926
6927         return 0;
6928 }
6929
6930 /* Save PCI command register before chip reset */
6931 static void tg3_save_pci_state(struct tg3 *tp)
6932 {
6933         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6934 }
6935
6936 /* Restore PCI state after chip reset */
6937 static void tg3_restore_pci_state(struct tg3 *tp)
6938 {
6939         u32 val;
6940
6941         /* Re-enable indirect register accesses. */
6942         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6943                                tp->misc_host_ctrl);
6944
6945         /* Set MAX PCI retry to zero. */
6946         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6947         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6948             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6949                 val |= PCISTATE_RETRY_SAME_DMA;
6950         /* Allow reads and writes to the APE register and memory space. */
6951         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6952                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6953                        PCISTATE_ALLOW_APE_SHMEM_WR |
6954                        PCISTATE_ALLOW_APE_PSPACE_WR;
6955         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6956
6957         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6958
6959         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6960                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6961                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6962                 else {
6963                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6964                                               tp->pci_cacheline_sz);
6965                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6966                                               tp->pci_lat_timer);
6967                 }
6968         }
6969
6970         /* Make sure PCI-X relaxed ordering bit is clear. */
6971         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6972                 u16 pcix_cmd;
6973
6974                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6975                                      &pcix_cmd);
6976                 pcix_cmd &= ~PCI_X_CMD_ERO;
6977                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6978                                       pcix_cmd);
6979         }
6980
6981         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6982
6983                 /* Chip reset on 5780 will reset MSI enable bit,
6984                  * so need to restore it.
6985                  */
6986                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6987                         u16 ctrl;
6988
6989                         pci_read_config_word(tp->pdev,
6990                                              tp->msi_cap + PCI_MSI_FLAGS,
6991                                              &ctrl);
6992                         pci_write_config_word(tp->pdev,
6993                                               tp->msi_cap + PCI_MSI_FLAGS,
6994                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6995                         val = tr32(MSGINT_MODE);
6996                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6997                 }
6998         }
6999 }
7000
7001 static void tg3_stop_fw(struct tg3 *);
7002
7003 /* tp->lock is held. */
7004 static int tg3_chip_reset(struct tg3 *tp)
7005 {
7006         u32 val;
7007         void (*write_op)(struct tg3 *, u32, u32);
7008         int i, err;
7009
7010         tg3_nvram_lock(tp);
7011
7012         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7013
7014         /* No matching tg3_nvram_unlock() after this because
7015          * chip reset below will undo the nvram lock.
7016          */
7017         tp->nvram_lock_cnt = 0;
7018
7019         /* GRC_MISC_CFG core clock reset will clear the memory
7020          * enable bit in PCI register 4 and the MSI enable bit
7021          * on some chips, so we save relevant registers here.
7022          */
7023         tg3_save_pci_state(tp);
7024
7025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7026             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7027                 tw32(GRC_FASTBOOT_PC, 0);
7028
7029         /*
7030          * We must avoid the readl() that normally takes place.
7031          * It locks machines, causes machine checks, and other
7032          * fun things.  So, temporarily disable the 5701
7033          * hardware workaround, while we do the reset.
7034          */
7035         write_op = tp->write32;
7036         if (write_op == tg3_write_flush_reg32)
7037                 tp->write32 = tg3_write32;
7038
7039         /* Prevent the irq handler from reading or writing PCI registers
7040          * during chip reset when the memory enable bit in the PCI command
7041          * register may be cleared.  The chip does not generate interrupt
7042          * at this time, but the irq handler may still be called due to irq
7043          * sharing or irqpoll.
7044          */
7045         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7046         for (i = 0; i < tp->irq_cnt; i++) {
7047                 struct tg3_napi *tnapi = &tp->napi[i];
7048                 if (tnapi->hw_status) {
7049                         tnapi->hw_status->status = 0;
7050                         tnapi->hw_status->status_tag = 0;
7051                 }
7052                 tnapi->last_tag = 0;
7053                 tnapi->last_irq_tag = 0;
7054         }
7055         smp_mb();
7056
7057         for (i = 0; i < tp->irq_cnt; i++)
7058                 synchronize_irq(tp->napi[i].irq_vec);
7059
7060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7061                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7062                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7063         }
7064
7065         /* do the reset */
7066         val = GRC_MISC_CFG_CORECLK_RESET;
7067
7068         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7069                 /* Force PCIe 1.0a mode */
7070                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7071                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7072                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7073                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7074                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7075
7076                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7077                         tw32(GRC_MISC_CFG, (1 << 29));
7078                         val |= (1 << 29);
7079                 }
7080         }
7081
7082         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7083                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7084                 tw32(GRC_VCPU_EXT_CTRL,
7085                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7086         }
7087
7088         /* Manage gphy power for all CPMU absent PCIe devices. */
7089         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7090             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7091                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7092
7093         tw32(GRC_MISC_CFG, val);
7094
7095         /* restore 5701 hardware bug workaround write method */
7096         tp->write32 = write_op;
7097
7098         /* Unfortunately, we have to delay before the PCI read back.
7099          * Some 575X chips even will not respond to a PCI cfg access
7100          * when the reset command is given to the chip.
7101          *
7102          * How do these hardware designers expect things to work
7103          * properly if the PCI write is posted for a long period
7104          * of time?  It is always necessary to have some method by
7105          * which a register read back can occur to push the write
7106          * out which does the reset.
7107          *
7108          * For most tg3 variants the trick below was working.
7109          * Ho hum...
7110          */
7111         udelay(120);
7112
7113         /* Flush PCI posted writes.  The normal MMIO registers
7114          * are inaccessible at this time so this is the only
7115          * way to make this reliably (actually, this is no longer
7116          * the case, see above).  I tried to use indirect
7117          * register read/write but this upset some 5701 variants.
7118          */
7119         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7120
7121         udelay(120);
7122
7123         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7124                 u16 val16;
7125
7126                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7127                         int i;
7128                         u32 cfg_val;
7129
7130                         /* Wait for link training to complete.  */
7131                         for (i = 0; i < 5000; i++)
7132                                 udelay(100);
7133
7134                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7135                         pci_write_config_dword(tp->pdev, 0xc4,
7136                                                cfg_val | (1 << 15));
7137                 }
7138
7139                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7140                 pci_read_config_word(tp->pdev,
7141                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7142                                      &val16);
7143                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7144                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7145                 /*
7146                  * Older PCIe devices only support the 128 byte
7147                  * MPS setting.  Enforce the restriction.
7148                  */
7149                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7150                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7151                 pci_write_config_word(tp->pdev,
7152                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7153                                       val16);
7154
7155                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7156
7157                 /* Clear error status */
7158                 pci_write_config_word(tp->pdev,
7159                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7160                                       PCI_EXP_DEVSTA_CED |
7161                                       PCI_EXP_DEVSTA_NFED |
7162                                       PCI_EXP_DEVSTA_FED |
7163                                       PCI_EXP_DEVSTA_URD);
7164         }
7165
7166         tg3_restore_pci_state(tp);
7167
7168         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7169
7170         val = 0;
7171         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7172                 val = tr32(MEMARB_MODE);
7173         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7174
7175         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7176                 tg3_stop_fw(tp);
7177                 tw32(0x5000, 0x400);
7178         }
7179
7180         tw32(GRC_MODE, tp->grc_mode);
7181
7182         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7183                 val = tr32(0xc4);
7184
7185                 tw32(0xc4, val | (1 << 15));
7186         }
7187
7188         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7189             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7190                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7191                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7192                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7193                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7194         }
7195
7196         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7197                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7198                                MAC_MODE_APE_RX_EN |
7199                                MAC_MODE_TDE_ENABLE;
7200
7201         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7202                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7203                 val = tp->mac_mode;
7204         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7205                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7206                 val = tp->mac_mode;
7207         } else
7208                 val = 0;
7209
7210         tw32_f(MAC_MODE, val);
7211         udelay(40);
7212
7213         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7214
7215         err = tg3_poll_fw(tp);
7216         if (err)
7217                 return err;
7218
7219         tg3_mdio_start(tp);
7220
7221         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7222             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7223             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7224             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7225                 val = tr32(0x7c00);
7226
7227                 tw32(0x7c00, val | (1 << 25));
7228         }
7229
7230         /* Reprobe ASF enable state.  */
7231         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7232         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7233         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7234         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7235                 u32 nic_cfg;
7236
7237                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7238                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7239                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7240                         tp->last_event_jiffies = jiffies;
7241                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7242                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7243                 }
7244         }
7245
7246         return 0;
7247 }
7248
7249 /* tp->lock is held. */
7250 static void tg3_stop_fw(struct tg3 *tp)
7251 {
7252         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7253            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7254                 /* Wait for RX cpu to ACK the previous event. */
7255                 tg3_wait_for_event_ack(tp);
7256
7257                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7258
7259                 tg3_generate_fw_event(tp);
7260
7261                 /* Wait for RX cpu to ACK this event. */
7262                 tg3_wait_for_event_ack(tp);
7263         }
7264 }
7265
7266 /* tp->lock is held. */
7267 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7268 {
7269         int err;
7270
7271         tg3_stop_fw(tp);
7272
7273         tg3_write_sig_pre_reset(tp, kind);
7274
7275         tg3_abort_hw(tp, silent);
7276         err = tg3_chip_reset(tp);
7277
7278         __tg3_set_mac_addr(tp, 0);
7279
7280         tg3_write_sig_legacy(tp, kind);
7281         tg3_write_sig_post_reset(tp, kind);
7282
7283         if (err)
7284                 return err;
7285
7286         return 0;
7287 }
7288
7289 #define RX_CPU_SCRATCH_BASE     0x30000
7290 #define RX_CPU_SCRATCH_SIZE     0x04000
7291 #define TX_CPU_SCRATCH_BASE     0x34000
7292 #define TX_CPU_SCRATCH_SIZE     0x04000
7293
7294 /* tp->lock is held. */
7295 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7296 {
7297         int i;
7298
7299         BUG_ON(offset == TX_CPU_BASE &&
7300             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7301
7302         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7303                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7304
7305                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7306                 return 0;
7307         }
7308         if (offset == RX_CPU_BASE) {
7309                 for (i = 0; i < 10000; i++) {
7310                         tw32(offset + CPU_STATE, 0xffffffff);
7311                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7312                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7313                                 break;
7314                 }
7315
7316                 tw32(offset + CPU_STATE, 0xffffffff);
7317                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7318                 udelay(10);
7319         } else {
7320                 for (i = 0; i < 10000; i++) {
7321                         tw32(offset + CPU_STATE, 0xffffffff);
7322                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7323                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7324                                 break;
7325                 }
7326         }
7327
7328         if (i >= 10000) {
7329                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7330                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7331                 return -ENODEV;
7332         }
7333
7334         /* Clear firmware's nvram arbitration. */
7335         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7336                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7337         return 0;
7338 }
7339
7340 struct fw_info {
7341         unsigned int fw_base;
7342         unsigned int fw_len;
7343         const __be32 *fw_data;
7344 };
7345
7346 /* tp->lock is held. */
7347 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7348                                  int cpu_scratch_size, struct fw_info *info)
7349 {
7350         int err, lock_err, i;
7351         void (*write_op)(struct tg3 *, u32, u32);
7352
7353         if (cpu_base == TX_CPU_BASE &&
7354             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7355                 netdev_err(tp->dev,
7356                            "%s: Trying to load TX cpu firmware which is 5705\n",
7357                            __func__);
7358                 return -EINVAL;
7359         }
7360
7361         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7362                 write_op = tg3_write_mem;
7363         else
7364                 write_op = tg3_write_indirect_reg32;
7365
7366         /* It is possible that bootcode is still loading at this point.
7367          * Get the nvram lock first before halting the cpu.
7368          */
7369         lock_err = tg3_nvram_lock(tp);
7370         err = tg3_halt_cpu(tp, cpu_base);
7371         if (!lock_err)
7372                 tg3_nvram_unlock(tp);
7373         if (err)
7374                 goto out;
7375
7376         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7377                 write_op(tp, cpu_scratch_base + i, 0);
7378         tw32(cpu_base + CPU_STATE, 0xffffffff);
7379         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7380         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7381                 write_op(tp, (cpu_scratch_base +
7382                               (info->fw_base & 0xffff) +
7383                               (i * sizeof(u32))),
7384                               be32_to_cpu(info->fw_data[i]));
7385
7386         err = 0;
7387
7388 out:
7389         return err;
7390 }
7391
7392 /* tp->lock is held. */
7393 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7394 {
7395         struct fw_info info;
7396         const __be32 *fw_data;
7397         int err, i;
7398
7399         fw_data = (void *)tp->fw->data;
7400
7401         /* Firmware blob starts with version numbers, followed by
7402            start address and length. We are setting complete length.
7403            length = end_address_of_bss - start_address_of_text.
7404            Remainder is the blob to be loaded contiguously
7405            from start address. */
7406
7407         info.fw_base = be32_to_cpu(fw_data[1]);
7408         info.fw_len = tp->fw->size - 12;
7409         info.fw_data = &fw_data[3];
7410
7411         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7412                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7413                                     &info);
7414         if (err)
7415                 return err;
7416
7417         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7418                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7419                                     &info);
7420         if (err)
7421                 return err;
7422
7423         /* Now startup only the RX cpu. */
7424         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7425         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7426
7427         for (i = 0; i < 5; i++) {
7428                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7429                         break;
7430                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7431                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7432                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7433                 udelay(1000);
7434         }
7435         if (i >= 5) {
7436                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7437                            "should be %08x\n", __func__,
7438                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7439                 return -ENODEV;
7440         }
7441         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7442         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7443
7444         return 0;
7445 }
7446
7447 /* 5705 needs a special version of the TSO firmware.  */
7448
7449 /* tp->lock is held. */
7450 static int tg3_load_tso_firmware(struct tg3 *tp)
7451 {
7452         struct fw_info info;
7453         const __be32 *fw_data;
7454         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7455         int err, i;
7456
7457         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7458                 return 0;
7459
7460         fw_data = (void *)tp->fw->data;
7461
7462         /* Firmware blob starts with version numbers, followed by
7463            start address and length. We are setting complete length.
7464            length = end_address_of_bss - start_address_of_text.
7465            Remainder is the blob to be loaded contiguously
7466            from start address. */
7467
7468         info.fw_base = be32_to_cpu(fw_data[1]);
7469         cpu_scratch_size = tp->fw_len;
7470         info.fw_len = tp->fw->size - 12;
7471         info.fw_data = &fw_data[3];
7472
7473         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7474                 cpu_base = RX_CPU_BASE;
7475                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7476         } else {
7477                 cpu_base = TX_CPU_BASE;
7478                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7479                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7480         }
7481
7482         err = tg3_load_firmware_cpu(tp, cpu_base,
7483                                     cpu_scratch_base, cpu_scratch_size,
7484                                     &info);
7485         if (err)
7486                 return err;
7487
7488         /* Now startup the cpu. */
7489         tw32(cpu_base + CPU_STATE, 0xffffffff);
7490         tw32_f(cpu_base + CPU_PC, info.fw_base);
7491
7492         for (i = 0; i < 5; i++) {
7493                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7494                         break;
7495                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7496                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7497                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7498                 udelay(1000);
7499         }
7500         if (i >= 5) {
7501                 netdev_err(tp->dev,
7502                            "%s fails to set CPU PC, is %08x should be %08x\n",
7503                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7504                 return -ENODEV;
7505         }
7506         tw32(cpu_base + CPU_STATE, 0xffffffff);
7507         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7508         return 0;
7509 }
7510
7511
7512 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7513 {
7514         struct tg3 *tp = netdev_priv(dev);
7515         struct sockaddr *addr = p;
7516         int err = 0, skip_mac_1 = 0;
7517
7518         if (!is_valid_ether_addr(addr->sa_data))
7519                 return -EINVAL;
7520
7521         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7522
7523         if (!netif_running(dev))
7524                 return 0;
7525
7526         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7527                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7528
7529                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7530                 addr0_low = tr32(MAC_ADDR_0_LOW);
7531                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7532                 addr1_low = tr32(MAC_ADDR_1_LOW);
7533
7534                 /* Skip MAC addr 1 if ASF is using it. */
7535                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7536                     !(addr1_high == 0 && addr1_low == 0))
7537                         skip_mac_1 = 1;
7538         }
7539         spin_lock_bh(&tp->lock);
7540         __tg3_set_mac_addr(tp, skip_mac_1);
7541         spin_unlock_bh(&tp->lock);
7542
7543         return err;
7544 }
7545
7546 /* tp->lock is held. */
7547 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7548                            dma_addr_t mapping, u32 maxlen_flags,
7549                            u32 nic_addr)
7550 {
7551         tg3_write_mem(tp,
7552                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7553                       ((u64) mapping >> 32));
7554         tg3_write_mem(tp,
7555                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7556                       ((u64) mapping & 0xffffffff));
7557         tg3_write_mem(tp,
7558                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7559                        maxlen_flags);
7560
7561         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7562                 tg3_write_mem(tp,
7563                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7564                               nic_addr);
7565 }
7566
7567 static void __tg3_set_rx_mode(struct net_device *);
7568 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7569 {
7570         int i;
7571
7572         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7573                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7574                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7575                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7576         } else {
7577                 tw32(HOSTCC_TXCOL_TICKS, 0);
7578                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7579                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7580         }
7581
7582         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7583                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7584                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7585                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7586         } else {
7587                 tw32(HOSTCC_RXCOL_TICKS, 0);
7588                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7589                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7590         }
7591
7592         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7593                 u32 val = ec->stats_block_coalesce_usecs;
7594
7595                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7596                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7597
7598                 if (!netif_carrier_ok(tp->dev))
7599                         val = 0;
7600
7601                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7602         }
7603
7604         for (i = 0; i < tp->irq_cnt - 1; i++) {
7605                 u32 reg;
7606
7607                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7608                 tw32(reg, ec->rx_coalesce_usecs);
7609                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7610                 tw32(reg, ec->rx_max_coalesced_frames);
7611                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7612                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7613
7614                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7615                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7616                         tw32(reg, ec->tx_coalesce_usecs);
7617                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7618                         tw32(reg, ec->tx_max_coalesced_frames);
7619                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7620                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7621                 }
7622         }
7623
7624         for (; i < tp->irq_max - 1; i++) {
7625                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7626                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7627                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7628
7629                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7630                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7631                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7632                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7633                 }
7634         }
7635 }
7636
7637 /* tp->lock is held. */
7638 static void tg3_rings_reset(struct tg3 *tp)
7639 {
7640         int i;
7641         u32 stblk, txrcb, rxrcb, limit;
7642         struct tg3_napi *tnapi = &tp->napi[0];
7643
7644         /* Disable all transmit rings but the first. */
7645         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7646                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7647         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7648                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7649                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7650         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7651                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7652         else
7653                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7654
7655         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7656              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7657                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7658                               BDINFO_FLAGS_DISABLED);
7659
7660
7661         /* Disable all receive return rings but the first. */
7662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7663             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7664                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7665         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7666                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7667         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7668                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7669                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7670         else
7671                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7672
7673         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7674              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7675                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7676                               BDINFO_FLAGS_DISABLED);
7677
7678         /* Disable interrupts */
7679         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7680
7681         /* Zero mailbox registers. */
7682         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7683                 for (i = 1; i < tp->irq_max; i++) {
7684                         tp->napi[i].tx_prod = 0;
7685                         tp->napi[i].tx_cons = 0;
7686                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7687                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7688                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7689                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7690                 }
7691                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7692                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7693         } else {
7694                 tp->napi[0].tx_prod = 0;
7695                 tp->napi[0].tx_cons = 0;
7696                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7697                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7698         }
7699
7700         /* Make sure the NIC-based send BD rings are disabled. */
7701         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7702                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7703                 for (i = 0; i < 16; i++)
7704                         tw32_tx_mbox(mbox + i * 8, 0);
7705         }
7706
7707         txrcb = NIC_SRAM_SEND_RCB;
7708         rxrcb = NIC_SRAM_RCV_RET_RCB;
7709
7710         /* Clear status block in ram. */
7711         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7712
7713         /* Set status block DMA address */
7714         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7715              ((u64) tnapi->status_mapping >> 32));
7716         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7717              ((u64) tnapi->status_mapping & 0xffffffff));
7718
7719         if (tnapi->tx_ring) {
7720                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7721                                (TG3_TX_RING_SIZE <<
7722                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7723                                NIC_SRAM_TX_BUFFER_DESC);
7724                 txrcb += TG3_BDINFO_SIZE;
7725         }
7726
7727         if (tnapi->rx_rcb) {
7728                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7729                                (tp->rx_ret_ring_mask + 1) <<
7730                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7731                 rxrcb += TG3_BDINFO_SIZE;
7732         }
7733
7734         stblk = HOSTCC_STATBLCK_RING1;
7735
7736         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7737                 u64 mapping = (u64)tnapi->status_mapping;
7738                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7739                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7740
7741                 /* Clear status block in ram. */
7742                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7743
7744                 if (tnapi->tx_ring) {
7745                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7746                                        (TG3_TX_RING_SIZE <<
7747                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7748                                        NIC_SRAM_TX_BUFFER_DESC);
7749                         txrcb += TG3_BDINFO_SIZE;
7750                 }
7751
7752                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7753                                ((tp->rx_ret_ring_mask + 1) <<
7754                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7755
7756                 stblk += 8;
7757                 rxrcb += TG3_BDINFO_SIZE;
7758         }
7759 }
7760
7761 /* tp->lock is held. */
7762 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7763 {
7764         u32 val, rdmac_mode;
7765         int i, err, limit;
7766         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7767
7768         tg3_disable_ints(tp);
7769
7770         tg3_stop_fw(tp);
7771
7772         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7773
7774         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7775                 tg3_abort_hw(tp, 1);
7776
7777         /* Enable MAC control of LPI */
7778         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7779                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7780                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7781                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7782
7783                 tw32_f(TG3_CPMU_EEE_CTRL,
7784                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7785
7786                 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7787                       TG3_CPMU_EEEMD_LPI_IN_TX |
7788                       TG3_CPMU_EEEMD_LPI_IN_RX |
7789                       TG3_CPMU_EEEMD_EEE_ENABLE;
7790
7791                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7792                         val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7793
7794                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7795                         val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7796
7797                 tw32_f(TG3_CPMU_EEE_MODE, val);
7798
7799                 tw32_f(TG3_CPMU_EEE_DBTMR1,
7800                        TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7801                        TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7802
7803                 tw32_f(TG3_CPMU_EEE_DBTMR2,
7804                        TG3_CPMU_DBTMR1_APE_TX_2047US |
7805                        TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7806         }
7807
7808         if (reset_phy)
7809                 tg3_phy_reset(tp);
7810
7811         err = tg3_chip_reset(tp);
7812         if (err)
7813                 return err;
7814
7815         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7816
7817         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7818                 val = tr32(TG3_CPMU_CTRL);
7819                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7820                 tw32(TG3_CPMU_CTRL, val);
7821
7822                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7823                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7824                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7825                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7826
7827                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7828                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7829                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7830                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7831
7832                 val = tr32(TG3_CPMU_HST_ACC);
7833                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7834                 val |= CPMU_HST_ACC_MACCLK_6_25;
7835                 tw32(TG3_CPMU_HST_ACC, val);
7836         }
7837
7838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7839                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7840                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7841                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7842                 tw32(PCIE_PWR_MGMT_THRESH, val);
7843
7844                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7845                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7846
7847                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7848
7849                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7850                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7851         }
7852
7853         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7854                 u32 grc_mode = tr32(GRC_MODE);
7855
7856                 /* Access the lower 1K of PL PCIE block registers. */
7857                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7858                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7859
7860                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7861                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7862                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7863
7864                 tw32(GRC_MODE, grc_mode);
7865         }
7866
7867         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7868                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7869                         u32 grc_mode = tr32(GRC_MODE);
7870
7871                         /* Access the lower 1K of PL PCIE block registers. */
7872                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7873                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7874
7875                         val = tr32(TG3_PCIE_TLDLPL_PORT +
7876                                    TG3_PCIE_PL_LO_PHYCTL5);
7877                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7878                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7879
7880                         tw32(GRC_MODE, grc_mode);
7881                 }
7882
7883                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7884                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7885                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7886                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7887         }
7888
7889         /* This works around an issue with Athlon chipsets on
7890          * B3 tigon3 silicon.  This bit has no effect on any
7891          * other revision.  But do not set this on PCI Express
7892          * chips and don't even touch the clocks if the CPMU is present.
7893          */
7894         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7895                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7896                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7897                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7898         }
7899
7900         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7901             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7902                 val = tr32(TG3PCI_PCISTATE);
7903                 val |= PCISTATE_RETRY_SAME_DMA;
7904                 tw32(TG3PCI_PCISTATE, val);
7905         }
7906
7907         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7908                 /* Allow reads and writes to the
7909                  * APE register and memory space.
7910                  */
7911                 val = tr32(TG3PCI_PCISTATE);
7912                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7913                        PCISTATE_ALLOW_APE_SHMEM_WR |
7914                        PCISTATE_ALLOW_APE_PSPACE_WR;
7915                 tw32(TG3PCI_PCISTATE, val);
7916         }
7917
7918         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7919                 /* Enable some hw fixes.  */
7920                 val = tr32(TG3PCI_MSI_DATA);
7921                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7922                 tw32(TG3PCI_MSI_DATA, val);
7923         }
7924
7925         /* Descriptor ring init may make accesses to the
7926          * NIC SRAM area to setup the TX descriptors, so we
7927          * can only do this after the hardware has been
7928          * successfully reset.
7929          */
7930         err = tg3_init_rings(tp);
7931         if (err)
7932                 return err;
7933
7934         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7935                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7936                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7937                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7938                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7939                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7940         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7941                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7942                 /* This value is determined during the probe time DMA
7943                  * engine test, tg3_test_dma.
7944                  */
7945                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7946         }
7947
7948         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7949                           GRC_MODE_4X_NIC_SEND_RINGS |
7950                           GRC_MODE_NO_TX_PHDR_CSUM |
7951                           GRC_MODE_NO_RX_PHDR_CSUM);
7952         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7953
7954         /* Pseudo-header checksum is done by hardware logic and not
7955          * the offload processers, so make the chip do the pseudo-
7956          * header checksums on receive.  For transmit it is more
7957          * convenient to do the pseudo-header checksum in software
7958          * as Linux does that on transmit for us in all cases.
7959          */
7960         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7961
7962         tw32(GRC_MODE,
7963              tp->grc_mode |
7964              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7965
7966         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7967         val = tr32(GRC_MISC_CFG);
7968         val &= ~0xff;
7969         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7970         tw32(GRC_MISC_CFG, val);
7971
7972         /* Initialize MBUF/DESC pool. */
7973         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7974                 /* Do nothing.  */
7975         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7976                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7977                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7978                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7979                 else
7980                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7981                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7982                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7983         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7984                 int fw_len;
7985
7986                 fw_len = tp->fw_len;
7987                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7988                 tw32(BUFMGR_MB_POOL_ADDR,
7989                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7990                 tw32(BUFMGR_MB_POOL_SIZE,
7991                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7992         }
7993
7994         if (tp->dev->mtu <= ETH_DATA_LEN) {
7995                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7996                      tp->bufmgr_config.mbuf_read_dma_low_water);
7997                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7998                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7999                 tw32(BUFMGR_MB_HIGH_WATER,
8000                      tp->bufmgr_config.mbuf_high_water);
8001         } else {
8002                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8003                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8004                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8005                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8006                 tw32(BUFMGR_MB_HIGH_WATER,
8007                      tp->bufmgr_config.mbuf_high_water_jumbo);
8008         }
8009         tw32(BUFMGR_DMA_LOW_WATER,
8010              tp->bufmgr_config.dma_low_water);
8011         tw32(BUFMGR_DMA_HIGH_WATER,
8012              tp->bufmgr_config.dma_high_water);
8013
8014         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8016                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8017         tw32(BUFMGR_MODE, val);
8018         for (i = 0; i < 2000; i++) {
8019                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8020                         break;
8021                 udelay(10);
8022         }
8023         if (i >= 2000) {
8024                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8025                 return -ENODEV;
8026         }
8027
8028         /* Setup replenish threshold. */
8029         val = tp->rx_pending / 8;
8030         if (val == 0)
8031                 val = 1;
8032         else if (val > tp->rx_std_max_post)
8033                 val = tp->rx_std_max_post;
8034         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8035                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8036                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8037
8038                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8039                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8040         }
8041
8042         tw32(RCVBDI_STD_THRESH, val);
8043
8044         /* Initialize TG3_BDINFO's at:
8045          *  RCVDBDI_STD_BD:     standard eth size rx ring
8046          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8047          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8048          *
8049          * like so:
8050          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8051          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8052          *                              ring attribute flags
8053          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8054          *
8055          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8056          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8057          *
8058          * The size of each ring is fixed in the firmware, but the location is
8059          * configurable.
8060          */
8061         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8062              ((u64) tpr->rx_std_mapping >> 32));
8063         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8064              ((u64) tpr->rx_std_mapping & 0xffffffff));
8065         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8066             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8067                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8068                      NIC_SRAM_RX_BUFFER_DESC);
8069
8070         /* Disable the mini ring */
8071         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8072                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8073                      BDINFO_FLAGS_DISABLED);
8074
8075         /* Program the jumbo buffer descriptor ring control
8076          * blocks on those devices that have them.
8077          */
8078         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8079             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8080                 /* Setup replenish threshold. */
8081                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8082
8083                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8084                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8085                              ((u64) tpr->rx_jmb_mapping >> 32));
8086                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8087                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8088                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8089                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8090                              BDINFO_FLAGS_USE_EXT_RECV);
8091                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8092                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8093                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8094                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8095                 } else {
8096                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8097                              BDINFO_FLAGS_DISABLED);
8098                 }
8099
8100                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8101                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8102                                 val = RX_STD_MAX_SIZE_5705;
8103                         else
8104                                 val = RX_STD_MAX_SIZE_5717;
8105                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8106                         val |= (TG3_RX_STD_DMA_SZ << 2);
8107                 } else
8108                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8109         } else
8110                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8111
8112         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8113
8114         tpr->rx_std_prod_idx = tp->rx_pending;
8115         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8116
8117         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8118                           tp->rx_jumbo_pending : 0;
8119         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8120
8121         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8122                 tw32(STD_REPLENISH_LWM, 32);
8123                 tw32(JMB_REPLENISH_LWM, 16);
8124         }
8125
8126         tg3_rings_reset(tp);
8127
8128         /* Initialize MAC address and backoff seed. */
8129         __tg3_set_mac_addr(tp, 0);
8130
8131         /* MTU + ethernet header + FCS + optional VLAN tag */
8132         tw32(MAC_RX_MTU_SIZE,
8133              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8134
8135         /* The slot time is changed by tg3_setup_phy if we
8136          * run at gigabit with half duplex.
8137          */
8138         tw32(MAC_TX_LENGTHS,
8139              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8140              (6 << TX_LENGTHS_IPG_SHIFT) |
8141              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8142
8143         /* Receive rules. */
8144         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8145         tw32(RCVLPC_CONFIG, 0x0181);
8146
8147         /* Calculate RDMAC_MODE setting early, we need it to determine
8148          * the RCVLPC_STATE_ENABLE mask.
8149          */
8150         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8151                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8152                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8153                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8154                       RDMAC_MODE_LNGREAD_ENAB);
8155
8156         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8157                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8158
8159         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8160             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8162                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8163                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8164                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8165
8166         /* If statement applies to 5705 and 5750 PCI devices only */
8167         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8168              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8169             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8170                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8171                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8172                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8173                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8174                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8175                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8176                 }
8177         }
8178
8179         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8180                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8181
8182         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8183                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8184
8185         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8186             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8187             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8188                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8189
8190         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8191             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8192             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8193             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8194             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8195                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8196                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8197                         val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
8198                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
8199                 }
8200                 tw32(TG3_RDMA_RSRVCTRL_REG,
8201                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8202         }
8203
8204         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8205                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8206                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8207                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8208                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8209         }
8210
8211         /* Receive/send statistics. */
8212         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8213                 val = tr32(RCVLPC_STATS_ENABLE);
8214                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8215                 tw32(RCVLPC_STATS_ENABLE, val);
8216         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8217                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8218                 val = tr32(RCVLPC_STATS_ENABLE);
8219                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8220                 tw32(RCVLPC_STATS_ENABLE, val);
8221         } else {
8222                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8223         }
8224         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8225         tw32(SNDDATAI_STATSENAB, 0xffffff);
8226         tw32(SNDDATAI_STATSCTRL,
8227              (SNDDATAI_SCTRL_ENABLE |
8228               SNDDATAI_SCTRL_FASTUPD));
8229
8230         /* Setup host coalescing engine. */
8231         tw32(HOSTCC_MODE, 0);
8232         for (i = 0; i < 2000; i++) {
8233                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8234                         break;
8235                 udelay(10);
8236         }
8237
8238         __tg3_set_coalesce(tp, &tp->coal);
8239
8240         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8241                 /* Status/statistics block address.  See tg3_timer,
8242                  * the tg3_periodic_fetch_stats call there, and
8243                  * tg3_get_stats to see how this works for 5705/5750 chips.
8244                  */
8245                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8246                      ((u64) tp->stats_mapping >> 32));
8247                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8248                      ((u64) tp->stats_mapping & 0xffffffff));
8249                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8250
8251                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8252
8253                 /* Clear statistics and status block memory areas */
8254                 for (i = NIC_SRAM_STATS_BLK;
8255                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8256                      i += sizeof(u32)) {
8257                         tg3_write_mem(tp, i, 0);
8258                         udelay(40);
8259                 }
8260         }
8261
8262         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8263
8264         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8265         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8266         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8267                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8268
8269         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8270                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8271                 /* reset to prevent losing 1st rx packet intermittently */
8272                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8273                 udelay(10);
8274         }
8275
8276         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8277                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8278         else
8279                 tp->mac_mode = 0;
8280         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8281                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8282         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8283             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8284             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8285                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8286         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8287         udelay(40);
8288
8289         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8290          * If TG3_FLG2_IS_NIC is zero, we should read the
8291          * register to preserve the GPIO settings for LOMs. The GPIOs,
8292          * whether used as inputs or outputs, are set by boot code after
8293          * reset.
8294          */
8295         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8296                 u32 gpio_mask;
8297
8298                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8299                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8300                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8301
8302                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8303                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8304                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8305
8306                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8307                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8308
8309                 tp->grc_local_ctrl &= ~gpio_mask;
8310                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8311
8312                 /* GPIO1 must be driven high for eeprom write protect */
8313                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8314                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8315                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8316         }
8317         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8318         udelay(100);
8319
8320         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8321                 val = tr32(MSGINT_MODE);
8322                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8323                 tw32(MSGINT_MODE, val);
8324         }
8325
8326         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8327                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8328                 udelay(40);
8329         }
8330
8331         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8332                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8333                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8334                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8335                WDMAC_MODE_LNGREAD_ENAB);
8336
8337         /* If statement applies to 5705 and 5750 PCI devices only */
8338         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8339              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8340             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8341                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8342                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8343                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8344                         /* nothing */
8345                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8346                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8347                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8348                         val |= WDMAC_MODE_RX_ACCEL;
8349                 }
8350         }
8351
8352         /* Enable host coalescing bug fix */
8353         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8354                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8355
8356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8357                 val |= WDMAC_MODE_BURST_ALL_DATA;
8358
8359         tw32_f(WDMAC_MODE, val);
8360         udelay(40);
8361
8362         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8363                 u16 pcix_cmd;
8364
8365                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8366                                      &pcix_cmd);
8367                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8368                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8369                         pcix_cmd |= PCI_X_CMD_READ_2K;
8370                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8371                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8372                         pcix_cmd |= PCI_X_CMD_READ_2K;
8373                 }
8374                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8375                                       pcix_cmd);
8376         }
8377
8378         tw32_f(RDMAC_MODE, rdmac_mode);
8379         udelay(40);
8380
8381         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8382         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8383                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8384
8385         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8386                 tw32(SNDDATAC_MODE,
8387                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8388         else
8389                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8390
8391         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8392         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8393         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8395             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8396                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8397         tw32(RCVDBDI_MODE, val);
8398         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8399         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8400                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8401         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8402         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8403                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8404         tw32(SNDBDI_MODE, val);
8405         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8406
8407         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8408                 err = tg3_load_5701_a0_firmware_fix(tp);
8409                 if (err)
8410                         return err;
8411         }
8412
8413         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8414                 err = tg3_load_tso_firmware(tp);
8415                 if (err)
8416                         return err;
8417         }
8418
8419         tp->tx_mode = TX_MODE_ENABLE;
8420         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8421             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8422                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8423         tw32_f(MAC_TX_MODE, tp->tx_mode);
8424         udelay(100);
8425
8426         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8427                 u32 reg = MAC_RSS_INDIR_TBL_0;
8428                 u8 *ent = (u8 *)&val;
8429
8430                 /* Setup the indirection table */
8431                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8432                         int idx = i % sizeof(val);
8433
8434                         ent[idx] = i % (tp->irq_cnt - 1);
8435                         if (idx == sizeof(val) - 1) {
8436                                 tw32(reg, val);
8437                                 reg += 4;
8438                         }
8439                 }
8440
8441                 /* Setup the "secret" hash key. */
8442                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8443                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8444                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8445                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8446                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8447                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8448                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8449                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8450                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8451                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8452         }
8453
8454         tp->rx_mode = RX_MODE_ENABLE;
8455         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8456                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8457
8458         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8459                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8460                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8461                                RX_MODE_RSS_IPV6_HASH_EN |
8462                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8463                                RX_MODE_RSS_IPV4_HASH_EN |
8464                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8465
8466         tw32_f(MAC_RX_MODE, tp->rx_mode);
8467         udelay(10);
8468
8469         tw32(MAC_LED_CTRL, tp->led_ctrl);
8470
8471         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8472         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8473                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8474                 udelay(10);
8475         }
8476         tw32_f(MAC_RX_MODE, tp->rx_mode);
8477         udelay(10);
8478
8479         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8480                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8481                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8482                         /* Set drive transmission level to 1.2V  */
8483                         /* only if the signal pre-emphasis bit is not set  */
8484                         val = tr32(MAC_SERDES_CFG);
8485                         val &= 0xfffff000;
8486                         val |= 0x880;
8487                         tw32(MAC_SERDES_CFG, val);
8488                 }
8489                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8490                         tw32(MAC_SERDES_CFG, 0x616000);
8491         }
8492
8493         /* Prevent chip from dropping frames when flow control
8494          * is enabled.
8495          */
8496         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8497                 val = 1;
8498         else
8499                 val = 2;
8500         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8501
8502         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8503             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8504                 /* Use hardware link auto-negotiation */
8505                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8506         }
8507
8508         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8509             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8510                 u32 tmp;
8511
8512                 tmp = tr32(SERDES_RX_CTRL);
8513                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8514                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8515                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8516                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8517         }
8518
8519         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8520                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8521                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8522                         tp->link_config.speed = tp->link_config.orig_speed;
8523                         tp->link_config.duplex = tp->link_config.orig_duplex;
8524                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8525                 }
8526
8527                 err = tg3_setup_phy(tp, 0);
8528                 if (err)
8529                         return err;
8530
8531                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8532                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8533                         u32 tmp;
8534
8535                         /* Clear CRC stats. */
8536                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8537                                 tg3_writephy(tp, MII_TG3_TEST1,
8538                                              tmp | MII_TG3_TEST1_CRC_EN);
8539                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8540                         }
8541                 }
8542         }
8543
8544         __tg3_set_rx_mode(tp->dev);
8545
8546         /* Initialize receive rules. */
8547         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8548         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8549         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8550         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8551
8552         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8553             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8554                 limit = 8;
8555         else
8556                 limit = 16;
8557         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8558                 limit -= 4;
8559         switch (limit) {
8560         case 16:
8561                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8562         case 15:
8563                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8564         case 14:
8565                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8566         case 13:
8567                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8568         case 12:
8569                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8570         case 11:
8571                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8572         case 10:
8573                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8574         case 9:
8575                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8576         case 8:
8577                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8578         case 7:
8579                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8580         case 6:
8581                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8582         case 5:
8583                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8584         case 4:
8585                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8586         case 3:
8587                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8588         case 2:
8589         case 1:
8590
8591         default:
8592                 break;
8593         }
8594
8595         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8596                 /* Write our heartbeat update interval to APE. */
8597                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8598                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8599
8600         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8601
8602         return 0;
8603 }
8604
8605 /* Called at device open time to get the chip ready for
8606  * packet processing.  Invoked with tp->lock held.
8607  */
8608 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8609 {
8610         tg3_switch_clocks(tp);
8611
8612         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8613
8614         return tg3_reset_hw(tp, reset_phy);
8615 }
8616
8617 #define TG3_STAT_ADD32(PSTAT, REG) \
8618 do {    u32 __val = tr32(REG); \
8619         (PSTAT)->low += __val; \
8620         if ((PSTAT)->low < __val) \
8621                 (PSTAT)->high += 1; \
8622 } while (0)
8623
8624 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8625 {
8626         struct tg3_hw_stats *sp = tp->hw_stats;
8627
8628         if (!netif_carrier_ok(tp->dev))
8629                 return;
8630
8631         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8632         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8633         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8634         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8635         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8636         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8637         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8638         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8639         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8640         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8641         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8642         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8643         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8644
8645         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8646         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8647         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8648         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8649         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8650         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8651         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8652         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8653         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8654         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8655         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8656         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8657         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8658         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8659
8660         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8661         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8662         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8663 }
8664
8665 static void tg3_timer(unsigned long __opaque)
8666 {
8667         struct tg3 *tp = (struct tg3 *) __opaque;
8668
8669         if (tp->irq_sync)
8670                 goto restart_timer;
8671
8672         spin_lock(&tp->lock);
8673
8674         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8675                 /* All of this garbage is because when using non-tagged
8676                  * IRQ status the mailbox/status_block protocol the chip
8677                  * uses with the cpu is race prone.
8678                  */
8679                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8680                         tw32(GRC_LOCAL_CTRL,
8681                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8682                 } else {
8683                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8684                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8685                 }
8686
8687                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8688                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8689                         spin_unlock(&tp->lock);
8690                         schedule_work(&tp->reset_task);
8691                         return;
8692                 }
8693         }
8694
8695         /* This part only runs once per second. */
8696         if (!--tp->timer_counter) {
8697                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8698                         tg3_periodic_fetch_stats(tp);
8699
8700                 if (tp->setlpicnt && !--tp->setlpicnt) {
8701                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8702                         tw32(TG3_CPMU_EEE_MODE,
8703                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8704                 }
8705
8706                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8707                         u32 mac_stat;
8708                         int phy_event;
8709
8710                         mac_stat = tr32(MAC_STATUS);
8711
8712                         phy_event = 0;
8713                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8714                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8715                                         phy_event = 1;
8716                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8717                                 phy_event = 1;
8718
8719                         if (phy_event)
8720                                 tg3_setup_phy(tp, 0);
8721                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8722                         u32 mac_stat = tr32(MAC_STATUS);
8723                         int need_setup = 0;
8724
8725                         if (netif_carrier_ok(tp->dev) &&
8726                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8727                                 need_setup = 1;
8728                         }
8729                         if (!netif_carrier_ok(tp->dev) &&
8730                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8731                                          MAC_STATUS_SIGNAL_DET))) {
8732                                 need_setup = 1;
8733                         }
8734                         if (need_setup) {
8735                                 if (!tp->serdes_counter) {
8736                                         tw32_f(MAC_MODE,
8737                                              (tp->mac_mode &
8738                                               ~MAC_MODE_PORT_MODE_MASK));
8739                                         udelay(40);
8740                                         tw32_f(MAC_MODE, tp->mac_mode);
8741                                         udelay(40);
8742                                 }
8743                                 tg3_setup_phy(tp, 0);
8744                         }
8745                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8746                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8747                         tg3_serdes_parallel_detect(tp);
8748                 }
8749
8750                 tp->timer_counter = tp->timer_multiplier;
8751         }
8752
8753         /* Heartbeat is only sent once every 2 seconds.
8754          *
8755          * The heartbeat is to tell the ASF firmware that the host
8756          * driver is still alive.  In the event that the OS crashes,
8757          * ASF needs to reset the hardware to free up the FIFO space
8758          * that may be filled with rx packets destined for the host.
8759          * If the FIFO is full, ASF will no longer function properly.
8760          *
8761          * Unintended resets have been reported on real time kernels
8762          * where the timer doesn't run on time.  Netpoll will also have
8763          * same problem.
8764          *
8765          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8766          * to check the ring condition when the heartbeat is expiring
8767          * before doing the reset.  This will prevent most unintended
8768          * resets.
8769          */
8770         if (!--tp->asf_counter) {
8771                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8772                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8773                         tg3_wait_for_event_ack(tp);
8774
8775                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8776                                       FWCMD_NICDRV_ALIVE3);
8777                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8778                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8779                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8780
8781                         tg3_generate_fw_event(tp);
8782                 }
8783                 tp->asf_counter = tp->asf_multiplier;
8784         }
8785
8786         spin_unlock(&tp->lock);
8787
8788 restart_timer:
8789         tp->timer.expires = jiffies + tp->timer_offset;
8790         add_timer(&tp->timer);
8791 }
8792
8793 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8794 {
8795         irq_handler_t fn;
8796         unsigned long flags;
8797         char *name;
8798         struct tg3_napi *tnapi = &tp->napi[irq_num];
8799
8800         if (tp->irq_cnt == 1)
8801                 name = tp->dev->name;
8802         else {
8803                 name = &tnapi->irq_lbl[0];
8804                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8805                 name[IFNAMSIZ-1] = 0;
8806         }
8807
8808         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8809                 fn = tg3_msi;
8810                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8811                         fn = tg3_msi_1shot;
8812                 flags = IRQF_SAMPLE_RANDOM;
8813         } else {
8814                 fn = tg3_interrupt;
8815                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8816                         fn = tg3_interrupt_tagged;
8817                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8818         }
8819
8820         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8821 }
8822
8823 static int tg3_test_interrupt(struct tg3 *tp)
8824 {
8825         struct tg3_napi *tnapi = &tp->napi[0];
8826         struct net_device *dev = tp->dev;
8827         int err, i, intr_ok = 0;
8828         u32 val;
8829
8830         if (!netif_running(dev))
8831                 return -ENODEV;
8832
8833         tg3_disable_ints(tp);
8834
8835         free_irq(tnapi->irq_vec, tnapi);
8836
8837         /*
8838          * Turn off MSI one shot mode.  Otherwise this test has no
8839          * observable way to know whether the interrupt was delivered.
8840          */
8841         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8842             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8843                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8844                 tw32(MSGINT_MODE, val);
8845         }
8846
8847         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8848                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8849         if (err)
8850                 return err;
8851
8852         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8853         tg3_enable_ints(tp);
8854
8855         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8856                tnapi->coal_now);
8857
8858         for (i = 0; i < 5; i++) {
8859                 u32 int_mbox, misc_host_ctrl;
8860
8861                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8862                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8863
8864                 if ((int_mbox != 0) ||
8865                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8866                         intr_ok = 1;
8867                         break;
8868                 }
8869
8870                 msleep(10);
8871         }
8872
8873         tg3_disable_ints(tp);
8874
8875         free_irq(tnapi->irq_vec, tnapi);
8876
8877         err = tg3_request_irq(tp, 0);
8878
8879         if (err)
8880                 return err;
8881
8882         if (intr_ok) {
8883                 /* Reenable MSI one shot mode. */
8884                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8885                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8886                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8887                         tw32(MSGINT_MODE, val);
8888                 }
8889                 return 0;
8890         }
8891
8892         return -EIO;
8893 }
8894
8895 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8896  * successfully restored
8897  */
8898 static int tg3_test_msi(struct tg3 *tp)
8899 {
8900         int err;
8901         u16 pci_cmd;
8902
8903         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8904                 return 0;
8905
8906         /* Turn off SERR reporting in case MSI terminates with Master
8907          * Abort.
8908          */
8909         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8910         pci_write_config_word(tp->pdev, PCI_COMMAND,
8911                               pci_cmd & ~PCI_COMMAND_SERR);
8912
8913         err = tg3_test_interrupt(tp);
8914
8915         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8916
8917         if (!err)
8918                 return 0;
8919
8920         /* other failures */
8921         if (err != -EIO)
8922                 return err;
8923
8924         /* MSI test failed, go back to INTx mode */
8925         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8926                     "to INTx mode. Please report this failure to the PCI "
8927                     "maintainer and include system chipset information\n");
8928
8929         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8930
8931         pci_disable_msi(tp->pdev);
8932
8933         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8934         tp->napi[0].irq_vec = tp->pdev->irq;
8935
8936         err = tg3_request_irq(tp, 0);
8937         if (err)
8938                 return err;
8939
8940         /* Need to reset the chip because the MSI cycle may have terminated
8941          * with Master Abort.
8942          */
8943         tg3_full_lock(tp, 1);
8944
8945         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8946         err = tg3_init_hw(tp, 1);
8947
8948         tg3_full_unlock(tp);
8949
8950         if (err)
8951                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8952
8953         return err;
8954 }
8955
8956 static int tg3_request_firmware(struct tg3 *tp)
8957 {
8958         const __be32 *fw_data;
8959
8960         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8961                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8962                            tp->fw_needed);
8963                 return -ENOENT;
8964         }
8965
8966         fw_data = (void *)tp->fw->data;
8967
8968         /* Firmware blob starts with version numbers, followed by
8969          * start address and _full_ length including BSS sections
8970          * (which must be longer than the actual data, of course
8971          */
8972
8973         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8974         if (tp->fw_len < (tp->fw->size - 12)) {
8975                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8976                            tp->fw_len, tp->fw_needed);
8977                 release_firmware(tp->fw);
8978                 tp->fw = NULL;
8979                 return -EINVAL;
8980         }
8981
8982         /* We no longer need firmware; we have it. */
8983         tp->fw_needed = NULL;
8984         return 0;
8985 }
8986
8987 static bool tg3_enable_msix(struct tg3 *tp)
8988 {
8989         int i, rc, cpus = num_online_cpus();
8990         struct msix_entry msix_ent[tp->irq_max];
8991
8992         if (cpus == 1)
8993                 /* Just fallback to the simpler MSI mode. */
8994                 return false;
8995
8996         /*
8997          * We want as many rx rings enabled as there are cpus.
8998          * The first MSIX vector only deals with link interrupts, etc,
8999          * so we add one to the number of vectors we are requesting.
9000          */
9001         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9002
9003         for (i = 0; i < tp->irq_max; i++) {
9004                 msix_ent[i].entry  = i;
9005                 msix_ent[i].vector = 0;
9006         }
9007
9008         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9009         if (rc < 0) {
9010                 return false;
9011         } else if (rc != 0) {
9012                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9013                         return false;
9014                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9015                               tp->irq_cnt, rc);
9016                 tp->irq_cnt = rc;
9017         }
9018
9019         for (i = 0; i < tp->irq_max; i++)
9020                 tp->napi[i].irq_vec = msix_ent[i].vector;
9021
9022         netif_set_real_num_tx_queues(tp->dev, 1);
9023         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9024         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9025                 pci_disable_msix(tp->pdev);
9026                 return false;
9027         }
9028
9029         if (tp->irq_cnt > 1) {
9030                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9031                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9032                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9033                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9034                 }
9035         }
9036
9037         return true;
9038 }
9039
9040 static void tg3_ints_init(struct tg3 *tp)
9041 {
9042         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9043             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9044                 /* All MSI supporting chips should support tagged
9045                  * status.  Assert that this is the case.
9046                  */
9047                 netdev_warn(tp->dev,
9048                             "MSI without TAGGED_STATUS? Not using MSI\n");
9049                 goto defcfg;
9050         }
9051
9052         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9053                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9054         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9055                  pci_enable_msi(tp->pdev) == 0)
9056                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9057
9058         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9059                 u32 msi_mode = tr32(MSGINT_MODE);
9060                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9061                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9062                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9063         }
9064 defcfg:
9065         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9066                 tp->irq_cnt = 1;
9067                 tp->napi[0].irq_vec = tp->pdev->irq;
9068                 netif_set_real_num_tx_queues(tp->dev, 1);
9069                 netif_set_real_num_rx_queues(tp->dev, 1);
9070         }
9071 }
9072
9073 static void tg3_ints_fini(struct tg3 *tp)
9074 {
9075         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9076                 pci_disable_msix(tp->pdev);
9077         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9078                 pci_disable_msi(tp->pdev);
9079         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9080         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9081 }
9082
9083 static int tg3_open(struct net_device *dev)
9084 {
9085         struct tg3 *tp = netdev_priv(dev);
9086         int i, err;
9087
9088         if (tp->fw_needed) {
9089                 err = tg3_request_firmware(tp);
9090                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9091                         if (err)
9092                                 return err;
9093                 } else if (err) {
9094                         netdev_warn(tp->dev, "TSO capability disabled\n");
9095                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9096                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9097                         netdev_notice(tp->dev, "TSO capability restored\n");
9098                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9099                 }
9100         }
9101
9102         netif_carrier_off(tp->dev);
9103
9104         err = tg3_power_up(tp);
9105         if (err)
9106                 return err;
9107
9108         tg3_full_lock(tp, 0);
9109
9110         tg3_disable_ints(tp);
9111         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9112
9113         tg3_full_unlock(tp);
9114
9115         /*
9116          * Setup interrupts first so we know how
9117          * many NAPI resources to allocate
9118          */
9119         tg3_ints_init(tp);
9120
9121         /* The placement of this call is tied
9122          * to the setup and use of Host TX descriptors.
9123          */
9124         err = tg3_alloc_consistent(tp);
9125         if (err)
9126                 goto err_out1;
9127
9128         tg3_napi_init(tp);
9129
9130         tg3_napi_enable(tp);
9131
9132         for (i = 0; i < tp->irq_cnt; i++) {
9133                 struct tg3_napi *tnapi = &tp->napi[i];
9134                 err = tg3_request_irq(tp, i);
9135                 if (err) {
9136                         for (i--; i >= 0; i--)
9137                                 free_irq(tnapi->irq_vec, tnapi);
9138                         break;
9139                 }
9140         }
9141
9142         if (err)
9143                 goto err_out2;
9144
9145         tg3_full_lock(tp, 0);
9146
9147         err = tg3_init_hw(tp, 1);
9148         if (err) {
9149                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9150                 tg3_free_rings(tp);
9151         } else {
9152                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9153                         tp->timer_offset = HZ;
9154                 else
9155                         tp->timer_offset = HZ / 10;
9156
9157                 BUG_ON(tp->timer_offset > HZ);
9158                 tp->timer_counter = tp->timer_multiplier =
9159                         (HZ / tp->timer_offset);
9160                 tp->asf_counter = tp->asf_multiplier =
9161                         ((HZ / tp->timer_offset) * 2);
9162
9163                 init_timer(&tp->timer);
9164                 tp->timer.expires = jiffies + tp->timer_offset;
9165                 tp->timer.data = (unsigned long) tp;
9166                 tp->timer.function = tg3_timer;
9167         }
9168
9169         tg3_full_unlock(tp);
9170
9171         if (err)
9172                 goto err_out3;
9173
9174         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9175                 err = tg3_test_msi(tp);
9176
9177                 if (err) {
9178                         tg3_full_lock(tp, 0);
9179                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9180                         tg3_free_rings(tp);
9181                         tg3_full_unlock(tp);
9182
9183                         goto err_out2;
9184                 }
9185
9186                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9187                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9188                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9189
9190                         tw32(PCIE_TRANSACTION_CFG,
9191                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9192                 }
9193         }
9194
9195         tg3_phy_start(tp);
9196
9197         tg3_full_lock(tp, 0);
9198
9199         add_timer(&tp->timer);
9200         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9201         tg3_enable_ints(tp);
9202
9203         tg3_full_unlock(tp);
9204
9205         netif_tx_start_all_queues(dev);
9206
9207         return 0;
9208
9209 err_out3:
9210         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9211                 struct tg3_napi *tnapi = &tp->napi[i];
9212                 free_irq(tnapi->irq_vec, tnapi);
9213         }
9214
9215 err_out2:
9216         tg3_napi_disable(tp);
9217         tg3_napi_fini(tp);
9218         tg3_free_consistent(tp);
9219
9220 err_out1:
9221         tg3_ints_fini(tp);
9222         return err;
9223 }
9224
9225 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9226                                                  struct rtnl_link_stats64 *);
9227 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9228
9229 static int tg3_close(struct net_device *dev)
9230 {
9231         int i;
9232         struct tg3 *tp = netdev_priv(dev);
9233
9234         tg3_napi_disable(tp);
9235         cancel_work_sync(&tp->reset_task);
9236
9237         netif_tx_stop_all_queues(dev);
9238
9239         del_timer_sync(&tp->timer);
9240
9241         tg3_phy_stop(tp);
9242
9243         tg3_full_lock(tp, 1);
9244
9245         tg3_disable_ints(tp);
9246
9247         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9248         tg3_free_rings(tp);
9249         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9250
9251         tg3_full_unlock(tp);
9252
9253         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9254                 struct tg3_napi *tnapi = &tp->napi[i];
9255                 free_irq(tnapi->irq_vec, tnapi);
9256         }
9257
9258         tg3_ints_fini(tp);
9259
9260         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9261
9262         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9263                sizeof(tp->estats_prev));
9264
9265         tg3_napi_fini(tp);
9266
9267         tg3_free_consistent(tp);
9268
9269         tg3_power_down(tp);
9270
9271         netif_carrier_off(tp->dev);
9272
9273         return 0;
9274 }
9275
9276 static inline u64 get_stat64(tg3_stat64_t *val)
9277 {
9278        return ((u64)val->high << 32) | ((u64)val->low);
9279 }
9280
9281 static u64 calc_crc_errors(struct tg3 *tp)
9282 {
9283         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9284
9285         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9286             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9287              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9288                 u32 val;
9289
9290                 spin_lock_bh(&tp->lock);
9291                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9292                         tg3_writephy(tp, MII_TG3_TEST1,
9293                                      val | MII_TG3_TEST1_CRC_EN);
9294                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9295                 } else
9296                         val = 0;
9297                 spin_unlock_bh(&tp->lock);
9298
9299                 tp->phy_crc_errors += val;
9300
9301                 return tp->phy_crc_errors;
9302         }
9303
9304         return get_stat64(&hw_stats->rx_fcs_errors);
9305 }
9306
9307 #define ESTAT_ADD(member) \
9308         estats->member =        old_estats->member + \
9309                                 get_stat64(&hw_stats->member)
9310
9311 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9312 {
9313         struct tg3_ethtool_stats *estats = &tp->estats;
9314         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9315         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9316
9317         if (!hw_stats)
9318                 return old_estats;
9319
9320         ESTAT_ADD(rx_octets);
9321         ESTAT_ADD(rx_fragments);
9322         ESTAT_ADD(rx_ucast_packets);
9323         ESTAT_ADD(rx_mcast_packets);
9324         ESTAT_ADD(rx_bcast_packets);
9325         ESTAT_ADD(rx_fcs_errors);
9326         ESTAT_ADD(rx_align_errors);
9327         ESTAT_ADD(rx_xon_pause_rcvd);
9328         ESTAT_ADD(rx_xoff_pause_rcvd);
9329         ESTAT_ADD(rx_mac_ctrl_rcvd);
9330         ESTAT_ADD(rx_xoff_entered);
9331         ESTAT_ADD(rx_frame_too_long_errors);
9332         ESTAT_ADD(rx_jabbers);
9333         ESTAT_ADD(rx_undersize_packets);
9334         ESTAT_ADD(rx_in_length_errors);
9335         ESTAT_ADD(rx_out_length_errors);
9336         ESTAT_ADD(rx_64_or_less_octet_packets);
9337         ESTAT_ADD(rx_65_to_127_octet_packets);
9338         ESTAT_ADD(rx_128_to_255_octet_packets);
9339         ESTAT_ADD(rx_256_to_511_octet_packets);
9340         ESTAT_ADD(rx_512_to_1023_octet_packets);
9341         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9342         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9343         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9344         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9345         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9346
9347         ESTAT_ADD(tx_octets);
9348         ESTAT_ADD(tx_collisions);
9349         ESTAT_ADD(tx_xon_sent);
9350         ESTAT_ADD(tx_xoff_sent);
9351         ESTAT_ADD(tx_flow_control);
9352         ESTAT_ADD(tx_mac_errors);
9353         ESTAT_ADD(tx_single_collisions);
9354         ESTAT_ADD(tx_mult_collisions);
9355         ESTAT_ADD(tx_deferred);
9356         ESTAT_ADD(tx_excessive_collisions);
9357         ESTAT_ADD(tx_late_collisions);
9358         ESTAT_ADD(tx_collide_2times);
9359         ESTAT_ADD(tx_collide_3times);
9360         ESTAT_ADD(tx_collide_4times);
9361         ESTAT_ADD(tx_collide_5times);
9362         ESTAT_ADD(tx_collide_6times);
9363         ESTAT_ADD(tx_collide_7times);
9364         ESTAT_ADD(tx_collide_8times);
9365         ESTAT_ADD(tx_collide_9times);
9366         ESTAT_ADD(tx_collide_10times);
9367         ESTAT_ADD(tx_collide_11times);
9368         ESTAT_ADD(tx_collide_12times);
9369         ESTAT_ADD(tx_collide_13times);
9370         ESTAT_ADD(tx_collide_14times);
9371         ESTAT_ADD(tx_collide_15times);
9372         ESTAT_ADD(tx_ucast_packets);
9373         ESTAT_ADD(tx_mcast_packets);
9374         ESTAT_ADD(tx_bcast_packets);
9375         ESTAT_ADD(tx_carrier_sense_errors);
9376         ESTAT_ADD(tx_discards);
9377         ESTAT_ADD(tx_errors);
9378
9379         ESTAT_ADD(dma_writeq_full);
9380         ESTAT_ADD(dma_write_prioq_full);
9381         ESTAT_ADD(rxbds_empty);
9382         ESTAT_ADD(rx_discards);
9383         ESTAT_ADD(rx_errors);
9384         ESTAT_ADD(rx_threshold_hit);
9385
9386         ESTAT_ADD(dma_readq_full);
9387         ESTAT_ADD(dma_read_prioq_full);
9388         ESTAT_ADD(tx_comp_queue_full);
9389
9390         ESTAT_ADD(ring_set_send_prod_index);
9391         ESTAT_ADD(ring_status_update);
9392         ESTAT_ADD(nic_irqs);
9393         ESTAT_ADD(nic_avoided_irqs);
9394         ESTAT_ADD(nic_tx_threshold_hit);
9395
9396         return estats;
9397 }
9398
9399 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9400                                                  struct rtnl_link_stats64 *stats)
9401 {
9402         struct tg3 *tp = netdev_priv(dev);
9403         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9404         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9405
9406         if (!hw_stats)
9407                 return old_stats;
9408
9409         stats->rx_packets = old_stats->rx_packets +
9410                 get_stat64(&hw_stats->rx_ucast_packets) +
9411                 get_stat64(&hw_stats->rx_mcast_packets) +
9412                 get_stat64(&hw_stats->rx_bcast_packets);
9413
9414         stats->tx_packets = old_stats->tx_packets +
9415                 get_stat64(&hw_stats->tx_ucast_packets) +
9416                 get_stat64(&hw_stats->tx_mcast_packets) +
9417                 get_stat64(&hw_stats->tx_bcast_packets);
9418
9419         stats->rx_bytes = old_stats->rx_bytes +
9420                 get_stat64(&hw_stats->rx_octets);
9421         stats->tx_bytes = old_stats->tx_bytes +
9422                 get_stat64(&hw_stats->tx_octets);
9423
9424         stats->rx_errors = old_stats->rx_errors +
9425                 get_stat64(&hw_stats->rx_errors);
9426         stats->tx_errors = old_stats->tx_errors +
9427                 get_stat64(&hw_stats->tx_errors) +
9428                 get_stat64(&hw_stats->tx_mac_errors) +
9429                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9430                 get_stat64(&hw_stats->tx_discards);
9431
9432         stats->multicast = old_stats->multicast +
9433                 get_stat64(&hw_stats->rx_mcast_packets);
9434         stats->collisions = old_stats->collisions +
9435                 get_stat64(&hw_stats->tx_collisions);
9436
9437         stats->rx_length_errors = old_stats->rx_length_errors +
9438                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9439                 get_stat64(&hw_stats->rx_undersize_packets);
9440
9441         stats->rx_over_errors = old_stats->rx_over_errors +
9442                 get_stat64(&hw_stats->rxbds_empty);
9443         stats->rx_frame_errors = old_stats->rx_frame_errors +
9444                 get_stat64(&hw_stats->rx_align_errors);
9445         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9446                 get_stat64(&hw_stats->tx_discards);
9447         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9448                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9449
9450         stats->rx_crc_errors = old_stats->rx_crc_errors +
9451                 calc_crc_errors(tp);
9452
9453         stats->rx_missed_errors = old_stats->rx_missed_errors +
9454                 get_stat64(&hw_stats->rx_discards);
9455
9456         stats->rx_dropped = tp->rx_dropped;
9457
9458         return stats;
9459 }
9460
9461 static inline u32 calc_crc(unsigned char *buf, int len)
9462 {
9463         u32 reg;
9464         u32 tmp;
9465         int j, k;
9466
9467         reg = 0xffffffff;
9468
9469         for (j = 0; j < len; j++) {
9470                 reg ^= buf[j];
9471
9472                 for (k = 0; k < 8; k++) {
9473                         tmp = reg & 0x01;
9474
9475                         reg >>= 1;
9476
9477                         if (tmp)
9478                                 reg ^= 0xedb88320;
9479                 }
9480         }
9481
9482         return ~reg;
9483 }
9484
9485 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9486 {
9487         /* accept or reject all multicast frames */
9488         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9489         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9490         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9491         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9492 }
9493
9494 static void __tg3_set_rx_mode(struct net_device *dev)
9495 {
9496         struct tg3 *tp = netdev_priv(dev);
9497         u32 rx_mode;
9498
9499         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9500                                   RX_MODE_KEEP_VLAN_TAG);
9501
9502 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9503         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9504          * flag clear.
9505          */
9506         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9507                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9508 #endif
9509
9510         if (dev->flags & IFF_PROMISC) {
9511                 /* Promiscuous mode. */
9512                 rx_mode |= RX_MODE_PROMISC;
9513         } else if (dev->flags & IFF_ALLMULTI) {
9514                 /* Accept all multicast. */
9515                 tg3_set_multi(tp, 1);
9516         } else if (netdev_mc_empty(dev)) {
9517                 /* Reject all multicast. */
9518                 tg3_set_multi(tp, 0);
9519         } else {
9520                 /* Accept one or more multicast(s). */
9521                 struct netdev_hw_addr *ha;
9522                 u32 mc_filter[4] = { 0, };
9523                 u32 regidx;
9524                 u32 bit;
9525                 u32 crc;
9526
9527                 netdev_for_each_mc_addr(ha, dev) {
9528                         crc = calc_crc(ha->addr, ETH_ALEN);
9529                         bit = ~crc & 0x7f;
9530                         regidx = (bit & 0x60) >> 5;
9531                         bit &= 0x1f;
9532                         mc_filter[regidx] |= (1 << bit);
9533                 }
9534
9535                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9536                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9537                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9538                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9539         }
9540
9541         if (rx_mode != tp->rx_mode) {
9542                 tp->rx_mode = rx_mode;
9543                 tw32_f(MAC_RX_MODE, rx_mode);
9544                 udelay(10);
9545         }
9546 }
9547
9548 static void tg3_set_rx_mode(struct net_device *dev)
9549 {
9550         struct tg3 *tp = netdev_priv(dev);
9551
9552         if (!netif_running(dev))
9553                 return;
9554
9555         tg3_full_lock(tp, 0);
9556         __tg3_set_rx_mode(dev);
9557         tg3_full_unlock(tp);
9558 }
9559
9560 #define TG3_REGDUMP_LEN         (32 * 1024)
9561
9562 static int tg3_get_regs_len(struct net_device *dev)
9563 {
9564         return TG3_REGDUMP_LEN;
9565 }
9566
9567 static void tg3_get_regs(struct net_device *dev,
9568                 struct ethtool_regs *regs, void *_p)
9569 {
9570         u32 *p = _p;
9571         struct tg3 *tp = netdev_priv(dev);
9572         u8 *orig_p = _p;
9573         int i;
9574
9575         regs->version = 0;
9576
9577         memset(p, 0, TG3_REGDUMP_LEN);
9578
9579         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9580                 return;
9581
9582         tg3_full_lock(tp, 0);
9583
9584 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9585 #define GET_REG32_LOOP(base, len)               \
9586 do {    p = (u32 *)(orig_p + (base));           \
9587         for (i = 0; i < len; i += 4)            \
9588                 __GET_REG32((base) + i);        \
9589 } while (0)
9590 #define GET_REG32_1(reg)                        \
9591 do {    p = (u32 *)(orig_p + (reg));            \
9592         __GET_REG32((reg));                     \
9593 } while (0)
9594
9595         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9596         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9597         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9598         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9599         GET_REG32_1(SNDDATAC_MODE);
9600         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9601         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9602         GET_REG32_1(SNDBDC_MODE);
9603         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9604         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9605         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9606         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9607         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9608         GET_REG32_1(RCVDCC_MODE);
9609         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9610         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9611         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9612         GET_REG32_1(MBFREE_MODE);
9613         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9614         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9615         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9616         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9617         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9618         GET_REG32_1(RX_CPU_MODE);
9619         GET_REG32_1(RX_CPU_STATE);
9620         GET_REG32_1(RX_CPU_PGMCTR);
9621         GET_REG32_1(RX_CPU_HWBKPT);
9622         GET_REG32_1(TX_CPU_MODE);
9623         GET_REG32_1(TX_CPU_STATE);
9624         GET_REG32_1(TX_CPU_PGMCTR);
9625         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9626         GET_REG32_LOOP(FTQ_RESET, 0x120);
9627         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9628         GET_REG32_1(DMAC_MODE);
9629         GET_REG32_LOOP(GRC_MODE, 0x4c);
9630         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9631                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9632
9633 #undef __GET_REG32
9634 #undef GET_REG32_LOOP
9635 #undef GET_REG32_1
9636
9637         tg3_full_unlock(tp);
9638 }
9639
9640 static int tg3_get_eeprom_len(struct net_device *dev)
9641 {
9642         struct tg3 *tp = netdev_priv(dev);
9643
9644         return tp->nvram_size;
9645 }
9646
9647 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9648 {
9649         struct tg3 *tp = netdev_priv(dev);
9650         int ret;
9651         u8  *pd;
9652         u32 i, offset, len, b_offset, b_count;
9653         __be32 val;
9654
9655         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9656                 return -EINVAL;
9657
9658         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9659                 return -EAGAIN;
9660
9661         offset = eeprom->offset;
9662         len = eeprom->len;
9663         eeprom->len = 0;
9664
9665         eeprom->magic = TG3_EEPROM_MAGIC;
9666
9667         if (offset & 3) {
9668                 /* adjustments to start on required 4 byte boundary */
9669                 b_offset = offset & 3;
9670                 b_count = 4 - b_offset;
9671                 if (b_count > len) {
9672                         /* i.e. offset=1 len=2 */
9673                         b_count = len;
9674                 }
9675                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9676                 if (ret)
9677                         return ret;
9678                 memcpy(data, ((char *)&val) + b_offset, b_count);
9679                 len -= b_count;
9680                 offset += b_count;
9681                 eeprom->len += b_count;
9682         }
9683
9684         /* read bytes upto the last 4 byte boundary */
9685         pd = &data[eeprom->len];
9686         for (i = 0; i < (len - (len & 3)); i += 4) {
9687                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9688                 if (ret) {
9689                         eeprom->len += i;
9690                         return ret;
9691                 }
9692                 memcpy(pd + i, &val, 4);
9693         }
9694         eeprom->len += i;
9695
9696         if (len & 3) {
9697                 /* read last bytes not ending on 4 byte boundary */
9698                 pd = &data[eeprom->len];
9699                 b_count = len & 3;
9700                 b_offset = offset + len - b_count;
9701                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9702                 if (ret)
9703                         return ret;
9704                 memcpy(pd, &val, b_count);
9705                 eeprom->len += b_count;
9706         }
9707         return 0;
9708 }
9709
9710 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9711
9712 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9713 {
9714         struct tg3 *tp = netdev_priv(dev);
9715         int ret;
9716         u32 offset, len, b_offset, odd_len;
9717         u8 *buf;
9718         __be32 start, end;
9719
9720         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9721                 return -EAGAIN;
9722
9723         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9724             eeprom->magic != TG3_EEPROM_MAGIC)
9725                 return -EINVAL;
9726
9727         offset = eeprom->offset;
9728         len = eeprom->len;
9729
9730         if ((b_offset = (offset & 3))) {
9731                 /* adjustments to start on required 4 byte boundary */
9732                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9733                 if (ret)
9734                         return ret;
9735                 len += b_offset;
9736                 offset &= ~3;
9737                 if (len < 4)
9738                         len = 4;
9739         }
9740
9741         odd_len = 0;
9742         if (len & 3) {
9743                 /* adjustments to end on required 4 byte boundary */
9744                 odd_len = 1;
9745                 len = (len + 3) & ~3;
9746                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9747                 if (ret)
9748                         return ret;
9749         }
9750
9751         buf = data;
9752         if (b_offset || odd_len) {
9753                 buf = kmalloc(len, GFP_KERNEL);
9754                 if (!buf)
9755                         return -ENOMEM;
9756                 if (b_offset)
9757                         memcpy(buf, &start, 4);
9758                 if (odd_len)
9759                         memcpy(buf+len-4, &end, 4);
9760                 memcpy(buf + b_offset, data, eeprom->len);
9761         }
9762
9763         ret = tg3_nvram_write_block(tp, offset, len, buf);
9764
9765         if (buf != data)
9766                 kfree(buf);
9767
9768         return ret;
9769 }
9770
9771 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9772 {
9773         struct tg3 *tp = netdev_priv(dev);
9774
9775         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9776                 struct phy_device *phydev;
9777                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9778                         return -EAGAIN;
9779                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9780                 return phy_ethtool_gset(phydev, cmd);
9781         }
9782
9783         cmd->supported = (SUPPORTED_Autoneg);
9784
9785         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9786                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9787                                    SUPPORTED_1000baseT_Full);
9788
9789         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9790                 cmd->supported |= (SUPPORTED_100baseT_Half |
9791                                   SUPPORTED_100baseT_Full |
9792                                   SUPPORTED_10baseT_Half |
9793                                   SUPPORTED_10baseT_Full |
9794                                   SUPPORTED_TP);
9795                 cmd->port = PORT_TP;
9796         } else {
9797                 cmd->supported |= SUPPORTED_FIBRE;
9798                 cmd->port = PORT_FIBRE;
9799         }
9800
9801         cmd->advertising = tp->link_config.advertising;
9802         if (netif_running(dev)) {
9803                 cmd->speed = tp->link_config.active_speed;
9804                 cmd->duplex = tp->link_config.active_duplex;
9805         } else {
9806                 cmd->speed = SPEED_INVALID;
9807                 cmd->duplex = DUPLEX_INVALID;
9808         }
9809         cmd->phy_address = tp->phy_addr;
9810         cmd->transceiver = XCVR_INTERNAL;
9811         cmd->autoneg = tp->link_config.autoneg;
9812         cmd->maxtxpkt = 0;
9813         cmd->maxrxpkt = 0;
9814         return 0;
9815 }
9816
9817 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9818 {
9819         struct tg3 *tp = netdev_priv(dev);
9820
9821         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9822                 struct phy_device *phydev;
9823                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9824                         return -EAGAIN;
9825                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9826                 return phy_ethtool_sset(phydev, cmd);
9827         }
9828
9829         if (cmd->autoneg != AUTONEG_ENABLE &&
9830             cmd->autoneg != AUTONEG_DISABLE)
9831                 return -EINVAL;
9832
9833         if (cmd->autoneg == AUTONEG_DISABLE &&
9834             cmd->duplex != DUPLEX_FULL &&
9835             cmd->duplex != DUPLEX_HALF)
9836                 return -EINVAL;
9837
9838         if (cmd->autoneg == AUTONEG_ENABLE) {
9839                 u32 mask = ADVERTISED_Autoneg |
9840                            ADVERTISED_Pause |
9841                            ADVERTISED_Asym_Pause;
9842
9843                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9844                         mask |= ADVERTISED_1000baseT_Half |
9845                                 ADVERTISED_1000baseT_Full;
9846
9847                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9848                         mask |= ADVERTISED_100baseT_Half |
9849                                 ADVERTISED_100baseT_Full |
9850                                 ADVERTISED_10baseT_Half |
9851                                 ADVERTISED_10baseT_Full |
9852                                 ADVERTISED_TP;
9853                 else
9854                         mask |= ADVERTISED_FIBRE;
9855
9856                 if (cmd->advertising & ~mask)
9857                         return -EINVAL;
9858
9859                 mask &= (ADVERTISED_1000baseT_Half |
9860                          ADVERTISED_1000baseT_Full |
9861                          ADVERTISED_100baseT_Half |
9862                          ADVERTISED_100baseT_Full |
9863                          ADVERTISED_10baseT_Half |
9864                          ADVERTISED_10baseT_Full);
9865
9866                 cmd->advertising &= mask;
9867         } else {
9868                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9869                         if (cmd->speed != SPEED_1000)
9870                                 return -EINVAL;
9871
9872                         if (cmd->duplex != DUPLEX_FULL)
9873                                 return -EINVAL;
9874                 } else {
9875                         if (cmd->speed != SPEED_100 &&
9876                             cmd->speed != SPEED_10)
9877                                 return -EINVAL;
9878                 }
9879         }
9880
9881         tg3_full_lock(tp, 0);
9882
9883         tp->link_config.autoneg = cmd->autoneg;
9884         if (cmd->autoneg == AUTONEG_ENABLE) {
9885                 tp->link_config.advertising = (cmd->advertising |
9886                                               ADVERTISED_Autoneg);
9887                 tp->link_config.speed = SPEED_INVALID;
9888                 tp->link_config.duplex = DUPLEX_INVALID;
9889         } else {
9890                 tp->link_config.advertising = 0;
9891                 tp->link_config.speed = cmd->speed;
9892                 tp->link_config.duplex = cmd->duplex;
9893         }
9894
9895         tp->link_config.orig_speed = tp->link_config.speed;
9896         tp->link_config.orig_duplex = tp->link_config.duplex;
9897         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9898
9899         if (netif_running(dev))
9900                 tg3_setup_phy(tp, 1);
9901
9902         tg3_full_unlock(tp);
9903
9904         return 0;
9905 }
9906
9907 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9908 {
9909         struct tg3 *tp = netdev_priv(dev);
9910
9911         strcpy(info->driver, DRV_MODULE_NAME);
9912         strcpy(info->version, DRV_MODULE_VERSION);
9913         strcpy(info->fw_version, tp->fw_ver);
9914         strcpy(info->bus_info, pci_name(tp->pdev));
9915 }
9916
9917 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9918 {
9919         struct tg3 *tp = netdev_priv(dev);
9920
9921         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9922             device_can_wakeup(&tp->pdev->dev))
9923                 wol->supported = WAKE_MAGIC;
9924         else
9925                 wol->supported = 0;
9926         wol->wolopts = 0;
9927         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9928             device_can_wakeup(&tp->pdev->dev))
9929                 wol->wolopts = WAKE_MAGIC;
9930         memset(&wol->sopass, 0, sizeof(wol->sopass));
9931 }
9932
9933 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9934 {
9935         struct tg3 *tp = netdev_priv(dev);
9936         struct device *dp = &tp->pdev->dev;
9937
9938         if (wol->wolopts & ~WAKE_MAGIC)
9939                 return -EINVAL;
9940         if ((wol->wolopts & WAKE_MAGIC) &&
9941             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9942                 return -EINVAL;
9943
9944         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9945
9946         spin_lock_bh(&tp->lock);
9947         if (device_may_wakeup(dp))
9948                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9949         else
9950                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9951         spin_unlock_bh(&tp->lock);
9952
9953
9954         return 0;
9955 }
9956
9957 static u32 tg3_get_msglevel(struct net_device *dev)
9958 {
9959         struct tg3 *tp = netdev_priv(dev);
9960         return tp->msg_enable;
9961 }
9962
9963 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9964 {
9965         struct tg3 *tp = netdev_priv(dev);
9966         tp->msg_enable = value;
9967 }
9968
9969 static int tg3_set_tso(struct net_device *dev, u32 value)
9970 {
9971         struct tg3 *tp = netdev_priv(dev);
9972
9973         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9974                 if (value)
9975                         return -EINVAL;
9976                 return 0;
9977         }
9978         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9979             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9980              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9981                 if (value) {
9982                         dev->features |= NETIF_F_TSO6;
9983                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9984                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9985                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9986                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9987                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9988                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9989                                 dev->features |= NETIF_F_TSO_ECN;
9990                 } else
9991                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9992         }
9993         return ethtool_op_set_tso(dev, value);
9994 }
9995
9996 static int tg3_nway_reset(struct net_device *dev)
9997 {
9998         struct tg3 *tp = netdev_priv(dev);
9999         int r;
10000
10001         if (!netif_running(dev))
10002                 return -EAGAIN;
10003
10004         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10005                 return -EINVAL;
10006
10007         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10008                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10009                         return -EAGAIN;
10010                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10011         } else {
10012                 u32 bmcr;
10013
10014                 spin_lock_bh(&tp->lock);
10015                 r = -EINVAL;
10016                 tg3_readphy(tp, MII_BMCR, &bmcr);
10017                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10018                     ((bmcr & BMCR_ANENABLE) ||
10019                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10020                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10021                                                    BMCR_ANENABLE);
10022                         r = 0;
10023                 }
10024                 spin_unlock_bh(&tp->lock);
10025         }
10026
10027         return r;
10028 }
10029
10030 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10031 {
10032         struct tg3 *tp = netdev_priv(dev);
10033
10034         ering->rx_max_pending = tp->rx_std_ring_mask;
10035         ering->rx_mini_max_pending = 0;
10036         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10037                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10038         else
10039                 ering->rx_jumbo_max_pending = 0;
10040
10041         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10042
10043         ering->rx_pending = tp->rx_pending;
10044         ering->rx_mini_pending = 0;
10045         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10046                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10047         else
10048                 ering->rx_jumbo_pending = 0;
10049
10050         ering->tx_pending = tp->napi[0].tx_pending;
10051 }
10052
10053 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10054 {
10055         struct tg3 *tp = netdev_priv(dev);
10056         int i, irq_sync = 0, err = 0;
10057
10058         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10059             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10060             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10061             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10062             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10063              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10064                 return -EINVAL;
10065
10066         if (netif_running(dev)) {
10067                 tg3_phy_stop(tp);
10068                 tg3_netif_stop(tp);
10069                 irq_sync = 1;
10070         }
10071
10072         tg3_full_lock(tp, irq_sync);
10073
10074         tp->rx_pending = ering->rx_pending;
10075
10076         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10077             tp->rx_pending > 63)
10078                 tp->rx_pending = 63;
10079         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10080
10081         for (i = 0; i < tp->irq_max; i++)
10082                 tp->napi[i].tx_pending = ering->tx_pending;
10083
10084         if (netif_running(dev)) {
10085                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10086                 err = tg3_restart_hw(tp, 1);
10087                 if (!err)
10088                         tg3_netif_start(tp);
10089         }
10090
10091         tg3_full_unlock(tp);
10092
10093         if (irq_sync && !err)
10094                 tg3_phy_start(tp);
10095
10096         return err;
10097 }
10098
10099 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10100 {
10101         struct tg3 *tp = netdev_priv(dev);
10102
10103         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10104
10105         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10106                 epause->rx_pause = 1;
10107         else
10108                 epause->rx_pause = 0;
10109
10110         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10111                 epause->tx_pause = 1;
10112         else
10113                 epause->tx_pause = 0;
10114 }
10115
10116 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10117 {
10118         struct tg3 *tp = netdev_priv(dev);
10119         int err = 0;
10120
10121         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10122                 u32 newadv;
10123                 struct phy_device *phydev;
10124
10125                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10126
10127                 if (!(phydev->supported & SUPPORTED_Pause) ||
10128                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10129                      (epause->rx_pause != epause->tx_pause)))
10130                         return -EINVAL;
10131
10132                 tp->link_config.flowctrl = 0;
10133                 if (epause->rx_pause) {
10134                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10135
10136                         if (epause->tx_pause) {
10137                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10138                                 newadv = ADVERTISED_Pause;
10139                         } else
10140                                 newadv = ADVERTISED_Pause |
10141                                          ADVERTISED_Asym_Pause;
10142                 } else if (epause->tx_pause) {
10143                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10144                         newadv = ADVERTISED_Asym_Pause;
10145                 } else
10146                         newadv = 0;
10147
10148                 if (epause->autoneg)
10149                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10150                 else
10151                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10152
10153                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10154                         u32 oldadv = phydev->advertising &
10155                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10156                         if (oldadv != newadv) {
10157                                 phydev->advertising &=
10158                                         ~(ADVERTISED_Pause |
10159                                           ADVERTISED_Asym_Pause);
10160                                 phydev->advertising |= newadv;
10161                                 if (phydev->autoneg) {
10162                                         /*
10163                                          * Always renegotiate the link to
10164                                          * inform our link partner of our
10165                                          * flow control settings, even if the
10166                                          * flow control is forced.  Let
10167                                          * tg3_adjust_link() do the final
10168                                          * flow control setup.
10169                                          */
10170                                         return phy_start_aneg(phydev);
10171                                 }
10172                         }
10173
10174                         if (!epause->autoneg)
10175                                 tg3_setup_flow_control(tp, 0, 0);
10176                 } else {
10177                         tp->link_config.orig_advertising &=
10178                                         ~(ADVERTISED_Pause |
10179                                           ADVERTISED_Asym_Pause);
10180                         tp->link_config.orig_advertising |= newadv;
10181                 }
10182         } else {
10183                 int irq_sync = 0;
10184
10185                 if (netif_running(dev)) {
10186                         tg3_netif_stop(tp);
10187                         irq_sync = 1;
10188                 }
10189
10190                 tg3_full_lock(tp, irq_sync);
10191
10192                 if (epause->autoneg)
10193                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10194                 else
10195                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10196                 if (epause->rx_pause)
10197                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10198                 else
10199                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10200                 if (epause->tx_pause)
10201                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10202                 else
10203                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10204
10205                 if (netif_running(dev)) {
10206                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10207                         err = tg3_restart_hw(tp, 1);
10208                         if (!err)
10209                                 tg3_netif_start(tp);
10210                 }
10211
10212                 tg3_full_unlock(tp);
10213         }
10214
10215         return err;
10216 }
10217
10218 static u32 tg3_get_rx_csum(struct net_device *dev)
10219 {
10220         struct tg3 *tp = netdev_priv(dev);
10221         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10222 }
10223
10224 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10225 {
10226         struct tg3 *tp = netdev_priv(dev);
10227
10228         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10229                 if (data != 0)
10230                         return -EINVAL;
10231                 return 0;
10232         }
10233
10234         spin_lock_bh(&tp->lock);
10235         if (data)
10236                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10237         else
10238                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10239         spin_unlock_bh(&tp->lock);
10240
10241         return 0;
10242 }
10243
10244 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10245 {
10246         struct tg3 *tp = netdev_priv(dev);
10247
10248         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10249                 if (data != 0)
10250                         return -EINVAL;
10251                 return 0;
10252         }
10253
10254         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10255                 ethtool_op_set_tx_ipv6_csum(dev, data);
10256         else
10257                 ethtool_op_set_tx_csum(dev, data);
10258
10259         return 0;
10260 }
10261
10262 static int tg3_get_sset_count(struct net_device *dev, int sset)
10263 {
10264         switch (sset) {
10265         case ETH_SS_TEST:
10266                 return TG3_NUM_TEST;
10267         case ETH_SS_STATS:
10268                 return TG3_NUM_STATS;
10269         default:
10270                 return -EOPNOTSUPP;
10271         }
10272 }
10273
10274 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10275 {
10276         switch (stringset) {
10277         case ETH_SS_STATS:
10278                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10279                 break;
10280         case ETH_SS_TEST:
10281                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10282                 break;
10283         default:
10284                 WARN_ON(1);     /* we need a WARN() */
10285                 break;
10286         }
10287 }
10288
10289 static int tg3_phys_id(struct net_device *dev, u32 data)
10290 {
10291         struct tg3 *tp = netdev_priv(dev);
10292         int i;
10293
10294         if (!netif_running(tp->dev))
10295                 return -EAGAIN;
10296
10297         if (data == 0)
10298                 data = UINT_MAX / 2;
10299
10300         for (i = 0; i < (data * 2); i++) {
10301                 if ((i % 2) == 0)
10302                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10303                                            LED_CTRL_1000MBPS_ON |
10304                                            LED_CTRL_100MBPS_ON |
10305                                            LED_CTRL_10MBPS_ON |
10306                                            LED_CTRL_TRAFFIC_OVERRIDE |
10307                                            LED_CTRL_TRAFFIC_BLINK |
10308                                            LED_CTRL_TRAFFIC_LED);
10309
10310                 else
10311                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10312                                            LED_CTRL_TRAFFIC_OVERRIDE);
10313
10314                 if (msleep_interruptible(500))
10315                         break;
10316         }
10317         tw32(MAC_LED_CTRL, tp->led_ctrl);
10318         return 0;
10319 }
10320
10321 static void tg3_get_ethtool_stats(struct net_device *dev,
10322                                    struct ethtool_stats *estats, u64 *tmp_stats)
10323 {
10324         struct tg3 *tp = netdev_priv(dev);
10325         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10326 }
10327
10328 #define NVRAM_TEST_SIZE 0x100
10329 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10330 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10331 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10332 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10333 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10334
10335 static int tg3_test_nvram(struct tg3 *tp)
10336 {
10337         u32 csum, magic;
10338         __be32 *buf;
10339         int i, j, k, err = 0, size;
10340
10341         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10342                 return 0;
10343
10344         if (tg3_nvram_read(tp, 0, &magic) != 0)
10345                 return -EIO;
10346
10347         if (magic == TG3_EEPROM_MAGIC)
10348                 size = NVRAM_TEST_SIZE;
10349         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10350                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10351                     TG3_EEPROM_SB_FORMAT_1) {
10352                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10353                         case TG3_EEPROM_SB_REVISION_0:
10354                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10355                                 break;
10356                         case TG3_EEPROM_SB_REVISION_2:
10357                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10358                                 break;
10359                         case TG3_EEPROM_SB_REVISION_3:
10360                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10361                                 break;
10362                         default:
10363                                 return 0;
10364                         }
10365                 } else
10366                         return 0;
10367         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10368                 size = NVRAM_SELFBOOT_HW_SIZE;
10369         else
10370                 return -EIO;
10371
10372         buf = kmalloc(size, GFP_KERNEL);
10373         if (buf == NULL)
10374                 return -ENOMEM;
10375
10376         err = -EIO;
10377         for (i = 0, j = 0; i < size; i += 4, j++) {
10378                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10379                 if (err)
10380                         break;
10381         }
10382         if (i < size)
10383                 goto out;
10384
10385         /* Selfboot format */
10386         magic = be32_to_cpu(buf[0]);
10387         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10388             TG3_EEPROM_MAGIC_FW) {
10389                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10390
10391                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10392                     TG3_EEPROM_SB_REVISION_2) {
10393                         /* For rev 2, the csum doesn't include the MBA. */
10394                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10395                                 csum8 += buf8[i];
10396                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10397                                 csum8 += buf8[i];
10398                 } else {
10399                         for (i = 0; i < size; i++)
10400                                 csum8 += buf8[i];
10401                 }
10402
10403                 if (csum8 == 0) {
10404                         err = 0;
10405                         goto out;
10406                 }
10407
10408                 err = -EIO;
10409                 goto out;
10410         }
10411
10412         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10413             TG3_EEPROM_MAGIC_HW) {
10414                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10415                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10416                 u8 *buf8 = (u8 *) buf;
10417
10418                 /* Separate the parity bits and the data bytes.  */
10419                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10420                         if ((i == 0) || (i == 8)) {
10421                                 int l;
10422                                 u8 msk;
10423
10424                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10425                                         parity[k++] = buf8[i] & msk;
10426                                 i++;
10427                         } else if (i == 16) {
10428                                 int l;
10429                                 u8 msk;
10430
10431                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10432                                         parity[k++] = buf8[i] & msk;
10433                                 i++;
10434
10435                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10436                                         parity[k++] = buf8[i] & msk;
10437                                 i++;
10438                         }
10439                         data[j++] = buf8[i];
10440                 }
10441
10442                 err = -EIO;
10443                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10444                         u8 hw8 = hweight8(data[i]);
10445
10446                         if ((hw8 & 0x1) && parity[i])
10447                                 goto out;
10448                         else if (!(hw8 & 0x1) && !parity[i])
10449                                 goto out;
10450                 }
10451                 err = 0;
10452                 goto out;
10453         }
10454
10455         /* Bootstrap checksum at offset 0x10 */
10456         csum = calc_crc((unsigned char *) buf, 0x10);
10457         if (csum != be32_to_cpu(buf[0x10/4]))
10458                 goto out;
10459
10460         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10461         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10462         if (csum != be32_to_cpu(buf[0xfc/4]))
10463                 goto out;
10464
10465         err = 0;
10466
10467 out:
10468         kfree(buf);
10469         return err;
10470 }
10471
10472 #define TG3_SERDES_TIMEOUT_SEC  2
10473 #define TG3_COPPER_TIMEOUT_SEC  6
10474
10475 static int tg3_test_link(struct tg3 *tp)
10476 {
10477         int i, max;
10478
10479         if (!netif_running(tp->dev))
10480                 return -ENODEV;
10481
10482         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10483                 max = TG3_SERDES_TIMEOUT_SEC;
10484         else
10485                 max = TG3_COPPER_TIMEOUT_SEC;
10486
10487         for (i = 0; i < max; i++) {
10488                 if (netif_carrier_ok(tp->dev))
10489                         return 0;
10490
10491                 if (msleep_interruptible(1000))
10492                         break;
10493         }
10494
10495         return -EIO;
10496 }
10497
10498 /* Only test the commonly used registers */
10499 static int tg3_test_registers(struct tg3 *tp)
10500 {
10501         int i, is_5705, is_5750;
10502         u32 offset, read_mask, write_mask, val, save_val, read_val;
10503         static struct {
10504                 u16 offset;
10505                 u16 flags;
10506 #define TG3_FL_5705     0x1
10507 #define TG3_FL_NOT_5705 0x2
10508 #define TG3_FL_NOT_5788 0x4
10509 #define TG3_FL_NOT_5750 0x8
10510                 u32 read_mask;
10511                 u32 write_mask;
10512         } reg_tbl[] = {
10513                 /* MAC Control Registers */
10514                 { MAC_MODE, TG3_FL_NOT_5705,
10515                         0x00000000, 0x00ef6f8c },
10516                 { MAC_MODE, TG3_FL_5705,
10517                         0x00000000, 0x01ef6b8c },
10518                 { MAC_STATUS, TG3_FL_NOT_5705,
10519                         0x03800107, 0x00000000 },
10520                 { MAC_STATUS, TG3_FL_5705,
10521                         0x03800100, 0x00000000 },
10522                 { MAC_ADDR_0_HIGH, 0x0000,
10523                         0x00000000, 0x0000ffff },
10524                 { MAC_ADDR_0_LOW, 0x0000,
10525                         0x00000000, 0xffffffff },
10526                 { MAC_RX_MTU_SIZE, 0x0000,
10527                         0x00000000, 0x0000ffff },
10528                 { MAC_TX_MODE, 0x0000,
10529                         0x00000000, 0x00000070 },
10530                 { MAC_TX_LENGTHS, 0x0000,
10531                         0x00000000, 0x00003fff },
10532                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10533                         0x00000000, 0x000007fc },
10534                 { MAC_RX_MODE, TG3_FL_5705,
10535                         0x00000000, 0x000007dc },
10536                 { MAC_HASH_REG_0, 0x0000,
10537                         0x00000000, 0xffffffff },
10538                 { MAC_HASH_REG_1, 0x0000,
10539                         0x00000000, 0xffffffff },
10540                 { MAC_HASH_REG_2, 0x0000,
10541                         0x00000000, 0xffffffff },
10542                 { MAC_HASH_REG_3, 0x0000,
10543                         0x00000000, 0xffffffff },
10544
10545                 /* Receive Data and Receive BD Initiator Control Registers. */
10546                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10547                         0x00000000, 0xffffffff },
10548                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10549                         0x00000000, 0xffffffff },
10550                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10551                         0x00000000, 0x00000003 },
10552                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10553                         0x00000000, 0xffffffff },
10554                 { RCVDBDI_STD_BD+0, 0x0000,
10555                         0x00000000, 0xffffffff },
10556                 { RCVDBDI_STD_BD+4, 0x0000,
10557                         0x00000000, 0xffffffff },
10558                 { RCVDBDI_STD_BD+8, 0x0000,
10559                         0x00000000, 0xffff0002 },
10560                 { RCVDBDI_STD_BD+0xc, 0x0000,
10561                         0x00000000, 0xffffffff },
10562
10563                 /* Receive BD Initiator Control Registers. */
10564                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10565                         0x00000000, 0xffffffff },
10566                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10567                         0x00000000, 0x000003ff },
10568                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10569                         0x00000000, 0xffffffff },
10570
10571                 /* Host Coalescing Control Registers. */
10572                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10573                         0x00000000, 0x00000004 },
10574                 { HOSTCC_MODE, TG3_FL_5705,
10575                         0x00000000, 0x000000f6 },
10576                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10577                         0x00000000, 0xffffffff },
10578                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10579                         0x00000000, 0x000003ff },
10580                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10581                         0x00000000, 0xffffffff },
10582                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10583                         0x00000000, 0x000003ff },
10584                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10585                         0x00000000, 0xffffffff },
10586                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10587                         0x00000000, 0x000000ff },
10588                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10589                         0x00000000, 0xffffffff },
10590                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10591                         0x00000000, 0x000000ff },
10592                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10593                         0x00000000, 0xffffffff },
10594                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10595                         0x00000000, 0xffffffff },
10596                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10597                         0x00000000, 0xffffffff },
10598                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10599                         0x00000000, 0x000000ff },
10600                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10601                         0x00000000, 0xffffffff },
10602                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10603                         0x00000000, 0x000000ff },
10604                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10605                         0x00000000, 0xffffffff },
10606                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10607                         0x00000000, 0xffffffff },
10608                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10609                         0x00000000, 0xffffffff },
10610                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10611                         0x00000000, 0xffffffff },
10612                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10613                         0x00000000, 0xffffffff },
10614                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10615                         0xffffffff, 0x00000000 },
10616                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10617                         0xffffffff, 0x00000000 },
10618
10619                 /* Buffer Manager Control Registers. */
10620                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10621                         0x00000000, 0x007fff80 },
10622                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10623                         0x00000000, 0x007fffff },
10624                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10625                         0x00000000, 0x0000003f },
10626                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10627                         0x00000000, 0x000001ff },
10628                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10629                         0x00000000, 0x000001ff },
10630                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10631                         0xffffffff, 0x00000000 },
10632                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10633                         0xffffffff, 0x00000000 },
10634
10635                 /* Mailbox Registers */
10636                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10637                         0x00000000, 0x000001ff },
10638                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10639                         0x00000000, 0x000001ff },
10640                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10641                         0x00000000, 0x000007ff },
10642                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10643                         0x00000000, 0x000001ff },
10644
10645                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10646         };
10647
10648         is_5705 = is_5750 = 0;
10649         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10650                 is_5705 = 1;
10651                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10652                         is_5750 = 1;
10653         }
10654
10655         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10656                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10657                         continue;
10658
10659                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10660                         continue;
10661
10662                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10663                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10664                         continue;
10665
10666                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10667                         continue;
10668
10669                 offset = (u32) reg_tbl[i].offset;
10670                 read_mask = reg_tbl[i].read_mask;
10671                 write_mask = reg_tbl[i].write_mask;
10672
10673                 /* Save the original register content */
10674                 save_val = tr32(offset);
10675
10676                 /* Determine the read-only value. */
10677                 read_val = save_val & read_mask;
10678
10679                 /* Write zero to the register, then make sure the read-only bits
10680                  * are not changed and the read/write bits are all zeros.
10681                  */
10682                 tw32(offset, 0);
10683
10684                 val = tr32(offset);
10685
10686                 /* Test the read-only and read/write bits. */
10687                 if (((val & read_mask) != read_val) || (val & write_mask))
10688                         goto out;
10689
10690                 /* Write ones to all the bits defined by RdMask and WrMask, then
10691                  * make sure the read-only bits are not changed and the
10692                  * read/write bits are all ones.
10693                  */
10694                 tw32(offset, read_mask | write_mask);
10695
10696                 val = tr32(offset);
10697
10698                 /* Test the read-only bits. */
10699                 if ((val & read_mask) != read_val)
10700                         goto out;
10701
10702                 /* Test the read/write bits. */
10703                 if ((val & write_mask) != write_mask)
10704                         goto out;
10705
10706                 tw32(offset, save_val);
10707         }
10708
10709         return 0;
10710
10711 out:
10712         if (netif_msg_hw(tp))
10713                 netdev_err(tp->dev,
10714                            "Register test failed at offset %x\n", offset);
10715         tw32(offset, save_val);
10716         return -EIO;
10717 }
10718
10719 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10720 {
10721         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10722         int i;
10723         u32 j;
10724
10725         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10726                 for (j = 0; j < len; j += 4) {
10727                         u32 val;
10728
10729                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10730                         tg3_read_mem(tp, offset + j, &val);
10731                         if (val != test_pattern[i])
10732                                 return -EIO;
10733                 }
10734         }
10735         return 0;
10736 }
10737
10738 static int tg3_test_memory(struct tg3 *tp)
10739 {
10740         static struct mem_entry {
10741                 u32 offset;
10742                 u32 len;
10743         } mem_tbl_570x[] = {
10744                 { 0x00000000, 0x00b50},
10745                 { 0x00002000, 0x1c000},
10746                 { 0xffffffff, 0x00000}
10747         }, mem_tbl_5705[] = {
10748                 { 0x00000100, 0x0000c},
10749                 { 0x00000200, 0x00008},
10750                 { 0x00004000, 0x00800},
10751                 { 0x00006000, 0x01000},
10752                 { 0x00008000, 0x02000},
10753                 { 0x00010000, 0x0e000},
10754                 { 0xffffffff, 0x00000}
10755         }, mem_tbl_5755[] = {
10756                 { 0x00000200, 0x00008},
10757                 { 0x00004000, 0x00800},
10758                 { 0x00006000, 0x00800},
10759                 { 0x00008000, 0x02000},
10760                 { 0x00010000, 0x0c000},
10761                 { 0xffffffff, 0x00000}
10762         }, mem_tbl_5906[] = {
10763                 { 0x00000200, 0x00008},
10764                 { 0x00004000, 0x00400},
10765                 { 0x00006000, 0x00400},
10766                 { 0x00008000, 0x01000},
10767                 { 0x00010000, 0x01000},
10768                 { 0xffffffff, 0x00000}
10769         }, mem_tbl_5717[] = {
10770                 { 0x00000200, 0x00008},
10771                 { 0x00010000, 0x0a000},
10772                 { 0x00020000, 0x13c00},
10773                 { 0xffffffff, 0x00000}
10774         }, mem_tbl_57765[] = {
10775                 { 0x00000200, 0x00008},
10776                 { 0x00004000, 0x00800},
10777                 { 0x00006000, 0x09800},
10778                 { 0x00010000, 0x0a000},
10779                 { 0xffffffff, 0x00000}
10780         };
10781         struct mem_entry *mem_tbl;
10782         int err = 0;
10783         int i;
10784
10785         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10786             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10787                 mem_tbl = mem_tbl_5717;
10788         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10789                 mem_tbl = mem_tbl_57765;
10790         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10791                 mem_tbl = mem_tbl_5755;
10792         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10793                 mem_tbl = mem_tbl_5906;
10794         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10795                 mem_tbl = mem_tbl_5705;
10796         else
10797                 mem_tbl = mem_tbl_570x;
10798
10799         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10800                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10801                 if (err)
10802                         break;
10803         }
10804
10805         return err;
10806 }
10807
10808 #define TG3_MAC_LOOPBACK        0
10809 #define TG3_PHY_LOOPBACK        1
10810
10811 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10812 {
10813         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10814         u32 desc_idx, coal_now;
10815         struct sk_buff *skb, *rx_skb;
10816         u8 *tx_data;
10817         dma_addr_t map;
10818         int num_pkts, tx_len, rx_len, i, err;
10819         struct tg3_rx_buffer_desc *desc;
10820         struct tg3_napi *tnapi, *rnapi;
10821         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10822
10823         tnapi = &tp->napi[0];
10824         rnapi = &tp->napi[0];
10825         if (tp->irq_cnt > 1) {
10826                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10827                         rnapi = &tp->napi[1];
10828                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10829                         tnapi = &tp->napi[1];
10830         }
10831         coal_now = tnapi->coal_now | rnapi->coal_now;
10832
10833         if (loopback_mode == TG3_MAC_LOOPBACK) {
10834                 /* HW errata - mac loopback fails in some cases on 5780.
10835                  * Normal traffic and PHY loopback are not affected by
10836                  * errata.
10837                  */
10838                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10839                         return 0;
10840
10841                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10842                            MAC_MODE_PORT_INT_LPBACK;
10843                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10844                         mac_mode |= MAC_MODE_LINK_POLARITY;
10845                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10846                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10847                 else
10848                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10849                 tw32(MAC_MODE, mac_mode);
10850         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10851                 u32 val;
10852
10853                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10854                         tg3_phy_fet_toggle_apd(tp, false);
10855                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10856                 } else
10857                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10858
10859                 tg3_phy_toggle_automdix(tp, 0);
10860
10861                 tg3_writephy(tp, MII_BMCR, val);
10862                 udelay(40);
10863
10864                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10865                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10866                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10867                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10868                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10869                         /* The write needs to be flushed for the AC131 */
10870                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10871                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10872                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10873                 } else
10874                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10875
10876                 /* reset to prevent losing 1st rx packet intermittently */
10877                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10878                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10879                         udelay(10);
10880                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10881                 }
10882                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10883                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10884                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10885                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10886                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10887                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10888                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10889                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10890                 }
10891                 tw32(MAC_MODE, mac_mode);
10892         } else {
10893                 return -EINVAL;
10894         }
10895
10896         err = -EIO;
10897
10898         tx_len = 1514;
10899         skb = netdev_alloc_skb(tp->dev, tx_len);
10900         if (!skb)
10901                 return -ENOMEM;
10902
10903         tx_data = skb_put(skb, tx_len);
10904         memcpy(tx_data, tp->dev->dev_addr, 6);
10905         memset(tx_data + 6, 0x0, 8);
10906
10907         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10908
10909         for (i = 14; i < tx_len; i++)
10910                 tx_data[i] = (u8) (i & 0xff);
10911
10912         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10913         if (pci_dma_mapping_error(tp->pdev, map)) {
10914                 dev_kfree_skb(skb);
10915                 return -EIO;
10916         }
10917
10918         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10919                rnapi->coal_now);
10920
10921         udelay(10);
10922
10923         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10924
10925         num_pkts = 0;
10926
10927         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10928
10929         tnapi->tx_prod++;
10930         num_pkts++;
10931
10932         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10933         tr32_mailbox(tnapi->prodmbox);
10934
10935         udelay(10);
10936
10937         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10938         for (i = 0; i < 35; i++) {
10939                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10940                        coal_now);
10941
10942                 udelay(10);
10943
10944                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10945                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10946                 if ((tx_idx == tnapi->tx_prod) &&
10947                     (rx_idx == (rx_start_idx + num_pkts)))
10948                         break;
10949         }
10950
10951         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10952         dev_kfree_skb(skb);
10953
10954         if (tx_idx != tnapi->tx_prod)
10955                 goto out;
10956
10957         if (rx_idx != rx_start_idx + num_pkts)
10958                 goto out;
10959
10960         desc = &rnapi->rx_rcb[rx_start_idx];
10961         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10962         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10963         if (opaque_key != RXD_OPAQUE_RING_STD)
10964                 goto out;
10965
10966         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10967             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10968                 goto out;
10969
10970         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10971         if (rx_len != tx_len)
10972                 goto out;
10973
10974         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10975
10976         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10977         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10978
10979         for (i = 14; i < tx_len; i++) {
10980                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10981                         goto out;
10982         }
10983         err = 0;
10984
10985         /* tg3_free_rings will unmap and free the rx_skb */
10986 out:
10987         return err;
10988 }
10989
10990 #define TG3_MAC_LOOPBACK_FAILED         1
10991 #define TG3_PHY_LOOPBACK_FAILED         2
10992 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10993                                          TG3_PHY_LOOPBACK_FAILED)
10994
10995 static int tg3_test_loopback(struct tg3 *tp)
10996 {
10997         int err = 0;
10998         u32 cpmuctrl = 0;
10999
11000         if (!netif_running(tp->dev))
11001                 return TG3_LOOPBACK_FAILED;
11002
11003         err = tg3_reset_hw(tp, 1);
11004         if (err)
11005                 return TG3_LOOPBACK_FAILED;
11006
11007         /* Turn off gphy autopowerdown. */
11008         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11009                 tg3_phy_toggle_apd(tp, false);
11010
11011         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11012                 int i;
11013                 u32 status;
11014
11015                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11016
11017                 /* Wait for up to 40 microseconds to acquire lock. */
11018                 for (i = 0; i < 4; i++) {
11019                         status = tr32(TG3_CPMU_MUTEX_GNT);
11020                         if (status == CPMU_MUTEX_GNT_DRIVER)
11021                                 break;
11022                         udelay(10);
11023                 }
11024
11025                 if (status != CPMU_MUTEX_GNT_DRIVER)
11026                         return TG3_LOOPBACK_FAILED;
11027
11028                 /* Turn off link-based power management. */
11029                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11030                 tw32(TG3_CPMU_CTRL,
11031                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11032                                   CPMU_CTRL_LINK_AWARE_MODE));
11033         }
11034
11035         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11036                 err |= TG3_MAC_LOOPBACK_FAILED;
11037
11038         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11039                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11040
11041                 /* Release the mutex */
11042                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11043         }
11044
11045         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11046             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11047                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11048                         err |= TG3_PHY_LOOPBACK_FAILED;
11049         }
11050
11051         /* Re-enable gphy autopowerdown. */
11052         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11053                 tg3_phy_toggle_apd(tp, true);
11054
11055         return err;
11056 }
11057
11058 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11059                           u64 *data)
11060 {
11061         struct tg3 *tp = netdev_priv(dev);
11062
11063         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11064                 tg3_power_up(tp);
11065
11066         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11067
11068         if (tg3_test_nvram(tp) != 0) {
11069                 etest->flags |= ETH_TEST_FL_FAILED;
11070                 data[0] = 1;
11071         }
11072         if (tg3_test_link(tp) != 0) {
11073                 etest->flags |= ETH_TEST_FL_FAILED;
11074                 data[1] = 1;
11075         }
11076         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11077                 int err, err2 = 0, irq_sync = 0;
11078
11079                 if (netif_running(dev)) {
11080                         tg3_phy_stop(tp);
11081                         tg3_netif_stop(tp);
11082                         irq_sync = 1;
11083                 }
11084
11085                 tg3_full_lock(tp, irq_sync);
11086
11087                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11088                 err = tg3_nvram_lock(tp);
11089                 tg3_halt_cpu(tp, RX_CPU_BASE);
11090                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11091                         tg3_halt_cpu(tp, TX_CPU_BASE);
11092                 if (!err)
11093                         tg3_nvram_unlock(tp);
11094
11095                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11096                         tg3_phy_reset(tp);
11097
11098                 if (tg3_test_registers(tp) != 0) {
11099                         etest->flags |= ETH_TEST_FL_FAILED;
11100                         data[2] = 1;
11101                 }
11102                 if (tg3_test_memory(tp) != 0) {
11103                         etest->flags |= ETH_TEST_FL_FAILED;
11104                         data[3] = 1;
11105                 }
11106                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11107                         etest->flags |= ETH_TEST_FL_FAILED;
11108
11109                 tg3_full_unlock(tp);
11110
11111                 if (tg3_test_interrupt(tp) != 0) {
11112                         etest->flags |= ETH_TEST_FL_FAILED;
11113                         data[5] = 1;
11114                 }
11115
11116                 tg3_full_lock(tp, 0);
11117
11118                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11119                 if (netif_running(dev)) {
11120                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11121                         err2 = tg3_restart_hw(tp, 1);
11122                         if (!err2)
11123                                 tg3_netif_start(tp);
11124                 }
11125
11126                 tg3_full_unlock(tp);
11127
11128                 if (irq_sync && !err2)
11129                         tg3_phy_start(tp);
11130         }
11131         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11132                 tg3_power_down(tp);
11133
11134 }
11135
11136 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11137 {
11138         struct mii_ioctl_data *data = if_mii(ifr);
11139         struct tg3 *tp = netdev_priv(dev);
11140         int err;
11141
11142         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11143                 struct phy_device *phydev;
11144                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11145                         return -EAGAIN;
11146                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11147                 return phy_mii_ioctl(phydev, ifr, cmd);
11148         }
11149
11150         switch (cmd) {
11151         case SIOCGMIIPHY:
11152                 data->phy_id = tp->phy_addr;
11153
11154                 /* fallthru */
11155         case SIOCGMIIREG: {
11156                 u32 mii_regval;
11157
11158                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11159                         break;                  /* We have no PHY */
11160
11161                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11162                         return -EAGAIN;
11163
11164                 spin_lock_bh(&tp->lock);
11165                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11166                 spin_unlock_bh(&tp->lock);
11167
11168                 data->val_out = mii_regval;
11169
11170                 return err;
11171         }
11172
11173         case SIOCSMIIREG:
11174                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11175                         break;                  /* We have no PHY */
11176
11177                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11178                         return -EAGAIN;
11179
11180                 spin_lock_bh(&tp->lock);
11181                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11182                 spin_unlock_bh(&tp->lock);
11183
11184                 return err;
11185
11186         default:
11187                 /* do nothing */
11188                 break;
11189         }
11190         return -EOPNOTSUPP;
11191 }
11192
11193 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11194 {
11195         struct tg3 *tp = netdev_priv(dev);
11196
11197         memcpy(ec, &tp->coal, sizeof(*ec));
11198         return 0;
11199 }
11200
11201 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11202 {
11203         struct tg3 *tp = netdev_priv(dev);
11204         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11205         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11206
11207         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11208                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11209                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11210                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11211                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11212         }
11213
11214         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11215             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11216             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11217             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11218             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11219             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11220             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11221             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11222             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11223             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11224                 return -EINVAL;
11225
11226         /* No rx interrupts will be generated if both are zero */
11227         if ((ec->rx_coalesce_usecs == 0) &&
11228             (ec->rx_max_coalesced_frames == 0))
11229                 return -EINVAL;
11230
11231         /* No tx interrupts will be generated if both are zero */
11232         if ((ec->tx_coalesce_usecs == 0) &&
11233             (ec->tx_max_coalesced_frames == 0))
11234                 return -EINVAL;
11235
11236         /* Only copy relevant parameters, ignore all others. */
11237         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11238         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11239         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11240         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11241         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11242         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11243         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11244         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11245         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11246
11247         if (netif_running(dev)) {
11248                 tg3_full_lock(tp, 0);
11249                 __tg3_set_coalesce(tp, &tp->coal);
11250                 tg3_full_unlock(tp);
11251         }
11252         return 0;
11253 }
11254
11255 static const struct ethtool_ops tg3_ethtool_ops = {
11256         .get_settings           = tg3_get_settings,
11257         .set_settings           = tg3_set_settings,
11258         .get_drvinfo            = tg3_get_drvinfo,
11259         .get_regs_len           = tg3_get_regs_len,
11260         .get_regs               = tg3_get_regs,
11261         .get_wol                = tg3_get_wol,
11262         .set_wol                = tg3_set_wol,
11263         .get_msglevel           = tg3_get_msglevel,
11264         .set_msglevel           = tg3_set_msglevel,
11265         .nway_reset             = tg3_nway_reset,
11266         .get_link               = ethtool_op_get_link,
11267         .get_eeprom_len         = tg3_get_eeprom_len,
11268         .get_eeprom             = tg3_get_eeprom,
11269         .set_eeprom             = tg3_set_eeprom,
11270         .get_ringparam          = tg3_get_ringparam,
11271         .set_ringparam          = tg3_set_ringparam,
11272         .get_pauseparam         = tg3_get_pauseparam,
11273         .set_pauseparam         = tg3_set_pauseparam,
11274         .get_rx_csum            = tg3_get_rx_csum,
11275         .set_rx_csum            = tg3_set_rx_csum,
11276         .set_tx_csum            = tg3_set_tx_csum,
11277         .set_sg                 = ethtool_op_set_sg,
11278         .set_tso                = tg3_set_tso,
11279         .self_test              = tg3_self_test,
11280         .get_strings            = tg3_get_strings,
11281         .phys_id                = tg3_phys_id,
11282         .get_ethtool_stats      = tg3_get_ethtool_stats,
11283         .get_coalesce           = tg3_get_coalesce,
11284         .set_coalesce           = tg3_set_coalesce,
11285         .get_sset_count         = tg3_get_sset_count,
11286 };
11287
11288 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11289 {
11290         u32 cursize, val, magic;
11291
11292         tp->nvram_size = EEPROM_CHIP_SIZE;
11293
11294         if (tg3_nvram_read(tp, 0, &magic) != 0)
11295                 return;
11296
11297         if ((magic != TG3_EEPROM_MAGIC) &&
11298             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11299             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11300                 return;
11301
11302         /*
11303          * Size the chip by reading offsets at increasing powers of two.
11304          * When we encounter our validation signature, we know the addressing
11305          * has wrapped around, and thus have our chip size.
11306          */
11307         cursize = 0x10;
11308
11309         while (cursize < tp->nvram_size) {
11310                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11311                         return;
11312
11313                 if (val == magic)
11314                         break;
11315
11316                 cursize <<= 1;
11317         }
11318
11319         tp->nvram_size = cursize;
11320 }
11321
11322 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11323 {
11324         u32 val;
11325
11326         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11327             tg3_nvram_read(tp, 0, &val) != 0)
11328                 return;
11329
11330         /* Selfboot format */
11331         if (val != TG3_EEPROM_MAGIC) {
11332                 tg3_get_eeprom_size(tp);
11333                 return;
11334         }
11335
11336         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11337                 if (val != 0) {
11338                         /* This is confusing.  We want to operate on the
11339                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11340                          * call will read from NVRAM and byteswap the data
11341                          * according to the byteswapping settings for all
11342                          * other register accesses.  This ensures the data we
11343                          * want will always reside in the lower 16-bits.
11344                          * However, the data in NVRAM is in LE format, which
11345                          * means the data from the NVRAM read will always be
11346                          * opposite the endianness of the CPU.  The 16-bit
11347                          * byteswap then brings the data to CPU endianness.
11348                          */
11349                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11350                         return;
11351                 }
11352         }
11353         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11354 }
11355
11356 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11357 {
11358         u32 nvcfg1;
11359
11360         nvcfg1 = tr32(NVRAM_CFG1);
11361         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11362                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11363         } else {
11364                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11365                 tw32(NVRAM_CFG1, nvcfg1);
11366         }
11367
11368         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11369             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11370                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11371                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11372                         tp->nvram_jedecnum = JEDEC_ATMEL;
11373                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11374                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375                         break;
11376                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11377                         tp->nvram_jedecnum = JEDEC_ATMEL;
11378                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11379                         break;
11380                 case FLASH_VENDOR_ATMEL_EEPROM:
11381                         tp->nvram_jedecnum = JEDEC_ATMEL;
11382                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11383                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11384                         break;
11385                 case FLASH_VENDOR_ST:
11386                         tp->nvram_jedecnum = JEDEC_ST;
11387                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11388                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11389                         break;
11390                 case FLASH_VENDOR_SAIFUN:
11391                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11392                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11393                         break;
11394                 case FLASH_VENDOR_SST_SMALL:
11395                 case FLASH_VENDOR_SST_LARGE:
11396                         tp->nvram_jedecnum = JEDEC_SST;
11397                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11398                         break;
11399                 }
11400         } else {
11401                 tp->nvram_jedecnum = JEDEC_ATMEL;
11402                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11403                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11404         }
11405 }
11406
11407 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11408 {
11409         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11410         case FLASH_5752PAGE_SIZE_256:
11411                 tp->nvram_pagesize = 256;
11412                 break;
11413         case FLASH_5752PAGE_SIZE_512:
11414                 tp->nvram_pagesize = 512;
11415                 break;
11416         case FLASH_5752PAGE_SIZE_1K:
11417                 tp->nvram_pagesize = 1024;
11418                 break;
11419         case FLASH_5752PAGE_SIZE_2K:
11420                 tp->nvram_pagesize = 2048;
11421                 break;
11422         case FLASH_5752PAGE_SIZE_4K:
11423                 tp->nvram_pagesize = 4096;
11424                 break;
11425         case FLASH_5752PAGE_SIZE_264:
11426                 tp->nvram_pagesize = 264;
11427                 break;
11428         case FLASH_5752PAGE_SIZE_528:
11429                 tp->nvram_pagesize = 528;
11430                 break;
11431         }
11432 }
11433
11434 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11435 {
11436         u32 nvcfg1;
11437
11438         nvcfg1 = tr32(NVRAM_CFG1);
11439
11440         /* NVRAM protection for TPM */
11441         if (nvcfg1 & (1 << 27))
11442                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11443
11444         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11445         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11446         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11447                 tp->nvram_jedecnum = JEDEC_ATMEL;
11448                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449                 break;
11450         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11451                 tp->nvram_jedecnum = JEDEC_ATMEL;
11452                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11453                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11454                 break;
11455         case FLASH_5752VENDOR_ST_M45PE10:
11456         case FLASH_5752VENDOR_ST_M45PE20:
11457         case FLASH_5752VENDOR_ST_M45PE40:
11458                 tp->nvram_jedecnum = JEDEC_ST;
11459                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11461                 break;
11462         }
11463
11464         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11465                 tg3_nvram_get_pagesize(tp, nvcfg1);
11466         } else {
11467                 /* For eeprom, set pagesize to maximum eeprom size */
11468                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11469
11470                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11471                 tw32(NVRAM_CFG1, nvcfg1);
11472         }
11473 }
11474
11475 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11476 {
11477         u32 nvcfg1, protect = 0;
11478
11479         nvcfg1 = tr32(NVRAM_CFG1);
11480
11481         /* NVRAM protection for TPM */
11482         if (nvcfg1 & (1 << 27)) {
11483                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11484                 protect = 1;
11485         }
11486
11487         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11488         switch (nvcfg1) {
11489         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11490         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11491         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11492         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11493                 tp->nvram_jedecnum = JEDEC_ATMEL;
11494                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11495                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11496                 tp->nvram_pagesize = 264;
11497                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11498                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11499                         tp->nvram_size = (protect ? 0x3e200 :
11500                                           TG3_NVRAM_SIZE_512KB);
11501                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11502                         tp->nvram_size = (protect ? 0x1f200 :
11503                                           TG3_NVRAM_SIZE_256KB);
11504                 else
11505                         tp->nvram_size = (protect ? 0x1f200 :
11506                                           TG3_NVRAM_SIZE_128KB);
11507                 break;
11508         case FLASH_5752VENDOR_ST_M45PE10:
11509         case FLASH_5752VENDOR_ST_M45PE20:
11510         case FLASH_5752VENDOR_ST_M45PE40:
11511                 tp->nvram_jedecnum = JEDEC_ST;
11512                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11513                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11514                 tp->nvram_pagesize = 256;
11515                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11516                         tp->nvram_size = (protect ?
11517                                           TG3_NVRAM_SIZE_64KB :
11518                                           TG3_NVRAM_SIZE_128KB);
11519                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11520                         tp->nvram_size = (protect ?
11521                                           TG3_NVRAM_SIZE_64KB :
11522                                           TG3_NVRAM_SIZE_256KB);
11523                 else
11524                         tp->nvram_size = (protect ?
11525                                           TG3_NVRAM_SIZE_128KB :
11526                                           TG3_NVRAM_SIZE_512KB);
11527                 break;
11528         }
11529 }
11530
11531 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11532 {
11533         u32 nvcfg1;
11534
11535         nvcfg1 = tr32(NVRAM_CFG1);
11536
11537         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11538         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11539         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11540         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11541         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11542                 tp->nvram_jedecnum = JEDEC_ATMEL;
11543                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11544                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11545
11546                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11547                 tw32(NVRAM_CFG1, nvcfg1);
11548                 break;
11549         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11550         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11551         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11552         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11553                 tp->nvram_jedecnum = JEDEC_ATMEL;
11554                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11555                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11556                 tp->nvram_pagesize = 264;
11557                 break;
11558         case FLASH_5752VENDOR_ST_M45PE10:
11559         case FLASH_5752VENDOR_ST_M45PE20:
11560         case FLASH_5752VENDOR_ST_M45PE40:
11561                 tp->nvram_jedecnum = JEDEC_ST;
11562                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11563                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11564                 tp->nvram_pagesize = 256;
11565                 break;
11566         }
11567 }
11568
11569 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11570 {
11571         u32 nvcfg1, protect = 0;
11572
11573         nvcfg1 = tr32(NVRAM_CFG1);
11574
11575         /* NVRAM protection for TPM */
11576         if (nvcfg1 & (1 << 27)) {
11577                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11578                 protect = 1;
11579         }
11580
11581         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11582         switch (nvcfg1) {
11583         case FLASH_5761VENDOR_ATMEL_ADB021D:
11584         case FLASH_5761VENDOR_ATMEL_ADB041D:
11585         case FLASH_5761VENDOR_ATMEL_ADB081D:
11586         case FLASH_5761VENDOR_ATMEL_ADB161D:
11587         case FLASH_5761VENDOR_ATMEL_MDB021D:
11588         case FLASH_5761VENDOR_ATMEL_MDB041D:
11589         case FLASH_5761VENDOR_ATMEL_MDB081D:
11590         case FLASH_5761VENDOR_ATMEL_MDB161D:
11591                 tp->nvram_jedecnum = JEDEC_ATMEL;
11592                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11593                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11594                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11595                 tp->nvram_pagesize = 256;
11596                 break;
11597         case FLASH_5761VENDOR_ST_A_M45PE20:
11598         case FLASH_5761VENDOR_ST_A_M45PE40:
11599         case FLASH_5761VENDOR_ST_A_M45PE80:
11600         case FLASH_5761VENDOR_ST_A_M45PE16:
11601         case FLASH_5761VENDOR_ST_M_M45PE20:
11602         case FLASH_5761VENDOR_ST_M_M45PE40:
11603         case FLASH_5761VENDOR_ST_M_M45PE80:
11604         case FLASH_5761VENDOR_ST_M_M45PE16:
11605                 tp->nvram_jedecnum = JEDEC_ST;
11606                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11607                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11608                 tp->nvram_pagesize = 256;
11609                 break;
11610         }
11611
11612         if (protect) {
11613                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11614         } else {
11615                 switch (nvcfg1) {
11616                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11617                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11618                 case FLASH_5761VENDOR_ST_A_M45PE16:
11619                 case FLASH_5761VENDOR_ST_M_M45PE16:
11620                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11621                         break;
11622                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11623                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11624                 case FLASH_5761VENDOR_ST_A_M45PE80:
11625                 case FLASH_5761VENDOR_ST_M_M45PE80:
11626                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11627                         break;
11628                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11629                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11630                 case FLASH_5761VENDOR_ST_A_M45PE40:
11631                 case FLASH_5761VENDOR_ST_M_M45PE40:
11632                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11633                         break;
11634                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11635                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11636                 case FLASH_5761VENDOR_ST_A_M45PE20:
11637                 case FLASH_5761VENDOR_ST_M_M45PE20:
11638                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11639                         break;
11640                 }
11641         }
11642 }
11643
11644 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11645 {
11646         tp->nvram_jedecnum = JEDEC_ATMEL;
11647         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11648         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11649 }
11650
11651 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11652 {
11653         u32 nvcfg1;
11654
11655         nvcfg1 = tr32(NVRAM_CFG1);
11656
11657         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11658         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11659         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11660                 tp->nvram_jedecnum = JEDEC_ATMEL;
11661                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11662                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11663
11664                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11665                 tw32(NVRAM_CFG1, nvcfg1);
11666                 return;
11667         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11668         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11669         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11670         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11671         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11672         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11673         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11674                 tp->nvram_jedecnum = JEDEC_ATMEL;
11675                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11676                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11677
11678                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11679                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11680                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11681                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11682                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11683                         break;
11684                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11685                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11686                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11687                         break;
11688                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11689                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11690                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11691                         break;
11692                 }
11693                 break;
11694         case FLASH_5752VENDOR_ST_M45PE10:
11695         case FLASH_5752VENDOR_ST_M45PE20:
11696         case FLASH_5752VENDOR_ST_M45PE40:
11697                 tp->nvram_jedecnum = JEDEC_ST;
11698                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11699                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11700
11701                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11702                 case FLASH_5752VENDOR_ST_M45PE10:
11703                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11704                         break;
11705                 case FLASH_5752VENDOR_ST_M45PE20:
11706                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11707                         break;
11708                 case FLASH_5752VENDOR_ST_M45PE40:
11709                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11710                         break;
11711                 }
11712                 break;
11713         default:
11714                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11715                 return;
11716         }
11717
11718         tg3_nvram_get_pagesize(tp, nvcfg1);
11719         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11720                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11721 }
11722
11723
11724 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11725 {
11726         u32 nvcfg1;
11727
11728         nvcfg1 = tr32(NVRAM_CFG1);
11729
11730         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11731         case FLASH_5717VENDOR_ATMEL_EEPROM:
11732         case FLASH_5717VENDOR_MICRO_EEPROM:
11733                 tp->nvram_jedecnum = JEDEC_ATMEL;
11734                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11735                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11736
11737                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11738                 tw32(NVRAM_CFG1, nvcfg1);
11739                 return;
11740         case FLASH_5717VENDOR_ATMEL_MDB011D:
11741         case FLASH_5717VENDOR_ATMEL_ADB011B:
11742         case FLASH_5717VENDOR_ATMEL_ADB011D:
11743         case FLASH_5717VENDOR_ATMEL_MDB021D:
11744         case FLASH_5717VENDOR_ATMEL_ADB021B:
11745         case FLASH_5717VENDOR_ATMEL_ADB021D:
11746         case FLASH_5717VENDOR_ATMEL_45USPT:
11747                 tp->nvram_jedecnum = JEDEC_ATMEL;
11748                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11749                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11750
11751                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11752                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11753                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11754                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11755                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11756                         break;
11757                 default:
11758                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11759                         break;
11760                 }
11761                 break;
11762         case FLASH_5717VENDOR_ST_M_M25PE10:
11763         case FLASH_5717VENDOR_ST_A_M25PE10:
11764         case FLASH_5717VENDOR_ST_M_M45PE10:
11765         case FLASH_5717VENDOR_ST_A_M45PE10:
11766         case FLASH_5717VENDOR_ST_M_M25PE20:
11767         case FLASH_5717VENDOR_ST_A_M25PE20:
11768         case FLASH_5717VENDOR_ST_M_M45PE20:
11769         case FLASH_5717VENDOR_ST_A_M45PE20:
11770         case FLASH_5717VENDOR_ST_25USPT:
11771         case FLASH_5717VENDOR_ST_45USPT:
11772                 tp->nvram_jedecnum = JEDEC_ST;
11773                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11774                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11775
11776                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11777                 case FLASH_5717VENDOR_ST_M_M25PE20:
11778                 case FLASH_5717VENDOR_ST_A_M25PE20:
11779                 case FLASH_5717VENDOR_ST_M_M45PE20:
11780                 case FLASH_5717VENDOR_ST_A_M45PE20:
11781                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11782                         break;
11783                 default:
11784                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11785                         break;
11786                 }
11787                 break;
11788         default:
11789                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11790                 return;
11791         }
11792
11793         tg3_nvram_get_pagesize(tp, nvcfg1);
11794         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11795                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11796 }
11797
11798 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11799 static void __devinit tg3_nvram_init(struct tg3 *tp)
11800 {
11801         tw32_f(GRC_EEPROM_ADDR,
11802              (EEPROM_ADDR_FSM_RESET |
11803               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11804                EEPROM_ADDR_CLKPERD_SHIFT)));
11805
11806         msleep(1);
11807
11808         /* Enable seeprom accesses. */
11809         tw32_f(GRC_LOCAL_CTRL,
11810              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11811         udelay(100);
11812
11813         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11814             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11815                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11816
11817                 if (tg3_nvram_lock(tp)) {
11818                         netdev_warn(tp->dev,
11819                                     "Cannot get nvram lock, %s failed\n",
11820                                     __func__);
11821                         return;
11822                 }
11823                 tg3_enable_nvram_access(tp);
11824
11825                 tp->nvram_size = 0;
11826
11827                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11828                         tg3_get_5752_nvram_info(tp);
11829                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11830                         tg3_get_5755_nvram_info(tp);
11831                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11832                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11833                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11834                         tg3_get_5787_nvram_info(tp);
11835                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11836                         tg3_get_5761_nvram_info(tp);
11837                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11838                         tg3_get_5906_nvram_info(tp);
11839                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11840                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11841                         tg3_get_57780_nvram_info(tp);
11842                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11843                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11844                         tg3_get_5717_nvram_info(tp);
11845                 else
11846                         tg3_get_nvram_info(tp);
11847
11848                 if (tp->nvram_size == 0)
11849                         tg3_get_nvram_size(tp);
11850
11851                 tg3_disable_nvram_access(tp);
11852                 tg3_nvram_unlock(tp);
11853
11854         } else {
11855                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11856
11857                 tg3_get_eeprom_size(tp);
11858         }
11859 }
11860
11861 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11862                                     u32 offset, u32 len, u8 *buf)
11863 {
11864         int i, j, rc = 0;
11865         u32 val;
11866
11867         for (i = 0; i < len; i += 4) {
11868                 u32 addr;
11869                 __be32 data;
11870
11871                 addr = offset + i;
11872
11873                 memcpy(&data, buf + i, 4);
11874
11875                 /*
11876                  * The SEEPROM interface expects the data to always be opposite
11877                  * the native endian format.  We accomplish this by reversing
11878                  * all the operations that would have been performed on the
11879                  * data from a call to tg3_nvram_read_be32().
11880                  */
11881                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11882
11883                 val = tr32(GRC_EEPROM_ADDR);
11884                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11885
11886                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11887                         EEPROM_ADDR_READ);
11888                 tw32(GRC_EEPROM_ADDR, val |
11889                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11890                         (addr & EEPROM_ADDR_ADDR_MASK) |
11891                         EEPROM_ADDR_START |
11892                         EEPROM_ADDR_WRITE);
11893
11894                 for (j = 0; j < 1000; j++) {
11895                         val = tr32(GRC_EEPROM_ADDR);
11896
11897                         if (val & EEPROM_ADDR_COMPLETE)
11898                                 break;
11899                         msleep(1);
11900                 }
11901                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11902                         rc = -EBUSY;
11903                         break;
11904                 }
11905         }
11906
11907         return rc;
11908 }
11909
11910 /* offset and length are dword aligned */
11911 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11912                 u8 *buf)
11913 {
11914         int ret = 0;
11915         u32 pagesize = tp->nvram_pagesize;
11916         u32 pagemask = pagesize - 1;
11917         u32 nvram_cmd;
11918         u8 *tmp;
11919
11920         tmp = kmalloc(pagesize, GFP_KERNEL);
11921         if (tmp == NULL)
11922                 return -ENOMEM;
11923
11924         while (len) {
11925                 int j;
11926                 u32 phy_addr, page_off, size;
11927
11928                 phy_addr = offset & ~pagemask;
11929
11930                 for (j = 0; j < pagesize; j += 4) {
11931                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11932                                                   (__be32 *) (tmp + j));
11933                         if (ret)
11934                                 break;
11935                 }
11936                 if (ret)
11937                         break;
11938
11939                 page_off = offset & pagemask;
11940                 size = pagesize;
11941                 if (len < size)
11942                         size = len;
11943
11944                 len -= size;
11945
11946                 memcpy(tmp + page_off, buf, size);
11947
11948                 offset = offset + (pagesize - page_off);
11949
11950                 tg3_enable_nvram_access(tp);
11951
11952                 /*
11953                  * Before we can erase the flash page, we need
11954                  * to issue a special "write enable" command.
11955                  */
11956                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11957
11958                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11959                         break;
11960
11961                 /* Erase the target page */
11962                 tw32(NVRAM_ADDR, phy_addr);
11963
11964                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11965                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11966
11967                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11968                         break;
11969
11970                 /* Issue another write enable to start the write. */
11971                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11972
11973                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11974                         break;
11975
11976                 for (j = 0; j < pagesize; j += 4) {
11977                         __be32 data;
11978
11979                         data = *((__be32 *) (tmp + j));
11980
11981                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11982
11983                         tw32(NVRAM_ADDR, phy_addr + j);
11984
11985                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11986                                 NVRAM_CMD_WR;
11987
11988                         if (j == 0)
11989                                 nvram_cmd |= NVRAM_CMD_FIRST;
11990                         else if (j == (pagesize - 4))
11991                                 nvram_cmd |= NVRAM_CMD_LAST;
11992
11993                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11994                                 break;
11995                 }
11996                 if (ret)
11997                         break;
11998         }
11999
12000         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12001         tg3_nvram_exec_cmd(tp, nvram_cmd);
12002
12003         kfree(tmp);
12004
12005         return ret;
12006 }
12007
12008 /* offset and length are dword aligned */
12009 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12010                 u8 *buf)
12011 {
12012         int i, ret = 0;
12013
12014         for (i = 0; i < len; i += 4, offset += 4) {
12015                 u32 page_off, phy_addr, nvram_cmd;
12016                 __be32 data;
12017
12018                 memcpy(&data, buf + i, 4);
12019                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12020
12021                 page_off = offset % tp->nvram_pagesize;
12022
12023                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12024
12025                 tw32(NVRAM_ADDR, phy_addr);
12026
12027                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12028
12029                 if (page_off == 0 || i == 0)
12030                         nvram_cmd |= NVRAM_CMD_FIRST;
12031                 if (page_off == (tp->nvram_pagesize - 4))
12032                         nvram_cmd |= NVRAM_CMD_LAST;
12033
12034                 if (i == (len - 4))
12035                         nvram_cmd |= NVRAM_CMD_LAST;
12036
12037                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12038                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12039                     (tp->nvram_jedecnum == JEDEC_ST) &&
12040                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12041
12042                         if ((ret = tg3_nvram_exec_cmd(tp,
12043                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12044                                 NVRAM_CMD_DONE)))
12045
12046                                 break;
12047                 }
12048                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12049                         /* We always do complete word writes to eeprom. */
12050                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12051                 }
12052
12053                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12054                         break;
12055         }
12056         return ret;
12057 }
12058
12059 /* offset and length are dword aligned */
12060 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12061 {
12062         int ret;
12063
12064         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12065                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12066                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12067                 udelay(40);
12068         }
12069
12070         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12071                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12072         } else {
12073                 u32 grc_mode;
12074
12075                 ret = tg3_nvram_lock(tp);
12076                 if (ret)
12077                         return ret;
12078
12079                 tg3_enable_nvram_access(tp);
12080                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12081                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12082                         tw32(NVRAM_WRITE1, 0x406);
12083
12084                 grc_mode = tr32(GRC_MODE);
12085                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12086
12087                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12088                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12089
12090                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12091                                 buf);
12092                 } else {
12093                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12094                                 buf);
12095                 }
12096
12097                 grc_mode = tr32(GRC_MODE);
12098                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12099
12100                 tg3_disable_nvram_access(tp);
12101                 tg3_nvram_unlock(tp);
12102         }
12103
12104         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12105                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12106                 udelay(40);
12107         }
12108
12109         return ret;
12110 }
12111
12112 struct subsys_tbl_ent {
12113         u16 subsys_vendor, subsys_devid;
12114         u32 phy_id;
12115 };
12116
12117 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12118         /* Broadcom boards. */
12119         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12120           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12121         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12122           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12123         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12124           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12125         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12126           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12127         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12128           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12129         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12130           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12131         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12132           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12133         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12134           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12135         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12136           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12137         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12138           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12139         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12140           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12141
12142         /* 3com boards. */
12143         { TG3PCI_SUBVENDOR_ID_3COM,
12144           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12145         { TG3PCI_SUBVENDOR_ID_3COM,
12146           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12147         { TG3PCI_SUBVENDOR_ID_3COM,
12148           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12149         { TG3PCI_SUBVENDOR_ID_3COM,
12150           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12151         { TG3PCI_SUBVENDOR_ID_3COM,
12152           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12153
12154         /* DELL boards. */
12155         { TG3PCI_SUBVENDOR_ID_DELL,
12156           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12157         { TG3PCI_SUBVENDOR_ID_DELL,
12158           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12159         { TG3PCI_SUBVENDOR_ID_DELL,
12160           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12161         { TG3PCI_SUBVENDOR_ID_DELL,
12162           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12163
12164         /* Compaq boards. */
12165         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12166           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12167         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12168           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12169         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12170           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12171         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12172           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12173         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12174           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12175
12176         /* IBM boards. */
12177         { TG3PCI_SUBVENDOR_ID_IBM,
12178           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12179 };
12180
12181 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12182 {
12183         int i;
12184
12185         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12186                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12187                      tp->pdev->subsystem_vendor) &&
12188                     (subsys_id_to_phy_id[i].subsys_devid ==
12189                      tp->pdev->subsystem_device))
12190                         return &subsys_id_to_phy_id[i];
12191         }
12192         return NULL;
12193 }
12194
12195 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12196 {
12197         u32 val;
12198         u16 pmcsr;
12199
12200         /* On some early chips the SRAM cannot be accessed in D3hot state,
12201          * so need make sure we're in D0.
12202          */
12203         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12204         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12205         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12206         msleep(1);
12207
12208         /* Make sure register accesses (indirect or otherwise)
12209          * will function correctly.
12210          */
12211         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12212                                tp->misc_host_ctrl);
12213
12214         /* The memory arbiter has to be enabled in order for SRAM accesses
12215          * to succeed.  Normally on powerup the tg3 chip firmware will make
12216          * sure it is enabled, but other entities such as system netboot
12217          * code might disable it.
12218          */
12219         val = tr32(MEMARB_MODE);
12220         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12221
12222         tp->phy_id = TG3_PHY_ID_INVALID;
12223         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12224
12225         /* Assume an onboard device and WOL capable by default.  */
12226         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12227
12228         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12229                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12230                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12231                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12232                 }
12233                 val = tr32(VCPU_CFGSHDW);
12234                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12235                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12236                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12237                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12238                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12239                 goto done;
12240         }
12241
12242         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12243         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12244                 u32 nic_cfg, led_cfg;
12245                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12246                 int eeprom_phy_serdes = 0;
12247
12248                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12249                 tp->nic_sram_data_cfg = nic_cfg;
12250
12251                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12252                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12253                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12254                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12255                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12256                     (ver > 0) && (ver < 0x100))
12257                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12258
12259                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12260                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12261
12262                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12263                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12264                         eeprom_phy_serdes = 1;
12265
12266                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12267                 if (nic_phy_id != 0) {
12268                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12269                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12270
12271                         eeprom_phy_id  = (id1 >> 16) << 10;
12272                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12273                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12274                 } else
12275                         eeprom_phy_id = 0;
12276
12277                 tp->phy_id = eeprom_phy_id;
12278                 if (eeprom_phy_serdes) {
12279                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12280                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12281                         else
12282                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12283                 }
12284
12285                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12286                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12287                                     SHASTA_EXT_LED_MODE_MASK);
12288                 else
12289                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12290
12291                 switch (led_cfg) {
12292                 default:
12293                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12294                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12295                         break;
12296
12297                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12298                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12299                         break;
12300
12301                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12302                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12303
12304                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12305                          * read on some older 5700/5701 bootcode.
12306                          */
12307                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12308                             ASIC_REV_5700 ||
12309                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12310                             ASIC_REV_5701)
12311                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12312
12313                         break;
12314
12315                 case SHASTA_EXT_LED_SHARED:
12316                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12317                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12318                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12319                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12320                                                  LED_CTRL_MODE_PHY_2);
12321                         break;
12322
12323                 case SHASTA_EXT_LED_MAC:
12324                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12325                         break;
12326
12327                 case SHASTA_EXT_LED_COMBO:
12328                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12329                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12330                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12331                                                  LED_CTRL_MODE_PHY_2);
12332                         break;
12333
12334                 }
12335
12336                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12337                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12338                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12339                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12340
12341                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12342                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12343
12344                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12345                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12346                         if ((tp->pdev->subsystem_vendor ==
12347                              PCI_VENDOR_ID_ARIMA) &&
12348                             (tp->pdev->subsystem_device == 0x205a ||
12349                              tp->pdev->subsystem_device == 0x2063))
12350                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12351                 } else {
12352                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12353                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12354                 }
12355
12356                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12357                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12358                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12359                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12360                 }
12361
12362                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12363                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12364                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12365
12366                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12367                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12368                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12369
12370                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12371                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12372                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12373
12374                 if (cfg2 & (1 << 17))
12375                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12376
12377                 /* serdes signal pre-emphasis in register 0x590 set by */
12378                 /* bootcode if bit 18 is set */
12379                 if (cfg2 & (1 << 18))
12380                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12381
12382                 if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
12383                     ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12384                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
12385                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12386                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12387
12388                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12389                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12390                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12391                         u32 cfg3;
12392
12393                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12394                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12395                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12396                 }
12397
12398                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12399                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12400                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12401                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12402                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12403                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12404         }
12405 done:
12406         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12407         device_set_wakeup_enable(&tp->pdev->dev,
12408                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12409 }
12410
12411 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12412 {
12413         int i;
12414         u32 val;
12415
12416         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12417         tw32(OTP_CTRL, cmd);
12418
12419         /* Wait for up to 1 ms for command to execute. */
12420         for (i = 0; i < 100; i++) {
12421                 val = tr32(OTP_STATUS);
12422                 if (val & OTP_STATUS_CMD_DONE)
12423                         break;
12424                 udelay(10);
12425         }
12426
12427         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12428 }
12429
12430 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12431  * configuration is a 32-bit value that straddles the alignment boundary.
12432  * We do two 32-bit reads and then shift and merge the results.
12433  */
12434 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12435 {
12436         u32 bhalf_otp, thalf_otp;
12437
12438         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12439
12440         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12441                 return 0;
12442
12443         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12444
12445         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12446                 return 0;
12447
12448         thalf_otp = tr32(OTP_READ_DATA);
12449
12450         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12451
12452         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12453                 return 0;
12454
12455         bhalf_otp = tr32(OTP_READ_DATA);
12456
12457         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12458 }
12459
12460 static int __devinit tg3_phy_probe(struct tg3 *tp)
12461 {
12462         u32 hw_phy_id_1, hw_phy_id_2;
12463         u32 hw_phy_id, hw_phy_id_masked;
12464         int err;
12465
12466         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12467                 return tg3_phy_init(tp);
12468
12469         /* Reading the PHY ID register can conflict with ASF
12470          * firmware access to the PHY hardware.
12471          */
12472         err = 0;
12473         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12474             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12475                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12476         } else {
12477                 /* Now read the physical PHY_ID from the chip and verify
12478                  * that it is sane.  If it doesn't look good, we fall back
12479                  * to either the hard-coded table based PHY_ID and failing
12480                  * that the value found in the eeprom area.
12481                  */
12482                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12483                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12484
12485                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12486                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12487                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12488
12489                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12490         }
12491
12492         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12493                 tp->phy_id = hw_phy_id;
12494                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12495                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12496                 else
12497                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12498         } else {
12499                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12500                         /* Do nothing, phy ID already set up in
12501                          * tg3_get_eeprom_hw_cfg().
12502                          */
12503                 } else {
12504                         struct subsys_tbl_ent *p;
12505
12506                         /* No eeprom signature?  Try the hardcoded
12507                          * subsys device table.
12508                          */
12509                         p = tg3_lookup_by_subsys(tp);
12510                         if (!p)
12511                                 return -ENODEV;
12512
12513                         tp->phy_id = p->phy_id;
12514                         if (!tp->phy_id ||
12515                             tp->phy_id == TG3_PHY_ID_BCM8002)
12516                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12517                 }
12518         }
12519
12520         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12521             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12522               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12523              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12524               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12525                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12526
12527         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12528             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12529             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12530                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12531
12532                 tg3_readphy(tp, MII_BMSR, &bmsr);
12533                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12534                     (bmsr & BMSR_LSTATUS))
12535                         goto skip_phy_reset;
12536
12537                 err = tg3_phy_reset(tp);
12538                 if (err)
12539                         return err;
12540
12541                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12542                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12543                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12544                 tg3_ctrl = 0;
12545                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12546                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12547                                     MII_TG3_CTRL_ADV_1000_FULL);
12548                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12549                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12550                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12551                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12552                 }
12553
12554                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12555                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12556                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12557                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12558                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12559
12560                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12561                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12562
12563                         tg3_writephy(tp, MII_BMCR,
12564                                      BMCR_ANENABLE | BMCR_ANRESTART);
12565                 }
12566                 tg3_phy_set_wirespeed(tp);
12567
12568                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12569                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12570                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12571         }
12572
12573 skip_phy_reset:
12574         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12575                 err = tg3_init_5401phy_dsp(tp);
12576                 if (err)
12577                         return err;
12578
12579                 err = tg3_init_5401phy_dsp(tp);
12580         }
12581
12582         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12583                 tp->link_config.advertising =
12584                         (ADVERTISED_1000baseT_Half |
12585                          ADVERTISED_1000baseT_Full |
12586                          ADVERTISED_Autoneg |
12587                          ADVERTISED_FIBRE);
12588         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12589                 tp->link_config.advertising &=
12590                         ~(ADVERTISED_1000baseT_Half |
12591                           ADVERTISED_1000baseT_Full);
12592
12593         return err;
12594 }
12595
12596 static void __devinit tg3_read_vpd(struct tg3 *tp)
12597 {
12598         u8 *vpd_data;
12599         unsigned int block_end, rosize, len;
12600         int j, i = 0;
12601         u32 magic;
12602
12603         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12604             tg3_nvram_read(tp, 0x0, &magic))
12605                 goto out_no_vpd;
12606
12607         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12608         if (!vpd_data)
12609                 goto out_no_vpd;
12610
12611         if (magic == TG3_EEPROM_MAGIC) {
12612                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12613                         u32 tmp;
12614
12615                         /* The data is in little-endian format in NVRAM.
12616                          * Use the big-endian read routines to preserve
12617                          * the byte order as it exists in NVRAM.
12618                          */
12619                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12620                                 goto out_not_found;
12621
12622                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12623                 }
12624         } else {
12625                 ssize_t cnt;
12626                 unsigned int pos = 0;
12627
12628                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12629                         cnt = pci_read_vpd(tp->pdev, pos,
12630                                            TG3_NVM_VPD_LEN - pos,
12631                                            &vpd_data[pos]);
12632                         if (cnt == -ETIMEDOUT || cnt == -EINTR)
12633                                 cnt = 0;
12634                         else if (cnt < 0)
12635                                 goto out_not_found;
12636                 }
12637                 if (pos != TG3_NVM_VPD_LEN)
12638                         goto out_not_found;
12639         }
12640
12641         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12642                              PCI_VPD_LRDT_RO_DATA);
12643         if (i < 0)
12644                 goto out_not_found;
12645
12646         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12647         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12648         i += PCI_VPD_LRDT_TAG_SIZE;
12649
12650         if (block_end > TG3_NVM_VPD_LEN)
12651                 goto out_not_found;
12652
12653         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12654                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12655         if (j > 0) {
12656                 len = pci_vpd_info_field_size(&vpd_data[j]);
12657
12658                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12659                 if (j + len > block_end || len != 4 ||
12660                     memcmp(&vpd_data[j], "1028", 4))
12661                         goto partno;
12662
12663                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12664                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12665                 if (j < 0)
12666                         goto partno;
12667
12668                 len = pci_vpd_info_field_size(&vpd_data[j]);
12669
12670                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12671                 if (j + len > block_end)
12672                         goto partno;
12673
12674                 memcpy(tp->fw_ver, &vpd_data[j], len);
12675                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12676         }
12677
12678 partno:
12679         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12680                                       PCI_VPD_RO_KEYWORD_PARTNO);
12681         if (i < 0)
12682                 goto out_not_found;
12683
12684         len = pci_vpd_info_field_size(&vpd_data[i]);
12685
12686         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12687         if (len > TG3_BPN_SIZE ||
12688             (len + i) > TG3_NVM_VPD_LEN)
12689                 goto out_not_found;
12690
12691         memcpy(tp->board_part_number, &vpd_data[i], len);
12692
12693 out_not_found:
12694         kfree(vpd_data);
12695         if (tp->board_part_number[0])
12696                 return;
12697
12698 out_no_vpd:
12699         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12700                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12701                         strcpy(tp->board_part_number, "BCM5717");
12702                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12703                         strcpy(tp->board_part_number, "BCM5718");
12704                 else
12705                         goto nomatch;
12706         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12707                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12708                         strcpy(tp->board_part_number, "BCM57780");
12709                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12710                         strcpy(tp->board_part_number, "BCM57760");
12711                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12712                         strcpy(tp->board_part_number, "BCM57790");
12713                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12714                         strcpy(tp->board_part_number, "BCM57788");
12715                 else
12716                         goto nomatch;
12717         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12718                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12719                         strcpy(tp->board_part_number, "BCM57761");
12720                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12721                         strcpy(tp->board_part_number, "BCM57765");
12722                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12723                         strcpy(tp->board_part_number, "BCM57781");
12724                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12725                         strcpy(tp->board_part_number, "BCM57785");
12726                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12727                         strcpy(tp->board_part_number, "BCM57791");
12728                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12729                         strcpy(tp->board_part_number, "BCM57795");
12730                 else
12731                         goto nomatch;
12732         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12733                 strcpy(tp->board_part_number, "BCM95906");
12734         } else {
12735 nomatch:
12736                 strcpy(tp->board_part_number, "none");
12737         }
12738 }
12739
12740 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12741 {
12742         u32 val;
12743
12744         if (tg3_nvram_read(tp, offset, &val) ||
12745             (val & 0xfc000000) != 0x0c000000 ||
12746             tg3_nvram_read(tp, offset + 4, &val) ||
12747             val != 0)
12748                 return 0;
12749
12750         return 1;
12751 }
12752
12753 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12754 {
12755         u32 val, offset, start, ver_offset;
12756         int i, dst_off;
12757         bool newver = false;
12758
12759         if (tg3_nvram_read(tp, 0xc, &offset) ||
12760             tg3_nvram_read(tp, 0x4, &start))
12761                 return;
12762
12763         offset = tg3_nvram_logical_addr(tp, offset);
12764
12765         if (tg3_nvram_read(tp, offset, &val))
12766                 return;
12767
12768         if ((val & 0xfc000000) == 0x0c000000) {
12769                 if (tg3_nvram_read(tp, offset + 4, &val))
12770                         return;
12771
12772                 if (val == 0)
12773                         newver = true;
12774         }
12775
12776         dst_off = strlen(tp->fw_ver);
12777
12778         if (newver) {
12779                 if (TG3_VER_SIZE - dst_off < 16 ||
12780                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12781                         return;
12782
12783                 offset = offset + ver_offset - start;
12784                 for (i = 0; i < 16; i += 4) {
12785                         __be32 v;
12786                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12787                                 return;
12788
12789                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12790                 }
12791         } else {
12792                 u32 major, minor;
12793
12794                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12795                         return;
12796
12797                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12798                         TG3_NVM_BCVER_MAJSFT;
12799                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12800                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12801                          "v%d.%02d", major, minor);
12802         }
12803 }
12804
12805 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12806 {
12807         u32 val, major, minor;
12808
12809         /* Use native endian representation */
12810         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12811                 return;
12812
12813         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12814                 TG3_NVM_HWSB_CFG1_MAJSFT;
12815         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12816                 TG3_NVM_HWSB_CFG1_MINSFT;
12817
12818         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12819 }
12820
12821 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12822 {
12823         u32 offset, major, minor, build;
12824
12825         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12826
12827         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12828                 return;
12829
12830         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12831         case TG3_EEPROM_SB_REVISION_0:
12832                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12833                 break;
12834         case TG3_EEPROM_SB_REVISION_2:
12835                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12836                 break;
12837         case TG3_EEPROM_SB_REVISION_3:
12838                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12839                 break;
12840         case TG3_EEPROM_SB_REVISION_4:
12841                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12842                 break;
12843         case TG3_EEPROM_SB_REVISION_5:
12844                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12845                 break;
12846         case TG3_EEPROM_SB_REVISION_6:
12847                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12848                 break;
12849         default:
12850                 return;
12851         }
12852
12853         if (tg3_nvram_read(tp, offset, &val))
12854                 return;
12855
12856         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12857                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12858         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12859                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12860         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12861
12862         if (minor > 99 || build > 26)
12863                 return;
12864
12865         offset = strlen(tp->fw_ver);
12866         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12867                  " v%d.%02d", major, minor);
12868
12869         if (build > 0) {
12870                 offset = strlen(tp->fw_ver);
12871                 if (offset < TG3_VER_SIZE - 1)
12872                         tp->fw_ver[offset] = 'a' + build - 1;
12873         }
12874 }
12875
12876 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12877 {
12878         u32 val, offset, start;
12879         int i, vlen;
12880
12881         for (offset = TG3_NVM_DIR_START;
12882              offset < TG3_NVM_DIR_END;
12883              offset += TG3_NVM_DIRENT_SIZE) {
12884                 if (tg3_nvram_read(tp, offset, &val))
12885                         return;
12886
12887                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12888                         break;
12889         }
12890
12891         if (offset == TG3_NVM_DIR_END)
12892                 return;
12893
12894         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12895                 start = 0x08000000;
12896         else if (tg3_nvram_read(tp, offset - 4, &start))
12897                 return;
12898
12899         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12900             !tg3_fw_img_is_valid(tp, offset) ||
12901             tg3_nvram_read(tp, offset + 8, &val))
12902                 return;
12903
12904         offset += val - start;
12905
12906         vlen = strlen(tp->fw_ver);
12907
12908         tp->fw_ver[vlen++] = ',';
12909         tp->fw_ver[vlen++] = ' ';
12910
12911         for (i = 0; i < 4; i++) {
12912                 __be32 v;
12913                 if (tg3_nvram_read_be32(tp, offset, &v))
12914                         return;
12915
12916                 offset += sizeof(v);
12917
12918                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12919                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12920                         break;
12921                 }
12922
12923                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12924                 vlen += sizeof(v);
12925         }
12926 }
12927
12928 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12929 {
12930         int vlen;
12931         u32 apedata;
12932         char *fwtype;
12933
12934         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12935             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12936                 return;
12937
12938         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12939         if (apedata != APE_SEG_SIG_MAGIC)
12940                 return;
12941
12942         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12943         if (!(apedata & APE_FW_STATUS_READY))
12944                 return;
12945
12946         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12947
12948         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12949                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12950                 fwtype = "NCSI";
12951         } else {
12952                 fwtype = "DASH";
12953         }
12954
12955         vlen = strlen(tp->fw_ver);
12956
12957         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12958                  fwtype,
12959                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12960                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12961                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12962                  (apedata & APE_FW_VERSION_BLDMSK));
12963 }
12964
12965 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12966 {
12967         u32 val;
12968         bool vpd_vers = false;
12969
12970         if (tp->fw_ver[0] != 0)
12971                 vpd_vers = true;
12972
12973         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12974                 strcat(tp->fw_ver, "sb");
12975                 return;
12976         }
12977
12978         if (tg3_nvram_read(tp, 0, &val))
12979                 return;
12980
12981         if (val == TG3_EEPROM_MAGIC)
12982                 tg3_read_bc_ver(tp);
12983         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12984                 tg3_read_sb_ver(tp, val);
12985         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12986                 tg3_read_hwsb_ver(tp);
12987         else
12988                 return;
12989
12990         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12991              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12992                 goto done;
12993
12994         tg3_read_mgmtfw_ver(tp);
12995
12996 done:
12997         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12998 }
12999
13000 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13001
13002 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13003 {
13004         dev->vlan_features |= flags;
13005 }
13006
13007 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13008 {
13009         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13011                 return 4096;
13012         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13013                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13014                 return 1024;
13015         else
13016                 return 512;
13017 }
13018
13019 DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = {
13020         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13021         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13022         { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13023         { },
13024 };
13025
13026 static int __devinit tg3_get_invariants(struct tg3 *tp)
13027 {
13028         u32 misc_ctrl_reg;
13029         u32 pci_state_reg, grc_misc_cfg;
13030         u32 val;
13031         u16 pci_cmd;
13032         int err;
13033
13034         /* Force memory write invalidate off.  If we leave it on,
13035          * then on 5700_BX chips we have to enable a workaround.
13036          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13037          * to match the cacheline size.  The Broadcom driver have this
13038          * workaround but turns MWI off all the times so never uses
13039          * it.  This seems to suggest that the workaround is insufficient.
13040          */
13041         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13042         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13043         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13044
13045         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13046          * has the register indirect write enable bit set before
13047          * we try to access any of the MMIO registers.  It is also
13048          * critical that the PCI-X hw workaround situation is decided
13049          * before that as well.
13050          */
13051         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13052                               &misc_ctrl_reg);
13053
13054         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13055                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13056         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13057                 u32 prod_id_asic_rev;
13058
13059                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13060                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13061                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13062                         pci_read_config_dword(tp->pdev,
13063                                               TG3PCI_GEN2_PRODID_ASICREV,
13064                                               &prod_id_asic_rev);
13065                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13066                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13067                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13068                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13069                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13070                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13071                         pci_read_config_dword(tp->pdev,
13072                                               TG3PCI_GEN15_PRODID_ASICREV,
13073                                               &prod_id_asic_rev);
13074                 else
13075                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13076                                               &prod_id_asic_rev);
13077
13078                 tp->pci_chip_rev_id = prod_id_asic_rev;
13079         }
13080
13081         /* Wrong chip ID in 5752 A0. This code can be removed later
13082          * as A0 is not in production.
13083          */
13084         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13085                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13086
13087         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13088          * we need to disable memory and use config. cycles
13089          * only to access all registers. The 5702/03 chips
13090          * can mistakenly decode the special cycles from the
13091          * ICH chipsets as memory write cycles, causing corruption
13092          * of register and memory space. Only certain ICH bridges
13093          * will drive special cycles with non-zero data during the
13094          * address phase which can fall within the 5703's address
13095          * range. This is not an ICH bug as the PCI spec allows
13096          * non-zero address during special cycles. However, only
13097          * these ICH bridges are known to drive non-zero addresses
13098          * during special cycles.
13099          *
13100          * Since special cycles do not cross PCI bridges, we only
13101          * enable this workaround if the 5703 is on the secondary
13102          * bus of these ICH bridges.
13103          */
13104         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13105             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13106                 static struct tg3_dev_id {
13107                         u32     vendor;
13108                         u32     device;
13109                         u32     rev;
13110                 } ich_chipsets[] = {
13111                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13112                           PCI_ANY_ID },
13113                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13114                           PCI_ANY_ID },
13115                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13116                           0xa },
13117                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13118                           PCI_ANY_ID },
13119                         { },
13120                 };
13121                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13122                 struct pci_dev *bridge = NULL;
13123
13124                 while (pci_id->vendor != 0) {
13125                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13126                                                 bridge);
13127                         if (!bridge) {
13128                                 pci_id++;
13129                                 continue;
13130                         }
13131                         if (pci_id->rev != PCI_ANY_ID) {
13132                                 if (bridge->revision > pci_id->rev)
13133                                         continue;
13134                         }
13135                         if (bridge->subordinate &&
13136                             (bridge->subordinate->number ==
13137                              tp->pdev->bus->number)) {
13138
13139                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13140                                 pci_dev_put(bridge);
13141                                 break;
13142                         }
13143                 }
13144         }
13145
13146         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13147                 static struct tg3_dev_id {
13148                         u32     vendor;
13149                         u32     device;
13150                 } bridge_chipsets[] = {
13151                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13152                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13153                         { },
13154                 };
13155                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13156                 struct pci_dev *bridge = NULL;
13157
13158                 while (pci_id->vendor != 0) {
13159                         bridge = pci_get_device(pci_id->vendor,
13160                                                 pci_id->device,
13161                                                 bridge);
13162                         if (!bridge) {
13163                                 pci_id++;
13164                                 continue;
13165                         }
13166                         if (bridge->subordinate &&
13167                             (bridge->subordinate->number <=
13168                              tp->pdev->bus->number) &&
13169                             (bridge->subordinate->subordinate >=
13170                              tp->pdev->bus->number)) {
13171                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13172                                 pci_dev_put(bridge);
13173                                 break;
13174                         }
13175                 }
13176         }
13177
13178         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13179          * DMA addresses > 40-bit. This bridge may have other additional
13180          * 57xx devices behind it in some 4-port NIC designs for example.
13181          * Any tg3 device found behind the bridge will also need the 40-bit
13182          * DMA workaround.
13183          */
13184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13185             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13186                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13187                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13188                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13189         } else {
13190                 struct pci_dev *bridge = NULL;
13191
13192                 do {
13193                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13194                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13195                                                 bridge);
13196                         if (bridge && bridge->subordinate &&
13197                             (bridge->subordinate->number <=
13198                              tp->pdev->bus->number) &&
13199                             (bridge->subordinate->subordinate >=
13200                              tp->pdev->bus->number)) {
13201                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13202                                 pci_dev_put(bridge);
13203                                 break;
13204                         }
13205                 } while (bridge);
13206         }
13207
13208         /* Initialize misc host control in PCI block. */
13209         tp->misc_host_ctrl |= (misc_ctrl_reg &
13210                                MISC_HOST_CTRL_CHIPREV);
13211         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13212                                tp->misc_host_ctrl);
13213
13214         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13215             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13217                 tp->pdev_peer = tg3_find_peer(tp);
13218
13219         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13220             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13221             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13222                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13223
13224         /* Intentionally exclude ASIC_REV_5906 */
13225         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13226             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13227             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13228             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13229             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13230             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13231             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13232                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13233
13234         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13235             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13236             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13237             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13238             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13239                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13240
13241         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13242             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13243                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13244
13245         /* 5700 B0 chips do not support checksumming correctly due
13246          * to hardware bugs.
13247          */
13248         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13249                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13250         else {
13251                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13252
13253                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13254                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13255                         features |= NETIF_F_IPV6_CSUM;
13256                 tp->dev->features |= features;
13257                 vlan_features_add(tp->dev, features);
13258         }
13259
13260         /* Determine TSO capabilities */
13261         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13262                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13263         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13264                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13265                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13266         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13267                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13268                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13269                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13270                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13271         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13272                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13273                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13274                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13275                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13276                         tp->fw_needed = FIRMWARE_TG3TSO5;
13277                 else
13278                         tp->fw_needed = FIRMWARE_TG3TSO;
13279         }
13280
13281         tp->irq_max = 1;
13282
13283         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13284                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13285                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13286                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13287                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13288                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13289                      tp->pdev_peer == tp->pdev))
13290                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13291
13292                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13293                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13294                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13295                 }
13296
13297                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13298                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13299                         tp->irq_max = TG3_IRQ_MAX_VECS;
13300                 }
13301         }
13302
13303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13305             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13306                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13307         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13308                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13309                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13310         }
13311
13312         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13313                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13314
13315         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13316             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13317             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13318                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13319
13320         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13321                               &pci_state_reg);
13322
13323         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13324         if (tp->pcie_cap != 0) {
13325                 u16 lnkctl;
13326
13327                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13328
13329                 tp->pcie_readrq = 4096;
13330                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13331                         u16 word;
13332
13333                         pci_read_config_word(tp->pdev,
13334                                              tp->pcie_cap + PCI_EXP_LNKSTA,
13335                                              &word);
13336                         switch (word & PCI_EXP_LNKSTA_CLS) {
13337                         case PCI_EXP_LNKSTA_CLS_2_5GB:
13338                                 word &= PCI_EXP_LNKSTA_NLW;
13339                                 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13340                                 switch (word) {
13341                                 case 2:
13342                                         tp->pcie_readrq = 2048;
13343                                         break;
13344                                 case 4:
13345                                         tp->pcie_readrq = 1024;
13346                                         break;
13347                                 }
13348                                 break;
13349
13350                         case PCI_EXP_LNKSTA_CLS_5_0GB:
13351                                 word &= PCI_EXP_LNKSTA_NLW;
13352                                 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13353                                 switch (word) {
13354                                 case 1:
13355                                         tp->pcie_readrq = 2048;
13356                                         break;
13357                                 case 2:
13358                                         tp->pcie_readrq = 1024;
13359                                         break;
13360                                 case 4:
13361                                         tp->pcie_readrq = 512;
13362                                         break;
13363                                 }
13364                         }
13365                 }
13366
13367                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13368
13369                 pci_read_config_word(tp->pdev,
13370                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13371                                      &lnkctl);
13372                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13373                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13374                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13375                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13376                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13377                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13378                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13379                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13380                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13381                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13382                 }
13383         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13384                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13385         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13386                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13387                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13388                 if (!tp->pcix_cap) {
13389                         dev_err(&tp->pdev->dev,
13390                                 "Cannot find PCI-X capability, aborting\n");
13391                         return -EIO;
13392                 }
13393
13394                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13395                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13396         }
13397
13398         /* If we have an AMD 762 or VIA K8T800 chipset, write
13399          * reordering to the mailbox registers done by the host
13400          * controller can cause major troubles.  We read back from
13401          * every mailbox register write to force the writes to be
13402          * posted to the chip in order.
13403          */
13404         if (pci_dev_present(write_reorder_chipsets) &&
13405             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13406                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13407
13408         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13409                              &tp->pci_cacheline_sz);
13410         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13411                              &tp->pci_lat_timer);
13412         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13413             tp->pci_lat_timer < 64) {
13414                 tp->pci_lat_timer = 64;
13415                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13416                                       tp->pci_lat_timer);
13417         }
13418
13419         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13420                 /* 5700 BX chips need to have their TX producer index
13421                  * mailboxes written twice to workaround a bug.
13422                  */
13423                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13424
13425                 /* If we are in PCI-X mode, enable register write workaround.
13426                  *
13427                  * The workaround is to use indirect register accesses
13428                  * for all chip writes not to mailbox registers.
13429                  */
13430                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13431                         u32 pm_reg;
13432
13433                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13434
13435                         /* The chip can have it's power management PCI config
13436                          * space registers clobbered due to this bug.
13437                          * So explicitly force the chip into D0 here.
13438                          */
13439                         pci_read_config_dword(tp->pdev,
13440                                               tp->pm_cap + PCI_PM_CTRL,
13441                                               &pm_reg);
13442                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13443                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13444                         pci_write_config_dword(tp->pdev,
13445                                                tp->pm_cap + PCI_PM_CTRL,
13446                                                pm_reg);
13447
13448                         /* Also, force SERR#/PERR# in PCI command. */
13449                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13450                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13451                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13452                 }
13453         }
13454
13455         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13456                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13457         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13458                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13459
13460         /* Chip-specific fixup from Broadcom driver */
13461         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13462             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13463                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13464                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13465         }
13466
13467         /* Default fast path register access methods */
13468         tp->read32 = tg3_read32;
13469         tp->write32 = tg3_write32;
13470         tp->read32_mbox = tg3_read32;
13471         tp->write32_mbox = tg3_write32;
13472         tp->write32_tx_mbox = tg3_write32;
13473         tp->write32_rx_mbox = tg3_write32;
13474
13475         /* Various workaround register access methods */
13476         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13477                 tp->write32 = tg3_write_indirect_reg32;
13478         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13479                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13480                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13481                 /*
13482                  * Back to back register writes can cause problems on these
13483                  * chips, the workaround is to read back all reg writes
13484                  * except those to mailbox regs.
13485                  *
13486                  * See tg3_write_indirect_reg32().
13487                  */
13488                 tp->write32 = tg3_write_flush_reg32;
13489         }
13490
13491         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13492             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13493                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13494                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13495                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13496         }
13497
13498         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13499                 tp->read32 = tg3_read_indirect_reg32;
13500                 tp->write32 = tg3_write_indirect_reg32;
13501                 tp->read32_mbox = tg3_read_indirect_mbox;
13502                 tp->write32_mbox = tg3_write_indirect_mbox;
13503                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13504                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13505
13506                 iounmap(tp->regs);
13507                 tp->regs = NULL;
13508
13509                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13510                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13511                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13512         }
13513         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13514                 tp->read32_mbox = tg3_read32_mbox_5906;
13515                 tp->write32_mbox = tg3_write32_mbox_5906;
13516                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13517                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13518         }
13519
13520         if (tp->write32 == tg3_write_indirect_reg32 ||
13521             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13522              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13523               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13524                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13525
13526         /* Get eeprom hw config before calling tg3_set_power_state().
13527          * In particular, the TG3_FLG2_IS_NIC flag must be
13528          * determined before calling tg3_set_power_state() so that
13529          * we know whether or not to switch out of Vaux power.
13530          * When the flag is set, it means that GPIO1 is used for eeprom
13531          * write protect and also implies that it is a LOM where GPIOs
13532          * are not used to switch power.
13533          */
13534         tg3_get_eeprom_hw_cfg(tp);
13535
13536         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13537                 /* Allow reads and writes to the
13538                  * APE register and memory space.
13539                  */
13540                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13541                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13542                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13543                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13544                                        pci_state_reg);
13545         }
13546
13547         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13548             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13549             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13550             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13551             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13552                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13553
13554         /* Set up tp->grc_local_ctrl before calling tg_power_up().
13555          * GPIO1 driven high will bring 5700's external PHY out of reset.
13556          * It is also used as eeprom write protect on LOMs.
13557          */
13558         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13559         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13560             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13561                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13562                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13563         /* Unused GPIO3 must be driven as output on 5752 because there
13564          * are no pull-up resistors on unused GPIO pins.
13565          */
13566         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13567                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13568
13569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13570             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13571             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13572                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13573
13574         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13575             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13576                 /* Turn off the debug UART. */
13577                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13578                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13579                         /* Keep VMain power. */
13580                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13581                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13582         }
13583
13584         /* Force the chip into D0. */
13585         err = tg3_power_up(tp);
13586         if (err) {
13587                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13588                 return err;
13589         }
13590
13591         /* Derive initial jumbo mode from MTU assigned in
13592          * ether_setup() via the alloc_etherdev() call
13593          */
13594         if (tp->dev->mtu > ETH_DATA_LEN &&
13595             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13596                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13597
13598         /* Determine WakeOnLan speed to use. */
13599         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13600             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13601             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13602             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13603                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13604         } else {
13605                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13606         }
13607
13608         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13609                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13610
13611         /* A few boards don't want Ethernet@WireSpeed phy feature */
13612         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13613             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13614              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13615              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13616             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13617             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13618                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13619
13620         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13621             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13622                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13623         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13624                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13625
13626         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13627             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13628             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13629             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13630             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13631                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13632                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13633                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13634                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13635                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13636                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13637                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13638                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13639                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13640                 } else
13641                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13642         }
13643
13644         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13645             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13646                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13647                 if (tp->phy_otp == 0)
13648                         tp->phy_otp = TG3_OTP_DEFAULT;
13649         }
13650
13651         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13652                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13653         else
13654                 tp->mi_mode = MAC_MI_MODE_BASE;
13655
13656         tp->coalesce_mode = 0;
13657         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13658             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13659                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13660
13661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13662             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13663                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13664
13665         err = tg3_mdio_init(tp);
13666         if (err)
13667                 return err;
13668
13669         /* Initialize data/descriptor byte/word swapping. */
13670         val = tr32(GRC_MODE);
13671         val &= GRC_MODE_HOST_STACKUP;
13672         tw32(GRC_MODE, val | tp->grc_mode);
13673
13674         tg3_switch_clocks(tp);
13675
13676         /* Clear this out for sanity. */
13677         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13678
13679         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13680                               &pci_state_reg);
13681         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13682             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13683                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13684
13685                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13686                     chiprevid == CHIPREV_ID_5701_B0 ||
13687                     chiprevid == CHIPREV_ID_5701_B2 ||
13688                     chiprevid == CHIPREV_ID_5701_B5) {
13689                         void __iomem *sram_base;
13690
13691                         /* Write some dummy words into the SRAM status block
13692                          * area, see if it reads back correctly.  If the return
13693                          * value is bad, force enable the PCIX workaround.
13694                          */
13695                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13696
13697                         writel(0x00000000, sram_base);
13698                         writel(0x00000000, sram_base + 4);
13699                         writel(0xffffffff, sram_base + 4);
13700                         if (readl(sram_base) != 0x00000000)
13701                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13702                 }
13703         }
13704
13705         udelay(50);
13706         tg3_nvram_init(tp);
13707
13708         grc_misc_cfg = tr32(GRC_MISC_CFG);
13709         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13710
13711         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13712             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13713              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13714                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13715
13716         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13717             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13718                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13719         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13720                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13721                                       HOSTCC_MODE_CLRTICK_TXBD);
13722
13723                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13724                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13725                                        tp->misc_host_ctrl);
13726         }
13727
13728         /* Preserve the APE MAC_MODE bits */
13729         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13730                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13731         else
13732                 tp->mac_mode = TG3_DEF_MAC_MODE;
13733
13734         /* these are limited to 10/100 only */
13735         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13736              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13737             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13738              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13739              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13740               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13741               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13742             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13743              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13744               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13745               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13746             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13747             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13748             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13749             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13750                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13751
13752         err = tg3_phy_probe(tp);
13753         if (err) {
13754                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13755                 /* ... but do not return immediately ... */
13756                 tg3_mdio_fini(tp);
13757         }
13758
13759         tg3_read_vpd(tp);
13760         tg3_read_fw_ver(tp);
13761
13762         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13763                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13764         } else {
13765                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13766                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13767                 else
13768                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13769         }
13770
13771         /* 5700 {AX,BX} chips have a broken status block link
13772          * change bit implementation, so we must use the
13773          * status register in those cases.
13774          */
13775         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13776                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13777         else
13778                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13779
13780         /* The led_ctrl is set during tg3_phy_probe, here we might
13781          * have to force the link status polling mechanism based
13782          * upon subsystem IDs.
13783          */
13784         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13785             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13786             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13787                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13788                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13789         }
13790
13791         /* For all SERDES we poll the MAC status register. */
13792         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13793                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13794         else
13795                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13796
13797         tp->rx_offset = NET_IP_ALIGN;
13798         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13799         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13800             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13801                 tp->rx_offset = 0;
13802 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13803                 tp->rx_copy_thresh = ~(u16)0;
13804 #endif
13805         }
13806
13807         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13808         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13809         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13810
13811         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13812
13813         /* Increment the rx prod index on the rx std ring by at most
13814          * 8 for these chips to workaround hw errata.
13815          */
13816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13817             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13818             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13819                 tp->rx_std_max_post = 8;
13820
13821         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13822                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13823                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13824
13825         return err;
13826 }
13827
13828 #ifdef CONFIG_SPARC
13829 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13830 {
13831         struct net_device *dev = tp->dev;
13832         struct pci_dev *pdev = tp->pdev;
13833         struct device_node *dp = pci_device_to_OF_node(pdev);
13834         const unsigned char *addr;
13835         int len;
13836
13837         addr = of_get_property(dp, "local-mac-address", &len);
13838         if (addr && len == 6) {
13839                 memcpy(dev->dev_addr, addr, 6);
13840                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13841                 return 0;
13842         }
13843         return -ENODEV;
13844 }
13845
13846 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13847 {
13848         struct net_device *dev = tp->dev;
13849
13850         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13851         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13852         return 0;
13853 }
13854 #endif
13855
13856 static int __devinit tg3_get_device_address(struct tg3 *tp)
13857 {
13858         struct net_device *dev = tp->dev;
13859         u32 hi, lo, mac_offset;
13860         int addr_ok = 0;
13861
13862 #ifdef CONFIG_SPARC
13863         if (!tg3_get_macaddr_sparc(tp))
13864                 return 0;
13865 #endif
13866
13867         mac_offset = 0x7c;
13868         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13869             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13870                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13871                         mac_offset = 0xcc;
13872                 if (tg3_nvram_lock(tp))
13873                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13874                 else
13875                         tg3_nvram_unlock(tp);
13876         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13877                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13878                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13879                         mac_offset = 0xcc;
13880                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13881                         mac_offset += 0x18c;
13882         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13883                 mac_offset = 0x10;
13884
13885         /* First try to get it from MAC address mailbox. */
13886         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13887         if ((hi >> 16) == 0x484b) {
13888                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13889                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13890
13891                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13892                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13893                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13894                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13895                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13896
13897                 /* Some old bootcode may report a 0 MAC address in SRAM */
13898                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13899         }
13900         if (!addr_ok) {
13901                 /* Next, try NVRAM. */
13902                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13903                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13904                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13905                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13906                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13907                 }
13908                 /* Finally just fetch it out of the MAC control regs. */
13909                 else {
13910                         hi = tr32(MAC_ADDR_0_HIGH);
13911                         lo = tr32(MAC_ADDR_0_LOW);
13912
13913                         dev->dev_addr[5] = lo & 0xff;
13914                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13915                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13916                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13917                         dev->dev_addr[1] = hi & 0xff;
13918                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13919                 }
13920         }
13921
13922         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13923 #ifdef CONFIG_SPARC
13924                 if (!tg3_get_default_macaddr_sparc(tp))
13925                         return 0;
13926 #endif
13927                 return -EINVAL;
13928         }
13929         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13930         return 0;
13931 }
13932
13933 #define BOUNDARY_SINGLE_CACHELINE       1
13934 #define BOUNDARY_MULTI_CACHELINE        2
13935
13936 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13937 {
13938         int cacheline_size;
13939         u8 byte;
13940         int goal;
13941
13942         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13943         if (byte == 0)
13944                 cacheline_size = 1024;
13945         else
13946                 cacheline_size = (int) byte * 4;
13947
13948         /* On 5703 and later chips, the boundary bits have no
13949          * effect.
13950          */
13951         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13952             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13953             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13954                 goto out;
13955
13956 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13957         goal = BOUNDARY_MULTI_CACHELINE;
13958 #else
13959 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13960         goal = BOUNDARY_SINGLE_CACHELINE;
13961 #else
13962         goal = 0;
13963 #endif
13964 #endif
13965
13966         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13967                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13968                 goto out;
13969         }
13970
13971         if (!goal)
13972                 goto out;
13973
13974         /* PCI controllers on most RISC systems tend to disconnect
13975          * when a device tries to burst across a cache-line boundary.
13976          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13977          *
13978          * Unfortunately, for PCI-E there are only limited
13979          * write-side controls for this, and thus for reads
13980          * we will still get the disconnects.  We'll also waste
13981          * these PCI cycles for both read and write for chips
13982          * other than 5700 and 5701 which do not implement the
13983          * boundary bits.
13984          */
13985         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13986             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13987                 switch (cacheline_size) {
13988                 case 16:
13989                 case 32:
13990                 case 64:
13991                 case 128:
13992                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13993                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13994                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13995                         } else {
13996                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13997                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13998                         }
13999                         break;
14000
14001                 case 256:
14002                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14003                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14004                         break;
14005
14006                 default:
14007                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14008                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14009                         break;
14010                 }
14011         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14012                 switch (cacheline_size) {
14013                 case 16:
14014                 case 32:
14015                 case 64:
14016                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14017                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14018                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14019                                 break;
14020                         }
14021                         /* fallthrough */
14022                 case 128:
14023                 default:
14024                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14025                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14026                         break;
14027                 }
14028         } else {
14029                 switch (cacheline_size) {
14030                 case 16:
14031                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14032                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14033                                         DMA_RWCTRL_WRITE_BNDRY_16);
14034                                 break;
14035                         }
14036                         /* fallthrough */
14037                 case 32:
14038                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14039                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14040                                         DMA_RWCTRL_WRITE_BNDRY_32);
14041                                 break;
14042                         }
14043                         /* fallthrough */
14044                 case 64:
14045                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14046                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14047                                         DMA_RWCTRL_WRITE_BNDRY_64);
14048                                 break;
14049                         }
14050                         /* fallthrough */
14051                 case 128:
14052                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14053                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14054                                         DMA_RWCTRL_WRITE_BNDRY_128);
14055                                 break;
14056                         }
14057                         /* fallthrough */
14058                 case 256:
14059                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14060                                 DMA_RWCTRL_WRITE_BNDRY_256);
14061                         break;
14062                 case 512:
14063                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14064                                 DMA_RWCTRL_WRITE_BNDRY_512);
14065                         break;
14066                 case 1024:
14067                 default:
14068                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14069                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14070                         break;
14071                 }
14072         }
14073
14074 out:
14075         return val;
14076 }
14077
14078 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14079 {
14080         struct tg3_internal_buffer_desc test_desc;
14081         u32 sram_dma_descs;
14082         int i, ret;
14083
14084         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14085
14086         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14087         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14088         tw32(RDMAC_STATUS, 0);
14089         tw32(WDMAC_STATUS, 0);
14090
14091         tw32(BUFMGR_MODE, 0);
14092         tw32(FTQ_RESET, 0);
14093
14094         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14095         test_desc.addr_lo = buf_dma & 0xffffffff;
14096         test_desc.nic_mbuf = 0x00002100;
14097         test_desc.len = size;
14098
14099         /*
14100          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14101          * the *second* time the tg3 driver was getting loaded after an
14102          * initial scan.
14103          *
14104          * Broadcom tells me:
14105          *   ...the DMA engine is connected to the GRC block and a DMA
14106          *   reset may affect the GRC block in some unpredictable way...
14107          *   The behavior of resets to individual blocks has not been tested.
14108          *
14109          * Broadcom noted the GRC reset will also reset all sub-components.
14110          */
14111         if (to_device) {
14112                 test_desc.cqid_sqid = (13 << 8) | 2;
14113
14114                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14115                 udelay(40);
14116         } else {
14117                 test_desc.cqid_sqid = (16 << 8) | 7;
14118
14119                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14120                 udelay(40);
14121         }
14122         test_desc.flags = 0x00000005;
14123
14124         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14125                 u32 val;
14126
14127                 val = *(((u32 *)&test_desc) + i);
14128                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14129                                        sram_dma_descs + (i * sizeof(u32)));
14130                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14131         }
14132         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14133
14134         if (to_device)
14135                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14136         else
14137                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14138
14139         ret = -ENODEV;
14140         for (i = 0; i < 40; i++) {
14141                 u32 val;
14142
14143                 if (to_device)
14144                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14145                 else
14146                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14147                 if ((val & 0xffff) == sram_dma_descs) {
14148                         ret = 0;
14149                         break;
14150                 }
14151
14152                 udelay(100);
14153         }
14154
14155         return ret;
14156 }
14157
14158 #define TEST_BUFFER_SIZE        0x2000
14159
14160 DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = {
14161         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14162         { },
14163 };
14164
14165 static int __devinit tg3_test_dma(struct tg3 *tp)
14166 {
14167         dma_addr_t buf_dma;
14168         u32 *buf, saved_dma_rwctrl;
14169         int ret = 0;
14170
14171         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14172                                  &buf_dma, GFP_KERNEL);
14173         if (!buf) {
14174                 ret = -ENOMEM;
14175                 goto out_nofree;
14176         }
14177
14178         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14179                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14180
14181         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14182
14183         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14184                 goto out;
14185
14186         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14187                 /* DMA read watermark not used on PCIE */
14188                 tp->dma_rwctrl |= 0x00180000;
14189         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14190                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14191                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14192                         tp->dma_rwctrl |= 0x003f0000;
14193                 else
14194                         tp->dma_rwctrl |= 0x003f000f;
14195         } else {
14196                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14197                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14198                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14199                         u32 read_water = 0x7;
14200
14201                         /* If the 5704 is behind the EPB bridge, we can
14202                          * do the less restrictive ONE_DMA workaround for
14203                          * better performance.
14204                          */
14205                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14206                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14207                                 tp->dma_rwctrl |= 0x8000;
14208                         else if (ccval == 0x6 || ccval == 0x7)
14209                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14210
14211                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14212                                 read_water = 4;
14213                         /* Set bit 23 to enable PCIX hw bug fix */
14214                         tp->dma_rwctrl |=
14215                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14216                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14217                                 (1 << 23);
14218                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14219                         /* 5780 always in PCIX mode */
14220                         tp->dma_rwctrl |= 0x00144000;
14221                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14222                         /* 5714 always in PCIX mode */
14223                         tp->dma_rwctrl |= 0x00148000;
14224                 } else {
14225                         tp->dma_rwctrl |= 0x001b000f;
14226                 }
14227         }
14228
14229         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14230             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14231                 tp->dma_rwctrl &= 0xfffffff0;
14232
14233         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14234             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14235                 /* Remove this if it causes problems for some boards. */
14236                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14237
14238                 /* On 5700/5701 chips, we need to set this bit.
14239                  * Otherwise the chip will issue cacheline transactions
14240                  * to streamable DMA memory with not all the byte
14241                  * enables turned on.  This is an error on several
14242                  * RISC PCI controllers, in particular sparc64.
14243                  *
14244                  * On 5703/5704 chips, this bit has been reassigned
14245                  * a different meaning.  In particular, it is used
14246                  * on those chips to enable a PCI-X workaround.
14247                  */
14248                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14249         }
14250
14251         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14252
14253 #if 0
14254         /* Unneeded, already done by tg3_get_invariants.  */
14255         tg3_switch_clocks(tp);
14256 #endif
14257
14258         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14259             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14260                 goto out;
14261
14262         /* It is best to perform DMA test with maximum write burst size
14263          * to expose the 5700/5701 write DMA bug.
14264          */
14265         saved_dma_rwctrl = tp->dma_rwctrl;
14266         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14267         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14268
14269         while (1) {
14270                 u32 *p = buf, i;
14271
14272                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14273                         p[i] = i;
14274
14275                 /* Send the buffer to the chip. */
14276                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14277                 if (ret) {
14278                         dev_err(&tp->pdev->dev,
14279                                 "%s: Buffer write failed. err = %d\n",
14280                                 __func__, ret);
14281                         break;
14282                 }
14283
14284 #if 0
14285                 /* validate data reached card RAM correctly. */
14286                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14287                         u32 val;
14288                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14289                         if (le32_to_cpu(val) != p[i]) {
14290                                 dev_err(&tp->pdev->dev,
14291                                         "%s: Buffer corrupted on device! "
14292                                         "(%d != %d)\n", __func__, val, i);
14293                                 /* ret = -ENODEV here? */
14294                         }
14295                         p[i] = 0;
14296                 }
14297 #endif
14298                 /* Now read it back. */
14299                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14300                 if (ret) {
14301                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14302                                 "err = %d\n", __func__, ret);
14303                         break;
14304                 }
14305
14306                 /* Verify it. */
14307                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14308                         if (p[i] == i)
14309                                 continue;
14310
14311                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14312                             DMA_RWCTRL_WRITE_BNDRY_16) {
14313                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14314                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14315                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14316                                 break;
14317                         } else {
14318                                 dev_err(&tp->pdev->dev,
14319                                         "%s: Buffer corrupted on read back! "
14320                                         "(%d != %d)\n", __func__, p[i], i);
14321                                 ret = -ENODEV;
14322                                 goto out;
14323                         }
14324                 }
14325
14326                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14327                         /* Success. */
14328                         ret = 0;
14329                         break;
14330                 }
14331         }
14332         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14333             DMA_RWCTRL_WRITE_BNDRY_16) {
14334
14335                 /* DMA test passed without adjusting DMA boundary,
14336                  * now look for chipsets that are known to expose the
14337                  * DMA bug without failing the test.
14338                  */
14339                 if (pci_dev_present(dma_wait_state_chipsets)) {
14340                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14341                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14342                 } else {
14343                         /* Safe to use the calculated DMA boundary. */
14344                         tp->dma_rwctrl = saved_dma_rwctrl;
14345                 }
14346
14347                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14348         }
14349
14350 out:
14351         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14352 out_nofree:
14353         return ret;
14354 }
14355
14356 static void __devinit tg3_init_link_config(struct tg3 *tp)
14357 {
14358         tp->link_config.advertising =
14359                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14360                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14361                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14362                  ADVERTISED_Autoneg | ADVERTISED_MII);
14363         tp->link_config.speed = SPEED_INVALID;
14364         tp->link_config.duplex = DUPLEX_INVALID;
14365         tp->link_config.autoneg = AUTONEG_ENABLE;
14366         tp->link_config.active_speed = SPEED_INVALID;
14367         tp->link_config.active_duplex = DUPLEX_INVALID;
14368         tp->link_config.orig_speed = SPEED_INVALID;
14369         tp->link_config.orig_duplex = DUPLEX_INVALID;
14370         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14371 }
14372
14373 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14374 {
14375         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14376                 tp->bufmgr_config.mbuf_read_dma_low_water =
14377                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14378                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14379                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14380                 tp->bufmgr_config.mbuf_high_water =
14381                         DEFAULT_MB_HIGH_WATER_57765;
14382
14383                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14384                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14385                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14386                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14387                 tp->bufmgr_config.mbuf_high_water_jumbo =
14388                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14389         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14390                 tp->bufmgr_config.mbuf_read_dma_low_water =
14391                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14392                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14393                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14394                 tp->bufmgr_config.mbuf_high_water =
14395                         DEFAULT_MB_HIGH_WATER_5705;
14396                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14397                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14398                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14399                         tp->bufmgr_config.mbuf_high_water =
14400                                 DEFAULT_MB_HIGH_WATER_5906;
14401                 }
14402
14403                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14404                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14405                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14406                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14407                 tp->bufmgr_config.mbuf_high_water_jumbo =
14408                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14409         } else {
14410                 tp->bufmgr_config.mbuf_read_dma_low_water =
14411                         DEFAULT_MB_RDMA_LOW_WATER;
14412                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14413                         DEFAULT_MB_MACRX_LOW_WATER;
14414                 tp->bufmgr_config.mbuf_high_water =
14415                         DEFAULT_MB_HIGH_WATER;
14416
14417                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14418                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14419                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14420                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14421                 tp->bufmgr_config.mbuf_high_water_jumbo =
14422                         DEFAULT_MB_HIGH_WATER_JUMBO;
14423         }
14424
14425         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14426         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14427 }
14428
14429 static char * __devinit tg3_phy_string(struct tg3 *tp)
14430 {
14431         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14432         case TG3_PHY_ID_BCM5400:        return "5400";
14433         case TG3_PHY_ID_BCM5401:        return "5401";
14434         case TG3_PHY_ID_BCM5411:        return "5411";
14435         case TG3_PHY_ID_BCM5701:        return "5701";
14436         case TG3_PHY_ID_BCM5703:        return "5703";
14437         case TG3_PHY_ID_BCM5704:        return "5704";
14438         case TG3_PHY_ID_BCM5705:        return "5705";
14439         case TG3_PHY_ID_BCM5750:        return "5750";
14440         case TG3_PHY_ID_BCM5752:        return "5752";
14441         case TG3_PHY_ID_BCM5714:        return "5714";
14442         case TG3_PHY_ID_BCM5780:        return "5780";
14443         case TG3_PHY_ID_BCM5755:        return "5755";
14444         case TG3_PHY_ID_BCM5787:        return "5787";
14445         case TG3_PHY_ID_BCM5784:        return "5784";
14446         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14447         case TG3_PHY_ID_BCM5906:        return "5906";
14448         case TG3_PHY_ID_BCM5761:        return "5761";
14449         case TG3_PHY_ID_BCM5718C:       return "5718C";
14450         case TG3_PHY_ID_BCM5718S:       return "5718S";
14451         case TG3_PHY_ID_BCM57765:       return "57765";
14452         case TG3_PHY_ID_BCM5719C:       return "5719C";
14453         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14454         case 0:                 return "serdes";
14455         default:                return "unknown";
14456         }
14457 }
14458
14459 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14460 {
14461         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14462                 strcpy(str, "PCI Express");
14463                 return str;
14464         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14465                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14466
14467                 strcpy(str, "PCIX:");
14468
14469                 if ((clock_ctrl == 7) ||
14470                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14471                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14472                         strcat(str, "133MHz");
14473                 else if (clock_ctrl == 0)
14474                         strcat(str, "33MHz");
14475                 else if (clock_ctrl == 2)
14476                         strcat(str, "50MHz");
14477                 else if (clock_ctrl == 4)
14478                         strcat(str, "66MHz");
14479                 else if (clock_ctrl == 6)
14480                         strcat(str, "100MHz");
14481         } else {
14482                 strcpy(str, "PCI:");
14483                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14484                         strcat(str, "66MHz");
14485                 else
14486                         strcat(str, "33MHz");
14487         }
14488         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14489                 strcat(str, ":32-bit");
14490         else
14491                 strcat(str, ":64-bit");
14492         return str;
14493 }
14494
14495 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14496 {
14497         struct pci_dev *peer;
14498         unsigned int func, devnr = tp->pdev->devfn & ~7;
14499
14500         for (func = 0; func < 8; func++) {
14501                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14502                 if (peer && peer != tp->pdev)
14503                         break;
14504                 pci_dev_put(peer);
14505         }
14506         /* 5704 can be configured in single-port mode, set peer to
14507          * tp->pdev in that case.
14508          */
14509         if (!peer) {
14510                 peer = tp->pdev;
14511                 return peer;
14512         }
14513
14514         /*
14515          * We don't need to keep the refcount elevated; there's no way
14516          * to remove one half of this device without removing the other
14517          */
14518         pci_dev_put(peer);
14519
14520         return peer;
14521 }
14522
14523 static void __devinit tg3_init_coal(struct tg3 *tp)
14524 {
14525         struct ethtool_coalesce *ec = &tp->coal;
14526
14527         memset(ec, 0, sizeof(*ec));
14528         ec->cmd = ETHTOOL_GCOALESCE;
14529         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14530         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14531         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14532         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14533         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14534         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14535         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14536         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14537         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14538
14539         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14540                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14541                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14542                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14543                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14544                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14545         }
14546
14547         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14548                 ec->rx_coalesce_usecs_irq = 0;
14549                 ec->tx_coalesce_usecs_irq = 0;
14550                 ec->stats_block_coalesce_usecs = 0;
14551         }
14552 }
14553
14554 static const struct net_device_ops tg3_netdev_ops = {
14555         .ndo_open               = tg3_open,
14556         .ndo_stop               = tg3_close,
14557         .ndo_start_xmit         = tg3_start_xmit,
14558         .ndo_get_stats64        = tg3_get_stats64,
14559         .ndo_validate_addr      = eth_validate_addr,
14560         .ndo_set_multicast_list = tg3_set_rx_mode,
14561         .ndo_set_mac_address    = tg3_set_mac_addr,
14562         .ndo_do_ioctl           = tg3_ioctl,
14563         .ndo_tx_timeout         = tg3_tx_timeout,
14564         .ndo_change_mtu         = tg3_change_mtu,
14565 #ifdef CONFIG_NET_POLL_CONTROLLER
14566         .ndo_poll_controller    = tg3_poll_controller,
14567 #endif
14568 };
14569
14570 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14571         .ndo_open               = tg3_open,
14572         .ndo_stop               = tg3_close,
14573         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14574         .ndo_get_stats64        = tg3_get_stats64,
14575         .ndo_validate_addr      = eth_validate_addr,
14576         .ndo_set_multicast_list = tg3_set_rx_mode,
14577         .ndo_set_mac_address    = tg3_set_mac_addr,
14578         .ndo_do_ioctl           = tg3_ioctl,
14579         .ndo_tx_timeout         = tg3_tx_timeout,
14580         .ndo_change_mtu         = tg3_change_mtu,
14581 #ifdef CONFIG_NET_POLL_CONTROLLER
14582         .ndo_poll_controller    = tg3_poll_controller,
14583 #endif
14584 };
14585
14586 static int __devinit tg3_init_one(struct pci_dev *pdev,
14587                                   const struct pci_device_id *ent)
14588 {
14589         struct net_device *dev;
14590         struct tg3 *tp;
14591         int i, err, pm_cap;
14592         u32 sndmbx, rcvmbx, intmbx;
14593         char str[40];
14594         u64 dma_mask, persist_dma_mask;
14595
14596         printk_once(KERN_INFO "%s\n", version);
14597
14598         err = pci_enable_device(pdev);
14599         if (err) {
14600                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14601                 return err;
14602         }
14603
14604         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14605         if (err) {
14606                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14607                 goto err_out_disable_pdev;
14608         }
14609
14610         pci_set_master(pdev);
14611
14612         /* Find power-management capability. */
14613         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14614         if (pm_cap == 0) {
14615                 dev_err(&pdev->dev,
14616                         "Cannot find Power Management capability, aborting\n");
14617                 err = -EIO;
14618                 goto err_out_free_res;
14619         }
14620
14621         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14622         if (!dev) {
14623                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14624                 err = -ENOMEM;
14625                 goto err_out_free_res;
14626         }
14627
14628         SET_NETDEV_DEV(dev, &pdev->dev);
14629
14630         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14631
14632         tp = netdev_priv(dev);
14633         tp->pdev = pdev;
14634         tp->dev = dev;
14635         tp->pm_cap = pm_cap;
14636         tp->rx_mode = TG3_DEF_RX_MODE;
14637         tp->tx_mode = TG3_DEF_TX_MODE;
14638
14639         if (tg3_debug > 0)
14640                 tp->msg_enable = tg3_debug;
14641         else
14642                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14643
14644         /* The word/byte swap controls here control register access byte
14645          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14646          * setting below.
14647          */
14648         tp->misc_host_ctrl =
14649                 MISC_HOST_CTRL_MASK_PCI_INT |
14650                 MISC_HOST_CTRL_WORD_SWAP |
14651                 MISC_HOST_CTRL_INDIR_ACCESS |
14652                 MISC_HOST_CTRL_PCISTATE_RW;
14653
14654         /* The NONFRM (non-frame) byte/word swap controls take effect
14655          * on descriptor entries, anything which isn't packet data.
14656          *
14657          * The StrongARM chips on the board (one for tx, one for rx)
14658          * are running in big-endian mode.
14659          */
14660         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14661                         GRC_MODE_WSWAP_NONFRM_DATA);
14662 #ifdef __BIG_ENDIAN
14663         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14664 #endif
14665         spin_lock_init(&tp->lock);
14666         spin_lock_init(&tp->indirect_lock);
14667         INIT_WORK(&tp->reset_task, tg3_reset_task);
14668
14669         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14670         if (!tp->regs) {
14671                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14672                 err = -ENOMEM;
14673                 goto err_out_free_dev;
14674         }
14675
14676         tg3_init_link_config(tp);
14677
14678         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14679         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14680
14681         dev->ethtool_ops = &tg3_ethtool_ops;
14682         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14683         dev->irq = pdev->irq;
14684
14685         err = tg3_get_invariants(tp);
14686         if (err) {
14687                 dev_err(&pdev->dev,
14688                         "Problem fetching invariants of chip, aborting\n");
14689                 goto err_out_iounmap;
14690         }
14691
14692         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14693             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14694             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14695                 dev->netdev_ops = &tg3_netdev_ops;
14696         else
14697                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14698
14699
14700         /* The EPB bridge inside 5714, 5715, and 5780 and any
14701          * device behind the EPB cannot support DMA addresses > 40-bit.
14702          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14703          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14704          * do DMA address check in tg3_start_xmit().
14705          */
14706         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14707                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14708         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14709                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14710 #ifdef CONFIG_HIGHMEM
14711                 dma_mask = DMA_BIT_MASK(64);
14712 #endif
14713         } else
14714                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14715
14716         /* Configure DMA attributes. */
14717         if (dma_mask > DMA_BIT_MASK(32)) {
14718                 err = pci_set_dma_mask(pdev, dma_mask);
14719                 if (!err) {
14720                         dev->features |= NETIF_F_HIGHDMA;
14721                         err = pci_set_consistent_dma_mask(pdev,
14722                                                           persist_dma_mask);
14723                         if (err < 0) {
14724                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14725                                         "DMA for consistent allocations\n");
14726                                 goto err_out_iounmap;
14727                         }
14728                 }
14729         }
14730         if (err || dma_mask == DMA_BIT_MASK(32)) {
14731                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14732                 if (err) {
14733                         dev_err(&pdev->dev,
14734                                 "No usable DMA configuration, aborting\n");
14735                         goto err_out_iounmap;
14736                 }
14737         }
14738
14739         tg3_init_bufmgr_config(tp);
14740
14741         /* Selectively allow TSO based on operating conditions */
14742         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14743             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14744                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14745         else {
14746                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14747                 tp->fw_needed = NULL;
14748         }
14749
14750         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14751                 tp->fw_needed = FIRMWARE_TG3;
14752
14753         /* TSO is on by default on chips that support hardware TSO.
14754          * Firmware TSO on older chips gives lower performance, so it
14755          * is off by default, but can be enabled using ethtool.
14756          */
14757         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14758             (dev->features & NETIF_F_IP_CSUM)) {
14759                 dev->features |= NETIF_F_TSO;
14760                 vlan_features_add(dev, NETIF_F_TSO);
14761         }
14762         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14763             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14764                 if (dev->features & NETIF_F_IPV6_CSUM) {
14765                         dev->features |= NETIF_F_TSO6;
14766                         vlan_features_add(dev, NETIF_F_TSO6);
14767                 }
14768                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14769                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14770                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14771                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14772                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14773                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14774                         dev->features |= NETIF_F_TSO_ECN;
14775                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14776                 }
14777         }
14778
14779         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14780             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14781             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14782                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14783                 tp->rx_pending = 63;
14784         }
14785
14786         err = tg3_get_device_address(tp);
14787         if (err) {
14788                 dev_err(&pdev->dev,
14789                         "Could not obtain valid ethernet address, aborting\n");
14790                 goto err_out_iounmap;
14791         }
14792
14793         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14794                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14795                 if (!tp->aperegs) {
14796                         dev_err(&pdev->dev,
14797                                 "Cannot map APE registers, aborting\n");
14798                         err = -ENOMEM;
14799                         goto err_out_iounmap;
14800                 }
14801
14802                 tg3_ape_lock_init(tp);
14803
14804                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14805                         tg3_read_dash_ver(tp);
14806         }
14807
14808         /*
14809          * Reset chip in case UNDI or EFI driver did not shutdown
14810          * DMA self test will enable WDMAC and we'll see (spurious)
14811          * pending DMA on the PCI bus at that point.
14812          */
14813         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14814             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14815                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14816                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14817         }
14818
14819         err = tg3_test_dma(tp);
14820         if (err) {
14821                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14822                 goto err_out_apeunmap;
14823         }
14824
14825         /* flow control autonegotiation is default behavior */
14826         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14827         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14828
14829         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14830         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14831         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14832         for (i = 0; i < tp->irq_max; i++) {
14833                 struct tg3_napi *tnapi = &tp->napi[i];
14834
14835                 tnapi->tp = tp;
14836                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14837
14838                 tnapi->int_mbox = intmbx;
14839                 if (i < 4)
14840                         intmbx += 0x8;
14841                 else
14842                         intmbx += 0x4;
14843
14844                 tnapi->consmbox = rcvmbx;
14845                 tnapi->prodmbox = sndmbx;
14846
14847                 if (i)
14848                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14849                 else
14850                         tnapi->coal_now = HOSTCC_MODE_NOW;
14851
14852                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14853                         break;
14854
14855                 /*
14856                  * If we support MSIX, we'll be using RSS.  If we're using
14857                  * RSS, the first vector only handles link interrupts and the
14858                  * remaining vectors handle rx and tx interrupts.  Reuse the
14859                  * mailbox values for the next iteration.  The values we setup
14860                  * above are still useful for the single vectored mode.
14861                  */
14862                 if (!i)
14863                         continue;
14864
14865                 rcvmbx += 0x8;
14866
14867                 if (sndmbx & 0x4)
14868                         sndmbx -= 0x4;
14869                 else
14870                         sndmbx += 0xc;
14871         }
14872
14873         tg3_init_coal(tp);
14874
14875         pci_set_drvdata(pdev, dev);
14876
14877         err = register_netdev(dev);
14878         if (err) {
14879                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14880                 goto err_out_apeunmap;
14881         }
14882
14883         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14884                     tp->board_part_number,
14885                     tp->pci_chip_rev_id,
14886                     tg3_bus_string(tp, str),
14887                     dev->dev_addr);
14888
14889         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14890                 struct phy_device *phydev;
14891                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14892                 netdev_info(dev,
14893                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14894                             phydev->drv->name, dev_name(&phydev->dev));
14895         } else {
14896                 char *ethtype;
14897
14898                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14899                         ethtype = "10/100Base-TX";
14900                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14901                         ethtype = "1000Base-SX";
14902                 else
14903                         ethtype = "10/100/1000Base-T";
14904
14905                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14906                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14907                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14908         }
14909
14910         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14911                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14912                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14913                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14914                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14915                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14916         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14917                     tp->dma_rwctrl,
14918                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14919                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14920
14921         return 0;
14922
14923 err_out_apeunmap:
14924         if (tp->aperegs) {
14925                 iounmap(tp->aperegs);
14926                 tp->aperegs = NULL;
14927         }
14928
14929 err_out_iounmap:
14930         if (tp->regs) {
14931                 iounmap(tp->regs);
14932                 tp->regs = NULL;
14933         }
14934
14935 err_out_free_dev:
14936         free_netdev(dev);
14937
14938 err_out_free_res:
14939         pci_release_regions(pdev);
14940
14941 err_out_disable_pdev:
14942         pci_disable_device(pdev);
14943         pci_set_drvdata(pdev, NULL);
14944         return err;
14945 }
14946
14947 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14948 {
14949         struct net_device *dev = pci_get_drvdata(pdev);
14950
14951         if (dev) {
14952                 struct tg3 *tp = netdev_priv(dev);
14953
14954                 if (tp->fw)
14955                         release_firmware(tp->fw);
14956
14957                 cancel_work_sync(&tp->reset_task);
14958
14959                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14960                         tg3_phy_fini(tp);
14961                         tg3_mdio_fini(tp);
14962                 }
14963
14964                 unregister_netdev(dev);
14965                 if (tp->aperegs) {
14966                         iounmap(tp->aperegs);
14967                         tp->aperegs = NULL;
14968                 }
14969                 if (tp->regs) {
14970                         iounmap(tp->regs);
14971                         tp->regs = NULL;
14972                 }
14973                 free_netdev(dev);
14974                 pci_release_regions(pdev);
14975                 pci_disable_device(pdev);
14976                 pci_set_drvdata(pdev, NULL);
14977         }
14978 }
14979
14980 #ifdef CONFIG_PM_SLEEP
14981 static int tg3_suspend(struct device *device)
14982 {
14983         struct pci_dev *pdev = to_pci_dev(device);
14984         struct net_device *dev = pci_get_drvdata(pdev);
14985         struct tg3 *tp = netdev_priv(dev);
14986         int err;
14987
14988         if (!netif_running(dev))
14989                 return 0;
14990
14991         flush_work_sync(&tp->reset_task);
14992         tg3_phy_stop(tp);
14993         tg3_netif_stop(tp);
14994
14995         del_timer_sync(&tp->timer);
14996
14997         tg3_full_lock(tp, 1);
14998         tg3_disable_ints(tp);
14999         tg3_full_unlock(tp);
15000
15001         netif_device_detach(dev);
15002
15003         tg3_full_lock(tp, 0);
15004         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15005         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15006         tg3_full_unlock(tp);
15007
15008         err = tg3_power_down_prepare(tp);
15009         if (err) {
15010                 int err2;
15011
15012                 tg3_full_lock(tp, 0);
15013
15014                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15015                 err2 = tg3_restart_hw(tp, 1);
15016                 if (err2)
15017                         goto out;
15018
15019                 tp->timer.expires = jiffies + tp->timer_offset;
15020                 add_timer(&tp->timer);
15021
15022                 netif_device_attach(dev);
15023                 tg3_netif_start(tp);
15024
15025 out:
15026                 tg3_full_unlock(tp);
15027
15028                 if (!err2)
15029                         tg3_phy_start(tp);
15030         }
15031
15032         return err;
15033 }
15034
15035 static int tg3_resume(struct device *device)
15036 {
15037         struct pci_dev *pdev = to_pci_dev(device);
15038         struct net_device *dev = pci_get_drvdata(pdev);
15039         struct tg3 *tp = netdev_priv(dev);
15040         int err;
15041
15042         if (!netif_running(dev))
15043                 return 0;
15044
15045         netif_device_attach(dev);
15046
15047         tg3_full_lock(tp, 0);
15048
15049         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15050         err = tg3_restart_hw(tp, 1);
15051         if (err)
15052                 goto out;
15053
15054         tp->timer.expires = jiffies + tp->timer_offset;
15055         add_timer(&tp->timer);
15056
15057         tg3_netif_start(tp);
15058
15059 out:
15060         tg3_full_unlock(tp);
15061
15062         if (!err)
15063                 tg3_phy_start(tp);
15064
15065         return err;
15066 }
15067
15068 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15069 #define TG3_PM_OPS (&tg3_pm_ops)
15070
15071 #else
15072
15073 #define TG3_PM_OPS NULL
15074
15075 #endif /* CONFIG_PM_SLEEP */
15076
15077 static struct pci_driver tg3_driver = {
15078         .name           = DRV_MODULE_NAME,
15079         .id_table       = tg3_pci_tbl,
15080         .probe          = tg3_init_one,
15081         .remove         = __devexit_p(tg3_remove_one),
15082         .driver.pm      = TG3_PM_OPS,
15083 };
15084
15085 static int __init tg3_init(void)
15086 {
15087         return pci_register_driver(&tg3_driver);
15088 }
15089
15090 static void __exit tg3_cleanup(void)
15091 {
15092         pci_unregister_driver(&tg3_driver);
15093 }
15094
15095 module_init(tg3_init);
15096 module_exit(tg3_cleanup);