Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[pandora-kernel.git] / drivers / net / tg3.c
1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2009 Broadcom Corporation.
8  *
9  * Firmware is:
10  *      Derived from proprietary unpublished source code,
11  *      Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  *      Permission is hereby granted for the distribution of this firmware
14  *      data in hexadecimal or equivalent format, provided this copyright
15  *      notice is accompanying it.
16  */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0   0
59 #define BAR_2   2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME         "tg3"
70 #define PFX DRV_MODULE_NAME     ": "
71 #define DRV_MODULE_VERSION      "3.98"
72 #define DRV_MODULE_RELDATE      "February 25, 2009"
73
74 #define TG3_DEF_MAC_MODE        0
75 #define TG3_DEF_RX_MODE         0
76 #define TG3_DEF_TX_MODE         0
77 #define TG3_DEF_MSG_ENABLE        \
78         (NETIF_MSG_DRV          | \
79          NETIF_MSG_PROBE        | \
80          NETIF_MSG_LINK         | \
81          NETIF_MSG_TIMER        | \
82          NETIF_MSG_IFDOWN       | \
83          NETIF_MSG_IFUP         | \
84          NETIF_MSG_RX_ERR       | \
85          NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88  * and dev->tx_timeout() should be called to fix the problem
89  */
90 #define TG3_TX_TIMEOUT                  (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU                     60
94 #define TG3_MAX_MTU(tp) \
95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98  * You can't change the ring sizes, but you can change where you place
99  * them in the NIC onboard memory.
100  */
101 #define TG3_RX_RING_SIZE                512
102 #define TG3_DEF_RX_RING_PENDING         200
103 #define TG3_RX_JUMBO_RING_SIZE          256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107  * we really want to expose these constants to GCC so that modulo et
108  * al.  operations are done with shifts and masks instead of with
109  * hw multiply/modulo instructions.  Another solution would be to
110  * replace things like '% foo' with '& (foo - 1)'.
111  */
112 #define TG3_RX_RCB_RING_SIZE(tp)        \
113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
114
115 #define TG3_TX_RING_SIZE                512
116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
119                                  TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121                                  TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123                                    TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
125                                  TG3_TX_RING_SIZE)
126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
133
134 #define TG3_RAW_IP_ALIGN 2
135
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
139 #define TG3_NUM_TEST            6
140
141 #define FIRMWARE_TG3            "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
144
145 static char version[] __devinitdata =
146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION);
152 MODULE_FIRMWARE(FIRMWARE_TG3);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
156
157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug, int, 0);
159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161 static struct pci_device_id tg3_pci_tbl[] = {
162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234         {}
235 };
236
237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
239 static const struct {
240         const char string[ETH_GSTRING_LEN];
241 } ethtool_stats_keys[TG3_NUM_STATS] = {
242         { "rx_octets" },
243         { "rx_fragments" },
244         { "rx_ucast_packets" },
245         { "rx_mcast_packets" },
246         { "rx_bcast_packets" },
247         { "rx_fcs_errors" },
248         { "rx_align_errors" },
249         { "rx_xon_pause_rcvd" },
250         { "rx_xoff_pause_rcvd" },
251         { "rx_mac_ctrl_rcvd" },
252         { "rx_xoff_entered" },
253         { "rx_frame_too_long_errors" },
254         { "rx_jabbers" },
255         { "rx_undersize_packets" },
256         { "rx_in_length_errors" },
257         { "rx_out_length_errors" },
258         { "rx_64_or_less_octet_packets" },
259         { "rx_65_to_127_octet_packets" },
260         { "rx_128_to_255_octet_packets" },
261         { "rx_256_to_511_octet_packets" },
262         { "rx_512_to_1023_octet_packets" },
263         { "rx_1024_to_1522_octet_packets" },
264         { "rx_1523_to_2047_octet_packets" },
265         { "rx_2048_to_4095_octet_packets" },
266         { "rx_4096_to_8191_octet_packets" },
267         { "rx_8192_to_9022_octet_packets" },
268
269         { "tx_octets" },
270         { "tx_collisions" },
271
272         { "tx_xon_sent" },
273         { "tx_xoff_sent" },
274         { "tx_flow_control" },
275         { "tx_mac_errors" },
276         { "tx_single_collisions" },
277         { "tx_mult_collisions" },
278         { "tx_deferred" },
279         { "tx_excessive_collisions" },
280         { "tx_late_collisions" },
281         { "tx_collide_2times" },
282         { "tx_collide_3times" },
283         { "tx_collide_4times" },
284         { "tx_collide_5times" },
285         { "tx_collide_6times" },
286         { "tx_collide_7times" },
287         { "tx_collide_8times" },
288         { "tx_collide_9times" },
289         { "tx_collide_10times" },
290         { "tx_collide_11times" },
291         { "tx_collide_12times" },
292         { "tx_collide_13times" },
293         { "tx_collide_14times" },
294         { "tx_collide_15times" },
295         { "tx_ucast_packets" },
296         { "tx_mcast_packets" },
297         { "tx_bcast_packets" },
298         { "tx_carrier_sense_errors" },
299         { "tx_discards" },
300         { "tx_errors" },
301
302         { "dma_writeq_full" },
303         { "dma_write_prioq_full" },
304         { "rxbds_empty" },
305         { "rx_discards" },
306         { "rx_errors" },
307         { "rx_threshold_hit" },
308
309         { "dma_readq_full" },
310         { "dma_read_prioq_full" },
311         { "tx_comp_queue_full" },
312
313         { "ring_set_send_prod_index" },
314         { "ring_status_update" },
315         { "nic_irqs" },
316         { "nic_avoided_irqs" },
317         { "nic_tx_threshold_hit" }
318 };
319
320 static const struct {
321         const char string[ETH_GSTRING_LEN];
322 } ethtool_test_keys[TG3_NUM_TEST] = {
323         { "nvram test     (online) " },
324         { "link test      (online) " },
325         { "register test  (offline)" },
326         { "memory test    (offline)" },
327         { "loopback test  (offline)" },
328         { "interrupt test (offline)" },
329 };
330
331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332 {
333         writel(val, tp->regs + off);
334 }
335
336 static u32 tg3_read32(struct tg3 *tp, u32 off)
337 {
338         return (readl(tp->regs + off));
339 }
340
341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342 {
343         writel(val, tp->aperegs + off);
344 }
345
346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347 {
348         return (readl(tp->aperegs + off));
349 }
350
351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352 {
353         unsigned long flags;
354
355         spin_lock_irqsave(&tp->indirect_lock, flags);
356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
359 }
360
361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362 {
363         writel(val, tp->regs + off);
364         readl(tp->regs + off);
365 }
366
367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
368 {
369         unsigned long flags;
370         u32 val;
371
372         spin_lock_irqsave(&tp->indirect_lock, flags);
373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
376         return val;
377 }
378
379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380 {
381         unsigned long flags;
382
383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385                                        TG3_64BIT_REG_LOW, val);
386                 return;
387         }
388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390                                        TG3_64BIT_REG_LOW, val);
391                 return;
392         }
393
394         spin_lock_irqsave(&tp->indirect_lock, flags);
395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399         /* In indirect mode when disabling interrupts, we also need
400          * to clear the interrupt bit in the GRC local ctrl register.
401          */
402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403             (val == 0x1)) {
404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406         }
407 }
408
409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410 {
411         unsigned long flags;
412         u32 val;
413
414         spin_lock_irqsave(&tp->indirect_lock, flags);
415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
418         return val;
419 }
420
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422  * where it is unsafe to read back the register without some delay.
423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425  */
426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
427 {
428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430                 /* Non-posted methods */
431                 tp->write32(tp, off, val);
432         else {
433                 /* Posted method */
434                 tg3_write32(tp, off, val);
435                 if (usec_wait)
436                         udelay(usec_wait);
437                 tp->read32(tp, off);
438         }
439         /* Wait again after the read for the posted method to guarantee that
440          * the wait time is met.
441          */
442         if (usec_wait)
443                 udelay(usec_wait);
444 }
445
446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447 {
448         tp->write32_mbox(tp, off, val);
449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451                 tp->read32_mbox(tp, off);
452 }
453
454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
455 {
456         void __iomem *mbox = tp->regs + off;
457         writel(val, mbox);
458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459                 writel(val, mbox);
460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461                 readl(mbox);
462 }
463
464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465 {
466         return (readl(tp->regs + off + GRCMBOX_BASE));
467 }
468
469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470 {
471         writel(val, tp->regs + off + GRCMBOX_BASE);
472 }
473
474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
479
480 #define tw32(reg,val)           tp->write32(tp, reg, val)
481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg)               tp->read32(tp, reg)
484
485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486 {
487         unsigned long flags;
488
489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491                 return;
492
493         spin_lock_irqsave(&tp->indirect_lock, flags);
494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
497
498                 /* Always leave this as zero. */
499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500         } else {
501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
503
504                 /* Always leave this as zero. */
505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506         }
507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 }
509
510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511 {
512         unsigned long flags;
513
514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516                 *val = 0;
517                 return;
518         }
519
520         spin_lock_irqsave(&tp->indirect_lock, flags);
521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525                 /* Always leave this as zero. */
526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527         } else {
528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531                 /* Always leave this as zero. */
532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533         }
534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
535 }
536
537 static void tg3_ape_lock_init(struct tg3 *tp)
538 {
539         int i;
540
541         /* Make sure the driver hasn't any stale locks. */
542         for (i = 0; i < 8; i++)
543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544                                 APE_LOCK_GRANT_DRIVER);
545 }
546
547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
548 {
549         int i, off;
550         int ret = 0;
551         u32 status;
552
553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554                 return 0;
555
556         switch (locknum) {
557                 case TG3_APE_LOCK_GRC:
558                 case TG3_APE_LOCK_MEM:
559                         break;
560                 default:
561                         return -EINVAL;
562         }
563
564         off = 4 * locknum;
565
566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568         /* Wait for up to 1 millisecond to acquire lock. */
569         for (i = 0; i < 100; i++) {
570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571                 if (status == APE_LOCK_GRANT_DRIVER)
572                         break;
573                 udelay(10);
574         }
575
576         if (status != APE_LOCK_GRANT_DRIVER) {
577                 /* Revoke the lock request. */
578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579                                 APE_LOCK_GRANT_DRIVER);
580
581                 ret = -EBUSY;
582         }
583
584         return ret;
585 }
586
587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588 {
589         int off;
590
591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592                 return;
593
594         switch (locknum) {
595                 case TG3_APE_LOCK_GRC:
596                 case TG3_APE_LOCK_MEM:
597                         break;
598                 default:
599                         return;
600         }
601
602         off = 4 * locknum;
603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604 }
605
606 static void tg3_disable_ints(struct tg3 *tp)
607 {
608         tw32(TG3PCI_MISC_HOST_CTRL,
609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
611 }
612
613 static inline void tg3_cond_int(struct tg3 *tp)
614 {
615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616             (tp->hw_status->status & SD_STATUS_UPDATED))
617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
618         else
619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
621 }
622
623 static void tg3_enable_ints(struct tg3 *tp)
624 {
625         tp->irq_sync = 0;
626         wmb();
627
628         tw32(TG3PCI_MISC_HOST_CTRL,
629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631                        (tp->last_tag << 24));
632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634                                (tp->last_tag << 24));
635         tg3_cond_int(tp);
636 }
637
638 static inline unsigned int tg3_has_work(struct tg3 *tp)
639 {
640         struct tg3_hw_status *sblk = tp->hw_status;
641         unsigned int work_exists = 0;
642
643         /* check for phy events */
644         if (!(tp->tg3_flags &
645               (TG3_FLAG_USE_LINKCHG_REG |
646                TG3_FLAG_POLL_SERDES))) {
647                 if (sblk->status & SD_STATUS_LINK_CHG)
648                         work_exists = 1;
649         }
650         /* check for RX/TX work to do */
651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653                 work_exists = 1;
654
655         return work_exists;
656 }
657
658 /* tg3_restart_ints
659  *  similar to tg3_enable_ints, but it accurately determines whether there
660  *  is new work pending and can return without flushing the PIO write
661  *  which reenables interrupts
662  */
663 static void tg3_restart_ints(struct tg3 *tp)
664 {
665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666                      tp->last_tag << 24);
667         mmiowb();
668
669         /* When doing tagged status, this work check is unnecessary.
670          * The last_tag we write above tells the chip which piece of
671          * work we've completed.
672          */
673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674             tg3_has_work(tp))
675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
677 }
678
679 static inline void tg3_netif_stop(struct tg3 *tp)
680 {
681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
682         napi_disable(&tp->napi);
683         netif_tx_disable(tp->dev);
684 }
685
686 static inline void tg3_netif_start(struct tg3 *tp)
687 {
688         netif_wake_queue(tp->dev);
689         /* NOTE: unconditional netif_wake_queue is only appropriate
690          * so long as all callers are assured to have free tx slots
691          * (such as after tg3_init_hw)
692          */
693         napi_enable(&tp->napi);
694         tp->hw_status->status |= SD_STATUS_UPDATED;
695         tg3_enable_ints(tp);
696 }
697
698 static void tg3_switch_clocks(struct tg3 *tp)
699 {
700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701         u32 orig_clock_ctrl;
702
703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
705                 return;
706
707         orig_clock_ctrl = clock_ctrl;
708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709                        CLOCK_CTRL_CLKRUN_OENABLE |
710                        0x1f);
711         tp->pci_clock_ctrl = clock_ctrl;
712
713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
717                 }
718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720                             clock_ctrl |
721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722                             40);
723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
725                             40);
726         }
727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
728 }
729
730 #define PHY_BUSY_LOOPS  5000
731
732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733 {
734         u32 frame_val;
735         unsigned int loops;
736         int ret;
737
738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739                 tw32_f(MAC_MI_MODE,
740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741                 udelay(80);
742         }
743
744         *val = 0x0;
745
746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747                       MI_COM_PHY_ADDR_MASK);
748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749                       MI_COM_REG_ADDR_MASK);
750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
751
752         tw32_f(MAC_MI_COM, frame_val);
753
754         loops = PHY_BUSY_LOOPS;
755         while (loops != 0) {
756                 udelay(10);
757                 frame_val = tr32(MAC_MI_COM);
758
759                 if ((frame_val & MI_COM_BUSY) == 0) {
760                         udelay(5);
761                         frame_val = tr32(MAC_MI_COM);
762                         break;
763                 }
764                 loops -= 1;
765         }
766
767         ret = -EBUSY;
768         if (loops != 0) {
769                 *val = frame_val & MI_COM_DATA_MASK;
770                 ret = 0;
771         }
772
773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
775                 udelay(80);
776         }
777
778         return ret;
779 }
780
781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782 {
783         u32 frame_val;
784         unsigned int loops;
785         int ret;
786
787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789                 return 0;
790
791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792                 tw32_f(MAC_MI_MODE,
793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794                 udelay(80);
795         }
796
797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798                       MI_COM_PHY_ADDR_MASK);
799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800                       MI_COM_REG_ADDR_MASK);
801         frame_val |= (val & MI_COM_DATA_MASK);
802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
803
804         tw32_f(MAC_MI_COM, frame_val);
805
806         loops = PHY_BUSY_LOOPS;
807         while (loops != 0) {
808                 udelay(10);
809                 frame_val = tr32(MAC_MI_COM);
810                 if ((frame_val & MI_COM_BUSY) == 0) {
811                         udelay(5);
812                         frame_val = tr32(MAC_MI_COM);
813                         break;
814                 }
815                 loops -= 1;
816         }
817
818         ret = -EBUSY;
819         if (loops != 0)
820                 ret = 0;
821
822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
824                 udelay(80);
825         }
826
827         return ret;
828 }
829
830 static int tg3_bmcr_reset(struct tg3 *tp)
831 {
832         u32 phy_control;
833         int limit, err;
834
835         /* OK, reset it, and poll the BMCR_RESET bit until it
836          * clears or we time out.
837          */
838         phy_control = BMCR_RESET;
839         err = tg3_writephy(tp, MII_BMCR, phy_control);
840         if (err != 0)
841                 return -EBUSY;
842
843         limit = 5000;
844         while (limit--) {
845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846                 if (err != 0)
847                         return -EBUSY;
848
849                 if ((phy_control & BMCR_RESET) == 0) {
850                         udelay(40);
851                         break;
852                 }
853                 udelay(10);
854         }
855         if (limit < 0)
856                 return -EBUSY;
857
858         return 0;
859 }
860
861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862 {
863         struct tg3 *tp = bp->priv;
864         u32 val;
865
866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867                 return -EAGAIN;
868
869         if (tg3_readphy(tp, reg, &val))
870                 return -EIO;
871
872         return val;
873 }
874
875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876 {
877         struct tg3 *tp = bp->priv;
878
879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880                 return -EAGAIN;
881
882         if (tg3_writephy(tp, reg, val))
883                 return -EIO;
884
885         return 0;
886 }
887
888 static int tg3_mdio_reset(struct mii_bus *bp)
889 {
890         return 0;
891 }
892
893 static void tg3_mdio_config_5785(struct tg3 *tp)
894 {
895         u32 val;
896         struct phy_device *phydev;
897
898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900         case TG3_PHY_ID_BCM50610:
901                 val = MAC_PHYCFG2_50610_LED_MODES;
902                 break;
903         case TG3_PHY_ID_BCMAC131:
904                 val = MAC_PHYCFG2_AC131_LED_MODES;
905                 break;
906         case TG3_PHY_ID_RTL8211C:
907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908                 break;
909         case TG3_PHY_ID_RTL8201E:
910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911                 break;
912         default:
913                 return;
914         }
915
916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917                 tw32(MAC_PHYCFG2, val);
918
919                 val = tr32(MAC_PHYCFG1);
920                 val &= ~MAC_PHYCFG1_RGMII_INT;
921                 tw32(MAC_PHYCFG1, val);
922
923                 return;
924         }
925
926         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928                        MAC_PHYCFG2_FMODE_MASK_MASK |
929                        MAC_PHYCFG2_GMODE_MASK_MASK |
930                        MAC_PHYCFG2_ACT_MASK_MASK   |
931                        MAC_PHYCFG2_QUAL_MASK_MASK |
932                        MAC_PHYCFG2_INBAND_ENABLE;
933
934         tw32(MAC_PHYCFG2, val);
935
936         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
938         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943         }
944         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
946         val = tr32(MAC_EXT_RGMII_MODE);
947         val &= ~(MAC_RGMII_MODE_RX_INT_B |
948                  MAC_RGMII_MODE_RX_QUALITY |
949                  MAC_RGMII_MODE_RX_ACTIVITY |
950                  MAC_RGMII_MODE_RX_ENG_DET |
951                  MAC_RGMII_MODE_TX_ENABLE |
952                  MAC_RGMII_MODE_TX_LOWPWR |
953                  MAC_RGMII_MODE_TX_RESET);
954         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956                         val |= MAC_RGMII_MODE_RX_INT_B |
957                                MAC_RGMII_MODE_RX_QUALITY |
958                                MAC_RGMII_MODE_RX_ACTIVITY |
959                                MAC_RGMII_MODE_RX_ENG_DET;
960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961                         val |= MAC_RGMII_MODE_TX_ENABLE |
962                                MAC_RGMII_MODE_TX_LOWPWR |
963                                MAC_RGMII_MODE_TX_RESET;
964         }
965         tw32(MAC_EXT_RGMII_MODE, val);
966 }
967
968 static void tg3_mdio_start(struct tg3 *tp)
969 {
970         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
971                 mutex_lock(&tp->mdio_bus->mdio_lock);
972                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
973                 mutex_unlock(&tp->mdio_bus->mdio_lock);
974         }
975
976         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977         tw32_f(MAC_MI_MODE, tp->mi_mode);
978         udelay(80);
979
980         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982                 tg3_mdio_config_5785(tp);
983 }
984
985 static void tg3_mdio_stop(struct tg3 *tp)
986 {
987         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
988                 mutex_lock(&tp->mdio_bus->mdio_lock);
989                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
990                 mutex_unlock(&tp->mdio_bus->mdio_lock);
991         }
992 }
993
994 static int tg3_mdio_init(struct tg3 *tp)
995 {
996         int i;
997         u32 reg;
998         struct phy_device *phydev;
999
1000         tg3_mdio_start(tp);
1001
1002         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004                 return 0;
1005
1006         tp->mdio_bus = mdiobus_alloc();
1007         if (tp->mdio_bus == NULL)
1008                 return -ENOMEM;
1009
1010         tp->mdio_bus->name     = "tg3 mdio bus";
1011         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013         tp->mdio_bus->priv     = tp;
1014         tp->mdio_bus->parent   = &tp->pdev->dev;
1015         tp->mdio_bus->read     = &tg3_mdio_read;
1016         tp->mdio_bus->write    = &tg3_mdio_write;
1017         tp->mdio_bus->reset    = &tg3_mdio_reset;
1018         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1020
1021         for (i = 0; i < PHY_MAX_ADDR; i++)
1022                 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024         /* The bus registration will look for all the PHYs on the mdio bus.
1025          * Unfortunately, it does not ensure the PHY is powered up before
1026          * accessing the PHY ID registers.  A chip reset is the
1027          * quickest way to bring the device back to an operational state..
1028          */
1029         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030                 tg3_bmcr_reset(tp);
1031
1032         i = mdiobus_register(tp->mdio_bus);
1033         if (i) {
1034                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035                         tp->dev->name, i);
1036                 mdiobus_free(tp->mdio_bus);
1037                 return i;
1038         }
1039
1040         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042         if (!phydev || !phydev->drv) {
1043                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044                 mdiobus_unregister(tp->mdio_bus);
1045                 mdiobus_free(tp->mdio_bus);
1046                 return -ENODEV;
1047         }
1048
1049         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050         case TG3_PHY_ID_BCM57780:
1051                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052                 break;
1053         case TG3_PHY_ID_BCM50610:
1054                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060                 /* fallthru */
1061         case TG3_PHY_ID_RTL8211C:
1062                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063                 break;
1064         case TG3_PHY_ID_RTL8201E:
1065         case TG3_PHY_ID_BCMAC131:
1066                 phydev->interface = PHY_INTERFACE_MODE_MII;
1067                 break;
1068         }
1069
1070         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073                 tg3_mdio_config_5785(tp);
1074
1075         return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082                 mdiobus_unregister(tp->mdio_bus);
1083                 mdiobus_free(tp->mdio_bus);
1084                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085         }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091         u32 val;
1092
1093         val = tr32(GRC_RX_CPU_EVENT);
1094         val |= GRC_RX_CPU_DRIVER_EVENT;
1095         tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097         tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105         int i;
1106         unsigned int delay_cnt;
1107         long time_remain;
1108
1109         /* If enough time has passed, no wait is necessary. */
1110         time_remain = (long)(tp->last_event_jiffies + 1 +
1111                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112                       (long)jiffies;
1113         if (time_remain < 0)
1114                 return;
1115
1116         /* Check if we can shorten the wait time. */
1117         delay_cnt = jiffies_to_usecs(time_remain);
1118         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120         delay_cnt = (delay_cnt >> 3) + 1;
1121
1122         for (i = 0; i < delay_cnt; i++) {
1123                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124                         break;
1125                 udelay(8);
1126         }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132         u32 reg;
1133         u32 val;
1134
1135         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1137                 return;
1138
1139         tg3_wait_for_event_ack(tp);
1140
1141         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_BMCR, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_BMSR, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_LPA, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159         val = 0;
1160         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162                         val = reg << 16;
1163                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164                         val |= (reg & 0xffff);
1165         }
1166         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169                 val = reg << 16;
1170         else
1171                 val = 0;
1172         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174         tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179         if (!netif_carrier_ok(tp->dev)) {
1180                 if (netif_msg_link(tp))
1181                         printk(KERN_INFO PFX "%s: Link is down.\n",
1182                                tp->dev->name);
1183                 tg3_ump_link_report(tp);
1184         } else if (netif_msg_link(tp)) {
1185                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186                        tp->dev->name,
1187                        (tp->link_config.active_speed == SPEED_1000 ?
1188                         1000 :
1189                         (tp->link_config.active_speed == SPEED_100 ?
1190                          100 : 10)),
1191                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1192                         "full" : "half"));
1193
1194                 printk(KERN_INFO PFX
1195                        "%s: Flow control is %s for TX and %s for RX.\n",
1196                        tp->dev->name,
1197                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198                        "on" : "off",
1199                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200                        "on" : "off");
1201                 tg3_ump_link_report(tp);
1202         }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207         u16 miireg;
1208
1209         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210                 miireg = ADVERTISE_PAUSE_CAP;
1211         else if (flow_ctrl & FLOW_CTRL_TX)
1212                 miireg = ADVERTISE_PAUSE_ASYM;
1213         else if (flow_ctrl & FLOW_CTRL_RX)
1214                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215         else
1216                 miireg = 0;
1217
1218         return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223         u16 miireg;
1224
1225         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226                 miireg = ADVERTISE_1000XPAUSE;
1227         else if (flow_ctrl & FLOW_CTRL_TX)
1228                 miireg = ADVERTISE_1000XPSE_ASYM;
1229         else if (flow_ctrl & FLOW_CTRL_RX)
1230                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231         else
1232                 miireg = 0;
1233
1234         return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239         u8 cap = 0;
1240
1241         if (lcladv & ADVERTISE_1000XPAUSE) {
1242                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243                         if (rmtadv & LPA_1000XPAUSE)
1244                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246                                 cap = FLOW_CTRL_RX;
1247                 } else {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                 }
1251         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253                         cap = FLOW_CTRL_TX;
1254         }
1255
1256         return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261         u8 autoneg;
1262         u8 flowctrl = 0;
1263         u32 old_rx_mode = tp->rx_mode;
1264         u32 old_tx_mode = tp->tx_mode;
1265
1266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268         else
1269                 autoneg = tp->link_config.autoneg;
1270
1271         if (autoneg == AUTONEG_ENABLE &&
1272             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275                 else
1276                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277         } else
1278                 flowctrl = tp->link_config.flowctrl;
1279
1280         tp->link_config.active_flowctrl = flowctrl;
1281
1282         if (flowctrl & FLOW_CTRL_RX)
1283                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284         else
1285                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287         if (old_rx_mode != tp->rx_mode)
1288                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290         if (flowctrl & FLOW_CTRL_TX)
1291                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292         else
1293                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295         if (old_tx_mode != tp->tx_mode)
1296                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301         u8 oldflowctrl, linkmesg = 0;
1302         u32 mac_mode, lcl_adv, rmt_adv;
1303         struct tg3 *tp = netdev_priv(dev);
1304         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306         spin_lock(&tp->lock);
1307
1308         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309                                     MAC_MODE_HALF_DUPLEX);
1310
1311         oldflowctrl = tp->link_config.active_flowctrl;
1312
1313         if (phydev->link) {
1314                 lcl_adv = 0;
1315                 rmt_adv = 0;
1316
1317                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1319                 else
1320                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322                 if (phydev->duplex == DUPLEX_HALF)
1323                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1324                 else {
1325                         lcl_adv = tg3_advert_flowctrl_1000T(
1326                                   tp->link_config.flowctrl);
1327
1328                         if (phydev->pause)
1329                                 rmt_adv = LPA_PAUSE_CAP;
1330                         if (phydev->asym_pause)
1331                                 rmt_adv |= LPA_PAUSE_ASYM;
1332                 }
1333
1334                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335         } else
1336                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338         if (mac_mode != tp->mac_mode) {
1339                 tp->mac_mode = mac_mode;
1340                 tw32_f(MAC_MODE, tp->mac_mode);
1341                 udelay(40);
1342         }
1343
1344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345                 if (phydev->speed == SPEED_10)
1346                         tw32(MAC_MI_STAT,
1347                              MAC_MI_STAT_10MBPS_MODE |
1348                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349                 else
1350                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351         }
1352
1353         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354                 tw32(MAC_TX_LENGTHS,
1355                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356                       (6 << TX_LENGTHS_IPG_SHIFT) |
1357                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358         else
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366             phydev->speed != tp->link_config.active_speed ||
1367             phydev->duplex != tp->link_config.active_duplex ||
1368             oldflowctrl != tp->link_config.active_flowctrl)
1369             linkmesg = 1;
1370
1371         tp->link_config.active_speed = phydev->speed;
1372         tp->link_config.active_duplex = phydev->duplex;
1373
1374         spin_unlock(&tp->lock);
1375
1376         if (linkmesg)
1377                 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382         struct phy_device *phydev;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385                 return 0;
1386
1387         /* Bring the PHY back to a known state. */
1388         tg3_bmcr_reset(tp);
1389
1390         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392         /* Attach the MAC to the PHY. */
1393         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394                              phydev->dev_flags, phydev->interface);
1395         if (IS_ERR(phydev)) {
1396                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397                 return PTR_ERR(phydev);
1398         }
1399
1400         /* Mask with MAC supported features. */
1401         switch (phydev->interface) {
1402         case PHY_INTERFACE_MODE_GMII:
1403         case PHY_INTERFACE_MODE_RGMII:
1404                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405                         phydev->supported &= (PHY_GBIT_FEATURES |
1406                                               SUPPORTED_Pause |
1407                                               SUPPORTED_Asym_Pause);
1408                         break;
1409                 }
1410                 /* fallthru */
1411         case PHY_INTERFACE_MODE_MII:
1412                 phydev->supported &= (PHY_BASIC_FEATURES |
1413                                       SUPPORTED_Pause |
1414                                       SUPPORTED_Asym_Pause);
1415                 break;
1416         default:
1417                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418                 return -EINVAL;
1419         }
1420
1421         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423         phydev->advertising = phydev->supported;
1424
1425         return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430         struct phy_device *phydev;
1431
1432         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433                 return;
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         if (tp->link_config.phy_is_low_power) {
1438                 tp->link_config.phy_is_low_power = 0;
1439                 phydev->speed = tp->link_config.orig_speed;
1440                 phydev->duplex = tp->link_config.orig_duplex;
1441                 phydev->autoneg = tp->link_config.orig_autoneg;
1442                 phydev->advertising = tp->link_config.orig_advertising;
1443         }
1444
1445         phy_start(phydev);
1446
1447         phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453                 return;
1454
1455         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463         }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474         u32 reg;
1475
1476         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478                 return;
1479
1480         reg = MII_TG3_MISC_SHDW_WREN |
1481               MII_TG3_MISC_SHDW_SCR5_SEL |
1482               MII_TG3_MISC_SHDW_SCR5_LPED |
1483               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484               MII_TG3_MISC_SHDW_SCR5_SDTL |
1485               MII_TG3_MISC_SHDW_SCR5_C125OE;
1486         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492         reg = MII_TG3_MISC_SHDW_WREN |
1493               MII_TG3_MISC_SHDW_APD_SEL |
1494               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495         if (enable)
1496                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503         u32 phy;
1504
1505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507                 return;
1508
1509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510                 u32 ephy;
1511
1512                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1515                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516                                 if (enable)
1517                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518                                 else
1519                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521                         }
1522                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523                 }
1524         } else {
1525                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1527                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529                         if (enable)
1530                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531                         else
1532                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1534                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535                 }
1536         }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541         u32 val;
1542
1543         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544                 return;
1545
1546         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549                              (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554         u32 otp, phy;
1555
1556         if (!tp->phy_otp)
1557                 return;
1558
1559         otp = tp->phy_otp;
1560
1561         /* Enable SM_DSP clock and tx 6dB coding. */
1562         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564               MII_TG3_AUXCTL_ACTL_TX_6DB;
1565         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589         /* Turn off SM_DSP clock. */
1590         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591               MII_TG3_AUXCTL_ACTL_TX_6DB;
1592         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597         int limit = 100;
1598
1599         while (limit--) {
1600                 u32 tmp32;
1601
1602                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603                         if ((tmp32 & 0x1000) == 0)
1604                                 break;
1605                 }
1606         }
1607         if (limit < 0)
1608                 return -EBUSY;
1609
1610         return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615         static const u32 test_pat[4][6] = {
1616         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620         };
1621         int chan;
1622
1623         for (chan = 0; chan < 4; chan++) {
1624                 int i;
1625
1626                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627                              (chan * 0x2000) | 0x0200);
1628                 tg3_writephy(tp, 0x16, 0x0002);
1629
1630                 for (i = 0; i < 6; i++)
1631                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632                                      test_pat[chan][i]);
1633
1634                 tg3_writephy(tp, 0x16, 0x0202);
1635                 if (tg3_wait_macro_done(tp)) {
1636                         *resetp = 1;
1637                         return -EBUSY;
1638                 }
1639
1640                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641                              (chan * 0x2000) | 0x0200);
1642                 tg3_writephy(tp, 0x16, 0x0082);
1643                 if (tg3_wait_macro_done(tp)) {
1644                         *resetp = 1;
1645                         return -EBUSY;
1646                 }
1647
1648                 tg3_writephy(tp, 0x16, 0x0802);
1649                 if (tg3_wait_macro_done(tp)) {
1650                         *resetp = 1;
1651                         return -EBUSY;
1652                 }
1653
1654                 for (i = 0; i < 6; i += 2) {
1655                         u32 low, high;
1656
1657                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659                             tg3_wait_macro_done(tp)) {
1660                                 *resetp = 1;
1661                                 return -EBUSY;
1662                         }
1663                         low &= 0x7fff;
1664                         high &= 0x000f;
1665                         if (low != test_pat[chan][i] ||
1666                             high != test_pat[chan][i+1]) {
1667                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671                                 return -EBUSY;
1672                         }
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681         int chan;
1682
1683         for (chan = 0; chan < 4; chan++) {
1684                 int i;
1685
1686                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687                              (chan * 0x2000) | 0x0200);
1688                 tg3_writephy(tp, 0x16, 0x0002);
1689                 for (i = 0; i < 6; i++)
1690                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691                 tg3_writephy(tp, 0x16, 0x0202);
1692                 if (tg3_wait_macro_done(tp))
1693                         return -EBUSY;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701         u32 reg32, phy9_orig;
1702         int retries, do_phy_reset, err;
1703
1704         retries = 10;
1705         do_phy_reset = 1;
1706         do {
1707                 if (do_phy_reset) {
1708                         err = tg3_bmcr_reset(tp);
1709                         if (err)
1710                                 return err;
1711                         do_phy_reset = 0;
1712                 }
1713
1714                 /* Disable transmitter and interrupt.  */
1715                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716                         continue;
1717
1718                 reg32 |= 0x3000;
1719                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721                 /* Set full-duplex, 1000 mbps.  */
1722                 tg3_writephy(tp, MII_BMCR,
1723                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725                 /* Set to master mode.  */
1726                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727                         continue;
1728
1729                 tg3_writephy(tp, MII_TG3_CTRL,
1730                              (MII_TG3_CTRL_AS_MASTER |
1731                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733                 /* Enable SM_DSP_CLOCK and 6dB.  */
1734                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736                 /* Block the PHY control access.  */
1737                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741                 if (!err)
1742                         break;
1743         } while (--retries);
1744
1745         err = tg3_phy_reset_chanpat(tp);
1746         if (err)
1747                 return err;
1748
1749         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753         tg3_writephy(tp, 0x16, 0x0000);
1754
1755         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757                 /* Set Extended packet length bit for jumbo frames */
1758                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759         }
1760         else {
1761                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762         }
1763
1764         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767                 reg32 &= ~0x3000;
1768                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769         } else if (!err)
1770                 err = -EBUSY;
1771
1772         return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776  * link unless the FORCE argument is non-zero.
1777  */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780         u32 cpmuctrl;
1781         u32 phy_status;
1782         int err;
1783
1784         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785                 u32 val;
1786
1787                 val = tr32(GRC_MISC_CFG);
1788                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789                 udelay(40);
1790         }
1791         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1792         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793         if (err != 0)
1794                 return -EBUSY;
1795
1796         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797                 netif_carrier_off(tp->dev);
1798                 tg3_link_report(tp);
1799         }
1800
1801         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804                 err = tg3_phy_reset_5703_4_5(tp);
1805                 if (err)
1806                         return err;
1807                 goto out;
1808         }
1809
1810         cpmuctrl = 0;
1811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815                         tw32(TG3_CPMU_CTRL,
1816                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817         }
1818
1819         err = tg3_bmcr_reset(tp);
1820         if (err)
1821                 return err;
1822
1823         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824                 u32 phy;
1825
1826                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830         }
1831
1832         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834                 u32 val;
1835
1836                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1839                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840                         udelay(40);
1841                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842                 }
1843         }
1844
1845         tg3_phy_apply_otp(tp);
1846
1847         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848                 tg3_phy_toggle_apd(tp, true);
1849         else
1850                 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860         }
1861         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862                 tg3_writephy(tp, 0x1c, 0x8d68);
1863                 tg3_writephy(tp, 0x1c, 0x8d68);
1864         }
1865         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874         }
1875         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880                         tg3_writephy(tp, MII_TG3_TEST1,
1881                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1882                 } else
1883                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885         }
1886         /* Set Extended packet length bit (bit 14) on all chips that */
1887         /* support jumbo frames */
1888         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889                 /* Cannot do read-modify-write on 5401 */
1890                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892                 u32 phy_reg;
1893
1894                 /* Set bit 14 with read-modify-write to preserve other bits */
1895                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898         }
1899
1900         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901          * jumbo frames transmission.
1902          */
1903         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904                 u32 phy_reg;
1905
1906                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909         }
1910
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912                 /* adjust output voltage */
1913                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914         }
1915
1916         tg3_phy_toggle_automdix(tp, 1);
1917         tg3_phy_set_wirespeed(tp);
1918         return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923         struct tg3 *tp_peer = tp;
1924
1925         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926                 return;
1927
1928         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930                 struct net_device *dev_peer;
1931
1932                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933                 /* remove_one() may have been run on the peer. */
1934                 if (!dev_peer)
1935                         tp_peer = tp;
1936                 else
1937                         tp_peer = netdev_priv(dev_peer);
1938         }
1939
1940         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947                                     (GRC_LCLCTRL_GPIO_OE0 |
1948                                      GRC_LCLCTRL_GPIO_OE1 |
1949                                      GRC_LCLCTRL_GPIO_OE2 |
1950                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1951                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1952                                     100);
1953                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1954                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1956                                              GRC_LCLCTRL_GPIO_OE1 |
1957                                              GRC_LCLCTRL_GPIO_OE2 |
1958                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1959                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1960                                              tp->grc_local_ctrl;
1961                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1962
1963                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1964                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1965
1966                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1967                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1968                 } else {
1969                         u32 no_gpio2;
1970                         u32 grc_local_ctrl = 0;
1971
1972                         if (tp_peer != tp &&
1973                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1974                                 return;
1975
1976                         /* Workaround to prevent overdrawing Amps. */
1977                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1978                             ASIC_REV_5714) {
1979                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1980                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1981                                             grc_local_ctrl, 100);
1982                         }
1983
1984                         /* On 5753 and variants, GPIO2 cannot be used. */
1985                         no_gpio2 = tp->nic_sram_data_cfg &
1986                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1987
1988                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1989                                          GRC_LCLCTRL_GPIO_OE1 |
1990                                          GRC_LCLCTRL_GPIO_OE2 |
1991                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1992                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1993                         if (no_gpio2) {
1994                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1995                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1996                         }
1997                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1998                                                     grc_local_ctrl, 100);
1999
2000                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2001
2002                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2003                                                     grc_local_ctrl, 100);
2004
2005                         if (!no_gpio2) {
2006                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2007                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2008                                             grc_local_ctrl, 100);
2009                         }
2010                 }
2011         } else {
2012                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2013                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2014                         if (tp_peer != tp &&
2015                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2016                                 return;
2017
2018                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2019                                     (GRC_LCLCTRL_GPIO_OE1 |
2020                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2021
2022                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2023                                     GRC_LCLCTRL_GPIO_OE1, 100);
2024
2025                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2026                                     (GRC_LCLCTRL_GPIO_OE1 |
2027                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2028                 }
2029         }
2030 }
2031
2032 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2033 {
2034         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2035                 return 1;
2036         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2037                 if (speed != SPEED_10)
2038                         return 1;
2039         } else if (speed == SPEED_10)
2040                 return 1;
2041
2042         return 0;
2043 }
2044
2045 static int tg3_setup_phy(struct tg3 *, int);
2046
2047 #define RESET_KIND_SHUTDOWN     0
2048 #define RESET_KIND_INIT         1
2049 #define RESET_KIND_SUSPEND      2
2050
2051 static void tg3_write_sig_post_reset(struct tg3 *, int);
2052 static int tg3_halt_cpu(struct tg3 *, u32);
2053
2054 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2055 {
2056         u32 val;
2057
2058         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2059                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2060                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2061                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2062
2063                         sg_dig_ctrl |=
2064                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2065                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2066                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2067                 }
2068                 return;
2069         }
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2072                 tg3_bmcr_reset(tp);
2073                 val = tr32(GRC_MISC_CFG);
2074                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2075                 udelay(40);
2076                 return;
2077         } else if (do_low_power) {
2078                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2079                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2080
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2082                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2083                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2084                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2085                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2086         }
2087
2088         /* The PHY should not be powered down on some chips because
2089          * of bugs.
2090          */
2091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2092             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2093             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2094              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2095                 return;
2096
2097         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2098             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2099                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2100                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2101                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2102                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2103         }
2104
2105         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2106 }
2107
2108 /* tp->lock is held. */
2109 static int tg3_nvram_lock(struct tg3 *tp)
2110 {
2111         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2112                 int i;
2113
2114                 if (tp->nvram_lock_cnt == 0) {
2115                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2116                         for (i = 0; i < 8000; i++) {
2117                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2118                                         break;
2119                                 udelay(20);
2120                         }
2121                         if (i == 8000) {
2122                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2123                                 return -ENODEV;
2124                         }
2125                 }
2126                 tp->nvram_lock_cnt++;
2127         }
2128         return 0;
2129 }
2130
2131 /* tp->lock is held. */
2132 static void tg3_nvram_unlock(struct tg3 *tp)
2133 {
2134         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2135                 if (tp->nvram_lock_cnt > 0)
2136                         tp->nvram_lock_cnt--;
2137                 if (tp->nvram_lock_cnt == 0)
2138                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2139         }
2140 }
2141
2142 /* tp->lock is held. */
2143 static void tg3_enable_nvram_access(struct tg3 *tp)
2144 {
2145         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2146             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2147                 u32 nvaccess = tr32(NVRAM_ACCESS);
2148
2149                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2150         }
2151 }
2152
2153 /* tp->lock is held. */
2154 static void tg3_disable_nvram_access(struct tg3 *tp)
2155 {
2156         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2157             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2158                 u32 nvaccess = tr32(NVRAM_ACCESS);
2159
2160                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2161         }
2162 }
2163
2164 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2165                                         u32 offset, u32 *val)
2166 {
2167         u32 tmp;
2168         int i;
2169
2170         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2171                 return -EINVAL;
2172
2173         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2174                                         EEPROM_ADDR_DEVID_MASK |
2175                                         EEPROM_ADDR_READ);
2176         tw32(GRC_EEPROM_ADDR,
2177              tmp |
2178              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2179              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2180               EEPROM_ADDR_ADDR_MASK) |
2181              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2182
2183         for (i = 0; i < 1000; i++) {
2184                 tmp = tr32(GRC_EEPROM_ADDR);
2185
2186                 if (tmp & EEPROM_ADDR_COMPLETE)
2187                         break;
2188                 msleep(1);
2189         }
2190         if (!(tmp & EEPROM_ADDR_COMPLETE))
2191                 return -EBUSY;
2192
2193         *val = tr32(GRC_EEPROM_DATA);
2194         return 0;
2195 }
2196
2197 #define NVRAM_CMD_TIMEOUT 10000
2198
2199 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2200 {
2201         int i;
2202
2203         tw32(NVRAM_CMD, nvram_cmd);
2204         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2205                 udelay(10);
2206                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2207                         udelay(10);
2208                         break;
2209                 }
2210         }
2211
2212         if (i == NVRAM_CMD_TIMEOUT)
2213                 return -EBUSY;
2214
2215         return 0;
2216 }
2217
2218 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2219 {
2220         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2221             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2222             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2223            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2224             (tp->nvram_jedecnum == JEDEC_ATMEL))
2225
2226                 addr = ((addr / tp->nvram_pagesize) <<
2227                         ATMEL_AT45DB0X1B_PAGE_POS) +
2228                        (addr % tp->nvram_pagesize);
2229
2230         return addr;
2231 }
2232
2233 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2234 {
2235         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2236             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2237             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2238            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2239             (tp->nvram_jedecnum == JEDEC_ATMEL))
2240
2241                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2242                         tp->nvram_pagesize) +
2243                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2244
2245         return addr;
2246 }
2247
2248 /* NOTE: Data read in from NVRAM is byteswapped according to
2249  * the byteswapping settings for all other register accesses.
2250  * tg3 devices are BE devices, so on a BE machine, the data
2251  * returned will be exactly as it is seen in NVRAM.  On a LE
2252  * machine, the 32-bit value will be byteswapped.
2253  */
2254 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2255 {
2256         int ret;
2257
2258         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2259                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2260
2261         offset = tg3_nvram_phys_addr(tp, offset);
2262
2263         if (offset > NVRAM_ADDR_MSK)
2264                 return -EINVAL;
2265
2266         ret = tg3_nvram_lock(tp);
2267         if (ret)
2268                 return ret;
2269
2270         tg3_enable_nvram_access(tp);
2271
2272         tw32(NVRAM_ADDR, offset);
2273         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2274                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2275
2276         if (ret == 0)
2277                 *val = tr32(NVRAM_RDDATA);
2278
2279         tg3_disable_nvram_access(tp);
2280
2281         tg3_nvram_unlock(tp);
2282
2283         return ret;
2284 }
2285
2286 /* Ensures NVRAM data is in bytestream format. */
2287 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2288 {
2289         u32 v;
2290         int res = tg3_nvram_read(tp, offset, &v);
2291         if (!res)
2292                 *val = cpu_to_be32(v);
2293         return res;
2294 }
2295
2296 /* tp->lock is held. */
2297 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2298 {
2299         u32 addr_high, addr_low;
2300         int i;
2301
2302         addr_high = ((tp->dev->dev_addr[0] << 8) |
2303                      tp->dev->dev_addr[1]);
2304         addr_low = ((tp->dev->dev_addr[2] << 24) |
2305                     (tp->dev->dev_addr[3] << 16) |
2306                     (tp->dev->dev_addr[4] <<  8) |
2307                     (tp->dev->dev_addr[5] <<  0));
2308         for (i = 0; i < 4; i++) {
2309                 if (i == 1 && skip_mac_1)
2310                         continue;
2311                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2312                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2313         }
2314
2315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2316             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2317                 for (i = 0; i < 12; i++) {
2318                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2319                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2320                 }
2321         }
2322
2323         addr_high = (tp->dev->dev_addr[0] +
2324                      tp->dev->dev_addr[1] +
2325                      tp->dev->dev_addr[2] +
2326                      tp->dev->dev_addr[3] +
2327                      tp->dev->dev_addr[4] +
2328                      tp->dev->dev_addr[5]) &
2329                 TX_BACKOFF_SEED_MASK;
2330         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2331 }
2332
2333 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2334 {
2335         u32 misc_host_ctrl;
2336         bool device_should_wake, do_low_power;
2337
2338         /* Make sure register accesses (indirect or otherwise)
2339          * will function correctly.
2340          */
2341         pci_write_config_dword(tp->pdev,
2342                                TG3PCI_MISC_HOST_CTRL,
2343                                tp->misc_host_ctrl);
2344
2345         switch (state) {
2346         case PCI_D0:
2347                 pci_enable_wake(tp->pdev, state, false);
2348                 pci_set_power_state(tp->pdev, PCI_D0);
2349
2350                 /* Switch out of Vaux if it is a NIC */
2351                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2352                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2353
2354                 return 0;
2355
2356         case PCI_D1:
2357         case PCI_D2:
2358         case PCI_D3hot:
2359                 break;
2360
2361         default:
2362                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2363                         tp->dev->name, state);
2364                 return -EINVAL;
2365         }
2366
2367         /* Restore the CLKREQ setting. */
2368         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2369                 u16 lnkctl;
2370
2371                 pci_read_config_word(tp->pdev,
2372                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2373                                      &lnkctl);
2374                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2375                 pci_write_config_word(tp->pdev,
2376                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2377                                       lnkctl);
2378         }
2379
2380         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2381         tw32(TG3PCI_MISC_HOST_CTRL,
2382              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2383
2384         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2385                              device_may_wakeup(&tp->pdev->dev) &&
2386                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2387
2388         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2389                 do_low_power = false;
2390                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2391                     !tp->link_config.phy_is_low_power) {
2392                         struct phy_device *phydev;
2393                         u32 phyid, advertising;
2394
2395                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2396
2397                         tp->link_config.phy_is_low_power = 1;
2398
2399                         tp->link_config.orig_speed = phydev->speed;
2400                         tp->link_config.orig_duplex = phydev->duplex;
2401                         tp->link_config.orig_autoneg = phydev->autoneg;
2402                         tp->link_config.orig_advertising = phydev->advertising;
2403
2404                         advertising = ADVERTISED_TP |
2405                                       ADVERTISED_Pause |
2406                                       ADVERTISED_Autoneg |
2407                                       ADVERTISED_10baseT_Half;
2408
2409                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2410                             device_should_wake) {
2411                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2412                                         advertising |=
2413                                                 ADVERTISED_100baseT_Half |
2414                                                 ADVERTISED_100baseT_Full |
2415                                                 ADVERTISED_10baseT_Full;
2416                                 else
2417                                         advertising |= ADVERTISED_10baseT_Full;
2418                         }
2419
2420                         phydev->advertising = advertising;
2421
2422                         phy_start_aneg(phydev);
2423
2424                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2425                         if (phyid != TG3_PHY_ID_BCMAC131) {
2426                                 phyid &= TG3_PHY_OUI_MASK;
2427                                 if (phyid == TG3_PHY_OUI_1 ||
2428                                     phyid == TG3_PHY_OUI_2 ||
2429                                     phyid == TG3_PHY_OUI_3)
2430                                         do_low_power = true;
2431                         }
2432                 }
2433         } else {
2434                 do_low_power = true;
2435
2436                 if (tp->link_config.phy_is_low_power == 0) {
2437                         tp->link_config.phy_is_low_power = 1;
2438                         tp->link_config.orig_speed = tp->link_config.speed;
2439                         tp->link_config.orig_duplex = tp->link_config.duplex;
2440                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2441                 }
2442
2443                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2444                         tp->link_config.speed = SPEED_10;
2445                         tp->link_config.duplex = DUPLEX_HALF;
2446                         tp->link_config.autoneg = AUTONEG_ENABLE;
2447                         tg3_setup_phy(tp, 0);
2448                 }
2449         }
2450
2451         __tg3_set_mac_addr(tp, 0);
2452
2453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2454                 u32 val;
2455
2456                 val = tr32(GRC_VCPU_EXT_CTRL);
2457                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2458         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2459                 int i;
2460                 u32 val;
2461
2462                 for (i = 0; i < 200; i++) {
2463                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2464                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2465                                 break;
2466                         msleep(1);
2467                 }
2468         }
2469         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2470                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2471                                                      WOL_DRV_STATE_SHUTDOWN |
2472                                                      WOL_DRV_WOL |
2473                                                      WOL_SET_MAGIC_PKT);
2474
2475         if (device_should_wake) {
2476                 u32 mac_mode;
2477
2478                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2479                         if (do_low_power) {
2480                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2481                                 udelay(40);
2482                         }
2483
2484                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2485                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2486                         else
2487                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2488
2489                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2490                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2491                             ASIC_REV_5700) {
2492                                 u32 speed = (tp->tg3_flags &
2493                                              TG3_FLAG_WOL_SPEED_100MB) ?
2494                                              SPEED_100 : SPEED_10;
2495                                 if (tg3_5700_link_polarity(tp, speed))
2496                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2497                                 else
2498                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2499                         }
2500                 } else {
2501                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2502                 }
2503
2504                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2505                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2506
2507                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2508                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2509                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2510                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2511                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2512                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2513
2514                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2515                         mac_mode |= tp->mac_mode &
2516                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2517                         if (mac_mode & MAC_MODE_APE_TX_EN)
2518                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2519                 }
2520
2521                 tw32_f(MAC_MODE, mac_mode);
2522                 udelay(100);
2523
2524                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2525                 udelay(10);
2526         }
2527
2528         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2529             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2530              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2531                 u32 base_val;
2532
2533                 base_val = tp->pci_clock_ctrl;
2534                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2535                              CLOCK_CTRL_TXCLK_DISABLE);
2536
2537                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2538                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2539         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2540                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2541                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2542                 /* do nothing */
2543         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2544                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2545                 u32 newbits1, newbits2;
2546
2547                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2548                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2549                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2550                                     CLOCK_CTRL_TXCLK_DISABLE |
2551                                     CLOCK_CTRL_ALTCLK);
2552                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2553                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2554                         newbits1 = CLOCK_CTRL_625_CORE;
2555                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2556                 } else {
2557                         newbits1 = CLOCK_CTRL_ALTCLK;
2558                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2559                 }
2560
2561                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2562                             40);
2563
2564                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2565                             40);
2566
2567                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2568                         u32 newbits3;
2569
2570                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2571                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2572                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2573                                             CLOCK_CTRL_TXCLK_DISABLE |
2574                                             CLOCK_CTRL_44MHZ_CORE);
2575                         } else {
2576                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2577                         }
2578
2579                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2580                                     tp->pci_clock_ctrl | newbits3, 40);
2581                 }
2582         }
2583
2584         if (!(device_should_wake) &&
2585             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2586                 tg3_power_down_phy(tp, do_low_power);
2587
2588         tg3_frob_aux_power(tp);
2589
2590         /* Workaround for unstable PLL clock */
2591         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2592             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2593                 u32 val = tr32(0x7d00);
2594
2595                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2596                 tw32(0x7d00, val);
2597                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2598                         int err;
2599
2600                         err = tg3_nvram_lock(tp);
2601                         tg3_halt_cpu(tp, RX_CPU_BASE);
2602                         if (!err)
2603                                 tg3_nvram_unlock(tp);
2604                 }
2605         }
2606
2607         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2608
2609         if (device_should_wake)
2610                 pci_enable_wake(tp->pdev, state, true);
2611
2612         /* Finally, set the new power state. */
2613         pci_set_power_state(tp->pdev, state);
2614
2615         return 0;
2616 }
2617
2618 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2619 {
2620         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2621         case MII_TG3_AUX_STAT_10HALF:
2622                 *speed = SPEED_10;
2623                 *duplex = DUPLEX_HALF;
2624                 break;
2625
2626         case MII_TG3_AUX_STAT_10FULL:
2627                 *speed = SPEED_10;
2628                 *duplex = DUPLEX_FULL;
2629                 break;
2630
2631         case MII_TG3_AUX_STAT_100HALF:
2632                 *speed = SPEED_100;
2633                 *duplex = DUPLEX_HALF;
2634                 break;
2635
2636         case MII_TG3_AUX_STAT_100FULL:
2637                 *speed = SPEED_100;
2638                 *duplex = DUPLEX_FULL;
2639                 break;
2640
2641         case MII_TG3_AUX_STAT_1000HALF:
2642                 *speed = SPEED_1000;
2643                 *duplex = DUPLEX_HALF;
2644                 break;
2645
2646         case MII_TG3_AUX_STAT_1000FULL:
2647                 *speed = SPEED_1000;
2648                 *duplex = DUPLEX_FULL;
2649                 break;
2650
2651         default:
2652                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2653                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2654                                  SPEED_10;
2655                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2656                                   DUPLEX_HALF;
2657                         break;
2658                 }
2659                 *speed = SPEED_INVALID;
2660                 *duplex = DUPLEX_INVALID;
2661                 break;
2662         }
2663 }
2664
2665 static void tg3_phy_copper_begin(struct tg3 *tp)
2666 {
2667         u32 new_adv;
2668         int i;
2669
2670         if (tp->link_config.phy_is_low_power) {
2671                 /* Entering low power mode.  Disable gigabit and
2672                  * 100baseT advertisements.
2673                  */
2674                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2675
2676                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2677                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2678                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2679                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2680
2681                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2682         } else if (tp->link_config.speed == SPEED_INVALID) {
2683                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2684                         tp->link_config.advertising &=
2685                                 ~(ADVERTISED_1000baseT_Half |
2686                                   ADVERTISED_1000baseT_Full);
2687
2688                 new_adv = ADVERTISE_CSMA;
2689                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2690                         new_adv |= ADVERTISE_10HALF;
2691                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2692                         new_adv |= ADVERTISE_10FULL;
2693                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2694                         new_adv |= ADVERTISE_100HALF;
2695                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2696                         new_adv |= ADVERTISE_100FULL;
2697
2698                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2699
2700                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2701
2702                 if (tp->link_config.advertising &
2703                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2704                         new_adv = 0;
2705                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2706                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2707                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2708                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2709                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2710                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2711                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2712                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2713                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2714                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2715                 } else {
2716                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2717                 }
2718         } else {
2719                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2720                 new_adv |= ADVERTISE_CSMA;
2721
2722                 /* Asking for a specific link mode. */
2723                 if (tp->link_config.speed == SPEED_1000) {
2724                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2725
2726                         if (tp->link_config.duplex == DUPLEX_FULL)
2727                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2728                         else
2729                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2730                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2731                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2732                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2733                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2734                 } else {
2735                         if (tp->link_config.speed == SPEED_100) {
2736                                 if (tp->link_config.duplex == DUPLEX_FULL)
2737                                         new_adv |= ADVERTISE_100FULL;
2738                                 else
2739                                         new_adv |= ADVERTISE_100HALF;
2740                         } else {
2741                                 if (tp->link_config.duplex == DUPLEX_FULL)
2742                                         new_adv |= ADVERTISE_10FULL;
2743                                 else
2744                                         new_adv |= ADVERTISE_10HALF;
2745                         }
2746                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747
2748                         new_adv = 0;
2749                 }
2750
2751                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2752         }
2753
2754         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2755             tp->link_config.speed != SPEED_INVALID) {
2756                 u32 bmcr, orig_bmcr;
2757
2758                 tp->link_config.active_speed = tp->link_config.speed;
2759                 tp->link_config.active_duplex = tp->link_config.duplex;
2760
2761                 bmcr = 0;
2762                 switch (tp->link_config.speed) {
2763                 default:
2764                 case SPEED_10:
2765                         break;
2766
2767                 case SPEED_100:
2768                         bmcr |= BMCR_SPEED100;
2769                         break;
2770
2771                 case SPEED_1000:
2772                         bmcr |= TG3_BMCR_SPEED1000;
2773                         break;
2774                 }
2775
2776                 if (tp->link_config.duplex == DUPLEX_FULL)
2777                         bmcr |= BMCR_FULLDPLX;
2778
2779                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2780                     (bmcr != orig_bmcr)) {
2781                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2782                         for (i = 0; i < 1500; i++) {
2783                                 u32 tmp;
2784
2785                                 udelay(10);
2786                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2787                                     tg3_readphy(tp, MII_BMSR, &tmp))
2788                                         continue;
2789                                 if (!(tmp & BMSR_LSTATUS)) {
2790                                         udelay(40);
2791                                         break;
2792                                 }
2793                         }
2794                         tg3_writephy(tp, MII_BMCR, bmcr);
2795                         udelay(40);
2796                 }
2797         } else {
2798                 tg3_writephy(tp, MII_BMCR,
2799                              BMCR_ANENABLE | BMCR_ANRESTART);
2800         }
2801 }
2802
2803 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2804 {
2805         int err;
2806
2807         /* Turn off tap power management. */
2808         /* Set Extended packet length bit */
2809         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2810
2811         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2812         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2813
2814         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2815         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2816
2817         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2818         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2819
2820         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2821         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2822
2823         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2824         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2825
2826         udelay(40);
2827
2828         return err;
2829 }
2830
2831 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2832 {
2833         u32 adv_reg, all_mask = 0;
2834
2835         if (mask & ADVERTISED_10baseT_Half)
2836                 all_mask |= ADVERTISE_10HALF;
2837         if (mask & ADVERTISED_10baseT_Full)
2838                 all_mask |= ADVERTISE_10FULL;
2839         if (mask & ADVERTISED_100baseT_Half)
2840                 all_mask |= ADVERTISE_100HALF;
2841         if (mask & ADVERTISED_100baseT_Full)
2842                 all_mask |= ADVERTISE_100FULL;
2843
2844         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2845                 return 0;
2846
2847         if ((adv_reg & all_mask) != all_mask)
2848                 return 0;
2849         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2850                 u32 tg3_ctrl;
2851
2852                 all_mask = 0;
2853                 if (mask & ADVERTISED_1000baseT_Half)
2854                         all_mask |= ADVERTISE_1000HALF;
2855                 if (mask & ADVERTISED_1000baseT_Full)
2856                         all_mask |= ADVERTISE_1000FULL;
2857
2858                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2859                         return 0;
2860
2861                 if ((tg3_ctrl & all_mask) != all_mask)
2862                         return 0;
2863         }
2864         return 1;
2865 }
2866
2867 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2868 {
2869         u32 curadv, reqadv;
2870
2871         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2872                 return 1;
2873
2874         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2875         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2876
2877         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2878                 if (curadv != reqadv)
2879                         return 0;
2880
2881                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2882                         tg3_readphy(tp, MII_LPA, rmtadv);
2883         } else {
2884                 /* Reprogram the advertisement register, even if it
2885                  * does not affect the current link.  If the link
2886                  * gets renegotiated in the future, we can save an
2887                  * additional renegotiation cycle by advertising
2888                  * it correctly in the first place.
2889                  */
2890                 if (curadv != reqadv) {
2891                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2892                                      ADVERTISE_PAUSE_ASYM);
2893                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2894                 }
2895         }
2896
2897         return 1;
2898 }
2899
2900 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2901 {
2902         int current_link_up;
2903         u32 bmsr, dummy;
2904         u32 lcl_adv, rmt_adv;
2905         u16 current_speed;
2906         u8 current_duplex;
2907         int i, err;
2908
2909         tw32(MAC_EVENT, 0);
2910
2911         tw32_f(MAC_STATUS,
2912              (MAC_STATUS_SYNC_CHANGED |
2913               MAC_STATUS_CFG_CHANGED |
2914               MAC_STATUS_MI_COMPLETION |
2915               MAC_STATUS_LNKSTATE_CHANGED));
2916         udelay(40);
2917
2918         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2919                 tw32_f(MAC_MI_MODE,
2920                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2921                 udelay(80);
2922         }
2923
2924         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2925
2926         /* Some third-party PHYs need to be reset on link going
2927          * down.
2928          */
2929         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2930              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2931              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2932             netif_carrier_ok(tp->dev)) {
2933                 tg3_readphy(tp, MII_BMSR, &bmsr);
2934                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2935                     !(bmsr & BMSR_LSTATUS))
2936                         force_reset = 1;
2937         }
2938         if (force_reset)
2939                 tg3_phy_reset(tp);
2940
2941         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2942                 tg3_readphy(tp, MII_BMSR, &bmsr);
2943                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2944                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2945                         bmsr = 0;
2946
2947                 if (!(bmsr & BMSR_LSTATUS)) {
2948                         err = tg3_init_5401phy_dsp(tp);
2949                         if (err)
2950                                 return err;
2951
2952                         tg3_readphy(tp, MII_BMSR, &bmsr);
2953                         for (i = 0; i < 1000; i++) {
2954                                 udelay(10);
2955                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2956                                     (bmsr & BMSR_LSTATUS)) {
2957                                         udelay(40);
2958                                         break;
2959                                 }
2960                         }
2961
2962                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2963                             !(bmsr & BMSR_LSTATUS) &&
2964                             tp->link_config.active_speed == SPEED_1000) {
2965                                 err = tg3_phy_reset(tp);
2966                                 if (!err)
2967                                         err = tg3_init_5401phy_dsp(tp);
2968                                 if (err)
2969                                         return err;
2970                         }
2971                 }
2972         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2973                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2974                 /* 5701 {A0,B0} CRC bug workaround */
2975                 tg3_writephy(tp, 0x15, 0x0a75);
2976                 tg3_writephy(tp, 0x1c, 0x8c68);
2977                 tg3_writephy(tp, 0x1c, 0x8d68);
2978                 tg3_writephy(tp, 0x1c, 0x8c68);
2979         }
2980
2981         /* Clear pending interrupts... */
2982         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2983         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2984
2985         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2986                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2987         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2988                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2989
2990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2992                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2993                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2994                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2995                 else
2996                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2997         }
2998
2999         current_link_up = 0;
3000         current_speed = SPEED_INVALID;
3001         current_duplex = DUPLEX_INVALID;
3002
3003         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3004                 u32 val;
3005
3006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3007                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3008                 if (!(val & (1 << 10))) {
3009                         val |= (1 << 10);
3010                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3011                         goto relink;
3012                 }
3013         }
3014
3015         bmsr = 0;
3016         for (i = 0; i < 100; i++) {
3017                 tg3_readphy(tp, MII_BMSR, &bmsr);
3018                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3019                     (bmsr & BMSR_LSTATUS))
3020                         break;
3021                 udelay(40);
3022         }
3023
3024         if (bmsr & BMSR_LSTATUS) {
3025                 u32 aux_stat, bmcr;
3026
3027                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3028                 for (i = 0; i < 2000; i++) {
3029                         udelay(10);
3030                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3031                             aux_stat)
3032                                 break;
3033                 }
3034
3035                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3036                                              &current_speed,
3037                                              &current_duplex);
3038
3039                 bmcr = 0;
3040                 for (i = 0; i < 200; i++) {
3041                         tg3_readphy(tp, MII_BMCR, &bmcr);
3042                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3043                                 continue;
3044                         if (bmcr && bmcr != 0x7fff)
3045                                 break;
3046                         udelay(10);
3047                 }
3048
3049                 lcl_adv = 0;
3050                 rmt_adv = 0;
3051
3052                 tp->link_config.active_speed = current_speed;
3053                 tp->link_config.active_duplex = current_duplex;
3054
3055                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3056                         if ((bmcr & BMCR_ANENABLE) &&
3057                             tg3_copper_is_advertising_all(tp,
3058                                                 tp->link_config.advertising)) {
3059                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3060                                                                   &rmt_adv))
3061                                         current_link_up = 1;
3062                         }
3063                 } else {
3064                         if (!(bmcr & BMCR_ANENABLE) &&
3065                             tp->link_config.speed == current_speed &&
3066                             tp->link_config.duplex == current_duplex &&
3067                             tp->link_config.flowctrl ==
3068                             tp->link_config.active_flowctrl) {
3069                                 current_link_up = 1;
3070                         }
3071                 }
3072
3073                 if (current_link_up == 1 &&
3074                     tp->link_config.active_duplex == DUPLEX_FULL)
3075                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3076         }
3077
3078 relink:
3079         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3080                 u32 tmp;
3081
3082                 tg3_phy_copper_begin(tp);
3083
3084                 tg3_readphy(tp, MII_BMSR, &tmp);
3085                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3086                     (tmp & BMSR_LSTATUS))
3087                         current_link_up = 1;
3088         }
3089
3090         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3091         if (current_link_up == 1) {
3092                 if (tp->link_config.active_speed == SPEED_100 ||
3093                     tp->link_config.active_speed == SPEED_10)
3094                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3095                 else
3096                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3097         } else
3098                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3099
3100         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3101         if (tp->link_config.active_duplex == DUPLEX_HALF)
3102                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3103
3104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3105                 if (current_link_up == 1 &&
3106                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3107                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3108                 else
3109                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3110         }
3111
3112         /* ??? Without this setting Netgear GA302T PHY does not
3113          * ??? send/receive packets...
3114          */
3115         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3116             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3117                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3118                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3119                 udelay(80);
3120         }
3121
3122         tw32_f(MAC_MODE, tp->mac_mode);
3123         udelay(40);
3124
3125         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3126                 /* Polled via timer. */
3127                 tw32_f(MAC_EVENT, 0);
3128         } else {
3129                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3130         }
3131         udelay(40);
3132
3133         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3134             current_link_up == 1 &&
3135             tp->link_config.active_speed == SPEED_1000 &&
3136             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3137              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3138                 udelay(120);
3139                 tw32_f(MAC_STATUS,
3140                      (MAC_STATUS_SYNC_CHANGED |
3141                       MAC_STATUS_CFG_CHANGED));
3142                 udelay(40);
3143                 tg3_write_mem(tp,
3144                               NIC_SRAM_FIRMWARE_MBOX,
3145                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3146         }
3147